Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         /**
  75          * find_pll() - Find the best values for the PLL
  76          * @limit: limits for the PLL
  77          * @crtc: current CRTC
  78          * @target: target frequency in kHz
  79          * @refclk: reference clock frequency in kHz
  80          * @match_clock: if provided, @best_clock P divider must
  81          *               match the P divider from @match_clock
  82          *               used for LVDS downclocking
  83          * @best_clock: best PLL values found
  84          *
  85          * Returns true on success, false on failure.
  86          */
  87         bool (*find_pll)(const intel_limit_t *limit,
  88                          struct drm_crtc *crtc,
  89                          int target, int refclk,
  90                          intel_clock_t *match_clock,
  91                          intel_clock_t *best_clock);
  92 };
  93
  94 /* FDI */
  95 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  96
  97 int
  98 intel_pch_rawclk(struct drm_device *dev)
  99 {
 100         struct drm_i915_private *dev_priv = dev->dev_private;
 101
 102         WARN_ON(!HAS_PCH_SPLIT(dev));
 103
 104         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
 105 }
 106
 107 static bool
 108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 109                     int target, int refclk, intel_clock_t *match_clock,
 110                     intel_clock_t *best_clock);
 111 static bool
 112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static bool
 117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 118                       int target, int refclk, intel_clock_t *match_clock,
 119                       intel_clock_t *best_clock);
 120 static bool
 121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 122                            int target, int refclk, intel_clock_t *match_clock,
 123                            intel_clock_t *best_clock);
 124
 125 static bool
 126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 127                         int target, int refclk, intel_clock_t *match_clock,
 128                         intel_clock_t *best_clock);
 129
 130 static inline u32 /* units of 100MHz */
 131 intel_fdi_link_freq(struct drm_device *dev)
 132 {
 133         if (IS_GEN5(dev)) {
 134                 struct drm_i915_private *dev_priv = dev->dev_private;
 135                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 136         } else
 137                 return 27;
 138 }
 139
 140 static const intel_limit_t intel_limits_i8xx_dvo = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 2, .max = 33 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 4, .p2_fast = 2 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i8xx_lvds = {
 155         .dot = { .min = 25000, .max = 350000 },
 156         .vco = { .min = 930000, .max = 1400000 },
 157         .n = { .min = 3, .max = 16 },
 158         .m = { .min = 96, .max = 140 },
 159         .m1 = { .min = 18, .max = 26 },
 160         .m2 = { .min = 6, .max = 16 },
 161         .p = { .min = 4, .max = 128 },
 162         .p1 = { .min = 1, .max = 6 },
 163         .p2 = { .dot_limit = 165000,
 164                 .p2_slow = 14, .p2_fast = 7 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_sdvo = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 8, .max = 18 },
 174         .m2 = { .min = 3, .max = 7 },
 175         .p = { .min = 5, .max = 80 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 200000,
 178                 .p2_slow = 10, .p2_fast = 5 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182 static const intel_limit_t intel_limits_i9xx_lvds = {
 183         .dot = { .min = 20000, .max = 400000 },
 184         .vco = { .min = 1400000, .max = 2800000 },
 185         .n = { .min = 1, .max = 6 },
 186         .m = { .min = 70, .max = 120 },
 187         .m1 = { .min = 8, .max = 18 },
 188         .m2 = { .min = 3, .max = 7 },
 189         .p = { .min = 7, .max = 98 },
 190         .p1 = { .min = 1, .max = 8 },
 191         .p2 = { .dot_limit = 112000,
 192                 .p2_slow = 14, .p2_fast = 7 },
 193         .find_pll = intel_find_best_PLL,
 194 };
 195
 196
 197 static const intel_limit_t intel_limits_g4x_sdvo = {
 198         .dot = { .min = 25000, .max = 270000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 17, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 10, .max = 30 },
 205         .p1 = { .min = 1, .max = 3},
 206         .p2 = { .dot_limit = 270000,
 207                 .p2_slow = 10,
 208                 .p2_fast = 10
 209         },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_hdmi = {
 214         .dot = { .min = 22000, .max = 400000 },
 215         .vco = { .min = 1750000, .max = 3500000},
 216         .n = { .min = 1, .max = 4 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 16, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 5, .max = 80 },
 221         .p1 = { .min = 1, .max = 8},
 222         .p2 = { .dot_limit = 165000,
 223                 .p2_slow = 10, .p2_fast = 5 },
 224         .find_pll = intel_g4x_find_best_PLL,
 225 };
 226
 227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 228         .dot = { .min = 20000, .max = 115000 },
 229         .vco = { .min = 1750000, .max = 3500000 },
 230         .n = { .min = 1, .max = 3 },
 231         .m = { .min = 104, .max = 138 },
 232         .m1 = { .min = 17, .max = 23 },
 233         .m2 = { .min = 5, .max = 11 },
 234         .p = { .min = 28, .max = 112 },
 235         .p1 = { .min = 2, .max = 8 },
 236         .p2 = { .dot_limit = 0,
 237                 .p2_slow = 14, .p2_fast = 14
 238         },
 239         .find_pll = intel_g4x_find_best_PLL,
 240 };
 241
 242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 243         .dot = { .min = 80000, .max = 224000 },
 244         .vco = { .min = 1750000, .max = 3500000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 104, .max = 138 },
 247         .m1 = { .min = 17, .max = 23 },
 248         .m2 = { .min = 5, .max = 11 },
 249         .p = { .min = 14, .max = 42 },
 250         .p1 = { .min = 2, .max = 6 },
 251         .p2 = { .dot_limit = 0,
 252                 .p2_slow = 7, .p2_fast = 7
 253         },
 254         .find_pll = intel_g4x_find_best_PLL,
 255 };
 256
 257 static const intel_limit_t intel_limits_g4x_display_port = {
 258         .dot = { .min = 161670, .max = 227000 },
 259         .vco = { .min = 1750000, .max = 3500000},
 260         .n = { .min = 1, .max = 2 },
 261         .m = { .min = 97, .max = 108 },
 262         .m1 = { .min = 0x10, .max = 0x12 },
 263         .m2 = { .min = 0x05, .max = 0x06 },
 264         .p = { .min = 10, .max = 20 },
 265         .p1 = { .min = 1, .max = 2},
 266         .p2 = { .dot_limit = 0,
 267                 .p2_slow = 10, .p2_fast = 10 },
 268         .find_pll = intel_find_pll_g4x_dp,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_sdvo = {
 272         .dot = { .min = 20000, .max = 400000},
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         /* Pineview's Ncounter is a ring counter */
 275         .n = { .min = 3, .max = 6 },
 276         .m = { .min = 2, .max = 256 },
 277         /* Pineview only has one combined m divider, which we treat as m2. */
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 5, .max = 80 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 200000,
 283                 .p2_slow = 10, .p2_fast = 5 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 static const intel_limit_t intel_limits_pineview_lvds = {
 288         .dot = { .min = 20000, .max = 400000 },
 289         .vco = { .min = 1700000, .max = 3500000 },
 290         .n = { .min = 3, .max = 6 },
 291         .m = { .min = 2, .max = 256 },
 292         .m1 = { .min = 0, .max = 0 },
 293         .m2 = { .min = 0, .max = 254 },
 294         .p = { .min = 7, .max = 112 },
 295         .p1 = { .min = 1, .max = 8 },
 296         .p2 = { .dot_limit = 112000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298         .find_pll = intel_find_best_PLL,
 299 };
 300
 301 /* Ironlake / Sandybridge
 302  *
 303  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 304  * the range value for them is (actual_value - 2).
 305  */
 306 static const intel_limit_t intel_limits_ironlake_dac = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 5 },
 310         .m = { .min = 79, .max = 127 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 5, .max = 80 },
 314         .p1 = { .min = 1, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 10, .p2_fast = 5 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 118 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 28, .max = 112 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 14, .p2_fast = 14 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 335         .dot = { .min = 25000, .max = 350000 },
 336         .vco = { .min = 1760000, .max = 3510000 },
 337         .n = { .min = 1, .max = 3 },
 338         .m = { .min = 79, .max = 127 },
 339         .m1 = { .min = 12, .max = 22 },
 340         .m2 = { .min = 5, .max = 9 },
 341         .p = { .min = 14, .max = 56 },
 342         .p1 = { .min = 2, .max = 8 },
 343         .p2 = { .dot_limit = 225000,
 344                 .p2_slow = 7, .p2_fast = 7 },
 345         .find_pll = intel_g4x_find_best_PLL,
 346 };
 347
 348 /* LVDS 100mhz refclk limits. */
 349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 2 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 28, .max = 112 },
 357         .p1 = { .min = 2, .max = 8 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 14, .p2_fast = 14 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000 },
 366         .n = { .min = 1, .max = 3 },
 367         .m = { .min = 79, .max = 126 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 14, .max = 42 },
 371         .p1 = { .min = 2, .max = 6 },
 372         .p2 = { .dot_limit = 225000,
 373                 .p2_slow = 7, .p2_fast = 7 },
 374         .find_pll = intel_g4x_find_best_PLL,
 375 };
 376
 377 static const intel_limit_t intel_limits_ironlake_display_port = {
 378         .dot = { .min = 25000, .max = 350000 },
 379         .vco = { .min = 1760000, .max = 3510000},
 380         .n = { .min = 1, .max = 2 },
 381         .m = { .min = 81, .max = 90 },
 382         .m1 = { .min = 12, .max = 22 },
 383         .m2 = { .min = 5, .max = 9 },
 384         .p = { .min = 10, .max = 20 },
 385         .p1 = { .min = 1, .max = 2},
 386         .p2 = { .dot_limit = 0,
 387                 .p2_slow = 10, .p2_fast = 10 },
 388         .find_pll = intel_find_pll_ironlake_dp,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_dac = {
 392         .dot = { .min = 25000, .max = 270000 },
 393         .vco = { .min = 4000000, .max = 6000000 },
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 22, .max = 450 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_hdmi = {
 406         .dot = { .min = 20000, .max = 165000 },
 407         .vco = { .min = 4000000, .max = 5994000},
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 60, .max = 300 }, /* guess */
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 static const intel_limit_t intel_limits_vlv_dp = {
 420         .dot = { .min = 25000, .max = 270000 },
 421         .vco = { .min = 4000000, .max = 6000000 },
 422         .n = { .min = 1, .max = 7 },
 423         .m = { .min = 22, .max = 450 },
 424         .m1 = { .min = 2, .max = 3 },
 425         .m2 = { .min = 11, .max = 156 },
 426         .p = { .min = 10, .max = 30 },
 427         .p1 = { .min = 2, .max = 3 },
 428         .p2 = { .dot_limit = 270000,
 429                 .p2_slow = 2, .p2_fast = 20 },
 430         .find_pll = intel_vlv_find_best_pll,
 431 };
 432
 433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 434 {
 435         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 436
 437         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 438                 DRM_ERROR("DPIO idle wait timed out\n");
 439                 return 0;
 440         }
 441
 442         I915_WRITE(DPIO_REG, reg);
 443         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 444                    DPIO_BYTE);
 445         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 446                 DRM_ERROR("DPIO read wait timed out\n");
 447                 return 0;
 448         }
 449
 450         return I915_READ(DPIO_DATA);
 451 }
 452
 453 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 454                              u32 val)
 455 {
 456         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 457
 458         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 459                 DRM_ERROR("DPIO idle wait timed out\n");
 460                 return;
 461         }
 462
 463         I915_WRITE(DPIO_DATA, val);
 464         I915_WRITE(DPIO_REG, reg);
 465         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 466                    DPIO_BYTE);
 467         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 468                 DRM_ERROR("DPIO write wait timed out\n");
 469 }
 470
 471 static void vlv_init_dpio(struct drm_device *dev)
 472 {
 473         struct drm_i915_private *dev_priv = dev->dev_private;
 474
 475         /* Reset the DPIO config */
 476         I915_WRITE(DPIO_CTL, 0);
 477         POSTING_READ(DPIO_CTL);
 478         I915_WRITE(DPIO_CTL, 1);
 479         POSTING_READ(DPIO_CTL);
 480 }
 481
 482 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 483                                                 int refclk)
 484 {
 485         struct drm_device *dev = crtc->dev;
 486         const intel_limit_t *limit;
 487
 488         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 489                 if (intel_is_dual_link_lvds(dev)) {
 490                         /* LVDS dual channel */
 491                         if (refclk == 100000)
 492                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 493                         else
 494                                 limit = &intel_limits_ironlake_dual_lvds;
 495                 } else {
 496                         if (refclk == 100000)
 497                                 limit = &intel_limits_ironlake_single_lvds_100m;
 498                         else
 499                                 limit = &intel_limits_ironlake_single_lvds;
 500                 }
 501         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 502                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 503                 limit = &intel_limits_ironlake_display_port;
 504         else
 505                 limit = &intel_limits_ironlake_dac;
 506
 507         return limit;
 508 }
 509
 510 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 511 {
 512         struct drm_device *dev = crtc->dev;
 513         const intel_limit_t *limit;
 514
 515         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 516                 if (intel_is_dual_link_lvds(dev))
 517                         /* LVDS with dual channel */
 518                         limit = &intel_limits_g4x_dual_channel_lvds;
 519                 else
 520                         /* LVDS with dual channel */
 521                         limit = &intel_limits_g4x_single_channel_lvds;
 522         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 523                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 524                 limit = &intel_limits_g4x_hdmi;
 525         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 526                 limit = &intel_limits_g4x_sdvo;
 527         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 528                 limit = &intel_limits_g4x_display_port;
 529         } else /* The option is for other outputs */
 530                 limit = &intel_limits_i9xx_sdvo;
 531
 532         return limit;
 533 }
 534
 535 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 536 {
 537         struct drm_device *dev = crtc->dev;
 538         const intel_limit_t *limit;
 539
 540         if (HAS_PCH_SPLIT(dev))
 541                 limit = intel_ironlake_limit(crtc, refclk);
 542         else if (IS_G4X(dev)) {
 543                 limit = intel_g4x_limit(crtc);
 544         } else if (IS_PINEVIEW(dev)) {
 545                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 546                         limit = &intel_limits_pineview_lvds;
 547                 else
 548                         limit = &intel_limits_pineview_sdvo;
 549         } else if (IS_VALLEYVIEW(dev)) {
 550                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 551                         limit = &intel_limits_vlv_dac;
 552                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 553                         limit = &intel_limits_vlv_hdmi;
 554                 else
 555                         limit = &intel_limits_vlv_dp;
 556         } else if (!IS_GEN2(dev)) {
 557                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 558                         limit = &intel_limits_i9xx_lvds;
 559                 else
 560                         limit = &intel_limits_i9xx_sdvo;
 561         } else {
 562                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 563                         limit = &intel_limits_i8xx_lvds;
 564                 else
 565                         limit = &intel_limits_i8xx_dvo;
 566         }
 567         return limit;
 568 }
 569
 570 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 571 static void pineview_clock(int refclk, intel_clock_t *clock)
 572 {
 573         clock->m = clock->m2 + 2;
 574         clock->p = clock->p1 * clock->p2;
 575         clock->vco = refclk * clock->m / clock->n;
 576         clock->dot = clock->vco / clock->p;
 577 }
 578
 579 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 580 {
 581         if (IS_PINEVIEW(dev)) {
 582                 pineview_clock(refclk, clock);
 583                 return;
 584         }
 585         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 586         clock->p = clock->p1 * clock->p2;
 587         clock->vco = refclk * clock->m / (clock->n + 2);
 588         clock->dot = clock->vco / clock->p;
 589 }
 590
 591 /**
 592  * Returns whether any output on the specified pipe is of the specified type
 593  */
 594 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 595 {
 596         struct drm_device *dev = crtc->dev;
 597         struct intel_encoder *encoder;
 598
 599         for_each_encoder_on_crtc(dev, crtc, encoder)
 600                 if (encoder->type == type)
 601                         return true;
 602
 603         return false;
 604 }
 605
 606 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 607 /**
 608  * Returns whether the given set of divisors are valid for a given refclk with
 609  * the given connectors.
 610  */
 611
 612 static bool intel_PLL_is_valid(struct drm_device *dev,
 613                                const intel_limit_t *limit,
 614                                const intel_clock_t *clock)
 615 {
 616         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 617                 INTELPllInvalid("p1 out of range\n");
 618         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 619                 INTELPllInvalid("p out of range\n");
 620         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 621                 INTELPllInvalid("m2 out of range\n");
 622         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 623                 INTELPllInvalid("m1 out of range\n");
 624         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 625                 INTELPllInvalid("m1 <= m2\n");
 626         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 627                 INTELPllInvalid("m out of range\n");
 628         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 629                 INTELPllInvalid("n out of range\n");
 630         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 631                 INTELPllInvalid("vco out of range\n");
 632         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 633          * connector, etc., rather than just a single range.
 634          */
 635         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 636                 INTELPllInvalid("dot out of range\n");
 637
 638         return true;
 639 }
 640
 641 static bool
 642 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 643                     int target, int refclk, intel_clock_t *match_clock,
 644                     intel_clock_t *best_clock)
 645
 646 {
 647         struct drm_device *dev = crtc->dev;
 648         intel_clock_t clock;
 649         int err = target;
 650
 651         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 652                 /*
 653                  * For LVDS just rely on its current settings for dual-channel.
 654                  * We haven't figured out how to reliably set up different
 655                  * single/dual channel state, if we even can.
 656                  */
 657                 if (intel_is_dual_link_lvds(dev))
 658                         clock.p2 = limit->p2.p2_fast;
 659                 else
 660                         clock.p2 = limit->p2.p2_slow;
 661         } else {
 662                 if (target < limit->p2.dot_limit)
 663                         clock.p2 = limit->p2.p2_slow;
 664                 else
 665                         clock.p2 = limit->p2.p2_fast;
 666         }
 667
 668         memset(best_clock, 0, sizeof(*best_clock));
 669
 670         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 671              clock.m1++) {
 672                 for (clock.m2 = limit->m2.min;
 673                      clock.m2 <= limit->m2.max; clock.m2++) {
 674                         /* m1 is always 0 in Pineview */
 675                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 676                                 break;
 677                         for (clock.n = limit->n.min;
 678                              clock.n <= limit->n.max; clock.n++) {
 679                                 for (clock.p1 = limit->p1.min;
 680                                         clock.p1 <= limit->p1.max; clock.p1++) {
 681                                         int this_err;
 682
 683                                         intel_clock(dev, refclk, &clock);
 684                                         if (!intel_PLL_is_valid(dev, limit,
 685                                                                 &clock))
 686                                                 continue;
 687                                         if (match_clock &&
 688                                             clock.p != match_clock->p)
 689                                                 continue;
 690
 691                                         this_err = abs(clock.dot - target);
 692                                         if (this_err < err) {
 693                                                 *best_clock = clock;
 694                                                 err = this_err;
 695                                         }
 696                                 }
 697                         }
 698                 }
 699         }
 700
 701         return (err != target);
 702 }
 703
 704 static bool
 705 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 706                         int target, int refclk, intel_clock_t *match_clock,
 707                         intel_clock_t *best_clock)
 708 {
 709         struct drm_device *dev = crtc->dev;
 710         intel_clock_t clock;
 711         int max_n;
 712         bool found;
 713         /* approximately equals target * 0.00585 */
 714         int err_most = (target >> 8) + (target >> 9);
 715         found = false;
 716
 717         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 718                 int lvds_reg;
 719
 720                 if (HAS_PCH_SPLIT(dev))
 721                         lvds_reg = PCH_LVDS;
 722                 else
 723                         lvds_reg = LVDS;
 724                 if (intel_is_dual_link_lvds(dev))
 725                         clock.p2 = limit->p2.p2_fast;
 726                 else
 727                         clock.p2 = limit->p2.p2_slow;
 728         } else {
 729                 if (target < limit->p2.dot_limit)
 730                         clock.p2 = limit->p2.p2_slow;
 731                 else
 732                         clock.p2 = limit->p2.p2_fast;
 733         }
 734
 735         memset(best_clock, 0, sizeof(*best_clock));
 736         max_n = limit->n.max;
 737         /* based on hardware requirement, prefer smaller n to precision */
 738         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 739                 /* based on hardware requirement, prefere larger m1,m2 */
 740                 for (clock.m1 = limit->m1.max;
 741                      clock.m1 >= limit->m1.min; clock.m1--) {
 742                         for (clock.m2 = limit->m2.max;
 743                              clock.m2 >= limit->m2.min; clock.m2--) {
 744                                 for (clock.p1 = limit->p1.max;
 745                                      clock.p1 >= limit->p1.min; clock.p1--) {
 746                                         int this_err;
 747
 748                                         intel_clock(dev, refclk, &clock);
 749                                         if (!intel_PLL_is_valid(dev, limit,
 750                                                                 &clock))
 751                                                 continue;
 752                                         if (match_clock &&
 753                                             clock.p != match_clock->p)
 754                                                 continue;
 755
 756                                         this_err = abs(clock.dot - target);
 757                                         if (this_err < err_most) {
 758                                                 *best_clock = clock;
 759                                                 err_most = this_err;
 760                                                 max_n = clock.n;
 761                                                 found = true;
 762                                         }
 763                                 }
 764                         }
 765                 }
 766         }
 767         return found;
 768 }
 769
 770 static bool
 771 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 772                            int target, int refclk, intel_clock_t *match_clock,
 773                            intel_clock_t *best_clock)
 774 {
 775         struct drm_device *dev = crtc->dev;
 776         intel_clock_t clock;
 777
 778         if (target < 200000) {
 779                 clock.n = 1;
 780                 clock.p1 = 2;
 781                 clock.p2 = 10;
 782                 clock.m1 = 12;
 783                 clock.m2 = 9;
 784         } else {
 785                 clock.n = 2;
 786                 clock.p1 = 1;
 787                 clock.p2 = 10;
 788                 clock.m1 = 14;
 789                 clock.m2 = 8;
 790         }
 791         intel_clock(dev, refclk, &clock);
 792         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 793         return true;
 794 }
 795
 796 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 797 static bool
 798 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 799                       int target, int refclk, intel_clock_t *match_clock,
 800                       intel_clock_t *best_clock)
 801 {
 802         intel_clock_t clock;
 803         if (target < 200000) {
 804                 clock.p1 = 2;
 805                 clock.p2 = 10;
 806                 clock.n = 2;
 807                 clock.m1 = 23;
 808                 clock.m2 = 8;
 809         } else {
 810                 clock.p1 = 1;
 811                 clock.p2 = 10;
 812                 clock.n = 1;
 813                 clock.m1 = 14;
 814                 clock.m2 = 2;
 815         }
 816         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 817         clock.p = (clock.p1 * clock.p2);
 818         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 819         clock.vco = 0;
 820         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 821         return true;
 822 }
 823 static bool
 824 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 825                         int target, int refclk, intel_clock_t *match_clock,
 826                         intel_clock_t *best_clock)
 827 {
 828         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 829         u32 m, n, fastclk;
 830         u32 updrate, minupdate, fracbits, p;
 831         unsigned long bestppm, ppm, absppm;
 832         int dotclk, flag;
 833
 834         flag = 0;
 835         dotclk = target * 1000;
 836         bestppm = 1000000;
 837         ppm = absppm = 0;
 838         fastclk = dotclk / (2*100);
 839         updrate = 0;
 840         minupdate = 19200;
 841         fracbits = 1;
 842         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 843         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 844
 845         /* based on hardware requirement, prefer smaller n to precision */
 846         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 847                 updrate = refclk / n;
 848                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 849                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 850                                 if (p2 > 10)
 851                                         p2 = p2 - 1;
 852                                 p = p1 * p2;
 853                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 854                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 855                                         m2 = (((2*(fastclk * p * n / m1 )) +
 856                                                refclk) / (2*refclk));
 857                                         m = m1 * m2;
 858                                         vco = updrate * m;
 859                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 860                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 861                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 862                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 863                                                         bestppm = 0;
 864                                                         flag = 1;
 865                                                 }
 866                                                 if (absppm < bestppm - 10) {
 867                                                         bestppm = absppm;
 868                                                         flag = 1;
 869                                                 }
 870                                                 if (flag) {
 871                                                         bestn = n;
 872                                                         bestm1 = m1;
 873                                                         bestm2 = m2;
 874                                                         bestp1 = p1;
 875                                                         bestp2 = p2;
 876                                                         flag = 0;
 877                                                 }
 878                                         }
 879                                 }
 880                         }
 881                 }
 882         }
 883         best_clock->n = bestn;
 884         best_clock->m1 = bestm1;
 885         best_clock->m2 = bestm2;
 886         best_clock->p1 = bestp1;
 887         best_clock->p2 = bestp2;
 888
 889         return true;
 890 }
 891
 892 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 893                                              enum pipe pipe)
 894 {
 895         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 897
 898         return intel_crtc->cpu_transcoder;
 899 }
 900
 901 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 902 {
 903         struct drm_i915_private *dev_priv = dev->dev_private;
 904         u32 frame, frame_reg = PIPEFRAME(pipe);
 905
 906         frame = I915_READ(frame_reg);
 907
 908         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 909                 DRM_DEBUG_KMS("vblank wait timed out\n");
 910 }
 911
 912 /**
 913  * intel_wait_for_vblank - wait for vblank on a given pipe
 914  * @dev: drm device
 915  * @pipe: pipe to wait for
 916  *
 917  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 918  * mode setting code.
 919  */
 920 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 921 {
 922         struct drm_i915_private *dev_priv = dev->dev_private;
 923         int pipestat_reg = PIPESTAT(pipe);
 924
 925         if (INTEL_INFO(dev)->gen >= 5) {
 926                 ironlake_wait_for_vblank(dev, pipe);
 927                 return;
 928         }
 929
 930         /* Clear existing vblank status. Note this will clear any other
 931          * sticky status fields as well.
 932          *
 933          * This races with i915_driver_irq_handler() with the result
 934          * that either function could miss a vblank event.  Here it is not
 935          * fatal, as we will either wait upon the next vblank interrupt or
 936          * timeout.  Generally speaking intel_wait_for_vblank() is only
 937          * called during modeset at which time the GPU should be idle and
 938          * should *not* be performing page flips and thus not waiting on
 939          * vblanks...
 940          * Currently, the result of us stealing a vblank from the irq
 941          * handler is that a single frame will be skipped during swapbuffers.
 942          */
 943         I915_WRITE(pipestat_reg,
 944                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 945
 946         /* Wait for vblank interrupt bit to set */
 947         if (wait_for(I915_READ(pipestat_reg) &
 948                      PIPE_VBLANK_INTERRUPT_STATUS,
 949                      50))
 950                 DRM_DEBUG_KMS("vblank wait timed out\n");
 951 }
 952
 953 /*
 954  * intel_wait_for_pipe_off - wait for pipe to turn off
 955  * @dev: drm device
 956  * @pipe: pipe to wait for
 957  *
 958  * After disabling a pipe, we can't wait for vblank in the usual way,
 959  * spinning on the vblank interrupt status bit, since we won't actually
 960  * see an interrupt when the pipe is disabled.
 961  *
 962  * On Gen4 and above:
 963  *   wait for the pipe register state bit to turn off
 964  *
 965  * Otherwise:
 966  *   wait for the display line value to settle (it usually
 967  *   ends up stopping at the start of the next frame).
 968  *
 969  */
 970 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 971 {
 972         struct drm_i915_private *dev_priv = dev->dev_private;
 973         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 974                                                                       pipe);
 975
 976         if (INTEL_INFO(dev)->gen >= 4) {
 977                 int reg = PIPECONF(cpu_transcoder);
 978
 979                 /* Wait for the Pipe State to go off */
 980                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 981                              100))
 982                         WARN(1, "pipe_off wait timed out\n");
 983         } else {
 984                 u32 last_line, line_mask;
 985                 int reg = PIPEDSL(pipe);
 986                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 987
 988                 if (IS_GEN2(dev))
 989                         line_mask = DSL_LINEMASK_GEN2;
 990                 else
 991                         line_mask = DSL_LINEMASK_GEN3;
 992
 993                 /* Wait for the display line to settle */
 994                 do {
 995                         last_line = I915_READ(reg) & line_mask;
 996                         mdelay(5);
 997                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 998                          time_after(timeout, jiffies));
 999                 if (time_after(jiffies, timeout))
1000                         WARN(1, "pipe_off wait timed out\n");
1001         }
1002 }
1003
1004 /*
1005  * ibx_digital_port_connected - is the specified port connected?
1006  * @dev_priv: i915 private structure
1007  * @port: the port to test
1008  *
1009  * Returns true if @port is connected, false otherwise.
1010  */
1011 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1012                                 struct intel_digital_port *port)
1013 {
1014         u32 bit;
1015
1016         if (HAS_PCH_IBX(dev_priv->dev)) {
1017                 switch(port->port) {
1018                 case PORT_B:
1019                         bit = SDE_PORTB_HOTPLUG;
1020                         break;
1021                 case PORT_C:
1022                         bit = SDE_PORTC_HOTPLUG;
1023                         break;
1024                 case PORT_D:
1025                         bit = SDE_PORTD_HOTPLUG;
1026                         break;
1027                 default:
1028                         return true;
1029                 }
1030         } else {
1031                 switch(port->port) {
1032                 case PORT_B:
1033                         bit = SDE_PORTB_HOTPLUG_CPT;
1034                         break;
1035                 case PORT_C:
1036                         bit = SDE_PORTC_HOTPLUG_CPT;
1037                         break;
1038                 case PORT_D:
1039                         bit = SDE_PORTD_HOTPLUG_CPT;
1040                         break;
1041                 default:
1042                         return true;
1043                 }
1044         }
1045
1046         return I915_READ(SDEISR) & bit;
1047 }
1048
1049 static const char *state_string(bool enabled)
1050 {
1051         return enabled ? "on" : "off";
1052 }
1053
1054 /* Only for pre-ILK configs */
1055 static void assert_pll(struct drm_i915_private *dev_priv,
1056                        enum pipe pipe, bool state)
1057 {
1058         int reg;
1059         u32 val;
1060         bool cur_state;
1061
1062         reg = DPLL(pipe);
1063         val = I915_READ(reg);
1064         cur_state = !!(val & DPLL_VCO_ENABLE);
1065         WARN(cur_state != state,
1066              "PLL state assertion failure (expected %s, current %s)\n",
1067              state_string(state), state_string(cur_state));
1068 }
1069 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1070 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1071
1072 /* For ILK+ */
1073 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1074                            struct intel_pch_pll *pll,
1075                            struct intel_crtc *crtc,
1076                            bool state)
1077 {
1078         u32 val;
1079         bool cur_state;
1080
1081         if (HAS_PCH_LPT(dev_priv->dev)) {
1082                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1083                 return;
1084         }
1085
1086         if (WARN (!pll,
1087                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1088                 return;
1089
1090         val = I915_READ(pll->pll_reg);
1091         cur_state = !!(val & DPLL_VCO_ENABLE);
1092         WARN(cur_state != state,
1093              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1094              pll->pll_reg, state_string(state), state_string(cur_state), val);
1095
1096         /* Make sure the selected PLL is correctly attached to the transcoder */
1097         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1098                 u32 pch_dpll;
1099
1100                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1101                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1102                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1103                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1104                           cur_state, crtc->pipe, pch_dpll)) {
1105                         cur_state = !!(val >> (4*crtc->pipe + 3));
1106                         WARN(cur_state != state,
1107                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1108                              pll->pll_reg == _PCH_DPLL_B,
1109                              state_string(state),
1110                              crtc->pipe,
1111                              val);
1112                 }
1113         }
1114 }
1115 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1116 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119                           enum pipe pipe, bool state)
1120 {
1121         int reg;
1122         u32 val;
1123         bool cur_state;
1124         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125                                                                       pipe);
1126
1127         if (HAS_DDI(dev_priv->dev)) {
1128                 /* DDI does not have a specific FDI_TX register */
1129                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130                 val = I915_READ(reg);
1131                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132         } else {
1133                 reg = FDI_TX_CTL(pipe);
1134                 val = I915_READ(reg);
1135                 cur_state = !!(val & FDI_TX_ENABLE);
1136         }
1137         WARN(cur_state != state,
1138              "FDI TX state assertion failure (expected %s, current %s)\n",
1139              state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145                           enum pipe pipe, bool state)
1146 {
1147         int reg;
1148         u32 val;
1149         bool cur_state;
1150
1151         reg = FDI_RX_CTL(pipe);
1152         val = I915_READ(reg);
1153         cur_state = !!(val & FDI_RX_ENABLE);
1154         WARN(cur_state != state,
1155              "FDI RX state assertion failure (expected %s, current %s)\n",
1156              state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162                                       enum pipe pipe)
1163 {
1164         int reg;
1165         u32 val;
1166
1167         /* ILK FDI PLL is always enabled */
1168         if (dev_priv->info->gen == 5)
1169                 return;
1170
1171         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172         if (HAS_DDI(dev_priv->dev))
1173                 return;
1174
1175         reg = FDI_TX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1181                                       enum pipe pipe)
1182 {
1183         int reg;
1184         u32 val;
1185
1186         reg = FDI_RX_CTL(pipe);
1187         val = I915_READ(reg);
1188         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1189 }
1190
1191 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1192                                   enum pipe pipe)
1193 {
1194         int pp_reg, lvds_reg;
1195         u32 val;
1196         enum pipe panel_pipe = PIPE_A;
1197         bool locked = true;
1198
1199         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1200                 pp_reg = PCH_PP_CONTROL;
1201                 lvds_reg = PCH_LVDS;
1202         } else {
1203                 pp_reg = PP_CONTROL;
1204                 lvds_reg = LVDS;
1205         }
1206
1207         val = I915_READ(pp_reg);
1208         if (!(val & PANEL_POWER_ON) ||
1209             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1210                 locked = false;
1211
1212         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1213                 panel_pipe = PIPE_B;
1214
1215         WARN(panel_pipe == pipe && locked,
1216              "panel assertion failure, pipe %c regs locked\n",
1217              pipe_name(pipe));
1218 }
1219
1220 void assert_pipe(struct drm_i915_private *dev_priv,
1221                  enum pipe pipe, bool state)
1222 {
1223         int reg;
1224         u32 val;
1225         bool cur_state;
1226         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1227                                                                       pipe);
1228
1229         /* if we need the pipe A quirk it must be always on */
1230         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1231                 state = true;
1232
1233         if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1234             !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1235                 cur_state = false;
1236         } else {
1237                 reg = PIPECONF(cpu_transcoder);
1238                 val = I915_READ(reg);
1239                 cur_state = !!(val & PIPECONF_ENABLE);
1240         }
1241
1242         WARN(cur_state != state,
1243              "pipe %c assertion failure (expected %s, current %s)\n",
1244              pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248                          enum plane plane, bool state)
1249 {
1250         int reg;
1251         u32 val;
1252         bool cur_state;
1253
1254         reg = DSPCNTR(plane);
1255         val = I915_READ(reg);
1256         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257         WARN(cur_state != state,
1258              "plane %c assertion failure (expected %s, current %s)\n",
1259              plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266                                    enum pipe pipe)
1267 {
1268         int reg, i;
1269         u32 val;
1270         int cur_pipe;
1271
1272         /* Planes are fixed to pipes on ILK+ */
1273         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1274                 reg = DSPCNTR(pipe);
1275                 val = I915_READ(reg);
1276                 WARN((val & DISPLAY_PLANE_ENABLE),
1277                      "plane %c assertion failure, should be disabled but not\n",
1278                      plane_name(pipe));
1279                 return;
1280         }
1281
1282         /* Need to check both planes against the pipe */
1283         for (i = 0; i < 2; i++) {
1284                 reg = DSPCNTR(i);
1285                 val = I915_READ(reg);
1286                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1287                         DISPPLANE_SEL_PIPE_SHIFT;
1288                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1289                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290                      plane_name(i), pipe_name(pipe));
1291         }
1292 }
1293
1294 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1295 {
1296         u32 val;
1297         bool enabled;
1298
1299         if (HAS_PCH_LPT(dev_priv->dev)) {
1300                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1301                 return;
1302         }
1303
1304         val = I915_READ(PCH_DREF_CONTROL);
1305         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1306                             DREF_SUPERSPREAD_SOURCE_MASK));
1307         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1308 }
1309
1310 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1311                                        enum pipe pipe)
1312 {
1313         int reg;
1314         u32 val;
1315         bool enabled;
1316
1317         reg = TRANSCONF(pipe);
1318         val = I915_READ(reg);
1319         enabled = !!(val & TRANS_ENABLE);
1320         WARN(enabled,
1321              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1322              pipe_name(pipe));
1323 }
1324
1325 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1326                             enum pipe pipe, u32 port_sel, u32 val)
1327 {
1328         if ((val & DP_PORT_EN) == 0)
1329                 return false;
1330
1331         if (HAS_PCH_CPT(dev_priv->dev)) {
1332                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1333                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1334                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1335                         return false;
1336         } else {
1337                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1338                         return false;
1339         }
1340         return true;
1341 }
1342
1343 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1344                               enum pipe pipe, u32 val)
1345 {
1346         if ((val & PORT_ENABLE) == 0)
1347                 return false;
1348
1349         if (HAS_PCH_CPT(dev_priv->dev)) {
1350                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351                         return false;
1352         } else {
1353                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1354                         return false;
1355         }
1356         return true;
1357 }
1358
1359 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1360                               enum pipe pipe, u32 val)
1361 {
1362         if ((val & LVDS_PORT_EN) == 0)
1363                 return false;
1364
1365         if (HAS_PCH_CPT(dev_priv->dev)) {
1366                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1367                         return false;
1368         } else {
1369                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1370                         return false;
1371         }
1372         return true;
1373 }
1374
1375 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1376                               enum pipe pipe, u32 val)
1377 {
1378         if ((val & ADPA_DAC_ENABLE) == 0)
1379                 return false;
1380         if (HAS_PCH_CPT(dev_priv->dev)) {
1381                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1382                         return false;
1383         } else {
1384                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1385                         return false;
1386         }
1387         return true;
1388 }
1389
1390 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1391                                    enum pipe pipe, int reg, u32 port_sel)
1392 {
1393         u32 val = I915_READ(reg);
1394         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1395              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1396              reg, pipe_name(pipe));
1397
1398         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1399              && (val & DP_PIPEB_SELECT),
1400              "IBX PCH dp port still using transcoder B\n");
1401 }
1402
1403 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1404                                      enum pipe pipe, int reg)
1405 {
1406         u32 val = I915_READ(reg);
1407         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1408              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1409              reg, pipe_name(pipe));
1410
1411         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1412              && (val & SDVO_PIPE_B_SELECT),
1413              "IBX PCH hdmi port still using transcoder B\n");
1414 }
1415
1416 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1417                                       enum pipe pipe)
1418 {
1419         int reg;
1420         u32 val;
1421
1422         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1423         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1424         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1425
1426         reg = PCH_ADPA;
1427         val = I915_READ(reg);
1428         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1429              "PCH VGA enabled on transcoder %c, should be disabled\n",
1430              pipe_name(pipe));
1431
1432         reg = PCH_LVDS;
1433         val = I915_READ(reg);
1434         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1435              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1439         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1440         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1441 }
1442
1443 /**
1444  * intel_enable_pll - enable a PLL
1445  * @dev_priv: i915 private structure
1446  * @pipe: pipe PLL to enable
1447  *
1448  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1449  * make sure the PLL reg is writable first though, since the panel write
1450  * protect mechanism may be enabled.
1451  *
1452  * Note!  This is for pre-ILK only.
1453  *
1454  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1455  */
1456 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1457 {
1458         int reg;
1459         u32 val;
1460
1461         /* No really, not for ILK+ */
1462         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1463
1464         /* PLL is protected by panel, make sure we can write it */
1465         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1466                 assert_panel_unlocked(dev_priv, pipe);
1467
1468         reg = DPLL(pipe);
1469         val = I915_READ(reg);
1470         val |= DPLL_VCO_ENABLE;
1471
1472         /* We do this three times for luck */
1473         I915_WRITE(reg, val);
1474         POSTING_READ(reg);
1475         udelay(150); /* wait for warmup */
1476         I915_WRITE(reg, val);
1477         POSTING_READ(reg);
1478         udelay(150); /* wait for warmup */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482 }
1483
1484 /**
1485  * intel_disable_pll - disable a PLL
1486  * @dev_priv: i915 private structure
1487  * @pipe: pipe PLL to disable
1488  *
1489  * Disable the PLL for @pipe, making sure the pipe is off first.
1490  *
1491  * Note!  This is for pre-ILK only.
1492  */
1493 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1494 {
1495         int reg;
1496         u32 val;
1497
1498         /* Don't disable pipe A or pipe A PLLs if needed */
1499         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1500                 return;
1501
1502         /* Make sure the pipe isn't still relying on us */
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         reg = DPLL(pipe);
1506         val = I915_READ(reg);
1507         val &= ~DPLL_VCO_ENABLE;
1508         I915_WRITE(reg, val);
1509         POSTING_READ(reg);
1510 }
1511
1512 /* SBI access */
1513 static void
1514 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1515                 enum intel_sbi_destination destination)
1516 {
1517         u32 tmp;
1518
1519         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1520
1521         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1522                                 100)) {
1523                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1524                 return;
1525         }
1526
1527         I915_WRITE(SBI_ADDR, (reg << 16));
1528         I915_WRITE(SBI_DATA, value);
1529
1530         if (destination == SBI_ICLK)
1531                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1532         else
1533                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1534         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1535
1536         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1537                                 100)) {
1538                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1539                 return;
1540         }
1541 }
1542
1543 static u32
1544 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1545                enum intel_sbi_destination destination)
1546 {
1547         u32 value = 0;
1548         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1549
1550         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1551                                 100)) {
1552                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1553                 return 0;
1554         }
1555
1556         I915_WRITE(SBI_ADDR, (reg << 16));
1557
1558         if (destination == SBI_ICLK)
1559                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1560         else
1561                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1562         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1563
1564         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1565                                 100)) {
1566                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1567                 return 0;
1568         }
1569
1570         return I915_READ(SBI_DATA);
1571 }
1572
1573 /**
1574  * ironlake_enable_pch_pll - enable PCH PLL
1575  * @dev_priv: i915 private structure
1576  * @pipe: pipe PLL to enable
1577  *
1578  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1579  * drives the transcoder clock.
1580  */
1581 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1582 {
1583         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1584         struct intel_pch_pll *pll;
1585         int reg;
1586         u32 val;
1587
1588         /* PCH PLLs only available on ILK, SNB and IVB */
1589         BUG_ON(dev_priv->info->gen < 5);
1590         pll = intel_crtc->pch_pll;
1591         if (pll == NULL)
1592                 return;
1593
1594         if (WARN_ON(pll->refcount == 0))
1595                 return;
1596
1597         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1598                       pll->pll_reg, pll->active, pll->on,
1599                       intel_crtc->base.base.id);
1600
1601         /* PCH refclock must be enabled first */
1602         assert_pch_refclk_enabled(dev_priv);
1603
1604         if (pll->active++ && pll->on) {
1605                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1606                 return;
1607         }
1608
1609         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1610
1611         reg = pll->pll_reg;
1612         val = I915_READ(reg);
1613         val |= DPLL_VCO_ENABLE;
1614         I915_WRITE(reg, val);
1615         POSTING_READ(reg);
1616         udelay(200);
1617
1618         pll->on = true;
1619 }
1620
1621 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1622 {
1623         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1624         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1625         int reg;
1626         u32 val;
1627
1628         /* PCH only available on ILK+ */
1629         BUG_ON(dev_priv->info->gen < 5);
1630         if (pll == NULL)
1631                return;
1632
1633         if (WARN_ON(pll->refcount == 0))
1634                 return;
1635
1636         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1637                       pll->pll_reg, pll->active, pll->on,
1638                       intel_crtc->base.base.id);
1639
1640         if (WARN_ON(pll->active == 0)) {
1641                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1642                 return;
1643         }
1644
1645         if (--pll->active) {
1646                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1647                 return;
1648         }
1649
1650         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1651
1652         /* Make sure transcoder isn't still depending on us */
1653         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1654
1655         reg = pll->pll_reg;
1656         val = I915_READ(reg);
1657         val &= ~DPLL_VCO_ENABLE;
1658         I915_WRITE(reg, val);
1659         POSTING_READ(reg);
1660         udelay(200);
1661
1662         pll->on = false;
1663 }
1664
1665 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1666                                            enum pipe pipe)
1667 {
1668         struct drm_device *dev = dev_priv->dev;
1669         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1670         uint32_t reg, val, pipeconf_val;
1671
1672         /* PCH only available on ILK+ */
1673         BUG_ON(dev_priv->info->gen < 5);
1674
1675         /* Make sure PCH DPLL is enabled */
1676         assert_pch_pll_enabled(dev_priv,
1677                                to_intel_crtc(crtc)->pch_pll,
1678                                to_intel_crtc(crtc));
1679
1680         /* FDI must be feeding us bits for PCH ports */
1681         assert_fdi_tx_enabled(dev_priv, pipe);
1682         assert_fdi_rx_enabled(dev_priv, pipe);
1683
1684         if (HAS_PCH_CPT(dev)) {
1685                 /* Workaround: Set the timing override bit before enabling the
1686                  * pch transcoder. */
1687                 reg = TRANS_CHICKEN2(pipe);
1688                 val = I915_READ(reg);
1689                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1690                 I915_WRITE(reg, val);
1691         }
1692
1693         reg = TRANSCONF(pipe);
1694         val = I915_READ(reg);
1695         pipeconf_val = I915_READ(PIPECONF(pipe));
1696
1697         if (HAS_PCH_IBX(dev_priv->dev)) {
1698                 /*
1699                  * make the BPC in transcoder be consistent with
1700                  * that in pipeconf reg.
1701                  */
1702                 val &= ~PIPECONF_BPC_MASK;
1703                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1704         }
1705
1706         val &= ~TRANS_INTERLACE_MASK;
1707         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1708                 if (HAS_PCH_IBX(dev_priv->dev) &&
1709                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1710                         val |= TRANS_LEGACY_INTERLACED_ILK;
1711                 else
1712                         val |= TRANS_INTERLACED;
1713         else
1714                 val |= TRANS_PROGRESSIVE;
1715
1716         I915_WRITE(reg, val | TRANS_ENABLE);
1717         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1718                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1719 }
1720
1721 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1722                                       enum transcoder cpu_transcoder)
1723 {
1724         u32 val, pipeconf_val;
1725
1726         /* PCH only available on ILK+ */
1727         BUG_ON(dev_priv->info->gen < 5);
1728
1729         /* FDI must be feeding us bits for PCH ports */
1730         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1731         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1732
1733         /* Workaround: set timing override bit. */
1734         val = I915_READ(_TRANSA_CHICKEN2);
1735         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1736         I915_WRITE(_TRANSA_CHICKEN2, val);
1737
1738         val = TRANS_ENABLE;
1739         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1740
1741         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1742             PIPECONF_INTERLACED_ILK)
1743                 val |= TRANS_INTERLACED;
1744         else
1745                 val |= TRANS_PROGRESSIVE;
1746
1747         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1748         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1749                 DRM_ERROR("Failed to enable PCH transcoder\n");
1750 }
1751
1752 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1753                                             enum pipe pipe)
1754 {
1755         struct drm_device *dev = dev_priv->dev;
1756         uint32_t reg, val;
1757
1758         /* FDI relies on the transcoder */
1759         assert_fdi_tx_disabled(dev_priv, pipe);
1760         assert_fdi_rx_disabled(dev_priv, pipe);
1761
1762         /* Ports must be off as well */
1763         assert_pch_ports_disabled(dev_priv, pipe);
1764
1765         reg = TRANSCONF(pipe);
1766         val = I915_READ(reg);
1767         val &= ~TRANS_ENABLE;
1768         I915_WRITE(reg, val);
1769         /* wait for PCH transcoder off, transcoder state */
1770         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1771                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1772
1773         if (!HAS_PCH_IBX(dev)) {
1774                 /* Workaround: Clear the timing override chicken bit again. */
1775                 reg = TRANS_CHICKEN2(pipe);
1776                 val = I915_READ(reg);
1777                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1778                 I915_WRITE(reg, val);
1779         }
1780 }
1781
1782 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1783 {
1784         u32 val;
1785
1786         val = I915_READ(_TRANSACONF);
1787         val &= ~TRANS_ENABLE;
1788         I915_WRITE(_TRANSACONF, val);
1789         /* wait for PCH transcoder off, transcoder state */
1790         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1791                 DRM_ERROR("Failed to disable PCH transcoder\n");
1792
1793         /* Workaround: clear timing override bit. */
1794         val = I915_READ(_TRANSA_CHICKEN2);
1795         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1796         I915_WRITE(_TRANSA_CHICKEN2, val);
1797 }
1798
1799 /**
1800  * intel_enable_pipe - enable a pipe, asserting requirements
1801  * @dev_priv: i915 private structure
1802  * @pipe: pipe to enable
1803  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1804  *
1805  * Enable @pipe, making sure that various hardware specific requirements
1806  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1807  *
1808  * @pipe should be %PIPE_A or %PIPE_B.
1809  *
1810  * Will wait until the pipe is actually running (i.e. first vblank) before
1811  * returning.
1812  */
1813 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1814                               bool pch_port)
1815 {
1816         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1817                                                                       pipe);
1818         enum pipe pch_transcoder;
1819         int reg;
1820         u32 val;
1821
1822         if (HAS_PCH_LPT(dev_priv->dev))
1823                 pch_transcoder = TRANSCODER_A;
1824         else
1825                 pch_transcoder = pipe;
1826
1827         /*
1828          * A pipe without a PLL won't actually be able to drive bits from
1829          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1830          * need the check.
1831          */
1832         if (!HAS_PCH_SPLIT(dev_priv->dev))
1833                 assert_pll_enabled(dev_priv, pipe);
1834         else {
1835                 if (pch_port) {
1836                         /* if driving the PCH, we need FDI enabled */
1837                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1838                         assert_fdi_tx_pll_enabled(dev_priv,
1839                                                   (enum pipe) cpu_transcoder);
1840                 }
1841                 /* FIXME: assert CPU port conditions for SNB+ */
1842         }
1843
1844         reg = PIPECONF(cpu_transcoder);
1845         val = I915_READ(reg);
1846         if (val & PIPECONF_ENABLE)
1847                 return;
1848
1849         I915_WRITE(reg, val | PIPECONF_ENABLE);
1850         intel_wait_for_vblank(dev_priv->dev, pipe);
1851 }
1852
1853 /**
1854  * intel_disable_pipe - disable a pipe, asserting requirements
1855  * @dev_priv: i915 private structure
1856  * @pipe: pipe to disable
1857  *
1858  * Disable @pipe, making sure that various hardware specific requirements
1859  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1860  *
1861  * @pipe should be %PIPE_A or %PIPE_B.
1862  *
1863  * Will wait until the pipe has shut down before returning.
1864  */
1865 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1866                                enum pipe pipe)
1867 {
1868         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1869                                                                       pipe);
1870         int reg;
1871         u32 val;
1872
1873         /*
1874          * Make sure planes won't keep trying to pump pixels to us,
1875          * or we might hang the display.
1876          */
1877         assert_planes_disabled(dev_priv, pipe);
1878
1879         /* Don't disable pipe A or pipe A PLLs if needed */
1880         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1881                 return;
1882
1883         reg = PIPECONF(cpu_transcoder);
1884         val = I915_READ(reg);
1885         if ((val & PIPECONF_ENABLE) == 0)
1886                 return;
1887
1888         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1889         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1890 }
1891
1892 /*
1893  * Plane regs are double buffered, going from enabled->disabled needs a
1894  * trigger in order to latch.  The display address reg provides this.
1895  */
1896 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1897                                       enum plane plane)
1898 {
1899         if (dev_priv->info->gen >= 4)
1900                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1901         else
1902                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1903 }
1904
1905 /**
1906  * intel_enable_plane - enable a display plane on a given pipe
1907  * @dev_priv: i915 private structure
1908  * @plane: plane to enable
1909  * @pipe: pipe being fed
1910  *
1911  * Enable @plane on @pipe, making sure that @pipe is running first.
1912  */
1913 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1914                                enum plane plane, enum pipe pipe)
1915 {
1916         int reg;
1917         u32 val;
1918
1919         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1920         assert_pipe_enabled(dev_priv, pipe);
1921
1922         reg = DSPCNTR(plane);
1923         val = I915_READ(reg);
1924         if (val & DISPLAY_PLANE_ENABLE)
1925                 return;
1926
1927         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1928         intel_flush_display_plane(dev_priv, plane);
1929         intel_wait_for_vblank(dev_priv->dev, pipe);
1930 }
1931
1932 /**
1933  * intel_disable_plane - disable a display plane
1934  * @dev_priv: i915 private structure
1935  * @plane: plane to disable
1936  * @pipe: pipe consuming the data
1937  *
1938  * Disable @plane; should be an independent operation.
1939  */
1940 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1941                                 enum plane plane, enum pipe pipe)
1942 {
1943         int reg;
1944         u32 val;
1945
1946         reg = DSPCNTR(plane);
1947         val = I915_READ(reg);
1948         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1949                 return;
1950
1951         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1952         intel_flush_display_plane(dev_priv, plane);
1953         intel_wait_for_vblank(dev_priv->dev, pipe);
1954 }
1955
1956 int
1957 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1958                            struct drm_i915_gem_object *obj,
1959                            struct intel_ring_buffer *pipelined)
1960 {
1961         struct drm_i915_private *dev_priv = dev->dev_private;
1962         u32 alignment;
1963         int ret;
1964
1965         switch (obj->tiling_mode) {
1966         case I915_TILING_NONE:
1967                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1968                         alignment = 128 * 1024;
1969                 else if (INTEL_INFO(dev)->gen >= 4)
1970                         alignment = 4 * 1024;
1971                 else
1972                         alignment = 64 * 1024;
1973                 break;
1974         case I915_TILING_X:
1975                 /* pin() will align the object as required by fence */
1976                 alignment = 0;
1977                 break;
1978         case I915_TILING_Y:
1979                 /* FIXME: Is this true? */
1980                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1981                 return -EINVAL;
1982         default:
1983                 BUG();
1984         }
1985
1986         dev_priv->mm.interruptible = false;
1987         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1988         if (ret)
1989                 goto err_interruptible;
1990
1991         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1992          * fence, whereas 965+ only requires a fence if using
1993          * framebuffer compression.  For simplicity, we always install
1994          * a fence as the cost is not that onerous.
1995          */
1996         ret = i915_gem_object_get_fence(obj);
1997         if (ret)
1998                 goto err_unpin;
1999
2000         i915_gem_object_pin_fence(obj);
2001
2002         dev_priv->mm.interruptible = true;
2003         return 0;
2004
2005 err_unpin:
2006         i915_gem_object_unpin(obj);
2007 err_interruptible:
2008         dev_priv->mm.interruptible = true;
2009         return ret;
2010 }
2011
2012 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2013 {
2014         i915_gem_object_unpin_fence(obj);
2015         i915_gem_object_unpin(obj);
2016 }
2017
2018 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2019  * is assumed to be a power-of-two. */
2020 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2021                                                unsigned int bpp,
2022                                                unsigned int pitch)
2023 {
2024         int tile_rows, tiles;
2025
2026         tile_rows = *y / 8;
2027         *y %= 8;
2028         tiles = *x / (512/bpp);
2029         *x %= 512/bpp;
2030
2031         return tile_rows * pitch * 8 + tiles * 4096;
2032 }
2033
2034 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2035                              int x, int y)
2036 {
2037         struct drm_device *dev = crtc->dev;
2038         struct drm_i915_private *dev_priv = dev->dev_private;
2039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2040         struct intel_framebuffer *intel_fb;
2041         struct drm_i915_gem_object *obj;
2042         int plane = intel_crtc->plane;
2043         unsigned long linear_offset;
2044         u32 dspcntr;
2045         u32 reg;
2046
2047         switch (plane) {
2048         case 0:
2049         case 1:
2050                 break;
2051         default:
2052                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2053                 return -EINVAL;
2054         }
2055
2056         intel_fb = to_intel_framebuffer(fb);
2057         obj = intel_fb->obj;
2058
2059         reg = DSPCNTR(plane);
2060         dspcntr = I915_READ(reg);
2061         /* Mask out pixel format bits in case we change it */
2062         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2063         switch (fb->pixel_format) {
2064         case DRM_FORMAT_C8:
2065                 dspcntr |= DISPPLANE_8BPP;
2066                 break;
2067         case DRM_FORMAT_XRGB1555:
2068         case DRM_FORMAT_ARGB1555:
2069                 dspcntr |= DISPPLANE_BGRX555;
2070                 break;
2071         case DRM_FORMAT_RGB565:
2072                 dspcntr |= DISPPLANE_BGRX565;
2073                 break;
2074         case DRM_FORMAT_XRGB8888:
2075         case DRM_FORMAT_ARGB8888:
2076                 dspcntr |= DISPPLANE_BGRX888;
2077                 break;
2078         case DRM_FORMAT_XBGR8888:
2079         case DRM_FORMAT_ABGR8888:
2080                 dspcntr |= DISPPLANE_RGBX888;
2081                 break;
2082         case DRM_FORMAT_XRGB2101010:
2083         case DRM_FORMAT_ARGB2101010:
2084                 dspcntr |= DISPPLANE_BGRX101010;
2085                 break;
2086         case DRM_FORMAT_XBGR2101010:
2087         case DRM_FORMAT_ABGR2101010:
2088                 dspcntr |= DISPPLANE_RGBX101010;
2089                 break;
2090         default:
2091                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2092                 return -EINVAL;
2093         }
2094
2095         if (INTEL_INFO(dev)->gen >= 4) {
2096                 if (obj->tiling_mode != I915_TILING_NONE)
2097                         dspcntr |= DISPPLANE_TILED;
2098                 else
2099                         dspcntr &= ~DISPPLANE_TILED;
2100         }
2101
2102         I915_WRITE(reg, dspcntr);
2103
2104         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2105
2106         if (INTEL_INFO(dev)->gen >= 4) {
2107                 intel_crtc->dspaddr_offset =
2108                         intel_gen4_compute_offset_xtiled(&x, &y,
2109                                                          fb->bits_per_pixel / 8,
2110                                                          fb->pitches[0]);
2111                 linear_offset -= intel_crtc->dspaddr_offset;
2112         } else {
2113                 intel_crtc->dspaddr_offset = linear_offset;
2114         }
2115
2116         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2117                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2118         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119         if (INTEL_INFO(dev)->gen >= 4) {
2120                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2121                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2122                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2123                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2124         } else
2125                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2126         POSTING_READ(reg);
2127
2128         return 0;
2129 }
2130
2131 static int ironlake_update_plane(struct drm_crtc *crtc,
2132                                  struct drm_framebuffer *fb, int x, int y)
2133 {
2134         struct drm_device *dev = crtc->dev;
2135         struct drm_i915_private *dev_priv = dev->dev_private;
2136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2137         struct intel_framebuffer *intel_fb;
2138         struct drm_i915_gem_object *obj;
2139         int plane = intel_crtc->plane;
2140         unsigned long linear_offset;
2141         u32 dspcntr;
2142         u32 reg;
2143
2144         switch (plane) {
2145         case 0:
2146         case 1:
2147         case 2:
2148                 break;
2149         default:
2150                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2151                 return -EINVAL;
2152         }
2153
2154         intel_fb = to_intel_framebuffer(fb);
2155         obj = intel_fb->obj;
2156
2157         reg = DSPCNTR(plane);
2158         dspcntr = I915_READ(reg);
2159         /* Mask out pixel format bits in case we change it */
2160         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2161         switch (fb->pixel_format) {
2162         case DRM_FORMAT_C8:
2163                 dspcntr |= DISPPLANE_8BPP;
2164                 break;
2165         case DRM_FORMAT_RGB565:
2166                 dspcntr |= DISPPLANE_BGRX565;
2167                 break;
2168         case DRM_FORMAT_XRGB8888:
2169         case DRM_FORMAT_ARGB8888:
2170                 dspcntr |= DISPPLANE_BGRX888;
2171                 break;
2172         case DRM_FORMAT_XBGR8888:
2173         case DRM_FORMAT_ABGR8888:
2174                 dspcntr |= DISPPLANE_RGBX888;
2175                 break;
2176         case DRM_FORMAT_XRGB2101010:
2177         case DRM_FORMAT_ARGB2101010:
2178                 dspcntr |= DISPPLANE_BGRX101010;
2179                 break;
2180         case DRM_FORMAT_XBGR2101010:
2181         case DRM_FORMAT_ABGR2101010:
2182                 dspcntr |= DISPPLANE_RGBX101010;
2183                 break;
2184         default:
2185                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2186                 return -EINVAL;
2187         }
2188
2189         if (obj->tiling_mode != I915_TILING_NONE)
2190                 dspcntr |= DISPPLANE_TILED;
2191         else
2192                 dspcntr &= ~DISPPLANE_TILED;
2193
2194         /* must disable */
2195         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2196
2197         I915_WRITE(reg, dspcntr);
2198
2199         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2200         intel_crtc->dspaddr_offset =
2201                 intel_gen4_compute_offset_xtiled(&x, &y,
2202                                                  fb->bits_per_pixel / 8,
2203                                                  fb->pitches[0]);
2204         linear_offset -= intel_crtc->dspaddr_offset;
2205
2206         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2207                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2208         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2209         I915_MODIFY_DISPBASE(DSPSURF(plane),
2210                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2211         if (IS_HASWELL(dev)) {
2212                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2213         } else {
2214                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2215                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2216         }
2217         POSTING_READ(reg);
2218
2219         return 0;
2220 }
2221
2222 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2223 static int
2224 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2225                            int x, int y, enum mode_set_atomic state)
2226 {
2227         struct drm_device *dev = crtc->dev;
2228         struct drm_i915_private *dev_priv = dev->dev_private;
2229
2230         if (dev_priv->display.disable_fbc)
2231                 dev_priv->display.disable_fbc(dev);
2232         intel_increase_pllclock(crtc);
2233
2234         return dev_priv->display.update_plane(crtc, fb, x, y);
2235 }
2236
2237 void intel_display_handle_reset(struct drm_device *dev)
2238 {
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct drm_crtc *crtc;
2241
2242         /*
2243          * Flips in the rings have been nuked by the reset,
2244          * so complete all pending flips so that user space
2245          * will get its events and not get stuck.
2246          *
2247          * Also update the base address of all primary
2248          * planes to the the last fb to make sure we're
2249          * showing the correct fb after a reset.
2250          *
2251          * Need to make two loops over the crtcs so that we
2252          * don't try to grab a crtc mutex before the
2253          * pending_flip_queue really got woken up.
2254          */
2255
2256         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2257                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2258                 enum plane plane = intel_crtc->plane;
2259
2260                 intel_prepare_page_flip(dev, plane);
2261                 intel_finish_page_flip_plane(dev, plane);
2262         }
2263
2264         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2265                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2266
2267                 mutex_lock(&crtc->mutex);
2268                 if (intel_crtc->active)
2269                         dev_priv->display.update_plane(crtc, crtc->fb,
2270                                                        crtc->x, crtc->y);
2271                 mutex_unlock(&crtc->mutex);
2272         }
2273 }
2274
2275 static int
2276 intel_finish_fb(struct drm_framebuffer *old_fb)
2277 {
2278         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2279         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2280         bool was_interruptible = dev_priv->mm.interruptible;
2281         int ret;
2282
2283         /* Big Hammer, we also need to ensure that any pending
2284          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2285          * current scanout is retired before unpinning the old
2286          * framebuffer.
2287          *
2288          * This should only fail upon a hung GPU, in which case we
2289          * can safely continue.
2290          */
2291         dev_priv->mm.interruptible = false;
2292         ret = i915_gem_object_finish_gpu(obj);
2293         dev_priv->mm.interruptible = was_interruptible;
2294
2295         return ret;
2296 }
2297
2298 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2299 {
2300         struct drm_device *dev = crtc->dev;
2301         struct drm_i915_master_private *master_priv;
2302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303
2304         if (!dev->primary->master)
2305                 return;
2306
2307         master_priv = dev->primary->master->driver_priv;
2308         if (!master_priv->sarea_priv)
2309                 return;
2310
2311         switch (intel_crtc->pipe) {
2312         case 0:
2313                 master_priv->sarea_priv->pipeA_x = x;
2314                 master_priv->sarea_priv->pipeA_y = y;
2315                 break;
2316         case 1:
2317                 master_priv->sarea_priv->pipeB_x = x;
2318                 master_priv->sarea_priv->pipeB_y = y;
2319                 break;
2320         default:
2321                 break;
2322         }
2323 }
2324
2325 static int
2326 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2327                     struct drm_framebuffer *fb)
2328 {
2329         struct drm_device *dev = crtc->dev;
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332         struct drm_framebuffer *old_fb;
2333         int ret;
2334
2335         /* no fb bound */
2336         if (!fb) {
2337                 DRM_ERROR("No FB bound\n");
2338                 return 0;
2339         }
2340
2341         if(intel_crtc->plane > dev_priv->num_pipe) {
2342                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2343                                 intel_crtc->plane,
2344                                 dev_priv->num_pipe);
2345                 return -EINVAL;
2346         }
2347
2348         mutex_lock(&dev->struct_mutex);
2349         ret = intel_pin_and_fence_fb_obj(dev,
2350                                          to_intel_framebuffer(fb)->obj,
2351                                          NULL);
2352         if (ret != 0) {
2353                 mutex_unlock(&dev->struct_mutex);
2354                 DRM_ERROR("pin & fence failed\n");
2355                 return ret;
2356         }
2357
2358         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2359         if (ret) {
2360                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2361                 mutex_unlock(&dev->struct_mutex);
2362                 DRM_ERROR("failed to update base address\n");
2363                 return ret;
2364         }
2365
2366         old_fb = crtc->fb;
2367         crtc->fb = fb;
2368         crtc->x = x;
2369         crtc->y = y;
2370
2371         if (old_fb) {
2372                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2373                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2374         }
2375
2376         intel_update_fbc(dev);
2377         mutex_unlock(&dev->struct_mutex);
2378
2379         intel_crtc_update_sarea_pos(crtc, x, y);
2380
2381         return 0;
2382 }
2383
2384 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2385 {
2386         struct drm_device *dev = crtc->dev;
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2389         int pipe = intel_crtc->pipe;
2390         u32 reg, temp;
2391
2392         /* enable normal train */
2393         reg = FDI_TX_CTL(pipe);
2394         temp = I915_READ(reg);
2395         if (IS_IVYBRIDGE(dev)) {
2396                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2397                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2398         } else {
2399                 temp &= ~FDI_LINK_TRAIN_NONE;
2400                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2401         }
2402         I915_WRITE(reg, temp);
2403
2404         reg = FDI_RX_CTL(pipe);
2405         temp = I915_READ(reg);
2406         if (HAS_PCH_CPT(dev)) {
2407                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2408                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2409         } else {
2410                 temp &= ~FDI_LINK_TRAIN_NONE;
2411                 temp |= FDI_LINK_TRAIN_NONE;
2412         }
2413         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2414
2415         /* wait one idle pattern time */
2416         POSTING_READ(reg);
2417         udelay(1000);
2418
2419         /* IVB wants error correction enabled */
2420         if (IS_IVYBRIDGE(dev))
2421                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2422                            FDI_FE_ERRC_ENABLE);
2423 }
2424
2425 static void ivb_modeset_global_resources(struct drm_device *dev)
2426 {
2427         struct drm_i915_private *dev_priv = dev->dev_private;
2428         struct intel_crtc *pipe_B_crtc =
2429                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2430         struct intel_crtc *pipe_C_crtc =
2431                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2432         uint32_t temp;
2433
2434         /* When everything is off disable fdi C so that we could enable fdi B
2435          * with all lanes. XXX: This misses the case where a pipe is not using
2436          * any pch resources and so doesn't need any fdi lanes. */
2437         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2438                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2439                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2440
2441                 temp = I915_READ(SOUTH_CHICKEN1);
2442                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2443                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2444                 I915_WRITE(SOUTH_CHICKEN1, temp);
2445         }
2446 }
2447
2448 /* The FDI link training functions for ILK/Ibexpeak. */
2449 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2450 {
2451         struct drm_device *dev = crtc->dev;
2452         struct drm_i915_private *dev_priv = dev->dev_private;
2453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2454         int pipe = intel_crtc->pipe;
2455         int plane = intel_crtc->plane;
2456         u32 reg, temp, tries;
2457
2458         /* FDI needs bits from pipe & plane first */
2459         assert_pipe_enabled(dev_priv, pipe);
2460         assert_plane_enabled(dev_priv, plane);
2461
2462         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2463            for train result */
2464         reg = FDI_RX_IMR(pipe);
2465         temp = I915_READ(reg);
2466         temp &= ~FDI_RX_SYMBOL_LOCK;
2467         temp &= ~FDI_RX_BIT_LOCK;
2468         I915_WRITE(reg, temp);
2469         I915_READ(reg);
2470         udelay(150);
2471
2472         /* enable CPU FDI TX and PCH FDI RX */
2473         reg = FDI_TX_CTL(pipe);
2474         temp = I915_READ(reg);
2475         temp &= ~(7 << 19);
2476         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2477         temp &= ~FDI_LINK_TRAIN_NONE;
2478         temp |= FDI_LINK_TRAIN_PATTERN_1;
2479         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2480
2481         reg = FDI_RX_CTL(pipe);
2482         temp = I915_READ(reg);
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_1;
2485         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2486
2487         POSTING_READ(reg);
2488         udelay(150);
2489
2490         /* Ironlake workaround, enable clock pointer after FDI enable*/
2491         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2492         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2493                    FDI_RX_PHASE_SYNC_POINTER_EN);
2494
2495         reg = FDI_RX_IIR(pipe);
2496         for (tries = 0; tries < 5; tries++) {
2497                 temp = I915_READ(reg);
2498                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2499
2500                 if ((temp & FDI_RX_BIT_LOCK)) {
2501                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2502                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2503                         break;
2504                 }
2505         }
2506         if (tries == 5)
2507                 DRM_ERROR("FDI train 1 fail!\n");
2508
2509         /* Train 2 */
2510         reg = FDI_TX_CTL(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_LINK_TRAIN_NONE;
2513         temp |= FDI_LINK_TRAIN_PATTERN_2;
2514         I915_WRITE(reg, temp);
2515
2516         reg = FDI_RX_CTL(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_LINK_TRAIN_NONE;
2519         temp |= FDI_LINK_TRAIN_PATTERN_2;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         reg = FDI_RX_IIR(pipe);
2526         for (tries = 0; tries < 5; tries++) {
2527                 temp = I915_READ(reg);
2528                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529
2530                 if (temp & FDI_RX_SYMBOL_LOCK) {
2531                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2532                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2533                         break;
2534                 }
2535         }
2536         if (tries == 5)
2537                 DRM_ERROR("FDI train 2 fail!\n");
2538
2539         DRM_DEBUG_KMS("FDI train done\n");
2540
2541 }
2542
2543 static const int snb_b_fdi_train_param[] = {
2544         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2545         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2546         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2547         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2548 };
2549
2550 /* The FDI link training functions for SNB/Cougarpoint. */
2551 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2552 {
2553         struct drm_device *dev = crtc->dev;
2554         struct drm_i915_private *dev_priv = dev->dev_private;
2555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556         int pipe = intel_crtc->pipe;
2557         u32 reg, temp, i, retry;
2558
2559         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2560            for train result */
2561         reg = FDI_RX_IMR(pipe);
2562         temp = I915_READ(reg);
2563         temp &= ~FDI_RX_SYMBOL_LOCK;
2564         temp &= ~FDI_RX_BIT_LOCK;
2565         I915_WRITE(reg, temp);
2566
2567         POSTING_READ(reg);
2568         udelay(150);
2569
2570         /* enable CPU FDI TX and PCH FDI RX */
2571         reg = FDI_TX_CTL(pipe);
2572         temp = I915_READ(reg);
2573         temp &= ~(7 << 19);
2574         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2575         temp &= ~FDI_LINK_TRAIN_NONE;
2576         temp |= FDI_LINK_TRAIN_PATTERN_1;
2577         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2578         /* SNB-B */
2579         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2580         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2581
2582         I915_WRITE(FDI_RX_MISC(pipe),
2583                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2584
2585         reg = FDI_RX_CTL(pipe);
2586         temp = I915_READ(reg);
2587         if (HAS_PCH_CPT(dev)) {
2588                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2590         } else {
2591                 temp &= ~FDI_LINK_TRAIN_NONE;
2592                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2593         }
2594         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2595
2596         POSTING_READ(reg);
2597         udelay(150);
2598
2599         for (i = 0; i < 4; i++) {
2600                 reg = FDI_TX_CTL(pipe);
2601                 temp = I915_READ(reg);
2602                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603                 temp |= snb_b_fdi_train_param[i];
2604                 I915_WRITE(reg, temp);
2605
2606                 POSTING_READ(reg);
2607                 udelay(500);
2608
2609                 for (retry = 0; retry < 5; retry++) {
2610                         reg = FDI_RX_IIR(pipe);
2611                         temp = I915_READ(reg);
2612                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613                         if (temp & FDI_RX_BIT_LOCK) {
2614                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2615                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2616                                 break;
2617                         }
2618                         udelay(50);
2619                 }
2620                 if (retry < 5)
2621                         break;
2622         }
2623         if (i == 4)
2624                 DRM_ERROR("FDI train 1 fail!\n");
2625
2626         /* Train 2 */
2627         reg = FDI_TX_CTL(pipe);
2628         temp = I915_READ(reg);
2629         temp &= ~FDI_LINK_TRAIN_NONE;
2630         temp |= FDI_LINK_TRAIN_PATTERN_2;
2631         if (IS_GEN6(dev)) {
2632                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2633                 /* SNB-B */
2634                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2635         }
2636         I915_WRITE(reg, temp);
2637
2638         reg = FDI_RX_CTL(pipe);
2639         temp = I915_READ(reg);
2640         if (HAS_PCH_CPT(dev)) {
2641                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2642                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2643         } else {
2644                 temp &= ~FDI_LINK_TRAIN_NONE;
2645                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2646         }
2647         I915_WRITE(reg, temp);
2648
2649         POSTING_READ(reg);
2650         udelay(150);
2651
2652         for (i = 0; i < 4; i++) {
2653                 reg = FDI_TX_CTL(pipe);
2654                 temp = I915_READ(reg);
2655                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2656                 temp |= snb_b_fdi_train_param[i];
2657                 I915_WRITE(reg, temp);
2658
2659                 POSTING_READ(reg);
2660                 udelay(500);
2661
2662                 for (retry = 0; retry < 5; retry++) {
2663                         reg = FDI_RX_IIR(pipe);
2664                         temp = I915_READ(reg);
2665                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666                         if (temp & FDI_RX_SYMBOL_LOCK) {
2667                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2668                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2669                                 break;
2670                         }
2671                         udelay(50);
2672                 }
2673                 if (retry < 5)
2674                         break;
2675         }
2676         if (i == 4)
2677                 DRM_ERROR("FDI train 2 fail!\n");
2678
2679         DRM_DEBUG_KMS("FDI train done.\n");
2680 }
2681
2682 /* Manual link training for Ivy Bridge A0 parts */
2683 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2684 {
2685         struct drm_device *dev = crtc->dev;
2686         struct drm_i915_private *dev_priv = dev->dev_private;
2687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2688         int pipe = intel_crtc->pipe;
2689         u32 reg, temp, i;
2690
2691         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2692            for train result */
2693         reg = FDI_RX_IMR(pipe);
2694         temp = I915_READ(reg);
2695         temp &= ~FDI_RX_SYMBOL_LOCK;
2696         temp &= ~FDI_RX_BIT_LOCK;
2697         I915_WRITE(reg, temp);
2698
2699         POSTING_READ(reg);
2700         udelay(150);
2701
2702         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2703                       I915_READ(FDI_RX_IIR(pipe)));
2704
2705         /* enable CPU FDI TX and PCH FDI RX */
2706         reg = FDI_TX_CTL(pipe);
2707         temp = I915_READ(reg);
2708         temp &= ~(7 << 19);
2709         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2710         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2711         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2712         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2713         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2714         temp |= FDI_COMPOSITE_SYNC;
2715         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2716
2717         I915_WRITE(FDI_RX_MISC(pipe),
2718                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2719
2720         reg = FDI_RX_CTL(pipe);
2721         temp = I915_READ(reg);
2722         temp &= ~FDI_LINK_TRAIN_AUTO;
2723         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2724         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2725         temp |= FDI_COMPOSITE_SYNC;
2726         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2727
2728         POSTING_READ(reg);
2729         udelay(150);
2730
2731         for (i = 0; i < 4; i++) {
2732                 reg = FDI_TX_CTL(pipe);
2733                 temp = I915_READ(reg);
2734                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2735                 temp |= snb_b_fdi_train_param[i];
2736                 I915_WRITE(reg, temp);
2737
2738                 POSTING_READ(reg);
2739                 udelay(500);
2740
2741                 reg = FDI_RX_IIR(pipe);
2742                 temp = I915_READ(reg);
2743                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2744
2745                 if (temp & FDI_RX_BIT_LOCK ||
2746                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2747                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2748                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2749                         break;
2750                 }
2751         }
2752         if (i == 4)
2753                 DRM_ERROR("FDI train 1 fail!\n");
2754
2755         /* Train 2 */
2756         reg = FDI_TX_CTL(pipe);
2757         temp = I915_READ(reg);
2758         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2759         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2760         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2761         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2762         I915_WRITE(reg, temp);
2763
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2768         I915_WRITE(reg, temp);
2769
2770         POSTING_READ(reg);
2771         udelay(150);
2772
2773         for (i = 0; i < 4; i++) {
2774                 reg = FDI_TX_CTL(pipe);
2775                 temp = I915_READ(reg);
2776                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2777                 temp |= snb_b_fdi_train_param[i];
2778                 I915_WRITE(reg, temp);
2779
2780                 POSTING_READ(reg);
2781                 udelay(500);
2782
2783                 reg = FDI_RX_IIR(pipe);
2784                 temp = I915_READ(reg);
2785                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2786
2787                 if (temp & FDI_RX_SYMBOL_LOCK) {
2788                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2789                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2790                         break;
2791                 }
2792         }
2793         if (i == 4)
2794                 DRM_ERROR("FDI train 2 fail!\n");
2795
2796         DRM_DEBUG_KMS("FDI train done.\n");
2797 }
2798
2799 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2800 {
2801         struct drm_device *dev = intel_crtc->base.dev;
2802         struct drm_i915_private *dev_priv = dev->dev_private;
2803         int pipe = intel_crtc->pipe;
2804         u32 reg, temp;
2805
2806
2807         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2808         reg = FDI_RX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         temp &= ~((0x7 << 19) | (0x7 << 16));
2811         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2812         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2813         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2814
2815         POSTING_READ(reg);
2816         udelay(200);
2817
2818         /* Switch from Rawclk to PCDclk */
2819         temp = I915_READ(reg);
2820         I915_WRITE(reg, temp | FDI_PCDCLK);
2821
2822         POSTING_READ(reg);
2823         udelay(200);
2824
2825         /* Enable CPU FDI TX PLL, always on for Ironlake */
2826         reg = FDI_TX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2829                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2830
2831                 POSTING_READ(reg);
2832                 udelay(100);
2833         }
2834 }
2835
2836 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2837 {
2838         struct drm_device *dev = intel_crtc->base.dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840         int pipe = intel_crtc->pipe;
2841         u32 reg, temp;
2842
2843         /* Switch from PCDclk to Rawclk */
2844         reg = FDI_RX_CTL(pipe);
2845         temp = I915_READ(reg);
2846         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2847
2848         /* Disable CPU FDI TX PLL */
2849         reg = FDI_TX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2852
2853         POSTING_READ(reg);
2854         udelay(100);
2855
2856         reg = FDI_RX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2859
2860         /* Wait for the clocks to turn off. */
2861         POSTING_READ(reg);
2862         udelay(100);
2863 }
2864
2865 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2866 {
2867         struct drm_device *dev = crtc->dev;
2868         struct drm_i915_private *dev_priv = dev->dev_private;
2869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2870         int pipe = intel_crtc->pipe;
2871         u32 reg, temp;
2872
2873         /* disable CPU FDI tx and PCH FDI rx */
2874         reg = FDI_TX_CTL(pipe);
2875         temp = I915_READ(reg);
2876         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2877         POSTING_READ(reg);
2878
2879         reg = FDI_RX_CTL(pipe);
2880         temp = I915_READ(reg);
2881         temp &= ~(0x7 << 16);
2882         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2883         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2884
2885         POSTING_READ(reg);
2886         udelay(100);
2887
2888         /* Ironlake workaround, disable clock pointer after downing FDI */
2889         if (HAS_PCH_IBX(dev)) {
2890                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2891         }
2892
2893         /* still set train pattern 1 */
2894         reg = FDI_TX_CTL(pipe);
2895         temp = I915_READ(reg);
2896         temp &= ~FDI_LINK_TRAIN_NONE;
2897         temp |= FDI_LINK_TRAIN_PATTERN_1;
2898         I915_WRITE(reg, temp);
2899
2900         reg = FDI_RX_CTL(pipe);
2901         temp = I915_READ(reg);
2902         if (HAS_PCH_CPT(dev)) {
2903                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2904                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2905         } else {
2906                 temp &= ~FDI_LINK_TRAIN_NONE;
2907                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2908         }
2909         /* BPC in FDI rx is consistent with that in PIPECONF */
2910         temp &= ~(0x07 << 16);
2911         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2912         I915_WRITE(reg, temp);
2913
2914         POSTING_READ(reg);
2915         udelay(100);
2916 }
2917
2918 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2919 {
2920         struct drm_device *dev = crtc->dev;
2921         struct drm_i915_private *dev_priv = dev->dev_private;
2922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2923         unsigned long flags;
2924         bool pending;
2925
2926         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2927             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2928                 return false;
2929
2930         spin_lock_irqsave(&dev->event_lock, flags);
2931         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2932         spin_unlock_irqrestore(&dev->event_lock, flags);
2933
2934         return pending;
2935 }
2936
2937 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2938 {
2939         struct drm_device *dev = crtc->dev;
2940         struct drm_i915_private *dev_priv = dev->dev_private;
2941
2942         if (crtc->fb == NULL)
2943                 return;
2944
2945         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2946
2947         wait_event(dev_priv->pending_flip_queue,
2948                    !intel_crtc_has_pending_flip(crtc));
2949
2950         mutex_lock(&dev->struct_mutex);
2951         intel_finish_fb(crtc->fb);
2952         mutex_unlock(&dev->struct_mutex);
2953 }
2954
2955 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2956 {
2957         struct drm_device *dev = crtc->dev;
2958         struct intel_encoder *intel_encoder;
2959
2960         /*
2961          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2962          * must be driven by its own crtc; no sharing is possible.
2963          */
2964         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2965                 switch (intel_encoder->type) {
2966                 case INTEL_OUTPUT_EDP:
2967                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2968                                 return false;
2969                         continue;
2970                 }
2971         }
2972
2973         return true;
2974 }
2975
2976 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2977 {
2978         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2979 }
2980
2981 /* Program iCLKIP clock to the desired frequency */
2982 static void lpt_program_iclkip(struct drm_crtc *crtc)
2983 {
2984         struct drm_device *dev = crtc->dev;
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2987         u32 temp;
2988
2989         mutex_lock(&dev_priv->dpio_lock);
2990
2991         /* It is necessary to ungate the pixclk gate prior to programming
2992          * the divisors, and gate it back when it is done.
2993          */
2994         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2995
2996         /* Disable SSCCTL */
2997         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2998                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2999                                 SBI_SSCCTL_DISABLE,
3000                         SBI_ICLK);
3001
3002         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3003         if (crtc->mode.clock == 20000) {
3004                 auxdiv = 1;
3005                 divsel = 0x41;
3006                 phaseinc = 0x20;
3007         } else {
3008                 /* The iCLK virtual clock root frequency is in MHz,
3009                  * but the crtc->mode.clock in in KHz. To get the divisors,
3010                  * it is necessary to divide one by another, so we
3011                  * convert the virtual clock precision to KHz here for higher
3012                  * precision.
3013                  */
3014                 u32 iclk_virtual_root_freq = 172800 * 1000;
3015                 u32 iclk_pi_range = 64;
3016                 u32 desired_divisor, msb_divisor_value, pi_value;
3017
3018                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3019                 msb_divisor_value = desired_divisor / iclk_pi_range;
3020                 pi_value = desired_divisor % iclk_pi_range;
3021
3022                 auxdiv = 0;
3023                 divsel = msb_divisor_value - 2;
3024                 phaseinc = pi_value;
3025         }
3026
3027         /* This should not happen with any sane values */
3028         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3029                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3030         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3031                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3032
3033         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3034                         crtc->mode.clock,
3035                         auxdiv,
3036                         divsel,
3037                         phasedir,
3038                         phaseinc);
3039
3040         /* Program SSCDIVINTPHASE6 */
3041         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3042         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3043         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3044         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3045         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3046         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3047         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3048         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3049
3050         /* Program SSCAUXDIV */
3051         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3052         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3053         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3054         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3055
3056         /* Enable modulator and associated divider */
3057         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3058         temp &= ~SBI_SSCCTL_DISABLE;
3059         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3060
3061         /* Wait for initialization time */
3062         udelay(24);
3063
3064         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3065
3066         mutex_unlock(&dev_priv->dpio_lock);
3067 }
3068
3069 /*
3070  * Enable PCH resources required for PCH ports:
3071  *   - PCH PLLs
3072  *   - FDI training & RX/TX
3073  *   - update transcoder timings
3074  *   - DP transcoding bits
3075  *   - transcoder
3076  */
3077 static void ironlake_pch_enable(struct drm_crtc *crtc)
3078 {
3079         struct drm_device *dev = crtc->dev;
3080         struct drm_i915_private *dev_priv = dev->dev_private;
3081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3082         int pipe = intel_crtc->pipe;
3083         u32 reg, temp;
3084
3085         assert_transcoder_disabled(dev_priv, pipe);
3086
3087         /* Write the TU size bits before fdi link training, so that error
3088          * detection works. */
3089         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3090                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3091
3092         /* For PCH output, training FDI link */
3093         dev_priv->display.fdi_link_train(crtc);
3094
3095         /* XXX: pch pll's can be enabled any time before we enable the PCH
3096          * transcoder, and we actually should do this to not upset any PCH
3097          * transcoder that already use the clock when we share it.
3098          *
3099          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3100          * unconditionally resets the pll - we need that to have the right LVDS
3101          * enable sequence. */
3102         ironlake_enable_pch_pll(intel_crtc);
3103
3104         if (HAS_PCH_CPT(dev)) {
3105                 u32 sel;
3106
3107                 temp = I915_READ(PCH_DPLL_SEL);
3108                 switch (pipe) {
3109                 default:
3110                 case 0:
3111                         temp |= TRANSA_DPLL_ENABLE;
3112                         sel = TRANSA_DPLLB_SEL;
3113                         break;
3114                 case 1:
3115                         temp |= TRANSB_DPLL_ENABLE;
3116                         sel = TRANSB_DPLLB_SEL;
3117                         break;
3118                 case 2:
3119                         temp |= TRANSC_DPLL_ENABLE;
3120                         sel = TRANSC_DPLLB_SEL;
3121                         break;
3122                 }
3123                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3124                         temp |= sel;
3125                 else
3126                         temp &= ~sel;
3127                 I915_WRITE(PCH_DPLL_SEL, temp);
3128         }
3129
3130         /* set transcoder timing, panel must allow it */
3131         assert_panel_unlocked(dev_priv, pipe);
3132         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3133         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3134         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3135
3136         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3137         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3138         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3139         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3140
3141         intel_fdi_normal_train(crtc);
3142
3143         /* For PCH DP, enable TRANS_DP_CTL */
3144         if (HAS_PCH_CPT(dev) &&
3145             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3146              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3147                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3148                 reg = TRANS_DP_CTL(pipe);
3149                 temp = I915_READ(reg);
3150                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3151                           TRANS_DP_SYNC_MASK |
3152                           TRANS_DP_BPC_MASK);
3153                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3154                          TRANS_DP_ENH_FRAMING);
3155                 temp |= bpc << 9; /* same format but at 11:9 */
3156
3157                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3158                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3159                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3160                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3161
3162                 switch (intel_trans_dp_port_sel(crtc)) {
3163                 case PCH_DP_B:
3164                         temp |= TRANS_DP_PORT_SEL_B;
3165                         break;
3166                 case PCH_DP_C:
3167                         temp |= TRANS_DP_PORT_SEL_C;
3168                         break;
3169                 case PCH_DP_D:
3170                         temp |= TRANS_DP_PORT_SEL_D;
3171                         break;
3172                 default:
3173                         BUG();
3174                 }
3175
3176                 I915_WRITE(reg, temp);
3177         }
3178
3179         ironlake_enable_pch_transcoder(dev_priv, pipe);
3180 }
3181
3182 static void lpt_pch_enable(struct drm_crtc *crtc)
3183 {
3184         struct drm_device *dev = crtc->dev;
3185         struct drm_i915_private *dev_priv = dev->dev_private;
3186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3188
3189         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3190
3191         lpt_program_iclkip(crtc);
3192
3193         /* Set transcoder timing. */
3194         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3195         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3196         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3197
3198         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3199         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3200         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3201         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3202
3203         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3204 }
3205
3206 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3207 {
3208         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3209
3210         if (pll == NULL)
3211                 return;
3212
3213         if (pll->refcount == 0) {
3214                 WARN(1, "bad PCH PLL refcount\n");
3215                 return;
3216         }
3217
3218         --pll->refcount;
3219         intel_crtc->pch_pll = NULL;
3220 }
3221
3222 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3223 {
3224         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3225         struct intel_pch_pll *pll;
3226         int i;
3227
3228         pll = intel_crtc->pch_pll;
3229         if (pll) {
3230                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3231                               intel_crtc->base.base.id, pll->pll_reg);
3232                 goto prepare;
3233         }
3234
3235         if (HAS_PCH_IBX(dev_priv->dev)) {
3236                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3237                 i = intel_crtc->pipe;
3238                 pll = &dev_priv->pch_plls[i];
3239
3240                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3241                               intel_crtc->base.base.id, pll->pll_reg);
3242
3243                 goto found;
3244         }
3245
3246         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3247                 pll = &dev_priv->pch_plls[i];
3248
3249                 /* Only want to check enabled timings first */
3250                 if (pll->refcount == 0)
3251                         continue;
3252
3253                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3254                     fp == I915_READ(pll->fp0_reg)) {
3255                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3256                                       intel_crtc->base.base.id,
3257                                       pll->pll_reg, pll->refcount, pll->active);
3258
3259                         goto found;
3260                 }
3261         }
3262
3263         /* Ok no matching timings, maybe there's a free one? */
3264         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3265                 pll = &dev_priv->pch_plls[i];
3266                 if (pll->refcount == 0) {
3267                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3268                                       intel_crtc->base.base.id, pll->pll_reg);
3269                         goto found;
3270                 }
3271         }
3272
3273         return NULL;
3274
3275 found:
3276         intel_crtc->pch_pll = pll;
3277         pll->refcount++;
3278         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3279 prepare: /* separate function? */
3280         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3281
3282         /* Wait for the clocks to stabilize before rewriting the regs */
3283         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3284         POSTING_READ(pll->pll_reg);
3285         udelay(150);
3286
3287         I915_WRITE(pll->fp0_reg, fp);
3288         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3289         pll->on = false;
3290         return pll;
3291 }
3292
3293 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3294 {
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296         int dslreg = PIPEDSL(pipe);
3297         u32 temp;
3298
3299         temp = I915_READ(dslreg);
3300         udelay(500);
3301         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3302                 if (wait_for(I915_READ(dslreg) != temp, 5))
3303                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3304         }
3305 }
3306
3307 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3308 {
3309         struct drm_device *dev = crtc->dev;
3310         struct drm_i915_private *dev_priv = dev->dev_private;
3311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312         struct intel_encoder *encoder;
3313         int pipe = intel_crtc->pipe;
3314         int plane = intel_crtc->plane;
3315         u32 temp;
3316         bool is_pch_port;
3317
3318         WARN_ON(!crtc->enabled);
3319
3320         if (intel_crtc->active)
3321                 return;
3322
3323         intel_crtc->active = true;
3324         intel_update_watermarks(dev);
3325
3326         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3327                 temp = I915_READ(PCH_LVDS);
3328                 if ((temp & LVDS_PORT_EN) == 0)
3329                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3330         }
3331
3332         is_pch_port = ironlake_crtc_driving_pch(crtc);
3333
3334         if (is_pch_port) {
3335                 /* Note: FDI PLL enabling _must_ be done before we enable the
3336                  * cpu pipes, hence this is separate from all the other fdi/pch
3337                  * enabling. */
3338                 ironlake_fdi_pll_enable(intel_crtc);
3339         } else {
3340                 assert_fdi_tx_disabled(dev_priv, pipe);
3341                 assert_fdi_rx_disabled(dev_priv, pipe);
3342         }
3343
3344         for_each_encoder_on_crtc(dev, crtc, encoder)
3345                 if (encoder->pre_enable)
3346                         encoder->pre_enable(encoder);
3347
3348         /* Enable panel fitting for LVDS */
3349         if (dev_priv->pch_pf_size &&
3350             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3351              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3352                 /* Force use of hard-coded filter coefficients
3353                  * as some pre-programmed values are broken,
3354                  * e.g. x201.
3355                  */
3356                 if (IS_IVYBRIDGE(dev))
3357                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3358                                                  PF_PIPE_SEL_IVB(pipe));
3359                 else
3360                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3361                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3362                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3363         }
3364
3365         /*
3366          * On ILK+ LUT must be loaded before the pipe is running but with
3367          * clocks enabled
3368          */
3369         intel_crtc_load_lut(crtc);
3370
3371         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3372         intel_enable_plane(dev_priv, plane, pipe);
3373
3374         if (is_pch_port)
3375                 ironlake_pch_enable(crtc);
3376
3377         mutex_lock(&dev->struct_mutex);
3378         intel_update_fbc(dev);
3379         mutex_unlock(&dev->struct_mutex);
3380
3381         intel_crtc_update_cursor(crtc, true);
3382
3383         for_each_encoder_on_crtc(dev, crtc, encoder)
3384                 encoder->enable(encoder);
3385
3386         if (HAS_PCH_CPT(dev))
3387                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3388
3389         /*
3390          * There seems to be a race in PCH platform hw (at least on some
3391          * outputs) where an enabled pipe still completes any pageflip right
3392          * away (as if the pipe is off) instead of waiting for vblank. As soon
3393          * as the first vblank happend, everything works as expected. Hence just
3394          * wait for one vblank before returning to avoid strange things
3395          * happening.
3396          */
3397         intel_wait_for_vblank(dev, intel_crtc->pipe);
3398 }
3399
3400 static void haswell_crtc_enable(struct drm_crtc *crtc)
3401 {
3402         struct drm_device *dev = crtc->dev;
3403         struct drm_i915_private *dev_priv = dev->dev_private;
3404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3405         struct intel_encoder *encoder;
3406         int pipe = intel_crtc->pipe;
3407         int plane = intel_crtc->plane;
3408         bool is_pch_port;
3409
3410         WARN_ON(!crtc->enabled);
3411
3412         if (intel_crtc->active)
3413                 return;
3414
3415         intel_crtc->active = true;
3416         intel_update_watermarks(dev);
3417
3418         is_pch_port = haswell_crtc_driving_pch(crtc);
3419
3420         if (is_pch_port)
3421                 dev_priv->display.fdi_link_train(crtc);
3422
3423         for_each_encoder_on_crtc(dev, crtc, encoder)
3424                 if (encoder->pre_enable)
3425                         encoder->pre_enable(encoder);
3426
3427         intel_ddi_enable_pipe_clock(intel_crtc);
3428
3429         /* Enable panel fitting for eDP */
3430         if (dev_priv->pch_pf_size &&
3431             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3432                 /* Force use of hard-coded filter coefficients
3433                  * as some pre-programmed values are broken,
3434                  * e.g. x201.
3435                  */
3436                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3437                                          PF_PIPE_SEL_IVB(pipe));
3438                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3439                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3440         }
3441
3442         /*
3443          * On ILK+ LUT must be loaded before the pipe is running but with
3444          * clocks enabled
3445          */
3446         intel_crtc_load_lut(crtc);
3447
3448         intel_ddi_set_pipe_settings(crtc);
3449         intel_ddi_enable_pipe_func(crtc);
3450
3451         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3452         intel_enable_plane(dev_priv, plane, pipe);
3453
3454         if (is_pch_port)
3455                 lpt_pch_enable(crtc);
3456
3457         mutex_lock(&dev->struct_mutex);
3458         intel_update_fbc(dev);
3459         mutex_unlock(&dev->struct_mutex);
3460
3461         intel_crtc_update_cursor(crtc, true);
3462
3463         for_each_encoder_on_crtc(dev, crtc, encoder)
3464                 encoder->enable(encoder);
3465
3466         /*
3467          * There seems to be a race in PCH platform hw (at least on some
3468          * outputs) where an enabled pipe still completes any pageflip right
3469          * away (as if the pipe is off) instead of waiting for vblank. As soon
3470          * as the first vblank happend, everything works as expected. Hence just
3471          * wait for one vblank before returning to avoid strange things
3472          * happening.
3473          */
3474         intel_wait_for_vblank(dev, intel_crtc->pipe);
3475 }
3476
3477 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3478 {
3479         struct drm_device *dev = crtc->dev;
3480         struct drm_i915_private *dev_priv = dev->dev_private;
3481         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3482         struct intel_encoder *encoder;
3483         int pipe = intel_crtc->pipe;
3484         int plane = intel_crtc->plane;
3485         u32 reg, temp;
3486
3487
3488         if (!intel_crtc->active)
3489                 return;
3490
3491         for_each_encoder_on_crtc(dev, crtc, encoder)
3492                 encoder->disable(encoder);
3493
3494         intel_crtc_wait_for_pending_flips(crtc);
3495         drm_vblank_off(dev, pipe);
3496         intel_crtc_update_cursor(crtc, false);
3497
3498         intel_disable_plane(dev_priv, plane, pipe);
3499
3500         if (dev_priv->cfb_plane == plane)
3501                 intel_disable_fbc(dev);
3502
3503         intel_disable_pipe(dev_priv, pipe);
3504
3505         /* Disable PF */
3506         I915_WRITE(PF_CTL(pipe), 0);
3507         I915_WRITE(PF_WIN_SZ(pipe), 0);
3508
3509         for_each_encoder_on_crtc(dev, crtc, encoder)
3510                 if (encoder->post_disable)
3511                         encoder->post_disable(encoder);
3512
3513         ironlake_fdi_disable(crtc);
3514
3515         ironlake_disable_pch_transcoder(dev_priv, pipe);
3516
3517         if (HAS_PCH_CPT(dev)) {
3518                 /* disable TRANS_DP_CTL */
3519                 reg = TRANS_DP_CTL(pipe);
3520                 temp = I915_READ(reg);
3521                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3522                 temp |= TRANS_DP_PORT_SEL_NONE;
3523                 I915_WRITE(reg, temp);
3524
3525                 /* disable DPLL_SEL */
3526                 temp = I915_READ(PCH_DPLL_SEL);
3527                 switch (pipe) {
3528                 case 0:
3529                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3530                         break;
3531                 case 1:
3532                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3533                         break;
3534                 case 2:
3535                         /* C shares PLL A or B */
3536                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3537                         break;
3538                 default:
3539                         BUG(); /* wtf */
3540                 }
3541                 I915_WRITE(PCH_DPLL_SEL, temp);
3542         }
3543
3544         /* disable PCH DPLL */
3545         intel_disable_pch_pll(intel_crtc);
3546
3547         ironlake_fdi_pll_disable(intel_crtc);
3548
3549         intel_crtc->active = false;
3550         intel_update_watermarks(dev);
3551
3552         mutex_lock(&dev->struct_mutex);
3553         intel_update_fbc(dev);
3554         mutex_unlock(&dev->struct_mutex);
3555 }
3556
3557 static void haswell_crtc_disable(struct drm_crtc *crtc)
3558 {
3559         struct drm_device *dev = crtc->dev;
3560         struct drm_i915_private *dev_priv = dev->dev_private;
3561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562         struct intel_encoder *encoder;
3563         int pipe = intel_crtc->pipe;
3564         int plane = intel_crtc->plane;
3565         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3566         bool is_pch_port;
3567
3568         if (!intel_crtc->active)
3569                 return;
3570
3571         is_pch_port = haswell_crtc_driving_pch(crtc);
3572
3573         for_each_encoder_on_crtc(dev, crtc, encoder)
3574                 encoder->disable(encoder);
3575
3576         intel_crtc_wait_for_pending_flips(crtc);
3577         drm_vblank_off(dev, pipe);
3578         intel_crtc_update_cursor(crtc, false);
3579
3580         intel_disable_plane(dev_priv, plane, pipe);
3581
3582         if (dev_priv->cfb_plane == plane)
3583                 intel_disable_fbc(dev);
3584
3585         intel_disable_pipe(dev_priv, pipe);
3586
3587         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3588
3589         /* Disable PF */
3590         I915_WRITE(PF_CTL(pipe), 0);
3591         I915_WRITE(PF_WIN_SZ(pipe), 0);
3592
3593         intel_ddi_disable_pipe_clock(intel_crtc);
3594
3595         for_each_encoder_on_crtc(dev, crtc, encoder)
3596                 if (encoder->post_disable)
3597                         encoder->post_disable(encoder);
3598
3599         if (is_pch_port) {
3600                 lpt_disable_pch_transcoder(dev_priv);
3601                 intel_ddi_fdi_disable(crtc);
3602         }
3603
3604         intel_crtc->active = false;
3605         intel_update_watermarks(dev);
3606
3607         mutex_lock(&dev->struct_mutex);
3608         intel_update_fbc(dev);
3609         mutex_unlock(&dev->struct_mutex);
3610 }
3611
3612 static void ironlake_crtc_off(struct drm_crtc *crtc)
3613 {
3614         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615         intel_put_pch_pll(intel_crtc);
3616 }
3617
3618 static void haswell_crtc_off(struct drm_crtc *crtc)
3619 {
3620         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621
3622         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3623          * start using it. */
3624         intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3625
3626         intel_ddi_put_crtc_pll(crtc);
3627 }
3628
3629 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3630 {
3631         if (!enable && intel_crtc->overlay) {
3632                 struct drm_device *dev = intel_crtc->base.dev;
3633                 struct drm_i915_private *dev_priv = dev->dev_private;
3634
3635                 mutex_lock(&dev->struct_mutex);
3636                 dev_priv->mm.interruptible = false;
3637                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3638                 dev_priv->mm.interruptible = true;
3639                 mutex_unlock(&dev->struct_mutex);
3640         }
3641
3642         /* Let userspace switch the overlay on again. In most cases userspace
3643          * has to recompute where to put it anyway.
3644          */
3645 }
3646
3647 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3648 {
3649         struct drm_device *dev = crtc->dev;
3650         struct drm_i915_private *dev_priv = dev->dev_private;
3651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652         struct intel_encoder *encoder;
3653         int pipe = intel_crtc->pipe;
3654         int plane = intel_crtc->plane;
3655
3656         WARN_ON(!crtc->enabled);
3657
3658         if (intel_crtc->active)
3659                 return;
3660
3661         intel_crtc->active = true;
3662         intel_update_watermarks(dev);
3663
3664         intel_enable_pll(dev_priv, pipe);
3665
3666         for_each_encoder_on_crtc(dev, crtc, encoder)
3667                 if (encoder->pre_enable)
3668                         encoder->pre_enable(encoder);
3669
3670         intel_enable_pipe(dev_priv, pipe, false);
3671         intel_enable_plane(dev_priv, plane, pipe);
3672
3673         intel_crtc_load_lut(crtc);
3674         intel_update_fbc(dev);
3675
3676         /* Give the overlay scaler a chance to enable if it's on this pipe */
3677         intel_crtc_dpms_overlay(intel_crtc, true);
3678         intel_crtc_update_cursor(crtc, true);
3679
3680         for_each_encoder_on_crtc(dev, crtc, encoder)
3681                 encoder->enable(encoder);
3682 }
3683
3684 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3685 {
3686         struct drm_device *dev = crtc->dev;
3687         struct drm_i915_private *dev_priv = dev->dev_private;
3688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689         struct intel_encoder *encoder;
3690         int pipe = intel_crtc->pipe;
3691         int plane = intel_crtc->plane;
3692         u32 pctl;
3693
3694
3695         if (!intel_crtc->active)
3696                 return;
3697
3698         for_each_encoder_on_crtc(dev, crtc, encoder)
3699                 encoder->disable(encoder);
3700
3701         /* Give the overlay scaler a chance to disable if it's on this pipe */
3702         intel_crtc_wait_for_pending_flips(crtc);
3703         drm_vblank_off(dev, pipe);
3704         intel_crtc_dpms_overlay(intel_crtc, false);
3705         intel_crtc_update_cursor(crtc, false);
3706
3707         if (dev_priv->cfb_plane == plane)
3708                 intel_disable_fbc(dev);
3709
3710         intel_disable_plane(dev_priv, plane, pipe);
3711         intel_disable_pipe(dev_priv, pipe);
3712
3713         /* Disable pannel fitter if it is on this pipe. */
3714         pctl = I915_READ(PFIT_CONTROL);
3715         if ((pctl & PFIT_ENABLE) &&
3716             ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3717                 I915_WRITE(PFIT_CONTROL, 0);
3718
3719         intel_disable_pll(dev_priv, pipe);
3720
3721         intel_crtc->active = false;
3722         intel_update_fbc(dev);
3723         intel_update_watermarks(dev);
3724 }
3725
3726 static void i9xx_crtc_off(struct drm_crtc *crtc)
3727 {
3728 }
3729
3730 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3731                                     bool enabled)
3732 {
3733         struct drm_device *dev = crtc->dev;
3734         struct drm_i915_master_private *master_priv;
3735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3736         int pipe = intel_crtc->pipe;
3737
3738         if (!dev->primary->master)
3739                 return;
3740
3741         master_priv = dev->primary->master->driver_priv;
3742         if (!master_priv->sarea_priv)
3743                 return;
3744
3745         switch (pipe) {
3746         case 0:
3747                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3748                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3749                 break;
3750         case 1:
3751                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3752                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3753                 break;
3754         default:
3755                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3756                 break;
3757         }
3758 }
3759
3760 /**
3761  * Sets the power management mode of the pipe and plane.
3762  */
3763 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3764 {
3765         struct drm_device *dev = crtc->dev;
3766         struct drm_i915_private *dev_priv = dev->dev_private;
3767         struct intel_encoder *intel_encoder;
3768         bool enable = false;
3769
3770         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3771                 enable |= intel_encoder->connectors_active;
3772
3773         if (enable)
3774                 dev_priv->display.crtc_enable(crtc);
3775         else
3776                 dev_priv->display.crtc_disable(crtc);
3777
3778         intel_crtc_update_sarea(crtc, enable);
3779 }
3780
3781 static void intel_crtc_noop(struct drm_crtc *crtc)
3782 {
3783 }
3784
3785 static void intel_crtc_disable(struct drm_crtc *crtc)
3786 {
3787         struct drm_device *dev = crtc->dev;
3788         struct drm_connector *connector;
3789         struct drm_i915_private *dev_priv = dev->dev_private;
3790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3791
3792         /* crtc should still be enabled when we disable it. */
3793         WARN_ON(!crtc->enabled);
3794
3795         intel_crtc->eld_vld = false;
3796         dev_priv->display.crtc_disable(crtc);
3797         intel_crtc_update_sarea(crtc, false);
3798         dev_priv->display.off(crtc);
3799
3800         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3801         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3802
3803         if (crtc->fb) {
3804                 mutex_lock(&dev->struct_mutex);
3805                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3806                 mutex_unlock(&dev->struct_mutex);
3807                 crtc->fb = NULL;
3808         }
3809
3810         /* Update computed state. */
3811         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3812                 if (!connector->encoder || !connector->encoder->crtc)
3813                         continue;
3814
3815                 if (connector->encoder->crtc != crtc)
3816                         continue;
3817
3818                 connector->dpms = DRM_MODE_DPMS_OFF;
3819                 to_intel_encoder(connector->encoder)->connectors_active = false;
3820         }
3821 }
3822
3823 void intel_modeset_disable(struct drm_device *dev)
3824 {
3825         struct drm_crtc *crtc;
3826
3827         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3828                 if (crtc->enabled)
3829                         intel_crtc_disable(crtc);
3830         }
3831 }
3832
3833 void intel_encoder_noop(struct drm_encoder *encoder)
3834 {
3835 }
3836
3837 void intel_encoder_destroy(struct drm_encoder *encoder)
3838 {
3839         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3840
3841         drm_encoder_cleanup(encoder);
3842         kfree(intel_encoder);
3843 }
3844
3845 /* Simple dpms helper for encodres with just one connector, no cloning and only
3846  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3847  * state of the entire output pipe. */
3848 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3849 {
3850         if (mode == DRM_MODE_DPMS_ON) {
3851                 encoder->connectors_active = true;
3852
3853                 intel_crtc_update_dpms(encoder->base.crtc);
3854         } else {
3855                 encoder->connectors_active = false;
3856
3857                 intel_crtc_update_dpms(encoder->base.crtc);
3858         }
3859 }
3860
3861 /* Cross check the actual hw state with our own modeset state tracking (and it's
3862  * internal consistency). */
3863 static void intel_connector_check_state(struct intel_connector *connector)
3864 {
3865         if (connector->get_hw_state(connector)) {
3866                 struct intel_encoder *encoder = connector->encoder;
3867                 struct drm_crtc *crtc;
3868                 bool encoder_enabled;
3869                 enum pipe pipe;
3870
3871                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3872                               connector->base.base.id,
3873                               drm_get_connector_name(&connector->base));
3874
3875                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3876                      "wrong connector dpms state\n");
3877                 WARN(connector->base.encoder != &encoder->base,
3878                      "active connector not linked to encoder\n");
3879                 WARN(!encoder->connectors_active,
3880                      "encoder->connectors_active not set\n");
3881
3882                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3883                 WARN(!encoder_enabled, "encoder not enabled\n");
3884                 if (WARN_ON(!encoder->base.crtc))
3885                         return;
3886
3887                 crtc = encoder->base.crtc;
3888
3889                 WARN(!crtc->enabled, "crtc not enabled\n");
3890                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3891                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3892                      "encoder active on the wrong pipe\n");
3893         }
3894 }
3895
3896 /* Even simpler default implementation, if there's really no special case to
3897  * consider. */
3898 void intel_connector_dpms(struct drm_connector *connector, int mode)
3899 {
3900         struct intel_encoder *encoder = intel_attached_encoder(connector);
3901
3902         /* All the simple cases only support two dpms states. */
3903         if (mode != DRM_MODE_DPMS_ON)
3904                 mode = DRM_MODE_DPMS_OFF;
3905
3906         if (mode == connector->dpms)
3907                 return;
3908
3909         connector->dpms = mode;
3910
3911         /* Only need to change hw state when actually enabled */
3912         if (encoder->base.crtc)
3913                 intel_encoder_dpms(encoder, mode);
3914         else
3915                 WARN_ON(encoder->connectors_active != false);
3916
3917         intel_modeset_check_state(connector->dev);
3918 }
3919
3920 /* Simple connector->get_hw_state implementation for encoders that support only
3921  * one connector and no cloning and hence the encoder state determines the state
3922  * of the connector. */
3923 bool intel_connector_get_hw_state(struct intel_connector *connector)
3924 {
3925         enum pipe pipe = 0;
3926         struct intel_encoder *encoder = connector->encoder;
3927
3928         return encoder->get_hw_state(encoder, &pipe);
3929 }
3930
3931 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3932                                   const struct drm_display_mode *mode,
3933                                   struct drm_display_mode *adjusted_mode)
3934 {
3935         struct drm_device *dev = crtc->dev;
3936
3937         if (HAS_PCH_SPLIT(dev)) {
3938                 /* FDI link clock is fixed at 2.7G */
3939                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3940                         return false;
3941         }
3942
3943         /* All interlaced capable intel hw wants timings in frames. Note though
3944          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3945          * timings, so we need to be careful not to clobber these.*/
3946         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3947                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3948
3949         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3950          * with a hsync front porch of 0.
3951          */
3952         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3953                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3954                 return false;
3955
3956         return true;
3957 }
3958
3959 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3960 {
3961         return 400000; /* FIXME */
3962 }
3963
3964 static int i945_get_display_clock_speed(struct drm_device *dev)
3965 {
3966         return 400000;
3967 }
3968
3969 static int i915_get_display_clock_speed(struct drm_device *dev)
3970 {
3971         return 333000;
3972 }
3973
3974 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3975 {
3976         return 200000;
3977 }
3978
3979 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3980 {
3981         u16 gcfgc = 0;
3982
3983         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3984
3985         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3986                 return 133000;
3987         else {
3988                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3989                 case GC_DISPLAY_CLOCK_333_MHZ:
3990                         return 333000;
3991                 default:
3992                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3993                         return 190000;
3994                 }
3995         }
3996 }
3997
3998 static int i865_get_display_clock_speed(struct drm_device *dev)
3999 {
4000         return 266000;
4001 }
4002
4003 static int i855_get_display_clock_speed(struct drm_device *dev)
4004 {
4005         u16 hpllcc = 0;
4006         /* Assume that the hardware is in the high speed state.  This
4007          * should be the default.
4008          */
4009         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4010         case GC_CLOCK_133_200:
4011         case GC_CLOCK_100_200:
4012                 return 200000;
4013         case GC_CLOCK_166_250:
4014                 return 250000;
4015         case GC_CLOCK_100_133:
4016                 return 133000;
4017         }
4018
4019         /* Shouldn't happen */
4020         return 0;
4021 }
4022
4023 static int i830_get_display_clock_speed(struct drm_device *dev)
4024 {
4025         return 133000;
4026 }
4027
4028 static void
4029 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4030 {
4031         while (*num > 0xffffff || *den > 0xffffff) {
4032                 *num >>= 1;
4033                 *den >>= 1;
4034         }
4035 }
4036
4037 void
4038 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4039                        int pixel_clock, int link_clock,
4040                        struct intel_link_m_n *m_n)
4041 {
4042         m_n->tu = 64;
4043         m_n->gmch_m = bits_per_pixel * pixel_clock;
4044         m_n->gmch_n = link_clock * nlanes * 8;
4045         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4046         m_n->link_m = pixel_clock;
4047         m_n->link_n = link_clock;
4048         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4049 }
4050
4051 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4052 {
4053         if (i915_panel_use_ssc >= 0)
4054                 return i915_panel_use_ssc != 0;
4055         return dev_priv->lvds_use_ssc
4056                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4057 }
4058
4059 /**
4060  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4061  * @crtc: CRTC structure
4062  * @mode: requested mode
4063  *
4064  * A pipe may be connected to one or more outputs.  Based on the depth of the
4065  * attached framebuffer, choose a good color depth to use on the pipe.
4066  *
4067  * If possible, match the pipe depth to the fb depth.  In some cases, this
4068  * isn't ideal, because the connected output supports a lesser or restricted
4069  * set of depths.  Resolve that here:
4070  *    LVDS typically supports only 6bpc, so clamp down in that case
4071  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4072  *    Displays may support a restricted set as well, check EDID and clamp as
4073  *      appropriate.
4074  *    DP may want to dither down to 6bpc to fit larger modes
4075  *
4076  * RETURNS:
4077  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4078  * true if they don't match).
4079  */
4080 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4081                                          struct drm_framebuffer *fb,
4082                                          unsigned int *pipe_bpp,
4083                                          struct drm_display_mode *mode)
4084 {
4085         struct drm_device *dev = crtc->dev;
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct drm_connector *connector;
4088         struct intel_encoder *intel_encoder;
4089         unsigned int display_bpc = UINT_MAX, bpc;
4090
4091         /* Walk the encoders & connectors on this crtc, get min bpc */
4092         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4093
4094                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4095                         unsigned int lvds_bpc;
4096
4097                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4098                             LVDS_A3_POWER_UP)
4099                                 lvds_bpc = 8;
4100                         else
4101                                 lvds_bpc = 6;
4102
4103                         if (lvds_bpc < display_bpc) {
4104                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4105                                 display_bpc = lvds_bpc;
4106                         }
4107                         continue;
4108                 }
4109
4110                 /* Not one of the known troublemakers, check the EDID */
4111                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4112                                     head) {
4113                         if (connector->encoder != &intel_encoder->base)
4114                                 continue;
4115
4116                         /* Don't use an invalid EDID bpc value */
4117                         if (connector->display_info.bpc &&
4118                             connector->display_info.bpc < display_bpc) {
4119                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4120                                 display_bpc = connector->display_info.bpc;
4121                         }
4122                 }
4123
4124                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4125                         /* Use VBT settings if we have an eDP panel */
4126                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4127
4128                         if (edp_bpc && edp_bpc < display_bpc) {
4129                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4130                                 display_bpc = edp_bpc;
4131                         }
4132                         continue;
4133                 }
4134
4135                 /*
4136                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4137                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4138                  */
4139                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4140                         if (display_bpc > 8 && display_bpc < 12) {
4141                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4142                                 display_bpc = 12;
4143                         } else {
4144                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4145                                 display_bpc = 8;
4146                         }
4147                 }
4148         }
4149
4150         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4151                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4152                 display_bpc = 6;
4153         }
4154
4155         /*
4156          * We could just drive the pipe at the highest bpc all the time and
4157          * enable dithering as needed, but that costs bandwidth.  So choose
4158          * the minimum value that expresses the full color range of the fb but
4159          * also stays within the max display bpc discovered above.
4160          */
4161
4162         switch (fb->depth) {
4163         case 8:
4164                 bpc = 8; /* since we go through a colormap */
4165                 break;
4166         case 15:
4167         case 16:
4168                 bpc = 6; /* min is 18bpp */
4169                 break;
4170         case 24:
4171                 bpc = 8;
4172                 break;
4173         case 30:
4174                 bpc = 10;
4175                 break;
4176         case 48:
4177                 bpc = 12;
4178                 break;
4179         default:
4180                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4181                 bpc = min((unsigned int)8, display_bpc);
4182                 break;
4183         }
4184
4185         display_bpc = min(display_bpc, bpc);
4186
4187         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4188                       bpc, display_bpc);
4189
4190         *pipe_bpp = display_bpc * 3;
4191
4192         return display_bpc != bpc;
4193 }
4194
4195 static int vlv_get_refclk(struct drm_crtc *crtc)
4196 {
4197         struct drm_device *dev = crtc->dev;
4198         struct drm_i915_private *dev_priv = dev->dev_private;
4199         int refclk = 27000; /* for DP & HDMI */
4200
4201         return 100000; /* only one validated so far */
4202
4203         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4204                 refclk = 96000;
4205         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4206                 if (intel_panel_use_ssc(dev_priv))
4207                         refclk = 100000;
4208                 else
4209                         refclk = 96000;
4210         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4211                 refclk = 100000;
4212         }
4213
4214         return refclk;
4215 }
4216
4217 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4218 {
4219         struct drm_device *dev = crtc->dev;
4220         struct drm_i915_private *dev_priv = dev->dev_private;
4221         int refclk;
4222
4223         if (IS_VALLEYVIEW(dev)) {
4224                 refclk = vlv_get_refclk(crtc);
4225         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4226             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4227                 refclk = dev_priv->lvds_ssc_freq * 1000;
4228                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4229                               refclk / 1000);
4230         } else if (!IS_GEN2(dev)) {
4231                 refclk = 96000;
4232         } else {
4233                 refclk = 48000;
4234         }
4235
4236         return refclk;
4237 }
4238
4239 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4240                                       intel_clock_t *clock)
4241 {
4242         /* SDVO TV has fixed PLL values depend on its clock range,
4243            this mirrors vbios setting. */
4244         if (adjusted_mode->clock >= 100000
4245             && adjusted_mode->clock < 140500) {
4246                 clock->p1 = 2;
4247                 clock->p2 = 10;
4248                 clock->n = 3;
4249                 clock->m1 = 16;
4250                 clock->m2 = 8;
4251         } else if (adjusted_mode->clock >= 140500
4252                    && adjusted_mode->clock <= 200000) {
4253                 clock->p1 = 1;
4254                 clock->p2 = 10;
4255                 clock->n = 6;
4256                 clock->m1 = 12;
4257                 clock->m2 = 8;
4258         }
4259 }
4260
4261 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4262                                      intel_clock_t *clock,
4263                                      intel_clock_t *reduced_clock)
4264 {
4265         struct drm_device *dev = crtc->dev;
4266         struct drm_i915_private *dev_priv = dev->dev_private;
4267         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4268         int pipe = intel_crtc->pipe;
4269         u32 fp, fp2 = 0;
4270
4271         if (IS_PINEVIEW(dev)) {
4272                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4273                 if (reduced_clock)
4274                         fp2 = (1 << reduced_clock->n) << 16 |
4275                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4276         } else {
4277                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4278                 if (reduced_clock)
4279                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4280                                 reduced_clock->m2;
4281         }
4282
4283         I915_WRITE(FP0(pipe), fp);
4284
4285         intel_crtc->lowfreq_avail = false;
4286         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4287             reduced_clock && i915_powersave) {
4288                 I915_WRITE(FP1(pipe), fp2);
4289                 intel_crtc->lowfreq_avail = true;
4290         } else {
4291                 I915_WRITE(FP1(pipe), fp);
4292         }
4293 }
4294
4295 static void vlv_update_pll(struct drm_crtc *crtc,
4296                            struct drm_display_mode *mode,
4297                            struct drm_display_mode *adjusted_mode,
4298                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4299                            int num_connectors)
4300 {
4301         struct drm_device *dev = crtc->dev;
4302         struct drm_i915_private *dev_priv = dev->dev_private;
4303         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4304         int pipe = intel_crtc->pipe;
4305         u32 dpll, mdiv, pdiv;
4306         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4307         bool is_sdvo;
4308         u32 temp;
4309
4310         mutex_lock(&dev_priv->dpio_lock);
4311
4312         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4313                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4314
4315         dpll = DPLL_VGA_MODE_DIS;
4316         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4317         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4318         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4319
4320         I915_WRITE(DPLL(pipe), dpll);
4321         POSTING_READ(DPLL(pipe));
4322
4323         bestn = clock->n;
4324         bestm1 = clock->m1;
4325         bestm2 = clock->m2;
4326         bestp1 = clock->p1;
4327         bestp2 = clock->p2;
4328
4329         /*
4330          * In Valleyview PLL and program lane counter registers are exposed
4331          * through DPIO interface
4332          */
4333         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4334         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4335         mdiv |= ((bestn << DPIO_N_SHIFT));
4336         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4337         mdiv |= (1 << DPIO_K_SHIFT);
4338         mdiv |= DPIO_ENABLE_CALIBRATION;
4339         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4340
4341         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4342
4343         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4344                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4345                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4346                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4347         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4348
4349         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4350
4351         dpll |= DPLL_VCO_ENABLE;
4352         I915_WRITE(DPLL(pipe), dpll);
4353         POSTING_READ(DPLL(pipe));
4354         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4355                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4356
4357         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4358
4359         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4360                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4361
4362         I915_WRITE(DPLL(pipe), dpll);
4363
4364         /* Wait for the clocks to stabilize. */
4365         POSTING_READ(DPLL(pipe));
4366         udelay(150);
4367
4368         temp = 0;
4369         if (is_sdvo) {
4370                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4371                 if (temp > 1)
4372                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4373                 else
4374                         temp = 0;
4375         }
4376         I915_WRITE(DPLL_MD(pipe), temp);
4377         POSTING_READ(DPLL_MD(pipe));
4378
4379         /* Now program lane control registers */
4380         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4381                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4382         {
4383                 temp = 0x1000C4;
4384                 if(pipe == 1)
4385                         temp |= (1 << 21);
4386                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4387         }
4388         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4389         {
4390                 temp = 0x1000C4;
4391                 if(pipe == 1)
4392                         temp |= (1 << 21);
4393                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4394         }
4395
4396         mutex_unlock(&dev_priv->dpio_lock);
4397 }
4398
4399 static void i9xx_update_pll(struct drm_crtc *crtc,
4400                             struct drm_display_mode *mode,
4401                             struct drm_display_mode *adjusted_mode,
4402                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4403                             int num_connectors)
4404 {
4405         struct drm_device *dev = crtc->dev;
4406         struct drm_i915_private *dev_priv = dev->dev_private;
4407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4408         struct intel_encoder *encoder;
4409         int pipe = intel_crtc->pipe;
4410         u32 dpll;
4411         bool is_sdvo;
4412
4413         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4414
4415         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4416                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4417
4418         dpll = DPLL_VGA_MODE_DIS;
4419
4420         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4421                 dpll |= DPLLB_MODE_LVDS;
4422         else
4423                 dpll |= DPLLB_MODE_DAC_SERIAL;
4424         if (is_sdvo) {
4425                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4426                 if (pixel_multiplier > 1) {
4427                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4428                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4429                 }
4430                 dpll |= DPLL_DVO_HIGH_SPEED;
4431         }
4432         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4433                 dpll |= DPLL_DVO_HIGH_SPEED;
4434
4435         /* compute bitmask from p1 value */
4436         if (IS_PINEVIEW(dev))
4437                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4438         else {
4439                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4440                 if (IS_G4X(dev) && reduced_clock)
4441                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4442         }
4443         switch (clock->p2) {
4444         case 5:
4445                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4446                 break;
4447         case 7:
4448                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4449                 break;
4450         case 10:
4451                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4452                 break;
4453         case 14:
4454                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4455                 break;
4456         }
4457         if (INTEL_INFO(dev)->gen >= 4)
4458                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4459
4460         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4461                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4462         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4463                 /* XXX: just matching BIOS for now */
4464                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4465                 dpll |= 3;
4466         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4467                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4468                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4469         else
4470                 dpll |= PLL_REF_INPUT_DREFCLK;
4471
4472         dpll |= DPLL_VCO_ENABLE;
4473         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4474         POSTING_READ(DPLL(pipe));
4475         udelay(150);
4476
4477         for_each_encoder_on_crtc(dev, crtc, encoder)
4478                 if (encoder->pre_pll_enable)
4479                         encoder->pre_pll_enable(encoder);
4480
4481         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4482                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4483
4484         I915_WRITE(DPLL(pipe), dpll);
4485
4486         /* Wait for the clocks to stabilize. */
4487         POSTING_READ(DPLL(pipe));
4488         udelay(150);
4489
4490         if (INTEL_INFO(dev)->gen >= 4) {
4491                 u32 temp = 0;
4492                 if (is_sdvo) {
4493                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4494                         if (temp > 1)
4495                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4496                         else
4497                                 temp = 0;
4498                 }
4499                 I915_WRITE(DPLL_MD(pipe), temp);
4500         } else {
4501                 /* The pixel multiplier can only be updated once the
4502                  * DPLL is enabled and the clocks are stable.
4503                  *
4504                  * So write it again.
4505                  */
4506                 I915_WRITE(DPLL(pipe), dpll);
4507         }
4508 }
4509
4510 static void i8xx_update_pll(struct drm_crtc *crtc,
4511                             struct drm_display_mode *adjusted_mode,
4512                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4513                             int num_connectors)
4514 {
4515         struct drm_device *dev = crtc->dev;
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518         struct intel_encoder *encoder;
4519         int pipe = intel_crtc->pipe;
4520         u32 dpll;
4521
4522         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4523
4524         dpll = DPLL_VGA_MODE_DIS;
4525
4526         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4527                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4528         } else {
4529                 if (clock->p1 == 2)
4530                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4531                 else
4532                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4533                 if (clock->p2 == 4)
4534                         dpll |= PLL_P2_DIVIDE_BY_4;
4535         }
4536
4537         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4538                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4539                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4540         else
4541                 dpll |= PLL_REF_INPUT_DREFCLK;
4542
4543         dpll |= DPLL_VCO_ENABLE;
4544         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4545         POSTING_READ(DPLL(pipe));
4546         udelay(150);
4547
4548         for_each_encoder_on_crtc(dev, crtc, encoder)
4549                 if (encoder->pre_pll_enable)
4550                         encoder->pre_pll_enable(encoder);
4551
4552         I915_WRITE(DPLL(pipe), dpll);
4553
4554         /* Wait for the clocks to stabilize. */
4555         POSTING_READ(DPLL(pipe));
4556         udelay(150);
4557
4558         /* The pixel multiplier can only be updated once the
4559          * DPLL is enabled and the clocks are stable.
4560          *
4561          * So write it again.
4562          */
4563         I915_WRITE(DPLL(pipe), dpll);
4564 }
4565
4566 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4567                                    struct drm_display_mode *mode,
4568                                    struct drm_display_mode *adjusted_mode)
4569 {
4570         struct drm_device *dev = intel_crtc->base.dev;
4571         struct drm_i915_private *dev_priv = dev->dev_private;
4572         enum pipe pipe = intel_crtc->pipe;
4573         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4574         uint32_t vsyncshift;
4575
4576         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4577                 /* the chip adds 2 halflines automatically */
4578                 adjusted_mode->crtc_vtotal -= 1;
4579                 adjusted_mode->crtc_vblank_end -= 1;
4580                 vsyncshift = adjusted_mode->crtc_hsync_start
4581                              - adjusted_mode->crtc_htotal / 2;
4582         } else {
4583                 vsyncshift = 0;
4584         }
4585
4586         if (INTEL_INFO(dev)->gen > 3)
4587                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4588
4589         I915_WRITE(HTOTAL(cpu_transcoder),
4590                    (adjusted_mode->crtc_hdisplay - 1) |
4591                    ((adjusted_mode->crtc_htotal - 1) << 16));
4592         I915_WRITE(HBLANK(cpu_transcoder),
4593                    (adjusted_mode->crtc_hblank_start - 1) |
4594                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4595         I915_WRITE(HSYNC(cpu_transcoder),
4596                    (adjusted_mode->crtc_hsync_start - 1) |
4597                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4598
4599         I915_WRITE(VTOTAL(cpu_transcoder),
4600                    (adjusted_mode->crtc_vdisplay - 1) |
4601                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4602         I915_WRITE(VBLANK(cpu_transcoder),
4603                    (adjusted_mode->crtc_vblank_start - 1) |
4604                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4605         I915_WRITE(VSYNC(cpu_transcoder),
4606                    (adjusted_mode->crtc_vsync_start - 1) |
4607                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4608
4609         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4610          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4611          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4612          * bits. */
4613         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4614             (pipe == PIPE_B || pipe == PIPE_C))
4615                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4616
4617         /* pipesrc controls the size that is scaled from, which should
4618          * always be the user's requested size.
4619          */
4620         I915_WRITE(PIPESRC(pipe),
4621                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4622 }
4623
4624 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4625                               struct drm_display_mode *mode,
4626                               struct drm_display_mode *adjusted_mode,
4627                               int x, int y,
4628                               struct drm_framebuffer *fb)
4629 {
4630         struct drm_device *dev = crtc->dev;
4631         struct drm_i915_private *dev_priv = dev->dev_private;
4632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4633         int pipe = intel_crtc->pipe;
4634         int plane = intel_crtc->plane;
4635         int refclk, num_connectors = 0;
4636         intel_clock_t clock, reduced_clock;
4637         u32 dspcntr, pipeconf;
4638         bool ok, has_reduced_clock = false, is_sdvo = false;
4639         bool is_lvds = false, is_tv = false, is_dp = false;
4640         struct intel_encoder *encoder;
4641         const intel_limit_t *limit;
4642         int ret;
4643
4644         for_each_encoder_on_crtc(dev, crtc, encoder) {
4645                 switch (encoder->type) {
4646                 case INTEL_OUTPUT_LVDS:
4647                         is_lvds = true;
4648                         break;
4649                 case INTEL_OUTPUT_SDVO:
4650                 case INTEL_OUTPUT_HDMI:
4651                         is_sdvo = true;
4652                         if (encoder->needs_tv_clock)
4653                                 is_tv = true;
4654                         break;
4655                 case INTEL_OUTPUT_TVOUT:
4656                         is_tv = true;
4657                         break;
4658                 case INTEL_OUTPUT_DISPLAYPORT:
4659                         is_dp = true;
4660                         break;
4661                 }
4662
4663                 num_connectors++;
4664         }
4665
4666         refclk = i9xx_get_refclk(crtc, num_connectors);
4667
4668         /*
4669          * Returns a set of divisors for the desired target clock with the given
4670          * refclk, or FALSE.  The returned values represent the clock equation:
4671          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4672          */
4673         limit = intel_limit(crtc, refclk);
4674         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4675                              &clock);
4676         if (!ok) {
4677                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4678                 return -EINVAL;
4679         }
4680
4681         /* Ensure that the cursor is valid for the new mode before changing... */
4682         intel_crtc_update_cursor(crtc, true);
4683
4684         if (is_lvds && dev_priv->lvds_downclock_avail) {
4685                 /*
4686                  * Ensure we match the reduced clock's P to the target clock.
4687                  * If the clocks don't match, we can't switch the display clock
4688                  * by using the FP0/FP1. In such case we will disable the LVDS
4689                  * downclock feature.
4690                 */
4691                 has_reduced_clock = limit->find_pll(limit, crtc,
4692                                                     dev_priv->lvds_downclock,
4693                                                     refclk,
4694                                                     &clock,
4695                                                     &reduced_clock);
4696         }
4697
4698         if (is_sdvo && is_tv)
4699                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4700
4701         if (IS_GEN2(dev))
4702                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4703                                 has_reduced_clock ? &reduced_clock : NULL,
4704                                 num_connectors);
4705         else if (IS_VALLEYVIEW(dev))
4706                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4707                                 has_reduced_clock ? &reduced_clock : NULL,
4708                                 num_connectors);
4709         else
4710                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4711                                 has_reduced_clock ? &reduced_clock : NULL,
4712                                 num_connectors);
4713
4714         /* setup pipeconf */
4715         pipeconf = I915_READ(PIPECONF(pipe));
4716
4717         /* Set up the display plane register */
4718         dspcntr = DISPPLANE_GAMMA_ENABLE;
4719
4720         if (pipe == 0)
4721                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4722         else
4723                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4724
4725         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4726                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4727                  * core speed.
4728                  *
4729                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4730                  * pipe == 0 check?
4731                  */
4732                 if (mode->clock >
4733                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4734                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4735                 else
4736                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4737         }
4738
4739         /* default to 8bpc */
4740         pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4741         if (is_dp) {
4742                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4743                         pipeconf |= PIPECONF_6BPC |
4744                                     PIPECONF_DITHER_EN |
4745                                     PIPECONF_DITHER_TYPE_SP;
4746                 }
4747         }
4748
4749         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4750                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4751                         pipeconf |= PIPECONF_6BPC |
4752                                         PIPECONF_ENABLE |
4753                                         I965_PIPECONF_ACTIVE;
4754                 }
4755         }
4756
4757         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4758         drm_mode_debug_printmodeline(mode);
4759
4760         if (HAS_PIPE_CXSR(dev)) {
4761                 if (intel_crtc->lowfreq_avail) {
4762                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4763                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4764                 } else {
4765                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4766                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4767                 }
4768         }
4769
4770         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4771         if (!IS_GEN2(dev) &&
4772             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4773                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4774         else
4775                 pipeconf |= PIPECONF_PROGRESSIVE;
4776
4777         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4778
4779         /* pipesrc and dspsize control the size that is scaled from,
4780          * which should always be the user's requested size.
4781          */
4782         I915_WRITE(DSPSIZE(plane),
4783                    ((mode->vdisplay - 1) << 16) |
4784                    (mode->hdisplay - 1));
4785         I915_WRITE(DSPPOS(plane), 0);
4786
4787         I915_WRITE(PIPECONF(pipe), pipeconf);
4788         POSTING_READ(PIPECONF(pipe));
4789         intel_enable_pipe(dev_priv, pipe, false);
4790
4791         intel_wait_for_vblank(dev, pipe);
4792
4793         I915_WRITE(DSPCNTR(plane), dspcntr);
4794         POSTING_READ(DSPCNTR(plane));
4795
4796         ret = intel_pipe_set_base(crtc, x, y, fb);
4797
4798         intel_update_watermarks(dev);
4799
4800         return ret;
4801 }
4802
4803 static void ironlake_init_pch_refclk(struct drm_device *dev)
4804 {
4805         struct drm_i915_private *dev_priv = dev->dev_private;
4806         struct drm_mode_config *mode_config = &dev->mode_config;
4807         struct intel_encoder *encoder;
4808         u32 temp;
4809         bool has_lvds = false;
4810         bool has_cpu_edp = false;
4811         bool has_pch_edp = false;
4812         bool has_panel = false;
4813         bool has_ck505 = false;
4814         bool can_ssc = false;
4815
4816         /* We need to take the global config into account */
4817         list_for_each_entry(encoder, &mode_config->encoder_list,
4818                             base.head) {
4819                 switch (encoder->type) {
4820                 case INTEL_OUTPUT_LVDS:
4821                         has_panel = true;
4822                         has_lvds = true;
4823                         break;
4824                 case INTEL_OUTPUT_EDP:
4825                         has_panel = true;
4826                         if (intel_encoder_is_pch_edp(&encoder->base))
4827                                 has_pch_edp = true;
4828                         else
4829                                 has_cpu_edp = true;
4830                         break;
4831                 }
4832         }
4833
4834         if (HAS_PCH_IBX(dev)) {
4835                 has_ck505 = dev_priv->display_clock_mode;
4836                 can_ssc = has_ck505;
4837         } else {
4838                 has_ck505 = false;
4839                 can_ssc = true;
4840         }
4841
4842         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4843                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4844                       has_ck505);
4845
4846         /* Ironlake: try to setup display ref clock before DPLL
4847          * enabling. This is only under driver's control after
4848          * PCH B stepping, previous chipset stepping should be
4849          * ignoring this setting.
4850          */
4851         temp = I915_READ(PCH_DREF_CONTROL);
4852         /* Always enable nonspread source */
4853         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4854
4855         if (has_ck505)
4856                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4857         else
4858                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4859
4860         if (has_panel) {
4861                 temp &= ~DREF_SSC_SOURCE_MASK;
4862                 temp |= DREF_SSC_SOURCE_ENABLE;
4863
4864                 /* SSC must be turned on before enabling the CPU output  */
4865                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4866                         DRM_DEBUG_KMS("Using SSC on panel\n");
4867                         temp |= DREF_SSC1_ENABLE;
4868                 } else
4869                         temp &= ~DREF_SSC1_ENABLE;
4870
4871                 /* Get SSC going before enabling the outputs */
4872                 I915_WRITE(PCH_DREF_CONTROL, temp);
4873                 POSTING_READ(PCH_DREF_CONTROL);
4874                 udelay(200);
4875
4876                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4877
4878                 /* Enable CPU source on CPU attached eDP */
4879                 if (has_cpu_edp) {
4880                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4881                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4882                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4883                         }
4884                         else
4885                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4886                 } else
4887                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4888
4889                 I915_WRITE(PCH_DREF_CONTROL, temp);
4890                 POSTING_READ(PCH_DREF_CONTROL);
4891                 udelay(200);
4892         } else {
4893                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4894
4895                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4896
4897                 /* Turn off CPU output */
4898                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4899
4900                 I915_WRITE(PCH_DREF_CONTROL, temp);
4901                 POSTING_READ(PCH_DREF_CONTROL);
4902                 udelay(200);
4903
4904                 /* Turn off the SSC source */
4905                 temp &= ~DREF_SSC_SOURCE_MASK;
4906                 temp |= DREF_SSC_SOURCE_DISABLE;
4907
4908                 /* Turn off SSC1 */
4909                 temp &= ~ DREF_SSC1_ENABLE;
4910
4911                 I915_WRITE(PCH_DREF_CONTROL, temp);
4912                 POSTING_READ(PCH_DREF_CONTROL);
4913                 udelay(200);
4914         }
4915 }
4916
4917 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4918 static void lpt_init_pch_refclk(struct drm_device *dev)
4919 {
4920         struct drm_i915_private *dev_priv = dev->dev_private;
4921         struct drm_mode_config *mode_config = &dev->mode_config;
4922         struct intel_encoder *encoder;
4923         bool has_vga = false;
4924         bool is_sdv = false;
4925         u32 tmp;
4926
4927         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4928                 switch (encoder->type) {
4929                 case INTEL_OUTPUT_ANALOG:
4930                         has_vga = true;
4931                         break;
4932                 }
4933         }
4934
4935         if (!has_vga)
4936                 return;
4937
4938         mutex_lock(&dev_priv->dpio_lock);
4939
4940         /* XXX: Rip out SDV support once Haswell ships for real. */
4941         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4942                 is_sdv = true;
4943
4944         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4945         tmp &= ~SBI_SSCCTL_DISABLE;
4946         tmp |= SBI_SSCCTL_PATHALT;
4947         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4948
4949         udelay(24);
4950
4951         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4952         tmp &= ~SBI_SSCCTL_PATHALT;
4953         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4954
4955         if (!is_sdv) {
4956                 tmp = I915_READ(SOUTH_CHICKEN2);
4957                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4958                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4959
4960                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4961                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4962                         DRM_ERROR("FDI mPHY reset assert timeout\n");
4963
4964                 tmp = I915_READ(SOUTH_CHICKEN2);
4965                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4966                 I915_WRITE(SOUTH_CHICKEN2, tmp);
4967
4968                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4969                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4970                                        100))
4971                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4972         }
4973
4974         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4975         tmp &= ~(0xFF << 24);
4976         tmp |= (0x12 << 24);
4977         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4978
4979         if (!is_sdv) {
4980                 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4981                 tmp &= ~(0x3 << 6);
4982                 tmp |= (1 << 6) | (1 << 0);
4983                 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4984         }
4985
4986         if (is_sdv) {
4987                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4988                 tmp |= 0x7FFF;
4989                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4990         }
4991
4992         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4993         tmp |= (1 << 11);
4994         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4995
4996         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4997         tmp |= (1 << 11);
4998         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4999
5000         if (is_sdv) {
5001                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5002                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5003                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5004
5005                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5006                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5007                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5008
5009                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5010                 tmp |= (0x3F << 8);
5011                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5012
5013                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5014                 tmp |= (0x3F << 8);
5015                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5016         }
5017
5018         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5019         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5020         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5021
5022         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5023         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5024         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5025
5026         if (!is_sdv) {
5027                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5028                 tmp &= ~(7 << 13);
5029                 tmp |= (5 << 13);
5030                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5031
5032                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5033                 tmp &= ~(7 << 13);
5034                 tmp |= (5 << 13);
5035                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5036         }
5037
5038         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5039         tmp &= ~0xFF;
5040         tmp |= 0x1C;
5041         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5042
5043         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5044         tmp &= ~0xFF;
5045         tmp |= 0x1C;
5046         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5047
5048         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5049         tmp &= ~(0xFF << 16);
5050         tmp |= (0x1C << 16);
5051         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5052
5053         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5054         tmp &= ~(0xFF << 16);
5055         tmp |= (0x1C << 16);
5056         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5057
5058         if (!is_sdv) {
5059                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5060                 tmp |= (1 << 27);
5061                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5062
5063                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5064                 tmp |= (1 << 27);
5065                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5066
5067                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5068                 tmp &= ~(0xF << 28);
5069                 tmp |= (4 << 28);
5070                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5071
5072                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5073                 tmp &= ~(0xF << 28);
5074                 tmp |= (4 << 28);
5075                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5076         }
5077
5078         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5079         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5080         tmp |= SBI_DBUFF0_ENABLE;
5081         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5082
5083         mutex_unlock(&dev_priv->dpio_lock);
5084 }
5085
5086 /*
5087  * Initialize reference clocks when the driver loads
5088  */
5089 void intel_init_pch_refclk(struct drm_device *dev)
5090 {
5091         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5092                 ironlake_init_pch_refclk(dev);
5093         else if (HAS_PCH_LPT(dev))
5094                 lpt_init_pch_refclk(dev);
5095 }
5096
5097 static int ironlake_get_refclk(struct drm_crtc *crtc)
5098 {
5099         struct drm_device *dev = crtc->dev;
5100         struct drm_i915_private *dev_priv = dev->dev_private;
5101         struct intel_encoder *encoder;
5102         struct intel_encoder *edp_encoder = NULL;
5103         int num_connectors = 0;
5104         bool is_lvds = false;
5105
5106         for_each_encoder_on_crtc(dev, crtc, encoder) {
5107                 switch (encoder->type) {
5108                 case INTEL_OUTPUT_LVDS:
5109                         is_lvds = true;
5110                         break;
5111                 case INTEL_OUTPUT_EDP:
5112                         edp_encoder = encoder;
5113                         break;
5114                 }
5115                 num_connectors++;
5116         }
5117
5118         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5119                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5120                               dev_priv->lvds_ssc_freq);
5121                 return dev_priv->lvds_ssc_freq * 1000;
5122         }
5123
5124         return 120000;
5125 }
5126
5127 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5128                                   struct drm_display_mode *adjusted_mode,
5129                                   bool dither)
5130 {
5131         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5133         int pipe = intel_crtc->pipe;
5134         uint32_t val;
5135
5136         val = I915_READ(PIPECONF(pipe));
5137
5138         val &= ~PIPECONF_BPC_MASK;
5139         switch (intel_crtc->bpp) {
5140         case 18:
5141                 val |= PIPECONF_6BPC;
5142                 break;
5143         case 24:
5144                 val |= PIPECONF_8BPC;
5145                 break;
5146         case 30:
5147                 val |= PIPECONF_10BPC;
5148                 break;
5149         case 36:
5150                 val |= PIPECONF_12BPC;
5151                 break;
5152         default:
5153                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5154                 BUG();
5155         }
5156
5157         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5158         if (dither)
5159                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5160
5161         val &= ~PIPECONF_INTERLACE_MASK;
5162         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5163                 val |= PIPECONF_INTERLACED_ILK;
5164         else
5165                 val |= PIPECONF_PROGRESSIVE;
5166
5167         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5168                 val |= PIPECONF_COLOR_RANGE_SELECT;
5169         else
5170                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5171
5172         I915_WRITE(PIPECONF(pipe), val);
5173         POSTING_READ(PIPECONF(pipe));
5174 }
5175
5176 /*
5177  * Set up the pipe CSC unit.
5178  *
5179  * Currently only full range RGB to limited range RGB conversion
5180  * is supported, but eventually this should handle various
5181  * RGB<->YCbCr scenarios as well.
5182  */
5183 static void intel_set_pipe_csc(struct drm_crtc *crtc,
5184                                const struct drm_display_mode *adjusted_mode)
5185 {
5186         struct drm_device *dev = crtc->dev;
5187         struct drm_i915_private *dev_priv = dev->dev_private;
5188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189         int pipe = intel_crtc->pipe;
5190         uint16_t coeff = 0x7800; /* 1.0 */
5191
5192         /*
5193          * TODO: Check what kind of values actually come out of the pipe
5194          * with these coeff/postoff values and adjust to get the best
5195          * accuracy. Perhaps we even need to take the bpc value into
5196          * consideration.
5197          */
5198
5199         if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5200                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5201
5202         /*
5203          * GY/GU and RY/RU should be the other way around according
5204          * to BSpec, but reality doesn't agree. Just set them up in
5205          * a way that results in the correct picture.
5206          */
5207         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5208         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5209
5210         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5211         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5212
5213         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5214         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5215
5216         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5217         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5218         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5219
5220         if (INTEL_INFO(dev)->gen > 6) {
5221                 uint16_t postoff = 0;
5222
5223                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5224                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5225
5226                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5227                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5228                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5229
5230                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5231         } else {
5232                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5233
5234                 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5235                         mode |= CSC_BLACK_SCREEN_OFFSET;
5236
5237                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5238         }
5239 }
5240
5241 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5242                                  struct drm_display_mode *adjusted_mode,
5243                                  bool dither)
5244 {
5245         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5246         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5247         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5248         uint32_t val;
5249
5250         val = I915_READ(PIPECONF(cpu_transcoder));
5251
5252         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5253         if (dither)
5254                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5255
5256         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5257         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5258                 val |= PIPECONF_INTERLACED_ILK;
5259         else
5260                 val |= PIPECONF_PROGRESSIVE;
5261
5262         I915_WRITE(PIPECONF(cpu_transcoder), val);
5263         POSTING_READ(PIPECONF(cpu_transcoder));
5264 }
5265
5266 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5267                                     struct drm_display_mode *adjusted_mode,
5268                                     intel_clock_t *clock,
5269                                     bool *has_reduced_clock,
5270                                     intel_clock_t *reduced_clock)
5271 {
5272         struct drm_device *dev = crtc->dev;
5273         struct drm_i915_private *dev_priv = dev->dev_private;
5274         struct intel_encoder *intel_encoder;
5275         int refclk;
5276         const intel_limit_t *limit;
5277         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5278
5279         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5280                 switch (intel_encoder->type) {
5281                 case INTEL_OUTPUT_LVDS:
5282                         is_lvds = true;
5283                         break;
5284                 case INTEL_OUTPUT_SDVO:
5285                 case INTEL_OUTPUT_HDMI:
5286                         is_sdvo = true;
5287                         if (intel_encoder->needs_tv_clock)
5288                                 is_tv = true;
5289                         break;
5290                 case INTEL_OUTPUT_TVOUT:
5291                         is_tv = true;
5292                         break;
5293                 }
5294         }
5295
5296         refclk = ironlake_get_refclk(crtc);
5297
5298         /*
5299          * Returns a set of divisors for the desired target clock with the given
5300          * refclk, or FALSE.  The returned values represent the clock equation:
5301          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5302          */
5303         limit = intel_limit(crtc, refclk);
5304         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5305                               clock);
5306         if (!ret)
5307                 return false;
5308
5309         if (is_lvds && dev_priv->lvds_downclock_avail) {
5310                 /*
5311                  * Ensure we match the reduced clock's P to the target clock.
5312                  * If the clocks don't match, we can't switch the display clock
5313                  * by using the FP0/FP1. In such case we will disable the LVDS
5314                  * downclock feature.
5315                 */
5316                 *has_reduced_clock = limit->find_pll(limit, crtc,
5317                                                      dev_priv->lvds_downclock,
5318                                                      refclk,
5319                                                      clock,
5320                                                      reduced_clock);
5321         }
5322
5323         if (is_sdvo && is_tv)
5324                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5325
5326         return true;
5327 }
5328
5329 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5330 {
5331         struct drm_i915_private *dev_priv = dev->dev_private;
5332         uint32_t temp;
5333
5334         temp = I915_READ(SOUTH_CHICKEN1);
5335         if (temp & FDI_BC_BIFURCATION_SELECT)
5336                 return;
5337
5338         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5339         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5340
5341         temp |= FDI_BC_BIFURCATION_SELECT;
5342         DRM_DEBUG_KMS("enabling fdi C rx\n");
5343         I915_WRITE(SOUTH_CHICKEN1, temp);
5344         POSTING_READ(SOUTH_CHICKEN1);
5345 }
5346
5347 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5348 {
5349         struct drm_device *dev = intel_crtc->base.dev;
5350         struct drm_i915_private *dev_priv = dev->dev_private;
5351         struct intel_crtc *pipe_B_crtc =
5352                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5353
5354         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5355                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5356         if (intel_crtc->fdi_lanes > 4) {
5357                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5358                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5359                 /* Clamp lanes to avoid programming the hw with bogus values. */
5360                 intel_crtc->fdi_lanes = 4;
5361
5362                 return false;
5363         }
5364
5365         if (dev_priv->num_pipe == 2)
5366                 return true;
5367
5368         switch (intel_crtc->pipe) {
5369         case PIPE_A:
5370                 return true;
5371         case PIPE_B:
5372                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5373                     intel_crtc->fdi_lanes > 2) {
5374                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5375                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5376                         /* Clamp lanes to avoid programming the hw with bogus values. */
5377                         intel_crtc->fdi_lanes = 2;
5378
5379                         return false;
5380                 }
5381
5382                 if (intel_crtc->fdi_lanes > 2)
5383                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5384                 else
5385                         cpt_enable_fdi_bc_bifurcation(dev);
5386
5387                 return true;
5388         case PIPE_C:
5389                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5390                         if (intel_crtc->fdi_lanes > 2) {
5391                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5392                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5393                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5394                                 intel_crtc->fdi_lanes = 2;
5395
5396                                 return false;
5397                         }
5398                 } else {
5399                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5400                         return false;
5401                 }
5402
5403                 cpt_enable_fdi_bc_bifurcation(dev);
5404
5405                 return true;
5406         default:
5407                 BUG();
5408         }
5409 }
5410
5411 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5412 {
5413         /*
5414          * Account for spread spectrum to avoid
5415          * oversubscribing the link. Max center spread
5416          * is 2.5%; use 5% for safety's sake.
5417          */
5418         u32 bps = target_clock * bpp * 21 / 20;
5419         return bps / (link_bw * 8) + 1;
5420 }
5421
5422 static void ironlake_set_m_n(struct drm_crtc *crtc,
5423                              struct drm_display_mode *mode,
5424                              struct drm_display_mode *adjusted_mode)
5425 {
5426         struct drm_device *dev = crtc->dev;
5427         struct drm_i915_private *dev_priv = dev->dev_private;
5428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5429         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5430         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5431         struct intel_link_m_n m_n = {0};
5432         int target_clock, pixel_multiplier, lane, link_bw;
5433         bool is_dp = false, is_cpu_edp = false;
5434
5435         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5436                 switch (intel_encoder->type) {
5437                 case INTEL_OUTPUT_DISPLAYPORT:
5438                         is_dp = true;
5439                         break;
5440                 case INTEL_OUTPUT_EDP:
5441                         is_dp = true;
5442                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5443                                 is_cpu_edp = true;
5444                         edp_encoder = intel_encoder;
5445                         break;
5446                 }
5447         }
5448
5449         /* FDI link */
5450         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5451         lane = 0;
5452         /* CPU eDP doesn't require FDI link, so just set DP M/N
5453            according to current link config */
5454         if (is_cpu_edp) {
5455                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5456         } else {
5457                 /* FDI is a binary signal running at ~2.7GHz, encoding
5458                  * each output octet as 10 bits. The actual frequency
5459                  * is stored as a divider into a 100MHz clock, and the
5460                  * mode pixel clock is stored in units of 1KHz.
5461                  * Hence the bw of each lane in terms of the mode signal
5462                  * is:
5463                  */
5464                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5465         }
5466
5467         /* [e]DP over FDI requires target mode clock instead of link clock. */
5468         if (edp_encoder)
5469                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5470         else if (is_dp)
5471                 target_clock = mode->clock;
5472         else
5473                 target_clock = adjusted_mode->clock;
5474
5475         if (!lane)
5476                 lane = ironlake_get_lanes_required(target_clock, link_bw,
5477                                                    intel_crtc->bpp);
5478
5479         intel_crtc->fdi_lanes = lane;
5480
5481         if (pixel_multiplier > 1)
5482                 link_bw *= pixel_multiplier;
5483         intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
5484
5485         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5486         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5487         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5488         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5489 }
5490
5491 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5492                                       struct drm_display_mode *adjusted_mode,
5493                                       intel_clock_t *clock, u32 fp)
5494 {
5495         struct drm_crtc *crtc = &intel_crtc->base;
5496         struct drm_device *dev = crtc->dev;
5497         struct drm_i915_private *dev_priv = dev->dev_private;
5498         struct intel_encoder *intel_encoder;
5499         uint32_t dpll;
5500         int factor, pixel_multiplier, num_connectors = 0;
5501         bool is_lvds = false, is_sdvo = false, is_tv = false;
5502         bool is_dp = false, is_cpu_edp = false;
5503
5504         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5505                 switch (intel_encoder->type) {
5506                 case INTEL_OUTPUT_LVDS:
5507                         is_lvds = true;
5508                         break;
5509                 case INTEL_OUTPUT_SDVO:
5510                 case INTEL_OUTPUT_HDMI:
5511                         is_sdvo = true;
5512                         if (intel_encoder->needs_tv_clock)
5513                                 is_tv = true;
5514                         break;
5515                 case INTEL_OUTPUT_TVOUT:
5516                         is_tv = true;
5517                         break;
5518                 case INTEL_OUTPUT_DISPLAYPORT:
5519                         is_dp = true;
5520                         break;
5521                 case INTEL_OUTPUT_EDP:
5522                         is_dp = true;
5523                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5524                                 is_cpu_edp = true;
5525                         break;
5526                 }
5527
5528                 num_connectors++;
5529         }
5530
5531         /* Enable autotuning of the PLL clock (if permissible) */
5532         factor = 21;
5533         if (is_lvds) {
5534                 if ((intel_panel_use_ssc(dev_priv) &&
5535                      dev_priv->lvds_ssc_freq == 100) ||
5536                     intel_is_dual_link_lvds(dev))
5537                         factor = 25;
5538         } else if (is_sdvo && is_tv)
5539                 factor = 20;
5540
5541         if (clock->m < factor * clock->n)
5542                 fp |= FP_CB_TUNE;
5543
5544         dpll = 0;
5545
5546         if (is_lvds)
5547                 dpll |= DPLLB_MODE_LVDS;
5548         else
5549                 dpll |= DPLLB_MODE_DAC_SERIAL;
5550         if (is_sdvo) {
5551                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5552                 if (pixel_multiplier > 1) {
5553                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5554                 }
5555                 dpll |= DPLL_DVO_HIGH_SPEED;
5556         }
5557         if (is_dp && !is_cpu_edp)
5558                 dpll |= DPLL_DVO_HIGH_SPEED;
5559
5560         /* compute bitmask from p1 value */
5561         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5562         /* also FPA1 */
5563         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5564
5565         switch (clock->p2) {
5566         case 5:
5567                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5568                 break;
5569         case 7:
5570                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5571                 break;
5572         case 10:
5573                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5574                 break;
5575         case 14:
5576                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5577                 break;
5578         }
5579
5580         if (is_sdvo && is_tv)
5581                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5582         else if (is_tv)
5583                 /* XXX: just matching BIOS for now */
5584                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5585                 dpll |= 3;
5586         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5587                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5588         else
5589                 dpll |= PLL_REF_INPUT_DREFCLK;
5590
5591         return dpll;
5592 }
5593
5594 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5595                                   struct drm_display_mode *mode,
5596                                   struct drm_display_mode *adjusted_mode,
5597                                   int x, int y,
5598                                   struct drm_framebuffer *fb)
5599 {
5600         struct drm_device *dev = crtc->dev;
5601         struct drm_i915_private *dev_priv = dev->dev_private;
5602         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5603         int pipe = intel_crtc->pipe;
5604         int plane = intel_crtc->plane;
5605         int num_connectors = 0;
5606         intel_clock_t clock, reduced_clock;
5607         u32 dpll, fp = 0, fp2 = 0;
5608         bool ok, has_reduced_clock = false;
5609         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5610         struct intel_encoder *encoder;
5611         int ret;
5612         bool dither, fdi_config_ok;
5613
5614         for_each_encoder_on_crtc(dev, crtc, encoder) {
5615                 switch (encoder->type) {
5616                 case INTEL_OUTPUT_LVDS:
5617                         is_lvds = true;
5618                         break;
5619                 case INTEL_OUTPUT_DISPLAYPORT:
5620                         is_dp = true;
5621                         break;
5622                 case INTEL_OUTPUT_EDP:
5623                         is_dp = true;
5624                         if (!intel_encoder_is_pch_edp(&encoder->base))
5625                                 is_cpu_edp = true;
5626                         break;
5627                 }
5628
5629                 num_connectors++;
5630         }
5631
5632         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5633              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5634
5635         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5636                                      &has_reduced_clock, &reduced_clock);
5637         if (!ok) {
5638                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5639                 return -EINVAL;
5640         }
5641
5642         /* Ensure that the cursor is valid for the new mode before changing... */
5643         intel_crtc_update_cursor(crtc, true);
5644
5645         /* determine panel color depth */
5646         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5647                                               adjusted_mode);
5648         if (is_lvds && dev_priv->lvds_dither)
5649                 dither = true;
5650
5651         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5652         if (has_reduced_clock)
5653                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5654                         reduced_clock.m2;
5655
5656         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5657
5658         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5659         drm_mode_debug_printmodeline(mode);
5660
5661         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5662         if (!is_cpu_edp) {
5663                 struct intel_pch_pll *pll;
5664
5665                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5666                 if (pll == NULL) {
5667                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5668                                          pipe);
5669                         return -EINVAL;
5670                 }
5671         } else
5672                 intel_put_pch_pll(intel_crtc);
5673
5674         if (is_dp && !is_cpu_edp)
5675                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5676
5677         for_each_encoder_on_crtc(dev, crtc, encoder)
5678                 if (encoder->pre_pll_enable)
5679                         encoder->pre_pll_enable(encoder);
5680
5681         if (intel_crtc->pch_pll) {
5682                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5683
5684                 /* Wait for the clocks to stabilize. */
5685                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5686                 udelay(150);
5687
5688                 /* The pixel multiplier can only be updated once the
5689                  * DPLL is enabled and the clocks are stable.
5690                  *
5691                  * So write it again.
5692                  */
5693                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5694         }
5695
5696         intel_crtc->lowfreq_avail = false;
5697         if (intel_crtc->pch_pll) {
5698                 if (is_lvds && has_reduced_clock && i915_powersave) {
5699                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5700                         intel_crtc->lowfreq_avail = true;
5701                 } else {
5702                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5703                 }
5704         }
5705
5706         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5707
5708         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5709          * ironlake_check_fdi_lanes. */
5710         ironlake_set_m_n(crtc, mode, adjusted_mode);
5711
5712         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5713
5714         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5715
5716         intel_wait_for_vblank(dev, pipe);
5717
5718         /* Set up the display plane register */
5719         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5720         POSTING_READ(DSPCNTR(plane));
5721
5722         ret = intel_pipe_set_base(crtc, x, y, fb);
5723
5724         intel_update_watermarks(dev);
5725
5726         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5727
5728         return fdi_config_ok ? ret : -EINVAL;
5729 }
5730
5731 static void haswell_modeset_global_resources(struct drm_device *dev)
5732 {
5733         struct drm_i915_private *dev_priv = dev->dev_private;
5734         bool enable = false;
5735         struct intel_crtc *crtc;
5736         struct intel_encoder *encoder;
5737
5738         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5739                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5740                         enable = true;
5741                 /* XXX: Should check for edp transcoder here, but thanks to init
5742                  * sequence that's not yet available. Just in case desktop eDP
5743                  * on PORT D is possible on haswell, too. */
5744         }
5745
5746         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5747                             base.head) {
5748                 if (encoder->type != INTEL_OUTPUT_EDP &&
5749                     encoder->connectors_active)
5750                         enable = true;
5751         }
5752
5753         /* Even the eDP panel fitter is outside the always-on well. */
5754         if (dev_priv->pch_pf_size)
5755                 enable = true;
5756
5757         intel_set_power_well(dev, enable);
5758 }
5759
5760 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5761                                  struct drm_display_mode *mode,
5762                                  struct drm_display_mode *adjusted_mode,
5763                                  int x, int y,
5764                                  struct drm_framebuffer *fb)
5765 {
5766         struct drm_device *dev = crtc->dev;
5767         struct drm_i915_private *dev_priv = dev->dev_private;
5768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5769         int pipe = intel_crtc->pipe;
5770         int plane = intel_crtc->plane;
5771         int num_connectors = 0;
5772         bool is_dp = false, is_cpu_edp = false;
5773         struct intel_encoder *encoder;
5774         int ret;
5775         bool dither;
5776
5777         for_each_encoder_on_crtc(dev, crtc, encoder) {
5778                 switch (encoder->type) {
5779                 case INTEL_OUTPUT_DISPLAYPORT:
5780                         is_dp = true;
5781                         break;
5782                 case INTEL_OUTPUT_EDP:
5783                         is_dp = true;
5784                         if (!intel_encoder_is_pch_edp(&encoder->base))
5785                                 is_cpu_edp = true;
5786                         break;
5787                 }
5788
5789                 num_connectors++;
5790         }
5791
5792         /* We are not sure yet this won't happen. */
5793         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5794              INTEL_PCH_TYPE(dev));
5795
5796         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5797              num_connectors, pipe_name(pipe));
5798
5799         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5800                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5801
5802         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5803
5804         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5805                 return -EINVAL;
5806
5807         /* Ensure that the cursor is valid for the new mode before changing... */
5808         intel_crtc_update_cursor(crtc, true);
5809
5810         /* determine panel color depth */
5811         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5812                                               adjusted_mode);
5813
5814         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5815         drm_mode_debug_printmodeline(mode);
5816
5817         if (is_dp && !is_cpu_edp)
5818                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5819
5820         intel_crtc->lowfreq_avail = false;
5821
5822         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5823
5824         if (!is_dp || is_cpu_edp)
5825                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5826
5827         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5828
5829         intel_set_pipe_csc(crtc, adjusted_mode);
5830
5831         /* Set up the display plane register */
5832         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5833         POSTING_READ(DSPCNTR(plane));
5834
5835         ret = intel_pipe_set_base(crtc, x, y, fb);
5836
5837         intel_update_watermarks(dev);
5838
5839         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5840
5841         return ret;
5842 }
5843
5844 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5845                                struct drm_display_mode *mode,
5846                                struct drm_display_mode *adjusted_mode,
5847                                int x, int y,
5848                                struct drm_framebuffer *fb)
5849 {
5850         struct drm_device *dev = crtc->dev;
5851         struct drm_i915_private *dev_priv = dev->dev_private;
5852         struct drm_encoder_helper_funcs *encoder_funcs;
5853         struct intel_encoder *encoder;
5854         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5855         int pipe = intel_crtc->pipe;
5856         int ret;
5857
5858         if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5859                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5860         else
5861                 intel_crtc->cpu_transcoder = pipe;
5862
5863         drm_vblank_pre_modeset(dev, pipe);
5864
5865         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5866                                               x, y, fb);
5867         drm_vblank_post_modeset(dev, pipe);
5868
5869         if (ret != 0)
5870                 return ret;
5871
5872         for_each_encoder_on_crtc(dev, crtc, encoder) {
5873                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5874                         encoder->base.base.id,
5875                         drm_get_encoder_name(&encoder->base),
5876                         mode->base.id, mode->name);
5877                 encoder_funcs = encoder->base.helper_private;
5878                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5879         }
5880
5881         return 0;
5882 }
5883
5884 static bool intel_eld_uptodate(struct drm_connector *connector,
5885                                int reg_eldv, uint32_t bits_eldv,
5886                                int reg_elda, uint32_t bits_elda,
5887                                int reg_edid)
5888 {
5889         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5890         uint8_t *eld = connector->eld;
5891         uint32_t i;
5892
5893         i = I915_READ(reg_eldv);
5894         i &= bits_eldv;
5895
5896         if (!eld[0])
5897                 return !i;
5898
5899         if (!i)
5900                 return false;
5901
5902         i = I915_READ(reg_elda);
5903         i &= ~bits_elda;
5904         I915_WRITE(reg_elda, i);
5905
5906         for (i = 0; i < eld[2]; i++)
5907                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5908                         return false;
5909
5910         return true;
5911 }
5912
5913 static void g4x_write_eld(struct drm_connector *connector,
5914                           struct drm_crtc *crtc)
5915 {
5916         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5917         uint8_t *eld = connector->eld;
5918         uint32_t eldv;
5919         uint32_t len;
5920         uint32_t i;
5921
5922         i = I915_READ(G4X_AUD_VID_DID);
5923
5924         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5925                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5926         else
5927                 eldv = G4X_ELDV_DEVCTG;
5928
5929         if (intel_eld_uptodate(connector,
5930                                G4X_AUD_CNTL_ST, eldv,
5931                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5932                                G4X_HDMIW_HDMIEDID))
5933                 return;
5934
5935         i = I915_READ(G4X_AUD_CNTL_ST);
5936         i &= ~(eldv | G4X_ELD_ADDR);
5937         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5938         I915_WRITE(G4X_AUD_CNTL_ST, i);
5939
5940         if (!eld[0])
5941                 return;
5942
5943         len = min_t(uint8_t, eld[2], len);
5944         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5945         for (i = 0; i < len; i++)
5946                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5947
5948         i = I915_READ(G4X_AUD_CNTL_ST);
5949         i |= eldv;
5950         I915_WRITE(G4X_AUD_CNTL_ST, i);
5951 }
5952
5953 static void haswell_write_eld(struct drm_connector *connector,
5954                                      struct drm_crtc *crtc)
5955 {
5956         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5957         uint8_t *eld = connector->eld;
5958         struct drm_device *dev = crtc->dev;
5959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5960         uint32_t eldv;
5961         uint32_t i;
5962         int len;
5963         int pipe = to_intel_crtc(crtc)->pipe;
5964         int tmp;
5965
5966         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5967         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5968         int aud_config = HSW_AUD_CFG(pipe);
5969         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5970
5971
5972         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5973
5974         /* Audio output enable */
5975         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5976         tmp = I915_READ(aud_cntrl_st2);
5977         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5978         I915_WRITE(aud_cntrl_st2, tmp);
5979
5980         /* Wait for 1 vertical blank */
5981         intel_wait_for_vblank(dev, pipe);
5982
5983         /* Set ELD valid state */
5984         tmp = I915_READ(aud_cntrl_st2);
5985         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5986         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5987         I915_WRITE(aud_cntrl_st2, tmp);
5988         tmp = I915_READ(aud_cntrl_st2);
5989         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5990
5991         /* Enable HDMI mode */
5992         tmp = I915_READ(aud_config);
5993         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5994         /* clear N_programing_enable and N_value_index */
5995         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5996         I915_WRITE(aud_config, tmp);
5997
5998         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5999
6000         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6001         intel_crtc->eld_vld = true;
6002
6003         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6004                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6005                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6006                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6007         } else
6008                 I915_WRITE(aud_config, 0);
6009
6010         if (intel_eld_uptodate(connector,
6011                                aud_cntrl_st2, eldv,
6012                                aud_cntl_st, IBX_ELD_ADDRESS,
6013                                hdmiw_hdmiedid))
6014                 return;
6015
6016         i = I915_READ(aud_cntrl_st2);
6017         i &= ~eldv;
6018         I915_WRITE(aud_cntrl_st2, i);
6019
6020         if (!eld[0])
6021                 return;
6022
6023         i = I915_READ(aud_cntl_st);
6024         i &= ~IBX_ELD_ADDRESS;
6025         I915_WRITE(aud_cntl_st, i);
6026         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6027         DRM_DEBUG_DRIVER("port num:%d\n", i);
6028
6029         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6030         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6031         for (i = 0; i < len; i++)
6032                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6033
6034         i = I915_READ(aud_cntrl_st2);
6035         i |= eldv;
6036         I915_WRITE(aud_cntrl_st2, i);
6037
6038 }
6039
6040 static void ironlake_write_eld(struct drm_connector *connector,
6041                                      struct drm_crtc *crtc)
6042 {
6043         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6044         uint8_t *eld = connector->eld;
6045         uint32_t eldv;
6046         uint32_t i;
6047         int len;
6048         int hdmiw_hdmiedid;
6049         int aud_config;
6050         int aud_cntl_st;
6051         int aud_cntrl_st2;
6052         int pipe = to_intel_crtc(crtc)->pipe;
6053
6054         if (HAS_PCH_IBX(connector->dev)) {
6055                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6056                 aud_config = IBX_AUD_CFG(pipe);
6057                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6058                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6059         } else {
6060                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6061                 aud_config = CPT_AUD_CFG(pipe);
6062                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6063                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6064         }
6065
6066         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6067
6068         i = I915_READ(aud_cntl_st);
6069         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6070         if (!i) {
6071                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6072                 /* operate blindly on all ports */
6073                 eldv = IBX_ELD_VALIDB;
6074                 eldv |= IBX_ELD_VALIDB << 4;
6075                 eldv |= IBX_ELD_VALIDB << 8;
6076         } else {
6077                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6078                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6079         }
6080
6081         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6082                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6083                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6084                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6085         } else
6086                 I915_WRITE(aud_config, 0);
6087
6088         if (intel_eld_uptodate(connector,
6089                                aud_cntrl_st2, eldv,
6090                                aud_cntl_st, IBX_ELD_ADDRESS,
6091                                hdmiw_hdmiedid))
6092                 return;
6093
6094         i = I915_READ(aud_cntrl_st2);
6095         i &= ~eldv;
6096         I915_WRITE(aud_cntrl_st2, i);
6097
6098         if (!eld[0])
6099                 return;
6100
6101         i = I915_READ(aud_cntl_st);
6102         i &= ~IBX_ELD_ADDRESS;
6103         I915_WRITE(aud_cntl_st, i);
6104
6105         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6106         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6107         for (i = 0; i < len; i++)
6108                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6109
6110         i = I915_READ(aud_cntrl_st2);
6111         i |= eldv;
6112         I915_WRITE(aud_cntrl_st2, i);
6113 }
6114
6115 void intel_write_eld(struct drm_encoder *encoder,
6116                      struct drm_display_mode *mode)
6117 {
6118         struct drm_crtc *crtc = encoder->crtc;
6119         struct drm_connector *connector;
6120         struct drm_device *dev = encoder->dev;
6121         struct drm_i915_private *dev_priv = dev->dev_private;
6122
6123         connector = drm_select_eld(encoder, mode);
6124         if (!connector)
6125                 return;
6126
6127         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6128                          connector->base.id,
6129                          drm_get_connector_name(connector),
6130                          connector->encoder->base.id,
6131                          drm_get_encoder_name(connector->encoder));
6132
6133         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6134
6135         if (dev_priv->display.write_eld)
6136                 dev_priv->display.write_eld(connector, crtc);
6137 }
6138
6139 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6140 void intel_crtc_load_lut(struct drm_crtc *crtc)
6141 {
6142         struct drm_device *dev = crtc->dev;
6143         struct drm_i915_private *dev_priv = dev->dev_private;
6144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6145         int palreg = PALETTE(intel_crtc->pipe);
6146         int i;
6147
6148         /* The clocks have to be on to load the palette. */
6149         if (!crtc->enabled || !intel_crtc->active)
6150                 return;
6151
6152         /* use legacy palette for Ironlake */
6153         if (HAS_PCH_SPLIT(dev))
6154                 palreg = LGC_PALETTE(intel_crtc->pipe);
6155
6156         for (i = 0; i < 256; i++) {
6157                 I915_WRITE(palreg + 4 * i,
6158                            (intel_crtc->lut_r[i] << 16) |
6159                            (intel_crtc->lut_g[i] << 8) |
6160                            intel_crtc->lut_b[i]);
6161         }
6162 }
6163
6164 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6165 {
6166         struct drm_device *dev = crtc->dev;
6167         struct drm_i915_private *dev_priv = dev->dev_private;
6168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6169         bool visible = base != 0;
6170         u32 cntl;
6171
6172         if (intel_crtc->cursor_visible == visible)
6173                 return;
6174
6175         cntl = I915_READ(_CURACNTR);
6176         if (visible) {
6177                 /* On these chipsets we can only modify the base whilst
6178                  * the cursor is disabled.
6179                  */
6180                 I915_WRITE(_CURABASE, base);
6181
6182                 cntl &= ~(CURSOR_FORMAT_MASK);
6183                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6184                 cntl |= CURSOR_ENABLE |
6185                         CURSOR_GAMMA_ENABLE |
6186                         CURSOR_FORMAT_ARGB;
6187         } else
6188                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6189         I915_WRITE(_CURACNTR, cntl);
6190
6191         intel_crtc->cursor_visible = visible;
6192 }
6193
6194 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6195 {
6196         struct drm_device *dev = crtc->dev;
6197         struct drm_i915_private *dev_priv = dev->dev_private;
6198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6199         int pipe = intel_crtc->pipe;
6200         bool visible = base != 0;
6201
6202         if (intel_crtc->cursor_visible != visible) {
6203                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6204                 if (base) {
6205                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6206                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6207                         cntl |= pipe << 28; /* Connect to correct pipe */
6208                 } else {
6209                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6210                         cntl |= CURSOR_MODE_DISABLE;
6211                 }
6212                 I915_WRITE(CURCNTR(pipe), cntl);
6213
6214                 intel_crtc->cursor_visible = visible;
6215         }
6216         /* and commit changes on next vblank */
6217         I915_WRITE(CURBASE(pipe), base);
6218 }
6219
6220 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6221 {
6222         struct drm_device *dev = crtc->dev;
6223         struct drm_i915_private *dev_priv = dev->dev_private;
6224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6225         int pipe = intel_crtc->pipe;
6226         bool visible = base != 0;
6227
6228         if (intel_crtc->cursor_visible != visible) {
6229                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6230                 if (base) {
6231                         cntl &= ~CURSOR_MODE;
6232                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6233                 } else {
6234                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6235                         cntl |= CURSOR_MODE_DISABLE;
6236                 }
6237                 if (IS_HASWELL(dev))
6238                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6239                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6240
6241                 intel_crtc->cursor_visible = visible;
6242         }
6243         /* and commit changes on next vblank */
6244         I915_WRITE(CURBASE_IVB(pipe), base);
6245 }
6246
6247 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6248 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6249                                      bool on)
6250 {
6251         struct drm_device *dev = crtc->dev;
6252         struct drm_i915_private *dev_priv = dev->dev_private;
6253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6254         int pipe = intel_crtc->pipe;
6255         int x = intel_crtc->cursor_x;
6256         int y = intel_crtc->cursor_y;
6257         u32 base, pos;
6258         bool visible;
6259
6260         pos = 0;
6261
6262         if (on && crtc->enabled && crtc->fb) {
6263                 base = intel_crtc->cursor_addr;
6264                 if (x > (int) crtc->fb->width)
6265                         base = 0;
6266
6267                 if (y > (int) crtc->fb->height)
6268                         base = 0;
6269         } else
6270                 base = 0;
6271
6272         if (x < 0) {
6273                 if (x + intel_crtc->cursor_width < 0)
6274                         base = 0;
6275
6276                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6277                 x = -x;
6278         }
6279         pos |= x << CURSOR_X_SHIFT;
6280
6281         if (y < 0) {
6282                 if (y + intel_crtc->cursor_height < 0)
6283                         base = 0;
6284
6285                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6286                 y = -y;
6287         }
6288         pos |= y << CURSOR_Y_SHIFT;
6289
6290         visible = base != 0;
6291         if (!visible && !intel_crtc->cursor_visible)
6292                 return;
6293
6294         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6295                 I915_WRITE(CURPOS_IVB(pipe), pos);
6296                 ivb_update_cursor(crtc, base);
6297         } else {
6298                 I915_WRITE(CURPOS(pipe), pos);
6299                 if (IS_845G(dev) || IS_I865G(dev))
6300                         i845_update_cursor(crtc, base);
6301                 else
6302                         i9xx_update_cursor(crtc, base);
6303         }
6304 }
6305
6306 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6307                                  struct drm_file *file,
6308                                  uint32_t handle,
6309                                  uint32_t width, uint32_t height)
6310 {
6311         struct drm_device *dev = crtc->dev;
6312         struct drm_i915_private *dev_priv = dev->dev_private;
6313         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314         struct drm_i915_gem_object *obj;
6315         uint32_t addr;
6316         int ret;
6317
6318         /* if we want to turn off the cursor ignore width and height */
6319         if (!handle) {
6320                 DRM_DEBUG_KMS("cursor off\n");
6321                 addr = 0;
6322                 obj = NULL;
6323                 mutex_lock(&dev->struct_mutex);
6324                 goto finish;
6325         }
6326
6327         /* Currently we only support 64x64 cursors */
6328         if (width != 64 || height != 64) {
6329                 DRM_ERROR("we currently only support 64x64 cursors\n");
6330                 return -EINVAL;
6331         }
6332
6333         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6334         if (&obj->base == NULL)
6335                 return -ENOENT;
6336
6337         if (obj->base.size < width * height * 4) {
6338                 DRM_ERROR("buffer is to small\n");
6339                 ret = -ENOMEM;
6340                 goto fail;
6341         }
6342
6343         /* we only need to pin inside GTT if cursor is non-phy */
6344         mutex_lock(&dev->struct_mutex);
6345         if (!dev_priv->info->cursor_needs_physical) {
6346                 if (obj->tiling_mode) {
6347                         DRM_ERROR("cursor cannot be tiled\n");
6348                         ret = -EINVAL;
6349                         goto fail_locked;
6350                 }
6351
6352                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6353                 if (ret) {
6354                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6355                         goto fail_locked;
6356                 }
6357
6358                 ret = i915_gem_object_put_fence(obj);
6359                 if (ret) {
6360                         DRM_ERROR("failed to release fence for cursor");
6361                         goto fail_unpin;
6362                 }
6363
6364                 addr = obj->gtt_offset;
6365         } else {
6366                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6367                 ret = i915_gem_attach_phys_object(dev, obj,
6368                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6369                                                   align);
6370                 if (ret) {
6371                         DRM_ERROR("failed to attach phys object\n");
6372                         goto fail_locked;
6373                 }
6374                 addr = obj->phys_obj->handle->busaddr;
6375         }
6376
6377         if (IS_GEN2(dev))
6378                 I915_WRITE(CURSIZE, (height << 12) | width);
6379
6380  finish:
6381         if (intel_crtc->cursor_bo) {
6382                 if (dev_priv->info->cursor_needs_physical) {
6383                         if (intel_crtc->cursor_bo != obj)
6384                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6385                 } else
6386                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6387                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6388         }
6389
6390         mutex_unlock(&dev->struct_mutex);
6391
6392         intel_crtc->cursor_addr = addr;
6393         intel_crtc->cursor_bo = obj;
6394         intel_crtc->cursor_width = width;
6395         intel_crtc->cursor_height = height;
6396
6397         intel_crtc_update_cursor(crtc, true);
6398
6399         return 0;
6400 fail_unpin:
6401         i915_gem_object_unpin(obj);
6402 fail_locked:
6403         mutex_unlock(&dev->struct_mutex);
6404 fail:
6405         drm_gem_object_unreference_unlocked(&obj->base);
6406         return ret;
6407 }
6408
6409 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6410 {
6411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6412
6413         intel_crtc->cursor_x = x;
6414         intel_crtc->cursor_y = y;
6415
6416         intel_crtc_update_cursor(crtc, true);
6417
6418         return 0;
6419 }
6420
6421 /** Sets the color ramps on behalf of RandR */
6422 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6423                                  u16 blue, int regno)
6424 {
6425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6426
6427         intel_crtc->lut_r[regno] = red >> 8;
6428         intel_crtc->lut_g[regno] = green >> 8;
6429         intel_crtc->lut_b[regno] = blue >> 8;
6430 }
6431
6432 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6433                              u16 *blue, int regno)
6434 {
6435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6436
6437         *red = intel_crtc->lut_r[regno] << 8;
6438         *green = intel_crtc->lut_g[regno] << 8;
6439         *blue = intel_crtc->lut_b[regno] << 8;
6440 }
6441
6442 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6443                                  u16 *blue, uint32_t start, uint32_t size)
6444 {
6445         int end = (start + size > 256) ? 256 : start + size, i;
6446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6447
6448         for (i = start; i < end; i++) {
6449                 intel_crtc->lut_r[i] = red[i] >> 8;
6450                 intel_crtc->lut_g[i] = green[i] >> 8;
6451                 intel_crtc->lut_b[i] = blue[i] >> 8;
6452         }
6453
6454         intel_crtc_load_lut(crtc);
6455 }
6456
6457 /**
6458  * Get a pipe with a simple mode set on it for doing load-based monitor
6459  * detection.
6460  *
6461  * It will be up to the load-detect code to adjust the pipe as appropriate for
6462  * its requirements.  The pipe will be connected to no other encoders.
6463  *
6464  * Currently this code will only succeed if there is a pipe with no encoders
6465  * configured for it.  In the future, it could choose to temporarily disable
6466  * some outputs to free up a pipe for its use.
6467  *
6468  * \return crtc, or NULL if no pipes are available.
6469  */
6470
6471 /* VESA 640x480x72Hz mode to set on the pipe */
6472 static struct drm_display_mode load_detect_mode = {
6473         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6474                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6475 };
6476
6477 static struct drm_framebuffer *
6478 intel_framebuffer_create(struct drm_device *dev,
6479                          struct drm_mode_fb_cmd2 *mode_cmd,
6480                          struct drm_i915_gem_object *obj)
6481 {
6482         struct intel_framebuffer *intel_fb;
6483         int ret;
6484
6485         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6486         if (!intel_fb) {
6487                 drm_gem_object_unreference_unlocked(&obj->base);
6488                 return ERR_PTR(-ENOMEM);
6489         }
6490
6491         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6492         if (ret) {
6493                 drm_gem_object_unreference_unlocked(&obj->base);
6494                 kfree(intel_fb);
6495                 return ERR_PTR(ret);
6496         }
6497
6498         return &intel_fb->base;
6499 }
6500
6501 static u32
6502 intel_framebuffer_pitch_for_width(int width, int bpp)
6503 {
6504         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6505         return ALIGN(pitch, 64);
6506 }
6507
6508 static u32
6509 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6510 {
6511         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6512         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6513 }
6514
6515 static struct drm_framebuffer *
6516 intel_framebuffer_create_for_mode(struct drm_device *dev,
6517                                   struct drm_display_mode *mode,
6518                                   int depth, int bpp)
6519 {
6520         struct drm_i915_gem_object *obj;
6521         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6522
6523         obj = i915_gem_alloc_object(dev,
6524                                     intel_framebuffer_size_for_mode(mode, bpp));
6525         if (obj == NULL)
6526                 return ERR_PTR(-ENOMEM);
6527
6528         mode_cmd.width = mode->hdisplay;
6529         mode_cmd.height = mode->vdisplay;
6530         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6531                                                                 bpp);
6532         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6533
6534         return intel_framebuffer_create(dev, &mode_cmd, obj);
6535 }
6536
6537 static struct drm_framebuffer *
6538 mode_fits_in_fbdev(struct drm_device *dev,
6539                    struct drm_display_mode *mode)
6540 {
6541         struct drm_i915_private *dev_priv = dev->dev_private;
6542         struct drm_i915_gem_object *obj;
6543         struct drm_framebuffer *fb;
6544
6545         if (dev_priv->fbdev == NULL)
6546                 return NULL;
6547
6548         obj = dev_priv->fbdev->ifb.obj;
6549         if (obj == NULL)
6550                 return NULL;
6551
6552         fb = &dev_priv->fbdev->ifb.base;
6553         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6554                                                                fb->bits_per_pixel))
6555                 return NULL;
6556
6557         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6558                 return NULL;
6559
6560         return fb;
6561 }
6562
6563 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6564                                 struct drm_display_mode *mode,
6565                                 struct intel_load_detect_pipe *old)
6566 {
6567         struct intel_crtc *intel_crtc;
6568         struct intel_encoder *intel_encoder =
6569                 intel_attached_encoder(connector);
6570         struct drm_crtc *possible_crtc;
6571         struct drm_encoder *encoder = &intel_encoder->base;
6572         struct drm_crtc *crtc = NULL;
6573         struct drm_device *dev = encoder->dev;
6574         struct drm_framebuffer *fb;
6575         int i = -1;
6576
6577         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6578                       connector->base.id, drm_get_connector_name(connector),
6579                       encoder->base.id, drm_get_encoder_name(encoder));
6580
6581         /*
6582          * Algorithm gets a little messy:
6583          *
6584          *   - if the connector already has an assigned crtc, use it (but make
6585          *     sure it's on first)
6586          *
6587          *   - try to find the first unused crtc that can drive this connector,
6588          *     and use that if we find one
6589          */
6590
6591         /* See if we already have a CRTC for this connector */
6592         if (encoder->crtc) {
6593                 crtc = encoder->crtc;
6594
6595                 mutex_lock(&crtc->mutex);
6596
6597                 old->dpms_mode = connector->dpms;
6598                 old->load_detect_temp = false;
6599
6600                 /* Make sure the crtc and connector are running */
6601                 if (connector->dpms != DRM_MODE_DPMS_ON)
6602                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6603
6604                 return true;
6605         }
6606
6607         /* Find an unused one (if possible) */
6608         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6609                 i++;
6610                 if (!(encoder->possible_crtcs & (1 << i)))
6611                         continue;
6612                 if (!possible_crtc->enabled) {
6613                         crtc = possible_crtc;
6614                         break;
6615                 }
6616         }
6617
6618         /*
6619          * If we didn't find an unused CRTC, don't use any.
6620          */
6621         if (!crtc) {
6622                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6623                 return false;
6624         }
6625
6626         mutex_lock(&crtc->mutex);
6627         intel_encoder->new_crtc = to_intel_crtc(crtc);
6628         to_intel_connector(connector)->new_encoder = intel_encoder;
6629
6630         intel_crtc = to_intel_crtc(crtc);
6631         old->dpms_mode = connector->dpms;
6632         old->load_detect_temp = true;
6633         old->release_fb = NULL;
6634
6635         if (!mode)
6636                 mode = &load_detect_mode;
6637
6638         /* We need a framebuffer large enough to accommodate all accesses
6639          * that the plane may generate whilst we perform load detection.
6640          * We can not rely on the fbcon either being present (we get called
6641          * during its initialisation to detect all boot displays, or it may
6642          * not even exist) or that it is large enough to satisfy the
6643          * requested mode.
6644          */
6645         fb = mode_fits_in_fbdev(dev, mode);
6646         if (fb == NULL) {
6647                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6648                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6649                 old->release_fb = fb;
6650         } else
6651                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6652         if (IS_ERR(fb)) {
6653                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6654                 mutex_unlock(&crtc->mutex);
6655                 return false;
6656         }
6657
6658         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6659                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6660                 if (old->release_fb)
6661                         old->release_fb->funcs->destroy(old->release_fb);
6662                 mutex_unlock(&crtc->mutex);
6663                 return false;
6664         }
6665
6666         /* let the connector get through one full cycle before testing */
6667         intel_wait_for_vblank(dev, intel_crtc->pipe);
6668         return true;
6669 }
6670
6671 void intel_release_load_detect_pipe(struct drm_connector *connector,
6672                                     struct intel_load_detect_pipe *old)
6673 {
6674         struct intel_encoder *intel_encoder =
6675                 intel_attached_encoder(connector);
6676         struct drm_encoder *encoder = &intel_encoder->base;
6677         struct drm_crtc *crtc = encoder->crtc;
6678
6679         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6680                       connector->base.id, drm_get_connector_name(connector),
6681                       encoder->base.id, drm_get_encoder_name(encoder));
6682
6683         if (old->load_detect_temp) {
6684                 to_intel_connector(connector)->new_encoder = NULL;
6685                 intel_encoder->new_crtc = NULL;
6686                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6687
6688                 if (old->release_fb) {
6689                         drm_framebuffer_unregister_private(old->release_fb);
6690                         drm_framebuffer_unreference(old->release_fb);
6691                 }
6692
6693                 mutex_unlock(&crtc->mutex);
6694                 return;
6695         }
6696
6697         /* Switch crtc and encoder back off if necessary */
6698         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6699                 connector->funcs->dpms(connector, old->dpms_mode);
6700
6701         mutex_unlock(&crtc->mutex);
6702 }
6703
6704 /* Returns the clock of the currently programmed mode of the given pipe. */
6705 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6706 {
6707         struct drm_i915_private *dev_priv = dev->dev_private;
6708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6709         int pipe = intel_crtc->pipe;
6710         u32 dpll = I915_READ(DPLL(pipe));
6711         u32 fp;
6712         intel_clock_t clock;
6713
6714         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6715                 fp = I915_READ(FP0(pipe));
6716         else
6717                 fp = I915_READ(FP1(pipe));
6718
6719         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6720         if (IS_PINEVIEW(dev)) {
6721                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6722                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6723         } else {
6724                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6725                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6726         }
6727
6728         if (!IS_GEN2(dev)) {
6729                 if (IS_PINEVIEW(dev))
6730                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6731                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6732                 else
6733                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6734                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6735
6736                 switch (dpll & DPLL_MODE_MASK) {
6737                 case DPLLB_MODE_DAC_SERIAL:
6738                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6739                                 5 : 10;
6740                         break;
6741                 case DPLLB_MODE_LVDS:
6742                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6743                                 7 : 14;
6744                         break;
6745                 default:
6746                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6747                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6748                         return 0;
6749                 }
6750
6751                 /* XXX: Handle the 100Mhz refclk */
6752                 intel_clock(dev, 96000, &clock);
6753         } else {
6754                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6755
6756                 if (is_lvds) {
6757                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6758                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6759                         clock.p2 = 14;
6760
6761                         if ((dpll & PLL_REF_INPUT_MASK) ==
6762                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6763                                 /* XXX: might not be 66MHz */
6764                                 intel_clock(dev, 66000, &clock);
6765                         } else
6766                                 intel_clock(dev, 48000, &clock);
6767                 } else {
6768                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6769                                 clock.p1 = 2;
6770                         else {
6771                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6772                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6773                         }
6774                         if (dpll & PLL_P2_DIVIDE_BY_4)
6775                                 clock.p2 = 4;
6776                         else
6777                                 clock.p2 = 2;
6778
6779                         intel_clock(dev, 48000, &clock);
6780                 }
6781         }
6782
6783         /* XXX: It would be nice to validate the clocks, but we can't reuse
6784          * i830PllIsValid() because it relies on the xf86_config connector
6785          * configuration being accurate, which it isn't necessarily.
6786          */
6787
6788         return clock.dot;
6789 }
6790
6791 /** Returns the currently programmed mode of the given pipe. */
6792 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6793                                              struct drm_crtc *crtc)
6794 {
6795         struct drm_i915_private *dev_priv = dev->dev_private;
6796         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6798         struct drm_display_mode *mode;
6799         int htot = I915_READ(HTOTAL(cpu_transcoder));
6800         int hsync = I915_READ(HSYNC(cpu_transcoder));
6801         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6802         int vsync = I915_READ(VSYNC(cpu_transcoder));
6803
6804         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6805         if (!mode)
6806                 return NULL;
6807
6808         mode->clock = intel_crtc_clock_get(dev, crtc);
6809         mode->hdisplay = (htot & 0xffff) + 1;
6810         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6811         mode->hsync_start = (hsync & 0xffff) + 1;
6812         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6813         mode->vdisplay = (vtot & 0xffff) + 1;
6814         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6815         mode->vsync_start = (vsync & 0xffff) + 1;
6816         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6817
6818         drm_mode_set_name(mode);
6819
6820         return mode;
6821 }
6822
6823 static void intel_increase_pllclock(struct drm_crtc *crtc)
6824 {
6825         struct drm_device *dev = crtc->dev;
6826         drm_i915_private_t *dev_priv = dev->dev_private;
6827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6828         int pipe = intel_crtc->pipe;
6829         int dpll_reg = DPLL(pipe);
6830         int dpll;
6831
6832         if (HAS_PCH_SPLIT(dev))
6833                 return;
6834
6835         if (!dev_priv->lvds_downclock_avail)
6836                 return;
6837
6838         dpll = I915_READ(dpll_reg);
6839         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6840                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6841
6842                 assert_panel_unlocked(dev_priv, pipe);
6843
6844                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6845                 I915_WRITE(dpll_reg, dpll);
6846                 intel_wait_for_vblank(dev, pipe);
6847
6848                 dpll = I915_READ(dpll_reg);
6849                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6850                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6851         }
6852 }
6853
6854 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6855 {
6856         struct drm_device *dev = crtc->dev;
6857         drm_i915_private_t *dev_priv = dev->dev_private;
6858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859
6860         if (HAS_PCH_SPLIT(dev))
6861                 return;
6862
6863         if (!dev_priv->lvds_downclock_avail)
6864                 return;
6865
6866         /*
6867          * Since this is called by a timer, we should never get here in
6868          * the manual case.
6869          */
6870         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6871                 int pipe = intel_crtc->pipe;
6872                 int dpll_reg = DPLL(pipe);
6873                 int dpll;
6874
6875                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6876
6877                 assert_panel_unlocked(dev_priv, pipe);
6878
6879                 dpll = I915_READ(dpll_reg);
6880                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6881                 I915_WRITE(dpll_reg, dpll);
6882                 intel_wait_for_vblank(dev, pipe);
6883                 dpll = I915_READ(dpll_reg);
6884                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6885                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6886         }
6887
6888 }
6889
6890 void intel_mark_busy(struct drm_device *dev)
6891 {
6892         i915_update_gfx_val(dev->dev_private);
6893 }
6894
6895 void intel_mark_idle(struct drm_device *dev)
6896 {
6897         struct drm_crtc *crtc;
6898
6899         if (!i915_powersave)
6900                 return;
6901
6902         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6903                 if (!crtc->fb)
6904                         continue;
6905
6906                 intel_decrease_pllclock(crtc);
6907         }
6908 }
6909
6910 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6911 {
6912         struct drm_device *dev = obj->base.dev;
6913         struct drm_crtc *crtc;
6914
6915         if (!i915_powersave)
6916                 return;
6917
6918         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6919                 if (!crtc->fb)
6920                         continue;
6921
6922                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6923                         intel_increase_pllclock(crtc);
6924         }
6925 }
6926
6927 static void intel_crtc_destroy(struct drm_crtc *crtc)
6928 {
6929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6930         struct drm_device *dev = crtc->dev;
6931         struct intel_unpin_work *work;
6932         unsigned long flags;
6933
6934         spin_lock_irqsave(&dev->event_lock, flags);
6935         work = intel_crtc->unpin_work;
6936         intel_crtc->unpin_work = NULL;
6937         spin_unlock_irqrestore(&dev->event_lock, flags);
6938
6939         if (work) {
6940                 cancel_work_sync(&work->work);
6941                 kfree(work);
6942         }
6943
6944         drm_crtc_cleanup(crtc);
6945
6946         kfree(intel_crtc);
6947 }
6948
6949 static void intel_unpin_work_fn(struct work_struct *__work)
6950 {
6951         struct intel_unpin_work *work =
6952                 container_of(__work, struct intel_unpin_work, work);
6953         struct drm_device *dev = work->crtc->dev;
6954
6955         mutex_lock(&dev->struct_mutex);
6956         intel_unpin_fb_obj(work->old_fb_obj);
6957         drm_gem_object_unreference(&work->pending_flip_obj->base);
6958         drm_gem_object_unreference(&work->old_fb_obj->base);
6959
6960         intel_update_fbc(dev);
6961         mutex_unlock(&dev->struct_mutex);
6962
6963         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6964         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6965
6966         kfree(work);
6967 }
6968
6969 static void do_intel_finish_page_flip(struct drm_device *dev,
6970                                       struct drm_crtc *crtc)
6971 {
6972         drm_i915_private_t *dev_priv = dev->dev_private;
6973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6974         struct intel_unpin_work *work;
6975         unsigned long flags;
6976
6977         /* Ignore early vblank irqs */
6978         if (intel_crtc == NULL)
6979                 return;
6980
6981         spin_lock_irqsave(&dev->event_lock, flags);
6982         work = intel_crtc->unpin_work;
6983
6984         /* Ensure we don't miss a work->pending update ... */
6985         smp_rmb();
6986
6987         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6988                 spin_unlock_irqrestore(&dev->event_lock, flags);
6989                 return;
6990         }
6991
6992         /* and that the unpin work is consistent wrt ->pending. */
6993         smp_rmb();
6994
6995         intel_crtc->unpin_work = NULL;
6996
6997         if (work->event)
6998                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6999
7000         drm_vblank_put(dev, intel_crtc->pipe);
7001
7002         spin_unlock_irqrestore(&dev->event_lock, flags);
7003
7004         wake_up_all(&dev_priv->pending_flip_queue);
7005
7006         queue_work(dev_priv->wq, &work->work);
7007
7008         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7009 }
7010
7011 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7012 {
7013         drm_i915_private_t *dev_priv = dev->dev_private;
7014         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7015
7016         do_intel_finish_page_flip(dev, crtc);
7017 }
7018
7019 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7020 {
7021         drm_i915_private_t *dev_priv = dev->dev_private;
7022         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7023
7024         do_intel_finish_page_flip(dev, crtc);
7025 }
7026
7027 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7028 {
7029         drm_i915_private_t *dev_priv = dev->dev_private;
7030         struct intel_crtc *intel_crtc =
7031                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7032         unsigned long flags;
7033
7034         /* NB: An MMIO update of the plane base pointer will also
7035          * generate a page-flip completion irq, i.e. every modeset
7036          * is also accompanied by a spurious intel_prepare_page_flip().
7037          */
7038         spin_lock_irqsave(&dev->event_lock, flags);
7039         if (intel_crtc->unpin_work)
7040                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7041         spin_unlock_irqrestore(&dev->event_lock, flags);
7042 }
7043
7044 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7045 {
7046         /* Ensure that the work item is consistent when activating it ... */
7047         smp_wmb();
7048         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7049         /* and that it is marked active as soon as the irq could fire. */
7050         smp_wmb();
7051 }
7052
7053 static int intel_gen2_queue_flip(struct drm_device *dev,
7054                                  struct drm_crtc *crtc,
7055                                  struct drm_framebuffer *fb,
7056                                  struct drm_i915_gem_object *obj)
7057 {
7058         struct drm_i915_private *dev_priv = dev->dev_private;
7059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7060         u32 flip_mask;
7061         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7062         int ret;
7063
7064         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7065         if (ret)
7066                 goto err;
7067
7068         ret = intel_ring_begin(ring, 6);
7069         if (ret)
7070                 goto err_unpin;
7071
7072         /* Can't queue multiple flips, so wait for the previous
7073          * one to finish before executing the next.
7074          */
7075         if (intel_crtc->plane)
7076                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7077         else
7078                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7079         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7080         intel_ring_emit(ring, MI_NOOP);
7081         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7082                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7083         intel_ring_emit(ring, fb->pitches[0]);
7084         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7085         intel_ring_emit(ring, 0); /* aux display base address, unused */
7086
7087         intel_mark_page_flip_active(intel_crtc);
7088         intel_ring_advance(ring);
7089         return 0;
7090
7091 err_unpin:
7092         intel_unpin_fb_obj(obj);
7093 err:
7094         return ret;
7095 }
7096
7097 static int intel_gen3_queue_flip(struct drm_device *dev,
7098                                  struct drm_crtc *crtc,
7099                                  struct drm_framebuffer *fb,
7100                                  struct drm_i915_gem_object *obj)
7101 {
7102         struct drm_i915_private *dev_priv = dev->dev_private;
7103         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7104         u32 flip_mask;
7105         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7106         int ret;
7107
7108         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7109         if (ret)
7110                 goto err;
7111
7112         ret = intel_ring_begin(ring, 6);
7113         if (ret)
7114                 goto err_unpin;
7115
7116         if (intel_crtc->plane)
7117                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7118         else
7119                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7120         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7121         intel_ring_emit(ring, MI_NOOP);
7122         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7123                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7124         intel_ring_emit(ring, fb->pitches[0]);
7125         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7126         intel_ring_emit(ring, MI_NOOP);
7127
7128         intel_mark_page_flip_active(intel_crtc);
7129         intel_ring_advance(ring);
7130         return 0;
7131
7132 err_unpin:
7133         intel_unpin_fb_obj(obj);
7134 err:
7135         return ret;
7136 }
7137
7138 static int intel_gen4_queue_flip(struct drm_device *dev,
7139                                  struct drm_crtc *crtc,
7140                                  struct drm_framebuffer *fb,
7141                                  struct drm_i915_gem_object *obj)
7142 {
7143         struct drm_i915_private *dev_priv = dev->dev_private;
7144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7145         uint32_t pf, pipesrc;
7146         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7147         int ret;
7148
7149         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7150         if (ret)
7151                 goto err;
7152
7153         ret = intel_ring_begin(ring, 4);
7154         if (ret)
7155                 goto err_unpin;
7156
7157         /* i965+ uses the linear or tiled offsets from the
7158          * Display Registers (which do not change across a page-flip)
7159          * so we need only reprogram the base address.
7160          */
7161         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7162                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7163         intel_ring_emit(ring, fb->pitches[0]);
7164         intel_ring_emit(ring,
7165                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7166                         obj->tiling_mode);
7167
7168         /* XXX Enabling the panel-fitter across page-flip is so far
7169          * untested on non-native modes, so ignore it for now.
7170          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7171          */
7172         pf = 0;
7173         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7174         intel_ring_emit(ring, pf | pipesrc);
7175
7176         intel_mark_page_flip_active(intel_crtc);
7177         intel_ring_advance(ring);
7178         return 0;
7179
7180 err_unpin:
7181         intel_unpin_fb_obj(obj);
7182 err:
7183         return ret;
7184 }
7185
7186 static int intel_gen6_queue_flip(struct drm_device *dev,
7187                                  struct drm_crtc *crtc,
7188                                  struct drm_framebuffer *fb,
7189                                  struct drm_i915_gem_object *obj)
7190 {
7191         struct drm_i915_private *dev_priv = dev->dev_private;
7192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7193         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7194         uint32_t pf, pipesrc;
7195         int ret;
7196
7197         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7198         if (ret)
7199                 goto err;
7200
7201         ret = intel_ring_begin(ring, 4);
7202         if (ret)
7203                 goto err_unpin;
7204
7205         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7206                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7207         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7208         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7209
7210         /* Contrary to the suggestions in the documentation,
7211          * "Enable Panel Fitter" does not seem to be required when page
7212          * flipping with a non-native mode, and worse causes a normal
7213          * modeset to fail.
7214          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7215          */
7216         pf = 0;
7217         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7218         intel_ring_emit(ring, pf | pipesrc);
7219
7220         intel_mark_page_flip_active(intel_crtc);
7221         intel_ring_advance(ring);
7222         return 0;
7223
7224 err_unpin:
7225         intel_unpin_fb_obj(obj);
7226 err:
7227         return ret;
7228 }
7229
7230 /*
7231  * On gen7 we currently use the blit ring because (in early silicon at least)
7232  * the render ring doesn't give us interrpts for page flip completion, which
7233  * means clients will hang after the first flip is queued.  Fortunately the
7234  * blit ring generates interrupts properly, so use it instead.
7235  */
7236 static int intel_gen7_queue_flip(struct drm_device *dev,
7237                                  struct drm_crtc *crtc,
7238                                  struct drm_framebuffer *fb,
7239                                  struct drm_i915_gem_object *obj)
7240 {
7241         struct drm_i915_private *dev_priv = dev->dev_private;
7242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7243         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7244         uint32_t plane_bit = 0;
7245         int ret;
7246
7247         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7248         if (ret)
7249                 goto err;
7250
7251         switch(intel_crtc->plane) {
7252         case PLANE_A:
7253                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7254                 break;
7255         case PLANE_B:
7256                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7257                 break;
7258         case PLANE_C:
7259                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7260                 break;
7261         default:
7262                 WARN_ONCE(1, "unknown plane in flip command\n");
7263                 ret = -ENODEV;
7264                 goto err_unpin;
7265         }
7266
7267         ret = intel_ring_begin(ring, 4);
7268         if (ret)
7269                 goto err_unpin;
7270
7271         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7272         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7273         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7274         intel_ring_emit(ring, (MI_NOOP));
7275
7276         intel_mark_page_flip_active(intel_crtc);
7277         intel_ring_advance(ring);
7278         return 0;
7279
7280 err_unpin:
7281         intel_unpin_fb_obj(obj);
7282 err:
7283         return ret;
7284 }
7285
7286 static int intel_default_queue_flip(struct drm_device *dev,
7287                                     struct drm_crtc *crtc,
7288                                     struct drm_framebuffer *fb,
7289                                     struct drm_i915_gem_object *obj)
7290 {
7291         return -ENODEV;
7292 }
7293
7294 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7295                                 struct drm_framebuffer *fb,
7296                                 struct drm_pending_vblank_event *event)
7297 {
7298         struct drm_device *dev = crtc->dev;
7299         struct drm_i915_private *dev_priv = dev->dev_private;
7300         struct intel_framebuffer *intel_fb;
7301         struct drm_i915_gem_object *obj;
7302         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7303         struct intel_unpin_work *work;
7304         unsigned long flags;
7305         int ret;
7306
7307         /* Can't change pixel format via MI display flips. */
7308         if (fb->pixel_format != crtc->fb->pixel_format)
7309                 return -EINVAL;
7310
7311         /*
7312          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7313          * Note that pitch changes could also affect these register.
7314          */
7315         if (INTEL_INFO(dev)->gen > 3 &&
7316             (fb->offsets[0] != crtc->fb->offsets[0] ||
7317              fb->pitches[0] != crtc->fb->pitches[0]))
7318                 return -EINVAL;
7319
7320         work = kzalloc(sizeof *work, GFP_KERNEL);
7321         if (work == NULL)
7322                 return -ENOMEM;
7323
7324         work->event = event;
7325         work->crtc = crtc;
7326         intel_fb = to_intel_framebuffer(crtc->fb);
7327         work->old_fb_obj = intel_fb->obj;
7328         INIT_WORK(&work->work, intel_unpin_work_fn);
7329
7330         ret = drm_vblank_get(dev, intel_crtc->pipe);
7331         if (ret)
7332                 goto free_work;
7333
7334         /* We borrow the event spin lock for protecting unpin_work */
7335         spin_lock_irqsave(&dev->event_lock, flags);
7336         if (intel_crtc->unpin_work) {
7337                 spin_unlock_irqrestore(&dev->event_lock, flags);
7338                 kfree(work);
7339                 drm_vblank_put(dev, intel_crtc->pipe);
7340
7341                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7342                 return -EBUSY;
7343         }
7344         intel_crtc->unpin_work = work;
7345         spin_unlock_irqrestore(&dev->event_lock, flags);
7346
7347         intel_fb = to_intel_framebuffer(fb);
7348         obj = intel_fb->obj;
7349
7350         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7351                 flush_workqueue(dev_priv->wq);
7352
7353         ret = i915_mutex_lock_interruptible(dev);
7354         if (ret)
7355                 goto cleanup;
7356
7357         /* Reference the objects for the scheduled work. */
7358         drm_gem_object_reference(&work->old_fb_obj->base);
7359         drm_gem_object_reference(&obj->base);
7360
7361         crtc->fb = fb;
7362
7363         work->pending_flip_obj = obj;
7364
7365         work->enable_stall_check = true;
7366
7367         atomic_inc(&intel_crtc->unpin_work_count);
7368         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7369
7370         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7371         if (ret)
7372                 goto cleanup_pending;
7373
7374         intel_disable_fbc(dev);
7375         intel_mark_fb_busy(obj);
7376         mutex_unlock(&dev->struct_mutex);
7377
7378         trace_i915_flip_request(intel_crtc->plane, obj);
7379
7380         return 0;
7381
7382 cleanup_pending:
7383         atomic_dec(&intel_crtc->unpin_work_count);
7384         drm_gem_object_unreference(&work->old_fb_obj->base);
7385         drm_gem_object_unreference(&obj->base);
7386         mutex_unlock(&dev->struct_mutex);
7387
7388 cleanup:
7389         spin_lock_irqsave(&dev->event_lock, flags);
7390         intel_crtc->unpin_work = NULL;
7391         spin_unlock_irqrestore(&dev->event_lock, flags);
7392
7393         drm_vblank_put(dev, intel_crtc->pipe);
7394 free_work:
7395         kfree(work);
7396
7397         return ret;
7398 }
7399
7400 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7401         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7402         .load_lut = intel_crtc_load_lut,
7403         .disable = intel_crtc_noop,
7404 };
7405
7406 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7407 {
7408         struct intel_encoder *other_encoder;
7409         struct drm_crtc *crtc = &encoder->new_crtc->base;
7410
7411         if (WARN_ON(!crtc))
7412                 return false;
7413
7414         list_for_each_entry(other_encoder,
7415                             &crtc->dev->mode_config.encoder_list,
7416                             base.head) {
7417
7418                 if (&other_encoder->new_crtc->base != crtc ||
7419                     encoder == other_encoder)
7420                         continue;
7421                 else
7422                         return true;
7423         }
7424
7425         return false;
7426 }
7427
7428 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7429                                   struct drm_crtc *crtc)
7430 {
7431         struct drm_device *dev;
7432         struct drm_crtc *tmp;
7433         int crtc_mask = 1;
7434
7435         WARN(!crtc, "checking null crtc?\n");
7436
7437         dev = crtc->dev;
7438
7439         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7440                 if (tmp == crtc)
7441                         break;
7442                 crtc_mask <<= 1;
7443         }
7444
7445         if (encoder->possible_crtcs & crtc_mask)
7446                 return true;
7447         return false;
7448 }
7449
7450 /**
7451  * intel_modeset_update_staged_output_state
7452  *
7453  * Updates the staged output configuration state, e.g. after we've read out the
7454  * current hw state.
7455  */
7456 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7457 {
7458         struct intel_encoder *encoder;
7459         struct intel_connector *connector;
7460
7461         list_for_each_entry(connector, &dev->mode_config.connector_list,
7462                             base.head) {
7463                 connector->new_encoder =
7464                         to_intel_encoder(connector->base.encoder);
7465         }
7466
7467         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7468                             base.head) {
7469                 encoder->new_crtc =
7470                         to_intel_crtc(encoder->base.crtc);
7471         }
7472 }
7473
7474 /**
7475  * intel_modeset_commit_output_state
7476  *
7477  * This function copies the stage display pipe configuration to the real one.
7478  */
7479 static void intel_modeset_commit_output_state(struct drm_device *dev)
7480 {
7481         struct intel_encoder *encoder;
7482         struct intel_connector *connector;
7483
7484         list_for_each_entry(connector, &dev->mode_config.connector_list,
7485                             base.head) {
7486                 connector->base.encoder = &connector->new_encoder->base;
7487         }
7488
7489         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7490                             base.head) {
7491                 encoder->base.crtc = &encoder->new_crtc->base;
7492         }
7493 }
7494
7495 static struct drm_display_mode *
7496 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7497                             struct drm_display_mode *mode)
7498 {
7499         struct drm_device *dev = crtc->dev;
7500         struct drm_display_mode *adjusted_mode;
7501         struct drm_encoder_helper_funcs *encoder_funcs;
7502         struct intel_encoder *encoder;
7503
7504         adjusted_mode = drm_mode_duplicate(dev, mode);
7505         if (!adjusted_mode)
7506                 return ERR_PTR(-ENOMEM);
7507
7508         /* Pass our mode to the connectors and the CRTC to give them a chance to
7509          * adjust it according to limitations or connector properties, and also
7510          * a chance to reject the mode entirely.
7511          */
7512         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7513                             base.head) {
7514
7515                 if (&encoder->new_crtc->base != crtc)
7516                         continue;
7517                 encoder_funcs = encoder->base.helper_private;
7518                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7519                                                 adjusted_mode))) {
7520                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7521                         goto fail;
7522                 }
7523         }
7524
7525         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7526                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7527                 goto fail;
7528         }
7529         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7530
7531         return adjusted_mode;
7532 fail:
7533         drm_mode_destroy(dev, adjusted_mode);
7534         return ERR_PTR(-EINVAL);
7535 }
7536
7537 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7538  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7539 static void
7540 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7541                              unsigned *prepare_pipes, unsigned *disable_pipes)
7542 {
7543         struct intel_crtc *intel_crtc;
7544         struct drm_device *dev = crtc->dev;
7545         struct intel_encoder *encoder;
7546         struct intel_connector *connector;
7547         struct drm_crtc *tmp_crtc;
7548
7549         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7550
7551         /* Check which crtcs have changed outputs connected to them, these need
7552          * to be part of the prepare_pipes mask. We don't (yet) support global
7553          * modeset across multiple crtcs, so modeset_pipes will only have one
7554          * bit set at most. */
7555         list_for_each_entry(connector, &dev->mode_config.connector_list,
7556                             base.head) {
7557                 if (connector->base.encoder == &connector->new_encoder->base)
7558                         continue;
7559
7560                 if (connector->base.encoder) {
7561                         tmp_crtc = connector->base.encoder->crtc;
7562
7563                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7564                 }
7565
7566                 if (connector->new_encoder)
7567                         *prepare_pipes |=
7568                                 1 << connector->new_encoder->new_crtc->pipe;
7569         }
7570
7571         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7572                             base.head) {
7573                 if (encoder->base.crtc == &encoder->new_crtc->base)
7574                         continue;
7575
7576                 if (encoder->base.crtc) {
7577                         tmp_crtc = encoder->base.crtc;
7578
7579                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7580                 }
7581
7582                 if (encoder->new_crtc)
7583                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7584         }
7585
7586         /* Check for any pipes that will be fully disabled ... */
7587         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7588                             base.head) {
7589                 bool used = false;
7590
7591                 /* Don't try to disable disabled crtcs. */
7592                 if (!intel_crtc->base.enabled)
7593                         continue;
7594
7595                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7596                                     base.head) {
7597                         if (encoder->new_crtc == intel_crtc)
7598                                 used = true;
7599                 }
7600
7601                 if (!used)
7602                         *disable_pipes |= 1 << intel_crtc->pipe;
7603         }
7604
7605
7606         /* set_mode is also used to update properties on life display pipes. */
7607         intel_crtc = to_intel_crtc(crtc);
7608         if (crtc->enabled)
7609                 *prepare_pipes |= 1 << intel_crtc->pipe;
7610
7611         /* We only support modeset on one single crtc, hence we need to do that
7612          * only for the passed in crtc iff we change anything else than just
7613          * disable crtcs.
7614          *
7615          * This is actually not true, to be fully compatible with the old crtc
7616          * helper we automatically disable _any_ output (i.e. doesn't need to be
7617          * connected to the crtc we're modesetting on) if it's disconnected.
7618          * Which is a rather nutty api (since changed the output configuration
7619          * without userspace's explicit request can lead to confusion), but
7620          * alas. Hence we currently need to modeset on all pipes we prepare. */
7621         if (*prepare_pipes)
7622                 *modeset_pipes = *prepare_pipes;
7623
7624         /* ... and mask these out. */
7625         *modeset_pipes &= ~(*disable_pipes);
7626         *prepare_pipes &= ~(*disable_pipes);
7627 }
7628
7629 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7630 {
7631         struct drm_encoder *encoder;
7632         struct drm_device *dev = crtc->dev;
7633
7634         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7635                 if (encoder->crtc == crtc)
7636                         return true;
7637
7638         return false;
7639 }
7640
7641 static void
7642 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7643 {
7644         struct intel_encoder *intel_encoder;
7645         struct intel_crtc *intel_crtc;
7646         struct drm_connector *connector;
7647
7648         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7649                             base.head) {
7650                 if (!intel_encoder->base.crtc)
7651                         continue;
7652
7653                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7654
7655                 if (prepare_pipes & (1 << intel_crtc->pipe))
7656                         intel_encoder->connectors_active = false;
7657         }
7658
7659         intel_modeset_commit_output_state(dev);
7660
7661         /* Update computed state. */
7662         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7663                             base.head) {
7664                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7665         }
7666
7667         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7668                 if (!connector->encoder || !connector->encoder->crtc)
7669                         continue;
7670
7671                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7672
7673                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7674                         struct drm_property *dpms_property =
7675                                 dev->mode_config.dpms_property;
7676
7677                         connector->dpms = DRM_MODE_DPMS_ON;
7678                         drm_object_property_set_value(&connector->base,
7679                                                          dpms_property,
7680                                                          DRM_MODE_DPMS_ON);
7681
7682                         intel_encoder = to_intel_encoder(connector->encoder);
7683                         intel_encoder->connectors_active = true;
7684                 }
7685         }
7686
7687 }
7688
7689 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7690         list_for_each_entry((intel_crtc), \
7691                             &(dev)->mode_config.crtc_list, \
7692                             base.head) \
7693                 if (mask & (1 <<(intel_crtc)->pipe)) \
7694
7695 void
7696 intel_modeset_check_state(struct drm_device *dev)
7697 {
7698         struct intel_crtc *crtc;
7699         struct intel_encoder *encoder;
7700         struct intel_connector *connector;
7701
7702         list_for_each_entry(connector, &dev->mode_config.connector_list,
7703                             base.head) {
7704                 /* This also checks the encoder/connector hw state with the
7705                  * ->get_hw_state callbacks. */
7706                 intel_connector_check_state(connector);
7707
7708                 WARN(&connector->new_encoder->base != connector->base.encoder,
7709                      "connector's staged encoder doesn't match current encoder\n");
7710         }
7711
7712         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7713                             base.head) {
7714                 bool enabled = false;
7715                 bool active = false;
7716                 enum pipe pipe, tracked_pipe;
7717
7718                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7719                               encoder->base.base.id,
7720                               drm_get_encoder_name(&encoder->base));
7721
7722                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7723                      "encoder's stage crtc doesn't match current crtc\n");
7724                 WARN(encoder->connectors_active && !encoder->base.crtc,
7725                      "encoder's active_connectors set, but no crtc\n");
7726
7727                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7728                                     base.head) {
7729                         if (connector->base.encoder != &encoder->base)
7730                                 continue;
7731                         enabled = true;
7732                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7733                                 active = true;
7734                 }
7735                 WARN(!!encoder->base.crtc != enabled,
7736                      "encoder's enabled state mismatch "
7737                      "(expected %i, found %i)\n",
7738                      !!encoder->base.crtc, enabled);
7739                 WARN(active && !encoder->base.crtc,
7740                      "active encoder with no crtc\n");
7741
7742                 WARN(encoder->connectors_active != active,
7743                      "encoder's computed active state doesn't match tracked active state "
7744                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7745
7746                 active = encoder->get_hw_state(encoder, &pipe);
7747                 WARN(active != encoder->connectors_active,
7748                      "encoder's hw state doesn't match sw tracking "
7749                      "(expected %i, found %i)\n",
7750                      encoder->connectors_active, active);
7751
7752                 if (!encoder->base.crtc)
7753                         continue;
7754
7755                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7756                 WARN(active && pipe != tracked_pipe,
7757                      "active encoder's pipe doesn't match"
7758                      "(expected %i, found %i)\n",
7759                      tracked_pipe, pipe);
7760
7761         }
7762
7763         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7764                             base.head) {
7765                 bool enabled = false;
7766                 bool active = false;
7767
7768                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7769                               crtc->base.base.id);
7770
7771                 WARN(crtc->active && !crtc->base.enabled,
7772                      "active crtc, but not enabled in sw tracking\n");
7773
7774                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7775                                     base.head) {
7776                         if (encoder->base.crtc != &crtc->base)
7777                                 continue;
7778                         enabled = true;
7779                         if (encoder->connectors_active)
7780                                 active = true;
7781                 }
7782                 WARN(active != crtc->active,
7783                      "crtc's computed active state doesn't match tracked active state "
7784                      "(expected %i, found %i)\n", active, crtc->active);
7785                 WARN(enabled != crtc->base.enabled,
7786                      "crtc's computed enabled state doesn't match tracked enabled state "
7787                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7788
7789                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7790         }
7791 }
7792
7793 int intel_set_mode(struct drm_crtc *crtc,
7794                    struct drm_display_mode *mode,
7795                    int x, int y, struct drm_framebuffer *fb)
7796 {
7797         struct drm_device *dev = crtc->dev;
7798         drm_i915_private_t *dev_priv = dev->dev_private;
7799         struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
7800         struct intel_crtc *intel_crtc;
7801         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7802         int ret = 0;
7803
7804         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
7805         if (!saved_mode)
7806                 return -ENOMEM;
7807         saved_hwmode = saved_mode + 1;
7808
7809         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7810                                      &prepare_pipes, &disable_pipes);
7811
7812         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7813                       modeset_pipes, prepare_pipes, disable_pipes);
7814
7815         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7816                 intel_crtc_disable(&intel_crtc->base);
7817
7818         *saved_hwmode = crtc->hwmode;
7819         *saved_mode = crtc->mode;
7820
7821         /* Hack: Because we don't (yet) support global modeset on multiple
7822          * crtcs, we don't keep track of the new mode for more than one crtc.
7823          * Hence simply check whether any bit is set in modeset_pipes in all the
7824          * pieces of code that are not yet converted to deal with mutliple crtcs
7825          * changing their mode at the same time. */
7826         adjusted_mode = NULL;
7827         if (modeset_pipes) {
7828                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7829                 if (IS_ERR(adjusted_mode)) {
7830                         ret = PTR_ERR(adjusted_mode);
7831                         goto out;
7832                 }
7833         }
7834
7835         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7836                 if (intel_crtc->base.enabled)
7837                         dev_priv->display.crtc_disable(&intel_crtc->base);
7838         }
7839
7840         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7841          * to set it here already despite that we pass it down the callchain.
7842          */
7843         if (modeset_pipes)
7844                 crtc->mode = *mode;
7845
7846         /* Only after disabling all output pipelines that will be changed can we
7847          * update the the output configuration. */
7848         intel_modeset_update_state(dev, prepare_pipes);
7849
7850         if (dev_priv->display.modeset_global_resources)
7851                 dev_priv->display.modeset_global_resources(dev);
7852
7853         /* Set up the DPLL and any encoders state that needs to adjust or depend
7854          * on the DPLL.
7855          */
7856         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7857                 ret = intel_crtc_mode_set(&intel_crtc->base,
7858                                           mode, adjusted_mode,
7859                                           x, y, fb);
7860                 if (ret)
7861                         goto done;
7862         }
7863
7864         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7865         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7866                 dev_priv->display.crtc_enable(&intel_crtc->base);
7867
7868         if (modeset_pipes) {
7869                 /* Store real post-adjustment hardware mode. */
7870                 crtc->hwmode = *adjusted_mode;
7871
7872                 /* Calculate and store various constants which
7873                  * are later needed by vblank and swap-completion
7874                  * timestamping. They are derived from true hwmode.
7875                  */
7876                 drm_calc_timestamping_constants(crtc);
7877         }
7878
7879         /* FIXME: add subpixel order */
7880 done:
7881         drm_mode_destroy(dev, adjusted_mode);
7882         if (ret && crtc->enabled) {
7883                 crtc->hwmode = *saved_hwmode;
7884                 crtc->mode = *saved_mode;
7885         } else {
7886                 intel_modeset_check_state(dev);
7887         }
7888
7889 out:
7890         kfree(saved_mode);
7891         return ret;
7892 }
7893
7894 void intel_crtc_restore_mode(struct drm_crtc *crtc)
7895 {
7896         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7897 }
7898
7899 #undef for_each_intel_crtc_masked
7900
7901 static void intel_set_config_free(struct intel_set_config *config)
7902 {
7903         if (!config)
7904                 return;
7905
7906         kfree(config->save_connector_encoders);
7907         kfree(config->save_encoder_crtcs);
7908         kfree(config);
7909 }
7910
7911 static int intel_set_config_save_state(struct drm_device *dev,
7912                                        struct intel_set_config *config)
7913 {
7914         struct drm_encoder *encoder;
7915         struct drm_connector *connector;
7916         int count;
7917
7918         config->save_encoder_crtcs =
7919                 kcalloc(dev->mode_config.num_encoder,
7920                         sizeof(struct drm_crtc *), GFP_KERNEL);
7921         if (!config->save_encoder_crtcs)
7922                 return -ENOMEM;
7923
7924         config->save_connector_encoders =
7925                 kcalloc(dev->mode_config.num_connector,
7926                         sizeof(struct drm_encoder *), GFP_KERNEL);
7927         if (!config->save_connector_encoders)
7928                 return -ENOMEM;
7929
7930         /* Copy data. Note that driver private data is not affected.
7931          * Should anything bad happen only the expected state is
7932          * restored, not the drivers personal bookkeeping.
7933          */
7934         count = 0;
7935         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7936                 config->save_encoder_crtcs[count++] = encoder->crtc;
7937         }
7938
7939         count = 0;
7940         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7941                 config->save_connector_encoders[count++] = connector->encoder;
7942         }
7943
7944         return 0;
7945 }
7946
7947 static void intel_set_config_restore_state(struct drm_device *dev,
7948                                            struct intel_set_config *config)
7949 {
7950         struct intel_encoder *encoder;
7951         struct intel_connector *connector;
7952         int count;
7953
7954         count = 0;
7955         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7956                 encoder->new_crtc =
7957                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7958         }
7959
7960         count = 0;
7961         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7962                 connector->new_encoder =
7963                         to_intel_encoder(config->save_connector_encoders[count++]);
7964         }
7965 }
7966
7967 static void
7968 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7969                                       struct intel_set_config *config)
7970 {
7971
7972         /* We should be able to check here if the fb has the same properties
7973          * and then just flip_or_move it */
7974         if (set->crtc->fb != set->fb) {
7975                 /* If we have no fb then treat it as a full mode set */
7976                 if (set->crtc->fb == NULL) {
7977                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7978                         config->mode_changed = true;
7979                 } else if (set->fb == NULL) {
7980                         config->mode_changed = true;
7981                 } else if (set->fb->depth != set->crtc->fb->depth) {
7982                         config->mode_changed = true;
7983                 } else if (set->fb->bits_per_pixel !=
7984                            set->crtc->fb->bits_per_pixel) {
7985                         config->mode_changed = true;
7986                 } else
7987                         config->fb_changed = true;
7988         }
7989
7990         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7991                 config->fb_changed = true;
7992
7993         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7994                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7995                 drm_mode_debug_printmodeline(&set->crtc->mode);
7996                 drm_mode_debug_printmodeline(set->mode);
7997                 config->mode_changed = true;
7998         }
7999 }
8000
8001 static int
8002 intel_modeset_stage_output_state(struct drm_device *dev,
8003                                  struct drm_mode_set *set,
8004                                  struct intel_set_config *config)
8005 {
8006         struct drm_crtc *new_crtc;
8007         struct intel_connector *connector;
8008         struct intel_encoder *encoder;
8009         int count, ro;
8010
8011         /* The upper layers ensure that we either disable a crtc or have a list
8012          * of connectors. For paranoia, double-check this. */
8013         WARN_ON(!set->fb && (set->num_connectors != 0));
8014         WARN_ON(set->fb && (set->num_connectors == 0));
8015
8016         count = 0;
8017         list_for_each_entry(connector, &dev->mode_config.connector_list,
8018                             base.head) {
8019                 /* Otherwise traverse passed in connector list and get encoders
8020                  * for them. */
8021                 for (ro = 0; ro < set->num_connectors; ro++) {
8022                         if (set->connectors[ro] == &connector->base) {
8023                                 connector->new_encoder = connector->encoder;
8024                                 break;
8025                         }
8026                 }
8027
8028                 /* If we disable the crtc, disable all its connectors. Also, if
8029                  * the connector is on the changing crtc but not on the new
8030                  * connector list, disable it. */
8031                 if ((!set->fb || ro == set->num_connectors) &&
8032                     connector->base.encoder &&
8033                     connector->base.encoder->crtc == set->crtc) {
8034                         connector->new_encoder = NULL;
8035
8036                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8037                                 connector->base.base.id,
8038                                 drm_get_connector_name(&connector->base));
8039                 }
8040
8041
8042                 if (&connector->new_encoder->base != connector->base.encoder) {
8043                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8044                         config->mode_changed = true;
8045                 }
8046         }
8047         /* connector->new_encoder is now updated for all connectors. */
8048
8049         /* Update crtc of enabled connectors. */
8050         count = 0;
8051         list_for_each_entry(connector, &dev->mode_config.connector_list,
8052                             base.head) {
8053                 if (!connector->new_encoder)
8054                         continue;
8055
8056                 new_crtc = connector->new_encoder->base.crtc;
8057
8058                 for (ro = 0; ro < set->num_connectors; ro++) {
8059                         if (set->connectors[ro] == &connector->base)
8060                                 new_crtc = set->crtc;
8061                 }
8062
8063                 /* Make sure the new CRTC will work with the encoder */
8064                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8065                                            new_crtc)) {
8066                         return -EINVAL;
8067                 }
8068                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8069
8070                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8071                         connector->base.base.id,
8072                         drm_get_connector_name(&connector->base),
8073                         new_crtc->base.id);
8074         }
8075
8076         /* Check for any encoders that needs to be disabled. */
8077         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8078                             base.head) {
8079                 list_for_each_entry(connector,
8080                                     &dev->mode_config.connector_list,
8081                                     base.head) {
8082                         if (connector->new_encoder == encoder) {
8083                                 WARN_ON(!connector->new_encoder->new_crtc);
8084
8085                                 goto next_encoder;
8086                         }
8087                 }
8088                 encoder->new_crtc = NULL;
8089 next_encoder:
8090                 /* Only now check for crtc changes so we don't miss encoders
8091                  * that will be disabled. */
8092                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8093                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8094                         config->mode_changed = true;
8095                 }
8096         }
8097         /* Now we've also updated encoder->new_crtc for all encoders. */
8098
8099         return 0;
8100 }
8101
8102 static int intel_crtc_set_config(struct drm_mode_set *set)
8103 {
8104         struct drm_device *dev;
8105         struct drm_mode_set save_set;
8106         struct intel_set_config *config;
8107         int ret;
8108
8109         BUG_ON(!set);
8110         BUG_ON(!set->crtc);
8111         BUG_ON(!set->crtc->helper_private);
8112
8113         if (!set->mode)
8114                 set->fb = NULL;
8115
8116         /* The fb helper likes to play gross jokes with ->mode_set_config.
8117          * Unfortunately the crtc helper doesn't do much at all for this case,
8118          * so we have to cope with this madness until the fb helper is fixed up. */
8119         if (set->fb && set->num_connectors == 0)
8120                 return 0;
8121
8122         if (set->fb) {
8123                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8124                                 set->crtc->base.id, set->fb->base.id,
8125                                 (int)set->num_connectors, set->x, set->y);
8126         } else {
8127                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8128         }
8129
8130         dev = set->crtc->dev;
8131
8132         ret = -ENOMEM;
8133         config = kzalloc(sizeof(*config), GFP_KERNEL);
8134         if (!config)
8135                 goto out_config;
8136
8137         ret = intel_set_config_save_state(dev, config);
8138         if (ret)
8139                 goto out_config;
8140
8141         save_set.crtc = set->crtc;
8142         save_set.mode = &set->crtc->mode;
8143         save_set.x = set->crtc->x;
8144         save_set.y = set->crtc->y;
8145         save_set.fb = set->crtc->fb;
8146
8147         /* Compute whether we need a full modeset, only an fb base update or no
8148          * change at all. In the future we might also check whether only the
8149          * mode changed, e.g. for LVDS where we only change the panel fitter in
8150          * such cases. */
8151         intel_set_config_compute_mode_changes(set, config);
8152
8153         ret = intel_modeset_stage_output_state(dev, set, config);
8154         if (ret)
8155                 goto fail;
8156
8157         if (config->mode_changed) {
8158                 if (set->mode) {
8159                         DRM_DEBUG_KMS("attempting to set mode from"
8160                                         " userspace\n");
8161                         drm_mode_debug_printmodeline(set->mode);
8162                 }
8163
8164                 ret = intel_set_mode(set->crtc, set->mode,
8165                                      set->x, set->y, set->fb);
8166                 if (ret) {
8167                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8168                                   set->crtc->base.id, ret);
8169                         goto fail;
8170                 }
8171         } else if (config->fb_changed) {
8172                 intel_crtc_wait_for_pending_flips(set->crtc);
8173
8174                 ret = intel_pipe_set_base(set->crtc,
8175                                           set->x, set->y, set->fb);
8176         }
8177
8178         intel_set_config_free(config);
8179
8180         return 0;
8181
8182 fail:
8183         intel_set_config_restore_state(dev, config);
8184
8185         /* Try to restore the config */
8186         if (config->mode_changed &&
8187             intel_set_mode(save_set.crtc, save_set.mode,
8188                            save_set.x, save_set.y, save_set.fb))
8189                 DRM_ERROR("failed to restore config after modeset failure\n");
8190
8191 out_config:
8192         intel_set_config_free(config);
8193         return ret;
8194 }
8195
8196 static const struct drm_crtc_funcs intel_crtc_funcs = {
8197         .cursor_set = intel_crtc_cursor_set,
8198         .cursor_move = intel_crtc_cursor_move,
8199         .gamma_set = intel_crtc_gamma_set,
8200         .set_config = intel_crtc_set_config,
8201         .destroy = intel_crtc_destroy,
8202         .page_flip = intel_crtc_page_flip,
8203 };
8204
8205 static void intel_cpu_pll_init(struct drm_device *dev)
8206 {
8207         if (HAS_DDI(dev))
8208                 intel_ddi_pll_init(dev);
8209 }
8210
8211 static void intel_pch_pll_init(struct drm_device *dev)
8212 {
8213         drm_i915_private_t *dev_priv = dev->dev_private;
8214         int i;
8215
8216         if (dev_priv->num_pch_pll == 0) {
8217                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8218                 return;
8219         }
8220
8221         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8222                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8223                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8224                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8225         }
8226 }
8227
8228 static void intel_crtc_init(struct drm_device *dev, int pipe)
8229 {
8230         drm_i915_private_t *dev_priv = dev->dev_private;
8231         struct intel_crtc *intel_crtc;
8232         int i;
8233
8234         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8235         if (intel_crtc == NULL)
8236                 return;
8237
8238         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8239
8240         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8241         for (i = 0; i < 256; i++) {
8242                 intel_crtc->lut_r[i] = i;
8243                 intel_crtc->lut_g[i] = i;
8244                 intel_crtc->lut_b[i] = i;
8245         }
8246
8247         /* Swap pipes & planes for FBC on pre-965 */
8248         intel_crtc->pipe = pipe;
8249         intel_crtc->plane = pipe;
8250         intel_crtc->cpu_transcoder = pipe;
8251         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8252                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8253                 intel_crtc->plane = !pipe;
8254         }
8255
8256         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8257                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8258         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8259         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8260
8261         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8262
8263         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8264 }
8265
8266 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8267                                 struct drm_file *file)
8268 {
8269         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8270         struct drm_mode_object *drmmode_obj;
8271         struct intel_crtc *crtc;
8272
8273         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8274                 return -ENODEV;
8275
8276         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8277                         DRM_MODE_OBJECT_CRTC);
8278
8279         if (!drmmode_obj) {
8280                 DRM_ERROR("no such CRTC id\n");
8281                 return -EINVAL;
8282         }
8283
8284         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8285         pipe_from_crtc_id->pipe = crtc->pipe;
8286
8287         return 0;
8288 }
8289
8290 static int intel_encoder_clones(struct intel_encoder *encoder)
8291 {
8292         struct drm_device *dev = encoder->base.dev;
8293         struct intel_encoder *source_encoder;
8294         int index_mask = 0;
8295         int entry = 0;
8296
8297         list_for_each_entry(source_encoder,
8298                             &dev->mode_config.encoder_list, base.head) {
8299
8300                 if (encoder == source_encoder)
8301                         index_mask |= (1 << entry);
8302
8303                 /* Intel hw has only one MUX where enocoders could be cloned. */
8304                 if (encoder->cloneable && source_encoder->cloneable)
8305                         index_mask |= (1 << entry);
8306
8307                 entry++;
8308         }
8309
8310         return index_mask;
8311 }
8312
8313 static bool has_edp_a(struct drm_device *dev)
8314 {
8315         struct drm_i915_private *dev_priv = dev->dev_private;
8316
8317         if (!IS_MOBILE(dev))
8318                 return false;
8319
8320         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8321                 return false;
8322
8323         if (IS_GEN5(dev) &&
8324             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8325                 return false;
8326
8327         return true;
8328 }
8329
8330 static void intel_setup_outputs(struct drm_device *dev)
8331 {
8332         struct drm_i915_private *dev_priv = dev->dev_private;
8333         struct intel_encoder *encoder;
8334         bool dpd_is_edp = false;
8335         bool has_lvds;
8336
8337         has_lvds = intel_lvds_init(dev);
8338         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8339                 /* disable the panel fitter on everything but LVDS */
8340                 I915_WRITE(PFIT_CONTROL, 0);
8341         }
8342
8343         if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8344                 intel_crt_init(dev);
8345
8346         if (HAS_DDI(dev)) {
8347                 int found;
8348
8349                 /* Haswell uses DDI functions to detect digital outputs */
8350                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8351                 /* DDI A only supports eDP */
8352                 if (found)
8353                         intel_ddi_init(dev, PORT_A);
8354
8355                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8356                  * register */
8357                 found = I915_READ(SFUSE_STRAP);
8358
8359                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8360                         intel_ddi_init(dev, PORT_B);
8361                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8362                         intel_ddi_init(dev, PORT_C);
8363                 if (found & SFUSE_STRAP_DDID_DETECTED)
8364                         intel_ddi_init(dev, PORT_D);
8365         } else if (HAS_PCH_SPLIT(dev)) {
8366                 int found;
8367                 dpd_is_edp = intel_dpd_is_edp(dev);
8368
8369                 if (has_edp_a(dev))
8370                         intel_dp_init(dev, DP_A, PORT_A);
8371
8372                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8373                         /* PCH SDVOB multiplex with HDMIB */
8374                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8375                         if (!found)
8376                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8377                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8378                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8379                 }
8380
8381                 if (I915_READ(HDMIC) & PORT_DETECTED)
8382                         intel_hdmi_init(dev, HDMIC, PORT_C);
8383
8384                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8385                         intel_hdmi_init(dev, HDMID, PORT_D);
8386
8387                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8388                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8389
8390                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8391                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8392         } else if (IS_VALLEYVIEW(dev)) {
8393                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8394                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8395                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8396
8397                 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8398                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8399                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8400                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8401                 }
8402
8403                 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8404                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
8405
8406         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8407                 bool found = false;
8408
8409                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8410                         DRM_DEBUG_KMS("probing SDVOB\n");
8411                         found = intel_sdvo_init(dev, SDVOB, true);
8412                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8413                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8414                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8415                         }
8416
8417                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8418                                 DRM_DEBUG_KMS("probing DP_B\n");
8419                                 intel_dp_init(dev, DP_B, PORT_B);
8420                         }
8421                 }
8422
8423                 /* Before G4X SDVOC doesn't have its own detect register */
8424
8425                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8426                         DRM_DEBUG_KMS("probing SDVOC\n");
8427                         found = intel_sdvo_init(dev, SDVOC, false);
8428                 }
8429
8430                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8431
8432                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8433                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8434                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8435                         }
8436                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8437                                 DRM_DEBUG_KMS("probing DP_C\n");
8438                                 intel_dp_init(dev, DP_C, PORT_C);
8439                         }
8440                 }
8441
8442                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8443                     (I915_READ(DP_D) & DP_DETECTED)) {
8444                         DRM_DEBUG_KMS("probing DP_D\n");
8445                         intel_dp_init(dev, DP_D, PORT_D);
8446                 }
8447         } else if (IS_GEN2(dev))
8448                 intel_dvo_init(dev);
8449
8450         if (SUPPORTS_TV(dev))
8451                 intel_tv_init(dev);
8452
8453         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8454                 encoder->base.possible_crtcs = encoder->crtc_mask;
8455                 encoder->base.possible_clones =
8456                         intel_encoder_clones(encoder);
8457         }
8458
8459         intel_init_pch_refclk(dev);
8460
8461         drm_helper_move_panel_connectors_to_head(dev);
8462 }
8463
8464 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8465 {
8466         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8467
8468         drm_framebuffer_cleanup(fb);
8469         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8470
8471         kfree(intel_fb);
8472 }
8473
8474 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8475                                                 struct drm_file *file,
8476                                                 unsigned int *handle)
8477 {
8478         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8479         struct drm_i915_gem_object *obj = intel_fb->obj;
8480
8481         return drm_gem_handle_create(file, &obj->base, handle);
8482 }
8483
8484 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8485         .destroy = intel_user_framebuffer_destroy,
8486         .create_handle = intel_user_framebuffer_create_handle,
8487 };
8488
8489 int intel_framebuffer_init(struct drm_device *dev,
8490                            struct intel_framebuffer *intel_fb,
8491                            struct drm_mode_fb_cmd2 *mode_cmd,
8492                            struct drm_i915_gem_object *obj)
8493 {
8494         int ret;
8495
8496         if (obj->tiling_mode == I915_TILING_Y) {
8497                 DRM_DEBUG("hardware does not support tiling Y\n");
8498                 return -EINVAL;
8499         }
8500
8501         if (mode_cmd->pitches[0] & 63) {
8502                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8503                           mode_cmd->pitches[0]);
8504                 return -EINVAL;
8505         }
8506
8507         /* FIXME <= Gen4 stride limits are bit unclear */
8508         if (mode_cmd->pitches[0] > 32768) {
8509                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8510                           mode_cmd->pitches[0]);
8511                 return -EINVAL;
8512         }
8513
8514         if (obj->tiling_mode != I915_TILING_NONE &&
8515             mode_cmd->pitches[0] != obj->stride) {
8516                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8517                           mode_cmd->pitches[0], obj->stride);
8518                 return -EINVAL;
8519         }
8520
8521         /* Reject formats not supported by any plane early. */
8522         switch (mode_cmd->pixel_format) {
8523         case DRM_FORMAT_C8:
8524         case DRM_FORMAT_RGB565:
8525         case DRM_FORMAT_XRGB8888:
8526         case DRM_FORMAT_ARGB8888:
8527                 break;
8528         case DRM_FORMAT_XRGB1555:
8529         case DRM_FORMAT_ARGB1555:
8530                 if (INTEL_INFO(dev)->gen > 3) {
8531                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8532                         return -EINVAL;
8533                 }
8534                 break;
8535         case DRM_FORMAT_XBGR8888:
8536         case DRM_FORMAT_ABGR8888:
8537         case DRM_FORMAT_XRGB2101010:
8538         case DRM_FORMAT_ARGB2101010:
8539         case DRM_FORMAT_XBGR2101010:
8540         case DRM_FORMAT_ABGR2101010:
8541                 if (INTEL_INFO(dev)->gen < 4) {
8542                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8543                         return -EINVAL;
8544                 }
8545                 break;
8546         case DRM_FORMAT_YUYV:
8547         case DRM_FORMAT_UYVY:
8548         case DRM_FORMAT_YVYU:
8549         case DRM_FORMAT_VYUY:
8550                 if (INTEL_INFO(dev)->gen < 5) {
8551                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8552                         return -EINVAL;
8553                 }
8554                 break;
8555         default:
8556                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8557                 return -EINVAL;
8558         }
8559
8560         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8561         if (mode_cmd->offsets[0] != 0)
8562                 return -EINVAL;
8563
8564         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8565         intel_fb->obj = obj;
8566
8567         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8568         if (ret) {
8569                 DRM_ERROR("framebuffer init failed %d\n", ret);
8570                 return ret;
8571         }
8572
8573         return 0;
8574 }
8575
8576 static struct drm_framebuffer *
8577 intel_user_framebuffer_create(struct drm_device *dev,
8578                               struct drm_file *filp,
8579                               struct drm_mode_fb_cmd2 *mode_cmd)
8580 {
8581         struct drm_i915_gem_object *obj;
8582
8583         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8584                                                 mode_cmd->handles[0]));
8585         if (&obj->base == NULL)
8586                 return ERR_PTR(-ENOENT);
8587
8588         return intel_framebuffer_create(dev, mode_cmd, obj);
8589 }
8590
8591 static const struct drm_mode_config_funcs intel_mode_funcs = {
8592         .fb_create = intel_user_framebuffer_create,
8593         .output_poll_changed = intel_fb_output_poll_changed,
8594 };
8595
8596 /* Set up chip specific display functions */
8597 static void intel_init_display(struct drm_device *dev)
8598 {
8599         struct drm_i915_private *dev_priv = dev->dev_private;
8600
8601         /* We always want a DPMS function */
8602         if (HAS_DDI(dev)) {
8603                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8604                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8605                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8606                 dev_priv->display.off = haswell_crtc_off;
8607                 dev_priv->display.update_plane = ironlake_update_plane;
8608         } else if (HAS_PCH_SPLIT(dev)) {
8609                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8610                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8611                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8612                 dev_priv->display.off = ironlake_crtc_off;
8613                 dev_priv->display.update_plane = ironlake_update_plane;
8614         } else {
8615                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8616                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8617                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8618                 dev_priv->display.off = i9xx_crtc_off;
8619                 dev_priv->display.update_plane = i9xx_update_plane;
8620         }
8621
8622         /* Returns the core display clock speed */
8623         if (IS_VALLEYVIEW(dev))
8624                 dev_priv->display.get_display_clock_speed =
8625                         valleyview_get_display_clock_speed;
8626         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8627                 dev_priv->display.get_display_clock_speed =
8628                         i945_get_display_clock_speed;
8629         else if (IS_I915G(dev))
8630                 dev_priv->display.get_display_clock_speed =
8631                         i915_get_display_clock_speed;
8632         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8633                 dev_priv->display.get_display_clock_speed =
8634                         i9xx_misc_get_display_clock_speed;
8635         else if (IS_I915GM(dev))
8636                 dev_priv->display.get_display_clock_speed =
8637                         i915gm_get_display_clock_speed;
8638         else if (IS_I865G(dev))
8639                 dev_priv->display.get_display_clock_speed =
8640                         i865_get_display_clock_speed;
8641         else if (IS_I85X(dev))
8642                 dev_priv->display.get_display_clock_speed =
8643                         i855_get_display_clock_speed;
8644         else /* 852, 830 */
8645                 dev_priv->display.get_display_clock_speed =
8646                         i830_get_display_clock_speed;
8647
8648         if (HAS_PCH_SPLIT(dev)) {
8649                 if (IS_GEN5(dev)) {
8650                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8651                         dev_priv->display.write_eld = ironlake_write_eld;
8652                 } else if (IS_GEN6(dev)) {
8653                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8654                         dev_priv->display.write_eld = ironlake_write_eld;
8655                 } else if (IS_IVYBRIDGE(dev)) {
8656                         /* FIXME: detect B0+ stepping and use auto training */
8657                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8658                         dev_priv->display.write_eld = ironlake_write_eld;
8659                         dev_priv->display.modeset_global_resources =
8660                                 ivb_modeset_global_resources;
8661                 } else if (IS_HASWELL(dev)) {
8662                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8663                         dev_priv->display.write_eld = haswell_write_eld;
8664                         dev_priv->display.modeset_global_resources =
8665                                 haswell_modeset_global_resources;
8666                 }
8667         } else if (IS_G4X(dev)) {
8668                 dev_priv->display.write_eld = g4x_write_eld;
8669         }
8670
8671         /* Default just returns -ENODEV to indicate unsupported */
8672         dev_priv->display.queue_flip = intel_default_queue_flip;
8673
8674         switch (INTEL_INFO(dev)->gen) {
8675         case 2:
8676                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8677                 break;
8678
8679         case 3:
8680                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8681                 break;
8682
8683         case 4:
8684         case 5:
8685                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8686                 break;
8687
8688         case 6:
8689                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8690                 break;
8691         case 7:
8692                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8693                 break;
8694         }
8695 }
8696
8697 /*
8698  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8699  * resume, or other times.  This quirk makes sure that's the case for
8700  * affected systems.
8701  */
8702 static void quirk_pipea_force(struct drm_device *dev)
8703 {
8704         struct drm_i915_private *dev_priv = dev->dev_private;
8705
8706         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8707         DRM_INFO("applying pipe a force quirk\n");
8708 }
8709
8710 /*
8711  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8712  */
8713 static void quirk_ssc_force_disable(struct drm_device *dev)
8714 {
8715         struct drm_i915_private *dev_priv = dev->dev_private;
8716         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8717         DRM_INFO("applying lvds SSC disable quirk\n");
8718 }
8719
8720 /*
8721  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8722  * brightness value
8723  */
8724 static void quirk_invert_brightness(struct drm_device *dev)
8725 {
8726         struct drm_i915_private *dev_priv = dev->dev_private;
8727         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8728         DRM_INFO("applying inverted panel brightness quirk\n");
8729 }
8730
8731 struct intel_quirk {
8732         int device;
8733         int subsystem_vendor;
8734         int subsystem_device;
8735         void (*hook)(struct drm_device *dev);
8736 };
8737
8738 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8739 struct intel_dmi_quirk {
8740         void (*hook)(struct drm_device *dev);
8741         const struct dmi_system_id (*dmi_id_list)[];
8742 };
8743
8744 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8745 {
8746         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8747         return 1;
8748 }
8749
8750 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8751         {
8752                 .dmi_id_list = &(const struct dmi_system_id[]) {
8753                         {
8754                                 .callback = intel_dmi_reverse_brightness,
8755                                 .ident = "NCR Corporation",
8756                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8757                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8758                                 },
8759                         },
8760                         { }  /* terminating entry */
8761                 },
8762                 .hook = quirk_invert_brightness,
8763         },
8764 };
8765
8766 static struct intel_quirk intel_quirks[] = {
8767         /* HP Mini needs pipe A force quirk (LP: #322104) */
8768         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8769
8770         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8771         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8772
8773         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8774         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8775
8776         /* 830/845 need to leave pipe A & dpll A up */
8777         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8778         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8779
8780         /* Lenovo U160 cannot use SSC on LVDS */
8781         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8782
8783         /* Sony Vaio Y cannot use SSC on LVDS */
8784         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8785
8786         /* Acer Aspire 5734Z must invert backlight brightness */
8787         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8788
8789         /* Acer/eMachines G725 */
8790         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8791
8792         /* Acer/eMachines e725 */
8793         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8794
8795         /* Acer/Packard Bell NCL20 */
8796         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8797
8798         /* Acer Aspire 4736Z */
8799         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8800 };
8801
8802 static void intel_init_quirks(struct drm_device *dev)
8803 {
8804         struct pci_dev *d = dev->pdev;
8805         int i;
8806
8807         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8808                 struct intel_quirk *q = &intel_quirks[i];
8809
8810                 if (d->device == q->device &&
8811                     (d->subsystem_vendor == q->subsystem_vendor ||
8812                      q->subsystem_vendor == PCI_ANY_ID) &&
8813                     (d->subsystem_device == q->subsystem_device ||
8814                      q->subsystem_device == PCI_ANY_ID))
8815                         q->hook(dev);
8816         }
8817         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8818                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8819                         intel_dmi_quirks[i].hook(dev);
8820         }
8821 }
8822
8823 /* Disable the VGA plane that we never use */
8824 static void i915_disable_vga(struct drm_device *dev)
8825 {
8826         struct drm_i915_private *dev_priv = dev->dev_private;
8827         u8 sr1;
8828         u32 vga_reg = i915_vgacntrl_reg(dev);
8829
8830         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8831         outb(SR01, VGA_SR_INDEX);
8832         sr1 = inb(VGA_SR_DATA);
8833         outb(sr1 | 1<<5, VGA_SR_DATA);
8834         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8835         udelay(300);
8836
8837         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8838         POSTING_READ(vga_reg);
8839 }
8840
8841 void intel_modeset_init_hw(struct drm_device *dev)
8842 {
8843         intel_init_power_well(dev);
8844
8845         intel_prepare_ddi(dev);
8846
8847         intel_init_clock_gating(dev);
8848
8849         mutex_lock(&dev->struct_mutex);
8850         intel_enable_gt_powersave(dev);
8851         mutex_unlock(&dev->struct_mutex);
8852 }
8853
8854 void intel_modeset_init(struct drm_device *dev)
8855 {
8856         struct drm_i915_private *dev_priv = dev->dev_private;
8857         int i, ret;
8858
8859         drm_mode_config_init(dev);
8860
8861         dev->mode_config.min_width = 0;
8862         dev->mode_config.min_height = 0;
8863
8864         dev->mode_config.preferred_depth = 24;
8865         dev->mode_config.prefer_shadow = 1;
8866
8867         dev->mode_config.funcs = &intel_mode_funcs;
8868
8869         intel_init_quirks(dev);
8870
8871         intel_init_pm(dev);
8872
8873         intel_init_display(dev);
8874
8875         if (IS_GEN2(dev)) {
8876                 dev->mode_config.max_width = 2048;
8877                 dev->mode_config.max_height = 2048;
8878         } else if (IS_GEN3(dev)) {
8879                 dev->mode_config.max_width = 4096;
8880                 dev->mode_config.max_height = 4096;
8881         } else {
8882                 dev->mode_config.max_width = 8192;
8883                 dev->mode_config.max_height = 8192;
8884         }
8885         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
8886
8887         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8888                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8889
8890         for (i = 0; i < dev_priv->num_pipe; i++) {
8891                 intel_crtc_init(dev, i);
8892                 ret = intel_plane_init(dev, i);
8893                 if (ret)
8894                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8895         }
8896
8897         intel_cpu_pll_init(dev);
8898         intel_pch_pll_init(dev);
8899
8900         /* Just disable it once at startup */
8901         i915_disable_vga(dev);
8902         intel_setup_outputs(dev);
8903
8904         /* Just in case the BIOS is doing something questionable. */
8905         intel_disable_fbc(dev);
8906 }
8907
8908 static void
8909 intel_connector_break_all_links(struct intel_connector *connector)
8910 {
8911         connector->base.dpms = DRM_MODE_DPMS_OFF;
8912         connector->base.encoder = NULL;
8913         connector->encoder->connectors_active = false;
8914         connector->encoder->base.crtc = NULL;
8915 }
8916
8917 static void intel_enable_pipe_a(struct drm_device *dev)
8918 {
8919         struct intel_connector *connector;
8920         struct drm_connector *crt = NULL;
8921         struct intel_load_detect_pipe load_detect_temp;
8922
8923         /* We can't just switch on the pipe A, we need to set things up with a
8924          * proper mode and output configuration. As a gross hack, enable pipe A
8925          * by enabling the load detect pipe once. */
8926         list_for_each_entry(connector,
8927                             &dev->mode_config.connector_list,
8928                             base.head) {
8929                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8930                         crt = &connector->base;
8931                         break;
8932                 }
8933         }
8934
8935         if (!crt)
8936                 return;
8937
8938         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8939                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8940
8941
8942 }
8943
8944 static bool
8945 intel_check_plane_mapping(struct intel_crtc *crtc)
8946 {
8947         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8948         u32 reg, val;
8949
8950         if (dev_priv->num_pipe == 1)
8951                 return true;
8952
8953         reg = DSPCNTR(!crtc->plane);
8954         val = I915_READ(reg);
8955
8956         if ((val & DISPLAY_PLANE_ENABLE) &&
8957             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8958                 return false;
8959
8960         return true;
8961 }
8962
8963 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8964 {
8965         struct drm_device *dev = crtc->base.dev;
8966         struct drm_i915_private *dev_priv = dev->dev_private;
8967         u32 reg;
8968
8969         /* Clear any frame start delays used for debugging left by the BIOS */
8970         reg = PIPECONF(crtc->cpu_transcoder);
8971         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8972
8973         /* We need to sanitize the plane -> pipe mapping first because this will
8974          * disable the crtc (and hence change the state) if it is wrong. Note
8975          * that gen4+ has a fixed plane -> pipe mapping.  */
8976         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8977                 struct intel_connector *connector;
8978                 bool plane;
8979
8980                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8981                               crtc->base.base.id);
8982
8983                 /* Pipe has the wrong plane attached and the plane is active.
8984                  * Temporarily change the plane mapping and disable everything
8985                  * ...  */
8986                 plane = crtc->plane;
8987                 crtc->plane = !plane;
8988                 dev_priv->display.crtc_disable(&crtc->base);
8989                 crtc->plane = plane;
8990
8991                 /* ... and break all links. */
8992                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8993                                     base.head) {
8994                         if (connector->encoder->base.crtc != &crtc->base)
8995                                 continue;
8996
8997                         intel_connector_break_all_links(connector);
8998                 }
8999
9000                 WARN_ON(crtc->active);
9001                 crtc->base.enabled = false;
9002         }
9003
9004         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9005             crtc->pipe == PIPE_A && !crtc->active) {
9006                 /* BIOS forgot to enable pipe A, this mostly happens after
9007                  * resume. Force-enable the pipe to fix this, the update_dpms
9008                  * call below we restore the pipe to the right state, but leave
9009                  * the required bits on. */
9010                 intel_enable_pipe_a(dev);
9011         }
9012
9013         /* Adjust the state of the output pipe according to whether we
9014          * have active connectors/encoders. */
9015         intel_crtc_update_dpms(&crtc->base);
9016
9017         if (crtc->active != crtc->base.enabled) {
9018                 struct intel_encoder *encoder;
9019
9020                 /* This can happen either due to bugs in the get_hw_state
9021                  * functions or because the pipe is force-enabled due to the
9022                  * pipe A quirk. */
9023                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9024                               crtc->base.base.id,
9025                               crtc->base.enabled ? "enabled" : "disabled",
9026                               crtc->active ? "enabled" : "disabled");
9027
9028                 crtc->base.enabled = crtc->active;
9029
9030                 /* Because we only establish the connector -> encoder ->
9031                  * crtc links if something is active, this means the
9032                  * crtc is now deactivated. Break the links. connector
9033                  * -> encoder links are only establish when things are
9034                  *  actually up, hence no need to break them. */
9035                 WARN_ON(crtc->active);
9036
9037                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9038                         WARN_ON(encoder->connectors_active);
9039                         encoder->base.crtc = NULL;
9040                 }
9041         }
9042 }
9043
9044 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9045 {
9046         struct intel_connector *connector;
9047         struct drm_device *dev = encoder->base.dev;
9048
9049         /* We need to check both for a crtc link (meaning that the
9050          * encoder is active and trying to read from a pipe) and the
9051          * pipe itself being active. */
9052         bool has_active_crtc = encoder->base.crtc &&
9053                 to_intel_crtc(encoder->base.crtc)->active;
9054
9055         if (encoder->connectors_active && !has_active_crtc) {
9056                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9057                               encoder->base.base.id,
9058                               drm_get_encoder_name(&encoder->base));
9059
9060                 /* Connector is active, but has no active pipe. This is
9061                  * fallout from our resume register restoring. Disable
9062                  * the encoder manually again. */
9063                 if (encoder->base.crtc) {
9064                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9065                                       encoder->base.base.id,
9066                                       drm_get_encoder_name(&encoder->base));
9067                         encoder->disable(encoder);
9068                 }
9069
9070                 /* Inconsistent output/port/pipe state happens presumably due to
9071                  * a bug in one of the get_hw_state functions. Or someplace else
9072                  * in our code, like the register restore mess on resume. Clamp
9073                  * things to off as a safer default. */
9074                 list_for_each_entry(connector,
9075                                     &dev->mode_config.connector_list,
9076                                     base.head) {
9077                         if (connector->encoder != encoder)
9078                                 continue;
9079
9080                         intel_connector_break_all_links(connector);
9081                 }
9082         }
9083         /* Enabled encoders without active connectors will be fixed in
9084          * the crtc fixup. */
9085 }
9086
9087 void i915_redisable_vga(struct drm_device *dev)
9088 {
9089         struct drm_i915_private *dev_priv = dev->dev_private;
9090         u32 vga_reg = i915_vgacntrl_reg(dev);
9091
9092         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9093                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9094                 i915_disable_vga(dev);
9095         }
9096 }
9097
9098 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9099  * and i915 state tracking structures. */
9100 void intel_modeset_setup_hw_state(struct drm_device *dev,
9101                                   bool force_restore)
9102 {
9103         struct drm_i915_private *dev_priv = dev->dev_private;
9104         enum pipe pipe;
9105         u32 tmp;
9106         struct intel_crtc *crtc;
9107         struct intel_encoder *encoder;
9108         struct intel_connector *connector;
9109
9110         if (HAS_DDI(dev)) {
9111                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9112
9113                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9114                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9115                         case TRANS_DDI_EDP_INPUT_A_ON:
9116                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9117                                 pipe = PIPE_A;
9118                                 break;
9119                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9120                                 pipe = PIPE_B;
9121                                 break;
9122                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9123                                 pipe = PIPE_C;
9124                                 break;
9125                         }
9126
9127                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9128                         crtc->cpu_transcoder = TRANSCODER_EDP;
9129
9130                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9131                                       pipe_name(pipe));
9132                 }
9133         }
9134
9135         for_each_pipe(pipe) {
9136                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9137
9138                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9139                 if (tmp & PIPECONF_ENABLE)
9140                         crtc->active = true;
9141                 else
9142                         crtc->active = false;
9143
9144                 crtc->base.enabled = crtc->active;
9145
9146                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9147                               crtc->base.base.id,
9148                               crtc->active ? "enabled" : "disabled");
9149         }
9150
9151         if (HAS_DDI(dev))
9152                 intel_ddi_setup_hw_pll_state(dev);
9153
9154         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9155                             base.head) {
9156                 pipe = 0;
9157
9158                 if (encoder->get_hw_state(encoder, &pipe)) {
9159                         encoder->base.crtc =
9160                                 dev_priv->pipe_to_crtc_mapping[pipe];
9161                 } else {
9162                         encoder->base.crtc = NULL;
9163                 }
9164
9165                 encoder->connectors_active = false;
9166                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9167                               encoder->base.base.id,
9168                               drm_get_encoder_name(&encoder->base),
9169                               encoder->base.crtc ? "enabled" : "disabled",
9170                               pipe);
9171         }
9172
9173         list_for_each_entry(connector, &dev->mode_config.connector_list,
9174                             base.head) {
9175                 if (connector->get_hw_state(connector)) {
9176                         connector->base.dpms = DRM_MODE_DPMS_ON;
9177                         connector->encoder->connectors_active = true;
9178                         connector->base.encoder = &connector->encoder->base;
9179                 } else {
9180                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9181                         connector->base.encoder = NULL;
9182                 }
9183                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9184                               connector->base.base.id,
9185                               drm_get_connector_name(&connector->base),
9186                               connector->base.encoder ? "enabled" : "disabled");
9187         }
9188
9189         /* HW state is read out, now we need to sanitize this mess. */
9190         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9191                             base.head) {
9192                 intel_sanitize_encoder(encoder);
9193         }
9194
9195         for_each_pipe(pipe) {
9196                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9197                 intel_sanitize_crtc(crtc);
9198         }
9199
9200         if (force_restore) {
9201                 for_each_pipe(pipe) {
9202                         intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
9203                 }
9204
9205                 i915_redisable_vga(dev);
9206         } else {
9207                 intel_modeset_update_staged_output_state(dev);
9208         }
9209
9210         intel_modeset_check_state(dev);
9211
9212         drm_mode_config_reset(dev);
9213 }
9214
9215 void intel_modeset_gem_init(struct drm_device *dev)
9216 {
9217         intel_modeset_init_hw(dev);
9218
9219         intel_setup_overlay(dev);
9220
9221         intel_modeset_setup_hw_state(dev, false);
9222 }
9223
9224 void intel_modeset_cleanup(struct drm_device *dev)
9225 {
9226         struct drm_i915_private *dev_priv = dev->dev_private;
9227         struct drm_crtc *crtc;
9228         struct intel_crtc *intel_crtc;
9229
9230         drm_kms_helper_poll_fini(dev);
9231         mutex_lock(&dev->struct_mutex);
9232
9233         intel_unregister_dsm_handler();
9234
9235
9236         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9237                 /* Skip inactive CRTCs */
9238                 if (!crtc->fb)
9239                         continue;
9240
9241                 intel_crtc = to_intel_crtc(crtc);
9242                 intel_increase_pllclock(crtc);
9243         }
9244
9245         intel_disable_fbc(dev);
9246
9247         intel_disable_gt_powersave(dev);
9248
9249         ironlake_teardown_rc6(dev);
9250
9251         if (IS_VALLEYVIEW(dev))
9252                 vlv_init_dpio(dev);
9253
9254         mutex_unlock(&dev->struct_mutex);
9255
9256         /* Disable the irq before mode object teardown, for the irq might
9257          * enqueue unpin/hotplug work. */
9258         drm_irq_uninstall(dev);
9259         cancel_work_sync(&dev_priv->hotplug_work);
9260         cancel_work_sync(&dev_priv->rps.work);
9261
9262         /* flush any delayed tasks or pending work */
9263         flush_scheduled_work();
9264
9265         drm_mode_config_cleanup(dev);
9266
9267         intel_cleanup_overlay(dev);
9268 }
9269
9270 /*
9271  * Return which encoder is currently attached for connector.
9272  */
9273 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9274 {
9275         return &intel_attached_encoder(connector)->base;
9276 }
9277
9278 void intel_connector_attach_encoder(struct intel_connector *connector,
9279                                     struct intel_encoder *encoder)
9280 {
9281         connector->encoder = encoder;
9282         drm_mode_connector_attach_encoder(&connector->base,
9283                                           &encoder->base);
9284 }
9285
9286 /*
9287  * set vga decode state - true == enable VGA decode
9288  */
9289 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9290 {
9291         struct drm_i915_private *dev_priv = dev->dev_private;
9292         u16 gmch_ctrl;
9293
9294         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9295         if (state)
9296                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9297         else
9298                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9299         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9300         return 0;
9301 }
9302
9303 #ifdef CONFIG_DEBUG_FS
9304 #include <linux/seq_file.h>
9305
9306 struct intel_display_error_state {
9307         struct intel_cursor_error_state {
9308                 u32 control;
9309                 u32 position;
9310                 u32 base;
9311                 u32 size;
9312         } cursor[I915_MAX_PIPES];
9313
9314         struct intel_pipe_error_state {
9315                 u32 conf;
9316                 u32 source;
9317
9318                 u32 htotal;
9319                 u32 hblank;
9320                 u32 hsync;
9321                 u32 vtotal;
9322                 u32 vblank;
9323                 u32 vsync;
9324         } pipe[I915_MAX_PIPES];
9325
9326         struct intel_plane_error_state {
9327                 u32 control;
9328                 u32 stride;
9329                 u32 size;
9330                 u32 pos;
9331                 u32 addr;
9332                 u32 surface;
9333                 u32 tile_offset;
9334         } plane[I915_MAX_PIPES];
9335 };
9336
9337 struct intel_display_error_state *
9338 intel_display_capture_error_state(struct drm_device *dev)
9339 {
9340         drm_i915_private_t *dev_priv = dev->dev_private;
9341         struct intel_display_error_state *error;
9342         enum transcoder cpu_transcoder;
9343         int i;
9344
9345         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9346         if (error == NULL)
9347                 return NULL;
9348
9349         for_each_pipe(i) {
9350                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9351
9352                 error->cursor[i].control = I915_READ(CURCNTR(i));
9353                 error->cursor[i].position = I915_READ(CURPOS(i));
9354                 error->cursor[i].base = I915_READ(CURBASE(i));
9355
9356                 error->plane[i].control = I915_READ(DSPCNTR(i));
9357                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9358                 error->plane[i].size = I915_READ(DSPSIZE(i));
9359                 error->plane[i].pos = I915_READ(DSPPOS(i));
9360                 error->plane[i].addr = I915_READ(DSPADDR(i));
9361                 if (INTEL_INFO(dev)->gen >= 4) {
9362                         error->plane[i].surface = I915_READ(DSPSURF(i));
9363                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9364                 }
9365
9366                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9367                 error->pipe[i].source = I915_READ(PIPESRC(i));
9368                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9369                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9370                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9371                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9372                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9373                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9374         }
9375
9376         return error;
9377 }
9378
9379 void
9380 intel_display_print_error_state(struct seq_file *m,
9381                                 struct drm_device *dev,
9382                                 struct intel_display_error_state *error)
9383 {
9384         drm_i915_private_t *dev_priv = dev->dev_private;
9385         int i;
9386
9387         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9388         for_each_pipe(i) {
9389                 seq_printf(m, "Pipe [%d]:\n", i);
9390                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9391                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9392                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9393                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9394                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9395                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9396                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9397                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9398
9399                 seq_printf(m, "Plane [%d]:\n", i);
9400                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9401                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9402                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9403                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9404                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9405                 if (INTEL_INFO(dev)->gen >= 4) {
9406                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9407                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9408                 }
9409
9410                 seq_printf(m, "Cursor [%d]:\n", i);
9411                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9412                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9413                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9414         }
9415 }
9416 #endif