Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include "drmP.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include "drm_dp_helper.h"
  41 #include "drm_crtc_helper.h"
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 static bool
  84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  85                     int target, int refclk, intel_clock_t *match_clock,
  86                     intel_clock_t *best_clock);
  87 static bool
  88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  89                         int target, int refclk, intel_clock_t *match_clock,
  90                         intel_clock_t *best_clock);
  91
  92 static bool
  93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94                       int target, int refclk, intel_clock_t *match_clock,
  95                       intel_clock_t *best_clock);
  96 static bool
  97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  98                            int target, int refclk, intel_clock_t *match_clock,
  99                            intel_clock_t *best_clock);
 100
 101 static bool
 102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 103                         int target, int refclk, intel_clock_t *match_clock,
 104                         intel_clock_t *best_clock);
 105
 106 static inline u32 /* units of 100MHz */
 107 intel_fdi_link_freq(struct drm_device *dev)
 108 {
 109         if (IS_GEN5(dev)) {
 110                 struct drm_i915_private *dev_priv = dev->dev_private;
 111                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 112         } else
 113                 return 27;
 114 }
 115
 116 static const intel_limit_t intel_limits_i8xx_dvo = {
 117         .dot = { .min = 25000, .max = 350000 },
 118         .vco = { .min = 930000, .max = 1400000 },
 119         .n = { .min = 3, .max = 16 },
 120         .m = { .min = 96, .max = 140 },
 121         .m1 = { .min = 18, .max = 26 },
 122         .m2 = { .min = 6, .max = 16 },
 123         .p = { .min = 4, .max = 128 },
 124         .p1 = { .min = 2, .max = 33 },
 125         .p2 = { .dot_limit = 165000,
 126                 .p2_slow = 4, .p2_fast = 2 },
 127         .find_pll = intel_find_best_PLL,
 128 };
 129
 130 static const intel_limit_t intel_limits_i8xx_lvds = {
 131         .dot = { .min = 25000, .max = 350000 },
 132         .vco = { .min = 930000, .max = 1400000 },
 133         .n = { .min = 3, .max = 16 },
 134         .m = { .min = 96, .max = 140 },
 135         .m1 = { .min = 18, .max = 26 },
 136         .m2 = { .min = 6, .max = 16 },
 137         .p = { .min = 4, .max = 128 },
 138         .p1 = { .min = 1, .max = 6 },
 139         .p2 = { .dot_limit = 165000,
 140                 .p2_slow = 14, .p2_fast = 7 },
 141         .find_pll = intel_find_best_PLL,
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_sdvo = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 10, .max = 22 },
 150         .m2 = { .min = 5, .max = 9 },
 151         .p = { .min = 5, .max = 80 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 200000,
 154                 .p2_slow = 10, .p2_fast = 5 },
 155         .find_pll = intel_find_best_PLL,
 156 };
 157
 158 static const intel_limit_t intel_limits_i9xx_lvds = {
 159         .dot = { .min = 20000, .max = 400000 },
 160         .vco = { .min = 1400000, .max = 2800000 },
 161         .n = { .min = 1, .max = 6 },
 162         .m = { .min = 70, .max = 120 },
 163         .m1 = { .min = 10, .max = 22 },
 164         .m2 = { .min = 5, .max = 9 },
 165         .p = { .min = 7, .max = 98 },
 166         .p1 = { .min = 1, .max = 8 },
 167         .p2 = { .dot_limit = 112000,
 168                 .p2_slow = 14, .p2_fast = 7 },
 169         .find_pll = intel_find_best_PLL,
 170 };
 171
 172
 173 static const intel_limit_t intel_limits_g4x_sdvo = {
 174         .dot = { .min = 25000, .max = 270000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 17, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 10, .max = 30 },
 181         .p1 = { .min = 1, .max = 3},
 182         .p2 = { .dot_limit = 270000,
 183                 .p2_slow = 10,
 184                 .p2_fast = 10
 185         },
 186         .find_pll = intel_g4x_find_best_PLL,
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_hdmi = {
 190         .dot = { .min = 22000, .max = 400000 },
 191         .vco = { .min = 1750000, .max = 3500000},
 192         .n = { .min = 1, .max = 4 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 16, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 5, .max = 80 },
 197         .p1 = { .min = 1, .max = 8},
 198         .p2 = { .dot_limit = 165000,
 199                 .p2_slow = 10, .p2_fast = 5 },
 200         .find_pll = intel_g4x_find_best_PLL,
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 204         .dot = { .min = 20000, .max = 115000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 28, .max = 112 },
 211         .p1 = { .min = 2, .max = 8 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 14, .p2_fast = 14
 214         },
 215         .find_pll = intel_g4x_find_best_PLL,
 216 };
 217
 218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 219         .dot = { .min = 80000, .max = 224000 },
 220         .vco = { .min = 1750000, .max = 3500000 },
 221         .n = { .min = 1, .max = 3 },
 222         .m = { .min = 104, .max = 138 },
 223         .m1 = { .min = 17, .max = 23 },
 224         .m2 = { .min = 5, .max = 11 },
 225         .p = { .min = 14, .max = 42 },
 226         .p1 = { .min = 2, .max = 6 },
 227         .p2 = { .dot_limit = 0,
 228                 .p2_slow = 7, .p2_fast = 7
 229         },
 230         .find_pll = intel_g4x_find_best_PLL,
 231 };
 232
 233 static const intel_limit_t intel_limits_g4x_display_port = {
 234         .dot = { .min = 161670, .max = 227000 },
 235         .vco = { .min = 1750000, .max = 3500000},
 236         .n = { .min = 1, .max = 2 },
 237         .m = { .min = 97, .max = 108 },
 238         .m1 = { .min = 0x10, .max = 0x12 },
 239         .m2 = { .min = 0x05, .max = 0x06 },
 240         .p = { .min = 10, .max = 20 },
 241         .p1 = { .min = 1, .max = 2},
 242         .p2 = { .dot_limit = 0,
 243                 .p2_slow = 10, .p2_fast = 10 },
 244         .find_pll = intel_find_pll_g4x_dp,
 245 };
 246
 247 static const intel_limit_t intel_limits_pineview_sdvo = {
 248         .dot = { .min = 20000, .max = 400000},
 249         .vco = { .min = 1700000, .max = 3500000 },
 250         /* Pineview's Ncounter is a ring counter */
 251         .n = { .min = 3, .max = 6 },
 252         .m = { .min = 2, .max = 256 },
 253         /* Pineview only has one combined m divider, which we treat as m2. */
 254         .m1 = { .min = 0, .max = 0 },
 255         .m2 = { .min = 0, .max = 254 },
 256         .p = { .min = 5, .max = 80 },
 257         .p1 = { .min = 1, .max = 8 },
 258         .p2 = { .dot_limit = 200000,
 259                 .p2_slow = 10, .p2_fast = 5 },
 260         .find_pll = intel_find_best_PLL,
 261 };
 262
 263 static const intel_limit_t intel_limits_pineview_lvds = {
 264         .dot = { .min = 20000, .max = 400000 },
 265         .vco = { .min = 1700000, .max = 3500000 },
 266         .n = { .min = 3, .max = 6 },
 267         .m = { .min = 2, .max = 256 },
 268         .m1 = { .min = 0, .max = 0 },
 269         .m2 = { .min = 0, .max = 254 },
 270         .p = { .min = 7, .max = 112 },
 271         .p1 = { .min = 1, .max = 8 },
 272         .p2 = { .dot_limit = 112000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274         .find_pll = intel_find_best_PLL,
 275 };
 276
 277 /* Ironlake / Sandybridge
 278  *
 279  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 280  * the range value for them is (actual_value - 2).
 281  */
 282 static const intel_limit_t intel_limits_ironlake_dac = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 5 },
 286         .m = { .min = 79, .max = 127 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 5, .max = 80 },
 290         .p1 = { .min = 1, .max = 8 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 10, .p2_fast = 5 },
 293         .find_pll = intel_g4x_find_best_PLL,
 294 };
 295
 296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 297         .dot = { .min = 25000, .max = 350000 },
 298         .vco = { .min = 1760000, .max = 3510000 },
 299         .n = { .min = 1, .max = 3 },
 300         .m = { .min = 79, .max = 118 },
 301         .m1 = { .min = 12, .max = 22 },
 302         .m2 = { .min = 5, .max = 9 },
 303         .p = { .min = 28, .max = 112 },
 304         .p1 = { .min = 2, .max = 8 },
 305         .p2 = { .dot_limit = 225000,
 306                 .p2_slow = 14, .p2_fast = 14 },
 307         .find_pll = intel_g4x_find_best_PLL,
 308 };
 309
 310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 311         .dot = { .min = 25000, .max = 350000 },
 312         .vco = { .min = 1760000, .max = 3510000 },
 313         .n = { .min = 1, .max = 3 },
 314         .m = { .min = 79, .max = 127 },
 315         .m1 = { .min = 12, .max = 22 },
 316         .m2 = { .min = 5, .max = 9 },
 317         .p = { .min = 14, .max = 56 },
 318         .p1 = { .min = 2, .max = 8 },
 319         .p2 = { .dot_limit = 225000,
 320                 .p2_slow = 7, .p2_fast = 7 },
 321         .find_pll = intel_g4x_find_best_PLL,
 322 };
 323
 324 /* LVDS 100mhz refclk limits. */
 325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 326         .dot = { .min = 25000, .max = 350000 },
 327         .vco = { .min = 1760000, .max = 3510000 },
 328         .n = { .min = 1, .max = 2 },
 329         .m = { .min = 79, .max = 126 },
 330         .m1 = { .min = 12, .max = 22 },
 331         .m2 = { .min = 5, .max = 9 },
 332         .p = { .min = 28, .max = 112 },
 333         .p1 = { .min = 2, .max = 8 },
 334         .p2 = { .dot_limit = 225000,
 335                 .p2_slow = 14, .p2_fast = 14 },
 336         .find_pll = intel_g4x_find_best_PLL,
 337 };
 338
 339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 340         .dot = { .min = 25000, .max = 350000 },
 341         .vco = { .min = 1760000, .max = 3510000 },
 342         .n = { .min = 1, .max = 3 },
 343         .m = { .min = 79, .max = 126 },
 344         .m1 = { .min = 12, .max = 22 },
 345         .m2 = { .min = 5, .max = 9 },
 346         .p = { .min = 14, .max = 42 },
 347         .p1 = { .min = 2, .max = 6 },
 348         .p2 = { .dot_limit = 225000,
 349                 .p2_slow = 7, .p2_fast = 7 },
 350         .find_pll = intel_g4x_find_best_PLL,
 351 };
 352
 353 static const intel_limit_t intel_limits_ironlake_display_port = {
 354         .dot = { .min = 25000, .max = 350000 },
 355         .vco = { .min = 1760000, .max = 3510000},
 356         .n = { .min = 1, .max = 2 },
 357         .m = { .min = 81, .max = 90 },
 358         .m1 = { .min = 12, .max = 22 },
 359         .m2 = { .min = 5, .max = 9 },
 360         .p = { .min = 10, .max = 20 },
 361         .p1 = { .min = 1, .max = 2},
 362         .p2 = { .dot_limit = 0,
 363                 .p2_slow = 10, .p2_fast = 10 },
 364         .find_pll = intel_find_pll_ironlake_dp,
 365 };
 366
 367 static const intel_limit_t intel_limits_vlv_dac = {
 368         .dot = { .min = 25000, .max = 270000 },
 369         .vco = { .min = 4000000, .max = 6000000 },
 370         .n = { .min = 1, .max = 7 },
 371         .m = { .min = 22, .max = 450 }, /* guess */
 372         .m1 = { .min = 2, .max = 3 },
 373         .m2 = { .min = 11, .max = 156 },
 374         .p = { .min = 10, .max = 30 },
 375         .p1 = { .min = 2, .max = 3 },
 376         .p2 = { .dot_limit = 270000,
 377                 .p2_slow = 2, .p2_fast = 20 },
 378         .find_pll = intel_vlv_find_best_pll,
 379 };
 380
 381 static const intel_limit_t intel_limits_vlv_hdmi = {
 382         .dot = { .min = 20000, .max = 165000 },
 383         .vco = { .min = 5994000, .max = 4000000 },
 384         .n = { .min = 1, .max = 7 },
 385         .m = { .min = 60, .max = 300 }, /* guess */
 386         .m1 = { .min = 2, .max = 3 },
 387         .m2 = { .min = 11, .max = 156 },
 388         .p = { .min = 10, .max = 30 },
 389         .p1 = { .min = 2, .max = 3 },
 390         .p2 = { .dot_limit = 270000,
 391                 .p2_slow = 2, .p2_fast = 20 },
 392         .find_pll = intel_vlv_find_best_pll,
 393 };
 394
 395 static const intel_limit_t intel_limits_vlv_dp = {
 396         .dot = { .min = 162000, .max = 270000 },
 397         .vco = { .min = 5994000, .max = 4000000 },
 398         .n = { .min = 1, .max = 7 },
 399         .m = { .min = 60, .max = 300 }, /* guess */
 400         .m1 = { .min = 2, .max = 3 },
 401         .m2 = { .min = 11, .max = 156 },
 402         .p = { .min = 10, .max = 30 },
 403         .p1 = { .min = 2, .max = 3 },
 404         .p2 = { .dot_limit = 270000,
 405                 .p2_slow = 2, .p2_fast = 20 },
 406         .find_pll = intel_vlv_find_best_pll,
 407 };
 408
 409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 410 {
 411         unsigned long flags;
 412         u32 val = 0;
 413
 414         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 415         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 416                 DRM_ERROR("DPIO idle wait timed out\n");
 417                 goto out_unlock;
 418         }
 419
 420         I915_WRITE(DPIO_REG, reg);
 421         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 422                    DPIO_BYTE);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO read wait timed out\n");
 425                 goto out_unlock;
 426         }
 427         val = I915_READ(DPIO_DATA);
 428
 429 out_unlock:
 430         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 431         return val;
 432 }
 433
 434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 435                              u32 val)
 436 {
 437         unsigned long flags;
 438
 439         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 440         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 441                 DRM_ERROR("DPIO idle wait timed out\n");
 442                 goto out_unlock;
 443         }
 444
 445         I915_WRITE(DPIO_DATA, val);
 446         I915_WRITE(DPIO_REG, reg);
 447         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 448                    DPIO_BYTE);
 449         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 450                 DRM_ERROR("DPIO write wait timed out\n");
 451
 452 out_unlock:
 453        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 454 }
 455
 456 static void vlv_init_dpio(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459
 460         /* Reset the DPIO config */
 461         I915_WRITE(DPIO_CTL, 0);
 462         POSTING_READ(DPIO_CTL);
 463         I915_WRITE(DPIO_CTL, 1);
 464         POSTING_READ(DPIO_CTL);
 465 }
 466
 467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 468 {
 469         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 470         return 1;
 471 }
 472
 473 static const struct dmi_system_id intel_dual_link_lvds[] = {
 474         {
 475                 .callback = intel_dual_link_lvds_callback,
 476                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 477                 .matches = {
 478                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 479                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 480                 },
 481         },
 482         { }     /* terminating entry */
 483 };
 484
 485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 486                               unsigned int reg)
 487 {
 488         unsigned int val;
 489
 490         /* use the module option value if specified */
 491         if (i915_lvds_channel_mode > 0)
 492                 return i915_lvds_channel_mode == 2;
 493
 494         if (dmi_check_system(intel_dual_link_lvds))
 495                 return true;
 496
 497         if (dev_priv->lvds_val)
 498                 val = dev_priv->lvds_val;
 499         else {
 500                 /* BIOS should set the proper LVDS register value at boot, but
 501                  * in reality, it doesn't set the value when the lid is closed;
 502                  * we need to check "the value to be set" in VBT when LVDS
 503                  * register is uninitialized.
 504                  */
 505                 val = I915_READ(reg);
 506                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 507                         val = dev_priv->bios_lvds_val;
 508                 dev_priv->lvds_val = val;
 509         }
 510         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 511 }
 512
 513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 514                                                 int refclk)
 515 {
 516         struct drm_device *dev = crtc->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         const intel_limit_t *limit;
 519
 520         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 521                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 522                         /* LVDS dual channel */
 523                         if (refclk == 100000)
 524                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 525                         else
 526                                 limit = &intel_limits_ironlake_dual_lvds;
 527                 } else {
 528                         if (refclk == 100000)
 529                                 limit = &intel_limits_ironlake_single_lvds_100m;
 530                         else
 531                                 limit = &intel_limits_ironlake_single_lvds;
 532                 }
 533         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 534                         HAS_eDP)
 535                 limit = &intel_limits_ironlake_display_port;
 536         else
 537                 limit = &intel_limits_ironlake_dac;
 538
 539         return limit;
 540 }
 541
 542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 543 {
 544         struct drm_device *dev = crtc->dev;
 545         struct drm_i915_private *dev_priv = dev->dev_private;
 546         const intel_limit_t *limit;
 547
 548         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 549                 if (is_dual_link_lvds(dev_priv, LVDS))
 550                         /* LVDS with dual channel */
 551                         limit = &intel_limits_g4x_dual_channel_lvds;
 552                 else
 553                         /* LVDS with dual channel */
 554                         limit = &intel_limits_g4x_single_channel_lvds;
 555         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 556                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 557                 limit = &intel_limits_g4x_hdmi;
 558         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 559                 limit = &intel_limits_g4x_sdvo;
 560         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 561                 limit = &intel_limits_g4x_display_port;
 562         } else /* The option is for other outputs */
 563                 limit = &intel_limits_i9xx_sdvo;
 564
 565         return limit;
 566 }
 567
 568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 569 {
 570         struct drm_device *dev = crtc->dev;
 571         const intel_limit_t *limit;
 572
 573         if (HAS_PCH_SPLIT(dev))
 574                 limit = intel_ironlake_limit(crtc, refclk);
 575         else if (IS_G4X(dev)) {
 576                 limit = intel_g4x_limit(crtc);
 577         } else if (IS_PINEVIEW(dev)) {
 578                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 579                         limit = &intel_limits_pineview_lvds;
 580                 else
 581                         limit = &intel_limits_pineview_sdvo;
 582         } else if (IS_VALLEYVIEW(dev)) {
 583                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 584                         limit = &intel_limits_vlv_dac;
 585                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 586                         limit = &intel_limits_vlv_hdmi;
 587                 else
 588                         limit = &intel_limits_vlv_dp;
 589         } else if (!IS_GEN2(dev)) {
 590                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 591                         limit = &intel_limits_i9xx_lvds;
 592                 else
 593                         limit = &intel_limits_i9xx_sdvo;
 594         } else {
 595                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 596                         limit = &intel_limits_i8xx_lvds;
 597                 else
 598                         limit = &intel_limits_i8xx_dvo;
 599         }
 600         return limit;
 601 }
 602
 603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 604 static void pineview_clock(int refclk, intel_clock_t *clock)
 605 {
 606         clock->m = clock->m2 + 2;
 607         clock->p = clock->p1 * clock->p2;
 608         clock->vco = refclk * clock->m / clock->n;
 609         clock->dot = clock->vco / clock->p;
 610 }
 611
 612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 613 {
 614         if (IS_PINEVIEW(dev)) {
 615                 pineview_clock(refclk, clock);
 616                 return;
 617         }
 618         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 619         clock->p = clock->p1 * clock->p2;
 620         clock->vco = refclk * clock->m / (clock->n + 2);
 621         clock->dot = clock->vco / clock->p;
 622 }
 623
 624 /**
 625  * Returns whether any output on the specified pipe is of the specified type
 626  */
 627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 628 {
 629         struct drm_device *dev = crtc->dev;
 630         struct drm_mode_config *mode_config = &dev->mode_config;
 631         struct intel_encoder *encoder;
 632
 633         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 634                 if (encoder->base.crtc == crtc && encoder->type == type)
 635                         return true;
 636
 637         return false;
 638 }
 639
 640 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 641 /**
 642  * Returns whether the given set of divisors are valid for a given refclk with
 643  * the given connectors.
 644  */
 645
 646 static bool intel_PLL_is_valid(struct drm_device *dev,
 647                                const intel_limit_t *limit,
 648                                const intel_clock_t *clock)
 649 {
 650         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 651                 INTELPllInvalid("p1 out of range\n");
 652         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 653                 INTELPllInvalid("p out of range\n");
 654         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 655                 INTELPllInvalid("m2 out of range\n");
 656         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 657                 INTELPllInvalid("m1 out of range\n");
 658         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 659                 INTELPllInvalid("m1 <= m2\n");
 660         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 661                 INTELPllInvalid("m out of range\n");
 662         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 663                 INTELPllInvalid("n out of range\n");
 664         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 665                 INTELPllInvalid("vco out of range\n");
 666         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 667          * connector, etc., rather than just a single range.
 668          */
 669         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 670                 INTELPllInvalid("dot out of range\n");
 671
 672         return true;
 673 }
 674
 675 static bool
 676 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 677                     int target, int refclk, intel_clock_t *match_clock,
 678                     intel_clock_t *best_clock)
 679
 680 {
 681         struct drm_device *dev = crtc->dev;
 682         struct drm_i915_private *dev_priv = dev->dev_private;
 683         intel_clock_t clock;
 684         int err = target;
 685
 686         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 687             (I915_READ(LVDS)) != 0) {
 688                 /*
 689                  * For LVDS, if the panel is on, just rely on its current
 690                  * settings for dual-channel.  We haven't figured out how to
 691                  * reliably set up different single/dual channel state, if we
 692                  * even can.
 693                  */
 694                 if (is_dual_link_lvds(dev_priv, LVDS))
 695                         clock.p2 = limit->p2.p2_fast;
 696                 else
 697                         clock.p2 = limit->p2.p2_slow;
 698         } else {
 699                 if (target < limit->p2.dot_limit)
 700                         clock.p2 = limit->p2.p2_slow;
 701                 else
 702                         clock.p2 = limit->p2.p2_fast;
 703         }
 704
 705         memset(best_clock, 0, sizeof(*best_clock));
 706
 707         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 708              clock.m1++) {
 709                 for (clock.m2 = limit->m2.min;
 710                      clock.m2 <= limit->m2.max; clock.m2++) {
 711                         /* m1 is always 0 in Pineview */
 712                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 713                                 break;
 714                         for (clock.n = limit->n.min;
 715                              clock.n <= limit->n.max; clock.n++) {
 716                                 for (clock.p1 = limit->p1.min;
 717                                         clock.p1 <= limit->p1.max; clock.p1++) {
 718                                         int this_err;
 719
 720                                         intel_clock(dev, refclk, &clock);
 721                                         if (!intel_PLL_is_valid(dev, limit,
 722                                                                 &clock))
 723                                                 continue;
 724                                         if (match_clock &&
 725                                             clock.p != match_clock->p)
 726                                                 continue;
 727
 728                                         this_err = abs(clock.dot - target);
 729                                         if (this_err < err) {
 730                                                 *best_clock = clock;
 731                                                 err = this_err;
 732                                         }
 733                                 }
 734                         }
 735                 }
 736         }
 737
 738         return (err != target);
 739 }
 740
 741 static bool
 742 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 743                         int target, int refclk, intel_clock_t *match_clock,
 744                         intel_clock_t *best_clock)
 745 {
 746         struct drm_device *dev = crtc->dev;
 747         struct drm_i915_private *dev_priv = dev->dev_private;
 748         intel_clock_t clock;
 749         int max_n;
 750         bool found;
 751         /* approximately equals target * 0.00585 */
 752         int err_most = (target >> 8) + (target >> 9);
 753         found = false;
 754
 755         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 756                 int lvds_reg;
 757
 758                 if (HAS_PCH_SPLIT(dev))
 759                         lvds_reg = PCH_LVDS;
 760                 else
 761                         lvds_reg = LVDS;
 762                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 763                     LVDS_CLKB_POWER_UP)
 764                         clock.p2 = limit->p2.p2_fast;
 765                 else
 766                         clock.p2 = limit->p2.p2_slow;
 767         } else {
 768                 if (target < limit->p2.dot_limit)
 769                         clock.p2 = limit->p2.p2_slow;
 770                 else
 771                         clock.p2 = limit->p2.p2_fast;
 772         }
 773
 774         memset(best_clock, 0, sizeof(*best_clock));
 775         max_n = limit->n.max;
 776         /* based on hardware requirement, prefer smaller n to precision */
 777         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 778                 /* based on hardware requirement, prefere larger m1,m2 */
 779                 for (clock.m1 = limit->m1.max;
 780                      clock.m1 >= limit->m1.min; clock.m1--) {
 781                         for (clock.m2 = limit->m2.max;
 782                              clock.m2 >= limit->m2.min; clock.m2--) {
 783                                 for (clock.p1 = limit->p1.max;
 784                                      clock.p1 >= limit->p1.min; clock.p1--) {
 785                                         int this_err;
 786
 787                                         intel_clock(dev, refclk, &clock);
 788                                         if (!intel_PLL_is_valid(dev, limit,
 789                                                                 &clock))
 790                                                 continue;
 791                                         if (match_clock &&
 792                                             clock.p != match_clock->p)
 793                                                 continue;
 794
 795                                         this_err = abs(clock.dot - target);
 796                                         if (this_err < err_most) {
 797                                                 *best_clock = clock;
 798                                                 err_most = this_err;
 799                                                 max_n = clock.n;
 800                                                 found = true;
 801                                         }
 802                                 }
 803                         }
 804                 }
 805         }
 806         return found;
 807 }
 808
 809 static bool
 810 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 811                            int target, int refclk, intel_clock_t *match_clock,
 812                            intel_clock_t *best_clock)
 813 {
 814         struct drm_device *dev = crtc->dev;
 815         intel_clock_t clock;
 816
 817         if (target < 200000) {
 818                 clock.n = 1;
 819                 clock.p1 = 2;
 820                 clock.p2 = 10;
 821                 clock.m1 = 12;
 822                 clock.m2 = 9;
 823         } else {
 824                 clock.n = 2;
 825                 clock.p1 = 1;
 826                 clock.p2 = 10;
 827                 clock.m1 = 14;
 828                 clock.m2 = 8;
 829         }
 830         intel_clock(dev, refclk, &clock);
 831         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 832         return true;
 833 }
 834
 835 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 836 static bool
 837 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 838                       int target, int refclk, intel_clock_t *match_clock,
 839                       intel_clock_t *best_clock)
 840 {
 841         intel_clock_t clock;
 842         if (target < 200000) {
 843                 clock.p1 = 2;
 844                 clock.p2 = 10;
 845                 clock.n = 2;
 846                 clock.m1 = 23;
 847                 clock.m2 = 8;
 848         } else {
 849                 clock.p1 = 1;
 850                 clock.p2 = 10;
 851                 clock.n = 1;
 852                 clock.m1 = 14;
 853                 clock.m2 = 2;
 854         }
 855         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 856         clock.p = (clock.p1 * clock.p2);
 857         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 858         clock.vco = 0;
 859         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 860         return true;
 861 }
 862 static bool
 863 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 864                         int target, int refclk, intel_clock_t *match_clock,
 865                         intel_clock_t *best_clock)
 866 {
 867         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 868         u32 m, n, fastclk;
 869         u32 updrate, minupdate, fracbits, p;
 870         unsigned long bestppm, ppm, absppm;
 871         int dotclk, flag;
 872
 873         dotclk = target * 1000;
 874         bestppm = 1000000;
 875         ppm = absppm = 0;
 876         fastclk = dotclk / (2*100);
 877         updrate = 0;
 878         minupdate = 19200;
 879         fracbits = 1;
 880         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 881         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 882
 883         /* based on hardware requirement, prefer smaller n to precision */
 884         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 885                 updrate = refclk / n;
 886                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 887                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 888                                 if (p2 > 10)
 889                                         p2 = p2 - 1;
 890                                 p = p1 * p2;
 891                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 892                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 893                                         m2 = (((2*(fastclk * p * n / m1 )) +
 894                                                refclk) / (2*refclk));
 895                                         m = m1 * m2;
 896                                         vco = updrate * m;
 897                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 898                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 899                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 900                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 901                                                         bestppm = 0;
 902                                                         flag = 1;
 903                                                 }
 904                                                 if (absppm < bestppm - 10) {
 905                                                         bestppm = absppm;
 906                                                         flag = 1;
 907                                                 }
 908                                                 if (flag) {
 909                                                         bestn = n;
 910                                                         bestm1 = m1;
 911                                                         bestm2 = m2;
 912                                                         bestp1 = p1;
 913                                                         bestp2 = p2;
 914                                                         flag = 0;
 915                                                 }
 916                                         }
 917                                 }
 918                         }
 919                 }
 920         }
 921         best_clock->n = bestn;
 922         best_clock->m1 = bestm1;
 923         best_clock->m2 = bestm2;
 924         best_clock->p1 = bestp1;
 925         best_clock->p2 = bestp2;
 926
 927         return true;
 928 }
 929
 930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 931 {
 932         struct drm_i915_private *dev_priv = dev->dev_private;
 933         u32 frame, frame_reg = PIPEFRAME(pipe);
 934
 935         frame = I915_READ(frame_reg);
 936
 937         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 938                 DRM_DEBUG_KMS("vblank wait timed out\n");
 939 }
 940
 941 /**
 942  * intel_wait_for_vblank - wait for vblank on a given pipe
 943  * @dev: drm device
 944  * @pipe: pipe to wait for
 945  *
 946  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 947  * mode setting code.
 948  */
 949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         int pipestat_reg = PIPESTAT(pipe);
 953
 954         if (INTEL_INFO(dev)->gen >= 5) {
 955                 ironlake_wait_for_vblank(dev, pipe);
 956                 return;
 957         }
 958
 959         /* Clear existing vblank status. Note this will clear any other
 960          * sticky status fields as well.
 961          *
 962          * This races with i915_driver_irq_handler() with the result
 963          * that either function could miss a vblank event.  Here it is not
 964          * fatal, as we will either wait upon the next vblank interrupt or
 965          * timeout.  Generally speaking intel_wait_for_vblank() is only
 966          * called during modeset at which time the GPU should be idle and
 967          * should *not* be performing page flips and thus not waiting on
 968          * vblanks...
 969          * Currently, the result of us stealing a vblank from the irq
 970          * handler is that a single frame will be skipped during swapbuffers.
 971          */
 972         I915_WRITE(pipestat_reg,
 973                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 974
 975         /* Wait for vblank interrupt bit to set */
 976         if (wait_for(I915_READ(pipestat_reg) &
 977                      PIPE_VBLANK_INTERRUPT_STATUS,
 978                      50))
 979                 DRM_DEBUG_KMS("vblank wait timed out\n");
 980 }
 981
 982 /*
 983  * intel_wait_for_pipe_off - wait for pipe to turn off
 984  * @dev: drm device
 985  * @pipe: pipe to wait for
 986  *
 987  * After disabling a pipe, we can't wait for vblank in the usual way,
 988  * spinning on the vblank interrupt status bit, since we won't actually
 989  * see an interrupt when the pipe is disabled.
 990  *
 991  * On Gen4 and above:
 992  *   wait for the pipe register state bit to turn off
 993  *
 994  * Otherwise:
 995  *   wait for the display line value to settle (it usually
 996  *   ends up stopping at the start of the next frame).
 997  *
 998  */
 999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         if (INTEL_INFO(dev)->gen >= 4) {
1004                 int reg = PIPECONF(pipe);
1005
1006                 /* Wait for the Pipe State to go off */
1007                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008                              100))
1009                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010         } else {
1011                 u32 last_line, line_mask;
1012                 int reg = PIPEDSL(pipe);
1013                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015                 if (IS_GEN2(dev))
1016                         line_mask = DSL_LINEMASK_GEN2;
1017                 else
1018                         line_mask = DSL_LINEMASK_GEN3;
1019
1020                 /* Wait for the display line to settle */
1021                 do {
1022                         last_line = I915_READ(reg) & line_mask;
1023                         mdelay(5);
1024                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025                          time_after(timeout, jiffies));
1026                 if (time_after(jiffies, timeout))
1027                         DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028         }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033         return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038                        enum pipe pipe, bool state)
1039 {
1040         int reg;
1041         u32 val;
1042         bool cur_state;
1043
1044         reg = DPLL(pipe);
1045         val = I915_READ(reg);
1046         cur_state = !!(val & DPLL_VCO_ENABLE);
1047         WARN(cur_state != state,
1048              "PLL state assertion failure (expected %s, current %s)\n",
1049              state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056                            struct intel_pch_pll *pll,
1057                            struct intel_crtc *crtc,
1058                            bool state)
1059 {
1060         u32 val;
1061         bool cur_state;
1062
1063         if (HAS_PCH_LPT(dev_priv->dev)) {
1064                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065                 return;
1066         }
1067
1068         if (WARN (!pll,
1069                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070                 return;
1071
1072         val = I915_READ(pll->pll_reg);
1073         cur_state = !!(val & DPLL_VCO_ENABLE);
1074         WARN(cur_state != state,
1075              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076              pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078         /* Make sure the selected PLL is correctly attached to the transcoder */
1079         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080                 u32 pch_dpll;
1081
1082                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1086                           cur_state, crtc->pipe, pch_dpll)) {
1087                         cur_state = !!(val >> (4*crtc->pipe + 3));
1088                         WARN(cur_state != state,
1089                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1090                              pll->pll_reg == _PCH_DPLL_B,
1091                              state_string(state),
1092                              crtc->pipe,
1093                              val);
1094                 }
1095         }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101                           enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106
1107         if (IS_HASWELL(dev_priv->dev)) {
1108                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109                 reg = DDI_FUNC_CTL(pipe);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112         } else {
1113                 reg = FDI_TX_CTL(pipe);
1114                 val = I915_READ(reg);
1115                 cur_state = !!(val & FDI_TX_ENABLE);
1116         }
1117         WARN(cur_state != state,
1118              "FDI TX state assertion failure (expected %s, current %s)\n",
1119              state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125                           enum pipe pipe, bool state)
1126 {
1127         int reg;
1128         u32 val;
1129         bool cur_state;
1130
1131         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133                         return;
1134         } else {
1135                 reg = FDI_RX_CTL(pipe);
1136                 val = I915_READ(reg);
1137                 cur_state = !!(val & FDI_RX_ENABLE);
1138         }
1139         WARN(cur_state != state,
1140              "FDI RX state assertion failure (expected %s, current %s)\n",
1141              state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147                                       enum pipe pipe)
1148 {
1149         int reg;
1150         u32 val;
1151
1152         /* ILK FDI PLL is always enabled */
1153         if (dev_priv->info->gen == 5)
1154                 return;
1155
1156         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157         if (IS_HASWELL(dev_priv->dev))
1158                 return;
1159
1160         reg = FDI_TX_CTL(pipe);
1161         val = I915_READ(reg);
1162         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166                                       enum pipe pipe)
1167 {
1168         int reg;
1169         u32 val;
1170
1171         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173                 return;
1174         }
1175         reg = FDI_RX_CTL(pipe);
1176         val = I915_READ(reg);
1177         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181                                   enum pipe pipe)
1182 {
1183         int pp_reg, lvds_reg;
1184         u32 val;
1185         enum pipe panel_pipe = PIPE_A;
1186         bool locked = true;
1187
1188         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189                 pp_reg = PCH_PP_CONTROL;
1190                 lvds_reg = PCH_LVDS;
1191         } else {
1192                 pp_reg = PP_CONTROL;
1193                 lvds_reg = LVDS;
1194         }
1195
1196         val = I915_READ(pp_reg);
1197         if (!(val & PANEL_POWER_ON) ||
1198             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199                 locked = false;
1200
1201         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202                 panel_pipe = PIPE_B;
1203
1204         WARN(panel_pipe == pipe && locked,
1205              "panel assertion failure, pipe %c regs locked\n",
1206              pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210                  enum pipe pipe, bool state)
1211 {
1212         int reg;
1213         u32 val;
1214         bool cur_state;
1215
1216         /* if we need the pipe A quirk it must be always on */
1217         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218                 state = true;
1219
1220         reg = PIPECONF(pipe);
1221         val = I915_READ(reg);
1222         cur_state = !!(val & PIPECONF_ENABLE);
1223         WARN(cur_state != state,
1224              "pipe %c assertion failure (expected %s, current %s)\n",
1225              pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229                          enum plane plane, bool state)
1230 {
1231         int reg;
1232         u32 val;
1233         bool cur_state;
1234
1235         reg = DSPCNTR(plane);
1236         val = I915_READ(reg);
1237         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238         WARN(cur_state != state,
1239              "plane %c assertion failure (expected %s, current %s)\n",
1240              plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247                                    enum pipe pipe)
1248 {
1249         int reg, i;
1250         u32 val;
1251         int cur_pipe;
1252
1253         /* Planes are fixed to pipes on ILK+ */
1254         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255                 reg = DSPCNTR(pipe);
1256                 val = I915_READ(reg);
1257                 WARN((val & DISPLAY_PLANE_ENABLE),
1258                      "plane %c assertion failure, should be disabled but not\n",
1259                      plane_name(pipe));
1260                 return;
1261         }
1262
1263         /* Need to check both planes against the pipe */
1264         for (i = 0; i < 2; i++) {
1265                 reg = DSPCNTR(i);
1266                 val = I915_READ(reg);
1267                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268                         DISPPLANE_SEL_PIPE_SHIFT;
1269                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271                      plane_name(i), pipe_name(pipe));
1272         }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277         u32 val;
1278         bool enabled;
1279
1280         if (HAS_PCH_LPT(dev_priv->dev)) {
1281                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282                 return;
1283         }
1284
1285         val = I915_READ(PCH_DREF_CONTROL);
1286         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287                             DREF_SUPERSPREAD_SOURCE_MASK));
1288         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292                                        enum pipe pipe)
1293 {
1294         int reg;
1295         u32 val;
1296         bool enabled;
1297
1298         reg = TRANSCONF(pipe);
1299         val = I915_READ(reg);
1300         enabled = !!(val & TRANS_ENABLE);
1301         WARN(enabled,
1302              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303              pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307                             enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309         if ((val & DP_PORT_EN) == 0)
1310                 return false;
1311
1312         if (HAS_PCH_CPT(dev_priv->dev)) {
1313                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else {
1318                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319                         return false;
1320         }
1321         return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325                               enum pipe pipe, u32 val)
1326 {
1327         if ((val & PORT_ENABLE) == 0)
1328                 return false;
1329
1330         if (HAS_PCH_CPT(dev_priv->dev)) {
1331                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332                         return false;
1333         } else {
1334                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335                         return false;
1336         }
1337         return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341                               enum pipe pipe, u32 val)
1342 {
1343         if ((val & LVDS_PORT_EN) == 0)
1344                 return false;
1345
1346         if (HAS_PCH_CPT(dev_priv->dev)) {
1347                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348                         return false;
1349         } else {
1350                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351                         return false;
1352         }
1353         return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357                               enum pipe pipe, u32 val)
1358 {
1359         if ((val & ADPA_DAC_ENABLE) == 0)
1360                 return false;
1361         if (HAS_PCH_CPT(dev_priv->dev)) {
1362                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363                         return false;
1364         } else {
1365                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366                         return false;
1367         }
1368         return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372                                    enum pipe pipe, int reg, u32 port_sel)
1373 {
1374         u32 val = I915_READ(reg);
1375         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377              reg, pipe_name(pipe));
1378
1379         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380              "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384                                      enum pipe pipe, int reg)
1385 {
1386         u32 val = I915_READ(reg);
1387         WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1388              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389              reg, pipe_name(pipe));
1390
1391         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392              "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396                                       enum pipe pipe)
1397 {
1398         int reg;
1399         u32 val;
1400
1401         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405         reg = PCH_ADPA;
1406         val = I915_READ(reg);
1407         WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1408              "PCH VGA enabled on transcoder %c, should be disabled\n",
1409              pipe_name(pipe));
1410
1411         reg = PCH_LVDS;
1412         val = I915_READ(reg);
1413         WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1414              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415              pipe_name(pipe));
1416
1417         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423  * intel_enable_pll - enable a PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1428  * make sure the PLL reg is writable first though, since the panel write
1429  * protect mechanism may be enabled.
1430  *
1431  * Note!  This is for pre-ILK only.
1432  */
1433 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1434 {
1435         int reg;
1436         u32 val;
1437
1438         /* No really, not for ILK+ */
1439         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1440
1441         /* PLL is protected by panel, make sure we can write it */
1442         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1443                 assert_panel_unlocked(dev_priv, pipe);
1444
1445         reg = DPLL(pipe);
1446         val = I915_READ(reg);
1447         val |= DPLL_VCO_ENABLE;
1448
1449         /* We do this three times for luck */
1450         I915_WRITE(reg, val);
1451         POSTING_READ(reg);
1452         udelay(150); /* wait for warmup */
1453         I915_WRITE(reg, val);
1454         POSTING_READ(reg);
1455         udelay(150); /* wait for warmup */
1456         I915_WRITE(reg, val);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462  * intel_disable_pll - disable a PLL
1463  * @dev_priv: i915 private structure
1464  * @pipe: pipe PLL to disable
1465  *
1466  * Disable the PLL for @pipe, making sure the pipe is off first.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  */
1470 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472         int reg;
1473         u32 val;
1474
1475         /* Don't disable pipe A or pipe A PLLs if needed */
1476         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1477                 return;
1478
1479         /* Make sure the pipe isn't still relying on us */
1480         assert_pipe_disabled(dev_priv, pipe);
1481
1482         reg = DPLL(pipe);
1483         val = I915_READ(reg);
1484         val &= ~DPLL_VCO_ENABLE;
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487 }
1488
1489 /* SBI access */
1490 static void
1491 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1492 {
1493         unsigned long flags;
1494
1495         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1496         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1497                                 100)) {
1498                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1499                 goto out_unlock;
1500         }
1501
1502         I915_WRITE(SBI_ADDR,
1503                         (reg << 16));
1504         I915_WRITE(SBI_DATA,
1505                         value);
1506         I915_WRITE(SBI_CTL_STAT,
1507                         SBI_BUSY |
1508                         SBI_CTL_OP_CRWR);
1509
1510         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1511                                 100)) {
1512                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1513                 goto out_unlock;
1514         }
1515
1516 out_unlock:
1517         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1518 }
1519
1520 static u32
1521 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1522 {
1523         unsigned long flags;
1524         u32 value = 0;
1525
1526         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1527         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1528                                 100)) {
1529                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1530                 goto out_unlock;
1531         }
1532
1533         I915_WRITE(SBI_ADDR,
1534                         (reg << 16));
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRRD);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545         value = I915_READ(SBI_DATA);
1546
1547 out_unlock:
1548         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1549         return value;
1550 }
1551
1552 /**
1553  * intel_enable_pch_pll - enable PCH PLL
1554  * @dev_priv: i915 private structure
1555  * @pipe: pipe PLL to enable
1556  *
1557  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1558  * drives the transcoder clock.
1559  */
1560 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1561 {
1562         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1563         struct intel_pch_pll *pll;
1564         int reg;
1565         u32 val;
1566
1567         /* PCH PLLs only available on ILK, SNB and IVB */
1568         BUG_ON(dev_priv->info->gen < 5);
1569         pll = intel_crtc->pch_pll;
1570         if (pll == NULL)
1571                 return;
1572
1573         if (WARN_ON(pll->refcount == 0))
1574                 return;
1575
1576         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1577                       pll->pll_reg, pll->active, pll->on,
1578                       intel_crtc->base.base.id);
1579
1580         /* PCH refclock must be enabled first */
1581         assert_pch_refclk_enabled(dev_priv);
1582
1583         if (pll->active++ && pll->on) {
1584                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1585                 return;
1586         }
1587
1588         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1589
1590         reg = pll->pll_reg;
1591         val = I915_READ(reg);
1592         val |= DPLL_VCO_ENABLE;
1593         I915_WRITE(reg, val);
1594         POSTING_READ(reg);
1595         udelay(200);
1596
1597         pll->on = true;
1598 }
1599
1600 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1601 {
1602         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1603         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1604         int reg;
1605         u32 val;
1606
1607         /* PCH only available on ILK+ */
1608         BUG_ON(dev_priv->info->gen < 5);
1609         if (pll == NULL)
1610                return;
1611
1612         if (WARN_ON(pll->refcount == 0))
1613                 return;
1614
1615         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1616                       pll->pll_reg, pll->active, pll->on,
1617                       intel_crtc->base.base.id);
1618
1619         if (WARN_ON(pll->active == 0)) {
1620                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1621                 return;
1622         }
1623
1624         if (--pll->active) {
1625                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1626                 return;
1627         }
1628
1629         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1630
1631         /* Make sure transcoder isn't still depending on us */
1632         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1633
1634         reg = pll->pll_reg;
1635         val = I915_READ(reg);
1636         val &= ~DPLL_VCO_ENABLE;
1637         I915_WRITE(reg, val);
1638         POSTING_READ(reg);
1639         udelay(200);
1640
1641         pll->on = false;
1642 }
1643
1644 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1645                                     enum pipe pipe)
1646 {
1647         int reg;
1648         u32 val, pipeconf_val;
1649         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1650
1651         /* PCH only available on ILK+ */
1652         BUG_ON(dev_priv->info->gen < 5);
1653
1654         /* Make sure PCH DPLL is enabled */
1655         assert_pch_pll_enabled(dev_priv,
1656                                to_intel_crtc(crtc)->pch_pll,
1657                                to_intel_crtc(crtc));
1658
1659         /* FDI must be feeding us bits for PCH ports */
1660         assert_fdi_tx_enabled(dev_priv, pipe);
1661         assert_fdi_rx_enabled(dev_priv, pipe);
1662
1663         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1664                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1665                 return;
1666         }
1667         reg = TRANSCONF(pipe);
1668         val = I915_READ(reg);
1669         pipeconf_val = I915_READ(PIPECONF(pipe));
1670
1671         if (HAS_PCH_IBX(dev_priv->dev)) {
1672                 /*
1673                  * make the BPC in transcoder be consistent with
1674                  * that in pipeconf reg.
1675                  */
1676                 val &= ~PIPE_BPC_MASK;
1677                 val |= pipeconf_val & PIPE_BPC_MASK;
1678         }
1679
1680         val &= ~TRANS_INTERLACE_MASK;
1681         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1682                 if (HAS_PCH_IBX(dev_priv->dev) &&
1683                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1684                         val |= TRANS_LEGACY_INTERLACED_ILK;
1685                 else
1686                         val |= TRANS_INTERLACED;
1687         else
1688                 val |= TRANS_PROGRESSIVE;
1689
1690         I915_WRITE(reg, val | TRANS_ENABLE);
1691         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1692                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1693 }
1694
1695 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1696                                      enum pipe pipe)
1697 {
1698         int reg;
1699         u32 val;
1700
1701         /* FDI relies on the transcoder */
1702         assert_fdi_tx_disabled(dev_priv, pipe);
1703         assert_fdi_rx_disabled(dev_priv, pipe);
1704
1705         /* Ports must be off as well */
1706         assert_pch_ports_disabled(dev_priv, pipe);
1707
1708         reg = TRANSCONF(pipe);
1709         val = I915_READ(reg);
1710         val &= ~TRANS_ENABLE;
1711         I915_WRITE(reg, val);
1712         /* wait for PCH transcoder off, transcoder state */
1713         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1714                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1715 }
1716
1717 /**
1718  * intel_enable_pipe - enable a pipe, asserting requirements
1719  * @dev_priv: i915 private structure
1720  * @pipe: pipe to enable
1721  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1722  *
1723  * Enable @pipe, making sure that various hardware specific requirements
1724  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1725  *
1726  * @pipe should be %PIPE_A or %PIPE_B.
1727  *
1728  * Will wait until the pipe is actually running (i.e. first vblank) before
1729  * returning.
1730  */
1731 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1732                               bool pch_port)
1733 {
1734         int reg;
1735         u32 val;
1736
1737         /*
1738          * A pipe without a PLL won't actually be able to drive bits from
1739          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1740          * need the check.
1741          */
1742         if (!HAS_PCH_SPLIT(dev_priv->dev))
1743                 assert_pll_enabled(dev_priv, pipe);
1744         else {
1745                 if (pch_port) {
1746                         /* if driving the PCH, we need FDI enabled */
1747                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1748                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1749                 }
1750                 /* FIXME: assert CPU port conditions for SNB+ */
1751         }
1752
1753         reg = PIPECONF(pipe);
1754         val = I915_READ(reg);
1755         if (val & PIPECONF_ENABLE)
1756                 return;
1757
1758         I915_WRITE(reg, val | PIPECONF_ENABLE);
1759         intel_wait_for_vblank(dev_priv->dev, pipe);
1760 }
1761
1762 /**
1763  * intel_disable_pipe - disable a pipe, asserting requirements
1764  * @dev_priv: i915 private structure
1765  * @pipe: pipe to disable
1766  *
1767  * Disable @pipe, making sure that various hardware specific requirements
1768  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1769  *
1770  * @pipe should be %PIPE_A or %PIPE_B.
1771  *
1772  * Will wait until the pipe has shut down before returning.
1773  */
1774 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1775                                enum pipe pipe)
1776 {
1777         int reg;
1778         u32 val;
1779
1780         /*
1781          * Make sure planes won't keep trying to pump pixels to us,
1782          * or we might hang the display.
1783          */
1784         assert_planes_disabled(dev_priv, pipe);
1785
1786         /* Don't disable pipe A or pipe A PLLs if needed */
1787         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1788                 return;
1789
1790         reg = PIPECONF(pipe);
1791         val = I915_READ(reg);
1792         if ((val & PIPECONF_ENABLE) == 0)
1793                 return;
1794
1795         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1796         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1797 }
1798
1799 /*
1800  * Plane regs are double buffered, going from enabled->disabled needs a
1801  * trigger in order to latch.  The display address reg provides this.
1802  */
1803 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1804                                       enum plane plane)
1805 {
1806         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1807         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1808 }
1809
1810 /**
1811  * intel_enable_plane - enable a display plane on a given pipe
1812  * @dev_priv: i915 private structure
1813  * @plane: plane to enable
1814  * @pipe: pipe being fed
1815  *
1816  * Enable @plane on @pipe, making sure that @pipe is running first.
1817  */
1818 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1819                                enum plane plane, enum pipe pipe)
1820 {
1821         int reg;
1822         u32 val;
1823
1824         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1825         assert_pipe_enabled(dev_priv, pipe);
1826
1827         reg = DSPCNTR(plane);
1828         val = I915_READ(reg);
1829         if (val & DISPLAY_PLANE_ENABLE)
1830                 return;
1831
1832         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1833         intel_flush_display_plane(dev_priv, plane);
1834         intel_wait_for_vblank(dev_priv->dev, pipe);
1835 }
1836
1837 /**
1838  * intel_disable_plane - disable a display plane
1839  * @dev_priv: i915 private structure
1840  * @plane: plane to disable
1841  * @pipe: pipe consuming the data
1842  *
1843  * Disable @plane; should be an independent operation.
1844  */
1845 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1846                                 enum plane plane, enum pipe pipe)
1847 {
1848         int reg;
1849         u32 val;
1850
1851         reg = DSPCNTR(plane);
1852         val = I915_READ(reg);
1853         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1854                 return;
1855
1856         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1857         intel_flush_display_plane(dev_priv, plane);
1858         intel_wait_for_vblank(dev_priv->dev, pipe);
1859 }
1860
1861 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1862                            enum pipe pipe, int reg, u32 port_sel)
1863 {
1864         u32 val = I915_READ(reg);
1865         if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1866                 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1867                 I915_WRITE(reg, val & ~DP_PORT_EN);
1868         }
1869 }
1870
1871 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1872                              enum pipe pipe, int reg)
1873 {
1874         u32 val = I915_READ(reg);
1875         if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1876                 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1877                               reg, pipe);
1878                 I915_WRITE(reg, val & ~PORT_ENABLE);
1879         }
1880 }
1881
1882 /* Disable any ports connected to this transcoder */
1883 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1884                                     enum pipe pipe)
1885 {
1886         u32 reg, val;
1887
1888         val = I915_READ(PCH_PP_CONTROL);
1889         I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1890
1891         disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1892         disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1893         disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1894
1895         reg = PCH_ADPA;
1896         val = I915_READ(reg);
1897         if (adpa_pipe_enabled(dev_priv, val, pipe))
1898                 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1899
1900         reg = PCH_LVDS;
1901         val = I915_READ(reg);
1902         if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1903                 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1904                 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1905                 POSTING_READ(reg);
1906                 udelay(100);
1907         }
1908
1909         disable_pch_hdmi(dev_priv, pipe, HDMIB);
1910         disable_pch_hdmi(dev_priv, pipe, HDMIC);
1911         disable_pch_hdmi(dev_priv, pipe, HDMID);
1912 }
1913
1914 int
1915 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1916                            struct drm_i915_gem_object *obj,
1917                            struct intel_ring_buffer *pipelined)
1918 {
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         u32 alignment;
1921         int ret;
1922
1923         switch (obj->tiling_mode) {
1924         case I915_TILING_NONE:
1925                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1926                         alignment = 128 * 1024;
1927                 else if (INTEL_INFO(dev)->gen >= 4)
1928                         alignment = 4 * 1024;
1929                 else
1930                         alignment = 64 * 1024;
1931                 break;
1932         case I915_TILING_X:
1933                 /* pin() will align the object as required by fence */
1934                 alignment = 0;
1935                 break;
1936         case I915_TILING_Y:
1937                 /* FIXME: Is this true? */
1938                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1939                 return -EINVAL;
1940         default:
1941                 BUG();
1942         }
1943
1944         dev_priv->mm.interruptible = false;
1945         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1946         if (ret)
1947                 goto err_interruptible;
1948
1949         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1950          * fence, whereas 965+ only requires a fence if using
1951          * framebuffer compression.  For simplicity, we always install
1952          * a fence as the cost is not that onerous.
1953          */
1954         ret = i915_gem_object_get_fence(obj);
1955         if (ret)
1956                 goto err_unpin;
1957
1958         i915_gem_object_pin_fence(obj);
1959
1960         dev_priv->mm.interruptible = true;
1961         return 0;
1962
1963 err_unpin:
1964         i915_gem_object_unpin(obj);
1965 err_interruptible:
1966         dev_priv->mm.interruptible = true;
1967         return ret;
1968 }
1969
1970 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1971 {
1972         i915_gem_object_unpin_fence(obj);
1973         i915_gem_object_unpin(obj);
1974 }
1975
1976 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1977                              int x, int y)
1978 {
1979         struct drm_device *dev = crtc->dev;
1980         struct drm_i915_private *dev_priv = dev->dev_private;
1981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1982         struct intel_framebuffer *intel_fb;
1983         struct drm_i915_gem_object *obj;
1984         int plane = intel_crtc->plane;
1985         unsigned long Start, Offset;
1986         u32 dspcntr;
1987         u32 reg;
1988
1989         switch (plane) {
1990         case 0:
1991         case 1:
1992                 break;
1993         default:
1994                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1995                 return -EINVAL;
1996         }
1997
1998         intel_fb = to_intel_framebuffer(fb);
1999         obj = intel_fb->obj;
2000
2001         reg = DSPCNTR(plane);
2002         dspcntr = I915_READ(reg);
2003         /* Mask out pixel format bits in case we change it */
2004         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2005         switch (fb->bits_per_pixel) {
2006         case 8:
2007                 dspcntr |= DISPPLANE_8BPP;
2008                 break;
2009         case 16:
2010                 if (fb->depth == 15)
2011                         dspcntr |= DISPPLANE_15_16BPP;
2012                 else
2013                         dspcntr |= DISPPLANE_16BPP;
2014                 break;
2015         case 24:
2016         case 32:
2017                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2018                 break;
2019         default:
2020                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2021                 return -EINVAL;
2022         }
2023         if (INTEL_INFO(dev)->gen >= 4) {
2024                 if (obj->tiling_mode != I915_TILING_NONE)
2025                         dspcntr |= DISPPLANE_TILED;
2026                 else
2027                         dspcntr &= ~DISPPLANE_TILED;
2028         }
2029
2030         I915_WRITE(reg, dspcntr);
2031
2032         Start = obj->gtt_offset;
2033         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2034
2035         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2036                       Start, Offset, x, y, fb->pitches[0]);
2037         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2038         if (INTEL_INFO(dev)->gen >= 4) {
2039                 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
2040                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2041                 I915_WRITE(DSPADDR(plane), Offset);
2042         } else
2043                 I915_WRITE(DSPADDR(plane), Start + Offset);
2044         POSTING_READ(reg);
2045
2046         return 0;
2047 }
2048
2049 static int ironlake_update_plane(struct drm_crtc *crtc,
2050                                  struct drm_framebuffer *fb, int x, int y)
2051 {
2052         struct drm_device *dev = crtc->dev;
2053         struct drm_i915_private *dev_priv = dev->dev_private;
2054         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2055         struct intel_framebuffer *intel_fb;
2056         struct drm_i915_gem_object *obj;
2057         int plane = intel_crtc->plane;
2058         unsigned long Start, Offset;
2059         u32 dspcntr;
2060         u32 reg;
2061
2062         switch (plane) {
2063         case 0:
2064         case 1:
2065         case 2:
2066                 break;
2067         default:
2068                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2069                 return -EINVAL;
2070         }
2071
2072         intel_fb = to_intel_framebuffer(fb);
2073         obj = intel_fb->obj;
2074
2075         reg = DSPCNTR(plane);
2076         dspcntr = I915_READ(reg);
2077         /* Mask out pixel format bits in case we change it */
2078         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2079         switch (fb->bits_per_pixel) {
2080         case 8:
2081                 dspcntr |= DISPPLANE_8BPP;
2082                 break;
2083         case 16:
2084                 if (fb->depth != 16)
2085                         return -EINVAL;
2086
2087                 dspcntr |= DISPPLANE_16BPP;
2088                 break;
2089         case 24:
2090         case 32:
2091                 if (fb->depth == 24)
2092                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2093                 else if (fb->depth == 30)
2094                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2095                 else
2096                         return -EINVAL;
2097                 break;
2098         default:
2099                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2100                 return -EINVAL;
2101         }
2102
2103         if (obj->tiling_mode != I915_TILING_NONE)
2104                 dspcntr |= DISPPLANE_TILED;
2105         else
2106                 dspcntr &= ~DISPPLANE_TILED;
2107
2108         /* must disable */
2109         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2110
2111         I915_WRITE(reg, dspcntr);
2112
2113         Start = obj->gtt_offset;
2114         Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2115
2116         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2117                       Start, Offset, x, y, fb->pitches[0]);
2118         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119         I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
2120         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2121         I915_WRITE(DSPADDR(plane), Offset);
2122         POSTING_READ(reg);
2123
2124         return 0;
2125 }
2126
2127 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2128 static int
2129 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2130                            int x, int y, enum mode_set_atomic state)
2131 {
2132         struct drm_device *dev = crtc->dev;
2133         struct drm_i915_private *dev_priv = dev->dev_private;
2134
2135         if (dev_priv->display.disable_fbc)
2136                 dev_priv->display.disable_fbc(dev);
2137         intel_increase_pllclock(crtc);
2138
2139         return dev_priv->display.update_plane(crtc, fb, x, y);
2140 }
2141
2142 static int
2143 intel_finish_fb(struct drm_framebuffer *old_fb)
2144 {
2145         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2146         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2147         bool was_interruptible = dev_priv->mm.interruptible;
2148         int ret;
2149
2150         wait_event(dev_priv->pending_flip_queue,
2151                    atomic_read(&dev_priv->mm.wedged) ||
2152                    atomic_read(&obj->pending_flip) == 0);
2153
2154         /* Big Hammer, we also need to ensure that any pending
2155          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2156          * current scanout is retired before unpinning the old
2157          * framebuffer.
2158          *
2159          * This should only fail upon a hung GPU, in which case we
2160          * can safely continue.
2161          */
2162         dev_priv->mm.interruptible = false;
2163         ret = i915_gem_object_finish_gpu(obj);
2164         dev_priv->mm.interruptible = was_interruptible;
2165
2166         return ret;
2167 }
2168
2169 static int
2170 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2171                     struct drm_framebuffer *old_fb)
2172 {
2173         struct drm_device *dev = crtc->dev;
2174         struct drm_i915_private *dev_priv = dev->dev_private;
2175         struct drm_i915_master_private *master_priv;
2176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2177         int ret;
2178
2179         /* no fb bound */
2180         if (!crtc->fb) {
2181                 DRM_ERROR("No FB bound\n");
2182                 return 0;
2183         }
2184
2185         if(intel_crtc->plane > dev_priv->num_pipe) {
2186                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2187                                 intel_crtc->plane,
2188                                 dev_priv->num_pipe);
2189                 return -EINVAL;
2190         }
2191
2192         mutex_lock(&dev->struct_mutex);
2193         ret = intel_pin_and_fence_fb_obj(dev,
2194                                          to_intel_framebuffer(crtc->fb)->obj,
2195                                          NULL);
2196         if (ret != 0) {
2197                 mutex_unlock(&dev->struct_mutex);
2198                 DRM_ERROR("pin & fence failed\n");
2199                 return ret;
2200         }
2201
2202         if (old_fb)
2203                 intel_finish_fb(old_fb);
2204
2205         ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2206         if (ret) {
2207                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2208                 mutex_unlock(&dev->struct_mutex);
2209                 DRM_ERROR("failed to update base address\n");
2210                 return ret;
2211         }
2212
2213         if (old_fb) {
2214                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2215                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2216         }
2217
2218         intel_update_fbc(dev);
2219         mutex_unlock(&dev->struct_mutex);
2220
2221         if (!dev->primary->master)
2222                 return 0;
2223
2224         master_priv = dev->primary->master->driver_priv;
2225         if (!master_priv->sarea_priv)
2226                 return 0;
2227
2228         if (intel_crtc->pipe) {
2229                 master_priv->sarea_priv->pipeB_x = x;
2230                 master_priv->sarea_priv->pipeB_y = y;
2231         } else {
2232                 master_priv->sarea_priv->pipeA_x = x;
2233                 master_priv->sarea_priv->pipeA_y = y;
2234         }
2235
2236         return 0;
2237 }
2238
2239 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2240 {
2241         struct drm_device *dev = crtc->dev;
2242         struct drm_i915_private *dev_priv = dev->dev_private;
2243         u32 dpa_ctl;
2244
2245         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2246         dpa_ctl = I915_READ(DP_A);
2247         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2248
2249         if (clock < 200000) {
2250                 u32 temp;
2251                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2252                 /* workaround for 160Mhz:
2253                    1) program 0x4600c bits 15:0 = 0x8124
2254                    2) program 0x46010 bit 0 = 1
2255                    3) program 0x46034 bit 24 = 1
2256                    4) program 0x64000 bit 14 = 1
2257                    */
2258                 temp = I915_READ(0x4600c);
2259                 temp &= 0xffff0000;
2260                 I915_WRITE(0x4600c, temp | 0x8124);
2261
2262                 temp = I915_READ(0x46010);
2263                 I915_WRITE(0x46010, temp | 1);
2264
2265                 temp = I915_READ(0x46034);
2266                 I915_WRITE(0x46034, temp | (1 << 24));
2267         } else {
2268                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2269         }
2270         I915_WRITE(DP_A, dpa_ctl);
2271
2272         POSTING_READ(DP_A);
2273         udelay(500);
2274 }
2275
2276 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2277 {
2278         struct drm_device *dev = crtc->dev;
2279         struct drm_i915_private *dev_priv = dev->dev_private;
2280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2281         int pipe = intel_crtc->pipe;
2282         u32 reg, temp;
2283
2284         /* enable normal train */
2285         reg = FDI_TX_CTL(pipe);
2286         temp = I915_READ(reg);
2287         if (IS_IVYBRIDGE(dev)) {
2288                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2289                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2290         } else {
2291                 temp &= ~FDI_LINK_TRAIN_NONE;
2292                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2293         }
2294         I915_WRITE(reg, temp);
2295
2296         reg = FDI_RX_CTL(pipe);
2297         temp = I915_READ(reg);
2298         if (HAS_PCH_CPT(dev)) {
2299                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2300                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2301         } else {
2302                 temp &= ~FDI_LINK_TRAIN_NONE;
2303                 temp |= FDI_LINK_TRAIN_NONE;
2304         }
2305         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2306
2307         /* wait one idle pattern time */
2308         POSTING_READ(reg);
2309         udelay(1000);
2310
2311         /* IVB wants error correction enabled */
2312         if (IS_IVYBRIDGE(dev))
2313                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2314                            FDI_FE_ERRC_ENABLE);
2315 }
2316
2317 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2318 {
2319         struct drm_i915_private *dev_priv = dev->dev_private;
2320         u32 flags = I915_READ(SOUTH_CHICKEN1);
2321
2322         flags |= FDI_PHASE_SYNC_OVR(pipe);
2323         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2324         flags |= FDI_PHASE_SYNC_EN(pipe);
2325         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2326         POSTING_READ(SOUTH_CHICKEN1);
2327 }
2328
2329 /* The FDI link training functions for ILK/Ibexpeak. */
2330 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2331 {
2332         struct drm_device *dev = crtc->dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335         int pipe = intel_crtc->pipe;
2336         int plane = intel_crtc->plane;
2337         u32 reg, temp, tries;
2338
2339         /* FDI needs bits from pipe & plane first */
2340         assert_pipe_enabled(dev_priv, pipe);
2341         assert_plane_enabled(dev_priv, plane);
2342
2343         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2344            for train result */
2345         reg = FDI_RX_IMR(pipe);
2346         temp = I915_READ(reg);
2347         temp &= ~FDI_RX_SYMBOL_LOCK;
2348         temp &= ~FDI_RX_BIT_LOCK;
2349         I915_WRITE(reg, temp);
2350         I915_READ(reg);
2351         udelay(150);
2352
2353         /* enable CPU FDI TX and PCH FDI RX */
2354         reg = FDI_TX_CTL(pipe);
2355         temp = I915_READ(reg);
2356         temp &= ~(7 << 19);
2357         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2358         temp &= ~FDI_LINK_TRAIN_NONE;
2359         temp |= FDI_LINK_TRAIN_PATTERN_1;
2360         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2361
2362         reg = FDI_RX_CTL(pipe);
2363         temp = I915_READ(reg);
2364         temp &= ~FDI_LINK_TRAIN_NONE;
2365         temp |= FDI_LINK_TRAIN_PATTERN_1;
2366         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2367
2368         POSTING_READ(reg);
2369         udelay(150);
2370
2371         /* Ironlake workaround, enable clock pointer after FDI enable*/
2372         if (HAS_PCH_IBX(dev)) {
2373                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2374                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2375                            FDI_RX_PHASE_SYNC_POINTER_EN);
2376         }
2377
2378         reg = FDI_RX_IIR(pipe);
2379         for (tries = 0; tries < 5; tries++) {
2380                 temp = I915_READ(reg);
2381                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2382
2383                 if ((temp & FDI_RX_BIT_LOCK)) {
2384                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2385                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2386                         break;
2387                 }
2388         }
2389         if (tries == 5)
2390                 DRM_ERROR("FDI train 1 fail!\n");
2391
2392         /* Train 2 */
2393         reg = FDI_TX_CTL(pipe);
2394         temp = I915_READ(reg);
2395         temp &= ~FDI_LINK_TRAIN_NONE;
2396         temp |= FDI_LINK_TRAIN_PATTERN_2;
2397         I915_WRITE(reg, temp);
2398
2399         reg = FDI_RX_CTL(pipe);
2400         temp = I915_READ(reg);
2401         temp &= ~FDI_LINK_TRAIN_NONE;
2402         temp |= FDI_LINK_TRAIN_PATTERN_2;
2403         I915_WRITE(reg, temp);
2404
2405         POSTING_READ(reg);
2406         udelay(150);
2407
2408         reg = FDI_RX_IIR(pipe);
2409         for (tries = 0; tries < 5; tries++) {
2410                 temp = I915_READ(reg);
2411                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412
2413                 if (temp & FDI_RX_SYMBOL_LOCK) {
2414                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2415                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2416                         break;
2417                 }
2418         }
2419         if (tries == 5)
2420                 DRM_ERROR("FDI train 2 fail!\n");
2421
2422         DRM_DEBUG_KMS("FDI train done\n");
2423
2424 }
2425
2426 static const int snb_b_fdi_train_param[] = {
2427         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2428         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2429         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2430         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2431 };
2432
2433 /* The FDI link training functions for SNB/Cougarpoint. */
2434 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2435 {
2436         struct drm_device *dev = crtc->dev;
2437         struct drm_i915_private *dev_priv = dev->dev_private;
2438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2439         int pipe = intel_crtc->pipe;
2440         u32 reg, temp, i, retry;
2441
2442         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2443            for train result */
2444         reg = FDI_RX_IMR(pipe);
2445         temp = I915_READ(reg);
2446         temp &= ~FDI_RX_SYMBOL_LOCK;
2447         temp &= ~FDI_RX_BIT_LOCK;
2448         I915_WRITE(reg, temp);
2449
2450         POSTING_READ(reg);
2451         udelay(150);
2452
2453         /* enable CPU FDI TX and PCH FDI RX */
2454         reg = FDI_TX_CTL(pipe);
2455         temp = I915_READ(reg);
2456         temp &= ~(7 << 19);
2457         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2458         temp &= ~FDI_LINK_TRAIN_NONE;
2459         temp |= FDI_LINK_TRAIN_PATTERN_1;
2460         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2461         /* SNB-B */
2462         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2463         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2464
2465         reg = FDI_RX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         if (HAS_PCH_CPT(dev)) {
2468                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2469                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2470         } else {
2471                 temp &= ~FDI_LINK_TRAIN_NONE;
2472                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2473         }
2474         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2475
2476         POSTING_READ(reg);
2477         udelay(150);
2478
2479         if (HAS_PCH_CPT(dev))
2480                 cpt_phase_pointer_enable(dev, pipe);
2481
2482         for (i = 0; i < 4; i++) {
2483                 reg = FDI_TX_CTL(pipe);
2484                 temp = I915_READ(reg);
2485                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486                 temp |= snb_b_fdi_train_param[i];
2487                 I915_WRITE(reg, temp);
2488
2489                 POSTING_READ(reg);
2490                 udelay(500);
2491
2492                 for (retry = 0; retry < 5; retry++) {
2493                         reg = FDI_RX_IIR(pipe);
2494                         temp = I915_READ(reg);
2495                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2496                         if (temp & FDI_RX_BIT_LOCK) {
2497                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2498                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2499                                 break;
2500                         }
2501                         udelay(50);
2502                 }
2503                 if (retry < 5)
2504                         break;
2505         }
2506         if (i == 4)
2507                 DRM_ERROR("FDI train 1 fail!\n");
2508
2509         /* Train 2 */
2510         reg = FDI_TX_CTL(pipe);
2511         temp = I915_READ(reg);
2512         temp &= ~FDI_LINK_TRAIN_NONE;
2513         temp |= FDI_LINK_TRAIN_PATTERN_2;
2514         if (IS_GEN6(dev)) {
2515                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516                 /* SNB-B */
2517                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2518         }
2519         I915_WRITE(reg, temp);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         if (HAS_PCH_CPT(dev)) {
2524                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2525                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2526         } else {
2527                 temp &= ~FDI_LINK_TRAIN_NONE;
2528                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2529         }
2530         I915_WRITE(reg, temp);
2531
2532         POSTING_READ(reg);
2533         udelay(150);
2534
2535         for (i = 0; i < 4; i++) {
2536                 reg = FDI_TX_CTL(pipe);
2537                 temp = I915_READ(reg);
2538                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539                 temp |= snb_b_fdi_train_param[i];
2540                 I915_WRITE(reg, temp);
2541
2542                 POSTING_READ(reg);
2543                 udelay(500);
2544
2545                 for (retry = 0; retry < 5; retry++) {
2546                         reg = FDI_RX_IIR(pipe);
2547                         temp = I915_READ(reg);
2548                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2549                         if (temp & FDI_RX_SYMBOL_LOCK) {
2550                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2551                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2552                                 break;
2553                         }
2554                         udelay(50);
2555                 }
2556                 if (retry < 5)
2557                         break;
2558         }
2559         if (i == 4)
2560                 DRM_ERROR("FDI train 2 fail!\n");
2561
2562         DRM_DEBUG_KMS("FDI train done.\n");
2563 }
2564
2565 /* Manual link training for Ivy Bridge A0 parts */
2566 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2567 {
2568         struct drm_device *dev = crtc->dev;
2569         struct drm_i915_private *dev_priv = dev->dev_private;
2570         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2571         int pipe = intel_crtc->pipe;
2572         u32 reg, temp, i;
2573
2574         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2575            for train result */
2576         reg = FDI_RX_IMR(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_RX_SYMBOL_LOCK;
2579         temp &= ~FDI_RX_BIT_LOCK;
2580         I915_WRITE(reg, temp);
2581
2582         POSTING_READ(reg);
2583         udelay(150);
2584
2585         /* enable CPU FDI TX and PCH FDI RX */
2586         reg = FDI_TX_CTL(pipe);
2587         temp = I915_READ(reg);
2588         temp &= ~(7 << 19);
2589         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2590         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2591         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2592         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2593         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2594         temp |= FDI_COMPOSITE_SYNC;
2595         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2596
2597         reg = FDI_RX_CTL(pipe);
2598         temp = I915_READ(reg);
2599         temp &= ~FDI_LINK_TRAIN_AUTO;
2600         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2601         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2602         temp |= FDI_COMPOSITE_SYNC;
2603         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2604
2605         POSTING_READ(reg);
2606         udelay(150);
2607
2608         if (HAS_PCH_CPT(dev))
2609                 cpt_phase_pointer_enable(dev, pipe);
2610
2611         for (i = 0; i < 4; i++) {
2612                 reg = FDI_TX_CTL(pipe);
2613                 temp = I915_READ(reg);
2614                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615                 temp |= snb_b_fdi_train_param[i];
2616                 I915_WRITE(reg, temp);
2617
2618                 POSTING_READ(reg);
2619                 udelay(500);
2620
2621                 reg = FDI_RX_IIR(pipe);
2622                 temp = I915_READ(reg);
2623                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2624
2625                 if (temp & FDI_RX_BIT_LOCK ||
2626                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2627                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2628                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2629                         break;
2630                 }
2631         }
2632         if (i == 4)
2633                 DRM_ERROR("FDI train 1 fail!\n");
2634
2635         /* Train 2 */
2636         reg = FDI_TX_CTL(pipe);
2637         temp = I915_READ(reg);
2638         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2639         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2640         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642         I915_WRITE(reg, temp);
2643
2644         reg = FDI_RX_CTL(pipe);
2645         temp = I915_READ(reg);
2646         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2648         I915_WRITE(reg, temp);
2649
2650         POSTING_READ(reg);
2651         udelay(150);
2652
2653         for (i = 0; i < 4; i++) {
2654                 reg = FDI_TX_CTL(pipe);
2655                 temp = I915_READ(reg);
2656                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657                 temp |= snb_b_fdi_train_param[i];
2658                 I915_WRITE(reg, temp);
2659
2660                 POSTING_READ(reg);
2661                 udelay(500);
2662
2663                 reg = FDI_RX_IIR(pipe);
2664                 temp = I915_READ(reg);
2665                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666
2667                 if (temp & FDI_RX_SYMBOL_LOCK) {
2668                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2669                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2670                         break;
2671                 }
2672         }
2673         if (i == 4)
2674                 DRM_ERROR("FDI train 2 fail!\n");
2675
2676         DRM_DEBUG_KMS("FDI train done.\n");
2677 }
2678
2679 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2680 {
2681         struct drm_device *dev = crtc->dev;
2682         struct drm_i915_private *dev_priv = dev->dev_private;
2683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2684         int pipe = intel_crtc->pipe;
2685         u32 reg, temp;
2686
2687         /* Write the TU size bits so error detection works */
2688         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2689                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2690
2691         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2692         reg = FDI_RX_CTL(pipe);
2693         temp = I915_READ(reg);
2694         temp &= ~((0x7 << 19) | (0x7 << 16));
2695         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2696         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2697         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2698
2699         POSTING_READ(reg);
2700         udelay(200);
2701
2702         /* Switch from Rawclk to PCDclk */
2703         temp = I915_READ(reg);
2704         I915_WRITE(reg, temp | FDI_PCDCLK);
2705
2706         POSTING_READ(reg);
2707         udelay(200);
2708
2709         /* On Haswell, the PLL configuration for ports and pipes is handled
2710          * separately, as part of DDI setup */
2711         if (!IS_HASWELL(dev)) {
2712                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2713                 reg = FDI_TX_CTL(pipe);
2714                 temp = I915_READ(reg);
2715                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2716                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2717
2718                         POSTING_READ(reg);
2719                         udelay(100);
2720                 }
2721         }
2722 }
2723
2724 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2725 {
2726         struct drm_i915_private *dev_priv = dev->dev_private;
2727         u32 flags = I915_READ(SOUTH_CHICKEN1);
2728
2729         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2730         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2731         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2732         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2733         POSTING_READ(SOUTH_CHICKEN1);
2734 }
2735 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int pipe = intel_crtc->pipe;
2741         u32 reg, temp;
2742
2743         /* disable CPU FDI tx and PCH FDI rx */
2744         reg = FDI_TX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747         POSTING_READ(reg);
2748
2749         reg = FDI_RX_CTL(pipe);
2750         temp = I915_READ(reg);
2751         temp &= ~(0x7 << 16);
2752         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2753         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755         POSTING_READ(reg);
2756         udelay(100);
2757
2758         /* Ironlake workaround, disable clock pointer after downing FDI */
2759         if (HAS_PCH_IBX(dev)) {
2760                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2761                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2762                            I915_READ(FDI_RX_CHICKEN(pipe) &
2763                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2764         } else if (HAS_PCH_CPT(dev)) {
2765                 cpt_phase_pointer_disable(dev, pipe);
2766         }
2767
2768         /* still set train pattern 1 */
2769         reg = FDI_TX_CTL(pipe);
2770         temp = I915_READ(reg);
2771         temp &= ~FDI_LINK_TRAIN_NONE;
2772         temp |= FDI_LINK_TRAIN_PATTERN_1;
2773         I915_WRITE(reg, temp);
2774
2775         reg = FDI_RX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         if (HAS_PCH_CPT(dev)) {
2778                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2779                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2780         } else {
2781                 temp &= ~FDI_LINK_TRAIN_NONE;
2782                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2783         }
2784         /* BPC in FDI rx is consistent with that in PIPECONF */
2785         temp &= ~(0x07 << 16);
2786         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2787         I915_WRITE(reg, temp);
2788
2789         POSTING_READ(reg);
2790         udelay(100);
2791 }
2792
2793 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2794 {
2795         struct drm_device *dev = crtc->dev;
2796
2797         if (crtc->fb == NULL)
2798                 return;
2799
2800         mutex_lock(&dev->struct_mutex);
2801         intel_finish_fb(crtc->fb);
2802         mutex_unlock(&dev->struct_mutex);
2803 }
2804
2805 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2806 {
2807         struct drm_device *dev = crtc->dev;
2808         struct drm_mode_config *mode_config = &dev->mode_config;
2809         struct intel_encoder *encoder;
2810
2811         /*
2812          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2813          * must be driven by its own crtc; no sharing is possible.
2814          */
2815         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2816                 if (encoder->base.crtc != crtc)
2817                         continue;
2818
2819                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2820                  * CPU handles all others */
2821                 if (IS_HASWELL(dev)) {
2822                         /* It is still unclear how this will work on PPT, so throw up a warning */
2823                         WARN_ON(!HAS_PCH_LPT(dev));
2824
2825                         if (encoder->type == DRM_MODE_ENCODER_DAC) {
2826                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2827                                 return true;
2828                         } else {
2829                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2830                                                 encoder->type);
2831                                 return false;
2832                         }
2833                 }
2834
2835                 switch (encoder->type) {
2836                 case INTEL_OUTPUT_EDP:
2837                         if (!intel_encoder_is_pch_edp(&encoder->base))
2838                                 return false;
2839                         continue;
2840                 }
2841         }
2842
2843         return true;
2844 }
2845
2846 /* Program iCLKIP clock to the desired frequency */
2847 static void lpt_program_iclkip(struct drm_crtc *crtc)
2848 {
2849         struct drm_device *dev = crtc->dev;
2850         struct drm_i915_private *dev_priv = dev->dev_private;
2851         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2852         u32 temp;
2853
2854         /* It is necessary to ungate the pixclk gate prior to programming
2855          * the divisors, and gate it back when it is done.
2856          */
2857         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2858
2859         /* Disable SSCCTL */
2860         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2861                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2862                                         SBI_SSCCTL_DISABLE);
2863
2864         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2865         if (crtc->mode.clock == 20000) {
2866                 auxdiv = 1;
2867                 divsel = 0x41;
2868                 phaseinc = 0x20;
2869         } else {
2870                 /* The iCLK virtual clock root frequency is in MHz,
2871                  * but the crtc->mode.clock in in KHz. To get the divisors,
2872                  * it is necessary to divide one by another, so we
2873                  * convert the virtual clock precision to KHz here for higher
2874                  * precision.
2875                  */
2876                 u32 iclk_virtual_root_freq = 172800 * 1000;
2877                 u32 iclk_pi_range = 64;
2878                 u32 desired_divisor, msb_divisor_value, pi_value;
2879
2880                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2881                 msb_divisor_value = desired_divisor / iclk_pi_range;
2882                 pi_value = desired_divisor % iclk_pi_range;
2883
2884                 auxdiv = 0;
2885                 divsel = msb_divisor_value - 2;
2886                 phaseinc = pi_value;
2887         }
2888
2889         /* This should not happen with any sane values */
2890         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2891                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2892         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2893                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2894
2895         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2896                         crtc->mode.clock,
2897                         auxdiv,
2898                         divsel,
2899                         phasedir,
2900                         phaseinc);
2901
2902         /* Program SSCDIVINTPHASE6 */
2903         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2904         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2905         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2906         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2907         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2908         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2909         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2910
2911         intel_sbi_write(dev_priv,
2912                         SBI_SSCDIVINTPHASE6,
2913                         temp);
2914
2915         /* Program SSCAUXDIV */
2916         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2917         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2918         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2919         intel_sbi_write(dev_priv,
2920                         SBI_SSCAUXDIV6,
2921                         temp);
2922
2923
2924         /* Enable modulator and associated divider */
2925         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2926         temp &= ~SBI_SSCCTL_DISABLE;
2927         intel_sbi_write(dev_priv,
2928                         SBI_SSCCTL6,
2929                         temp);
2930
2931         /* Wait for initialization time */
2932         udelay(24);
2933
2934         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2935 }
2936
2937 /*
2938  * Enable PCH resources required for PCH ports:
2939  *   - PCH PLLs
2940  *   - FDI training & RX/TX
2941  *   - update transcoder timings
2942  *   - DP transcoding bits
2943  *   - transcoder
2944  */
2945 static void ironlake_pch_enable(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950         int pipe = intel_crtc->pipe;
2951         u32 reg, temp;
2952
2953         assert_transcoder_disabled(dev_priv, pipe);
2954
2955         /* For PCH output, training FDI link */
2956         dev_priv->display.fdi_link_train(crtc);
2957
2958         intel_enable_pch_pll(intel_crtc);
2959
2960         if (HAS_PCH_LPT(dev)) {
2961                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2962                 lpt_program_iclkip(crtc);
2963         } else if (HAS_PCH_CPT(dev)) {
2964                 u32 sel;
2965
2966                 temp = I915_READ(PCH_DPLL_SEL);
2967                 switch (pipe) {
2968                 default:
2969                 case 0:
2970                         temp |= TRANSA_DPLL_ENABLE;
2971                         sel = TRANSA_DPLLB_SEL;
2972                         break;
2973                 case 1:
2974                         temp |= TRANSB_DPLL_ENABLE;
2975                         sel = TRANSB_DPLLB_SEL;
2976                         break;
2977                 case 2:
2978                         temp |= TRANSC_DPLL_ENABLE;
2979                         sel = TRANSC_DPLLB_SEL;
2980                         break;
2981                 }
2982                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2983                         temp |= sel;
2984                 else
2985                         temp &= ~sel;
2986                 I915_WRITE(PCH_DPLL_SEL, temp);
2987         }
2988
2989         /* set transcoder timing, panel must allow it */
2990         assert_panel_unlocked(dev_priv, pipe);
2991         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2992         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2993         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2994
2995         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2996         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2997         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2998         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
2999
3000         if (!IS_HASWELL(dev))
3001                 intel_fdi_normal_train(crtc);
3002
3003         /* For PCH DP, enable TRANS_DP_CTL */
3004         if (HAS_PCH_CPT(dev) &&
3005             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3006              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3007                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3008                 reg = TRANS_DP_CTL(pipe);
3009                 temp = I915_READ(reg);
3010                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3011                           TRANS_DP_SYNC_MASK |
3012                           TRANS_DP_BPC_MASK);
3013                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3014                          TRANS_DP_ENH_FRAMING);
3015                 temp |= bpc << 9; /* same format but at 11:9 */
3016
3017                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3018                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3019                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3020                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3021
3022                 switch (intel_trans_dp_port_sel(crtc)) {
3023                 case PCH_DP_B:
3024                         temp |= TRANS_DP_PORT_SEL_B;
3025                         break;
3026                 case PCH_DP_C:
3027                         temp |= TRANS_DP_PORT_SEL_C;
3028                         break;
3029                 case PCH_DP_D:
3030                         temp |= TRANS_DP_PORT_SEL_D;
3031                         break;
3032                 default:
3033                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3034                         temp |= TRANS_DP_PORT_SEL_B;
3035                         break;
3036                 }
3037
3038                 I915_WRITE(reg, temp);
3039         }
3040
3041         intel_enable_transcoder(dev_priv, pipe);
3042 }
3043
3044 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3045 {
3046         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3047
3048         if (pll == NULL)
3049                 return;
3050
3051         if (pll->refcount == 0) {
3052                 WARN(1, "bad PCH PLL refcount\n");
3053                 return;
3054         }
3055
3056         --pll->refcount;
3057         intel_crtc->pch_pll = NULL;
3058 }
3059
3060 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3061 {
3062         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3063         struct intel_pch_pll *pll;
3064         int i;
3065
3066         pll = intel_crtc->pch_pll;
3067         if (pll) {
3068                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3069                               intel_crtc->base.base.id, pll->pll_reg);
3070                 goto prepare;
3071         }
3072
3073         if (HAS_PCH_IBX(dev_priv->dev)) {
3074                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3075                 i = intel_crtc->pipe;
3076                 pll = &dev_priv->pch_plls[i];
3077
3078                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3079                               intel_crtc->base.base.id, pll->pll_reg);
3080
3081                 goto found;
3082         }
3083
3084         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3085                 pll = &dev_priv->pch_plls[i];
3086
3087                 /* Only want to check enabled timings first */
3088                 if (pll->refcount == 0)
3089                         continue;
3090
3091                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3092                     fp == I915_READ(pll->fp0_reg)) {
3093                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3094                                       intel_crtc->base.base.id,
3095                                       pll->pll_reg, pll->refcount, pll->active);
3096
3097                         goto found;
3098                 }
3099         }
3100
3101         /* Ok no matching timings, maybe there's a free one? */
3102         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3103                 pll = &dev_priv->pch_plls[i];
3104                 if (pll->refcount == 0) {
3105                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3106                                       intel_crtc->base.base.id, pll->pll_reg);
3107                         goto found;
3108                 }
3109         }
3110
3111         return NULL;
3112
3113 found:
3114         intel_crtc->pch_pll = pll;
3115         pll->refcount++;
3116         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3117 prepare: /* separate function? */
3118         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3119
3120         /* Wait for the clocks to stabilize before rewriting the regs */
3121         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3122         POSTING_READ(pll->pll_reg);
3123         udelay(150);
3124
3125         I915_WRITE(pll->fp0_reg, fp);
3126         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3127         pll->on = false;
3128         return pll;
3129 }
3130
3131 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3132 {
3133         struct drm_i915_private *dev_priv = dev->dev_private;
3134         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3135         u32 temp;
3136
3137         temp = I915_READ(dslreg);
3138         udelay(500);
3139         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3140                 /* Without this, mode sets may fail silently on FDI */
3141                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3142                 udelay(250);
3143                 I915_WRITE(tc2reg, 0);
3144                 if (wait_for(I915_READ(dslreg) != temp, 5))
3145                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3146         }
3147 }
3148
3149 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3150 {
3151         struct drm_device *dev = crtc->dev;
3152         struct drm_i915_private *dev_priv = dev->dev_private;
3153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3154         int pipe = intel_crtc->pipe;
3155         int plane = intel_crtc->plane;
3156         u32 temp;
3157         bool is_pch_port;
3158
3159         if (intel_crtc->active)
3160                 return;
3161
3162         intel_crtc->active = true;
3163         intel_update_watermarks(dev);
3164
3165         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3166                 temp = I915_READ(PCH_LVDS);
3167                 if ((temp & LVDS_PORT_EN) == 0)
3168                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3169         }
3170
3171         is_pch_port = intel_crtc_driving_pch(crtc);
3172
3173         if (is_pch_port)
3174                 ironlake_fdi_pll_enable(crtc);
3175         else
3176                 ironlake_fdi_disable(crtc);
3177
3178         /* Enable panel fitting for LVDS */
3179         if (dev_priv->pch_pf_size &&
3180             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3181                 /* Force use of hard-coded filter coefficients
3182                  * as some pre-programmed values are broken,
3183                  * e.g. x201.
3184                  */
3185                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3186                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3187                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3188         }
3189
3190         /*
3191          * On ILK+ LUT must be loaded before the pipe is running but with
3192          * clocks enabled
3193          */
3194         intel_crtc_load_lut(crtc);
3195
3196         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3197         intel_enable_plane(dev_priv, plane, pipe);
3198
3199         if (is_pch_port)
3200                 ironlake_pch_enable(crtc);
3201
3202         mutex_lock(&dev->struct_mutex);
3203         intel_update_fbc(dev);
3204         mutex_unlock(&dev->struct_mutex);
3205
3206         intel_crtc_update_cursor(crtc, true);
3207 }
3208
3209 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3210 {
3211         struct drm_device *dev = crtc->dev;
3212         struct drm_i915_private *dev_priv = dev->dev_private;
3213         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214         int pipe = intel_crtc->pipe;
3215         int plane = intel_crtc->plane;
3216         u32 reg, temp;
3217
3218         if (!intel_crtc->active)
3219                 return;
3220
3221         intel_crtc_wait_for_pending_flips(crtc);
3222         drm_vblank_off(dev, pipe);
3223         intel_crtc_update_cursor(crtc, false);
3224
3225         intel_disable_plane(dev_priv, plane, pipe);
3226
3227         if (dev_priv->cfb_plane == plane)
3228                 intel_disable_fbc(dev);
3229
3230         intel_disable_pipe(dev_priv, pipe);
3231
3232         /* Disable PF */
3233         I915_WRITE(PF_CTL(pipe), 0);
3234         I915_WRITE(PF_WIN_SZ(pipe), 0);
3235
3236         ironlake_fdi_disable(crtc);
3237
3238         /* This is a horrible layering violation; we should be doing this in
3239          * the connector/encoder ->prepare instead, but we don't always have
3240          * enough information there about the config to know whether it will
3241          * actually be necessary or just cause undesired flicker.
3242          */
3243         intel_disable_pch_ports(dev_priv, pipe);
3244
3245         intel_disable_transcoder(dev_priv, pipe);
3246
3247         if (HAS_PCH_CPT(dev)) {
3248                 /* disable TRANS_DP_CTL */
3249                 reg = TRANS_DP_CTL(pipe);
3250                 temp = I915_READ(reg);
3251                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3252                 temp |= TRANS_DP_PORT_SEL_NONE;
3253                 I915_WRITE(reg, temp);
3254
3255                 /* disable DPLL_SEL */
3256                 temp = I915_READ(PCH_DPLL_SEL);
3257                 switch (pipe) {
3258                 case 0:
3259                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3260                         break;
3261                 case 1:
3262                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3263                         break;
3264                 case 2:
3265                         /* C shares PLL A or B */
3266                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3267                         break;
3268                 default:
3269                         BUG(); /* wtf */
3270                 }
3271                 I915_WRITE(PCH_DPLL_SEL, temp);
3272         }
3273
3274         /* disable PCH DPLL */
3275         intel_disable_pch_pll(intel_crtc);
3276
3277         /* Switch from PCDclk to Rawclk */
3278         reg = FDI_RX_CTL(pipe);
3279         temp = I915_READ(reg);
3280         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3281
3282         /* Disable CPU FDI TX PLL */
3283         reg = FDI_TX_CTL(pipe);
3284         temp = I915_READ(reg);
3285         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3286
3287         POSTING_READ(reg);
3288         udelay(100);
3289
3290         reg = FDI_RX_CTL(pipe);
3291         temp = I915_READ(reg);
3292         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3293
3294         /* Wait for the clocks to turn off. */
3295         POSTING_READ(reg);
3296         udelay(100);
3297
3298         intel_crtc->active = false;
3299         intel_update_watermarks(dev);
3300
3301         mutex_lock(&dev->struct_mutex);
3302         intel_update_fbc(dev);
3303         mutex_unlock(&dev->struct_mutex);
3304 }
3305
3306 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3307 {
3308         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309         int pipe = intel_crtc->pipe;
3310         int plane = intel_crtc->plane;
3311
3312         /* XXX: When our outputs are all unaware of DPMS modes other than off
3313          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3314          */
3315         switch (mode) {
3316         case DRM_MODE_DPMS_ON:
3317         case DRM_MODE_DPMS_STANDBY:
3318         case DRM_MODE_DPMS_SUSPEND:
3319                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3320                 ironlake_crtc_enable(crtc);
3321                 break;
3322
3323         case DRM_MODE_DPMS_OFF:
3324                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3325                 ironlake_crtc_disable(crtc);
3326                 break;
3327         }
3328 }
3329
3330 static void ironlake_crtc_off(struct drm_crtc *crtc)
3331 {
3332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333         intel_put_pch_pll(intel_crtc);
3334 }
3335
3336 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3337 {
3338         if (!enable && intel_crtc->overlay) {
3339                 struct drm_device *dev = intel_crtc->base.dev;
3340                 struct drm_i915_private *dev_priv = dev->dev_private;
3341
3342                 mutex_lock(&dev->struct_mutex);
3343                 dev_priv->mm.interruptible = false;
3344                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3345                 dev_priv->mm.interruptible = true;
3346                 mutex_unlock(&dev->struct_mutex);
3347         }
3348
3349         /* Let userspace switch the overlay on again. In most cases userspace
3350          * has to recompute where to put it anyway.
3351          */
3352 }
3353
3354 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3355 {
3356         struct drm_device *dev = crtc->dev;
3357         struct drm_i915_private *dev_priv = dev->dev_private;
3358         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3359         int pipe = intel_crtc->pipe;
3360         int plane = intel_crtc->plane;
3361
3362         if (intel_crtc->active)
3363                 return;
3364
3365         intel_crtc->active = true;
3366         intel_update_watermarks(dev);
3367
3368         intel_enable_pll(dev_priv, pipe);
3369         intel_enable_pipe(dev_priv, pipe, false);
3370         intel_enable_plane(dev_priv, plane, pipe);
3371
3372         intel_crtc_load_lut(crtc);
3373         intel_update_fbc(dev);
3374
3375         /* Give the overlay scaler a chance to enable if it's on this pipe */
3376         intel_crtc_dpms_overlay(intel_crtc, true);
3377         intel_crtc_update_cursor(crtc, true);
3378 }
3379
3380 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3381 {
3382         struct drm_device *dev = crtc->dev;
3383         struct drm_i915_private *dev_priv = dev->dev_private;
3384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385         int pipe = intel_crtc->pipe;
3386         int plane = intel_crtc->plane;
3387
3388         if (!intel_crtc->active)
3389                 return;
3390
3391         /* Give the overlay scaler a chance to disable if it's on this pipe */
3392         intel_crtc_wait_for_pending_flips(crtc);
3393         drm_vblank_off(dev, pipe);
3394         intel_crtc_dpms_overlay(intel_crtc, false);
3395         intel_crtc_update_cursor(crtc, false);
3396
3397         if (dev_priv->cfb_plane == plane)
3398                 intel_disable_fbc(dev);
3399
3400         intel_disable_plane(dev_priv, plane, pipe);
3401         intel_disable_pipe(dev_priv, pipe);
3402         intel_disable_pll(dev_priv, pipe);
3403
3404         intel_crtc->active = false;
3405         intel_update_fbc(dev);
3406         intel_update_watermarks(dev);
3407 }
3408
3409 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3410 {
3411         /* XXX: When our outputs are all unaware of DPMS modes other than off
3412          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3413          */
3414         switch (mode) {
3415         case DRM_MODE_DPMS_ON:
3416         case DRM_MODE_DPMS_STANDBY:
3417         case DRM_MODE_DPMS_SUSPEND:
3418                 i9xx_crtc_enable(crtc);
3419                 break;
3420         case DRM_MODE_DPMS_OFF:
3421                 i9xx_crtc_disable(crtc);
3422                 break;
3423         }
3424 }
3425
3426 static void i9xx_crtc_off(struct drm_crtc *crtc)
3427 {
3428 }
3429
3430 /**
3431  * Sets the power management mode of the pipe and plane.
3432  */
3433 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3434 {
3435         struct drm_device *dev = crtc->dev;
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         struct drm_i915_master_private *master_priv;
3438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3439         int pipe = intel_crtc->pipe;
3440         bool enabled;
3441
3442         if (intel_crtc->dpms_mode == mode)
3443                 return;
3444
3445         intel_crtc->dpms_mode = mode;
3446
3447         dev_priv->display.dpms(crtc, mode);
3448
3449         if (!dev->primary->master)
3450                 return;
3451
3452         master_priv = dev->primary->master->driver_priv;
3453         if (!master_priv->sarea_priv)
3454                 return;
3455
3456         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3457
3458         switch (pipe) {
3459         case 0:
3460                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3461                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3462                 break;
3463         case 1:
3464                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3465                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3466                 break;
3467         default:
3468                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3469                 break;
3470         }
3471 }
3472
3473 static void intel_crtc_disable(struct drm_crtc *crtc)
3474 {
3475         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3476         struct drm_device *dev = crtc->dev;
3477         struct drm_i915_private *dev_priv = dev->dev_private;
3478
3479         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3480         dev_priv->display.off(crtc);
3481
3482         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3483         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3484
3485         if (crtc->fb) {
3486                 mutex_lock(&dev->struct_mutex);
3487                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3488                 mutex_unlock(&dev->struct_mutex);
3489         }
3490 }
3491
3492 /* Prepare for a mode set.
3493  *
3494  * Note we could be a lot smarter here.  We need to figure out which outputs
3495  * will be enabled, which disabled (in short, how the config will changes)
3496  * and perform the minimum necessary steps to accomplish that, e.g. updating
3497  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3498  * panel fitting is in the proper state, etc.
3499  */
3500 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3501 {
3502         i9xx_crtc_disable(crtc);
3503 }
3504
3505 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3506 {
3507         i9xx_crtc_enable(crtc);
3508 }
3509
3510 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3511 {
3512         ironlake_crtc_disable(crtc);
3513 }
3514
3515 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3516 {
3517         ironlake_crtc_enable(crtc);
3518 }
3519
3520 void intel_encoder_prepare(struct drm_encoder *encoder)
3521 {
3522         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3523         /* lvds has its own version of prepare see intel_lvds_prepare */
3524         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3525 }
3526
3527 void intel_encoder_commit(struct drm_encoder *encoder)
3528 {
3529         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3530         struct drm_device *dev = encoder->dev;
3531         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3532
3533         /* lvds has its own version of commit see intel_lvds_commit */
3534         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3535
3536         if (HAS_PCH_CPT(dev))
3537                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3538 }
3539
3540 void intel_encoder_destroy(struct drm_encoder *encoder)
3541 {
3542         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3543
3544         drm_encoder_cleanup(encoder);
3545         kfree(intel_encoder);
3546 }
3547
3548 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3549                                   struct drm_display_mode *mode,
3550                                   struct drm_display_mode *adjusted_mode)
3551 {
3552         struct drm_device *dev = crtc->dev;
3553
3554         if (HAS_PCH_SPLIT(dev)) {
3555                 /* FDI link clock is fixed at 2.7G */
3556                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3557                         return false;
3558         }
3559
3560         /* All interlaced capable intel hw wants timings in frames. Note though
3561          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3562          * timings, so we need to be careful not to clobber these.*/
3563         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3564                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3565
3566         return true;
3567 }
3568
3569 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3570 {
3571         return 400000; /* FIXME */
3572 }
3573
3574 static int i945_get_display_clock_speed(struct drm_device *dev)
3575 {
3576         return 400000;
3577 }
3578
3579 static int i915_get_display_clock_speed(struct drm_device *dev)
3580 {
3581         return 333000;
3582 }
3583
3584 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3585 {
3586         return 200000;
3587 }
3588
3589 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3590 {
3591         u16 gcfgc = 0;
3592
3593         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3594
3595         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3596                 return 133000;
3597         else {
3598                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3599                 case GC_DISPLAY_CLOCK_333_MHZ:
3600                         return 333000;
3601                 default:
3602                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3603                         return 190000;
3604                 }
3605         }
3606 }
3607
3608 static int i865_get_display_clock_speed(struct drm_device *dev)
3609 {
3610         return 266000;
3611 }
3612
3613 static int i855_get_display_clock_speed(struct drm_device *dev)
3614 {
3615         u16 hpllcc = 0;
3616         /* Assume that the hardware is in the high speed state.  This
3617          * should be the default.
3618          */
3619         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3620         case GC_CLOCK_133_200:
3621         case GC_CLOCK_100_200:
3622                 return 200000;
3623         case GC_CLOCK_166_250:
3624                 return 250000;
3625         case GC_CLOCK_100_133:
3626                 return 133000;
3627         }
3628
3629         /* Shouldn't happen */
3630         return 0;
3631 }
3632
3633 static int i830_get_display_clock_speed(struct drm_device *dev)
3634 {
3635         return 133000;
3636 }
3637
3638 struct fdi_m_n {
3639         u32        tu;
3640         u32        gmch_m;
3641         u32        gmch_n;
3642         u32        link_m;
3643         u32        link_n;
3644 };
3645
3646 static void
3647 fdi_reduce_ratio(u32 *num, u32 *den)
3648 {
3649         while (*num > 0xffffff || *den > 0xffffff) {
3650                 *num >>= 1;
3651                 *den >>= 1;
3652         }
3653 }
3654
3655 static void
3656 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3657                      int link_clock, struct fdi_m_n *m_n)
3658 {
3659         m_n->tu = 64; /* default size */
3660
3661         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3662         m_n->gmch_m = bits_per_pixel * pixel_clock;
3663         m_n->gmch_n = link_clock * nlanes * 8;
3664         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3665
3666         m_n->link_m = pixel_clock;
3667         m_n->link_n = link_clock;
3668         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3669 }
3670
3671 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3672 {
3673         if (i915_panel_use_ssc >= 0)
3674                 return i915_panel_use_ssc != 0;
3675         return dev_priv->lvds_use_ssc
3676                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3677 }
3678
3679 /**
3680  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3681  * @crtc: CRTC structure
3682  * @mode: requested mode
3683  *
3684  * A pipe may be connected to one or more outputs.  Based on the depth of the
3685  * attached framebuffer, choose a good color depth to use on the pipe.
3686  *
3687  * If possible, match the pipe depth to the fb depth.  In some cases, this
3688  * isn't ideal, because the connected output supports a lesser or restricted
3689  * set of depths.  Resolve that here:
3690  *    LVDS typically supports only 6bpc, so clamp down in that case
3691  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3692  *    Displays may support a restricted set as well, check EDID and clamp as
3693  *      appropriate.
3694  *    DP may want to dither down to 6bpc to fit larger modes
3695  *
3696  * RETURNS:
3697  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3698  * true if they don't match).
3699  */
3700 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3701                                          unsigned int *pipe_bpp,
3702                                          struct drm_display_mode *mode)
3703 {
3704         struct drm_device *dev = crtc->dev;
3705         struct drm_i915_private *dev_priv = dev->dev_private;
3706         struct drm_encoder *encoder;
3707         struct drm_connector *connector;
3708         unsigned int display_bpc = UINT_MAX, bpc;
3709
3710         /* Walk the encoders & connectors on this crtc, get min bpc */
3711         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3712                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3713
3714                 if (encoder->crtc != crtc)
3715                         continue;
3716
3717                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3718                         unsigned int lvds_bpc;
3719
3720                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3721                             LVDS_A3_POWER_UP)
3722                                 lvds_bpc = 8;
3723                         else
3724                                 lvds_bpc = 6;
3725
3726                         if (lvds_bpc < display_bpc) {
3727                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3728                                 display_bpc = lvds_bpc;
3729                         }
3730                         continue;
3731                 }
3732
3733                 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3734                         /* Use VBT settings if we have an eDP panel */
3735                         unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3736
3737                         if (edp_bpc < display_bpc) {
3738                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3739                                 display_bpc = edp_bpc;
3740                         }
3741                         continue;
3742                 }
3743
3744                 /* Not one of the known troublemakers, check the EDID */
3745                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3746                                     head) {
3747                         if (connector->encoder != encoder)
3748                                 continue;
3749
3750                         /* Don't use an invalid EDID bpc value */
3751                         if (connector->display_info.bpc &&
3752                             connector->display_info.bpc < display_bpc) {
3753                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3754                                 display_bpc = connector->display_info.bpc;
3755                         }
3756                 }
3757
3758                 /*
3759                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3760                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3761                  */
3762                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3763                         if (display_bpc > 8 && display_bpc < 12) {
3764                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3765                                 display_bpc = 12;
3766                         } else {
3767                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3768                                 display_bpc = 8;
3769                         }
3770                 }
3771         }
3772
3773         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3774                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3775                 display_bpc = 6;
3776         }
3777
3778         /*
3779          * We could just drive the pipe at the highest bpc all the time and
3780          * enable dithering as needed, but that costs bandwidth.  So choose
3781          * the minimum value that expresses the full color range of the fb but
3782          * also stays within the max display bpc discovered above.
3783          */
3784
3785         switch (crtc->fb->depth) {
3786         case 8:
3787                 bpc = 8; /* since we go through a colormap */
3788                 break;
3789         case 15:
3790         case 16:
3791                 bpc = 6; /* min is 18bpp */
3792                 break;
3793         case 24:
3794                 bpc = 8;
3795                 break;
3796         case 30:
3797                 bpc = 10;
3798                 break;
3799         case 48:
3800                 bpc = 12;
3801                 break;
3802         default:
3803                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3804                 bpc = min((unsigned int)8, display_bpc);
3805                 break;
3806         }
3807
3808         display_bpc = min(display_bpc, bpc);
3809
3810         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3811                       bpc, display_bpc);
3812
3813         *pipe_bpp = display_bpc * 3;
3814
3815         return display_bpc != bpc;
3816 }
3817
3818 static int vlv_get_refclk(struct drm_crtc *crtc)
3819 {
3820         struct drm_device *dev = crtc->dev;
3821         struct drm_i915_private *dev_priv = dev->dev_private;
3822         int refclk = 27000; /* for DP & HDMI */
3823
3824         return 100000; /* only one validated so far */
3825
3826         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3827                 refclk = 96000;
3828         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3829                 if (intel_panel_use_ssc(dev_priv))
3830                         refclk = 100000;
3831                 else
3832                         refclk = 96000;
3833         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3834                 refclk = 100000;
3835         }
3836
3837         return refclk;
3838 }
3839
3840 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3841 {
3842         struct drm_device *dev = crtc->dev;
3843         struct drm_i915_private *dev_priv = dev->dev_private;
3844         int refclk;
3845
3846         if (IS_VALLEYVIEW(dev)) {
3847                 refclk = vlv_get_refclk(crtc);
3848         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3849             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3850                 refclk = dev_priv->lvds_ssc_freq * 1000;
3851                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3852                               refclk / 1000);
3853         } else if (!IS_GEN2(dev)) {
3854                 refclk = 96000;
3855         } else {
3856                 refclk = 48000;
3857         }
3858
3859         return refclk;
3860 }
3861
3862 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3863                                       intel_clock_t *clock)
3864 {
3865         /* SDVO TV has fixed PLL values depend on its clock range,
3866            this mirrors vbios setting. */
3867         if (adjusted_mode->clock >= 100000
3868             && adjusted_mode->clock < 140500) {
3869                 clock->p1 = 2;
3870                 clock->p2 = 10;
3871                 clock->n = 3;
3872                 clock->m1 = 16;
3873                 clock->m2 = 8;
3874         } else if (adjusted_mode->clock >= 140500
3875                    && adjusted_mode->clock <= 200000) {
3876                 clock->p1 = 1;
3877                 clock->p2 = 10;
3878                 clock->n = 6;
3879                 clock->m1 = 12;
3880                 clock->m2 = 8;
3881         }
3882 }
3883
3884 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3885                                      intel_clock_t *clock,
3886                                      intel_clock_t *reduced_clock)
3887 {
3888         struct drm_device *dev = crtc->dev;
3889         struct drm_i915_private *dev_priv = dev->dev_private;
3890         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3891         int pipe = intel_crtc->pipe;
3892         u32 fp, fp2 = 0;
3893
3894         if (IS_PINEVIEW(dev)) {
3895                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3896                 if (reduced_clock)
3897                         fp2 = (1 << reduced_clock->n) << 16 |
3898                                 reduced_clock->m1 << 8 | reduced_clock->m2;
3899         } else {
3900                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3901                 if (reduced_clock)
3902                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3903                                 reduced_clock->m2;
3904         }
3905
3906         I915_WRITE(FP0(pipe), fp);
3907
3908         intel_crtc->lowfreq_avail = false;
3909         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3910             reduced_clock && i915_powersave) {
3911                 I915_WRITE(FP1(pipe), fp2);
3912                 intel_crtc->lowfreq_avail = true;
3913         } else {
3914                 I915_WRITE(FP1(pipe), fp);
3915         }
3916 }
3917
3918 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3919                               struct drm_display_mode *adjusted_mode)
3920 {
3921         struct drm_device *dev = crtc->dev;
3922         struct drm_i915_private *dev_priv = dev->dev_private;
3923         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3924         int pipe = intel_crtc->pipe;
3925         u32 temp;
3926
3927         temp = I915_READ(LVDS);
3928         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3929         if (pipe == 1) {
3930                 temp |= LVDS_PIPEB_SELECT;
3931         } else {
3932                 temp &= ~LVDS_PIPEB_SELECT;
3933         }
3934         /* set the corresponsding LVDS_BORDER bit */
3935         temp |= dev_priv->lvds_border_bits;
3936         /* Set the B0-B3 data pairs corresponding to whether we're going to
3937          * set the DPLLs for dual-channel mode or not.
3938          */
3939         if (clock->p2 == 7)
3940                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3941         else
3942                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3943
3944         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3945          * appropriately here, but we need to look more thoroughly into how
3946          * panels behave in the two modes.
3947          */
3948         /* set the dithering flag on LVDS as needed */
3949         if (INTEL_INFO(dev)->gen >= 4) {
3950                 if (dev_priv->lvds_dither)
3951                         temp |= LVDS_ENABLE_DITHER;
3952                 else
3953                         temp &= ~LVDS_ENABLE_DITHER;
3954         }
3955         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3956         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3957                 temp |= LVDS_HSYNC_POLARITY;
3958         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3959                 temp |= LVDS_VSYNC_POLARITY;
3960         I915_WRITE(LVDS, temp);
3961 }
3962
3963 static void vlv_update_pll(struct drm_crtc *crtc,
3964                            struct drm_display_mode *mode,
3965                            struct drm_display_mode *adjusted_mode,
3966                            intel_clock_t *clock, intel_clock_t *reduced_clock,
3967                            int refclk, int num_connectors)
3968 {
3969         struct drm_device *dev = crtc->dev;
3970         struct drm_i915_private *dev_priv = dev->dev_private;
3971         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3972         int pipe = intel_crtc->pipe;
3973         u32 dpll, mdiv, pdiv;
3974         u32 bestn, bestm1, bestm2, bestp1, bestp2;
3975         bool is_hdmi;
3976
3977         is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3978
3979         bestn = clock->n;
3980         bestm1 = clock->m1;
3981         bestm2 = clock->m2;
3982         bestp1 = clock->p1;
3983         bestp2 = clock->p2;
3984
3985         /* Enable DPIO clock input */
3986         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
3987                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
3988         I915_WRITE(DPLL(pipe), dpll);
3989         POSTING_READ(DPLL(pipe));
3990
3991         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
3992         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
3993         mdiv |= ((bestn << DPIO_N_SHIFT));
3994         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
3995         mdiv |= (1 << DPIO_K_SHIFT);
3996         mdiv |= DPIO_ENABLE_CALIBRATION;
3997         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
3998
3999         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4000
4001         pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4002                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4003                 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4004         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4005
4006         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4007
4008         dpll |= DPLL_VCO_ENABLE;
4009         I915_WRITE(DPLL(pipe), dpll);
4010         POSTING_READ(DPLL(pipe));
4011         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4012                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4013
4014         if (is_hdmi) {
4015                 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4016
4017                 if (temp > 1)
4018                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4019                 else
4020                         temp = 0;
4021
4022                 I915_WRITE(DPLL_MD(pipe), temp);
4023                 POSTING_READ(DPLL_MD(pipe));
4024         }
4025
4026         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4027 }
4028
4029 static void i9xx_update_pll(struct drm_crtc *crtc,
4030                             struct drm_display_mode *mode,
4031                             struct drm_display_mode *adjusted_mode,
4032                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4033                             int num_connectors)
4034 {
4035         struct drm_device *dev = crtc->dev;
4036         struct drm_i915_private *dev_priv = dev->dev_private;
4037         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4038         int pipe = intel_crtc->pipe;
4039         u32 dpll;
4040         bool is_sdvo;
4041
4042         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4043                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4044
4045         dpll = DPLL_VGA_MODE_DIS;
4046
4047         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4048                 dpll |= DPLLB_MODE_LVDS;
4049         else
4050                 dpll |= DPLLB_MODE_DAC_SERIAL;
4051         if (is_sdvo) {
4052                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4053                 if (pixel_multiplier > 1) {
4054                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4055                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4056                 }
4057                 dpll |= DPLL_DVO_HIGH_SPEED;
4058         }
4059         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4060                 dpll |= DPLL_DVO_HIGH_SPEED;
4061
4062         /* compute bitmask from p1 value */
4063         if (IS_PINEVIEW(dev))
4064                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4065         else {
4066                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4067                 if (IS_G4X(dev) && reduced_clock)
4068                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4069         }
4070         switch (clock->p2) {
4071         case 5:
4072                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4073                 break;
4074         case 7:
4075                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4076                 break;
4077         case 10:
4078                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4079                 break;
4080         case 14:
4081                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4082                 break;
4083         }
4084         if (INTEL_INFO(dev)->gen >= 4)
4085                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4086
4087         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4088                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4089         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4090                 /* XXX: just matching BIOS for now */
4091                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4092                 dpll |= 3;
4093         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4094                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4095                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4096         else
4097                 dpll |= PLL_REF_INPUT_DREFCLK;
4098
4099         dpll |= DPLL_VCO_ENABLE;
4100         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4101         POSTING_READ(DPLL(pipe));
4102         udelay(150);
4103
4104         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4105          * This is an exception to the general rule that mode_set doesn't turn
4106          * things on.
4107          */
4108         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4109                 intel_update_lvds(crtc, clock, adjusted_mode);
4110
4111         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4112                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4113
4114         I915_WRITE(DPLL(pipe), dpll);
4115
4116         /* Wait for the clocks to stabilize. */
4117         POSTING_READ(DPLL(pipe));
4118         udelay(150);
4119
4120         if (INTEL_INFO(dev)->gen >= 4) {
4121                 u32 temp = 0;
4122                 if (is_sdvo) {
4123                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4124                         if (temp > 1)
4125                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4126                         else
4127                                 temp = 0;
4128                 }
4129                 I915_WRITE(DPLL_MD(pipe), temp);
4130         } else {
4131                 /* The pixel multiplier can only be updated once the
4132                  * DPLL is enabled and the clocks are stable.
4133                  *
4134                  * So write it again.
4135                  */
4136                 I915_WRITE(DPLL(pipe), dpll);
4137         }
4138 }
4139
4140 static void i8xx_update_pll(struct drm_crtc *crtc,
4141                             struct drm_display_mode *adjusted_mode,
4142                             intel_clock_t *clock,
4143                             int num_connectors)
4144 {
4145         struct drm_device *dev = crtc->dev;
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4148         int pipe = intel_crtc->pipe;
4149         u32 dpll;
4150
4151         dpll = DPLL_VGA_MODE_DIS;
4152
4153         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4154                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4155         } else {
4156                 if (clock->p1 == 2)
4157                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4158                 else
4159                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4160                 if (clock->p2 == 4)
4161                         dpll |= PLL_P2_DIVIDE_BY_4;
4162         }
4163
4164         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4165                 /* XXX: just matching BIOS for now */
4166                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4167                 dpll |= 3;
4168         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4169                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4170                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4171         else
4172                 dpll |= PLL_REF_INPUT_DREFCLK;
4173
4174         dpll |= DPLL_VCO_ENABLE;
4175         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4176         POSTING_READ(DPLL(pipe));
4177         udelay(150);
4178
4179         I915_WRITE(DPLL(pipe), dpll);
4180
4181         /* Wait for the clocks to stabilize. */
4182         POSTING_READ(DPLL(pipe));
4183         udelay(150);
4184
4185         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4186          * This is an exception to the general rule that mode_set doesn't turn
4187          * things on.
4188          */
4189         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4190                 intel_update_lvds(crtc, clock, adjusted_mode);
4191
4192         /* The pixel multiplier can only be updated once the
4193          * DPLL is enabled and the clocks are stable.
4194          *
4195          * So write it again.
4196          */
4197         I915_WRITE(DPLL(pipe), dpll);
4198 }
4199
4200 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4201                               struct drm_display_mode *mode,
4202                               struct drm_display_mode *adjusted_mode,
4203                               int x, int y,
4204                               struct drm_framebuffer *old_fb)
4205 {
4206         struct drm_device *dev = crtc->dev;
4207         struct drm_i915_private *dev_priv = dev->dev_private;
4208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209         int pipe = intel_crtc->pipe;
4210         int plane = intel_crtc->plane;
4211         int refclk, num_connectors = 0;
4212         intel_clock_t clock, reduced_clock;
4213         u32 dspcntr, pipeconf, vsyncshift;
4214         bool ok, has_reduced_clock = false, is_sdvo = false;
4215         bool is_lvds = false, is_tv = false, is_dp = false;
4216         struct drm_mode_config *mode_config = &dev->mode_config;
4217         struct intel_encoder *encoder;
4218         const intel_limit_t *limit;
4219         int ret;
4220
4221         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4222                 if (encoder->base.crtc != crtc)
4223                         continue;
4224
4225                 switch (encoder->type) {
4226                 case INTEL_OUTPUT_LVDS:
4227                         is_lvds = true;
4228                         break;
4229                 case INTEL_OUTPUT_SDVO:
4230                 case INTEL_OUTPUT_HDMI:
4231                         is_sdvo = true;
4232                         if (encoder->needs_tv_clock)
4233                                 is_tv = true;
4234                         break;
4235                 case INTEL_OUTPUT_TVOUT:
4236                         is_tv = true;
4237                         break;
4238                 case INTEL_OUTPUT_DISPLAYPORT:
4239                         is_dp = true;
4240                         break;
4241                 }
4242
4243                 num_connectors++;
4244         }
4245
4246         refclk = i9xx_get_refclk(crtc, num_connectors);
4247
4248         /*
4249          * Returns a set of divisors for the desired target clock with the given
4250          * refclk, or FALSE.  The returned values represent the clock equation:
4251          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4252          */
4253         limit = intel_limit(crtc, refclk);
4254         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4255                              &clock);
4256         if (!ok) {
4257                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4258                 return -EINVAL;
4259         }
4260
4261         /* Ensure that the cursor is valid for the new mode before changing... */
4262         intel_crtc_update_cursor(crtc, true);
4263
4264         if (is_lvds && dev_priv->lvds_downclock_avail) {
4265                 /*
4266                  * Ensure we match the reduced clock's P to the target clock.
4267                  * If the clocks don't match, we can't switch the display clock
4268                  * by using the FP0/FP1. In such case we will disable the LVDS
4269                  * downclock feature.
4270                 */
4271                 has_reduced_clock = limit->find_pll(limit, crtc,
4272                                                     dev_priv->lvds_downclock,
4273                                                     refclk,
4274                                                     &clock,
4275                                                     &reduced_clock);
4276         }
4277
4278         if (is_sdvo && is_tv)
4279                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4280
4281         i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4282                                  &reduced_clock : NULL);
4283
4284         if (IS_GEN2(dev))
4285                 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4286         else if (IS_VALLEYVIEW(dev))
4287                 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4288                                refclk, num_connectors);
4289         else
4290                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4291                                 has_reduced_clock ? &reduced_clock : NULL,
4292                                 num_connectors);
4293
4294         /* setup pipeconf */
4295         pipeconf = I915_READ(PIPECONF(pipe));
4296
4297         /* Set up the display plane register */
4298         dspcntr = DISPPLANE_GAMMA_ENABLE;
4299
4300         if (pipe == 0)
4301                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4302         else
4303                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4304
4305         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4306                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4307                  * core speed.
4308                  *
4309                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4310                  * pipe == 0 check?
4311                  */
4312                 if (mode->clock >
4313                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4314                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4315                 else
4316                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4317         }
4318
4319         /* default to 8bpc */
4320         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4321         if (is_dp) {
4322                 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4323                         pipeconf |= PIPECONF_BPP_6 |
4324                                     PIPECONF_DITHER_EN |
4325                                     PIPECONF_DITHER_TYPE_SP;
4326                 }
4327         }
4328
4329         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4330         drm_mode_debug_printmodeline(mode);
4331
4332         if (HAS_PIPE_CXSR(dev)) {
4333                 if (intel_crtc->lowfreq_avail) {
4334                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4335                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4336                 } else {
4337                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4338                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4339                 }
4340         }
4341
4342         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4343         if (!IS_GEN2(dev) &&
4344             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4345                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4346                 /* the chip adds 2 halflines automatically */
4347                 adjusted_mode->crtc_vtotal -= 1;
4348                 adjusted_mode->crtc_vblank_end -= 1;
4349                 vsyncshift = adjusted_mode->crtc_hsync_start
4350                              - adjusted_mode->crtc_htotal/2;
4351         } else {
4352                 pipeconf |= PIPECONF_PROGRESSIVE;
4353                 vsyncshift = 0;
4354         }
4355
4356         if (!IS_GEN3(dev))
4357                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4358
4359         I915_WRITE(HTOTAL(pipe),
4360                    (adjusted_mode->crtc_hdisplay - 1) |
4361                    ((adjusted_mode->crtc_htotal - 1) << 16));
4362         I915_WRITE(HBLANK(pipe),
4363                    (adjusted_mode->crtc_hblank_start - 1) |
4364                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4365         I915_WRITE(HSYNC(pipe),
4366                    (adjusted_mode->crtc_hsync_start - 1) |
4367                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4368
4369         I915_WRITE(VTOTAL(pipe),
4370                    (adjusted_mode->crtc_vdisplay - 1) |
4371                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4372         I915_WRITE(VBLANK(pipe),
4373                    (adjusted_mode->crtc_vblank_start - 1) |
4374                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4375         I915_WRITE(VSYNC(pipe),
4376                    (adjusted_mode->crtc_vsync_start - 1) |
4377                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4378
4379         /* pipesrc and dspsize control the size that is scaled from,
4380          * which should always be the user's requested size.
4381          */
4382         I915_WRITE(DSPSIZE(plane),
4383                    ((mode->vdisplay - 1) << 16) |
4384                    (mode->hdisplay - 1));
4385         I915_WRITE(DSPPOS(plane), 0);
4386         I915_WRITE(PIPESRC(pipe),
4387                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4388
4389         I915_WRITE(PIPECONF(pipe), pipeconf);
4390         POSTING_READ(PIPECONF(pipe));
4391         intel_enable_pipe(dev_priv, pipe, false);
4392
4393         intel_wait_for_vblank(dev, pipe);
4394
4395         I915_WRITE(DSPCNTR(plane), dspcntr);
4396         POSTING_READ(DSPCNTR(plane));
4397
4398         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4399
4400         intel_update_watermarks(dev);
4401
4402         return ret;
4403 }
4404
4405 /*
4406  * Initialize reference clocks when the driver loads
4407  */
4408 void ironlake_init_pch_refclk(struct drm_device *dev)
4409 {
4410         struct drm_i915_private *dev_priv = dev->dev_private;
4411         struct drm_mode_config *mode_config = &dev->mode_config;
4412         struct intel_encoder *encoder;
4413         u32 temp;
4414         bool has_lvds = false;
4415         bool has_cpu_edp = false;
4416         bool has_pch_edp = false;
4417         bool has_panel = false;
4418         bool has_ck505 = false;
4419         bool can_ssc = false;
4420
4421         /* We need to take the global config into account */
4422         list_for_each_entry(encoder, &mode_config->encoder_list,
4423                             base.head) {
4424                 switch (encoder->type) {
4425                 case INTEL_OUTPUT_LVDS:
4426                         has_panel = true;
4427                         has_lvds = true;
4428                         break;
4429                 case INTEL_OUTPUT_EDP:
4430                         has_panel = true;
4431                         if (intel_encoder_is_pch_edp(&encoder->base))
4432                                 has_pch_edp = true;
4433                         else
4434                                 has_cpu_edp = true;
4435                         break;
4436                 }
4437         }
4438
4439         if (HAS_PCH_IBX(dev)) {
4440                 has_ck505 = dev_priv->display_clock_mode;
4441                 can_ssc = has_ck505;
4442         } else {
4443                 has_ck505 = false;
4444                 can_ssc = true;
4445         }
4446
4447         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4448                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4449                       has_ck505);
4450
4451         /* Ironlake: try to setup display ref clock before DPLL
4452          * enabling. This is only under driver's control after
4453          * PCH B stepping, previous chipset stepping should be
4454          * ignoring this setting.
4455          */
4456         temp = I915_READ(PCH_DREF_CONTROL);
4457         /* Always enable nonspread source */
4458         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4459
4460         if (has_ck505)
4461                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4462         else
4463                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4464
4465         if (has_panel) {
4466                 temp &= ~DREF_SSC_SOURCE_MASK;
4467                 temp |= DREF_SSC_SOURCE_ENABLE;
4468
4469                 /* SSC must be turned on before enabling the CPU output  */
4470                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4471                         DRM_DEBUG_KMS("Using SSC on panel\n");
4472                         temp |= DREF_SSC1_ENABLE;
4473                 } else
4474                         temp &= ~DREF_SSC1_ENABLE;
4475
4476                 /* Get SSC going before enabling the outputs */
4477                 I915_WRITE(PCH_DREF_CONTROL, temp);
4478                 POSTING_READ(PCH_DREF_CONTROL);
4479                 udelay(200);
4480
4481                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4482
4483                 /* Enable CPU source on CPU attached eDP */
4484                 if (has_cpu_edp) {
4485                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4486                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4487                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4488                         }
4489                         else
4490                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4491                 } else
4492                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4493
4494                 I915_WRITE(PCH_DREF_CONTROL, temp);
4495                 POSTING_READ(PCH_DREF_CONTROL);
4496                 udelay(200);
4497         } else {
4498                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4499
4500                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4501
4502                 /* Turn off CPU output */
4503                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4504
4505                 I915_WRITE(PCH_DREF_CONTROL, temp);
4506                 POSTING_READ(PCH_DREF_CONTROL);
4507                 udelay(200);
4508
4509                 /* Turn off the SSC source */
4510                 temp &= ~DREF_SSC_SOURCE_MASK;
4511                 temp |= DREF_SSC_SOURCE_DISABLE;
4512
4513                 /* Turn off SSC1 */
4514                 temp &= ~ DREF_SSC1_ENABLE;
4515
4516                 I915_WRITE(PCH_DREF_CONTROL, temp);
4517                 POSTING_READ(PCH_DREF_CONTROL);
4518                 udelay(200);
4519         }
4520 }
4521
4522 static int ironlake_get_refclk(struct drm_crtc *crtc)
4523 {
4524         struct drm_device *dev = crtc->dev;
4525         struct drm_i915_private *dev_priv = dev->dev_private;
4526         struct intel_encoder *encoder;
4527         struct drm_mode_config *mode_config = &dev->mode_config;
4528         struct intel_encoder *edp_encoder = NULL;
4529         int num_connectors = 0;
4530         bool is_lvds = false;
4531
4532         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4533                 if (encoder->base.crtc != crtc)
4534                         continue;
4535
4536                 switch (encoder->type) {
4537                 case INTEL_OUTPUT_LVDS:
4538                         is_lvds = true;
4539                         break;
4540                 case INTEL_OUTPUT_EDP:
4541                         edp_encoder = encoder;
4542                         break;
4543                 }
4544                 num_connectors++;
4545         }
4546
4547         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4548                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4549                               dev_priv->lvds_ssc_freq);
4550                 return dev_priv->lvds_ssc_freq * 1000;
4551         }
4552
4553         return 120000;
4554 }
4555
4556 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4557                                   struct drm_display_mode *mode,
4558                                   struct drm_display_mode *adjusted_mode,
4559                                   int x, int y,
4560                                   struct drm_framebuffer *old_fb)
4561 {
4562         struct drm_device *dev = crtc->dev;
4563         struct drm_i915_private *dev_priv = dev->dev_private;
4564         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565         int pipe = intel_crtc->pipe;
4566         int plane = intel_crtc->plane;
4567         int refclk, num_connectors = 0;
4568         intel_clock_t clock, reduced_clock;
4569         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4570         bool ok, has_reduced_clock = false, is_sdvo = false;
4571         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4572         struct drm_mode_config *mode_config = &dev->mode_config;
4573         struct intel_encoder *encoder, *edp_encoder = NULL;
4574         const intel_limit_t *limit;
4575         int ret;
4576         struct fdi_m_n m_n = {0};
4577         u32 temp;
4578         int target_clock, pixel_multiplier, lane, link_bw, factor;
4579         unsigned int pipe_bpp;
4580         bool dither;
4581         bool is_cpu_edp = false, is_pch_edp = false;
4582
4583         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4584                 if (encoder->base.crtc != crtc)
4585                         continue;
4586
4587                 switch (encoder->type) {
4588                 case INTEL_OUTPUT_LVDS:
4589                         is_lvds = true;
4590                         break;
4591                 case INTEL_OUTPUT_SDVO:
4592                 case INTEL_OUTPUT_HDMI:
4593                         is_sdvo = true;
4594                         if (encoder->needs_tv_clock)
4595                                 is_tv = true;
4596                         break;
4597                 case INTEL_OUTPUT_TVOUT:
4598                         is_tv = true;
4599                         break;
4600                 case INTEL_OUTPUT_ANALOG:
4601                         is_crt = true;
4602                         break;
4603                 case INTEL_OUTPUT_DISPLAYPORT:
4604                         is_dp = true;
4605                         break;
4606                 case INTEL_OUTPUT_EDP:
4607                         is_dp = true;
4608                         if (intel_encoder_is_pch_edp(&encoder->base))
4609                                 is_pch_edp = true;
4610                         else
4611                                 is_cpu_edp = true;
4612                         edp_encoder = encoder;
4613                         break;
4614                 }
4615
4616                 num_connectors++;
4617         }
4618
4619         refclk = ironlake_get_refclk(crtc);
4620
4621         /*
4622          * Returns a set of divisors for the desired target clock with the given
4623          * refclk, or FALSE.  The returned values represent the clock equation:
4624          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4625          */
4626         limit = intel_limit(crtc, refclk);
4627         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4628                              &clock);
4629         if (!ok) {
4630                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4631                 return -EINVAL;
4632         }
4633
4634         /* Ensure that the cursor is valid for the new mode before changing... */
4635         intel_crtc_update_cursor(crtc, true);
4636
4637         if (is_lvds && dev_priv->lvds_downclock_avail) {
4638                 /*
4639                  * Ensure we match the reduced clock's P to the target clock.
4640                  * If the clocks don't match, we can't switch the display clock
4641                  * by using the FP0/FP1. In such case we will disable the LVDS
4642                  * downclock feature.
4643                 */
4644                 has_reduced_clock = limit->find_pll(limit, crtc,
4645                                                     dev_priv->lvds_downclock,
4646                                                     refclk,
4647                                                     &clock,
4648                                                     &reduced_clock);
4649         }
4650
4651         if (is_sdvo && is_tv)
4652                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4653
4654
4655         /* FDI link */
4656         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4657         lane = 0;
4658         /* CPU eDP doesn't require FDI link, so just set DP M/N
4659            according to current link config */
4660         if (is_cpu_edp) {
4661                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4662         } else {
4663                 /* FDI is a binary signal running at ~2.7GHz, encoding
4664                  * each output octet as 10 bits. The actual frequency
4665                  * is stored as a divider into a 100MHz clock, and the
4666                  * mode pixel clock is stored in units of 1KHz.
4667                  * Hence the bw of each lane in terms of the mode signal
4668                  * is:
4669                  */
4670                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4671         }
4672
4673         /* [e]DP over FDI requires target mode clock instead of link clock. */
4674         if (edp_encoder)
4675                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4676         else if (is_dp)
4677                 target_clock = mode->clock;
4678         else
4679                 target_clock = adjusted_mode->clock;
4680
4681         /* determine panel color depth */
4682         temp = I915_READ(PIPECONF(pipe));
4683         temp &= ~PIPE_BPC_MASK;
4684         dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4685         switch (pipe_bpp) {
4686         case 18:
4687                 temp |= PIPE_6BPC;
4688                 break;
4689         case 24:
4690                 temp |= PIPE_8BPC;
4691                 break;
4692         case 30:
4693                 temp |= PIPE_10BPC;
4694                 break;
4695         case 36:
4696                 temp |= PIPE_12BPC;
4697                 break;
4698         default:
4699                 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4700                         pipe_bpp);
4701                 temp |= PIPE_8BPC;
4702                 pipe_bpp = 24;
4703                 break;
4704         }
4705
4706         intel_crtc->bpp = pipe_bpp;
4707         I915_WRITE(PIPECONF(pipe), temp);
4708
4709         if (!lane) {
4710                 /*
4711                  * Account for spread spectrum to avoid
4712                  * oversubscribing the link. Max center spread
4713                  * is 2.5%; use 5% for safety's sake.
4714                  */
4715                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4716                 lane = bps / (link_bw * 8) + 1;
4717         }
4718
4719         intel_crtc->fdi_lanes = lane;
4720
4721         if (pixel_multiplier > 1)
4722                 link_bw *= pixel_multiplier;
4723         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4724                              &m_n);
4725
4726         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4727         if (has_reduced_clock)
4728                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4729                         reduced_clock.m2;
4730
4731         /* Enable autotuning of the PLL clock (if permissible) */
4732         factor = 21;
4733         if (is_lvds) {
4734                 if ((intel_panel_use_ssc(dev_priv) &&
4735                      dev_priv->lvds_ssc_freq == 100) ||
4736                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4737                         factor = 25;
4738         } else if (is_sdvo && is_tv)
4739                 factor = 20;
4740
4741         if (clock.m < factor * clock.n)
4742                 fp |= FP_CB_TUNE;
4743
4744         dpll = 0;
4745
4746         if (is_lvds)
4747                 dpll |= DPLLB_MODE_LVDS;
4748         else
4749                 dpll |= DPLLB_MODE_DAC_SERIAL;
4750         if (is_sdvo) {
4751                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4752                 if (pixel_multiplier > 1) {
4753                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4754                 }
4755                 dpll |= DPLL_DVO_HIGH_SPEED;
4756         }
4757         if (is_dp && !is_cpu_edp)
4758                 dpll |= DPLL_DVO_HIGH_SPEED;
4759
4760         /* compute bitmask from p1 value */
4761         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4762         /* also FPA1 */
4763         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4764
4765         switch (clock.p2) {
4766         case 5:
4767                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4768                 break;
4769         case 7:
4770                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4771                 break;
4772         case 10:
4773                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4774                 break;
4775         case 14:
4776                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4777                 break;
4778         }
4779
4780         if (is_sdvo && is_tv)
4781                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4782         else if (is_tv)
4783                 /* XXX: just matching BIOS for now */
4784                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4785                 dpll |= 3;
4786         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4787                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4788         else
4789                 dpll |= PLL_REF_INPUT_DREFCLK;
4790
4791         /* setup pipeconf */
4792         pipeconf = I915_READ(PIPECONF(pipe));
4793
4794         /* Set up the display plane register */
4795         dspcntr = DISPPLANE_GAMMA_ENABLE;
4796
4797         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4798         drm_mode_debug_printmodeline(mode);
4799
4800         /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4801          * pre-Haswell/LPT generation */
4802         if (HAS_PCH_LPT(dev)) {
4803                 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4804                                 pipe);
4805         } else if (!is_cpu_edp) {
4806                 struct intel_pch_pll *pll;
4807
4808                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4809                 if (pll == NULL) {
4810                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4811                                          pipe);
4812                         return -EINVAL;
4813                 }
4814         } else
4815                 intel_put_pch_pll(intel_crtc);
4816
4817         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4818          * This is an exception to the general rule that mode_set doesn't turn
4819          * things on.
4820          */
4821         if (is_lvds) {
4822                 temp = I915_READ(PCH_LVDS);
4823                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4824                 if (HAS_PCH_CPT(dev)) {
4825                         temp &= ~PORT_TRANS_SEL_MASK;
4826                         temp |= PORT_TRANS_SEL_CPT(pipe);
4827                 } else {
4828                         if (pipe == 1)
4829                                 temp |= LVDS_PIPEB_SELECT;
4830                         else
4831                                 temp &= ~LVDS_PIPEB_SELECT;
4832                 }
4833
4834                 /* set the corresponsding LVDS_BORDER bit */
4835                 temp |= dev_priv->lvds_border_bits;
4836                 /* Set the B0-B3 data pairs corresponding to whether we're going to
4837                  * set the DPLLs for dual-channel mode or not.
4838                  */
4839                 if (clock.p2 == 7)
4840                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4841                 else
4842                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4843
4844                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4845                  * appropriately here, but we need to look more thoroughly into how
4846                  * panels behave in the two modes.
4847                  */
4848                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4849                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4850                         temp |= LVDS_HSYNC_POLARITY;
4851                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4852                         temp |= LVDS_VSYNC_POLARITY;
4853                 I915_WRITE(PCH_LVDS, temp);
4854         }
4855
4856         pipeconf &= ~PIPECONF_DITHER_EN;
4857         pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4858         if ((is_lvds && dev_priv->lvds_dither) || dither) {
4859                 pipeconf |= PIPECONF_DITHER_EN;
4860                 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4861         }
4862         if (is_dp && !is_cpu_edp) {
4863                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4864         } else {
4865                 /* For non-DP output, clear any trans DP clock recovery setting.*/
4866                 I915_WRITE(TRANSDATA_M1(pipe), 0);
4867                 I915_WRITE(TRANSDATA_N1(pipe), 0);
4868                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4869                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4870         }
4871
4872         if (intel_crtc->pch_pll) {
4873                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4874
4875                 /* Wait for the clocks to stabilize. */
4876                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4877                 udelay(150);
4878
4879                 /* The pixel multiplier can only be updated once the
4880                  * DPLL is enabled and the clocks are stable.
4881                  *
4882                  * So write it again.
4883                  */
4884                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4885         }
4886
4887         intel_crtc->lowfreq_avail = false;
4888         if (intel_crtc->pch_pll) {
4889                 if (is_lvds && has_reduced_clock && i915_powersave) {
4890                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4891                         intel_crtc->lowfreq_avail = true;
4892                 } else {
4893                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4894                 }
4895         }
4896
4897         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4898         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4899                 pipeconf |= PIPECONF_INTERLACED_ILK;
4900                 /* the chip adds 2 halflines automatically */
4901                 adjusted_mode->crtc_vtotal -= 1;
4902                 adjusted_mode->crtc_vblank_end -= 1;
4903                 I915_WRITE(VSYNCSHIFT(pipe),
4904                            adjusted_mode->crtc_hsync_start
4905                            - adjusted_mode->crtc_htotal/2);
4906         } else {
4907                 pipeconf |= PIPECONF_PROGRESSIVE;
4908                 I915_WRITE(VSYNCSHIFT(pipe), 0);
4909         }
4910
4911         I915_WRITE(HTOTAL(pipe),
4912                    (adjusted_mode->crtc_hdisplay - 1) |
4913                    ((adjusted_mode->crtc_htotal - 1) << 16));
4914         I915_WRITE(HBLANK(pipe),
4915                    (adjusted_mode->crtc_hblank_start - 1) |
4916                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4917         I915_WRITE(HSYNC(pipe),
4918                    (adjusted_mode->crtc_hsync_start - 1) |
4919                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4920
4921         I915_WRITE(VTOTAL(pipe),
4922                    (adjusted_mode->crtc_vdisplay - 1) |
4923                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4924         I915_WRITE(VBLANK(pipe),
4925                    (adjusted_mode->crtc_vblank_start - 1) |
4926                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4927         I915_WRITE(VSYNC(pipe),
4928                    (adjusted_mode->crtc_vsync_start - 1) |
4929                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4930
4931         /* pipesrc controls the size that is scaled from, which should
4932          * always be the user's requested size.
4933          */
4934         I915_WRITE(PIPESRC(pipe),
4935                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4936
4937         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4938         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4939         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4940         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4941
4942         if (is_cpu_edp)
4943                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4944
4945         I915_WRITE(PIPECONF(pipe), pipeconf);
4946         POSTING_READ(PIPECONF(pipe));
4947
4948         intel_wait_for_vblank(dev, pipe);
4949
4950         I915_WRITE(DSPCNTR(plane), dspcntr);
4951         POSTING_READ(DSPCNTR(plane));
4952
4953         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4954
4955         intel_update_watermarks(dev);
4956
4957         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4958
4959         return ret;
4960 }
4961
4962 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4963                                struct drm_display_mode *mode,
4964                                struct drm_display_mode *adjusted_mode,
4965                                int x, int y,
4966                                struct drm_framebuffer *old_fb)
4967 {
4968         struct drm_device *dev = crtc->dev;
4969         struct drm_i915_private *dev_priv = dev->dev_private;
4970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4971         int pipe = intel_crtc->pipe;
4972         int ret;
4973
4974         drm_vblank_pre_modeset(dev, pipe);
4975
4976         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4977                                               x, y, old_fb);
4978         drm_vblank_post_modeset(dev, pipe);
4979
4980         if (ret)
4981                 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4982         else
4983                 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4984
4985         return ret;
4986 }
4987
4988 static bool intel_eld_uptodate(struct drm_connector *connector,
4989                                int reg_eldv, uint32_t bits_eldv,
4990                                int reg_elda, uint32_t bits_elda,
4991                                int reg_edid)
4992 {
4993         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4994         uint8_t *eld = connector->eld;
4995         uint32_t i;
4996
4997         i = I915_READ(reg_eldv);
4998         i &= bits_eldv;
4999
5000         if (!eld[0])
5001                 return !i;
5002
5003         if (!i)
5004                 return false;
5005
5006         i = I915_READ(reg_elda);
5007         i &= ~bits_elda;
5008         I915_WRITE(reg_elda, i);
5009
5010         for (i = 0; i < eld[2]; i++)
5011                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5012                         return false;
5013
5014         return true;
5015 }
5016
5017 static void g4x_write_eld(struct drm_connector *connector,
5018                           struct drm_crtc *crtc)
5019 {
5020         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5021         uint8_t *eld = connector->eld;
5022         uint32_t eldv;
5023         uint32_t len;
5024         uint32_t i;
5025
5026         i = I915_READ(G4X_AUD_VID_DID);
5027
5028         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5029                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5030         else
5031                 eldv = G4X_ELDV_DEVCTG;
5032
5033         if (intel_eld_uptodate(connector,
5034                                G4X_AUD_CNTL_ST, eldv,
5035                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5036                                G4X_HDMIW_HDMIEDID))
5037                 return;
5038
5039         i = I915_READ(G4X_AUD_CNTL_ST);
5040         i &= ~(eldv | G4X_ELD_ADDR);
5041         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5042         I915_WRITE(G4X_AUD_CNTL_ST, i);
5043
5044         if (!eld[0])
5045                 return;
5046
5047         len = min_t(uint8_t, eld[2], len);
5048         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5049         for (i = 0; i < len; i++)
5050                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5051
5052         i = I915_READ(G4X_AUD_CNTL_ST);
5053         i |= eldv;
5054         I915_WRITE(G4X_AUD_CNTL_ST, i);
5055 }
5056
5057 static void ironlake_write_eld(struct drm_connector *connector,
5058                                      struct drm_crtc *crtc)
5059 {
5060         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5061         uint8_t *eld = connector->eld;
5062         uint32_t eldv;
5063         uint32_t i;
5064         int len;
5065         int hdmiw_hdmiedid;
5066         int aud_config;
5067         int aud_cntl_st;
5068         int aud_cntrl_st2;
5069
5070         if (HAS_PCH_IBX(connector->dev)) {
5071                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
5072                 aud_config = IBX_AUD_CONFIG_A;
5073                 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5074                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5075         } else {
5076                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
5077                 aud_config = CPT_AUD_CONFIG_A;
5078                 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5079                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5080         }
5081
5082         i = to_intel_crtc(crtc)->pipe;
5083         hdmiw_hdmiedid += i * 0x100;
5084         aud_cntl_st += i * 0x100;
5085         aud_config += i * 0x100;
5086
5087         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5088
5089         i = I915_READ(aud_cntl_st);
5090         i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
5091         if (!i) {
5092                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5093                 /* operate blindly on all ports */
5094                 eldv = IBX_ELD_VALIDB;
5095                 eldv |= IBX_ELD_VALIDB << 4;
5096                 eldv |= IBX_ELD_VALIDB << 8;
5097         } else {
5098                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5099                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5100         }
5101
5102         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5103                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5104                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5105                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5106         } else
5107                 I915_WRITE(aud_config, 0);
5108
5109         if (intel_eld_uptodate(connector,
5110                                aud_cntrl_st2, eldv,
5111                                aud_cntl_st, IBX_ELD_ADDRESS,
5112                                hdmiw_hdmiedid))
5113                 return;
5114
5115         i = I915_READ(aud_cntrl_st2);
5116         i &= ~eldv;
5117         I915_WRITE(aud_cntrl_st2, i);
5118
5119         if (!eld[0])
5120                 return;
5121
5122         i = I915_READ(aud_cntl_st);
5123         i &= ~IBX_ELD_ADDRESS;
5124         I915_WRITE(aud_cntl_st, i);
5125
5126         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5127         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5128         for (i = 0; i < len; i++)
5129                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5130
5131         i = I915_READ(aud_cntrl_st2);
5132         i |= eldv;
5133         I915_WRITE(aud_cntrl_st2, i);
5134 }
5135
5136 void intel_write_eld(struct drm_encoder *encoder,
5137                      struct drm_display_mode *mode)
5138 {
5139         struct drm_crtc *crtc = encoder->crtc;
5140         struct drm_connector *connector;
5141         struct drm_device *dev = encoder->dev;
5142         struct drm_i915_private *dev_priv = dev->dev_private;
5143
5144         connector = drm_select_eld(encoder, mode);
5145         if (!connector)
5146                 return;
5147
5148         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5149                          connector->base.id,
5150                          drm_get_connector_name(connector),
5151                          connector->encoder->base.id,
5152                          drm_get_encoder_name(connector->encoder));
5153
5154         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5155
5156         if (dev_priv->display.write_eld)
5157                 dev_priv->display.write_eld(connector, crtc);
5158 }
5159
5160 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5161 void intel_crtc_load_lut(struct drm_crtc *crtc)
5162 {
5163         struct drm_device *dev = crtc->dev;
5164         struct drm_i915_private *dev_priv = dev->dev_private;
5165         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5166         int palreg = PALETTE(intel_crtc->pipe);
5167         int i;
5168
5169         /* The clocks have to be on to load the palette. */
5170         if (!crtc->enabled || !intel_crtc->active)
5171                 return;
5172
5173         /* use legacy palette for Ironlake */
5174         if (HAS_PCH_SPLIT(dev))
5175                 palreg = LGC_PALETTE(intel_crtc->pipe);
5176
5177         for (i = 0; i < 256; i++) {
5178                 I915_WRITE(palreg + 4 * i,
5179                            (intel_crtc->lut_r[i] << 16) |
5180                            (intel_crtc->lut_g[i] << 8) |
5181                            intel_crtc->lut_b[i]);
5182         }
5183 }
5184
5185 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5186 {
5187         struct drm_device *dev = crtc->dev;
5188         struct drm_i915_private *dev_priv = dev->dev_private;
5189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5190         bool visible = base != 0;
5191         u32 cntl;
5192
5193         if (intel_crtc->cursor_visible == visible)
5194                 return;
5195
5196         cntl = I915_READ(_CURACNTR);
5197         if (visible) {
5198                 /* On these chipsets we can only modify the base whilst
5199                  * the cursor is disabled.
5200                  */
5201                 I915_WRITE(_CURABASE, base);
5202
5203                 cntl &= ~(CURSOR_FORMAT_MASK);
5204                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5205                 cntl |= CURSOR_ENABLE |
5206                         CURSOR_GAMMA_ENABLE |
5207                         CURSOR_FORMAT_ARGB;
5208         } else
5209                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5210         I915_WRITE(_CURACNTR, cntl);
5211
5212         intel_crtc->cursor_visible = visible;
5213 }
5214
5215 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5216 {
5217         struct drm_device *dev = crtc->dev;
5218         struct drm_i915_private *dev_priv = dev->dev_private;
5219         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5220         int pipe = intel_crtc->pipe;
5221         bool visible = base != 0;
5222
5223         if (intel_crtc->cursor_visible != visible) {
5224                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5225                 if (base) {
5226                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5227                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5228                         cntl |= pipe << 28; /* Connect to correct pipe */
5229                 } else {
5230                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5231                         cntl |= CURSOR_MODE_DISABLE;
5232                 }
5233                 I915_WRITE(CURCNTR(pipe), cntl);
5234
5235                 intel_crtc->cursor_visible = visible;
5236         }
5237         /* and commit changes on next vblank */
5238         I915_WRITE(CURBASE(pipe), base);
5239 }
5240
5241 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5242 {
5243         struct drm_device *dev = crtc->dev;
5244         struct drm_i915_private *dev_priv = dev->dev_private;
5245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5246         int pipe = intel_crtc->pipe;
5247         bool visible = base != 0;
5248
5249         if (intel_crtc->cursor_visible != visible) {
5250                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5251                 if (base) {
5252                         cntl &= ~CURSOR_MODE;
5253                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5254                 } else {
5255                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5256                         cntl |= CURSOR_MODE_DISABLE;
5257                 }
5258                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5259
5260                 intel_crtc->cursor_visible = visible;
5261         }
5262         /* and commit changes on next vblank */
5263         I915_WRITE(CURBASE_IVB(pipe), base);
5264 }
5265
5266 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5267 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5268                                      bool on)
5269 {
5270         struct drm_device *dev = crtc->dev;
5271         struct drm_i915_private *dev_priv = dev->dev_private;
5272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5273         int pipe = intel_crtc->pipe;
5274         int x = intel_crtc->cursor_x;
5275         int y = intel_crtc->cursor_y;
5276         u32 base, pos;
5277         bool visible;
5278
5279         pos = 0;
5280
5281         if (on && crtc->enabled && crtc->fb) {
5282                 base = intel_crtc->cursor_addr;
5283                 if (x > (int) crtc->fb->width)
5284                         base = 0;
5285
5286                 if (y > (int) crtc->fb->height)
5287                         base = 0;
5288         } else
5289                 base = 0;
5290
5291         if (x < 0) {
5292                 if (x + intel_crtc->cursor_width < 0)
5293                         base = 0;
5294
5295                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5296                 x = -x;
5297         }
5298         pos |= x << CURSOR_X_SHIFT;
5299
5300         if (y < 0) {
5301                 if (y + intel_crtc->cursor_height < 0)
5302                         base = 0;
5303
5304                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5305                 y = -y;
5306         }
5307         pos |= y << CURSOR_Y_SHIFT;
5308
5309         visible = base != 0;
5310         if (!visible && !intel_crtc->cursor_visible)
5311                 return;
5312
5313         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5314                 I915_WRITE(CURPOS_IVB(pipe), pos);
5315                 ivb_update_cursor(crtc, base);
5316         } else {
5317                 I915_WRITE(CURPOS(pipe), pos);
5318                 if (IS_845G(dev) || IS_I865G(dev))
5319                         i845_update_cursor(crtc, base);
5320                 else
5321                         i9xx_update_cursor(crtc, base);
5322         }
5323 }
5324
5325 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5326                                  struct drm_file *file,
5327                                  uint32_t handle,
5328                                  uint32_t width, uint32_t height)
5329 {
5330         struct drm_device *dev = crtc->dev;
5331         struct drm_i915_private *dev_priv = dev->dev_private;
5332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5333         struct drm_i915_gem_object *obj;
5334         uint32_t addr;
5335         int ret;
5336
5337         DRM_DEBUG_KMS("\n");
5338
5339         /* if we want to turn off the cursor ignore width and height */
5340         if (!handle) {
5341                 DRM_DEBUG_KMS("cursor off\n");
5342                 addr = 0;
5343                 obj = NULL;
5344                 mutex_lock(&dev->struct_mutex);
5345                 goto finish;
5346         }
5347
5348         /* Currently we only support 64x64 cursors */
5349         if (width != 64 || height != 64) {
5350                 DRM_ERROR("we currently only support 64x64 cursors\n");
5351                 return -EINVAL;
5352         }
5353
5354         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5355         if (&obj->base == NULL)
5356                 return -ENOENT;
5357
5358         if (obj->base.size < width * height * 4) {
5359                 DRM_ERROR("buffer is to small\n");
5360                 ret = -ENOMEM;
5361                 goto fail;
5362         }
5363
5364         /* we only need to pin inside GTT if cursor is non-phy */
5365         mutex_lock(&dev->struct_mutex);
5366         if (!dev_priv->info->cursor_needs_physical) {
5367                 if (obj->tiling_mode) {
5368                         DRM_ERROR("cursor cannot be tiled\n");
5369                         ret = -EINVAL;
5370                         goto fail_locked;
5371                 }
5372
5373                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5374                 if (ret) {
5375                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5376                         goto fail_locked;
5377                 }
5378
5379                 ret = i915_gem_object_put_fence(obj);
5380                 if (ret) {
5381                         DRM_ERROR("failed to release fence for cursor");
5382                         goto fail_unpin;
5383                 }
5384
5385                 addr = obj->gtt_offset;
5386         } else {
5387                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5388                 ret = i915_gem_attach_phys_object(dev, obj,
5389                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5390                                                   align);
5391                 if (ret) {
5392                         DRM_ERROR("failed to attach phys object\n");
5393                         goto fail_locked;
5394                 }
5395                 addr = obj->phys_obj->handle->busaddr;
5396         }
5397
5398         if (IS_GEN2(dev))
5399                 I915_WRITE(CURSIZE, (height << 12) | width);
5400
5401  finish:
5402         if (intel_crtc->cursor_bo) {
5403                 if (dev_priv->info->cursor_needs_physical) {
5404                         if (intel_crtc->cursor_bo != obj)
5405                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5406                 } else
5407                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5408                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5409         }
5410
5411         mutex_unlock(&dev->struct_mutex);
5412
5413         intel_crtc->cursor_addr = addr;
5414         intel_crtc->cursor_bo = obj;
5415         intel_crtc->cursor_width = width;
5416         intel_crtc->cursor_height = height;
5417
5418         intel_crtc_update_cursor(crtc, true);
5419
5420         return 0;
5421 fail_unpin:
5422         i915_gem_object_unpin(obj);
5423 fail_locked:
5424         mutex_unlock(&dev->struct_mutex);
5425 fail:
5426         drm_gem_object_unreference_unlocked(&obj->base);
5427         return ret;
5428 }
5429
5430 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5431 {
5432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5433
5434         intel_crtc->cursor_x = x;
5435         intel_crtc->cursor_y = y;
5436
5437         intel_crtc_update_cursor(crtc, true);
5438
5439         return 0;
5440 }
5441
5442 /** Sets the color ramps on behalf of RandR */
5443 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5444                                  u16 blue, int regno)
5445 {
5446         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5447
5448         intel_crtc->lut_r[regno] = red >> 8;
5449         intel_crtc->lut_g[regno] = green >> 8;
5450         intel_crtc->lut_b[regno] = blue >> 8;
5451 }
5452
5453 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5454                              u16 *blue, int regno)
5455 {
5456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5457
5458         *red = intel_crtc->lut_r[regno] << 8;
5459         *green = intel_crtc->lut_g[regno] << 8;
5460         *blue = intel_crtc->lut_b[regno] << 8;
5461 }
5462
5463 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5464                                  u16 *blue, uint32_t start, uint32_t size)
5465 {
5466         int end = (start + size > 256) ? 256 : start + size, i;
5467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5468
5469         for (i = start; i < end; i++) {
5470                 intel_crtc->lut_r[i] = red[i] >> 8;
5471                 intel_crtc->lut_g[i] = green[i] >> 8;
5472                 intel_crtc->lut_b[i] = blue[i] >> 8;
5473         }
5474
5475         intel_crtc_load_lut(crtc);
5476 }
5477
5478 /**
5479  * Get a pipe with a simple mode set on it for doing load-based monitor
5480  * detection.
5481  *
5482  * It will be up to the load-detect code to adjust the pipe as appropriate for
5483  * its requirements.  The pipe will be connected to no other encoders.
5484  *
5485  * Currently this code will only succeed if there is a pipe with no encoders
5486  * configured for it.  In the future, it could choose to temporarily disable
5487  * some outputs to free up a pipe for its use.
5488  *
5489  * \return crtc, or NULL if no pipes are available.
5490  */
5491
5492 /* VESA 640x480x72Hz mode to set on the pipe */
5493 static struct drm_display_mode load_detect_mode = {
5494         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5495                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5496 };
5497
5498 static struct drm_framebuffer *
5499 intel_framebuffer_create(struct drm_device *dev,
5500                          struct drm_mode_fb_cmd2 *mode_cmd,
5501                          struct drm_i915_gem_object *obj)
5502 {
5503         struct intel_framebuffer *intel_fb;
5504         int ret;
5505
5506         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5507         if (!intel_fb) {
5508                 drm_gem_object_unreference_unlocked(&obj->base);
5509                 return ERR_PTR(-ENOMEM);
5510         }
5511
5512         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5513         if (ret) {
5514                 drm_gem_object_unreference_unlocked(&obj->base);
5515                 kfree(intel_fb);
5516                 return ERR_PTR(ret);
5517         }
5518
5519         return &intel_fb->base;
5520 }
5521
5522 static u32
5523 intel_framebuffer_pitch_for_width(int width, int bpp)
5524 {
5525         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5526         return ALIGN(pitch, 64);
5527 }
5528
5529 static u32
5530 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5531 {
5532         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5533         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5534 }
5535
5536 static struct drm_framebuffer *
5537 intel_framebuffer_create_for_mode(struct drm_device *dev,
5538                                   struct drm_display_mode *mode,
5539                                   int depth, int bpp)
5540 {
5541         struct drm_i915_gem_object *obj;
5542         struct drm_mode_fb_cmd2 mode_cmd;
5543
5544         obj = i915_gem_alloc_object(dev,
5545                                     intel_framebuffer_size_for_mode(mode, bpp));
5546         if (obj == NULL)
5547                 return ERR_PTR(-ENOMEM);
5548
5549         mode_cmd.width = mode->hdisplay;
5550         mode_cmd.height = mode->vdisplay;
5551         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5552                                                                 bpp);
5553         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5554
5555         return intel_framebuffer_create(dev, &mode_cmd, obj);
5556 }
5557
5558 static struct drm_framebuffer *
5559 mode_fits_in_fbdev(struct drm_device *dev,
5560                    struct drm_display_mode *mode)
5561 {
5562         struct drm_i915_private *dev_priv = dev->dev_private;
5563         struct drm_i915_gem_object *obj;
5564         struct drm_framebuffer *fb;
5565
5566         if (dev_priv->fbdev == NULL)
5567                 return NULL;
5568
5569         obj = dev_priv->fbdev->ifb.obj;
5570         if (obj == NULL)
5571                 return NULL;
5572
5573         fb = &dev_priv->fbdev->ifb.base;
5574         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5575                                                                fb->bits_per_pixel))
5576                 return NULL;
5577
5578         if (obj->base.size < mode->vdisplay * fb->pitches[0])
5579                 return NULL;
5580
5581         return fb;
5582 }
5583
5584 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5585                                 struct drm_connector *connector,
5586                                 struct drm_display_mode *mode,
5587                                 struct intel_load_detect_pipe *old)
5588 {
5589         struct intel_crtc *intel_crtc;
5590         struct drm_crtc *possible_crtc;
5591         struct drm_encoder *encoder = &intel_encoder->base;
5592         struct drm_crtc *crtc = NULL;
5593         struct drm_device *dev = encoder->dev;
5594         struct drm_framebuffer *old_fb;
5595         int i = -1;
5596
5597         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5598                       connector->base.id, drm_get_connector_name(connector),
5599                       encoder->base.id, drm_get_encoder_name(encoder));
5600
5601         /*
5602          * Algorithm gets a little messy:
5603          *
5604          *   - if the connector already has an assigned crtc, use it (but make
5605          *     sure it's on first)
5606          *
5607          *   - try to find the first unused crtc that can drive this connector,
5608          *     and use that if we find one
5609          */
5610
5611         /* See if we already have a CRTC for this connector */
5612         if (encoder->crtc) {
5613                 crtc = encoder->crtc;
5614
5615                 intel_crtc = to_intel_crtc(crtc);
5616                 old->dpms_mode = intel_crtc->dpms_mode;
5617                 old->load_detect_temp = false;
5618
5619                 /* Make sure the crtc and connector are running */
5620                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5621                         struct drm_encoder_helper_funcs *encoder_funcs;
5622                         struct drm_crtc_helper_funcs *crtc_funcs;
5623
5624                         crtc_funcs = crtc->helper_private;
5625                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5626
5627                         encoder_funcs = encoder->helper_private;
5628                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5629                 }
5630
5631                 return true;
5632         }
5633
5634         /* Find an unused one (if possible) */
5635         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5636                 i++;
5637                 if (!(encoder->possible_crtcs & (1 << i)))
5638                         continue;
5639                 if (!possible_crtc->enabled) {
5640                         crtc = possible_crtc;
5641                         break;
5642                 }
5643         }
5644
5645         /*
5646          * If we didn't find an unused CRTC, don't use any.
5647          */
5648         if (!crtc) {
5649                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5650                 return false;
5651         }
5652
5653         encoder->crtc = crtc;
5654         connector->encoder = encoder;
5655
5656         intel_crtc = to_intel_crtc(crtc);
5657         old->dpms_mode = intel_crtc->dpms_mode;
5658         old->load_detect_temp = true;
5659         old->release_fb = NULL;
5660
5661         if (!mode)
5662                 mode = &load_detect_mode;
5663
5664         old_fb = crtc->fb;
5665
5666         /* We need a framebuffer large enough to accommodate all accesses
5667          * that the plane may generate whilst we perform load detection.
5668          * We can not rely on the fbcon either being present (we get called
5669          * during its initialisation to detect all boot displays, or it may
5670          * not even exist) or that it is large enough to satisfy the
5671          * requested mode.
5672          */
5673         crtc->fb = mode_fits_in_fbdev(dev, mode);
5674         if (crtc->fb == NULL) {
5675                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5676                 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5677                 old->release_fb = crtc->fb;
5678         } else
5679                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5680         if (IS_ERR(crtc->fb)) {
5681                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5682                 crtc->fb = old_fb;
5683                 return false;
5684         }
5685
5686         if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5687                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5688                 if (old->release_fb)
5689                         old->release_fb->funcs->destroy(old->release_fb);
5690                 crtc->fb = old_fb;
5691                 return false;
5692         }
5693
5694         /* let the connector get through one full cycle before testing */
5695         intel_wait_for_vblank(dev, intel_crtc->pipe);
5696
5697         return true;
5698 }
5699
5700 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5701                                     struct drm_connector *connector,
5702                                     struct intel_load_detect_pipe *old)
5703 {
5704         struct drm_encoder *encoder = &intel_encoder->base;
5705         struct drm_device *dev = encoder->dev;
5706         struct drm_crtc *crtc = encoder->crtc;
5707         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5708         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5709
5710         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5711                       connector->base.id, drm_get_connector_name(connector),
5712                       encoder->base.id, drm_get_encoder_name(encoder));
5713
5714         if (old->load_detect_temp) {
5715                 connector->encoder = NULL;
5716                 drm_helper_disable_unused_functions(dev);
5717
5718                 if (old->release_fb)
5719                         old->release_fb->funcs->destroy(old->release_fb);
5720
5721                 return;
5722         }
5723
5724         /* Switch crtc and encoder back off if necessary */
5725         if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5726                 encoder_funcs->dpms(encoder, old->dpms_mode);
5727                 crtc_funcs->dpms(crtc, old->dpms_mode);
5728         }
5729 }
5730
5731 /* Returns the clock of the currently programmed mode of the given pipe. */
5732 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5733 {
5734         struct drm_i915_private *dev_priv = dev->dev_private;
5735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5736         int pipe = intel_crtc->pipe;
5737         u32 dpll = I915_READ(DPLL(pipe));
5738         u32 fp;
5739         intel_clock_t clock;
5740
5741         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5742                 fp = I915_READ(FP0(pipe));
5743         else
5744                 fp = I915_READ(FP1(pipe));
5745
5746         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5747         if (IS_PINEVIEW(dev)) {
5748                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5749                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5750         } else {
5751                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5752                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5753         }
5754
5755         if (!IS_GEN2(dev)) {
5756                 if (IS_PINEVIEW(dev))
5757                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5758                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5759                 else
5760                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5761                                DPLL_FPA01_P1_POST_DIV_SHIFT);
5762
5763                 switch (dpll & DPLL_MODE_MASK) {
5764                 case DPLLB_MODE_DAC_SERIAL:
5765                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5766                                 5 : 10;
5767                         break;
5768                 case DPLLB_MODE_LVDS:
5769                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5770                                 7 : 14;
5771                         break;
5772                 default:
5773                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5774                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
5775                         return 0;
5776                 }
5777
5778                 /* XXX: Handle the 100Mhz refclk */
5779                 intel_clock(dev, 96000, &clock);
5780         } else {
5781                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5782
5783                 if (is_lvds) {
5784                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5785                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
5786                         clock.p2 = 14;
5787
5788                         if ((dpll & PLL_REF_INPUT_MASK) ==
5789                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5790                                 /* XXX: might not be 66MHz */
5791                                 intel_clock(dev, 66000, &clock);
5792                         } else
5793                                 intel_clock(dev, 48000, &clock);
5794                 } else {
5795                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
5796                                 clock.p1 = 2;
5797                         else {
5798                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5799                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5800                         }
5801                         if (dpll & PLL_P2_DIVIDE_BY_4)
5802                                 clock.p2 = 4;
5803                         else
5804                                 clock.p2 = 2;
5805
5806                         intel_clock(dev, 48000, &clock);
5807                 }
5808         }
5809
5810         /* XXX: It would be nice to validate the clocks, but we can't reuse
5811          * i830PllIsValid() because it relies on the xf86_config connector
5812          * configuration being accurate, which it isn't necessarily.
5813          */
5814
5815         return clock.dot;
5816 }
5817
5818 /** Returns the currently programmed mode of the given pipe. */
5819 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5820                                              struct drm_crtc *crtc)
5821 {
5822         struct drm_i915_private *dev_priv = dev->dev_private;
5823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5824         int pipe = intel_crtc->pipe;
5825         struct drm_display_mode *mode;
5826         int htot = I915_READ(HTOTAL(pipe));
5827         int hsync = I915_READ(HSYNC(pipe));
5828         int vtot = I915_READ(VTOTAL(pipe));
5829         int vsync = I915_READ(VSYNC(pipe));
5830
5831         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5832         if (!mode)
5833                 return NULL;
5834
5835         mode->clock = intel_crtc_clock_get(dev, crtc);
5836         mode->hdisplay = (htot & 0xffff) + 1;
5837         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5838         mode->hsync_start = (hsync & 0xffff) + 1;
5839         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5840         mode->vdisplay = (vtot & 0xffff) + 1;
5841         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5842         mode->vsync_start = (vsync & 0xffff) + 1;
5843         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5844
5845         drm_mode_set_name(mode);
5846
5847         return mode;
5848 }
5849
5850 #define GPU_IDLE_TIMEOUT 500 /* ms */
5851
5852 /* When this timer fires, we've been idle for awhile */
5853 static void intel_gpu_idle_timer(unsigned long arg)
5854 {
5855         struct drm_device *dev = (struct drm_device *)arg;
5856         drm_i915_private_t *dev_priv = dev->dev_private;
5857
5858         if (!list_empty(&dev_priv->mm.active_list)) {
5859                 /* Still processing requests, so just re-arm the timer. */
5860                 mod_timer(&dev_priv->idle_timer, jiffies +
5861                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5862                 return;
5863         }
5864
5865         dev_priv->busy = false;
5866         queue_work(dev_priv->wq, &dev_priv->idle_work);
5867 }
5868
5869 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5870
5871 static void intel_crtc_idle_timer(unsigned long arg)
5872 {
5873         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5874         struct drm_crtc *crtc = &intel_crtc->base;
5875         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5876         struct intel_framebuffer *intel_fb;
5877
5878         intel_fb = to_intel_framebuffer(crtc->fb);
5879         if (intel_fb && intel_fb->obj->active) {
5880                 /* The framebuffer is still being accessed by the GPU. */
5881                 mod_timer(&intel_crtc->idle_timer, jiffies +
5882                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5883                 return;
5884         }
5885
5886         intel_crtc->busy = false;
5887         queue_work(dev_priv->wq, &dev_priv->idle_work);
5888 }
5889
5890 static void intel_increase_pllclock(struct drm_crtc *crtc)
5891 {
5892         struct drm_device *dev = crtc->dev;
5893         drm_i915_private_t *dev_priv = dev->dev_private;
5894         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5895         int pipe = intel_crtc->pipe;
5896         int dpll_reg = DPLL(pipe);
5897         int dpll;
5898
5899         if (HAS_PCH_SPLIT(dev))
5900                 return;
5901
5902         if (!dev_priv->lvds_downclock_avail)
5903                 return;
5904
5905         dpll = I915_READ(dpll_reg);
5906         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5907                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5908
5909                 assert_panel_unlocked(dev_priv, pipe);
5910
5911                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5912                 I915_WRITE(dpll_reg, dpll);
5913                 intel_wait_for_vblank(dev, pipe);
5914
5915                 dpll = I915_READ(dpll_reg);
5916                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5917                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5918         }
5919
5920         /* Schedule downclock */
5921         mod_timer(&intel_crtc->idle_timer, jiffies +
5922                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5923 }
5924
5925 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5926 {
5927         struct drm_device *dev = crtc->dev;
5928         drm_i915_private_t *dev_priv = dev->dev_private;
5929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5930
5931         if (HAS_PCH_SPLIT(dev))
5932                 return;
5933
5934         if (!dev_priv->lvds_downclock_avail)
5935                 return;
5936
5937         /*
5938          * Since this is called by a timer, we should never get here in
5939          * the manual case.
5940          */
5941         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5942                 int pipe = intel_crtc->pipe;
5943                 int dpll_reg = DPLL(pipe);
5944                 int dpll;
5945
5946                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5947
5948                 assert_panel_unlocked(dev_priv, pipe);
5949
5950                 dpll = I915_READ(dpll_reg);
5951                 dpll |= DISPLAY_RATE_SELECT_FPA1;
5952                 I915_WRITE(dpll_reg, dpll);
5953                 intel_wait_for_vblank(dev, pipe);
5954                 dpll = I915_READ(dpll_reg);
5955                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5956                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5957         }
5958
5959 }
5960
5961 /**
5962  * intel_idle_update - adjust clocks for idleness
5963  * @work: work struct
5964  *
5965  * Either the GPU or display (or both) went idle.  Check the busy status
5966  * here and adjust the CRTC and GPU clocks as necessary.
5967  */
5968 static void intel_idle_update(struct work_struct *work)
5969 {
5970         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5971                                                     idle_work);
5972         struct drm_device *dev = dev_priv->dev;
5973         struct drm_crtc *crtc;
5974         struct intel_crtc *intel_crtc;
5975
5976         if (!i915_powersave)
5977                 return;
5978
5979         mutex_lock(&dev->struct_mutex);
5980
5981         i915_update_gfx_val(dev_priv);
5982
5983         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5984                 /* Skip inactive CRTCs */
5985                 if (!crtc->fb)
5986                         continue;
5987
5988                 intel_crtc = to_intel_crtc(crtc);
5989                 if (!intel_crtc->busy)
5990                         intel_decrease_pllclock(crtc);
5991         }
5992
5993
5994         mutex_unlock(&dev->struct_mutex);
5995 }
5996
5997 /**
5998  * intel_mark_busy - mark the GPU and possibly the display busy
5999  * @dev: drm device
6000  * @obj: object we're operating on
6001  *
6002  * Callers can use this function to indicate that the GPU is busy processing
6003  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
6004  * buffer), we'll also mark the display as busy, so we know to increase its
6005  * clock frequency.
6006  */
6007 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6008 {
6009         drm_i915_private_t *dev_priv = dev->dev_private;
6010         struct drm_crtc *crtc = NULL;
6011         struct intel_framebuffer *intel_fb;
6012         struct intel_crtc *intel_crtc;
6013
6014         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6015                 return;
6016
6017         if (!dev_priv->busy) {
6018                 intel_sanitize_pm(dev);
6019                 dev_priv->busy = true;
6020         } else
6021                 mod_timer(&dev_priv->idle_timer, jiffies +
6022                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6023
6024         if (obj == NULL)
6025                 return;
6026
6027         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6028                 if (!crtc->fb)
6029                         continue;
6030
6031                 intel_crtc = to_intel_crtc(crtc);
6032                 intel_fb = to_intel_framebuffer(crtc->fb);
6033                 if (intel_fb->obj == obj) {
6034                         if (!intel_crtc->busy) {
6035                                 /* Non-busy -> busy, upclock */
6036                                 intel_increase_pllclock(crtc);
6037                                 intel_crtc->busy = true;
6038                         } else {
6039                                 /* Busy -> busy, put off timer */
6040                                 mod_timer(&intel_crtc->idle_timer, jiffies +
6041                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6042                         }
6043                 }
6044         }
6045 }
6046
6047 static void intel_crtc_destroy(struct drm_crtc *crtc)
6048 {
6049         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6050         struct drm_device *dev = crtc->dev;
6051         struct intel_unpin_work *work;
6052         unsigned long flags;
6053
6054         spin_lock_irqsave(&dev->event_lock, flags);
6055         work = intel_crtc->unpin_work;
6056         intel_crtc->unpin_work = NULL;
6057         spin_unlock_irqrestore(&dev->event_lock, flags);
6058
6059         if (work) {
6060                 cancel_work_sync(&work->work);
6061                 kfree(work);
6062         }
6063
6064         drm_crtc_cleanup(crtc);
6065
6066         kfree(intel_crtc);
6067 }
6068
6069 static void intel_unpin_work_fn(struct work_struct *__work)
6070 {
6071         struct intel_unpin_work *work =
6072                 container_of(__work, struct intel_unpin_work, work);
6073
6074         mutex_lock(&work->dev->struct_mutex);
6075         intel_unpin_fb_obj(work->old_fb_obj);
6076         drm_gem_object_unreference(&work->pending_flip_obj->base);
6077         drm_gem_object_unreference(&work->old_fb_obj->base);
6078
6079         intel_update_fbc(work->dev);
6080         mutex_unlock(&work->dev->struct_mutex);
6081         kfree(work);
6082 }
6083
6084 static void do_intel_finish_page_flip(struct drm_device *dev,
6085                                       struct drm_crtc *crtc)
6086 {
6087         drm_i915_private_t *dev_priv = dev->dev_private;
6088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6089         struct intel_unpin_work *work;
6090         struct drm_i915_gem_object *obj;
6091         struct drm_pending_vblank_event *e;
6092         struct timeval tnow, tvbl;
6093         unsigned long flags;
6094
6095         /* Ignore early vblank irqs */
6096         if (intel_crtc == NULL)
6097                 return;
6098
6099         do_gettimeofday(&tnow);
6100
6101         spin_lock_irqsave(&dev->event_lock, flags);
6102         work = intel_crtc->unpin_work;
6103         if (work == NULL || !work->pending) {
6104                 spin_unlock_irqrestore(&dev->event_lock, flags);
6105                 return;
6106         }
6107
6108         intel_crtc->unpin_work = NULL;
6109
6110         if (work->event) {
6111                 e = work->event;
6112                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6113
6114                 /* Called before vblank count and timestamps have
6115                  * been updated for the vblank interval of flip
6116                  * completion? Need to increment vblank count and
6117                  * add one videorefresh duration to returned timestamp
6118                  * to account for this. We assume this happened if we
6119                  * get called over 0.9 frame durations after the last
6120                  * timestamped vblank.
6121                  *
6122                  * This calculation can not be used with vrefresh rates
6123                  * below 5Hz (10Hz to be on the safe side) without
6124                  * promoting to 64 integers.
6125                  */
6126                 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6127                     9 * crtc->framedur_ns) {
6128                         e->event.sequence++;
6129                         tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6130                                              crtc->framedur_ns);
6131                 }
6132
6133                 e->event.tv_sec = tvbl.tv_sec;
6134                 e->event.tv_usec = tvbl.tv_usec;
6135
6136                 list_add_tail(&e->base.link,
6137                               &e->base.file_priv->event_list);
6138                 wake_up_interruptible(&e->base.file_priv->event_wait);
6139         }
6140
6141         drm_vblank_put(dev, intel_crtc->pipe);
6142
6143         spin_unlock_irqrestore(&dev->event_lock, flags);
6144
6145         obj = work->old_fb_obj;
6146
6147         atomic_clear_mask(1 << intel_crtc->plane,
6148                           &obj->pending_flip.counter);
6149         if (atomic_read(&obj->pending_flip) == 0)
6150                 wake_up(&dev_priv->pending_flip_queue);
6151
6152         schedule_work(&work->work);
6153
6154         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6155 }
6156
6157 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6158 {
6159         drm_i915_private_t *dev_priv = dev->dev_private;
6160         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6161
6162         do_intel_finish_page_flip(dev, crtc);
6163 }
6164
6165 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6166 {
6167         drm_i915_private_t *dev_priv = dev->dev_private;
6168         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6169
6170         do_intel_finish_page_flip(dev, crtc);
6171 }
6172
6173 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6174 {
6175         drm_i915_private_t *dev_priv = dev->dev_private;
6176         struct intel_crtc *intel_crtc =
6177                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6178         unsigned long flags;
6179
6180         spin_lock_irqsave(&dev->event_lock, flags);
6181         if (intel_crtc->unpin_work) {
6182                 if ((++intel_crtc->unpin_work->pending) > 1)
6183                         DRM_ERROR("Prepared flip multiple times\n");
6184         } else {
6185                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6186         }
6187         spin_unlock_irqrestore(&dev->event_lock, flags);
6188 }
6189
6190 static int intel_gen2_queue_flip(struct drm_device *dev,
6191                                  struct drm_crtc *crtc,
6192                                  struct drm_framebuffer *fb,
6193                                  struct drm_i915_gem_object *obj)
6194 {
6195         struct drm_i915_private *dev_priv = dev->dev_private;
6196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6197         unsigned long offset;
6198         u32 flip_mask;
6199         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6200         int ret;
6201
6202         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6203         if (ret)
6204                 goto err;
6205
6206         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6207         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6208
6209         ret = intel_ring_begin(ring, 6);
6210         if (ret)
6211                 goto err_unpin;
6212
6213         /* Can't queue multiple flips, so wait for the previous
6214          * one to finish before executing the next.
6215          */
6216         if (intel_crtc->plane)
6217                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6218         else
6219                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6220         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6221         intel_ring_emit(ring, MI_NOOP);
6222         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6223                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6224         intel_ring_emit(ring, fb->pitches[0]);
6225         intel_ring_emit(ring, obj->gtt_offset + offset);
6226         intel_ring_emit(ring, 0); /* aux display base address, unused */
6227         intel_ring_advance(ring);
6228         return 0;
6229
6230 err_unpin:
6231         intel_unpin_fb_obj(obj);
6232 err:
6233         return ret;
6234 }
6235
6236 static int intel_gen3_queue_flip(struct drm_device *dev,
6237                                  struct drm_crtc *crtc,
6238                                  struct drm_framebuffer *fb,
6239                                  struct drm_i915_gem_object *obj)
6240 {
6241         struct drm_i915_private *dev_priv = dev->dev_private;
6242         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6243         unsigned long offset;
6244         u32 flip_mask;
6245         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6246         int ret;
6247
6248         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6249         if (ret)
6250                 goto err;
6251
6252         /* Offset into the new buffer for cases of shared fbs between CRTCs */
6253         offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
6254
6255         ret = intel_ring_begin(ring, 6);
6256         if (ret)
6257                 goto err_unpin;
6258
6259         if (intel_crtc->plane)
6260                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6261         else
6262                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6263         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6264         intel_ring_emit(ring, MI_NOOP);
6265         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6266                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6267         intel_ring_emit(ring, fb->pitches[0]);
6268         intel_ring_emit(ring, obj->gtt_offset + offset);
6269         intel_ring_emit(ring, MI_NOOP);
6270
6271         intel_ring_advance(ring);
6272         return 0;
6273
6274 err_unpin:
6275         intel_unpin_fb_obj(obj);
6276 err:
6277         return ret;
6278 }
6279
6280 static int intel_gen4_queue_flip(struct drm_device *dev,
6281                                  struct drm_crtc *crtc,
6282                                  struct drm_framebuffer *fb,
6283                                  struct drm_i915_gem_object *obj)
6284 {
6285         struct drm_i915_private *dev_priv = dev->dev_private;
6286         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6287         uint32_t pf, pipesrc;
6288         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6289         int ret;
6290
6291         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6292         if (ret)
6293                 goto err;
6294
6295         ret = intel_ring_begin(ring, 4);
6296         if (ret)
6297                 goto err_unpin;
6298
6299         /* i965+ uses the linear or tiled offsets from the
6300          * Display Registers (which do not change across a page-flip)
6301          * so we need only reprogram the base address.
6302          */
6303         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6304                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6305         intel_ring_emit(ring, fb->pitches[0]);
6306         intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
6307
6308         /* XXX Enabling the panel-fitter across page-flip is so far
6309          * untested on non-native modes, so ignore it for now.
6310          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6311          */
6312         pf = 0;
6313         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6314         intel_ring_emit(ring, pf | pipesrc);
6315         intel_ring_advance(ring);
6316         return 0;
6317
6318 err_unpin:
6319         intel_unpin_fb_obj(obj);
6320 err:
6321         return ret;
6322 }
6323
6324 static int intel_gen6_queue_flip(struct drm_device *dev,
6325                                  struct drm_crtc *crtc,
6326                                  struct drm_framebuffer *fb,
6327                                  struct drm_i915_gem_object *obj)
6328 {
6329         struct drm_i915_private *dev_priv = dev->dev_private;
6330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6332         uint32_t pf, pipesrc;
6333         int ret;
6334
6335         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6336         if (ret)
6337                 goto err;
6338
6339         ret = intel_ring_begin(ring, 4);
6340         if (ret)
6341                 goto err_unpin;
6342
6343         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6344                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6345         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6346         intel_ring_emit(ring, obj->gtt_offset);
6347
6348         /* Contrary to the suggestions in the documentation,
6349          * "Enable Panel Fitter" does not seem to be required when page
6350          * flipping with a non-native mode, and worse causes a normal
6351          * modeset to fail.
6352          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6353          */
6354         pf = 0;
6355         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6356         intel_ring_emit(ring, pf | pipesrc);
6357         intel_ring_advance(ring);
6358         return 0;
6359
6360 err_unpin:
6361         intel_unpin_fb_obj(obj);
6362 err:
6363         return ret;
6364 }
6365
6366 /*
6367  * On gen7 we currently use the blit ring because (in early silicon at least)
6368  * the render ring doesn't give us interrpts for page flip completion, which
6369  * means clients will hang after the first flip is queued.  Fortunately the
6370  * blit ring generates interrupts properly, so use it instead.
6371  */
6372 static int intel_gen7_queue_flip(struct drm_device *dev,
6373                                  struct drm_crtc *crtc,
6374                                  struct drm_framebuffer *fb,
6375                                  struct drm_i915_gem_object *obj)
6376 {
6377         struct drm_i915_private *dev_priv = dev->dev_private;
6378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6380         uint32_t plane_bit = 0;
6381         int ret;
6382
6383         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6384         if (ret)
6385                 goto err;
6386
6387         switch(intel_crtc->plane) {
6388         case PLANE_A:
6389                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6390                 break;
6391         case PLANE_B:
6392                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6393                 break;
6394         case PLANE_C:
6395                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6396                 break;
6397         default:
6398                 WARN_ONCE(1, "unknown plane in flip command\n");
6399                 ret = -ENODEV;
6400                 goto err;
6401         }
6402
6403         ret = intel_ring_begin(ring, 4);
6404         if (ret)
6405                 goto err_unpin;
6406
6407         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6408         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6409         intel_ring_emit(ring, (obj->gtt_offset));
6410         intel_ring_emit(ring, (MI_NOOP));
6411         intel_ring_advance(ring);
6412         return 0;
6413
6414 err_unpin:
6415         intel_unpin_fb_obj(obj);
6416 err:
6417         return ret;
6418 }
6419
6420 static int intel_default_queue_flip(struct drm_device *dev,
6421                                     struct drm_crtc *crtc,
6422                                     struct drm_framebuffer *fb,
6423                                     struct drm_i915_gem_object *obj)
6424 {
6425         return -ENODEV;
6426 }
6427
6428 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6429                                 struct drm_framebuffer *fb,
6430                                 struct drm_pending_vblank_event *event)
6431 {
6432         struct drm_device *dev = crtc->dev;
6433         struct drm_i915_private *dev_priv = dev->dev_private;
6434         struct intel_framebuffer *intel_fb;
6435         struct drm_i915_gem_object *obj;
6436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6437         struct intel_unpin_work *work;
6438         unsigned long flags;
6439         int ret;
6440
6441         work = kzalloc(sizeof *work, GFP_KERNEL);
6442         if (work == NULL)
6443                 return -ENOMEM;
6444
6445         work->event = event;
6446         work->dev = crtc->dev;
6447         intel_fb = to_intel_framebuffer(crtc->fb);
6448         work->old_fb_obj = intel_fb->obj;
6449         INIT_WORK(&work->work, intel_unpin_work_fn);
6450
6451         ret = drm_vblank_get(dev, intel_crtc->pipe);
6452         if (ret)
6453                 goto free_work;
6454
6455         /* We borrow the event spin lock for protecting unpin_work */
6456         spin_lock_irqsave(&dev->event_lock, flags);
6457         if (intel_crtc->unpin_work) {
6458                 spin_unlock_irqrestore(&dev->event_lock, flags);
6459                 kfree(work);
6460                 drm_vblank_put(dev, intel_crtc->pipe);
6461
6462                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6463                 return -EBUSY;
6464         }
6465         intel_crtc->unpin_work = work;
6466         spin_unlock_irqrestore(&dev->event_lock, flags);
6467
6468         intel_fb = to_intel_framebuffer(fb);
6469         obj = intel_fb->obj;
6470
6471         mutex_lock(&dev->struct_mutex);
6472
6473         /* Reference the objects for the scheduled work. */
6474         drm_gem_object_reference(&work->old_fb_obj->base);
6475         drm_gem_object_reference(&obj->base);
6476
6477         crtc->fb = fb;
6478
6479         work->pending_flip_obj = obj;
6480
6481         work->enable_stall_check = true;
6482
6483         /* Block clients from rendering to the new back buffer until
6484          * the flip occurs and the object is no longer visible.
6485          */
6486         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6487
6488         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6489         if (ret)
6490                 goto cleanup_pending;
6491
6492         intel_disable_fbc(dev);
6493         intel_mark_busy(dev, obj);
6494         mutex_unlock(&dev->struct_mutex);
6495
6496         trace_i915_flip_request(intel_crtc->plane, obj);
6497
6498         return 0;
6499
6500 cleanup_pending:
6501         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6502         drm_gem_object_unreference(&work->old_fb_obj->base);
6503         drm_gem_object_unreference(&obj->base);
6504         mutex_unlock(&dev->struct_mutex);
6505
6506         spin_lock_irqsave(&dev->event_lock, flags);
6507         intel_crtc->unpin_work = NULL;
6508         spin_unlock_irqrestore(&dev->event_lock, flags);
6509
6510         drm_vblank_put(dev, intel_crtc->pipe);
6511 free_work:
6512         kfree(work);
6513
6514         return ret;
6515 }
6516
6517 static void intel_sanitize_modesetting(struct drm_device *dev,
6518                                        int pipe, int plane)
6519 {
6520         struct drm_i915_private *dev_priv = dev->dev_private;
6521         u32 reg, val;
6522         int i;
6523
6524         /* Clear any frame start delays used for debugging left by the BIOS */
6525         for_each_pipe(i) {
6526                 reg = PIPECONF(i);
6527                 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6528         }
6529
6530         if (HAS_PCH_SPLIT(dev))
6531                 return;
6532
6533         /* Who knows what state these registers were left in by the BIOS or
6534          * grub?
6535          *
6536          * If we leave the registers in a conflicting state (e.g. with the
6537          * display plane reading from the other pipe than the one we intend
6538          * to use) then when we attempt to teardown the active mode, we will
6539          * not disable the pipes and planes in the correct order -- leaving
6540          * a plane reading from a disabled pipe and possibly leading to
6541          * undefined behaviour.
6542          */
6543
6544         reg = DSPCNTR(plane);
6545         val = I915_READ(reg);
6546
6547         if ((val & DISPLAY_PLANE_ENABLE) == 0)
6548                 return;
6549         if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6550                 return;
6551
6552         /* This display plane is active and attached to the other CPU pipe. */
6553         pipe = !pipe;
6554
6555         /* Disable the plane and wait for it to stop reading from the pipe. */
6556         intel_disable_plane(dev_priv, plane, pipe);
6557         intel_disable_pipe(dev_priv, pipe);
6558 }
6559
6560 static void intel_crtc_reset(struct drm_crtc *crtc)
6561 {
6562         struct drm_device *dev = crtc->dev;
6563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6564
6565         /* Reset flags back to the 'unknown' status so that they
6566          * will be correctly set on the initial modeset.
6567          */
6568         intel_crtc->dpms_mode = -1;
6569
6570         /* We need to fix up any BIOS configuration that conflicts with
6571          * our expectations.
6572          */
6573         intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6574 }
6575
6576 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6577         .dpms = intel_crtc_dpms,
6578         .mode_fixup = intel_crtc_mode_fixup,
6579         .mode_set = intel_crtc_mode_set,
6580         .mode_set_base = intel_pipe_set_base,
6581         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6582         .load_lut = intel_crtc_load_lut,
6583         .disable = intel_crtc_disable,
6584 };
6585
6586 static const struct drm_crtc_funcs intel_crtc_funcs = {
6587         .reset = intel_crtc_reset,
6588         .cursor_set = intel_crtc_cursor_set,
6589         .cursor_move = intel_crtc_cursor_move,
6590         .gamma_set = intel_crtc_gamma_set,
6591         .set_config = drm_crtc_helper_set_config,
6592         .destroy = intel_crtc_destroy,
6593         .page_flip = intel_crtc_page_flip,
6594 };
6595
6596 static void intel_pch_pll_init(struct drm_device *dev)
6597 {
6598         drm_i915_private_t *dev_priv = dev->dev_private;
6599         int i;
6600
6601         if (dev_priv->num_pch_pll == 0) {
6602                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6603                 return;
6604         }
6605
6606         for (i = 0; i < dev_priv->num_pch_pll; i++) {
6607                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6608                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6609                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6610         }
6611 }
6612
6613 static void intel_crtc_init(struct drm_device *dev, int pipe)
6614 {
6615         drm_i915_private_t *dev_priv = dev->dev_private;
6616         struct intel_crtc *intel_crtc;
6617         int i;
6618
6619         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6620         if (intel_crtc == NULL)
6621                 return;
6622
6623         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6624
6625         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6626         for (i = 0; i < 256; i++) {
6627                 intel_crtc->lut_r[i] = i;
6628                 intel_crtc->lut_g[i] = i;
6629                 intel_crtc->lut_b[i] = i;
6630         }
6631
6632         /* Swap pipes & planes for FBC on pre-965 */
6633         intel_crtc->pipe = pipe;
6634         intel_crtc->plane = pipe;
6635         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6636                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6637                 intel_crtc->plane = !pipe;
6638         }
6639
6640         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6641                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6642         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6643         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6644
6645         intel_crtc_reset(&intel_crtc->base);
6646         intel_crtc->active = true; /* force the pipe off on setup_init_config */
6647         intel_crtc->bpp = 24; /* default for pre-Ironlake */
6648
6649         if (HAS_PCH_SPLIT(dev)) {
6650                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6651                 intel_helper_funcs.commit = ironlake_crtc_commit;
6652         } else {
6653                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6654                 intel_helper_funcs.commit = i9xx_crtc_commit;
6655         }
6656
6657         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6658
6659         intel_crtc->busy = false;
6660
6661         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6662                     (unsigned long)intel_crtc);
6663 }
6664
6665 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6666                                 struct drm_file *file)
6667 {
6668         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6669         struct drm_mode_object *drmmode_obj;
6670         struct intel_crtc *crtc;
6671
6672         if (!drm_core_check_feature(dev, DRIVER_MODESET))
6673                 return -ENODEV;
6674
6675         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6676                         DRM_MODE_OBJECT_CRTC);
6677
6678         if (!drmmode_obj) {
6679                 DRM_ERROR("no such CRTC id\n");
6680                 return -EINVAL;
6681         }
6682
6683         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6684         pipe_from_crtc_id->pipe = crtc->pipe;
6685
6686         return 0;
6687 }
6688
6689 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
6690 {
6691         struct intel_encoder *encoder;
6692         int index_mask = 0;
6693         int entry = 0;
6694
6695         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6696                 if (type_mask & encoder->clone_mask)
6697                         index_mask |= (1 << entry);
6698                 entry++;
6699         }
6700
6701         return index_mask;
6702 }
6703
6704 static bool has_edp_a(struct drm_device *dev)
6705 {
6706         struct drm_i915_private *dev_priv = dev->dev_private;
6707
6708         if (!IS_MOBILE(dev))
6709                 return false;
6710
6711         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6712                 return false;
6713
6714         if (IS_GEN5(dev) &&
6715             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6716                 return false;
6717
6718         return true;
6719 }
6720
6721 static void intel_setup_outputs(struct drm_device *dev)
6722 {
6723         struct drm_i915_private *dev_priv = dev->dev_private;
6724         struct intel_encoder *encoder;
6725         bool dpd_is_edp = false;
6726         bool has_lvds;
6727
6728         has_lvds = intel_lvds_init(dev);
6729         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6730                 /* disable the panel fitter on everything but LVDS */
6731                 I915_WRITE(PFIT_CONTROL, 0);
6732         }
6733
6734         if (HAS_PCH_SPLIT(dev)) {
6735                 dpd_is_edp = intel_dpd_is_edp(dev);
6736
6737                 if (has_edp_a(dev))
6738                         intel_dp_init(dev, DP_A);
6739
6740                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6741                         intel_dp_init(dev, PCH_DP_D);
6742         }
6743
6744         intel_crt_init(dev);
6745
6746         if (IS_HASWELL(dev)) {
6747                 int found;
6748
6749                 /* Haswell uses DDI functions to detect digital outputs */
6750                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6751                 /* DDI A only supports eDP */
6752                 if (found)
6753                         intel_ddi_init(dev, PORT_A);
6754
6755                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6756                  * register */
6757                 found = I915_READ(SFUSE_STRAP);
6758
6759                 if (found & SFUSE_STRAP_DDIB_DETECTED)
6760                         intel_ddi_init(dev, PORT_B);
6761                 if (found & SFUSE_STRAP_DDIC_DETECTED)
6762                         intel_ddi_init(dev, PORT_C);
6763                 if (found & SFUSE_STRAP_DDID_DETECTED)
6764                         intel_ddi_init(dev, PORT_D);
6765         } else if (HAS_PCH_SPLIT(dev)) {
6766                 int found;
6767
6768                 if (I915_READ(HDMIB) & PORT_DETECTED) {
6769                         /* PCH SDVOB multiplex with HDMIB */
6770                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
6771                         if (!found)
6772                                 intel_hdmi_init(dev, HDMIB);
6773                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6774                                 intel_dp_init(dev, PCH_DP_B);
6775                 }
6776
6777                 if (I915_READ(HDMIC) & PORT_DETECTED)
6778                         intel_hdmi_init(dev, HDMIC);
6779
6780                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6781                         intel_hdmi_init(dev, HDMID);
6782
6783                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6784                         intel_dp_init(dev, PCH_DP_C);
6785
6786                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6787                         intel_dp_init(dev, PCH_DP_D);
6788         } else if (IS_VALLEYVIEW(dev)) {
6789                 int found;
6790
6791                 if (I915_READ(SDVOB) & PORT_DETECTED) {
6792                         /* SDVOB multiplex with HDMIB */
6793                         found = intel_sdvo_init(dev, SDVOB, true);
6794                         if (!found)
6795                                 intel_hdmi_init(dev, SDVOB);
6796                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
6797                                 intel_dp_init(dev, DP_B);
6798                 }
6799
6800                 if (I915_READ(SDVOC) & PORT_DETECTED)
6801                         intel_hdmi_init(dev, SDVOC);
6802
6803                 /* Shares lanes with HDMI on SDVOC */
6804                 if (I915_READ(DP_C) & DP_DETECTED)
6805                         intel_dp_init(dev, DP_C);
6806         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6807                 bool found = false;
6808
6809                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6810                         DRM_DEBUG_KMS("probing SDVOB\n");
6811                         found = intel_sdvo_init(dev, SDVOB, true);
6812                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6813                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6814                                 intel_hdmi_init(dev, SDVOB);
6815                         }
6816
6817                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6818                                 DRM_DEBUG_KMS("probing DP_B\n");
6819                                 intel_dp_init(dev, DP_B);
6820                         }
6821                 }
6822
6823                 /* Before G4X SDVOC doesn't have its own detect register */
6824
6825                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6826                         DRM_DEBUG_KMS("probing SDVOC\n");
6827                         found = intel_sdvo_init(dev, SDVOC, false);
6828                 }
6829
6830                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6831
6832                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6833                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6834                                 intel_hdmi_init(dev, SDVOC);
6835                         }
6836                         if (SUPPORTS_INTEGRATED_DP(dev)) {
6837                                 DRM_DEBUG_KMS("probing DP_C\n");
6838                                 intel_dp_init(dev, DP_C);
6839                         }
6840                 }
6841
6842                 if (SUPPORTS_INTEGRATED_DP(dev) &&
6843                     (I915_READ(DP_D) & DP_DETECTED)) {
6844                         DRM_DEBUG_KMS("probing DP_D\n");
6845                         intel_dp_init(dev, DP_D);
6846                 }
6847         } else if (IS_GEN2(dev))
6848                 intel_dvo_init(dev);
6849
6850         if (SUPPORTS_TV(dev))
6851                 intel_tv_init(dev);
6852
6853         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6854                 encoder->base.possible_crtcs = encoder->crtc_mask;
6855                 encoder->base.possible_clones =
6856                         intel_encoder_clones(dev, encoder->clone_mask);
6857         }
6858
6859         /* disable all the possible outputs/crtcs before entering KMS mode */
6860         drm_helper_disable_unused_functions(dev);
6861
6862         if (HAS_PCH_SPLIT(dev))
6863                 ironlake_init_pch_refclk(dev);
6864 }
6865
6866 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6867 {
6868         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6869
6870         drm_framebuffer_cleanup(fb);
6871         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6872
6873         kfree(intel_fb);
6874 }
6875
6876 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6877                                                 struct drm_file *file,
6878                                                 unsigned int *handle)
6879 {
6880         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6881         struct drm_i915_gem_object *obj = intel_fb->obj;
6882
6883         return drm_gem_handle_create(file, &obj->base, handle);
6884 }
6885
6886 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6887         .destroy = intel_user_framebuffer_destroy,
6888         .create_handle = intel_user_framebuffer_create_handle,
6889 };
6890
6891 int intel_framebuffer_init(struct drm_device *dev,
6892                            struct intel_framebuffer *intel_fb,
6893                            struct drm_mode_fb_cmd2 *mode_cmd,
6894                            struct drm_i915_gem_object *obj)
6895 {
6896         int ret;
6897
6898         if (obj->tiling_mode == I915_TILING_Y)
6899                 return -EINVAL;
6900
6901         if (mode_cmd->pitches[0] & 63)
6902                 return -EINVAL;
6903
6904         switch (mode_cmd->pixel_format) {
6905         case DRM_FORMAT_RGB332:
6906         case DRM_FORMAT_RGB565:
6907         case DRM_FORMAT_XRGB8888:
6908         case DRM_FORMAT_XBGR8888:
6909         case DRM_FORMAT_ARGB8888:
6910         case DRM_FORMAT_XRGB2101010:
6911         case DRM_FORMAT_ARGB2101010:
6912                 /* RGB formats are common across chipsets */
6913                 break;
6914         case DRM_FORMAT_YUYV:
6915         case DRM_FORMAT_UYVY:
6916         case DRM_FORMAT_YVYU:
6917         case DRM_FORMAT_VYUY:
6918                 break;
6919         default:
6920                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6921                                 mode_cmd->pixel_format);
6922                 return -EINVAL;
6923         }
6924
6925         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6926         if (ret) {
6927                 DRM_ERROR("framebuffer init failed %d\n", ret);
6928                 return ret;
6929         }
6930
6931         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6932         intel_fb->obj = obj;
6933         return 0;
6934 }
6935
6936 static struct drm_framebuffer *
6937 intel_user_framebuffer_create(struct drm_device *dev,
6938                               struct drm_file *filp,
6939                               struct drm_mode_fb_cmd2 *mode_cmd)
6940 {
6941         struct drm_i915_gem_object *obj;
6942
6943         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6944                                                 mode_cmd->handles[0]));
6945         if (&obj->base == NULL)
6946                 return ERR_PTR(-ENOENT);
6947
6948         return intel_framebuffer_create(dev, mode_cmd, obj);
6949 }
6950
6951 static const struct drm_mode_config_funcs intel_mode_funcs = {
6952         .fb_create = intel_user_framebuffer_create,
6953         .output_poll_changed = intel_fb_output_poll_changed,
6954 };
6955
6956 /* Set up chip specific display functions */
6957 static void intel_init_display(struct drm_device *dev)
6958 {
6959         struct drm_i915_private *dev_priv = dev->dev_private;
6960
6961         /* We always want a DPMS function */
6962         if (HAS_PCH_SPLIT(dev)) {
6963                 dev_priv->display.dpms = ironlake_crtc_dpms;
6964                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6965                 dev_priv->display.off = ironlake_crtc_off;
6966                 dev_priv->display.update_plane = ironlake_update_plane;
6967         } else {
6968                 dev_priv->display.dpms = i9xx_crtc_dpms;
6969                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6970                 dev_priv->display.off = i9xx_crtc_off;
6971                 dev_priv->display.update_plane = i9xx_update_plane;
6972         }
6973
6974         /* Returns the core display clock speed */
6975         if (IS_VALLEYVIEW(dev))
6976                 dev_priv->display.get_display_clock_speed =
6977                         valleyview_get_display_clock_speed;
6978         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6979                 dev_priv->display.get_display_clock_speed =
6980                         i945_get_display_clock_speed;
6981         else if (IS_I915G(dev))
6982                 dev_priv->display.get_display_clock_speed =
6983                         i915_get_display_clock_speed;
6984         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6985                 dev_priv->display.get_display_clock_speed =
6986                         i9xx_misc_get_display_clock_speed;
6987         else if (IS_I915GM(dev))
6988                 dev_priv->display.get_display_clock_speed =
6989                         i915gm_get_display_clock_speed;
6990         else if (IS_I865G(dev))
6991                 dev_priv->display.get_display_clock_speed =
6992                         i865_get_display_clock_speed;
6993         else if (IS_I85X(dev))
6994                 dev_priv->display.get_display_clock_speed =
6995                         i855_get_display_clock_speed;
6996         else /* 852, 830 */
6997                 dev_priv->display.get_display_clock_speed =
6998                         i830_get_display_clock_speed;
6999
7000         if (HAS_PCH_SPLIT(dev)) {
7001                 if (IS_GEN5(dev)) {
7002                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7003                         dev_priv->display.write_eld = ironlake_write_eld;
7004                 } else if (IS_GEN6(dev)) {
7005                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7006                         dev_priv->display.write_eld = ironlake_write_eld;
7007                 } else if (IS_IVYBRIDGE(dev)) {
7008                         /* FIXME: detect B0+ stepping and use auto training */
7009                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7010                         dev_priv->display.write_eld = ironlake_write_eld;
7011                 } else if (IS_HASWELL(dev)) {
7012                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7013                         dev_priv->display.write_eld = ironlake_write_eld;
7014                 } else
7015                         dev_priv->display.update_wm = NULL;
7016         } else if (IS_VALLEYVIEW(dev)) {
7017                 dev_priv->display.force_wake_get = vlv_force_wake_get;
7018                 dev_priv->display.force_wake_put = vlv_force_wake_put;
7019         } else if (IS_G4X(dev)) {
7020                 dev_priv->display.write_eld = g4x_write_eld;
7021         }
7022
7023         /* Default just returns -ENODEV to indicate unsupported */
7024         dev_priv->display.queue_flip = intel_default_queue_flip;
7025
7026         switch (INTEL_INFO(dev)->gen) {
7027         case 2:
7028                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7029                 break;
7030
7031         case 3:
7032                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7033                 break;
7034
7035         case 4:
7036         case 5:
7037                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7038                 break;
7039
7040         case 6:
7041                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7042                 break;
7043         case 7:
7044                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7045                 break;
7046         }
7047 }
7048
7049 /*
7050  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7051  * resume, or other times.  This quirk makes sure that's the case for
7052  * affected systems.
7053  */
7054 static void quirk_pipea_force(struct drm_device *dev)
7055 {
7056         struct drm_i915_private *dev_priv = dev->dev_private;
7057
7058         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7059         DRM_INFO("applying pipe a force quirk\n");
7060 }
7061
7062 /*
7063  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7064  */
7065 static void quirk_ssc_force_disable(struct drm_device *dev)
7066 {
7067         struct drm_i915_private *dev_priv = dev->dev_private;
7068         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7069         DRM_INFO("applying lvds SSC disable quirk\n");
7070 }
7071
7072 /*
7073  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7074  * brightness value
7075  */
7076 static void quirk_invert_brightness(struct drm_device *dev)
7077 {
7078         struct drm_i915_private *dev_priv = dev->dev_private;
7079         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7080         DRM_INFO("applying inverted panel brightness quirk\n");
7081 }
7082
7083 struct intel_quirk {
7084         int device;
7085         int subsystem_vendor;
7086         int subsystem_device;
7087         void (*hook)(struct drm_device *dev);
7088 };
7089
7090 static struct intel_quirk intel_quirks[] = {
7091         /* HP Mini needs pipe A force quirk (LP: #322104) */
7092         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7093
7094         /* Thinkpad R31 needs pipe A force quirk */
7095         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7096         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7097         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7098
7099         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7100         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
7101         /* ThinkPad X40 needs pipe A force quirk */
7102
7103         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7104         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7105
7106         /* 855 & before need to leave pipe A & dpll A up */
7107         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7108         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7109
7110         /* Lenovo U160 cannot use SSC on LVDS */
7111         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7112
7113         /* Sony Vaio Y cannot use SSC on LVDS */
7114         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7115
7116         /* Acer Aspire 5734Z must invert backlight brightness */
7117         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7118 };
7119
7120 static void intel_init_quirks(struct drm_device *dev)
7121 {
7122         struct pci_dev *d = dev->pdev;
7123         int i;
7124
7125         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7126                 struct intel_quirk *q = &intel_quirks[i];
7127
7128                 if (d->device == q->device &&
7129                     (d->subsystem_vendor == q->subsystem_vendor ||
7130                      q->subsystem_vendor == PCI_ANY_ID) &&
7131                     (d->subsystem_device == q->subsystem_device ||
7132                      q->subsystem_device == PCI_ANY_ID))
7133                         q->hook(dev);
7134         }
7135 }
7136
7137 /* Disable the VGA plane that we never use */
7138 static void i915_disable_vga(struct drm_device *dev)
7139 {
7140         struct drm_i915_private *dev_priv = dev->dev_private;
7141         u8 sr1;
7142         u32 vga_reg;
7143
7144         if (HAS_PCH_SPLIT(dev))
7145                 vga_reg = CPU_VGACNTRL;
7146         else
7147                 vga_reg = VGACNTRL;
7148
7149         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7150         outb(SR01, VGA_SR_INDEX);
7151         sr1 = inb(VGA_SR_DATA);
7152         outb(sr1 | 1<<5, VGA_SR_DATA);
7153         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7154         udelay(300);
7155
7156         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7157         POSTING_READ(vga_reg);
7158 }
7159
7160 static void ivb_pch_pwm_override(struct drm_device *dev)
7161 {
7162         struct drm_i915_private *dev_priv = dev->dev_private;
7163
7164         /*
7165          * IVB has CPU eDP backlight regs too, set things up to let the
7166          * PCH regs control the backlight
7167          */
7168         I915_WRITE(BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE);
7169         I915_WRITE(BLC_PWM_CPU_CTL, 0);
7170         I915_WRITE(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE | BLM_PCH_OVERRIDE_ENABLE);
7171 }
7172
7173 void intel_modeset_init_hw(struct drm_device *dev)
7174 {
7175         struct drm_i915_private *dev_priv = dev->dev_private;
7176
7177         intel_init_clock_gating(dev);
7178
7179         if (IS_IRONLAKE_M(dev)) {
7180                 ironlake_enable_drps(dev);
7181                 ironlake_enable_rc6(dev);
7182                 intel_init_emon(dev);
7183         }
7184
7185         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
7186                 gen6_enable_rps(dev_priv);
7187                 gen6_update_ring_freq(dev_priv);
7188         }
7189
7190         if (IS_IVYBRIDGE(dev))
7191                 ivb_pch_pwm_override(dev);
7192 }
7193
7194 void intel_modeset_init(struct drm_device *dev)
7195 {
7196         struct drm_i915_private *dev_priv = dev->dev_private;
7197         int i, ret;
7198
7199         drm_mode_config_init(dev);
7200
7201         dev->mode_config.min_width = 0;
7202         dev->mode_config.min_height = 0;
7203
7204         dev->mode_config.preferred_depth = 24;
7205         dev->mode_config.prefer_shadow = 1;
7206
7207         dev->mode_config.funcs = &intel_mode_funcs;
7208
7209         intel_init_quirks(dev);
7210
7211         intel_init_pm(dev);
7212
7213         intel_prepare_ddi(dev);
7214
7215         intel_init_display(dev);
7216
7217         if (IS_GEN2(dev)) {
7218                 dev->mode_config.max_width = 2048;
7219                 dev->mode_config.max_height = 2048;
7220         } else if (IS_GEN3(dev)) {
7221                 dev->mode_config.max_width = 4096;
7222                 dev->mode_config.max_height = 4096;
7223         } else {
7224                 dev->mode_config.max_width = 8192;
7225                 dev->mode_config.max_height = 8192;
7226         }
7227         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7228
7229         DRM_DEBUG_KMS("%d display pipe%s available.\n",
7230                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7231
7232         for (i = 0; i < dev_priv->num_pipe; i++) {
7233                 intel_crtc_init(dev, i);
7234                 ret = intel_plane_init(dev, i);
7235                 if (ret)
7236                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7237         }
7238
7239         intel_pch_pll_init(dev);
7240
7241         /* Just disable it once at startup */
7242         i915_disable_vga(dev);
7243         intel_setup_outputs(dev);
7244
7245         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7246         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7247                     (unsigned long)dev);
7248 }
7249
7250 void intel_modeset_gem_init(struct drm_device *dev)
7251 {
7252         intel_modeset_init_hw(dev);
7253
7254         intel_setup_overlay(dev);
7255 }
7256
7257 void intel_modeset_cleanup(struct drm_device *dev)
7258 {
7259         struct drm_i915_private *dev_priv = dev->dev_private;
7260         struct drm_crtc *crtc;
7261         struct intel_crtc *intel_crtc;
7262
7263         drm_kms_helper_poll_fini(dev);
7264         mutex_lock(&dev->struct_mutex);
7265
7266         intel_unregister_dsm_handler();
7267
7268
7269         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7270                 /* Skip inactive CRTCs */
7271                 if (!crtc->fb)
7272                         continue;
7273
7274                 intel_crtc = to_intel_crtc(crtc);
7275                 intel_increase_pllclock(crtc);
7276         }
7277
7278         intel_disable_fbc(dev);
7279
7280         if (IS_IRONLAKE_M(dev))
7281                 ironlake_disable_drps(dev);
7282         if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
7283                 gen6_disable_rps(dev);
7284
7285         if (IS_IRONLAKE_M(dev))
7286                 ironlake_disable_rc6(dev);
7287
7288         if (IS_VALLEYVIEW(dev))
7289                 vlv_init_dpio(dev);
7290
7291         mutex_unlock(&dev->struct_mutex);
7292
7293         /* Disable the irq before mode object teardown, for the irq might
7294          * enqueue unpin/hotplug work. */
7295         drm_irq_uninstall(dev);
7296         cancel_work_sync(&dev_priv->hotplug_work);
7297         cancel_work_sync(&dev_priv->rps_work);
7298
7299         /* flush any delayed tasks or pending work */
7300         flush_scheduled_work();
7301
7302         /* Shut off idle work before the crtcs get freed. */
7303         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7304                 intel_crtc = to_intel_crtc(crtc);
7305                 del_timer_sync(&intel_crtc->idle_timer);
7306         }
7307         del_timer_sync(&dev_priv->idle_timer);
7308         cancel_work_sync(&dev_priv->idle_work);
7309
7310         drm_mode_config_cleanup(dev);
7311 }
7312
7313 /*
7314  * Return which encoder is currently attached for connector.
7315  */
7316 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7317 {
7318         return &intel_attached_encoder(connector)->base;
7319 }
7320
7321 void intel_connector_attach_encoder(struct intel_connector *connector,
7322                                     struct intel_encoder *encoder)
7323 {
7324         connector->encoder = encoder;
7325         drm_mode_connector_attach_encoder(&connector->base,
7326                                           &encoder->base);
7327 }
7328
7329 /*
7330  * set vga decode state - true == enable VGA decode
7331  */
7332 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7333 {
7334         struct drm_i915_private *dev_priv = dev->dev_private;
7335         u16 gmch_ctrl;
7336
7337         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7338         if (state)
7339                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7340         else
7341                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7342         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7343         return 0;
7344 }
7345
7346 #ifdef CONFIG_DEBUG_FS
7347 #include <linux/seq_file.h>
7348
7349 struct intel_display_error_state {
7350         struct intel_cursor_error_state {
7351                 u32 control;
7352                 u32 position;
7353                 u32 base;
7354                 u32 size;
7355         } cursor[2];
7356
7357         struct intel_pipe_error_state {
7358                 u32 conf;
7359                 u32 source;
7360
7361                 u32 htotal;
7362                 u32 hblank;
7363                 u32 hsync;
7364                 u32 vtotal;
7365                 u32 vblank;
7366                 u32 vsync;
7367         } pipe[2];
7368
7369         struct intel_plane_error_state {
7370                 u32 control;
7371                 u32 stride;
7372                 u32 size;
7373                 u32 pos;
7374                 u32 addr;
7375                 u32 surface;
7376                 u32 tile_offset;
7377         } plane[2];
7378 };
7379
7380 struct intel_display_error_state *
7381 intel_display_capture_error_state(struct drm_device *dev)
7382 {
7383         drm_i915_private_t *dev_priv = dev->dev_private;
7384         struct intel_display_error_state *error;
7385         int i;
7386
7387         error = kmalloc(sizeof(*error), GFP_ATOMIC);
7388         if (error == NULL)
7389                 return NULL;
7390
7391         for (i = 0; i < 2; i++) {
7392                 error->cursor[i].control = I915_READ(CURCNTR(i));
7393                 error->cursor[i].position = I915_READ(CURPOS(i));
7394                 error->cursor[i].base = I915_READ(CURBASE(i));
7395
7396                 error->plane[i].control = I915_READ(DSPCNTR(i));
7397                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7398                 error->plane[i].size = I915_READ(DSPSIZE(i));
7399                 error->plane[i].pos = I915_READ(DSPPOS(i));
7400                 error->plane[i].addr = I915_READ(DSPADDR(i));
7401                 if (INTEL_INFO(dev)->gen >= 4) {
7402                         error->plane[i].surface = I915_READ(DSPSURF(i));
7403                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7404                 }
7405
7406                 error->pipe[i].conf = I915_READ(PIPECONF(i));
7407                 error->pipe[i].source = I915_READ(PIPESRC(i));
7408                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7409                 error->pipe[i].hblank = I915_READ(HBLANK(i));
7410                 error->pipe[i].hsync = I915_READ(HSYNC(i));
7411                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7412                 error->pipe[i].vblank = I915_READ(VBLANK(i));
7413                 error->pipe[i].vsync = I915_READ(VSYNC(i));
7414         }
7415
7416         return error;
7417 }
7418
7419 void
7420 intel_display_print_error_state(struct seq_file *m,
7421                                 struct drm_device *dev,
7422                                 struct intel_display_error_state *error)
7423 {
7424         int i;
7425
7426         for (i = 0; i < 2; i++) {
7427                 seq_printf(m, "Pipe [%d]:\n", i);
7428                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
7429                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
7430                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
7431                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
7432                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
7433                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
7434                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
7435                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
7436
7437                 seq_printf(m, "Plane [%d]:\n", i);
7438                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
7439                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
7440                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
7441                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
7442                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
7443                 if (INTEL_INFO(dev)->gen >= 4) {
7444                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
7445                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
7446                 }
7447
7448                 seq_printf(m, "Cursor [%d]:\n", i);
7449                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
7450                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
7451                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
7452         }
7453 }
7454 #endif