2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
62 #define INTEL_P2_NUM 2
63 typedef struct intel_limit intel_limit_t;
65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
73 intel_pch_rawclk(struct drm_device *dev)
75 struct drm_i915_private *dev_priv = dev->dev_private;
77 WARN_ON(!HAS_PCH_SPLIT(dev));
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
82 static inline u32 /* units of 100MHz */
83 intel_fdi_link_freq(struct drm_device *dev)
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
92 static const intel_limit_t intel_limits_i8xx_dvo = {
93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
105 static const intel_limit_t intel_limits_i8xx_lvds = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 1, .max = 6 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 14, .p2_fast = 7 },
118 static const intel_limit_t intel_limits_i9xx_sdvo = {
119 .dot = { .min = 20000, .max = 400000 },
120 .vco = { .min = 1400000, .max = 2800000 },
121 .n = { .min = 1, .max = 6 },
122 .m = { .min = 70, .max = 120 },
123 .m1 = { .min = 8, .max = 18 },
124 .m2 = { .min = 3, .max = 7 },
125 .p = { .min = 5, .max = 80 },
126 .p1 = { .min = 1, .max = 8 },
127 .p2 = { .dot_limit = 200000,
128 .p2_slow = 10, .p2_fast = 5 },
131 static const intel_limit_t intel_limits_i9xx_lvds = {
132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
138 .p = { .min = 7, .max = 98 },
139 .p1 = { .min = 1, .max = 8 },
140 .p2 = { .dot_limit = 112000,
141 .p2_slow = 14, .p2_fast = 7 },
145 static const intel_limit_t intel_limits_g4x_sdvo = {
146 .dot = { .min = 25000, .max = 270000 },
147 .vco = { .min = 1750000, .max = 3500000},
148 .n = { .min = 1, .max = 4 },
149 .m = { .min = 104, .max = 138 },
150 .m1 = { .min = 17, .max = 23 },
151 .m2 = { .min = 5, .max = 11 },
152 .p = { .min = 10, .max = 30 },
153 .p1 = { .min = 1, .max = 3},
154 .p2 = { .dot_limit = 270000,
160 static const intel_limit_t intel_limits_g4x_hdmi = {
161 .dot = { .min = 22000, .max = 400000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 16, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 5, .max = 80 },
168 .p1 = { .min = 1, .max = 8},
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 10, .p2_fast = 5 },
173 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
174 .dot = { .min = 20000, .max = 115000 },
175 .vco = { .min = 1750000, .max = 3500000 },
176 .n = { .min = 1, .max = 3 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 28, .max = 112 },
181 .p1 = { .min = 2, .max = 8 },
182 .p2 = { .dot_limit = 0,
183 .p2_slow = 14, .p2_fast = 14
187 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
188 .dot = { .min = 80000, .max = 224000 },
189 .vco = { .min = 1750000, .max = 3500000 },
190 .n = { .min = 1, .max = 3 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 17, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 14, .max = 42 },
195 .p1 = { .min = 2, .max = 6 },
196 .p2 = { .dot_limit = 0,
197 .p2_slow = 7, .p2_fast = 7
201 static const intel_limit_t intel_limits_pineview_sdvo = {
202 .dot = { .min = 20000, .max = 400000},
203 .vco = { .min = 1700000, .max = 3500000 },
204 /* Pineview's Ncounter is a ring counter */
205 .n = { .min = 3, .max = 6 },
206 .m = { .min = 2, .max = 256 },
207 /* Pineview only has one combined m divider, which we treat as m2. */
208 .m1 = { .min = 0, .max = 0 },
209 .m2 = { .min = 0, .max = 254 },
210 .p = { .min = 5, .max = 80 },
211 .p1 = { .min = 1, .max = 8 },
212 .p2 = { .dot_limit = 200000,
213 .p2_slow = 10, .p2_fast = 5 },
216 static const intel_limit_t intel_limits_pineview_lvds = {
217 .dot = { .min = 20000, .max = 400000 },
218 .vco = { .min = 1700000, .max = 3500000 },
219 .n = { .min = 3, .max = 6 },
220 .m = { .min = 2, .max = 256 },
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 7, .max = 112 },
224 .p1 = { .min = 1, .max = 8 },
225 .p2 = { .dot_limit = 112000,
226 .p2_slow = 14, .p2_fast = 14 },
229 /* Ironlake / Sandybridge
231 * We calculate clock using (register_value + 2) for N/M1/M2, so here
232 * the range value for them is (actual_value - 2).
234 static const intel_limit_t intel_limits_ironlake_dac = {
235 .dot = { .min = 25000, .max = 350000 },
236 .vco = { .min = 1760000, .max = 3510000 },
237 .n = { .min = 1, .max = 5 },
238 .m = { .min = 79, .max = 127 },
239 .m1 = { .min = 12, .max = 22 },
240 .m2 = { .min = 5, .max = 9 },
241 .p = { .min = 5, .max = 80 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 225000,
244 .p2_slow = 10, .p2_fast = 5 },
247 static const intel_limit_t intel_limits_ironlake_single_lvds = {
248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 79, .max = 118 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 28, .max = 112 },
255 .p1 = { .min = 2, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 14, .p2_fast = 14 },
260 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 127 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 14, .max = 56 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 7, .p2_fast = 7 },
273 /* LVDS 100mhz refclk limits. */
274 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 2 },
278 .m = { .min = 79, .max = 126 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
287 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 42 },
295 .p1 = { .min = 2, .max = 6 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
300 static const intel_limit_t intel_limits_vlv_dac = {
301 .dot = { .min = 25000, .max = 270000 },
302 .vco = { .min = 4000000, .max = 6000000 },
303 .n = { .min = 1, .max = 7 },
304 .m = { .min = 22, .max = 450 }, /* guess */
305 .m1 = { .min = 2, .max = 3 },
306 .m2 = { .min = 11, .max = 156 },
307 .p = { .min = 10, .max = 30 },
308 .p1 = { .min = 1, .max = 3 },
309 .p2 = { .dot_limit = 270000,
310 .p2_slow = 2, .p2_fast = 20 },
313 static const intel_limit_t intel_limits_vlv_hdmi = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 60, .max = 300 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 2, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
326 static const intel_limit_t intel_limits_vlv_dp = {
327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 22, .max = 450 },
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 1, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
342 struct drm_device *dev = crtc->dev;
343 const intel_limit_t *limit;
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
346 if (intel_is_dual_link_lvds(dev)) {
347 if (refclk == 100000)
348 limit = &intel_limits_ironlake_dual_lvds_100m;
350 limit = &intel_limits_ironlake_dual_lvds;
352 if (refclk == 100000)
353 limit = &intel_limits_ironlake_single_lvds_100m;
355 limit = &intel_limits_ironlake_single_lvds;
358 limit = &intel_limits_ironlake_dac;
363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
365 struct drm_device *dev = crtc->dev;
366 const intel_limit_t *limit;
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
369 if (intel_is_dual_link_lvds(dev))
370 limit = &intel_limits_g4x_dual_channel_lvds;
372 limit = &intel_limits_g4x_single_channel_lvds;
373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
375 limit = &intel_limits_g4x_hdmi;
376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
377 limit = &intel_limits_g4x_sdvo;
378 } else /* The option is for other outputs */
379 limit = &intel_limits_i9xx_sdvo;
384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
389 if (HAS_PCH_SPLIT(dev))
390 limit = intel_ironlake_limit(crtc, refclk);
391 else if (IS_G4X(dev)) {
392 limit = intel_g4x_limit(crtc);
393 } else if (IS_PINEVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
395 limit = &intel_limits_pineview_lvds;
397 limit = &intel_limits_pineview_sdvo;
398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
402 limit = &intel_limits_vlv_hdmi;
404 limit = &intel_limits_vlv_dp;
405 } else if (!IS_GEN2(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i9xx_lvds;
409 limit = &intel_limits_i9xx_sdvo;
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
412 limit = &intel_limits_i8xx_lvds;
414 limit = &intel_limits_i8xx_dvo;
419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
420 static void pineview_clock(int refclk, intel_clock_t *clock)
422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
433 static void i9xx_clock(int refclk, intel_clock_t *clock)
435 clock->m = i9xx_dpll_compute_m(clock);
436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
442 * Returns whether any output on the specified pipe is of the specified type
444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
446 struct drm_device *dev = crtc->dev;
447 struct intel_encoder *encoder;
449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
467 INTELPllInvalid("p1 out of range\n");
468 if (clock->p < limit->p.min || limit->p.max < clock->p)
469 INTELPllInvalid("p out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
475 INTELPllInvalid("m1 <= m2\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 if (clock->n < limit->n.min || limit->n.max < clock->n)
479 INTELPllInvalid("n out of range\n");
480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
481 INTELPllInvalid("vco out of range\n");
482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
486 INTELPllInvalid("dot out of range\n");
492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
496 struct drm_device *dev = crtc->dev;
500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
506 if (intel_is_dual_link_lvds(dev))
507 clock.p2 = limit->p2.p2_fast;
509 clock.p2 = limit->p2.p2_slow;
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
514 clock.p2 = limit->p2.p2_fast;
517 memset(best_clock, 0, sizeof(*best_clock));
519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
523 if (clock.m2 >= clock.m1)
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
536 clock.p != match_clock->p)
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
549 return (err != target);
553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
557 struct drm_device *dev = crtc->dev;
561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
567 if (intel_is_dual_link_lvds(dev))
568 clock.p2 = limit->p2.p2_fast;
570 clock.p2 = limit->p2.p2_slow;
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
575 clock.p2 = limit->p2.p2_fast;
578 memset(best_clock, 0, sizeof(*best_clock));
580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
590 pineview_clock(refclk, &clock);
591 if (!intel_PLL_is_valid(dev, limit,
595 clock.p != match_clock->p)
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
608 return (err != target);
612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
616 struct drm_device *dev = crtc->dev;
620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
625 if (intel_is_dual_link_lvds(dev))
626 clock.p2 = limit->p2.p2_fast;
628 clock.p2 = limit->p2.p2_slow;
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
633 clock.p2 = limit->p2.p2_fast;
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
638 /* based on hardware requirement, prefer smaller n to precision */
639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
640 /* based on hardware requirement, prefere larger m1,m2 */
641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
649 i9xx_clock(refclk, &clock);
650 if (!intel_PLL_is_valid(dev, limit,
654 this_err = abs(clock.dot - target);
655 if (this_err < err_most) {
669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
675 u32 updrate, minupdate, fracbits, p;
676 unsigned long bestppm, ppm, absppm;
680 dotclk = target * 1000;
683 fastclk = dotclk / (2*100);
687 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
688 bestm1 = bestm2 = bestp1 = bestp2 = 0;
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
692 updrate = refclk / n;
693 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
694 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
698 /* based on hardware requirement, prefer bigger m1,m2 values */
699 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
700 m2 = (((2*(fastclk * p * n / m1 )) +
701 refclk) / (2*refclk));
704 if (vco >= limit->vco.min && vco < limit->vco.max) {
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
711 if (absppm < bestppm - 10) {
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
737 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743 return intel_crtc->config.cpu_transcoder;
746 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 u32 frame, frame_reg = PIPEFRAME(pipe);
751 frame = I915_READ(frame_reg);
753 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
754 DRM_DEBUG_KMS("vblank wait timed out\n");
758 * intel_wait_for_vblank - wait for vblank on a given pipe
760 * @pipe: pipe to wait for
762 * Wait for vblank to occur on a given pipe. Needed for various bits of
765 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
767 struct drm_i915_private *dev_priv = dev->dev_private;
768 int pipestat_reg = PIPESTAT(pipe);
770 if (INTEL_INFO(dev)->gen >= 5) {
771 ironlake_wait_for_vblank(dev, pipe);
775 /* Clear existing vblank status. Note this will clear any other
776 * sticky status fields as well.
778 * This races with i915_driver_irq_handler() with the result
779 * that either function could miss a vblank event. Here it is not
780 * fatal, as we will either wait upon the next vblank interrupt or
781 * timeout. Generally speaking intel_wait_for_vblank() is only
782 * called during modeset at which time the GPU should be idle and
783 * should *not* be performing page flips and thus not waiting on
785 * Currently, the result of us stealing a vblank from the irq
786 * handler is that a single frame will be skipped during swapbuffers.
788 I915_WRITE(pipestat_reg,
789 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
791 /* Wait for vblank interrupt bit to set */
792 if (wait_for(I915_READ(pipestat_reg) &
793 PIPE_VBLANK_INTERRUPT_STATUS,
795 DRM_DEBUG_KMS("vblank wait timed out\n");
799 * intel_wait_for_pipe_off - wait for pipe to turn off
801 * @pipe: pipe to wait for
803 * After disabling a pipe, we can't wait for vblank in the usual way,
804 * spinning on the vblank interrupt status bit, since we won't actually
805 * see an interrupt when the pipe is disabled.
808 * wait for the pipe register state bit to turn off
811 * wait for the display line value to settle (it usually
812 * ends up stopping at the start of the next frame).
815 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
817 struct drm_i915_private *dev_priv = dev->dev_private;
818 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
821 if (INTEL_INFO(dev)->gen >= 4) {
822 int reg = PIPECONF(cpu_transcoder);
824 /* Wait for the Pipe State to go off */
825 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
827 WARN(1, "pipe_off wait timed out\n");
829 u32 last_line, line_mask;
830 int reg = PIPEDSL(pipe);
831 unsigned long timeout = jiffies + msecs_to_jiffies(100);
834 line_mask = DSL_LINEMASK_GEN2;
836 line_mask = DSL_LINEMASK_GEN3;
838 /* Wait for the display line to settle */
840 last_line = I915_READ(reg) & line_mask;
842 } while (((I915_READ(reg) & line_mask) != last_line) &&
843 time_after(timeout, jiffies));
844 if (time_after(jiffies, timeout))
845 WARN(1, "pipe_off wait timed out\n");
850 * ibx_digital_port_connected - is the specified port connected?
851 * @dev_priv: i915 private structure
852 * @port: the port to test
854 * Returns true if @port is connected, false otherwise.
856 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
857 struct intel_digital_port *port)
861 if (HAS_PCH_IBX(dev_priv->dev)) {
864 bit = SDE_PORTB_HOTPLUG;
867 bit = SDE_PORTC_HOTPLUG;
870 bit = SDE_PORTD_HOTPLUG;
878 bit = SDE_PORTB_HOTPLUG_CPT;
881 bit = SDE_PORTC_HOTPLUG_CPT;
884 bit = SDE_PORTD_HOTPLUG_CPT;
891 return I915_READ(SDEISR) & bit;
894 static const char *state_string(bool enabled)
896 return enabled ? "on" : "off";
899 /* Only for pre-ILK configs */
900 void assert_pll(struct drm_i915_private *dev_priv,
901 enum pipe pipe, bool state)
908 val = I915_READ(reg);
909 cur_state = !!(val & DPLL_VCO_ENABLE);
910 WARN(cur_state != state,
911 "PLL state assertion failure (expected %s, current %s)\n",
912 state_string(state), state_string(cur_state));
915 struct intel_shared_dpll *
916 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
918 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
920 if (crtc->config.shared_dpll < 0)
923 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
927 void assert_shared_dpll(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll,
932 struct intel_dpll_hw_state hw_state;
934 if (HAS_PCH_LPT(dev_priv->dev)) {
935 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
940 "asserting DPLL %s with no DPLL\n", state_string(state)))
943 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
944 WARN(cur_state != state,
945 "%s assertion failure (expected %s, current %s)\n",
946 pll->name, state_string(state), state_string(cur_state));
949 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
961 val = I915_READ(reg);
962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
972 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
975 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
989 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
992 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1003 if (HAS_DDI(dev_priv->dev))
1006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1011 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012 enum pipe pipe, bool state)
1018 reg = FDI_RX_CTL(pipe);
1019 val = I915_READ(reg);
1020 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021 WARN(cur_state != state,
1022 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023 state_string(state), state_string(cur_state));
1026 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1029 int pp_reg, lvds_reg;
1031 enum pipe panel_pipe = PIPE_A;
1034 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035 pp_reg = PCH_PP_CONTROL;
1036 lvds_reg = PCH_LVDS;
1038 pp_reg = PP_CONTROL;
1042 val = I915_READ(pp_reg);
1043 if (!(val & PANEL_POWER_ON) ||
1044 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1047 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048 panel_pipe = PIPE_B;
1050 WARN(panel_pipe == pipe && locked,
1051 "panel assertion failure, pipe %c regs locked\n",
1055 void assert_pipe(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
1061 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064 /* if we need the pipe A quirk it must be always on */
1065 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1068 if (!intel_display_power_enabled(dev_priv->dev,
1069 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1072 reg = PIPECONF(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & PIPECONF_ENABLE);
1077 WARN(cur_state != state,
1078 "pipe %c assertion failure (expected %s, current %s)\n",
1079 pipe_name(pipe), state_string(state), state_string(cur_state));
1082 static void assert_plane(struct drm_i915_private *dev_priv,
1083 enum plane plane, bool state)
1089 reg = DSPCNTR(plane);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092 WARN(cur_state != state,
1093 "plane %c assertion failure (expected %s, current %s)\n",
1094 plane_name(plane), state_string(state), state_string(cur_state));
1097 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1100 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1103 struct drm_device *dev = dev_priv->dev;
1108 /* Primary planes are fixed to pipes on gen4+ */
1109 if (INTEL_INFO(dev)->gen >= 4) {
1110 reg = DSPCNTR(pipe);
1111 val = I915_READ(reg);
1112 WARN((val & DISPLAY_PLANE_ENABLE),
1113 "plane %c assertion failure, should be disabled but not\n",
1118 /* Need to check both planes against the pipe */
1119 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1121 val = I915_READ(reg);
1122 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123 DISPPLANE_SEL_PIPE_SHIFT;
1124 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1125 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126 plane_name(i), pipe_name(pipe));
1130 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1133 struct drm_device *dev = dev_priv->dev;
1137 if (IS_VALLEYVIEW(dev)) {
1138 for (i = 0; i < dev_priv->num_plane; i++) {
1139 reg = SPCNTR(pipe, i);
1140 val = I915_READ(reg);
1141 WARN((val & SP_ENABLE),
1142 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 sprite_name(pipe, i), pipe_name(pipe));
1145 } else if (INTEL_INFO(dev)->gen >= 7) {
1147 val = I915_READ(reg);
1148 WARN((val & SPRITE_ENABLE),
1149 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1150 plane_name(pipe), pipe_name(pipe));
1151 } else if (INTEL_INFO(dev)->gen >= 5) {
1152 reg = DVSCNTR(pipe);
1153 val = I915_READ(reg);
1154 WARN((val & DVS_ENABLE),
1155 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1156 plane_name(pipe), pipe_name(pipe));
1160 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1165 if (HAS_PCH_LPT(dev_priv->dev)) {
1166 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1170 val = I915_READ(PCH_DREF_CONTROL);
1171 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172 DREF_SUPERSPREAD_SOURCE_MASK));
1173 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1176 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1183 reg = PCH_TRANSCONF(pipe);
1184 val = I915_READ(reg);
1185 enabled = !!(val & TRANS_ENABLE);
1187 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1191 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, u32 port_sel, u32 val)
1194 if ((val & DP_PORT_EN) == 0)
1197 if (HAS_PCH_CPT(dev_priv->dev)) {
1198 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1203 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, u32 val)
1212 if ((val & SDVO_ENABLE) == 0)
1215 if (HAS_PCH_CPT(dev_priv->dev)) {
1216 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1219 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1225 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1228 if ((val & LVDS_PORT_EN) == 0)
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
1232 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1235 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1244 if ((val & ADPA_DAC_ENABLE) == 0)
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe, int reg, u32 port_sel)
1259 u32 val = I915_READ(reg);
1260 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1261 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1262 reg, pipe_name(pipe));
1264 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265 && (val & DP_PIPEB_SELECT),
1266 "IBX PCH dp port still using transcoder B\n");
1269 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, int reg)
1272 u32 val = I915_READ(reg);
1273 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1274 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1275 reg, pipe_name(pipe));
1277 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1278 && (val & SDVO_PIPE_B_SELECT),
1279 "IBX PCH hdmi port still using transcoder B\n");
1282 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1293 val = I915_READ(reg);
1294 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1295 "PCH VGA enabled on transcoder %c, should be disabled\n",
1299 val = I915_READ(reg);
1300 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1301 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1304 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1309 static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1314 assert_pipe_disabled(dev_priv, pipe);
1316 /* No really, not for ILK+ */
1317 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1319 /* PLL is protected by panel, make sure we can write it */
1320 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321 assert_panel_unlocked(dev_priv, pipe);
1324 val = I915_READ(reg);
1325 val |= DPLL_VCO_ENABLE;
1327 /* We do this three times for luck */
1328 I915_WRITE(reg, val);
1330 udelay(150); /* wait for warmup */
1331 I915_WRITE(reg, val);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1336 udelay(150); /* wait for warmup */
1339 static void i9xx_enable_pll(struct intel_crtc *crtc)
1341 struct drm_device *dev = crtc->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int reg = DPLL(crtc->pipe);
1344 u32 dpll = crtc->config.dpll_hw_state.dpll;
1346 assert_pipe_disabled(dev_priv, crtc->pipe);
1348 /* No really, not for ILK+ */
1349 BUG_ON(dev_priv->info->gen >= 5);
1351 /* PLL is protected by panel, make sure we can write it */
1352 if (IS_MOBILE(dev) && !IS_I830(dev))
1353 assert_panel_unlocked(dev_priv, crtc->pipe);
1355 I915_WRITE(reg, dpll);
1357 /* Wait for the clocks to stabilize. */
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 I915_WRITE(DPLL_MD(crtc->pipe),
1363 crtc->config.dpll_hw_state.dpll_md);
1365 /* The pixel multiplier can only be updated once the
1366 * DPLL is enabled and the clocks are stable.
1368 * So write it again.
1370 I915_WRITE(reg, dpll);
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, dpll);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, dpll);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, dpll);
1382 udelay(150); /* wait for warmup */
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1392 * Note! This is for pre-ILK only.
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1413 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1418 port_mask = DPLL_PORTB_READY_MASK;
1420 port_mask = DPLL_PORTC_READY_MASK;
1422 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424 'B' + port, I915_READ(DPLL(0)));
1428 * ironlake_enable_shared_dpll - enable PCH PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1432 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433 * drives the transcoder clock.
1435 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1437 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1440 /* PCH PLLs only available on ILK, SNB and IVB */
1441 BUG_ON(dev_priv->info->gen < 5);
1442 if (WARN_ON(pll == NULL))
1445 if (WARN_ON(pll->refcount == 0))
1448 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449 pll->name, pll->active, pll->on,
1450 crtc->base.base.id);
1452 if (pll->active++) {
1454 assert_shared_dpll_enabled(dev_priv, pll);
1459 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1460 pll->enable(dev_priv, pll);
1464 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1466 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1469 /* PCH only available on ILK+ */
1470 BUG_ON(dev_priv->info->gen < 5);
1471 if (WARN_ON(pll == NULL))
1474 if (WARN_ON(pll->refcount == 0))
1477 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478 pll->name, pll->active, pll->on,
1479 crtc->base.base.id);
1481 if (WARN_ON(pll->active == 0)) {
1482 assert_shared_dpll_disabled(dev_priv, pll);
1486 assert_shared_dpll_enabled(dev_priv, pll);
1491 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1492 pll->disable(dev_priv, pll);
1496 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1499 struct drm_device *dev = dev_priv->dev;
1500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1502 uint32_t reg, val, pipeconf_val;
1504 /* PCH only available on ILK+ */
1505 BUG_ON(dev_priv->info->gen < 5);
1507 /* Make sure PCH DPLL is enabled */
1508 assert_shared_dpll_enabled(dev_priv,
1509 intel_crtc_to_shared_dpll(intel_crtc));
1511 /* FDI must be feeding us bits for PCH ports */
1512 assert_fdi_tx_enabled(dev_priv, pipe);
1513 assert_fdi_rx_enabled(dev_priv, pipe);
1515 if (HAS_PCH_CPT(dev)) {
1516 /* Workaround: Set the timing override bit before enabling the
1517 * pch transcoder. */
1518 reg = TRANS_CHICKEN2(pipe);
1519 val = I915_READ(reg);
1520 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521 I915_WRITE(reg, val);
1524 reg = PCH_TRANSCONF(pipe);
1525 val = I915_READ(reg);
1526 pipeconf_val = I915_READ(PIPECONF(pipe));
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1533 val &= ~PIPECONF_BPC_MASK;
1534 val |= pipeconf_val & PIPECONF_BPC_MASK;
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1543 val |= TRANS_INTERLACED;
1545 val |= TRANS_PROGRESSIVE;
1547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1549 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1552 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum transcoder cpu_transcoder)
1555 u32 val, pipeconf_val;
1557 /* PCH only available on ILK+ */
1558 BUG_ON(dev_priv->info->gen < 5);
1560 /* FDI must be feeding us bits for PCH ports */
1561 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1562 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1564 /* Workaround: set timing override bit. */
1565 val = I915_READ(_TRANSA_CHICKEN2);
1566 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1567 I915_WRITE(_TRANSA_CHICKEN2, val);
1570 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1572 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573 PIPECONF_INTERLACED_ILK)
1574 val |= TRANS_INTERLACED;
1576 val |= TRANS_PROGRESSIVE;
1578 I915_WRITE(LPT_TRANSCONF, val);
1579 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1580 DRM_ERROR("Failed to enable PCH transcoder\n");
1583 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1586 struct drm_device *dev = dev_priv->dev;
1589 /* FDI relies on the transcoder */
1590 assert_fdi_tx_disabled(dev_priv, pipe);
1591 assert_fdi_rx_disabled(dev_priv, pipe);
1593 /* Ports must be off as well */
1594 assert_pch_ports_disabled(dev_priv, pipe);
1596 reg = PCH_TRANSCONF(pipe);
1597 val = I915_READ(reg);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(reg, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1602 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1604 if (!HAS_PCH_IBX(dev)) {
1605 /* Workaround: Clear the timing override chicken bit again. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1613 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1617 val = I915_READ(LPT_TRANSCONF);
1618 val &= ~TRANS_ENABLE;
1619 I915_WRITE(LPT_TRANSCONF, val);
1620 /* wait for PCH transcoder off, transcoder state */
1621 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1622 DRM_ERROR("Failed to disable PCH transcoder\n");
1624 /* Workaround: clear timing override bit. */
1625 val = I915_READ(_TRANSA_CHICKEN2);
1626 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1627 I915_WRITE(_TRANSA_CHICKEN2, val);
1631 * intel_enable_pipe - enable a pipe, asserting requirements
1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe to enable
1634 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1636 * Enable @pipe, making sure that various hardware specific requirements
1637 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1639 * @pipe should be %PIPE_A or %PIPE_B.
1641 * Will wait until the pipe is actually running (i.e. first vblank) before
1644 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1647 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1649 enum pipe pch_transcoder;
1653 assert_planes_disabled(dev_priv, pipe);
1654 assert_sprites_disabled(dev_priv, pipe);
1656 if (HAS_PCH_LPT(dev_priv->dev))
1657 pch_transcoder = TRANSCODER_A;
1659 pch_transcoder = pipe;
1662 * A pipe without a PLL won't actually be able to drive bits from
1663 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1666 if (!HAS_PCH_SPLIT(dev_priv->dev))
1667 assert_pll_enabled(dev_priv, pipe);
1670 /* if driving the PCH, we need FDI enabled */
1671 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1672 assert_fdi_tx_pll_enabled(dev_priv,
1673 (enum pipe) cpu_transcoder);
1675 /* FIXME: assert CPU port conditions for SNB+ */
1678 reg = PIPECONF(cpu_transcoder);
1679 val = I915_READ(reg);
1680 if (val & PIPECONF_ENABLE)
1683 I915_WRITE(reg, val | PIPECONF_ENABLE);
1684 intel_wait_for_vblank(dev_priv->dev, pipe);
1688 * intel_disable_pipe - disable a pipe, asserting requirements
1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to disable
1692 * Disable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1695 * @pipe should be %PIPE_A or %PIPE_B.
1697 * Will wait until the pipe has shut down before returning.
1699 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1708 * Make sure planes won't keep trying to pump pixels to us,
1709 * or we might hang the display.
1711 assert_planes_disabled(dev_priv, pipe);
1712 assert_sprites_disabled(dev_priv, pipe);
1714 /* Don't disable pipe A or pipe A PLLs if needed */
1715 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1718 reg = PIPECONF(cpu_transcoder);
1719 val = I915_READ(reg);
1720 if ((val & PIPECONF_ENABLE) == 0)
1723 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1724 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1728 * Plane regs are double buffered, going from enabled->disabled needs a
1729 * trigger in order to latch. The display address reg provides this.
1731 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1734 if (dev_priv->info->gen >= 4)
1735 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1737 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1741 * intel_enable_plane - enable a display plane on a given pipe
1742 * @dev_priv: i915 private structure
1743 * @plane: plane to enable
1744 * @pipe: pipe being fed
1746 * Enable @plane on @pipe, making sure that @pipe is running first.
1748 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749 enum plane plane, enum pipe pipe)
1754 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755 assert_pipe_enabled(dev_priv, pipe);
1757 reg = DSPCNTR(plane);
1758 val = I915_READ(reg);
1759 if (val & DISPLAY_PLANE_ENABLE)
1762 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1763 intel_flush_display_plane(dev_priv, plane);
1764 intel_wait_for_vblank(dev_priv->dev, pipe);
1768 * intel_disable_plane - disable a display plane
1769 * @dev_priv: i915 private structure
1770 * @plane: plane to disable
1771 * @pipe: pipe consuming the data
1773 * Disable @plane; should be an independent operation.
1775 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776 enum plane plane, enum pipe pipe)
1781 reg = DSPCNTR(plane);
1782 val = I915_READ(reg);
1783 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1786 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1787 intel_flush_display_plane(dev_priv, plane);
1788 intel_wait_for_vblank(dev_priv->dev, pipe);
1791 static bool need_vtd_wa(struct drm_device *dev)
1793 #ifdef CONFIG_INTEL_IOMMU
1794 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1801 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1802 struct drm_i915_gem_object *obj,
1803 struct intel_ring_buffer *pipelined)
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1809 switch (obj->tiling_mode) {
1810 case I915_TILING_NONE:
1811 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812 alignment = 128 * 1024;
1813 else if (INTEL_INFO(dev)->gen >= 4)
1814 alignment = 4 * 1024;
1816 alignment = 64 * 1024;
1819 /* pin() will align the object as required by fence */
1823 /* Despite that we check this in framebuffer_init userspace can
1824 * screw us over and change the tiling after the fact. Only
1825 * pinned buffers can't change their tiling. */
1826 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1832 /* Note that the w/a also requires 64 PTE of padding following the
1833 * bo. We currently fill all unused PTE with the shadow page and so
1834 * we should always have valid PTE following the scanout preventing
1837 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838 alignment = 256 * 1024;
1840 dev_priv->mm.interruptible = false;
1841 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1843 goto err_interruptible;
1845 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846 * fence, whereas 965+ only requires a fence if using
1847 * framebuffer compression. For simplicity, we always install
1848 * a fence as the cost is not that onerous.
1850 ret = i915_gem_object_get_fence(obj);
1854 i915_gem_object_pin_fence(obj);
1856 dev_priv->mm.interruptible = true;
1860 i915_gem_object_unpin(obj);
1862 dev_priv->mm.interruptible = true;
1866 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1868 i915_gem_object_unpin_fence(obj);
1869 i915_gem_object_unpin(obj);
1872 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873 * is assumed to be a power-of-two. */
1874 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875 unsigned int tiling_mode,
1879 if (tiling_mode != I915_TILING_NONE) {
1880 unsigned int tile_rows, tiles;
1885 tiles = *x / (512/cpp);
1888 return tile_rows * pitch * 8 + tiles * 4096;
1890 unsigned int offset;
1892 offset = *y * pitch + *x * cpp;
1894 *x = (offset & 4095) / cpp;
1895 return offset & -4096;
1899 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 struct intel_framebuffer *intel_fb;
1906 struct drm_i915_gem_object *obj;
1907 int plane = intel_crtc->plane;
1908 unsigned long linear_offset;
1917 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1921 intel_fb = to_intel_framebuffer(fb);
1922 obj = intel_fb->obj;
1924 reg = DSPCNTR(plane);
1925 dspcntr = I915_READ(reg);
1926 /* Mask out pixel format bits in case we change it */
1927 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1928 switch (fb->pixel_format) {
1930 dspcntr |= DISPPLANE_8BPP;
1932 case DRM_FORMAT_XRGB1555:
1933 case DRM_FORMAT_ARGB1555:
1934 dspcntr |= DISPPLANE_BGRX555;
1936 case DRM_FORMAT_RGB565:
1937 dspcntr |= DISPPLANE_BGRX565;
1939 case DRM_FORMAT_XRGB8888:
1940 case DRM_FORMAT_ARGB8888:
1941 dspcntr |= DISPPLANE_BGRX888;
1943 case DRM_FORMAT_XBGR8888:
1944 case DRM_FORMAT_ABGR8888:
1945 dspcntr |= DISPPLANE_RGBX888;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 dspcntr |= DISPPLANE_BGRX101010;
1951 case DRM_FORMAT_XBGR2101010:
1952 case DRM_FORMAT_ABGR2101010:
1953 dspcntr |= DISPPLANE_RGBX101010;
1959 if (INTEL_INFO(dev)->gen >= 4) {
1960 if (obj->tiling_mode != I915_TILING_NONE)
1961 dspcntr |= DISPPLANE_TILED;
1963 dspcntr &= ~DISPPLANE_TILED;
1967 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1969 I915_WRITE(reg, dspcntr);
1971 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1973 if (INTEL_INFO(dev)->gen >= 4) {
1974 intel_crtc->dspaddr_offset =
1975 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976 fb->bits_per_pixel / 8,
1978 linear_offset -= intel_crtc->dspaddr_offset;
1980 intel_crtc->dspaddr_offset = linear_offset;
1983 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1984 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1985 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1986 if (INTEL_INFO(dev)->gen >= 4) {
1987 I915_MODIFY_DISPBASE(DSPSURF(plane),
1988 obj->gtt_offset + intel_crtc->dspaddr_offset);
1989 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1990 I915_WRITE(DSPLINOFF(plane), linear_offset);
1992 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1998 static int ironlake_update_plane(struct drm_crtc *crtc,
1999 struct drm_framebuffer *fb, int x, int y)
2001 struct drm_device *dev = crtc->dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2004 struct intel_framebuffer *intel_fb;
2005 struct drm_i915_gem_object *obj;
2006 int plane = intel_crtc->plane;
2007 unsigned long linear_offset;
2017 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2021 intel_fb = to_intel_framebuffer(fb);
2022 obj = intel_fb->obj;
2024 reg = DSPCNTR(plane);
2025 dspcntr = I915_READ(reg);
2026 /* Mask out pixel format bits in case we change it */
2027 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2028 switch (fb->pixel_format) {
2030 dspcntr |= DISPPLANE_8BPP;
2032 case DRM_FORMAT_RGB565:
2033 dspcntr |= DISPPLANE_BGRX565;
2035 case DRM_FORMAT_XRGB8888:
2036 case DRM_FORMAT_ARGB8888:
2037 dspcntr |= DISPPLANE_BGRX888;
2039 case DRM_FORMAT_XBGR8888:
2040 case DRM_FORMAT_ABGR8888:
2041 dspcntr |= DISPPLANE_RGBX888;
2043 case DRM_FORMAT_XRGB2101010:
2044 case DRM_FORMAT_ARGB2101010:
2045 dspcntr |= DISPPLANE_BGRX101010;
2047 case DRM_FORMAT_XBGR2101010:
2048 case DRM_FORMAT_ABGR2101010:
2049 dspcntr |= DISPPLANE_RGBX101010;
2055 if (obj->tiling_mode != I915_TILING_NONE)
2056 dspcntr |= DISPPLANE_TILED;
2058 dspcntr &= ~DISPPLANE_TILED;
2061 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2063 I915_WRITE(reg, dspcntr);
2065 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2066 intel_crtc->dspaddr_offset =
2067 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2068 fb->bits_per_pixel / 8,
2070 linear_offset -= intel_crtc->dspaddr_offset;
2072 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2073 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2074 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2075 I915_MODIFY_DISPBASE(DSPSURF(plane),
2076 obj->gtt_offset + intel_crtc->dspaddr_offset);
2077 if (IS_HASWELL(dev)) {
2078 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2080 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2081 I915_WRITE(DSPLINOFF(plane), linear_offset);
2088 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2090 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2091 int x, int y, enum mode_set_atomic state)
2093 struct drm_device *dev = crtc->dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2096 if (dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
2098 intel_increase_pllclock(crtc);
2100 return dev_priv->display.update_plane(crtc, fb, x, y);
2103 void intel_display_handle_reset(struct drm_device *dev)
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 struct drm_crtc *crtc;
2109 * Flips in the rings have been nuked by the reset,
2110 * so complete all pending flips so that user space
2111 * will get its events and not get stuck.
2113 * Also update the base address of all primary
2114 * planes to the the last fb to make sure we're
2115 * showing the correct fb after a reset.
2117 * Need to make two loops over the crtcs so that we
2118 * don't try to grab a crtc mutex before the
2119 * pending_flip_queue really got woken up.
2122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124 enum plane plane = intel_crtc->plane;
2126 intel_prepare_page_flip(dev, plane);
2127 intel_finish_page_flip_plane(dev, plane);
2130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133 mutex_lock(&crtc->mutex);
2134 if (intel_crtc->active)
2135 dev_priv->display.update_plane(crtc, crtc->fb,
2137 mutex_unlock(&crtc->mutex);
2142 intel_finish_fb(struct drm_framebuffer *old_fb)
2144 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2145 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2146 bool was_interruptible = dev_priv->mm.interruptible;
2149 /* Big Hammer, we also need to ensure that any pending
2150 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2151 * current scanout is retired before unpinning the old
2154 * This should only fail upon a hung GPU, in which case we
2155 * can safely continue.
2157 dev_priv->mm.interruptible = false;
2158 ret = i915_gem_object_finish_gpu(obj);
2159 dev_priv->mm.interruptible = was_interruptible;
2164 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2166 struct drm_device *dev = crtc->dev;
2167 struct drm_i915_master_private *master_priv;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170 if (!dev->primary->master)
2173 master_priv = dev->primary->master->driver_priv;
2174 if (!master_priv->sarea_priv)
2177 switch (intel_crtc->pipe) {
2179 master_priv->sarea_priv->pipeA_x = x;
2180 master_priv->sarea_priv->pipeA_y = y;
2183 master_priv->sarea_priv->pipeB_x = x;
2184 master_priv->sarea_priv->pipeB_y = y;
2192 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2193 struct drm_framebuffer *fb)
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2198 struct drm_framebuffer *old_fb;
2203 DRM_ERROR("No FB bound\n");
2207 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2208 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2209 plane_name(intel_crtc->plane),
2210 INTEL_INFO(dev)->num_pipes);
2214 mutex_lock(&dev->struct_mutex);
2215 ret = intel_pin_and_fence_fb_obj(dev,
2216 to_intel_framebuffer(fb)->obj,
2219 mutex_unlock(&dev->struct_mutex);
2220 DRM_ERROR("pin & fence failed\n");
2224 /* Update pipe size and adjust fitter if needed */
2225 if (i915_fastboot) {
2226 I915_WRITE(PIPESRC(intel_crtc->pipe),
2227 ((crtc->mode.hdisplay - 1) << 16) |
2228 (crtc->mode.vdisplay - 1));
2229 if (!intel_crtc->config.pch_pfit.size &&
2230 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2231 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2232 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2233 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2234 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2238 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2240 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2241 mutex_unlock(&dev->struct_mutex);
2242 DRM_ERROR("failed to update base address\n");
2252 if (intel_crtc->active && old_fb != fb)
2253 intel_wait_for_vblank(dev, intel_crtc->pipe);
2254 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2257 intel_update_fbc(dev);
2258 mutex_unlock(&dev->struct_mutex);
2260 intel_crtc_update_sarea_pos(crtc, x, y);
2265 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2267 struct drm_device *dev = crtc->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270 int pipe = intel_crtc->pipe;
2273 /* enable normal train */
2274 reg = FDI_TX_CTL(pipe);
2275 temp = I915_READ(reg);
2276 if (IS_IVYBRIDGE(dev)) {
2277 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2278 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2283 I915_WRITE(reg, temp);
2285 reg = FDI_RX_CTL(pipe);
2286 temp = I915_READ(reg);
2287 if (HAS_PCH_CPT(dev)) {
2288 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2289 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2291 temp &= ~FDI_LINK_TRAIN_NONE;
2292 temp |= FDI_LINK_TRAIN_NONE;
2294 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2296 /* wait one idle pattern time */
2300 /* IVB wants error correction enabled */
2301 if (IS_IVYBRIDGE(dev))
2302 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2303 FDI_FE_ERRC_ENABLE);
2306 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2308 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2311 static void ivb_modeset_global_resources(struct drm_device *dev)
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct intel_crtc *pipe_B_crtc =
2315 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2316 struct intel_crtc *pipe_C_crtc =
2317 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2321 * When everything is off disable fdi C so that we could enable fdi B
2322 * with all lanes. Note that we don't care about enabled pipes without
2323 * an enabled pch encoder.
2325 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2326 !pipe_has_enabled_pch(pipe_C_crtc)) {
2327 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2328 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2330 temp = I915_READ(SOUTH_CHICKEN1);
2331 temp &= ~FDI_BC_BIFURCATION_SELECT;
2332 DRM_DEBUG_KMS("disabling fdi C rx\n");
2333 I915_WRITE(SOUTH_CHICKEN1, temp);
2337 /* The FDI link training functions for ILK/Ibexpeak. */
2338 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2340 struct drm_device *dev = crtc->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343 int pipe = intel_crtc->pipe;
2344 int plane = intel_crtc->plane;
2345 u32 reg, temp, tries;
2347 /* FDI needs bits from pipe & plane first */
2348 assert_pipe_enabled(dev_priv, pipe);
2349 assert_plane_enabled(dev_priv, plane);
2351 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2353 reg = FDI_RX_IMR(pipe);
2354 temp = I915_READ(reg);
2355 temp &= ~FDI_RX_SYMBOL_LOCK;
2356 temp &= ~FDI_RX_BIT_LOCK;
2357 I915_WRITE(reg, temp);
2361 /* enable CPU FDI TX and PCH FDI RX */
2362 reg = FDI_TX_CTL(pipe);
2363 temp = I915_READ(reg);
2364 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2365 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_PATTERN_1;
2368 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2370 reg = FDI_RX_CTL(pipe);
2371 temp = I915_READ(reg);
2372 temp &= ~FDI_LINK_TRAIN_NONE;
2373 temp |= FDI_LINK_TRAIN_PATTERN_1;
2374 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2379 /* Ironlake workaround, enable clock pointer after FDI enable*/
2380 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2381 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2382 FDI_RX_PHASE_SYNC_POINTER_EN);
2384 reg = FDI_RX_IIR(pipe);
2385 for (tries = 0; tries < 5; tries++) {
2386 temp = I915_READ(reg);
2387 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2389 if ((temp & FDI_RX_BIT_LOCK)) {
2390 DRM_DEBUG_KMS("FDI train 1 done.\n");
2391 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2396 DRM_ERROR("FDI train 1 fail!\n");
2399 reg = FDI_TX_CTL(pipe);
2400 temp = I915_READ(reg);
2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_2;
2403 I915_WRITE(reg, temp);
2405 reg = FDI_RX_CTL(pipe);
2406 temp = I915_READ(reg);
2407 temp &= ~FDI_LINK_TRAIN_NONE;
2408 temp |= FDI_LINK_TRAIN_PATTERN_2;
2409 I915_WRITE(reg, temp);
2414 reg = FDI_RX_IIR(pipe);
2415 for (tries = 0; tries < 5; tries++) {
2416 temp = I915_READ(reg);
2417 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2419 if (temp & FDI_RX_SYMBOL_LOCK) {
2420 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2421 DRM_DEBUG_KMS("FDI train 2 done.\n");
2426 DRM_ERROR("FDI train 2 fail!\n");
2428 DRM_DEBUG_KMS("FDI train done\n");
2432 static const int snb_b_fdi_train_param[] = {
2433 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2434 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2435 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2436 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2439 /* The FDI link training functions for SNB/Cougarpoint. */
2440 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2442 struct drm_device *dev = crtc->dev;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445 int pipe = intel_crtc->pipe;
2446 u32 reg, temp, i, retry;
2448 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2450 reg = FDI_RX_IMR(pipe);
2451 temp = I915_READ(reg);
2452 temp &= ~FDI_RX_SYMBOL_LOCK;
2453 temp &= ~FDI_RX_BIT_LOCK;
2454 I915_WRITE(reg, temp);
2459 /* enable CPU FDI TX and PCH FDI RX */
2460 reg = FDI_TX_CTL(pipe);
2461 temp = I915_READ(reg);
2462 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2463 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_1;
2466 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2468 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2469 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2471 I915_WRITE(FDI_RX_MISC(pipe),
2472 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
2476 if (HAS_PCH_CPT(dev)) {
2477 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_1;
2483 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2488 for (i = 0; i < 4; i++) {
2489 reg = FDI_TX_CTL(pipe);
2490 temp = I915_READ(reg);
2491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492 temp |= snb_b_fdi_train_param[i];
2493 I915_WRITE(reg, temp);
2498 for (retry = 0; retry < 5; retry++) {
2499 reg = FDI_RX_IIR(pipe);
2500 temp = I915_READ(reg);
2501 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2502 if (temp & FDI_RX_BIT_LOCK) {
2503 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2504 DRM_DEBUG_KMS("FDI train 1 done.\n");
2513 DRM_ERROR("FDI train 1 fail!\n");
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
2521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2525 I915_WRITE(reg, temp);
2527 reg = FDI_RX_CTL(pipe);
2528 temp = I915_READ(reg);
2529 if (HAS_PCH_CPT(dev)) {
2530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2531 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_2;
2536 I915_WRITE(reg, temp);
2541 for (i = 0; i < 4; i++) {
2542 reg = FDI_TX_CTL(pipe);
2543 temp = I915_READ(reg);
2544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545 temp |= snb_b_fdi_train_param[i];
2546 I915_WRITE(reg, temp);
2551 for (retry = 0; retry < 5; retry++) {
2552 reg = FDI_RX_IIR(pipe);
2553 temp = I915_READ(reg);
2554 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2555 if (temp & FDI_RX_SYMBOL_LOCK) {
2556 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2566 DRM_ERROR("FDI train 2 fail!\n");
2568 DRM_DEBUG_KMS("FDI train done.\n");
2571 /* Manual link training for Ivy Bridge A0 parts */
2572 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2574 struct drm_device *dev = crtc->dev;
2575 struct drm_i915_private *dev_priv = dev->dev_private;
2576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2577 int pipe = intel_crtc->pipe;
2580 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2582 reg = FDI_RX_IMR(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_RX_SYMBOL_LOCK;
2585 temp &= ~FDI_RX_BIT_LOCK;
2586 I915_WRITE(reg, temp);
2591 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2592 I915_READ(FDI_RX_IIR(pipe)));
2594 /* enable CPU FDI TX and PCH FDI RX */
2595 reg = FDI_TX_CTL(pipe);
2596 temp = I915_READ(reg);
2597 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2598 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2599 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2600 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2603 temp |= FDI_COMPOSITE_SYNC;
2604 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2606 I915_WRITE(FDI_RX_MISC(pipe),
2607 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2609 reg = FDI_RX_CTL(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_LINK_TRAIN_AUTO;
2612 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2613 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2614 temp |= FDI_COMPOSITE_SYNC;
2615 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2620 for (i = 0; i < 4; i++) {
2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= snb_b_fdi_train_param[i];
2625 I915_WRITE(reg, temp);
2630 reg = FDI_RX_IIR(pipe);
2631 temp = I915_READ(reg);
2632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2634 if (temp & FDI_RX_BIT_LOCK ||
2635 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2636 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2637 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2642 DRM_ERROR("FDI train 1 fail!\n");
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2649 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651 I915_WRITE(reg, temp);
2653 reg = FDI_RX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2657 I915_WRITE(reg, temp);
2662 for (i = 0; i < 4; i++) {
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666 temp |= snb_b_fdi_train_param[i];
2667 I915_WRITE(reg, temp);
2672 reg = FDI_RX_IIR(pipe);
2673 temp = I915_READ(reg);
2674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2676 if (temp & FDI_RX_SYMBOL_LOCK) {
2677 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2678 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2683 DRM_ERROR("FDI train 2 fail!\n");
2685 DRM_DEBUG_KMS("FDI train done.\n");
2688 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2690 struct drm_device *dev = intel_crtc->base.dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 int pipe = intel_crtc->pipe;
2696 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2697 reg = FDI_RX_CTL(pipe);
2698 temp = I915_READ(reg);
2699 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2700 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2701 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2702 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2707 /* Switch from Rawclk to PCDclk */
2708 temp = I915_READ(reg);
2709 I915_WRITE(reg, temp | FDI_PCDCLK);
2714 /* Enable CPU FDI TX PLL, always on for Ironlake */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2718 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2725 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2727 struct drm_device *dev = intel_crtc->base.dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 int pipe = intel_crtc->pipe;
2732 /* Switch from PCDclk to Rawclk */
2733 reg = FDI_RX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2737 /* Disable CPU FDI TX PLL */
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2749 /* Wait for the clocks to turn off. */
2754 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2756 struct drm_device *dev = crtc->dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759 int pipe = intel_crtc->pipe;
2762 /* disable CPU FDI tx and PCH FDI rx */
2763 reg = FDI_TX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~(0x7 << 16);
2771 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2772 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2777 /* Ironlake workaround, disable clock pointer after downing FDI */
2778 if (HAS_PCH_IBX(dev)) {
2779 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2782 /* still set train pattern 1 */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 temp &= ~FDI_LINK_TRAIN_NONE;
2786 temp |= FDI_LINK_TRAIN_PATTERN_1;
2787 I915_WRITE(reg, temp);
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if (HAS_PCH_CPT(dev)) {
2792 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2793 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2795 temp &= ~FDI_LINK_TRAIN_NONE;
2796 temp |= FDI_LINK_TRAIN_PATTERN_1;
2798 /* BPC in FDI rx is consistent with that in PIPECONF */
2799 temp &= ~(0x07 << 16);
2800 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2801 I915_WRITE(reg, temp);
2807 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2809 struct drm_device *dev = crtc->dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2812 unsigned long flags;
2815 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2816 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2819 spin_lock_irqsave(&dev->event_lock, flags);
2820 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821 spin_unlock_irqrestore(&dev->event_lock, flags);
2826 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2831 if (crtc->fb == NULL)
2834 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2836 wait_event(dev_priv->pending_flip_queue,
2837 !intel_crtc_has_pending_flip(crtc));
2839 mutex_lock(&dev->struct_mutex);
2840 intel_finish_fb(crtc->fb);
2841 mutex_unlock(&dev->struct_mutex);
2844 /* Program iCLKIP clock to the desired frequency */
2845 static void lpt_program_iclkip(struct drm_crtc *crtc)
2847 struct drm_device *dev = crtc->dev;
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2852 mutex_lock(&dev_priv->dpio_lock);
2854 /* It is necessary to ungate the pixclk gate prior to programming
2855 * the divisors, and gate it back when it is done.
2857 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2859 /* Disable SSCCTL */
2860 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2861 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2865 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2866 if (crtc->mode.clock == 20000) {
2871 /* The iCLK virtual clock root frequency is in MHz,
2872 * but the crtc->mode.clock in in KHz. To get the divisors,
2873 * it is necessary to divide one by another, so we
2874 * convert the virtual clock precision to KHz here for higher
2877 u32 iclk_virtual_root_freq = 172800 * 1000;
2878 u32 iclk_pi_range = 64;
2879 u32 desired_divisor, msb_divisor_value, pi_value;
2881 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2882 msb_divisor_value = desired_divisor / iclk_pi_range;
2883 pi_value = desired_divisor % iclk_pi_range;
2886 divsel = msb_divisor_value - 2;
2887 phaseinc = pi_value;
2890 /* This should not happen with any sane values */
2891 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2892 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2893 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2894 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2896 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2903 /* Program SSCDIVINTPHASE6 */
2904 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2905 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2906 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2907 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2908 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2909 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2910 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2911 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2913 /* Program SSCAUXDIV */
2914 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2915 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2916 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2917 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2919 /* Enable modulator and associated divider */
2920 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2921 temp &= ~SBI_SSCCTL_DISABLE;
2922 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2924 /* Wait for initialization time */
2927 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2929 mutex_unlock(&dev_priv->dpio_lock);
2932 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2933 enum pipe pch_transcoder)
2935 struct drm_device *dev = crtc->base.dev;
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2939 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2940 I915_READ(HTOTAL(cpu_transcoder)));
2941 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2942 I915_READ(HBLANK(cpu_transcoder)));
2943 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2944 I915_READ(HSYNC(cpu_transcoder)));
2946 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2947 I915_READ(VTOTAL(cpu_transcoder)));
2948 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2949 I915_READ(VBLANK(cpu_transcoder)));
2950 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2951 I915_READ(VSYNC(cpu_transcoder)));
2952 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2953 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2957 * Enable PCH resources required for PCH ports:
2959 * - FDI training & RX/TX
2960 * - update transcoder timings
2961 * - DP transcoding bits
2964 static void ironlake_pch_enable(struct drm_crtc *crtc)
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969 int pipe = intel_crtc->pipe;
2972 assert_pch_transcoder_disabled(dev_priv, pipe);
2974 /* Write the TU size bits before fdi link training, so that error
2975 * detection works. */
2976 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2977 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2979 /* For PCH output, training FDI link */
2980 dev_priv->display.fdi_link_train(crtc);
2982 /* XXX: pch pll's can be enabled any time before we enable the PCH
2983 * transcoder, and we actually should do this to not upset any PCH
2984 * transcoder that already use the clock when we share it.
2986 * Note that enable_shared_dpll tries to do the right thing, but
2987 * get_shared_dpll unconditionally resets the pll - we need that to have
2988 * the right LVDS enable sequence. */
2989 ironlake_enable_shared_dpll(intel_crtc);
2991 if (HAS_PCH_CPT(dev)) {
2994 temp = I915_READ(PCH_DPLL_SEL);
2995 temp |= TRANS_DPLL_ENABLE(pipe);
2996 sel = TRANS_DPLLB_SEL(pipe);
2997 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3001 I915_WRITE(PCH_DPLL_SEL, temp);
3004 /* set transcoder timing, panel must allow it */
3005 assert_panel_unlocked(dev_priv, pipe);
3006 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3008 intel_fdi_normal_train(crtc);
3010 /* For PCH DP, enable TRANS_DP_CTL */
3011 if (HAS_PCH_CPT(dev) &&
3012 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3013 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3014 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3015 reg = TRANS_DP_CTL(pipe);
3016 temp = I915_READ(reg);
3017 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3018 TRANS_DP_SYNC_MASK |
3020 temp |= (TRANS_DP_OUTPUT_ENABLE |
3021 TRANS_DP_ENH_FRAMING);
3022 temp |= bpc << 9; /* same format but at 11:9 */
3024 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3025 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3026 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3027 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3029 switch (intel_trans_dp_port_sel(crtc)) {
3031 temp |= TRANS_DP_PORT_SEL_B;
3034 temp |= TRANS_DP_PORT_SEL_C;
3037 temp |= TRANS_DP_PORT_SEL_D;
3043 I915_WRITE(reg, temp);
3046 ironlake_enable_pch_transcoder(dev_priv, pipe);
3049 static void lpt_pch_enable(struct drm_crtc *crtc)
3051 struct drm_device *dev = crtc->dev;
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3056 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3058 lpt_program_iclkip(crtc);
3060 /* Set transcoder timing. */
3061 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3063 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3066 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3068 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3073 if (pll->refcount == 0) {
3074 WARN(1, "bad %s refcount\n", pll->name);
3078 if (--pll->refcount == 0) {
3080 WARN_ON(pll->active);
3083 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3086 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3088 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3089 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090 enum intel_dpll_id i;
3093 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3094 crtc->base.base.id, pll->name);
3095 intel_put_shared_dpll(crtc);
3098 if (HAS_PCH_IBX(dev_priv->dev)) {
3099 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3100 i = (enum intel_dpll_id) crtc->pipe;
3101 pll = &dev_priv->shared_dplls[i];
3103 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3104 crtc->base.base.id, pll->name);
3109 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3110 pll = &dev_priv->shared_dplls[i];
3112 /* Only want to check enabled timings first */
3113 if (pll->refcount == 0)
3116 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3117 sizeof(pll->hw_state)) == 0) {
3118 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3120 pll->name, pll->refcount, pll->active);
3126 /* Ok no matching timings, maybe there's a free one? */
3127 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3128 pll = &dev_priv->shared_dplls[i];
3129 if (pll->refcount == 0) {
3130 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3131 crtc->base.base.id, pll->name);
3139 crtc->config.shared_dpll = i;
3140 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3141 pipe_name(crtc->pipe));
3143 if (pll->active == 0) {
3144 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3145 sizeof(pll->hw_state));
3147 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3149 assert_shared_dpll_disabled(dev_priv, pll);
3151 pll->mode_set(dev_priv, pll);
3158 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 int dslreg = PIPEDSL(pipe);
3164 temp = I915_READ(dslreg);
3166 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3167 if (wait_for(I915_READ(dslreg) != temp, 5))
3168 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3172 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3174 struct drm_device *dev = crtc->base.dev;
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176 int pipe = crtc->pipe;
3178 if (crtc->config.pch_pfit.size) {
3179 /* Force use of hard-coded filter coefficients
3180 * as some pre-programmed values are broken,
3183 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3184 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3185 PF_PIPE_SEL_IVB(pipe));
3187 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3188 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3189 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3193 static void intel_enable_planes(struct drm_crtc *crtc)
3195 struct drm_device *dev = crtc->dev;
3196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3197 struct intel_plane *intel_plane;
3199 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3200 if (intel_plane->pipe == pipe)
3201 intel_plane_restore(&intel_plane->base);
3204 static void intel_disable_planes(struct drm_crtc *crtc)
3206 struct drm_device *dev = crtc->dev;
3207 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3208 struct intel_plane *intel_plane;
3210 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3211 if (intel_plane->pipe == pipe)
3212 intel_plane_disable(&intel_plane->base);
3215 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3217 struct drm_device *dev = crtc->dev;
3218 struct drm_i915_private *dev_priv = dev->dev_private;
3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3220 struct intel_encoder *encoder;
3221 int pipe = intel_crtc->pipe;
3222 int plane = intel_crtc->plane;
3224 WARN_ON(!crtc->enabled);
3226 if (intel_crtc->active)
3229 intel_crtc->active = true;
3231 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3232 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3234 intel_update_watermarks(dev);
3236 for_each_encoder_on_crtc(dev, crtc, encoder)
3237 if (encoder->pre_enable)
3238 encoder->pre_enable(encoder);
3240 if (intel_crtc->config.has_pch_encoder) {
3241 /* Note: FDI PLL enabling _must_ be done before we enable the
3242 * cpu pipes, hence this is separate from all the other fdi/pch
3244 ironlake_fdi_pll_enable(intel_crtc);
3246 assert_fdi_tx_disabled(dev_priv, pipe);
3247 assert_fdi_rx_disabled(dev_priv, pipe);
3250 ironlake_pfit_enable(intel_crtc);
3253 * On ILK+ LUT must be loaded before the pipe is running but with
3256 intel_crtc_load_lut(crtc);
3258 intel_enable_pipe(dev_priv, pipe,
3259 intel_crtc->config.has_pch_encoder);
3260 intel_enable_plane(dev_priv, plane, pipe);
3261 intel_enable_planes(crtc);
3262 intel_crtc_update_cursor(crtc, true);
3264 if (intel_crtc->config.has_pch_encoder)
3265 ironlake_pch_enable(crtc);
3267 mutex_lock(&dev->struct_mutex);
3268 intel_update_fbc(dev);
3269 mutex_unlock(&dev->struct_mutex);
3271 for_each_encoder_on_crtc(dev, crtc, encoder)
3272 encoder->enable(encoder);
3274 if (HAS_PCH_CPT(dev))
3275 cpt_verify_modeset(dev, intel_crtc->pipe);
3278 * There seems to be a race in PCH platform hw (at least on some
3279 * outputs) where an enabled pipe still completes any pageflip right
3280 * away (as if the pipe is off) instead of waiting for vblank. As soon
3281 * as the first vblank happend, everything works as expected. Hence just
3282 * wait for one vblank before returning to avoid strange things
3285 intel_wait_for_vblank(dev, intel_crtc->pipe);
3288 /* IPS only exists on ULT machines and is tied to pipe A. */
3289 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3291 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3294 static void hsw_enable_ips(struct intel_crtc *crtc)
3296 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3298 if (!crtc->config.ips_enabled)
3301 /* We can only enable IPS after we enable a plane and wait for a vblank.
3302 * We guarantee that the plane is enabled by calling intel_enable_ips
3303 * only after intel_enable_plane. And intel_enable_plane already waits
3304 * for a vblank, so all we need to do here is to enable the IPS bit. */
3305 assert_plane_enabled(dev_priv, crtc->plane);
3306 I915_WRITE(IPS_CTL, IPS_ENABLE);
3309 static void hsw_disable_ips(struct intel_crtc *crtc)
3311 struct drm_device *dev = crtc->base.dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3314 if (!crtc->config.ips_enabled)
3317 assert_plane_enabled(dev_priv, crtc->plane);
3318 I915_WRITE(IPS_CTL, 0);
3320 /* We need to wait for a vblank before we can disable the plane. */
3321 intel_wait_for_vblank(dev, crtc->pipe);
3324 static void haswell_crtc_enable(struct drm_crtc *crtc)
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329 struct intel_encoder *encoder;
3330 int pipe = intel_crtc->pipe;
3331 int plane = intel_crtc->plane;
3333 WARN_ON(!crtc->enabled);
3335 if (intel_crtc->active)
3338 intel_crtc->active = true;
3340 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3341 if (intel_crtc->config.has_pch_encoder)
3342 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3344 intel_update_watermarks(dev);
3346 if (intel_crtc->config.has_pch_encoder)
3347 dev_priv->display.fdi_link_train(crtc);
3349 for_each_encoder_on_crtc(dev, crtc, encoder)
3350 if (encoder->pre_enable)
3351 encoder->pre_enable(encoder);
3353 intel_ddi_enable_pipe_clock(intel_crtc);
3355 ironlake_pfit_enable(intel_crtc);
3358 * On ILK+ LUT must be loaded before the pipe is running but with
3361 intel_crtc_load_lut(crtc);
3363 intel_ddi_set_pipe_settings(crtc);
3364 intel_ddi_enable_transcoder_func(crtc);
3366 intel_enable_pipe(dev_priv, pipe,
3367 intel_crtc->config.has_pch_encoder);
3368 intel_enable_plane(dev_priv, plane, pipe);
3369 intel_enable_planes(crtc);
3370 intel_crtc_update_cursor(crtc, true);
3372 hsw_enable_ips(intel_crtc);
3374 if (intel_crtc->config.has_pch_encoder)
3375 lpt_pch_enable(crtc);
3377 mutex_lock(&dev->struct_mutex);
3378 intel_update_fbc(dev);
3379 mutex_unlock(&dev->struct_mutex);
3381 for_each_encoder_on_crtc(dev, crtc, encoder)
3382 encoder->enable(encoder);
3385 * There seems to be a race in PCH platform hw (at least on some
3386 * outputs) where an enabled pipe still completes any pageflip right
3387 * away (as if the pipe is off) instead of waiting for vblank. As soon
3388 * as the first vblank happend, everything works as expected. Hence just
3389 * wait for one vblank before returning to avoid strange things
3392 intel_wait_for_vblank(dev, intel_crtc->pipe);
3395 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3397 struct drm_device *dev = crtc->base.dev;
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399 int pipe = crtc->pipe;
3401 /* To avoid upsetting the power well on haswell only disable the pfit if
3402 * it's in use. The hw state code will make sure we get this right. */
3403 if (crtc->config.pch_pfit.size) {
3404 I915_WRITE(PF_CTL(pipe), 0);
3405 I915_WRITE(PF_WIN_POS(pipe), 0);
3406 I915_WRITE(PF_WIN_SZ(pipe), 0);
3410 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415 struct intel_encoder *encoder;
3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
3421 if (!intel_crtc->active)
3424 for_each_encoder_on_crtc(dev, crtc, encoder)
3425 encoder->disable(encoder);
3427 intel_crtc_wait_for_pending_flips(crtc);
3428 drm_vblank_off(dev, pipe);
3430 if (dev_priv->fbc.plane == plane)
3431 intel_disable_fbc(dev);
3433 intel_crtc_update_cursor(crtc, false);
3434 intel_disable_planes(crtc);
3435 intel_disable_plane(dev_priv, plane, pipe);
3437 if (intel_crtc->config.has_pch_encoder)
3438 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3440 intel_disable_pipe(dev_priv, pipe);
3442 ironlake_pfit_disable(intel_crtc);
3444 for_each_encoder_on_crtc(dev, crtc, encoder)
3445 if (encoder->post_disable)
3446 encoder->post_disable(encoder);
3448 if (intel_crtc->config.has_pch_encoder) {
3449 ironlake_fdi_disable(crtc);
3451 ironlake_disable_pch_transcoder(dev_priv, pipe);
3452 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3454 if (HAS_PCH_CPT(dev)) {
3455 /* disable TRANS_DP_CTL */
3456 reg = TRANS_DP_CTL(pipe);
3457 temp = I915_READ(reg);
3458 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3459 TRANS_DP_PORT_SEL_MASK);
3460 temp |= TRANS_DP_PORT_SEL_NONE;
3461 I915_WRITE(reg, temp);
3463 /* disable DPLL_SEL */
3464 temp = I915_READ(PCH_DPLL_SEL);
3465 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3466 I915_WRITE(PCH_DPLL_SEL, temp);
3469 /* disable PCH DPLL */
3470 intel_disable_shared_dpll(intel_crtc);
3472 ironlake_fdi_pll_disable(intel_crtc);
3475 intel_crtc->active = false;
3476 intel_update_watermarks(dev);
3478 mutex_lock(&dev->struct_mutex);
3479 intel_update_fbc(dev);
3480 mutex_unlock(&dev->struct_mutex);
3483 static void haswell_crtc_disable(struct drm_crtc *crtc)
3485 struct drm_device *dev = crtc->dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488 struct intel_encoder *encoder;
3489 int pipe = intel_crtc->pipe;
3490 int plane = intel_crtc->plane;
3491 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3493 if (!intel_crtc->active)
3496 for_each_encoder_on_crtc(dev, crtc, encoder)
3497 encoder->disable(encoder);
3499 intel_crtc_wait_for_pending_flips(crtc);
3500 drm_vblank_off(dev, pipe);
3502 /* FBC must be disabled before disabling the plane on HSW. */
3503 if (dev_priv->fbc.plane == plane)
3504 intel_disable_fbc(dev);
3506 hsw_disable_ips(intel_crtc);
3508 intel_crtc_update_cursor(crtc, false);
3509 intel_disable_planes(crtc);
3510 intel_disable_plane(dev_priv, plane, pipe);
3512 if (intel_crtc->config.has_pch_encoder)
3513 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3514 intel_disable_pipe(dev_priv, pipe);
3516 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3518 ironlake_pfit_disable(intel_crtc);
3520 intel_ddi_disable_pipe_clock(intel_crtc);
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 if (encoder->post_disable)
3524 encoder->post_disable(encoder);
3526 if (intel_crtc->config.has_pch_encoder) {
3527 lpt_disable_pch_transcoder(dev_priv);
3528 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3529 intel_ddi_fdi_disable(crtc);
3532 intel_crtc->active = false;
3533 intel_update_watermarks(dev);
3535 mutex_lock(&dev->struct_mutex);
3536 intel_update_fbc(dev);
3537 mutex_unlock(&dev->struct_mutex);
3540 static void ironlake_crtc_off(struct drm_crtc *crtc)
3542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543 intel_put_shared_dpll(intel_crtc);
3546 static void haswell_crtc_off(struct drm_crtc *crtc)
3548 intel_ddi_put_crtc_pll(crtc);
3551 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3553 if (!enable && intel_crtc->overlay) {
3554 struct drm_device *dev = intel_crtc->base.dev;
3555 struct drm_i915_private *dev_priv = dev->dev_private;
3557 mutex_lock(&dev->struct_mutex);
3558 dev_priv->mm.interruptible = false;
3559 (void) intel_overlay_switch_off(intel_crtc->overlay);
3560 dev_priv->mm.interruptible = true;
3561 mutex_unlock(&dev->struct_mutex);
3564 /* Let userspace switch the overlay on again. In most cases userspace
3565 * has to recompute where to put it anyway.
3570 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3571 * cursor plane briefly if not already running after enabling the display
3573 * This workaround avoids occasional blank screens when self refresh is
3577 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3579 u32 cntl = I915_READ(CURCNTR(pipe));
3581 if ((cntl & CURSOR_MODE) == 0) {
3582 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3584 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3585 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3586 intel_wait_for_vblank(dev_priv->dev, pipe);
3587 I915_WRITE(CURCNTR(pipe), cntl);
3588 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3589 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3593 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3595 struct drm_device *dev = crtc->base.dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc_config *pipe_config = &crtc->config;
3599 if (!crtc->config.gmch_pfit.control)
3603 * The panel fitter should only be adjusted whilst the pipe is disabled,
3604 * according to register description and PRM.
3606 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3607 assert_pipe_disabled(dev_priv, crtc->pipe);
3609 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3610 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3612 /* Border color in case we don't scale up to the full screen. Black by
3613 * default, change to something else for debugging. */
3614 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3617 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 struct intel_encoder *encoder;
3623 int pipe = intel_crtc->pipe;
3624 int plane = intel_crtc->plane;
3626 WARN_ON(!crtc->enabled);
3628 if (intel_crtc->active)
3631 intel_crtc->active = true;
3632 intel_update_watermarks(dev);
3634 mutex_lock(&dev_priv->dpio_lock);
3636 for_each_encoder_on_crtc(dev, crtc, encoder)
3637 if (encoder->pre_pll_enable)
3638 encoder->pre_pll_enable(encoder);
3640 vlv_enable_pll(dev_priv, pipe);
3642 for_each_encoder_on_crtc(dev, crtc, encoder)
3643 if (encoder->pre_enable)
3644 encoder->pre_enable(encoder);
3646 /* VLV wants encoder enabling _before_ the pipe is up. */
3647 for_each_encoder_on_crtc(dev, crtc, encoder)
3648 encoder->enable(encoder);
3650 i9xx_pfit_enable(intel_crtc);
3652 intel_crtc_load_lut(crtc);
3654 intel_enable_pipe(dev_priv, pipe, false);
3655 intel_enable_plane(dev_priv, plane, pipe);
3656 intel_enable_planes(crtc);
3657 intel_crtc_update_cursor(crtc, true);
3659 intel_update_fbc(dev);
3661 mutex_unlock(&dev_priv->dpio_lock);
3664 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3666 struct drm_device *dev = crtc->dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3669 struct intel_encoder *encoder;
3670 int pipe = intel_crtc->pipe;
3671 int plane = intel_crtc->plane;
3673 WARN_ON(!crtc->enabled);
3675 if (intel_crtc->active)
3678 intel_crtc->active = true;
3679 intel_update_watermarks(dev);
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 if (encoder->pre_enable)
3683 encoder->pre_enable(encoder);
3685 i9xx_enable_pll(intel_crtc);
3687 i9xx_pfit_enable(intel_crtc);
3689 intel_crtc_load_lut(crtc);
3691 intel_enable_pipe(dev_priv, pipe, false);
3692 intel_enable_plane(dev_priv, plane, pipe);
3693 intel_enable_planes(crtc);
3694 /* The fixup needs to happen before cursor is enabled */
3696 g4x_fixup_plane(dev_priv, pipe);
3697 intel_crtc_update_cursor(crtc, true);
3699 /* Give the overlay scaler a chance to enable if it's on this pipe */
3700 intel_crtc_dpms_overlay(intel_crtc, true);
3702 intel_update_fbc(dev);
3704 for_each_encoder_on_crtc(dev, crtc, encoder)
3705 encoder->enable(encoder);
3708 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3710 struct drm_device *dev = crtc->base.dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3713 if (!crtc->config.gmch_pfit.control)
3716 assert_pipe_disabled(dev_priv, crtc->pipe);
3718 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3719 I915_READ(PFIT_CONTROL));
3720 I915_WRITE(PFIT_CONTROL, 0);
3723 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3725 struct drm_device *dev = crtc->dev;
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728 struct intel_encoder *encoder;
3729 int pipe = intel_crtc->pipe;
3730 int plane = intel_crtc->plane;
3732 if (!intel_crtc->active)
3735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 encoder->disable(encoder);
3738 /* Give the overlay scaler a chance to disable if it's on this pipe */
3739 intel_crtc_wait_for_pending_flips(crtc);
3740 drm_vblank_off(dev, pipe);
3742 if (dev_priv->fbc.plane == plane)
3743 intel_disable_fbc(dev);
3745 intel_crtc_dpms_overlay(intel_crtc, false);
3746 intel_crtc_update_cursor(crtc, false);
3747 intel_disable_planes(crtc);
3748 intel_disable_plane(dev_priv, plane, pipe);
3750 intel_disable_pipe(dev_priv, pipe);
3752 i9xx_pfit_disable(intel_crtc);
3754 for_each_encoder_on_crtc(dev, crtc, encoder)
3755 if (encoder->post_disable)
3756 encoder->post_disable(encoder);
3758 intel_disable_pll(dev_priv, pipe);
3760 intel_crtc->active = false;
3761 intel_update_fbc(dev);
3762 intel_update_watermarks(dev);
3765 static void i9xx_crtc_off(struct drm_crtc *crtc)
3769 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3772 struct drm_device *dev = crtc->dev;
3773 struct drm_i915_master_private *master_priv;
3774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775 int pipe = intel_crtc->pipe;
3777 if (!dev->primary->master)
3780 master_priv = dev->primary->master->driver_priv;
3781 if (!master_priv->sarea_priv)
3786 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3787 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3790 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3791 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3794 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3800 * Sets the power management mode of the pipe and plane.
3802 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 struct intel_encoder *intel_encoder;
3807 bool enable = false;
3809 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3810 enable |= intel_encoder->connectors_active;
3813 dev_priv->display.crtc_enable(crtc);
3815 dev_priv->display.crtc_disable(crtc);
3817 intel_crtc_update_sarea(crtc, enable);
3820 static void intel_crtc_disable(struct drm_crtc *crtc)
3822 struct drm_device *dev = crtc->dev;
3823 struct drm_connector *connector;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 /* crtc should still be enabled when we disable it. */
3828 WARN_ON(!crtc->enabled);
3830 dev_priv->display.crtc_disable(crtc);
3831 intel_crtc->eld_vld = false;
3832 intel_crtc_update_sarea(crtc, false);
3833 dev_priv->display.off(crtc);
3835 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3836 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3839 mutex_lock(&dev->struct_mutex);
3840 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3841 mutex_unlock(&dev->struct_mutex);
3845 /* Update computed state. */
3846 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3847 if (!connector->encoder || !connector->encoder->crtc)
3850 if (connector->encoder->crtc != crtc)
3853 connector->dpms = DRM_MODE_DPMS_OFF;
3854 to_intel_encoder(connector->encoder)->connectors_active = false;
3858 void intel_modeset_disable(struct drm_device *dev)
3860 struct drm_crtc *crtc;
3862 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3864 intel_crtc_disable(crtc);
3868 void intel_encoder_destroy(struct drm_encoder *encoder)
3870 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3872 drm_encoder_cleanup(encoder);
3873 kfree(intel_encoder);
3876 /* Simple dpms helper for encodres with just one connector, no cloning and only
3877 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3878 * state of the entire output pipe. */
3879 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3881 if (mode == DRM_MODE_DPMS_ON) {
3882 encoder->connectors_active = true;
3884 intel_crtc_update_dpms(encoder->base.crtc);
3886 encoder->connectors_active = false;
3888 intel_crtc_update_dpms(encoder->base.crtc);
3892 /* Cross check the actual hw state with our own modeset state tracking (and it's
3893 * internal consistency). */
3894 static void intel_connector_check_state(struct intel_connector *connector)
3896 if (connector->get_hw_state(connector)) {
3897 struct intel_encoder *encoder = connector->encoder;
3898 struct drm_crtc *crtc;
3899 bool encoder_enabled;
3902 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3903 connector->base.base.id,
3904 drm_get_connector_name(&connector->base));
3906 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3907 "wrong connector dpms state\n");
3908 WARN(connector->base.encoder != &encoder->base,
3909 "active connector not linked to encoder\n");
3910 WARN(!encoder->connectors_active,
3911 "encoder->connectors_active not set\n");
3913 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3914 WARN(!encoder_enabled, "encoder not enabled\n");
3915 if (WARN_ON(!encoder->base.crtc))
3918 crtc = encoder->base.crtc;
3920 WARN(!crtc->enabled, "crtc not enabled\n");
3921 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3922 WARN(pipe != to_intel_crtc(crtc)->pipe,
3923 "encoder active on the wrong pipe\n");
3927 /* Even simpler default implementation, if there's really no special case to
3929 void intel_connector_dpms(struct drm_connector *connector, int mode)
3931 struct intel_encoder *encoder = intel_attached_encoder(connector);
3933 /* All the simple cases only support two dpms states. */
3934 if (mode != DRM_MODE_DPMS_ON)
3935 mode = DRM_MODE_DPMS_OFF;
3937 if (mode == connector->dpms)
3940 connector->dpms = mode;
3942 /* Only need to change hw state when actually enabled */
3943 if (encoder->base.crtc)
3944 intel_encoder_dpms(encoder, mode);
3946 WARN_ON(encoder->connectors_active != false);
3948 intel_modeset_check_state(connector->dev);
3951 /* Simple connector->get_hw_state implementation for encoders that support only
3952 * one connector and no cloning and hence the encoder state determines the state
3953 * of the connector. */
3954 bool intel_connector_get_hw_state(struct intel_connector *connector)
3957 struct intel_encoder *encoder = connector->encoder;
3959 return encoder->get_hw_state(encoder, &pipe);
3962 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3963 struct intel_crtc_config *pipe_config)
3965 struct drm_i915_private *dev_priv = dev->dev_private;
3966 struct intel_crtc *pipe_B_crtc =
3967 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3969 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3970 pipe_name(pipe), pipe_config->fdi_lanes);
3971 if (pipe_config->fdi_lanes > 4) {
3972 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3977 if (IS_HASWELL(dev)) {
3978 if (pipe_config->fdi_lanes > 2) {
3979 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3980 pipe_config->fdi_lanes);
3987 if (INTEL_INFO(dev)->num_pipes == 2)
3990 /* Ivybridge 3 pipe is really complicated */
3995 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3996 pipe_config->fdi_lanes > 2) {
3997 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3998 pipe_name(pipe), pipe_config->fdi_lanes);
4003 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4004 pipe_B_crtc->config.fdi_lanes <= 2) {
4005 if (pipe_config->fdi_lanes > 2) {
4006 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4011 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4021 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4022 struct intel_crtc_config *pipe_config)
4024 struct drm_device *dev = intel_crtc->base.dev;
4025 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4026 int lane, link_bw, fdi_dotclock;
4027 bool setup_ok, needs_recompute = false;
4030 /* FDI is a binary signal running at ~2.7GHz, encoding
4031 * each output octet as 10 bits. The actual frequency
4032 * is stored as a divider into a 100MHz clock, and the
4033 * mode pixel clock is stored in units of 1KHz.
4034 * Hence the bw of each lane in terms of the mode signal
4037 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4039 fdi_dotclock = adjusted_mode->clock;
4040 fdi_dotclock /= pipe_config->pixel_multiplier;
4042 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4043 pipe_config->pipe_bpp);
4045 pipe_config->fdi_lanes = lane;
4047 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4048 link_bw, &pipe_config->fdi_m_n);
4050 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4051 intel_crtc->pipe, pipe_config);
4052 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4053 pipe_config->pipe_bpp -= 2*3;
4054 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4055 pipe_config->pipe_bpp);
4056 needs_recompute = true;
4057 pipe_config->bw_constrained = true;
4062 if (needs_recompute)
4065 return setup_ok ? 0 : -EINVAL;
4068 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4069 struct intel_crtc_config *pipe_config)
4071 pipe_config->ips_enabled = i915_enable_ips &&
4072 hsw_crtc_supports_ips(crtc) &&
4073 pipe_config->pipe_bpp == 24;
4076 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4077 struct intel_crtc_config *pipe_config)
4079 struct drm_device *dev = crtc->base.dev;
4080 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4082 if (HAS_PCH_SPLIT(dev)) {
4083 /* FDI link clock is fixed at 2.7G */
4084 if (pipe_config->requested_mode.clock * 3
4085 > IRONLAKE_FDI_FREQ * 4)
4089 /* All interlaced capable intel hw wants timings in frames. Note though
4090 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4091 * timings, so we need to be careful not to clobber these.*/
4092 if (!pipe_config->timings_set)
4093 drm_mode_set_crtcinfo(adjusted_mode, 0);
4095 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4096 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4098 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4099 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4102 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4103 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4104 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4105 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4107 pipe_config->pipe_bpp = 8*3;
4111 hsw_compute_ips_config(crtc, pipe_config);
4113 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4114 * clock survives for now. */
4115 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4116 pipe_config->shared_dpll = crtc->config.shared_dpll;
4118 if (pipe_config->has_pch_encoder)
4119 return ironlake_fdi_compute_config(crtc, pipe_config);
4124 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4126 return 400000; /* FIXME */
4129 static int i945_get_display_clock_speed(struct drm_device *dev)
4134 static int i915_get_display_clock_speed(struct drm_device *dev)
4139 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4144 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4148 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4150 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4153 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4154 case GC_DISPLAY_CLOCK_333_MHZ:
4157 case GC_DISPLAY_CLOCK_190_200_MHZ:
4163 static int i865_get_display_clock_speed(struct drm_device *dev)
4168 static int i855_get_display_clock_speed(struct drm_device *dev)
4171 /* Assume that the hardware is in the high speed state. This
4172 * should be the default.
4174 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4175 case GC_CLOCK_133_200:
4176 case GC_CLOCK_100_200:
4178 case GC_CLOCK_166_250:
4180 case GC_CLOCK_100_133:
4184 /* Shouldn't happen */
4188 static int i830_get_display_clock_speed(struct drm_device *dev)
4194 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4196 while (*num > DATA_LINK_M_N_MASK ||
4197 *den > DATA_LINK_M_N_MASK) {
4203 static void compute_m_n(unsigned int m, unsigned int n,
4204 uint32_t *ret_m, uint32_t *ret_n)
4206 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4207 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4208 intel_reduce_m_n_ratio(ret_m, ret_n);
4212 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4213 int pixel_clock, int link_clock,
4214 struct intel_link_m_n *m_n)
4218 compute_m_n(bits_per_pixel * pixel_clock,
4219 link_clock * nlanes * 8,
4220 &m_n->gmch_m, &m_n->gmch_n);
4222 compute_m_n(pixel_clock, link_clock,
4223 &m_n->link_m, &m_n->link_n);
4226 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4228 if (i915_panel_use_ssc >= 0)
4229 return i915_panel_use_ssc != 0;
4230 return dev_priv->vbt.lvds_use_ssc
4231 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4234 static int vlv_get_refclk(struct drm_crtc *crtc)
4236 struct drm_device *dev = crtc->dev;
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 int refclk = 27000; /* for DP & HDMI */
4240 return 100000; /* only one validated so far */
4242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4244 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4245 if (intel_panel_use_ssc(dev_priv))
4249 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4256 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4258 struct drm_device *dev = crtc->dev;
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4262 if (IS_VALLEYVIEW(dev)) {
4263 refclk = vlv_get_refclk(crtc);
4264 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4265 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4266 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4267 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4269 } else if (!IS_GEN2(dev)) {
4278 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4280 return (1 << dpll->n) << 16 | dpll->m2;
4283 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4285 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4288 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4289 intel_clock_t *reduced_clock)
4291 struct drm_device *dev = crtc->base.dev;
4292 struct drm_i915_private *dev_priv = dev->dev_private;
4293 int pipe = crtc->pipe;
4296 if (IS_PINEVIEW(dev)) {
4297 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4299 fp2 = pnv_dpll_compute_fp(reduced_clock);
4301 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4303 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4306 I915_WRITE(FP0(pipe), fp);
4307 crtc->config.dpll_hw_state.fp0 = fp;
4309 crtc->lowfreq_avail = false;
4310 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4311 reduced_clock && i915_powersave) {
4312 I915_WRITE(FP1(pipe), fp2);
4313 crtc->config.dpll_hw_state.fp1 = fp2;
4314 crtc->lowfreq_avail = true;
4316 I915_WRITE(FP1(pipe), fp);
4317 crtc->config.dpll_hw_state.fp1 = fp;
4321 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4326 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4327 * and set it to a reasonable value instead.
4329 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4330 reg_val &= 0xffffff00;
4331 reg_val |= 0x00000030;
4332 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4334 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4335 reg_val &= 0x8cffffff;
4336 reg_val = 0x8c000000;
4337 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4339 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4340 reg_val &= 0xffffff00;
4341 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4343 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4344 reg_val &= 0x00ffffff;
4345 reg_val |= 0xb0000000;
4346 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4349 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4350 struct intel_link_m_n *m_n)
4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 int pipe = crtc->pipe;
4356 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4357 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4358 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4359 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4362 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4363 struct intel_link_m_n *m_n)
4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 int pipe = crtc->pipe;
4368 enum transcoder transcoder = crtc->config.cpu_transcoder;
4370 if (INTEL_INFO(dev)->gen >= 5) {
4371 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4372 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4373 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4374 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4376 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4377 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4378 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4379 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4383 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4385 if (crtc->config.has_pch_encoder)
4386 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4388 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4391 static void vlv_update_pll(struct intel_crtc *crtc)
4393 struct drm_device *dev = crtc->base.dev;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 struct intel_encoder *encoder;
4396 int pipe = crtc->pipe;
4398 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4400 u32 coreclk, reg_val, dpll_md;
4402 mutex_lock(&dev_priv->dpio_lock);
4404 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4406 bestn = crtc->config.dpll.n;
4407 bestm1 = crtc->config.dpll.m1;
4408 bestm2 = crtc->config.dpll.m2;
4409 bestp1 = crtc->config.dpll.p1;
4410 bestp2 = crtc->config.dpll.p2;
4412 /* See eDP HDMI DPIO driver vbios notes doc */
4414 /* PLL B needs special handling */
4416 vlv_pllb_recal_opamp(dev_priv);
4418 /* Set up Tx target for periodic Rcomp update */
4419 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4421 /* Disable target IRef on PLL */
4422 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4423 reg_val &= 0x00ffffff;
4424 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4426 /* Disable fast lock */
4427 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4429 /* Set idtafcrecal before PLL is enabled */
4430 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4431 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4432 mdiv |= ((bestn << DPIO_N_SHIFT));
4433 mdiv |= (1 << DPIO_K_SHIFT);
4436 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4437 * but we don't support that).
4438 * Note: don't use the DAC post divider as it seems unstable.
4440 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4441 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4443 mdiv |= DPIO_ENABLE_CALIBRATION;
4444 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4446 /* Set HBR and RBR LPF coefficients */
4447 if (crtc->config.port_clock == 162000 ||
4448 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4449 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4450 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4453 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4456 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4457 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4458 /* Use SSC source */
4460 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4463 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4465 } else { /* HDMI or VGA */
4466 /* Use bend source */
4468 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4471 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4475 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4476 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4477 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4478 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4479 coreclk |= 0x01000000;
4480 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4482 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4484 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4485 if (encoder->pre_pll_enable)
4486 encoder->pre_pll_enable(encoder);
4488 /* Enable DPIO clock input */
4489 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4490 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4492 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4494 dpll |= DPLL_VCO_ENABLE;
4495 crtc->config.dpll_hw_state.dpll = dpll;
4497 I915_WRITE(DPLL(pipe), dpll);
4498 POSTING_READ(DPLL(pipe));
4501 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4502 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4504 dpll_md = (crtc->config.pixel_multiplier - 1)
4505 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4506 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4508 I915_WRITE(DPLL_MD(pipe), dpll_md);
4509 POSTING_READ(DPLL_MD(pipe));
4511 if (crtc->config.has_dp_encoder)
4512 intel_dp_set_m_n(crtc);
4514 mutex_unlock(&dev_priv->dpio_lock);
4517 static void i9xx_update_pll(struct intel_crtc *crtc,
4518 intel_clock_t *reduced_clock,
4521 struct drm_device *dev = crtc->base.dev;
4522 struct drm_i915_private *dev_priv = dev->dev_private;
4525 struct dpll *clock = &crtc->config.dpll;
4527 i9xx_update_pll_dividers(crtc, reduced_clock);
4529 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4530 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4532 dpll = DPLL_VGA_MODE_DIS;
4534 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4535 dpll |= DPLLB_MODE_LVDS;
4537 dpll |= DPLLB_MODE_DAC_SERIAL;
4539 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4540 dpll |= (crtc->config.pixel_multiplier - 1)
4541 << SDVO_MULTIPLIER_SHIFT_HIRES;
4545 dpll |= DPLL_DVO_HIGH_SPEED;
4547 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4548 dpll |= DPLL_DVO_HIGH_SPEED;
4550 /* compute bitmask from p1 value */
4551 if (IS_PINEVIEW(dev))
4552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4555 if (IS_G4X(dev) && reduced_clock)
4556 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4558 switch (clock->p2) {
4560 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4563 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4566 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4569 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4572 if (INTEL_INFO(dev)->gen >= 4)
4573 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4575 if (crtc->config.sdvo_tv_clock)
4576 dpll |= PLL_REF_INPUT_TVCLKINBC;
4577 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4578 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4579 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4581 dpll |= PLL_REF_INPUT_DREFCLK;
4583 dpll |= DPLL_VCO_ENABLE;
4584 crtc->config.dpll_hw_state.dpll = dpll;
4586 if (INTEL_INFO(dev)->gen >= 4) {
4587 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4588 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4589 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4592 if (crtc->config.has_dp_encoder)
4593 intel_dp_set_m_n(crtc);
4596 static void i8xx_update_pll(struct intel_crtc *crtc,
4597 intel_clock_t *reduced_clock,
4600 struct drm_device *dev = crtc->base.dev;
4601 struct drm_i915_private *dev_priv = dev->dev_private;
4603 struct dpll *clock = &crtc->config.dpll;
4605 i9xx_update_pll_dividers(crtc, reduced_clock);
4607 dpll = DPLL_VGA_MODE_DIS;
4609 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4613 dpll |= PLL_P1_DIVIDE_BY_TWO;
4615 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4617 dpll |= PLL_P2_DIVIDE_BY_4;
4620 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4621 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4622 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4624 dpll |= PLL_REF_INPUT_DREFCLK;
4626 dpll |= DPLL_VCO_ENABLE;
4627 crtc->config.dpll_hw_state.dpll = dpll;
4630 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4632 struct drm_device *dev = intel_crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 enum pipe pipe = intel_crtc->pipe;
4635 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4636 struct drm_display_mode *adjusted_mode =
4637 &intel_crtc->config.adjusted_mode;
4638 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4639 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4641 /* We need to be careful not to changed the adjusted mode, for otherwise
4642 * the hw state checker will get angry at the mismatch. */
4643 crtc_vtotal = adjusted_mode->crtc_vtotal;
4644 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4646 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647 /* the chip adds 2 halflines automatically */
4649 crtc_vblank_end -= 1;
4650 vsyncshift = adjusted_mode->crtc_hsync_start
4651 - adjusted_mode->crtc_htotal / 2;
4656 if (INTEL_INFO(dev)->gen > 3)
4657 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4659 I915_WRITE(HTOTAL(cpu_transcoder),
4660 (adjusted_mode->crtc_hdisplay - 1) |
4661 ((adjusted_mode->crtc_htotal - 1) << 16));
4662 I915_WRITE(HBLANK(cpu_transcoder),
4663 (adjusted_mode->crtc_hblank_start - 1) |
4664 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4665 I915_WRITE(HSYNC(cpu_transcoder),
4666 (adjusted_mode->crtc_hsync_start - 1) |
4667 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4669 I915_WRITE(VTOTAL(cpu_transcoder),
4670 (adjusted_mode->crtc_vdisplay - 1) |
4671 ((crtc_vtotal - 1) << 16));
4672 I915_WRITE(VBLANK(cpu_transcoder),
4673 (adjusted_mode->crtc_vblank_start - 1) |
4674 ((crtc_vblank_end - 1) << 16));
4675 I915_WRITE(VSYNC(cpu_transcoder),
4676 (adjusted_mode->crtc_vsync_start - 1) |
4677 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4679 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4683 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684 (pipe == PIPE_B || pipe == PIPE_C))
4685 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4687 /* pipesrc controls the size that is scaled from, which should
4688 * always be the user's requested size.
4690 I915_WRITE(PIPESRC(pipe),
4691 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4694 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4695 struct intel_crtc_config *pipe_config)
4697 struct drm_device *dev = crtc->base.dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4702 tmp = I915_READ(HTOTAL(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HBLANK(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4708 tmp = I915_READ(HSYNC(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4712 tmp = I915_READ(VTOTAL(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VBLANK(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4718 tmp = I915_READ(VSYNC(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4722 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4723 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4724 pipe_config->adjusted_mode.crtc_vtotal += 1;
4725 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4728 tmp = I915_READ(PIPESRC(crtc->pipe));
4729 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4730 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4733 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4734 struct intel_crtc_config *pipe_config)
4736 struct drm_crtc *crtc = &intel_crtc->base;
4738 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4739 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4740 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4741 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4743 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4744 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4745 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4746 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4748 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4750 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4751 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4754 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4756 struct drm_device *dev = intel_crtc->base.dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4762 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4763 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4766 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4769 if (intel_crtc->config.requested_mode.clock >
4770 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4771 pipeconf |= PIPECONF_DOUBLE_WIDE;
4774 /* only g4x and later have fancy bpc/dither controls */
4775 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4776 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4777 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4778 pipeconf |= PIPECONF_DITHER_EN |
4779 PIPECONF_DITHER_TYPE_SP;
4781 switch (intel_crtc->config.pipe_bpp) {
4783 pipeconf |= PIPECONF_6BPC;
4786 pipeconf |= PIPECONF_8BPC;
4789 pipeconf |= PIPECONF_10BPC;
4792 /* Case prevented by intel_choose_pipe_bpp_dither. */
4797 if (HAS_PIPE_CXSR(dev)) {
4798 if (intel_crtc->lowfreq_avail) {
4799 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4800 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4802 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4806 if (!IS_GEN2(dev) &&
4807 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4808 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4810 pipeconf |= PIPECONF_PROGRESSIVE;
4812 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4813 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4815 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4816 POSTING_READ(PIPECONF(intel_crtc->pipe));
4819 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4821 struct drm_framebuffer *fb)
4823 struct drm_device *dev = crtc->dev;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4826 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4827 int pipe = intel_crtc->pipe;
4828 int plane = intel_crtc->plane;
4829 int refclk, num_connectors = 0;
4830 intel_clock_t clock, reduced_clock;
4832 bool ok, has_reduced_clock = false;
4833 bool is_lvds = false;
4834 struct intel_encoder *encoder;
4835 const intel_limit_t *limit;
4838 for_each_encoder_on_crtc(dev, crtc, encoder) {
4839 switch (encoder->type) {
4840 case INTEL_OUTPUT_LVDS:
4848 refclk = i9xx_get_refclk(crtc, num_connectors);
4851 * Returns a set of divisors for the desired target clock with the given
4852 * refclk, or FALSE. The returned values represent the clock equation:
4853 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4855 limit = intel_limit(crtc, refclk);
4856 ok = dev_priv->display.find_dpll(limit, crtc,
4857 intel_crtc->config.port_clock,
4858 refclk, NULL, &clock);
4859 if (!ok && !intel_crtc->config.clock_set) {
4860 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4864 /* Ensure that the cursor is valid for the new mode before changing... */
4865 intel_crtc_update_cursor(crtc, true);
4867 if (is_lvds && dev_priv->lvds_downclock_avail) {
4869 * Ensure we match the reduced clock's P to the target clock.
4870 * If the clocks don't match, we can't switch the display clock
4871 * by using the FP0/FP1. In such case we will disable the LVDS
4872 * downclock feature.
4875 dev_priv->display.find_dpll(limit, crtc,
4876 dev_priv->lvds_downclock,
4880 /* Compat-code for transition, will disappear. */
4881 if (!intel_crtc->config.clock_set) {
4882 intel_crtc->config.dpll.n = clock.n;
4883 intel_crtc->config.dpll.m1 = clock.m1;
4884 intel_crtc->config.dpll.m2 = clock.m2;
4885 intel_crtc->config.dpll.p1 = clock.p1;
4886 intel_crtc->config.dpll.p2 = clock.p2;
4890 i8xx_update_pll(intel_crtc,
4891 has_reduced_clock ? &reduced_clock : NULL,
4893 else if (IS_VALLEYVIEW(dev))
4894 vlv_update_pll(intel_crtc);
4896 i9xx_update_pll(intel_crtc,
4897 has_reduced_clock ? &reduced_clock : NULL,
4900 /* Set up the display plane register */
4901 dspcntr = DISPPLANE_GAMMA_ENABLE;
4903 if (!IS_VALLEYVIEW(dev)) {
4905 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4907 dspcntr |= DISPPLANE_SEL_PIPE_B;
4910 intel_set_pipe_timings(intel_crtc);
4912 /* pipesrc and dspsize control the size that is scaled from,
4913 * which should always be the user's requested size.
4915 I915_WRITE(DSPSIZE(plane),
4916 ((mode->vdisplay - 1) << 16) |
4917 (mode->hdisplay - 1));
4918 I915_WRITE(DSPPOS(plane), 0);
4920 i9xx_set_pipeconf(intel_crtc);
4922 I915_WRITE(DSPCNTR(plane), dspcntr);
4923 POSTING_READ(DSPCNTR(plane));
4925 ret = intel_pipe_set_base(crtc, x, y, fb);
4927 intel_update_watermarks(dev);
4932 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4933 struct intel_crtc_config *pipe_config)
4935 struct drm_device *dev = crtc->base.dev;
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4939 tmp = I915_READ(PFIT_CONTROL);
4941 if (INTEL_INFO(dev)->gen < 4) {
4942 if (crtc->pipe != PIPE_B)
4945 /* gen2/3 store dither state in pfit control, needs to match */
4946 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4948 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4952 if (!(tmp & PFIT_ENABLE))
4955 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4956 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4957 if (INTEL_INFO(dev)->gen < 5)
4958 pipe_config->gmch_pfit.lvds_border_bits =
4959 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4962 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4963 struct intel_crtc_config *pipe_config)
4965 struct drm_device *dev = crtc->base.dev;
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4969 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4970 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4972 tmp = I915_READ(PIPECONF(crtc->pipe));
4973 if (!(tmp & PIPECONF_ENABLE))
4976 intel_get_pipe_timings(crtc, pipe_config);
4978 i9xx_get_pfit_config(crtc, pipe_config);
4980 if (INTEL_INFO(dev)->gen >= 4) {
4981 tmp = I915_READ(DPLL_MD(crtc->pipe));
4982 pipe_config->pixel_multiplier =
4983 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4984 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4985 pipe_config->dpll_hw_state.dpll_md = tmp;
4986 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4987 tmp = I915_READ(DPLL(crtc->pipe));
4988 pipe_config->pixel_multiplier =
4989 ((tmp & SDVO_MULTIPLIER_MASK)
4990 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4992 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4993 * port and will be fixed up in the encoder->get_config
4995 pipe_config->pixel_multiplier = 1;
4997 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4998 if (!IS_VALLEYVIEW(dev)) {
4999 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5000 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5002 /* Mask out read-only status bits. */
5003 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5004 DPLL_PORTC_READY_MASK |
5005 DPLL_PORTB_READY_MASK);
5011 static void ironlake_init_pch_refclk(struct drm_device *dev)
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 struct drm_mode_config *mode_config = &dev->mode_config;
5015 struct intel_encoder *encoder;
5017 bool has_lvds = false;
5018 bool has_cpu_edp = false;
5019 bool has_panel = false;
5020 bool has_ck505 = false;
5021 bool can_ssc = false;
5023 /* We need to take the global config into account */
5024 list_for_each_entry(encoder, &mode_config->encoder_list,
5026 switch (encoder->type) {
5027 case INTEL_OUTPUT_LVDS:
5031 case INTEL_OUTPUT_EDP:
5033 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5039 if (HAS_PCH_IBX(dev)) {
5040 has_ck505 = dev_priv->vbt.display_clock_mode;
5041 can_ssc = has_ck505;
5047 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5048 has_panel, has_lvds, has_ck505);
5050 /* Ironlake: try to setup display ref clock before DPLL
5051 * enabling. This is only under driver's control after
5052 * PCH B stepping, previous chipset stepping should be
5053 * ignoring this setting.
5055 val = I915_READ(PCH_DREF_CONTROL);
5057 /* As we must carefully and slowly disable/enable each source in turn,
5058 * compute the final state we want first and check if we need to
5059 * make any changes at all.
5062 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5064 final |= DREF_NONSPREAD_CK505_ENABLE;
5066 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5068 final &= ~DREF_SSC_SOURCE_MASK;
5069 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5070 final &= ~DREF_SSC1_ENABLE;
5073 final |= DREF_SSC_SOURCE_ENABLE;
5075 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5076 final |= DREF_SSC1_ENABLE;
5079 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5080 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5082 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5084 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5086 final |= DREF_SSC_SOURCE_DISABLE;
5087 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5093 /* Always enable nonspread source */
5094 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5097 val |= DREF_NONSPREAD_CK505_ENABLE;
5099 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5102 val &= ~DREF_SSC_SOURCE_MASK;
5103 val |= DREF_SSC_SOURCE_ENABLE;
5105 /* SSC must be turned on before enabling the CPU output */
5106 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5107 DRM_DEBUG_KMS("Using SSC on panel\n");
5108 val |= DREF_SSC1_ENABLE;
5110 val &= ~DREF_SSC1_ENABLE;
5112 /* Get SSC going before enabling the outputs */
5113 I915_WRITE(PCH_DREF_CONTROL, val);
5114 POSTING_READ(PCH_DREF_CONTROL);
5117 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5119 /* Enable CPU source on CPU attached eDP */
5121 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5122 DRM_DEBUG_KMS("Using SSC on eDP\n");
5123 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5126 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5128 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5130 I915_WRITE(PCH_DREF_CONTROL, val);
5131 POSTING_READ(PCH_DREF_CONTROL);
5134 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5136 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5138 /* Turn off CPU output */
5139 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5141 I915_WRITE(PCH_DREF_CONTROL, val);
5142 POSTING_READ(PCH_DREF_CONTROL);
5145 /* Turn off the SSC source */
5146 val &= ~DREF_SSC_SOURCE_MASK;
5147 val |= DREF_SSC_SOURCE_DISABLE;
5150 val &= ~DREF_SSC1_ENABLE;
5152 I915_WRITE(PCH_DREF_CONTROL, val);
5153 POSTING_READ(PCH_DREF_CONTROL);
5157 BUG_ON(val != final);
5160 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5161 static void lpt_init_pch_refclk(struct drm_device *dev)
5163 struct drm_i915_private *dev_priv = dev->dev_private;
5164 struct drm_mode_config *mode_config = &dev->mode_config;
5165 struct intel_encoder *encoder;
5166 bool has_vga = false;
5167 bool is_sdv = false;
5170 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5171 switch (encoder->type) {
5172 case INTEL_OUTPUT_ANALOG:
5181 mutex_lock(&dev_priv->dpio_lock);
5183 /* XXX: Rip out SDV support once Haswell ships for real. */
5184 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5187 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5188 tmp &= ~SBI_SSCCTL_DISABLE;
5189 tmp |= SBI_SSCCTL_PATHALT;
5190 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5194 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5195 tmp &= ~SBI_SSCCTL_PATHALT;
5196 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5199 tmp = I915_READ(SOUTH_CHICKEN2);
5200 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5201 I915_WRITE(SOUTH_CHICKEN2, tmp);
5203 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5204 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5205 DRM_ERROR("FDI mPHY reset assert timeout\n");
5207 tmp = I915_READ(SOUTH_CHICKEN2);
5208 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5209 I915_WRITE(SOUTH_CHICKEN2, tmp);
5211 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5212 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5214 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5217 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5218 tmp &= ~(0xFF << 24);
5219 tmp |= (0x12 << 24);
5220 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5223 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5225 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5228 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5230 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5232 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5234 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5237 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5238 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5239 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5241 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5242 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5243 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5245 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5247 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5249 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5251 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5254 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5255 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5256 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5258 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5259 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5260 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5263 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5266 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5268 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5271 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5274 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5277 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5279 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5282 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5284 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5285 tmp &= ~(0xFF << 16);
5286 tmp |= (0x1C << 16);
5287 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5289 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5290 tmp &= ~(0xFF << 16);
5291 tmp |= (0x1C << 16);
5292 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5295 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5297 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5299 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5301 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5303 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5304 tmp &= ~(0xF << 28);
5306 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5308 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5309 tmp &= ~(0xF << 28);
5311 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5314 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5315 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5316 tmp |= SBI_DBUFF0_ENABLE;
5317 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5319 mutex_unlock(&dev_priv->dpio_lock);
5323 * Initialize reference clocks when the driver loads
5325 void intel_init_pch_refclk(struct drm_device *dev)
5327 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5328 ironlake_init_pch_refclk(dev);
5329 else if (HAS_PCH_LPT(dev))
5330 lpt_init_pch_refclk(dev);
5333 static int ironlake_get_refclk(struct drm_crtc *crtc)
5335 struct drm_device *dev = crtc->dev;
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct intel_encoder *encoder;
5338 int num_connectors = 0;
5339 bool is_lvds = false;
5341 for_each_encoder_on_crtc(dev, crtc, encoder) {
5342 switch (encoder->type) {
5343 case INTEL_OUTPUT_LVDS:
5350 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5351 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5352 dev_priv->vbt.lvds_ssc_freq);
5353 return dev_priv->vbt.lvds_ssc_freq * 1000;
5359 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5361 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5363 int pipe = intel_crtc->pipe;
5368 switch (intel_crtc->config.pipe_bpp) {
5370 val |= PIPECONF_6BPC;
5373 val |= PIPECONF_8BPC;
5376 val |= PIPECONF_10BPC;
5379 val |= PIPECONF_12BPC;
5382 /* Case prevented by intel_choose_pipe_bpp_dither. */
5386 if (intel_crtc->config.dither)
5387 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5389 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5390 val |= PIPECONF_INTERLACED_ILK;
5392 val |= PIPECONF_PROGRESSIVE;
5394 if (intel_crtc->config.limited_color_range)
5395 val |= PIPECONF_COLOR_RANGE_SELECT;
5397 I915_WRITE(PIPECONF(pipe), val);
5398 POSTING_READ(PIPECONF(pipe));
5402 * Set up the pipe CSC unit.
5404 * Currently only full range RGB to limited range RGB conversion
5405 * is supported, but eventually this should handle various
5406 * RGB<->YCbCr scenarios as well.
5408 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5410 struct drm_device *dev = crtc->dev;
5411 struct drm_i915_private *dev_priv = dev->dev_private;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413 int pipe = intel_crtc->pipe;
5414 uint16_t coeff = 0x7800; /* 1.0 */
5417 * TODO: Check what kind of values actually come out of the pipe
5418 * with these coeff/postoff values and adjust to get the best
5419 * accuracy. Perhaps we even need to take the bpc value into
5423 if (intel_crtc->config.limited_color_range)
5424 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5427 * GY/GU and RY/RU should be the other way around according
5428 * to BSpec, but reality doesn't agree. Just set them up in
5429 * a way that results in the correct picture.
5431 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5432 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5434 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5435 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5437 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5438 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5440 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5441 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5442 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5444 if (INTEL_INFO(dev)->gen > 6) {
5445 uint16_t postoff = 0;
5447 if (intel_crtc->config.limited_color_range)
5448 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5450 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5451 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5452 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5454 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5456 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5458 if (intel_crtc->config.limited_color_range)
5459 mode |= CSC_BLACK_SCREEN_OFFSET;
5461 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5465 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5467 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5469 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5474 if (intel_crtc->config.dither)
5475 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5477 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5478 val |= PIPECONF_INTERLACED_ILK;
5480 val |= PIPECONF_PROGRESSIVE;
5482 I915_WRITE(PIPECONF(cpu_transcoder), val);
5483 POSTING_READ(PIPECONF(cpu_transcoder));
5485 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5486 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5489 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5490 intel_clock_t *clock,
5491 bool *has_reduced_clock,
5492 intel_clock_t *reduced_clock)
5494 struct drm_device *dev = crtc->dev;
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 struct intel_encoder *intel_encoder;
5498 const intel_limit_t *limit;
5499 bool ret, is_lvds = false;
5501 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5502 switch (intel_encoder->type) {
5503 case INTEL_OUTPUT_LVDS:
5509 refclk = ironlake_get_refclk(crtc);
5512 * Returns a set of divisors for the desired target clock with the given
5513 * refclk, or FALSE. The returned values represent the clock equation:
5514 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5516 limit = intel_limit(crtc, refclk);
5517 ret = dev_priv->display.find_dpll(limit, crtc,
5518 to_intel_crtc(crtc)->config.port_clock,
5519 refclk, NULL, clock);
5523 if (is_lvds && dev_priv->lvds_downclock_avail) {
5525 * Ensure we match the reduced clock's P to the target clock.
5526 * If the clocks don't match, we can't switch the display clock
5527 * by using the FP0/FP1. In such case we will disable the LVDS
5528 * downclock feature.
5530 *has_reduced_clock =
5531 dev_priv->display.find_dpll(limit, crtc,
5532 dev_priv->lvds_downclock,
5540 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5542 struct drm_i915_private *dev_priv = dev->dev_private;
5545 temp = I915_READ(SOUTH_CHICKEN1);
5546 if (temp & FDI_BC_BIFURCATION_SELECT)
5549 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5550 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5552 temp |= FDI_BC_BIFURCATION_SELECT;
5553 DRM_DEBUG_KMS("enabling fdi C rx\n");
5554 I915_WRITE(SOUTH_CHICKEN1, temp);
5555 POSTING_READ(SOUTH_CHICKEN1);
5558 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5560 struct drm_device *dev = intel_crtc->base.dev;
5561 struct drm_i915_private *dev_priv = dev->dev_private;
5563 switch (intel_crtc->pipe) {
5567 if (intel_crtc->config.fdi_lanes > 2)
5568 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5570 cpt_enable_fdi_bc_bifurcation(dev);
5574 cpt_enable_fdi_bc_bifurcation(dev);
5582 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5585 * Account for spread spectrum to avoid
5586 * oversubscribing the link. Max center spread
5587 * is 2.5%; use 5% for safety's sake.
5589 u32 bps = target_clock * bpp * 21 / 20;
5590 return bps / (link_bw * 8) + 1;
5593 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5595 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5598 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5600 intel_clock_t *reduced_clock, u32 *fp2)
5602 struct drm_crtc *crtc = &intel_crtc->base;
5603 struct drm_device *dev = crtc->dev;
5604 struct drm_i915_private *dev_priv = dev->dev_private;
5605 struct intel_encoder *intel_encoder;
5607 int factor, num_connectors = 0;
5608 bool is_lvds = false, is_sdvo = false;
5610 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5611 switch (intel_encoder->type) {
5612 case INTEL_OUTPUT_LVDS:
5615 case INTEL_OUTPUT_SDVO:
5616 case INTEL_OUTPUT_HDMI:
5624 /* Enable autotuning of the PLL clock (if permissible) */
5627 if ((intel_panel_use_ssc(dev_priv) &&
5628 dev_priv->vbt.lvds_ssc_freq == 100) ||
5629 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5631 } else if (intel_crtc->config.sdvo_tv_clock)
5634 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5637 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5643 dpll |= DPLLB_MODE_LVDS;
5645 dpll |= DPLLB_MODE_DAC_SERIAL;
5647 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5648 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5651 dpll |= DPLL_DVO_HIGH_SPEED;
5652 if (intel_crtc->config.has_dp_encoder)
5653 dpll |= DPLL_DVO_HIGH_SPEED;
5655 /* compute bitmask from p1 value */
5656 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5658 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5660 switch (intel_crtc->config.dpll.p2) {
5662 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5665 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5668 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5671 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5675 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5676 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5678 dpll |= PLL_REF_INPUT_DREFCLK;
5680 return dpll | DPLL_VCO_ENABLE;
5683 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5685 struct drm_framebuffer *fb)
5687 struct drm_device *dev = crtc->dev;
5688 struct drm_i915_private *dev_priv = dev->dev_private;
5689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5690 int pipe = intel_crtc->pipe;
5691 int plane = intel_crtc->plane;
5692 int num_connectors = 0;
5693 intel_clock_t clock, reduced_clock;
5694 u32 dpll = 0, fp = 0, fp2 = 0;
5695 bool ok, has_reduced_clock = false;
5696 bool is_lvds = false;
5697 struct intel_encoder *encoder;
5698 struct intel_shared_dpll *pll;
5701 for_each_encoder_on_crtc(dev, crtc, encoder) {
5702 switch (encoder->type) {
5703 case INTEL_OUTPUT_LVDS:
5711 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5712 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5714 ok = ironlake_compute_clocks(crtc, &clock,
5715 &has_reduced_clock, &reduced_clock);
5716 if (!ok && !intel_crtc->config.clock_set) {
5717 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5720 /* Compat-code for transition, will disappear. */
5721 if (!intel_crtc->config.clock_set) {
5722 intel_crtc->config.dpll.n = clock.n;
5723 intel_crtc->config.dpll.m1 = clock.m1;
5724 intel_crtc->config.dpll.m2 = clock.m2;
5725 intel_crtc->config.dpll.p1 = clock.p1;
5726 intel_crtc->config.dpll.p2 = clock.p2;
5729 /* Ensure that the cursor is valid for the new mode before changing... */
5730 intel_crtc_update_cursor(crtc, true);
5732 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5733 if (intel_crtc->config.has_pch_encoder) {
5734 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5735 if (has_reduced_clock)
5736 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5738 dpll = ironlake_compute_dpll(intel_crtc,
5739 &fp, &reduced_clock,
5740 has_reduced_clock ? &fp2 : NULL);
5742 intel_crtc->config.dpll_hw_state.dpll = dpll;
5743 intel_crtc->config.dpll_hw_state.fp0 = fp;
5744 if (has_reduced_clock)
5745 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5747 intel_crtc->config.dpll_hw_state.fp1 = fp;
5749 pll = intel_get_shared_dpll(intel_crtc);
5751 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5756 intel_put_shared_dpll(intel_crtc);
5758 if (intel_crtc->config.has_dp_encoder)
5759 intel_dp_set_m_n(intel_crtc);
5761 if (is_lvds && has_reduced_clock && i915_powersave)
5762 intel_crtc->lowfreq_avail = true;
5764 intel_crtc->lowfreq_avail = false;
5766 if (intel_crtc->config.has_pch_encoder) {
5767 pll = intel_crtc_to_shared_dpll(intel_crtc);
5771 intel_set_pipe_timings(intel_crtc);
5773 if (intel_crtc->config.has_pch_encoder) {
5774 intel_cpu_transcoder_set_m_n(intel_crtc,
5775 &intel_crtc->config.fdi_m_n);
5778 if (IS_IVYBRIDGE(dev))
5779 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5781 ironlake_set_pipeconf(crtc);
5783 /* Set up the display plane register */
5784 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5785 POSTING_READ(DSPCNTR(plane));
5787 ret = intel_pipe_set_base(crtc, x, y, fb);
5789 intel_update_watermarks(dev);
5794 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5795 struct intel_crtc_config *pipe_config)
5797 struct drm_device *dev = crtc->base.dev;
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799 enum transcoder transcoder = pipe_config->cpu_transcoder;
5801 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5802 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5803 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5805 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5806 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5807 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5810 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5811 struct intel_crtc_config *pipe_config)
5813 struct drm_device *dev = crtc->base.dev;
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5817 tmp = I915_READ(PF_CTL(crtc->pipe));
5819 if (tmp & PF_ENABLE) {
5820 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5821 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5823 /* We currently do not free assignements of panel fitters on
5824 * ivb/hsw (since we don't use the higher upscaling modes which
5825 * differentiates them) so just WARN about this case for now. */
5827 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5828 PF_PIPE_SEL_IVB(crtc->pipe));
5833 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5834 struct intel_crtc_config *pipe_config)
5836 struct drm_device *dev = crtc->base.dev;
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5840 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5841 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5843 tmp = I915_READ(PIPECONF(crtc->pipe));
5844 if (!(tmp & PIPECONF_ENABLE))
5847 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5848 struct intel_shared_dpll *pll;
5850 pipe_config->has_pch_encoder = true;
5852 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5853 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5854 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5856 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5858 if (HAS_PCH_IBX(dev_priv->dev)) {
5859 pipe_config->shared_dpll =
5860 (enum intel_dpll_id) crtc->pipe;
5862 tmp = I915_READ(PCH_DPLL_SEL);
5863 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5864 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5866 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5869 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5871 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5872 &pipe_config->dpll_hw_state));
5874 tmp = pipe_config->dpll_hw_state.dpll;
5875 pipe_config->pixel_multiplier =
5876 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5877 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5879 pipe_config->pixel_multiplier = 1;
5882 intel_get_pipe_timings(crtc, pipe_config);
5884 ironlake_get_pfit_config(crtc, pipe_config);
5889 static void haswell_modeset_global_resources(struct drm_device *dev)
5891 bool enable = false;
5892 struct intel_crtc *crtc;
5894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5895 if (!crtc->base.enabled)
5898 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5899 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5903 intel_set_power_well(dev, enable);
5906 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5908 struct drm_framebuffer *fb)
5910 struct drm_device *dev = crtc->dev;
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5913 int plane = intel_crtc->plane;
5916 if (!intel_ddi_pll_mode_set(crtc))
5919 /* Ensure that the cursor is valid for the new mode before changing... */
5920 intel_crtc_update_cursor(crtc, true);
5922 if (intel_crtc->config.has_dp_encoder)
5923 intel_dp_set_m_n(intel_crtc);
5925 intel_crtc->lowfreq_avail = false;
5927 intel_set_pipe_timings(intel_crtc);
5929 if (intel_crtc->config.has_pch_encoder) {
5930 intel_cpu_transcoder_set_m_n(intel_crtc,
5931 &intel_crtc->config.fdi_m_n);
5934 haswell_set_pipeconf(crtc);
5936 intel_set_pipe_csc(crtc);
5938 /* Set up the display plane register */
5939 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5940 POSTING_READ(DSPCNTR(plane));
5942 ret = intel_pipe_set_base(crtc, x, y, fb);
5944 intel_update_watermarks(dev);
5949 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5950 struct intel_crtc_config *pipe_config)
5952 struct drm_device *dev = crtc->base.dev;
5953 struct drm_i915_private *dev_priv = dev->dev_private;
5954 enum intel_display_power_domain pfit_domain;
5957 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5958 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5960 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5961 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5962 enum pipe trans_edp_pipe;
5963 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5965 WARN(1, "unknown pipe linked to edp transcoder\n");
5966 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5967 case TRANS_DDI_EDP_INPUT_A_ON:
5968 trans_edp_pipe = PIPE_A;
5970 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5971 trans_edp_pipe = PIPE_B;
5973 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5974 trans_edp_pipe = PIPE_C;
5978 if (trans_edp_pipe == crtc->pipe)
5979 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5982 if (!intel_display_power_enabled(dev,
5983 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5986 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5987 if (!(tmp & PIPECONF_ENABLE))
5991 * Haswell has only FDI/PCH transcoder A. It is which is connected to
5992 * DDI E. So just check whether this pipe is wired to DDI E and whether
5993 * the PCH transcoder is on.
5995 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5996 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5997 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5998 pipe_config->has_pch_encoder = true;
6000 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6001 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6002 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6004 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6007 intel_get_pipe_timings(crtc, pipe_config);
6009 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6010 if (intel_display_power_enabled(dev, pfit_domain))
6011 ironlake_get_pfit_config(crtc, pipe_config);
6013 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6014 (I915_READ(IPS_CTL) & IPS_ENABLE);
6016 pipe_config->pixel_multiplier = 1;
6021 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6023 struct drm_framebuffer *fb)
6025 struct drm_device *dev = crtc->dev;
6026 struct drm_i915_private *dev_priv = dev->dev_private;
6027 struct drm_encoder_helper_funcs *encoder_funcs;
6028 struct intel_encoder *encoder;
6029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6030 struct drm_display_mode *adjusted_mode =
6031 &intel_crtc->config.adjusted_mode;
6032 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6033 int pipe = intel_crtc->pipe;
6036 drm_vblank_pre_modeset(dev, pipe);
6038 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6040 drm_vblank_post_modeset(dev, pipe);
6045 for_each_encoder_on_crtc(dev, crtc, encoder) {
6046 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6047 encoder->base.base.id,
6048 drm_get_encoder_name(&encoder->base),
6049 mode->base.id, mode->name);
6050 if (encoder->mode_set) {
6051 encoder->mode_set(encoder);
6053 encoder_funcs = encoder->base.helper_private;
6054 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6061 static bool intel_eld_uptodate(struct drm_connector *connector,
6062 int reg_eldv, uint32_t bits_eldv,
6063 int reg_elda, uint32_t bits_elda,
6066 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6067 uint8_t *eld = connector->eld;
6070 i = I915_READ(reg_eldv);
6079 i = I915_READ(reg_elda);
6081 I915_WRITE(reg_elda, i);
6083 for (i = 0; i < eld[2]; i++)
6084 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6090 static void g4x_write_eld(struct drm_connector *connector,
6091 struct drm_crtc *crtc)
6093 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6094 uint8_t *eld = connector->eld;
6099 i = I915_READ(G4X_AUD_VID_DID);
6101 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6102 eldv = G4X_ELDV_DEVCL_DEVBLC;
6104 eldv = G4X_ELDV_DEVCTG;
6106 if (intel_eld_uptodate(connector,
6107 G4X_AUD_CNTL_ST, eldv,
6108 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6109 G4X_HDMIW_HDMIEDID))
6112 i = I915_READ(G4X_AUD_CNTL_ST);
6113 i &= ~(eldv | G4X_ELD_ADDR);
6114 len = (i >> 9) & 0x1f; /* ELD buffer size */
6115 I915_WRITE(G4X_AUD_CNTL_ST, i);
6120 len = min_t(uint8_t, eld[2], len);
6121 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6122 for (i = 0; i < len; i++)
6123 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6125 i = I915_READ(G4X_AUD_CNTL_ST);
6127 I915_WRITE(G4X_AUD_CNTL_ST, i);
6130 static void haswell_write_eld(struct drm_connector *connector,
6131 struct drm_crtc *crtc)
6133 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6134 uint8_t *eld = connector->eld;
6135 struct drm_device *dev = crtc->dev;
6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6140 int pipe = to_intel_crtc(crtc)->pipe;
6143 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6144 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6145 int aud_config = HSW_AUD_CFG(pipe);
6146 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6149 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6151 /* Audio output enable */
6152 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6153 tmp = I915_READ(aud_cntrl_st2);
6154 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6155 I915_WRITE(aud_cntrl_st2, tmp);
6157 /* Wait for 1 vertical blank */
6158 intel_wait_for_vblank(dev, pipe);
6160 /* Set ELD valid state */
6161 tmp = I915_READ(aud_cntrl_st2);
6162 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6163 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6164 I915_WRITE(aud_cntrl_st2, tmp);
6165 tmp = I915_READ(aud_cntrl_st2);
6166 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6168 /* Enable HDMI mode */
6169 tmp = I915_READ(aud_config);
6170 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6171 /* clear N_programing_enable and N_value_index */
6172 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6173 I915_WRITE(aud_config, tmp);
6175 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6177 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6178 intel_crtc->eld_vld = true;
6180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6181 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6182 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6183 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6185 I915_WRITE(aud_config, 0);
6187 if (intel_eld_uptodate(connector,
6188 aud_cntrl_st2, eldv,
6189 aud_cntl_st, IBX_ELD_ADDRESS,
6193 i = I915_READ(aud_cntrl_st2);
6195 I915_WRITE(aud_cntrl_st2, i);
6200 i = I915_READ(aud_cntl_st);
6201 i &= ~IBX_ELD_ADDRESS;
6202 I915_WRITE(aud_cntl_st, i);
6203 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6204 DRM_DEBUG_DRIVER("port num:%d\n", i);
6206 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6207 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6208 for (i = 0; i < len; i++)
6209 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6211 i = I915_READ(aud_cntrl_st2);
6213 I915_WRITE(aud_cntrl_st2, i);
6217 static void ironlake_write_eld(struct drm_connector *connector,
6218 struct drm_crtc *crtc)
6220 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6221 uint8_t *eld = connector->eld;
6229 int pipe = to_intel_crtc(crtc)->pipe;
6231 if (HAS_PCH_IBX(connector->dev)) {
6232 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6233 aud_config = IBX_AUD_CFG(pipe);
6234 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6235 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6237 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6238 aud_config = CPT_AUD_CFG(pipe);
6239 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6240 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6243 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6245 i = I915_READ(aud_cntl_st);
6246 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6248 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6249 /* operate blindly on all ports */
6250 eldv = IBX_ELD_VALIDB;
6251 eldv |= IBX_ELD_VALIDB << 4;
6252 eldv |= IBX_ELD_VALIDB << 8;
6254 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6255 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6259 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6260 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6261 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6263 I915_WRITE(aud_config, 0);
6265 if (intel_eld_uptodate(connector,
6266 aud_cntrl_st2, eldv,
6267 aud_cntl_st, IBX_ELD_ADDRESS,
6271 i = I915_READ(aud_cntrl_st2);
6273 I915_WRITE(aud_cntrl_st2, i);
6278 i = I915_READ(aud_cntl_st);
6279 i &= ~IBX_ELD_ADDRESS;
6280 I915_WRITE(aud_cntl_st, i);
6282 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6283 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6284 for (i = 0; i < len; i++)
6285 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6287 i = I915_READ(aud_cntrl_st2);
6289 I915_WRITE(aud_cntrl_st2, i);
6292 void intel_write_eld(struct drm_encoder *encoder,
6293 struct drm_display_mode *mode)
6295 struct drm_crtc *crtc = encoder->crtc;
6296 struct drm_connector *connector;
6297 struct drm_device *dev = encoder->dev;
6298 struct drm_i915_private *dev_priv = dev->dev_private;
6300 connector = drm_select_eld(encoder, mode);
6304 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6306 drm_get_connector_name(connector),
6307 connector->encoder->base.id,
6308 drm_get_encoder_name(connector->encoder));
6310 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6312 if (dev_priv->display.write_eld)
6313 dev_priv->display.write_eld(connector, crtc);
6316 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6317 void intel_crtc_load_lut(struct drm_crtc *crtc)
6319 struct drm_device *dev = crtc->dev;
6320 struct drm_i915_private *dev_priv = dev->dev_private;
6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6322 enum pipe pipe = intel_crtc->pipe;
6323 int palreg = PALETTE(pipe);
6325 bool reenable_ips = false;
6327 /* The clocks have to be on to load the palette. */
6328 if (!crtc->enabled || !intel_crtc->active)
6331 if (!HAS_PCH_SPLIT(dev_priv->dev))
6332 assert_pll_enabled(dev_priv, pipe);
6334 /* use legacy palette for Ironlake */
6335 if (HAS_PCH_SPLIT(dev))
6336 palreg = LGC_PALETTE(pipe);
6338 /* Workaround : Do not read or write the pipe palette/gamma data while
6339 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6341 if (intel_crtc->config.ips_enabled &&
6342 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6343 GAMMA_MODE_MODE_SPLIT)) {
6344 hsw_disable_ips(intel_crtc);
6345 reenable_ips = true;
6348 for (i = 0; i < 256; i++) {
6349 I915_WRITE(palreg + 4 * i,
6350 (intel_crtc->lut_r[i] << 16) |
6351 (intel_crtc->lut_g[i] << 8) |
6352 intel_crtc->lut_b[i]);
6356 hsw_enable_ips(intel_crtc);
6359 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6361 struct drm_device *dev = crtc->dev;
6362 struct drm_i915_private *dev_priv = dev->dev_private;
6363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364 bool visible = base != 0;
6367 if (intel_crtc->cursor_visible == visible)
6370 cntl = I915_READ(_CURACNTR);
6372 /* On these chipsets we can only modify the base whilst
6373 * the cursor is disabled.
6375 I915_WRITE(_CURABASE, base);
6377 cntl &= ~(CURSOR_FORMAT_MASK);
6378 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6379 cntl |= CURSOR_ENABLE |
6380 CURSOR_GAMMA_ENABLE |
6383 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6384 I915_WRITE(_CURACNTR, cntl);
6386 intel_crtc->cursor_visible = visible;
6389 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6391 struct drm_device *dev = crtc->dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6394 int pipe = intel_crtc->pipe;
6395 bool visible = base != 0;
6397 if (intel_crtc->cursor_visible != visible) {
6398 uint32_t cntl = I915_READ(CURCNTR(pipe));
6400 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6401 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6402 cntl |= pipe << 28; /* Connect to correct pipe */
6404 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6405 cntl |= CURSOR_MODE_DISABLE;
6407 I915_WRITE(CURCNTR(pipe), cntl);
6409 intel_crtc->cursor_visible = visible;
6411 /* and commit changes on next vblank */
6412 I915_WRITE(CURBASE(pipe), base);
6415 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6417 struct drm_device *dev = crtc->dev;
6418 struct drm_i915_private *dev_priv = dev->dev_private;
6419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420 int pipe = intel_crtc->pipe;
6421 bool visible = base != 0;
6423 if (intel_crtc->cursor_visible != visible) {
6424 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6426 cntl &= ~CURSOR_MODE;
6427 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6429 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6430 cntl |= CURSOR_MODE_DISABLE;
6432 if (IS_HASWELL(dev))
6433 cntl |= CURSOR_PIPE_CSC_ENABLE;
6434 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6436 intel_crtc->cursor_visible = visible;
6438 /* and commit changes on next vblank */
6439 I915_WRITE(CURBASE_IVB(pipe), base);
6442 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6443 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6446 struct drm_device *dev = crtc->dev;
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6449 int pipe = intel_crtc->pipe;
6450 int x = intel_crtc->cursor_x;
6451 int y = intel_crtc->cursor_y;
6457 if (on && crtc->enabled && crtc->fb) {
6458 base = intel_crtc->cursor_addr;
6459 if (x > (int) crtc->fb->width)
6462 if (y > (int) crtc->fb->height)
6468 if (x + intel_crtc->cursor_width < 0)
6471 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6474 pos |= x << CURSOR_X_SHIFT;
6477 if (y + intel_crtc->cursor_height < 0)
6480 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6483 pos |= y << CURSOR_Y_SHIFT;
6485 visible = base != 0;
6486 if (!visible && !intel_crtc->cursor_visible)
6489 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6490 I915_WRITE(CURPOS_IVB(pipe), pos);
6491 ivb_update_cursor(crtc, base);
6493 I915_WRITE(CURPOS(pipe), pos);
6494 if (IS_845G(dev) || IS_I865G(dev))
6495 i845_update_cursor(crtc, base);
6497 i9xx_update_cursor(crtc, base);
6501 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6502 struct drm_file *file,
6504 uint32_t width, uint32_t height)
6506 struct drm_device *dev = crtc->dev;
6507 struct drm_i915_private *dev_priv = dev->dev_private;
6508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6509 struct drm_i915_gem_object *obj;
6513 /* if we want to turn off the cursor ignore width and height */
6515 DRM_DEBUG_KMS("cursor off\n");
6518 mutex_lock(&dev->struct_mutex);
6522 /* Currently we only support 64x64 cursors */
6523 if (width != 64 || height != 64) {
6524 DRM_ERROR("we currently only support 64x64 cursors\n");
6528 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6529 if (&obj->base == NULL)
6532 if (obj->base.size < width * height * 4) {
6533 DRM_ERROR("buffer is to small\n");
6538 /* we only need to pin inside GTT if cursor is non-phy */
6539 mutex_lock(&dev->struct_mutex);
6540 if (!dev_priv->info->cursor_needs_physical) {
6543 if (obj->tiling_mode) {
6544 DRM_ERROR("cursor cannot be tiled\n");
6549 /* Note that the w/a also requires 2 PTE of padding following
6550 * the bo. We currently fill all unused PTE with the shadow
6551 * page and so we should always have valid PTE following the
6552 * cursor preventing the VT-d warning.
6555 if (need_vtd_wa(dev))
6556 alignment = 64*1024;
6558 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6560 DRM_ERROR("failed to move cursor bo into the GTT\n");
6564 ret = i915_gem_object_put_fence(obj);
6566 DRM_ERROR("failed to release fence for cursor");
6570 addr = obj->gtt_offset;
6572 int align = IS_I830(dev) ? 16 * 1024 : 256;
6573 ret = i915_gem_attach_phys_object(dev, obj,
6574 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6577 DRM_ERROR("failed to attach phys object\n");
6580 addr = obj->phys_obj->handle->busaddr;
6584 I915_WRITE(CURSIZE, (height << 12) | width);
6587 if (intel_crtc->cursor_bo) {
6588 if (dev_priv->info->cursor_needs_physical) {
6589 if (intel_crtc->cursor_bo != obj)
6590 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6592 i915_gem_object_unpin(intel_crtc->cursor_bo);
6593 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6596 mutex_unlock(&dev->struct_mutex);
6598 intel_crtc->cursor_addr = addr;
6599 intel_crtc->cursor_bo = obj;
6600 intel_crtc->cursor_width = width;
6601 intel_crtc->cursor_height = height;
6603 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6607 i915_gem_object_unpin(obj);
6609 mutex_unlock(&dev->struct_mutex);
6611 drm_gem_object_unreference_unlocked(&obj->base);
6615 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6619 intel_crtc->cursor_x = x;
6620 intel_crtc->cursor_y = y;
6622 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6627 /** Sets the color ramps on behalf of RandR */
6628 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6629 u16 blue, int regno)
6631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6633 intel_crtc->lut_r[regno] = red >> 8;
6634 intel_crtc->lut_g[regno] = green >> 8;
6635 intel_crtc->lut_b[regno] = blue >> 8;
6638 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6639 u16 *blue, int regno)
6641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643 *red = intel_crtc->lut_r[regno] << 8;
6644 *green = intel_crtc->lut_g[regno] << 8;
6645 *blue = intel_crtc->lut_b[regno] << 8;
6648 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6649 u16 *blue, uint32_t start, uint32_t size)
6651 int end = (start + size > 256) ? 256 : start + size, i;
6652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654 for (i = start; i < end; i++) {
6655 intel_crtc->lut_r[i] = red[i] >> 8;
6656 intel_crtc->lut_g[i] = green[i] >> 8;
6657 intel_crtc->lut_b[i] = blue[i] >> 8;
6660 intel_crtc_load_lut(crtc);
6663 /* VESA 640x480x72Hz mode to set on the pipe */
6664 static struct drm_display_mode load_detect_mode = {
6665 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6666 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6669 static struct drm_framebuffer *
6670 intel_framebuffer_create(struct drm_device *dev,
6671 struct drm_mode_fb_cmd2 *mode_cmd,
6672 struct drm_i915_gem_object *obj)
6674 struct intel_framebuffer *intel_fb;
6677 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6679 drm_gem_object_unreference_unlocked(&obj->base);
6680 return ERR_PTR(-ENOMEM);
6683 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6685 drm_gem_object_unreference_unlocked(&obj->base);
6687 return ERR_PTR(ret);
6690 return &intel_fb->base;
6694 intel_framebuffer_pitch_for_width(int width, int bpp)
6696 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6697 return ALIGN(pitch, 64);
6701 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6703 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6704 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6707 static struct drm_framebuffer *
6708 intel_framebuffer_create_for_mode(struct drm_device *dev,
6709 struct drm_display_mode *mode,
6712 struct drm_i915_gem_object *obj;
6713 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6715 obj = i915_gem_alloc_object(dev,
6716 intel_framebuffer_size_for_mode(mode, bpp));
6718 return ERR_PTR(-ENOMEM);
6720 mode_cmd.width = mode->hdisplay;
6721 mode_cmd.height = mode->vdisplay;
6722 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6724 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6726 return intel_framebuffer_create(dev, &mode_cmd, obj);
6729 static struct drm_framebuffer *
6730 mode_fits_in_fbdev(struct drm_device *dev,
6731 struct drm_display_mode *mode)
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 struct drm_i915_gem_object *obj;
6735 struct drm_framebuffer *fb;
6737 if (dev_priv->fbdev == NULL)
6740 obj = dev_priv->fbdev->ifb.obj;
6744 fb = &dev_priv->fbdev->ifb.base;
6745 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6746 fb->bits_per_pixel))
6749 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6755 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6756 struct drm_display_mode *mode,
6757 struct intel_load_detect_pipe *old)
6759 struct intel_crtc *intel_crtc;
6760 struct intel_encoder *intel_encoder =
6761 intel_attached_encoder(connector);
6762 struct drm_crtc *possible_crtc;
6763 struct drm_encoder *encoder = &intel_encoder->base;
6764 struct drm_crtc *crtc = NULL;
6765 struct drm_device *dev = encoder->dev;
6766 struct drm_framebuffer *fb;
6769 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6770 connector->base.id, drm_get_connector_name(connector),
6771 encoder->base.id, drm_get_encoder_name(encoder));
6774 * Algorithm gets a little messy:
6776 * - if the connector already has an assigned crtc, use it (but make
6777 * sure it's on first)
6779 * - try to find the first unused crtc that can drive this connector,
6780 * and use that if we find one
6783 /* See if we already have a CRTC for this connector */
6784 if (encoder->crtc) {
6785 crtc = encoder->crtc;
6787 mutex_lock(&crtc->mutex);
6789 old->dpms_mode = connector->dpms;
6790 old->load_detect_temp = false;
6792 /* Make sure the crtc and connector are running */
6793 if (connector->dpms != DRM_MODE_DPMS_ON)
6794 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6799 /* Find an unused one (if possible) */
6800 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6802 if (!(encoder->possible_crtcs & (1 << i)))
6804 if (!possible_crtc->enabled) {
6805 crtc = possible_crtc;
6811 * If we didn't find an unused CRTC, don't use any.
6814 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6818 mutex_lock(&crtc->mutex);
6819 intel_encoder->new_crtc = to_intel_crtc(crtc);
6820 to_intel_connector(connector)->new_encoder = intel_encoder;
6822 intel_crtc = to_intel_crtc(crtc);
6823 old->dpms_mode = connector->dpms;
6824 old->load_detect_temp = true;
6825 old->release_fb = NULL;
6828 mode = &load_detect_mode;
6830 /* We need a framebuffer large enough to accommodate all accesses
6831 * that the plane may generate whilst we perform load detection.
6832 * We can not rely on the fbcon either being present (we get called
6833 * during its initialisation to detect all boot displays, or it may
6834 * not even exist) or that it is large enough to satisfy the
6837 fb = mode_fits_in_fbdev(dev, mode);
6839 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6840 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6841 old->release_fb = fb;
6843 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6845 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6846 mutex_unlock(&crtc->mutex);
6850 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6851 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6852 if (old->release_fb)
6853 old->release_fb->funcs->destroy(old->release_fb);
6854 mutex_unlock(&crtc->mutex);
6858 /* let the connector get through one full cycle before testing */
6859 intel_wait_for_vblank(dev, intel_crtc->pipe);
6863 void intel_release_load_detect_pipe(struct drm_connector *connector,
6864 struct intel_load_detect_pipe *old)
6866 struct intel_encoder *intel_encoder =
6867 intel_attached_encoder(connector);
6868 struct drm_encoder *encoder = &intel_encoder->base;
6869 struct drm_crtc *crtc = encoder->crtc;
6871 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6872 connector->base.id, drm_get_connector_name(connector),
6873 encoder->base.id, drm_get_encoder_name(encoder));
6875 if (old->load_detect_temp) {
6876 to_intel_connector(connector)->new_encoder = NULL;
6877 intel_encoder->new_crtc = NULL;
6878 intel_set_mode(crtc, NULL, 0, 0, NULL);
6880 if (old->release_fb) {
6881 drm_framebuffer_unregister_private(old->release_fb);
6882 drm_framebuffer_unreference(old->release_fb);
6885 mutex_unlock(&crtc->mutex);
6889 /* Switch crtc and encoder back off if necessary */
6890 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6891 connector->funcs->dpms(connector, old->dpms_mode);
6893 mutex_unlock(&crtc->mutex);
6896 /* Returns the clock of the currently programmed mode of the given pipe. */
6897 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6898 struct intel_crtc_config *pipe_config)
6900 struct drm_device *dev = crtc->base.dev;
6901 struct drm_i915_private *dev_priv = dev->dev_private;
6902 int pipe = pipe_config->cpu_transcoder;
6903 u32 dpll = I915_READ(DPLL(pipe));
6905 intel_clock_t clock;
6907 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6908 fp = I915_READ(FP0(pipe));
6910 fp = I915_READ(FP1(pipe));
6912 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6913 if (IS_PINEVIEW(dev)) {
6914 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6915 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6917 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6918 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6921 if (!IS_GEN2(dev)) {
6922 if (IS_PINEVIEW(dev))
6923 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6924 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6926 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6927 DPLL_FPA01_P1_POST_DIV_SHIFT);
6929 switch (dpll & DPLL_MODE_MASK) {
6930 case DPLLB_MODE_DAC_SERIAL:
6931 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6934 case DPLLB_MODE_LVDS:
6935 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6939 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6940 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6941 pipe_config->adjusted_mode.clock = 0;
6945 if (IS_PINEVIEW(dev))
6946 pineview_clock(96000, &clock);
6948 i9xx_clock(96000, &clock);
6950 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6953 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6954 DPLL_FPA01_P1_POST_DIV_SHIFT);
6957 if ((dpll & PLL_REF_INPUT_MASK) ==
6958 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6959 /* XXX: might not be 66MHz */
6960 i9xx_clock(66000, &clock);
6962 i9xx_clock(48000, &clock);
6964 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6967 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6968 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6970 if (dpll & PLL_P2_DIVIDE_BY_4)
6975 i9xx_clock(48000, &clock);
6979 pipe_config->adjusted_mode.clock = clock.dot *
6980 pipe_config->pixel_multiplier;
6983 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6984 struct intel_crtc_config *pipe_config)
6986 struct drm_device *dev = crtc->base.dev;
6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6989 int link_freq, repeat;
6993 repeat = pipe_config->pixel_multiplier;
6996 * The calculation for the data clock is:
6997 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
6998 * But we want to avoid losing precison if possible, so:
6999 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7001 * and the link clock is simpler:
7002 * link_clock = (m * link_clock * repeat) / n
7006 * We need to get the FDI or DP link clock here to derive
7009 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7010 * For DP, it's either 1.62GHz or 2.7GHz.
7011 * We do our calculations in 10*MHz since we don't need much precison.
7013 if (pipe_config->has_pch_encoder)
7014 link_freq = intel_fdi_link_freq(dev) * 10000;
7016 link_freq = pipe_config->port_clock;
7018 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7019 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7021 if (!link_m || !link_n)
7024 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7025 do_div(clock, link_n);
7027 pipe_config->adjusted_mode.clock = clock;
7030 /** Returns the currently programmed mode of the given pipe. */
7031 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7032 struct drm_crtc *crtc)
7034 struct drm_i915_private *dev_priv = dev->dev_private;
7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7036 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7037 struct drm_display_mode *mode;
7038 struct intel_crtc_config pipe_config;
7039 int htot = I915_READ(HTOTAL(cpu_transcoder));
7040 int hsync = I915_READ(HSYNC(cpu_transcoder));
7041 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7042 int vsync = I915_READ(VSYNC(cpu_transcoder));
7044 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7049 * Construct a pipe_config sufficient for getting the clock info
7050 * back out of crtc_clock_get.
7052 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7053 * to use a real value here instead.
7055 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7056 pipe_config.pixel_multiplier = 1;
7057 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7059 mode->clock = pipe_config.adjusted_mode.clock;
7060 mode->hdisplay = (htot & 0xffff) + 1;
7061 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7062 mode->hsync_start = (hsync & 0xffff) + 1;
7063 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7064 mode->vdisplay = (vtot & 0xffff) + 1;
7065 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7066 mode->vsync_start = (vsync & 0xffff) + 1;
7067 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7069 drm_mode_set_name(mode);
7074 static void intel_increase_pllclock(struct drm_crtc *crtc)
7076 struct drm_device *dev = crtc->dev;
7077 drm_i915_private_t *dev_priv = dev->dev_private;
7078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079 int pipe = intel_crtc->pipe;
7080 int dpll_reg = DPLL(pipe);
7083 if (HAS_PCH_SPLIT(dev))
7086 if (!dev_priv->lvds_downclock_avail)
7089 dpll = I915_READ(dpll_reg);
7090 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7091 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7093 assert_panel_unlocked(dev_priv, pipe);
7095 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7096 I915_WRITE(dpll_reg, dpll);
7097 intel_wait_for_vblank(dev, pipe);
7099 dpll = I915_READ(dpll_reg);
7100 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7101 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7105 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7107 struct drm_device *dev = crtc->dev;
7108 drm_i915_private_t *dev_priv = dev->dev_private;
7109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7111 if (HAS_PCH_SPLIT(dev))
7114 if (!dev_priv->lvds_downclock_avail)
7118 * Since this is called by a timer, we should never get here in
7121 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7122 int pipe = intel_crtc->pipe;
7123 int dpll_reg = DPLL(pipe);
7126 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7128 assert_panel_unlocked(dev_priv, pipe);
7130 dpll = I915_READ(dpll_reg);
7131 dpll |= DISPLAY_RATE_SELECT_FPA1;
7132 I915_WRITE(dpll_reg, dpll);
7133 intel_wait_for_vblank(dev, pipe);
7134 dpll = I915_READ(dpll_reg);
7135 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7136 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7141 void intel_mark_busy(struct drm_device *dev)
7143 i915_update_gfx_val(dev->dev_private);
7146 void intel_mark_idle(struct drm_device *dev)
7148 struct drm_crtc *crtc;
7150 if (!i915_powersave)
7153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7157 intel_decrease_pllclock(crtc);
7161 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7162 struct intel_ring_buffer *ring)
7164 struct drm_device *dev = obj->base.dev;
7165 struct drm_crtc *crtc;
7167 if (!i915_powersave)
7170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7174 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7177 intel_increase_pllclock(crtc);
7178 if (ring && intel_fbc_enabled(dev))
7179 ring->fbc_dirty = true;
7183 static void intel_crtc_destroy(struct drm_crtc *crtc)
7185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7186 struct drm_device *dev = crtc->dev;
7187 struct intel_unpin_work *work;
7188 unsigned long flags;
7190 spin_lock_irqsave(&dev->event_lock, flags);
7191 work = intel_crtc->unpin_work;
7192 intel_crtc->unpin_work = NULL;
7193 spin_unlock_irqrestore(&dev->event_lock, flags);
7196 cancel_work_sync(&work->work);
7200 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7202 drm_crtc_cleanup(crtc);
7207 static void intel_unpin_work_fn(struct work_struct *__work)
7209 struct intel_unpin_work *work =
7210 container_of(__work, struct intel_unpin_work, work);
7211 struct drm_device *dev = work->crtc->dev;
7213 mutex_lock(&dev->struct_mutex);
7214 intel_unpin_fb_obj(work->old_fb_obj);
7215 drm_gem_object_unreference(&work->pending_flip_obj->base);
7216 drm_gem_object_unreference(&work->old_fb_obj->base);
7218 intel_update_fbc(dev);
7219 mutex_unlock(&dev->struct_mutex);
7221 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7222 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7227 static void do_intel_finish_page_flip(struct drm_device *dev,
7228 struct drm_crtc *crtc)
7230 drm_i915_private_t *dev_priv = dev->dev_private;
7231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7232 struct intel_unpin_work *work;
7233 unsigned long flags;
7235 /* Ignore early vblank irqs */
7236 if (intel_crtc == NULL)
7239 spin_lock_irqsave(&dev->event_lock, flags);
7240 work = intel_crtc->unpin_work;
7242 /* Ensure we don't miss a work->pending update ... */
7245 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7246 spin_unlock_irqrestore(&dev->event_lock, flags);
7250 /* and that the unpin work is consistent wrt ->pending. */
7253 intel_crtc->unpin_work = NULL;
7256 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7258 drm_vblank_put(dev, intel_crtc->pipe);
7260 spin_unlock_irqrestore(&dev->event_lock, flags);
7262 wake_up_all(&dev_priv->pending_flip_queue);
7264 queue_work(dev_priv->wq, &work->work);
7266 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7269 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7271 drm_i915_private_t *dev_priv = dev->dev_private;
7272 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7274 do_intel_finish_page_flip(dev, crtc);
7277 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7279 drm_i915_private_t *dev_priv = dev->dev_private;
7280 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7282 do_intel_finish_page_flip(dev, crtc);
7285 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7287 drm_i915_private_t *dev_priv = dev->dev_private;
7288 struct intel_crtc *intel_crtc =
7289 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7290 unsigned long flags;
7292 /* NB: An MMIO update of the plane base pointer will also
7293 * generate a page-flip completion irq, i.e. every modeset
7294 * is also accompanied by a spurious intel_prepare_page_flip().
7296 spin_lock_irqsave(&dev->event_lock, flags);
7297 if (intel_crtc->unpin_work)
7298 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7299 spin_unlock_irqrestore(&dev->event_lock, flags);
7302 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7304 /* Ensure that the work item is consistent when activating it ... */
7306 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7307 /* and that it is marked active as soon as the irq could fire. */
7311 static int intel_gen2_queue_flip(struct drm_device *dev,
7312 struct drm_crtc *crtc,
7313 struct drm_framebuffer *fb,
7314 struct drm_i915_gem_object *obj)
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7319 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7322 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7326 ret = intel_ring_begin(ring, 6);
7330 /* Can't queue multiple flips, so wait for the previous
7331 * one to finish before executing the next.
7333 if (intel_crtc->plane)
7334 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7336 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7337 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7338 intel_ring_emit(ring, MI_NOOP);
7339 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7340 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7341 intel_ring_emit(ring, fb->pitches[0]);
7342 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7343 intel_ring_emit(ring, 0); /* aux display base address, unused */
7345 intel_mark_page_flip_active(intel_crtc);
7346 intel_ring_advance(ring);
7350 intel_unpin_fb_obj(obj);
7355 static int intel_gen3_queue_flip(struct drm_device *dev,
7356 struct drm_crtc *crtc,
7357 struct drm_framebuffer *fb,
7358 struct drm_i915_gem_object *obj)
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7363 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7366 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7370 ret = intel_ring_begin(ring, 6);
7374 if (intel_crtc->plane)
7375 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7377 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7378 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7379 intel_ring_emit(ring, MI_NOOP);
7380 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7381 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7382 intel_ring_emit(ring, fb->pitches[0]);
7383 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7384 intel_ring_emit(ring, MI_NOOP);
7386 intel_mark_page_flip_active(intel_crtc);
7387 intel_ring_advance(ring);
7391 intel_unpin_fb_obj(obj);
7396 static int intel_gen4_queue_flip(struct drm_device *dev,
7397 struct drm_crtc *crtc,
7398 struct drm_framebuffer *fb,
7399 struct drm_i915_gem_object *obj)
7401 struct drm_i915_private *dev_priv = dev->dev_private;
7402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7403 uint32_t pf, pipesrc;
7404 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7407 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7411 ret = intel_ring_begin(ring, 4);
7415 /* i965+ uses the linear or tiled offsets from the
7416 * Display Registers (which do not change across a page-flip)
7417 * so we need only reprogram the base address.
7419 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7421 intel_ring_emit(ring, fb->pitches[0]);
7422 intel_ring_emit(ring,
7423 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7426 /* XXX Enabling the panel-fitter across page-flip is so far
7427 * untested on non-native modes, so ignore it for now.
7428 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7431 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7432 intel_ring_emit(ring, pf | pipesrc);
7434 intel_mark_page_flip_active(intel_crtc);
7435 intel_ring_advance(ring);
7439 intel_unpin_fb_obj(obj);
7444 static int intel_gen6_queue_flip(struct drm_device *dev,
7445 struct drm_crtc *crtc,
7446 struct drm_framebuffer *fb,
7447 struct drm_i915_gem_object *obj)
7449 struct drm_i915_private *dev_priv = dev->dev_private;
7450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7451 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7452 uint32_t pf, pipesrc;
7455 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7459 ret = intel_ring_begin(ring, 4);
7463 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7464 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7465 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7466 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7468 /* Contrary to the suggestions in the documentation,
7469 * "Enable Panel Fitter" does not seem to be required when page
7470 * flipping with a non-native mode, and worse causes a normal
7472 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7475 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7476 intel_ring_emit(ring, pf | pipesrc);
7478 intel_mark_page_flip_active(intel_crtc);
7479 intel_ring_advance(ring);
7483 intel_unpin_fb_obj(obj);
7489 * On gen7 we currently use the blit ring because (in early silicon at least)
7490 * the render ring doesn't give us interrpts for page flip completion, which
7491 * means clients will hang after the first flip is queued. Fortunately the
7492 * blit ring generates interrupts properly, so use it instead.
7494 static int intel_gen7_queue_flip(struct drm_device *dev,
7495 struct drm_crtc *crtc,
7496 struct drm_framebuffer *fb,
7497 struct drm_i915_gem_object *obj)
7499 struct drm_i915_private *dev_priv = dev->dev_private;
7500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7501 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7502 uint32_t plane_bit = 0;
7505 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7509 switch(intel_crtc->plane) {
7511 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7514 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7517 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7520 WARN_ONCE(1, "unknown plane in flip command\n");
7525 ret = intel_ring_begin(ring, 4);
7529 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7530 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7531 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7532 intel_ring_emit(ring, (MI_NOOP));
7534 intel_mark_page_flip_active(intel_crtc);
7535 intel_ring_advance(ring);
7539 intel_unpin_fb_obj(obj);
7544 static int intel_default_queue_flip(struct drm_device *dev,
7545 struct drm_crtc *crtc,
7546 struct drm_framebuffer *fb,
7547 struct drm_i915_gem_object *obj)
7552 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7553 struct drm_framebuffer *fb,
7554 struct drm_pending_vblank_event *event)
7556 struct drm_device *dev = crtc->dev;
7557 struct drm_i915_private *dev_priv = dev->dev_private;
7558 struct drm_framebuffer *old_fb = crtc->fb;
7559 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7561 struct intel_unpin_work *work;
7562 unsigned long flags;
7565 /* Can't change pixel format via MI display flips. */
7566 if (fb->pixel_format != crtc->fb->pixel_format)
7570 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7571 * Note that pitch changes could also affect these register.
7573 if (INTEL_INFO(dev)->gen > 3 &&
7574 (fb->offsets[0] != crtc->fb->offsets[0] ||
7575 fb->pitches[0] != crtc->fb->pitches[0]))
7578 work = kzalloc(sizeof *work, GFP_KERNEL);
7582 work->event = event;
7584 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7585 INIT_WORK(&work->work, intel_unpin_work_fn);
7587 ret = drm_vblank_get(dev, intel_crtc->pipe);
7591 /* We borrow the event spin lock for protecting unpin_work */
7592 spin_lock_irqsave(&dev->event_lock, flags);
7593 if (intel_crtc->unpin_work) {
7594 spin_unlock_irqrestore(&dev->event_lock, flags);
7596 drm_vblank_put(dev, intel_crtc->pipe);
7598 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7601 intel_crtc->unpin_work = work;
7602 spin_unlock_irqrestore(&dev->event_lock, flags);
7604 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7605 flush_workqueue(dev_priv->wq);
7607 ret = i915_mutex_lock_interruptible(dev);
7611 /* Reference the objects for the scheduled work. */
7612 drm_gem_object_reference(&work->old_fb_obj->base);
7613 drm_gem_object_reference(&obj->base);
7617 work->pending_flip_obj = obj;
7619 work->enable_stall_check = true;
7621 atomic_inc(&intel_crtc->unpin_work_count);
7622 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7624 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7626 goto cleanup_pending;
7628 intel_disable_fbc(dev);
7629 intel_mark_fb_busy(obj, NULL);
7630 mutex_unlock(&dev->struct_mutex);
7632 trace_i915_flip_request(intel_crtc->plane, obj);
7637 atomic_dec(&intel_crtc->unpin_work_count);
7639 drm_gem_object_unreference(&work->old_fb_obj->base);
7640 drm_gem_object_unreference(&obj->base);
7641 mutex_unlock(&dev->struct_mutex);
7644 spin_lock_irqsave(&dev->event_lock, flags);
7645 intel_crtc->unpin_work = NULL;
7646 spin_unlock_irqrestore(&dev->event_lock, flags);
7648 drm_vblank_put(dev, intel_crtc->pipe);
7655 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7656 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7657 .load_lut = intel_crtc_load_lut,
7660 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7661 struct drm_crtc *crtc)
7663 struct drm_device *dev;
7664 struct drm_crtc *tmp;
7667 WARN(!crtc, "checking null crtc?\n");
7671 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7677 if (encoder->possible_crtcs & crtc_mask)
7683 * intel_modeset_update_staged_output_state
7685 * Updates the staged output configuration state, e.g. after we've read out the
7688 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7690 struct intel_encoder *encoder;
7691 struct intel_connector *connector;
7693 list_for_each_entry(connector, &dev->mode_config.connector_list,
7695 connector->new_encoder =
7696 to_intel_encoder(connector->base.encoder);
7699 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7702 to_intel_crtc(encoder->base.crtc);
7707 * intel_modeset_commit_output_state
7709 * This function copies the stage display pipe configuration to the real one.
7711 static void intel_modeset_commit_output_state(struct drm_device *dev)
7713 struct intel_encoder *encoder;
7714 struct intel_connector *connector;
7716 list_for_each_entry(connector, &dev->mode_config.connector_list,
7718 connector->base.encoder = &connector->new_encoder->base;
7721 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7723 encoder->base.crtc = &encoder->new_crtc->base;
7728 connected_sink_compute_bpp(struct intel_connector * connector,
7729 struct intel_crtc_config *pipe_config)
7731 int bpp = pipe_config->pipe_bpp;
7733 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7734 connector->base.base.id,
7735 drm_get_connector_name(&connector->base));
7737 /* Don't use an invalid EDID bpc value */
7738 if (connector->base.display_info.bpc &&
7739 connector->base.display_info.bpc * 3 < bpp) {
7740 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7741 bpp, connector->base.display_info.bpc*3);
7742 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7745 /* Clamp bpp to 8 on screens without EDID 1.4 */
7746 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7747 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7749 pipe_config->pipe_bpp = 24;
7754 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7755 struct drm_framebuffer *fb,
7756 struct intel_crtc_config *pipe_config)
7758 struct drm_device *dev = crtc->base.dev;
7759 struct intel_connector *connector;
7762 switch (fb->pixel_format) {
7764 bpp = 8*3; /* since we go through a colormap */
7766 case DRM_FORMAT_XRGB1555:
7767 case DRM_FORMAT_ARGB1555:
7768 /* checked in intel_framebuffer_init already */
7769 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7771 case DRM_FORMAT_RGB565:
7772 bpp = 6*3; /* min is 18bpp */
7774 case DRM_FORMAT_XBGR8888:
7775 case DRM_FORMAT_ABGR8888:
7776 /* checked in intel_framebuffer_init already */
7777 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7779 case DRM_FORMAT_XRGB8888:
7780 case DRM_FORMAT_ARGB8888:
7783 case DRM_FORMAT_XRGB2101010:
7784 case DRM_FORMAT_ARGB2101010:
7785 case DRM_FORMAT_XBGR2101010:
7786 case DRM_FORMAT_ABGR2101010:
7787 /* checked in intel_framebuffer_init already */
7788 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7792 /* TODO: gen4+ supports 16 bpc floating point, too. */
7794 DRM_DEBUG_KMS("unsupported depth\n");
7798 pipe_config->pipe_bpp = bpp;
7800 /* Clamp display bpp to EDID value */
7801 list_for_each_entry(connector, &dev->mode_config.connector_list,
7803 if (!connector->new_encoder ||
7804 connector->new_encoder->new_crtc != crtc)
7807 connected_sink_compute_bpp(connector, pipe_config);
7813 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7814 struct intel_crtc_config *pipe_config,
7815 const char *context)
7817 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7818 context, pipe_name(crtc->pipe));
7820 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7821 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7822 pipe_config->pipe_bpp, pipe_config->dither);
7823 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7824 pipe_config->has_pch_encoder,
7825 pipe_config->fdi_lanes,
7826 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7827 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7828 pipe_config->fdi_m_n.tu);
7829 DRM_DEBUG_KMS("requested mode:\n");
7830 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7831 DRM_DEBUG_KMS("adjusted mode:\n");
7832 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7833 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7834 pipe_config->gmch_pfit.control,
7835 pipe_config->gmch_pfit.pgm_ratios,
7836 pipe_config->gmch_pfit.lvds_border_bits);
7837 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7838 pipe_config->pch_pfit.pos,
7839 pipe_config->pch_pfit.size);
7840 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7843 static bool check_encoder_cloning(struct drm_crtc *crtc)
7845 int num_encoders = 0;
7846 bool uncloneable_encoders = false;
7847 struct intel_encoder *encoder;
7849 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7851 if (&encoder->new_crtc->base != crtc)
7855 if (!encoder->cloneable)
7856 uncloneable_encoders = true;
7859 return !(num_encoders > 1 && uncloneable_encoders);
7862 static struct intel_crtc_config *
7863 intel_modeset_pipe_config(struct drm_crtc *crtc,
7864 struct drm_framebuffer *fb,
7865 struct drm_display_mode *mode)
7867 struct drm_device *dev = crtc->dev;
7868 struct drm_encoder_helper_funcs *encoder_funcs;
7869 struct intel_encoder *encoder;
7870 struct intel_crtc_config *pipe_config;
7871 int plane_bpp, ret = -EINVAL;
7874 if (!check_encoder_cloning(crtc)) {
7875 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7876 return ERR_PTR(-EINVAL);
7879 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7881 return ERR_PTR(-ENOMEM);
7883 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7884 drm_mode_copy(&pipe_config->requested_mode, mode);
7885 pipe_config->cpu_transcoder =
7886 (enum transcoder) to_intel_crtc(crtc)->pipe;
7887 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7889 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7890 * plane pixel format and any sink constraints into account. Returns the
7891 * source plane bpp so that dithering can be selected on mismatches
7892 * after encoders and crtc also have had their say. */
7893 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7899 /* Ensure the port clock defaults are reset when retrying. */
7900 pipe_config->port_clock = 0;
7901 pipe_config->pixel_multiplier = 1;
7903 /* Pass our mode to the connectors and the CRTC to give them a chance to
7904 * adjust it according to limitations or connector properties, and also
7905 * a chance to reject the mode entirely.
7907 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7910 if (&encoder->new_crtc->base != crtc)
7913 if (encoder->compute_config) {
7914 if (!(encoder->compute_config(encoder, pipe_config))) {
7915 DRM_DEBUG_KMS("Encoder config failure\n");
7922 encoder_funcs = encoder->base.helper_private;
7923 if (!(encoder_funcs->mode_fixup(&encoder->base,
7924 &pipe_config->requested_mode,
7925 &pipe_config->adjusted_mode))) {
7926 DRM_DEBUG_KMS("Encoder fixup failed\n");
7931 /* Set default port clock if not overwritten by the encoder. Needs to be
7932 * done afterwards in case the encoder adjusts the mode. */
7933 if (!pipe_config->port_clock)
7934 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7936 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7938 DRM_DEBUG_KMS("CRTC fixup failed\n");
7943 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7948 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7953 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7954 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7955 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7960 return ERR_PTR(ret);
7963 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7964 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7966 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7967 unsigned *prepare_pipes, unsigned *disable_pipes)
7969 struct intel_crtc *intel_crtc;
7970 struct drm_device *dev = crtc->dev;
7971 struct intel_encoder *encoder;
7972 struct intel_connector *connector;
7973 struct drm_crtc *tmp_crtc;
7975 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7977 /* Check which crtcs have changed outputs connected to them, these need
7978 * to be part of the prepare_pipes mask. We don't (yet) support global
7979 * modeset across multiple crtcs, so modeset_pipes will only have one
7980 * bit set at most. */
7981 list_for_each_entry(connector, &dev->mode_config.connector_list,
7983 if (connector->base.encoder == &connector->new_encoder->base)
7986 if (connector->base.encoder) {
7987 tmp_crtc = connector->base.encoder->crtc;
7989 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7992 if (connector->new_encoder)
7994 1 << connector->new_encoder->new_crtc->pipe;
7997 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7999 if (encoder->base.crtc == &encoder->new_crtc->base)
8002 if (encoder->base.crtc) {
8003 tmp_crtc = encoder->base.crtc;
8005 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8008 if (encoder->new_crtc)
8009 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8012 /* Check for any pipes that will be fully disabled ... */
8013 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8017 /* Don't try to disable disabled crtcs. */
8018 if (!intel_crtc->base.enabled)
8021 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8023 if (encoder->new_crtc == intel_crtc)
8028 *disable_pipes |= 1 << intel_crtc->pipe;
8032 /* set_mode is also used to update properties on life display pipes. */
8033 intel_crtc = to_intel_crtc(crtc);
8035 *prepare_pipes |= 1 << intel_crtc->pipe;
8038 * For simplicity do a full modeset on any pipe where the output routing
8039 * changed. We could be more clever, but that would require us to be
8040 * more careful with calling the relevant encoder->mode_set functions.
8043 *modeset_pipes = *prepare_pipes;
8045 /* ... and mask these out. */
8046 *modeset_pipes &= ~(*disable_pipes);
8047 *prepare_pipes &= ~(*disable_pipes);
8050 * HACK: We don't (yet) fully support global modesets. intel_set_config
8051 * obies this rule, but the modeset restore mode of
8052 * intel_modeset_setup_hw_state does not.
8054 *modeset_pipes &= 1 << intel_crtc->pipe;
8055 *prepare_pipes &= 1 << intel_crtc->pipe;
8057 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8058 *modeset_pipes, *prepare_pipes, *disable_pipes);
8061 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8063 struct drm_encoder *encoder;
8064 struct drm_device *dev = crtc->dev;
8066 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8067 if (encoder->crtc == crtc)
8074 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8076 struct intel_encoder *intel_encoder;
8077 struct intel_crtc *intel_crtc;
8078 struct drm_connector *connector;
8080 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8082 if (!intel_encoder->base.crtc)
8085 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8087 if (prepare_pipes & (1 << intel_crtc->pipe))
8088 intel_encoder->connectors_active = false;
8091 intel_modeset_commit_output_state(dev);
8093 /* Update computed state. */
8094 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8096 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8099 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8100 if (!connector->encoder || !connector->encoder->crtc)
8103 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8105 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8106 struct drm_property *dpms_property =
8107 dev->mode_config.dpms_property;
8109 connector->dpms = DRM_MODE_DPMS_ON;
8110 drm_object_property_set_value(&connector->base,
8114 intel_encoder = to_intel_encoder(connector->encoder);
8115 intel_encoder->connectors_active = true;
8121 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8122 struct intel_crtc_config *new)
8124 int clock1, clock2, diff;
8126 clock1 = cur->adjusted_mode.clock;
8127 clock2 = new->adjusted_mode.clock;
8129 if (clock1 == clock2)
8132 if (!clock1 || !clock2)
8135 diff = abs(clock1 - clock2);
8137 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8143 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8144 list_for_each_entry((intel_crtc), \
8145 &(dev)->mode_config.crtc_list, \
8147 if (mask & (1 <<(intel_crtc)->pipe))
8150 intel_pipe_config_compare(struct drm_device *dev,
8151 struct intel_crtc_config *current_config,
8152 struct intel_crtc_config *pipe_config)
8154 #define PIPE_CONF_CHECK_X(name) \
8155 if (current_config->name != pipe_config->name) { \
8156 DRM_ERROR("mismatch in " #name " " \
8157 "(expected 0x%08x, found 0x%08x)\n", \
8158 current_config->name, \
8159 pipe_config->name); \
8163 #define PIPE_CONF_CHECK_I(name) \
8164 if (current_config->name != pipe_config->name) { \
8165 DRM_ERROR("mismatch in " #name " " \
8166 "(expected %i, found %i)\n", \
8167 current_config->name, \
8168 pipe_config->name); \
8172 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8173 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8174 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8175 "(expected %i, found %i)\n", \
8176 current_config->name & (mask), \
8177 pipe_config->name & (mask)); \
8181 #define PIPE_CONF_QUIRK(quirk) \
8182 ((current_config->quirks | pipe_config->quirks) & (quirk))
8184 PIPE_CONF_CHECK_I(cpu_transcoder);
8186 PIPE_CONF_CHECK_I(has_pch_encoder);
8187 PIPE_CONF_CHECK_I(fdi_lanes);
8188 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8189 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8190 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8191 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8192 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8194 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8195 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8196 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8197 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8198 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8199 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8201 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8202 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8203 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8204 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8205 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8206 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8208 PIPE_CONF_CHECK_I(pixel_multiplier);
8210 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8211 DRM_MODE_FLAG_INTERLACE);
8213 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8214 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8215 DRM_MODE_FLAG_PHSYNC);
8216 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8217 DRM_MODE_FLAG_NHSYNC);
8218 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8219 DRM_MODE_FLAG_PVSYNC);
8220 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8221 DRM_MODE_FLAG_NVSYNC);
8224 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8225 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8227 PIPE_CONF_CHECK_I(gmch_pfit.control);
8228 /* pfit ratios are autocomputed by the hw on gen4+ */
8229 if (INTEL_INFO(dev)->gen < 4)
8230 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8231 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8232 PIPE_CONF_CHECK_I(pch_pfit.pos);
8233 PIPE_CONF_CHECK_I(pch_pfit.size);
8235 PIPE_CONF_CHECK_I(ips_enabled);
8237 PIPE_CONF_CHECK_I(shared_dpll);
8238 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8239 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8240 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8241 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8243 #undef PIPE_CONF_CHECK_X
8244 #undef PIPE_CONF_CHECK_I
8245 #undef PIPE_CONF_CHECK_FLAGS
8246 #undef PIPE_CONF_QUIRK
8248 if (!IS_HASWELL(dev)) {
8249 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8250 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8251 current_config->adjusted_mode.clock,
8252 pipe_config->adjusted_mode.clock);
8261 check_connector_state(struct drm_device *dev)
8263 struct intel_connector *connector;
8265 list_for_each_entry(connector, &dev->mode_config.connector_list,
8267 /* This also checks the encoder/connector hw state with the
8268 * ->get_hw_state callbacks. */
8269 intel_connector_check_state(connector);
8271 WARN(&connector->new_encoder->base != connector->base.encoder,
8272 "connector's staged encoder doesn't match current encoder\n");
8277 check_encoder_state(struct drm_device *dev)
8279 struct intel_encoder *encoder;
8280 struct intel_connector *connector;
8282 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8284 bool enabled = false;
8285 bool active = false;
8286 enum pipe pipe, tracked_pipe;
8288 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8289 encoder->base.base.id,
8290 drm_get_encoder_name(&encoder->base));
8292 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8293 "encoder's stage crtc doesn't match current crtc\n");
8294 WARN(encoder->connectors_active && !encoder->base.crtc,
8295 "encoder's active_connectors set, but no crtc\n");
8297 list_for_each_entry(connector, &dev->mode_config.connector_list,
8299 if (connector->base.encoder != &encoder->base)
8302 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8305 WARN(!!encoder->base.crtc != enabled,
8306 "encoder's enabled state mismatch "
8307 "(expected %i, found %i)\n",
8308 !!encoder->base.crtc, enabled);
8309 WARN(active && !encoder->base.crtc,
8310 "active encoder with no crtc\n");
8312 WARN(encoder->connectors_active != active,
8313 "encoder's computed active state doesn't match tracked active state "
8314 "(expected %i, found %i)\n", active, encoder->connectors_active);
8316 active = encoder->get_hw_state(encoder, &pipe);
8317 WARN(active != encoder->connectors_active,
8318 "encoder's hw state doesn't match sw tracking "
8319 "(expected %i, found %i)\n",
8320 encoder->connectors_active, active);
8322 if (!encoder->base.crtc)
8325 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8326 WARN(active && pipe != tracked_pipe,
8327 "active encoder's pipe doesn't match"
8328 "(expected %i, found %i)\n",
8329 tracked_pipe, pipe);
8335 check_crtc_state(struct drm_device *dev)
8337 drm_i915_private_t *dev_priv = dev->dev_private;
8338 struct intel_crtc *crtc;
8339 struct intel_encoder *encoder;
8340 struct intel_crtc_config pipe_config;
8342 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8344 bool enabled = false;
8345 bool active = false;
8347 memset(&pipe_config, 0, sizeof(pipe_config));
8349 DRM_DEBUG_KMS("[CRTC:%d]\n",
8350 crtc->base.base.id);
8352 WARN(crtc->active && !crtc->base.enabled,
8353 "active crtc, but not enabled in sw tracking\n");
8355 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8357 if (encoder->base.crtc != &crtc->base)
8360 if (encoder->connectors_active)
8364 WARN(active != crtc->active,
8365 "crtc's computed active state doesn't match tracked active state "
8366 "(expected %i, found %i)\n", active, crtc->active);
8367 WARN(enabled != crtc->base.enabled,
8368 "crtc's computed enabled state doesn't match tracked enabled state "
8369 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8371 active = dev_priv->display.get_pipe_config(crtc,
8374 /* hw state is inconsistent with the pipe A quirk */
8375 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8376 active = crtc->active;
8378 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8380 if (encoder->base.crtc != &crtc->base)
8382 if (encoder->get_config)
8383 encoder->get_config(encoder, &pipe_config);
8386 if (dev_priv->display.get_clock)
8387 dev_priv->display.get_clock(crtc, &pipe_config);
8389 WARN(crtc->active != active,
8390 "crtc active state doesn't match with hw state "
8391 "(expected %i, found %i)\n", crtc->active, active);
8394 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8395 WARN(1, "pipe state doesn't match!\n");
8396 intel_dump_pipe_config(crtc, &pipe_config,
8398 intel_dump_pipe_config(crtc, &crtc->config,
8405 check_shared_dpll_state(struct drm_device *dev)
8407 drm_i915_private_t *dev_priv = dev->dev_private;
8408 struct intel_crtc *crtc;
8409 struct intel_dpll_hw_state dpll_hw_state;
8412 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8413 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8414 int enabled_crtcs = 0, active_crtcs = 0;
8417 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8419 DRM_DEBUG_KMS("%s\n", pll->name);
8421 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8423 WARN(pll->active > pll->refcount,
8424 "more active pll users than references: %i vs %i\n",
8425 pll->active, pll->refcount);
8426 WARN(pll->active && !pll->on,
8427 "pll in active use but not on in sw tracking\n");
8428 WARN(pll->on != active,
8429 "pll on state mismatch (expected %i, found %i)\n",
8432 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8434 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8436 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8439 WARN(pll->active != active_crtcs,
8440 "pll active crtcs mismatch (expected %i, found %i)\n",
8441 pll->active, active_crtcs);
8442 WARN(pll->refcount != enabled_crtcs,
8443 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8444 pll->refcount, enabled_crtcs);
8446 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8447 sizeof(dpll_hw_state)),
8448 "pll hw state mismatch\n");
8453 intel_modeset_check_state(struct drm_device *dev)
8455 check_connector_state(dev);
8456 check_encoder_state(dev);
8457 check_crtc_state(dev);
8458 check_shared_dpll_state(dev);
8461 static int __intel_set_mode(struct drm_crtc *crtc,
8462 struct drm_display_mode *mode,
8463 int x, int y, struct drm_framebuffer *fb)
8465 struct drm_device *dev = crtc->dev;
8466 drm_i915_private_t *dev_priv = dev->dev_private;
8467 struct drm_display_mode *saved_mode, *saved_hwmode;
8468 struct intel_crtc_config *pipe_config = NULL;
8469 struct intel_crtc *intel_crtc;
8470 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8473 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8476 saved_hwmode = saved_mode + 1;
8478 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8479 &prepare_pipes, &disable_pipes);
8481 *saved_hwmode = crtc->hwmode;
8482 *saved_mode = crtc->mode;
8484 /* Hack: Because we don't (yet) support global modeset on multiple
8485 * crtcs, we don't keep track of the new mode for more than one crtc.
8486 * Hence simply check whether any bit is set in modeset_pipes in all the
8487 * pieces of code that are not yet converted to deal with mutliple crtcs
8488 * changing their mode at the same time. */
8489 if (modeset_pipes) {
8490 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8491 if (IS_ERR(pipe_config)) {
8492 ret = PTR_ERR(pipe_config);
8497 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8501 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8502 intel_crtc_disable(&intel_crtc->base);
8504 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8505 if (intel_crtc->base.enabled)
8506 dev_priv->display.crtc_disable(&intel_crtc->base);
8509 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8510 * to set it here already despite that we pass it down the callchain.
8512 if (modeset_pipes) {
8514 /* mode_set/enable/disable functions rely on a correct pipe
8516 to_intel_crtc(crtc)->config = *pipe_config;
8519 /* Only after disabling all output pipelines that will be changed can we
8520 * update the the output configuration. */
8521 intel_modeset_update_state(dev, prepare_pipes);
8523 if (dev_priv->display.modeset_global_resources)
8524 dev_priv->display.modeset_global_resources(dev);
8526 /* Set up the DPLL and any encoders state that needs to adjust or depend
8529 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8530 ret = intel_crtc_mode_set(&intel_crtc->base,
8536 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8537 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8538 dev_priv->display.crtc_enable(&intel_crtc->base);
8540 if (modeset_pipes) {
8541 /* Store real post-adjustment hardware mode. */
8542 crtc->hwmode = pipe_config->adjusted_mode;
8544 /* Calculate and store various constants which
8545 * are later needed by vblank and swap-completion
8546 * timestamping. They are derived from true hwmode.
8548 drm_calc_timestamping_constants(crtc);
8551 /* FIXME: add subpixel order */
8553 if (ret && crtc->enabled) {
8554 crtc->hwmode = *saved_hwmode;
8555 crtc->mode = *saved_mode;
8564 int intel_set_mode(struct drm_crtc *crtc,
8565 struct drm_display_mode *mode,
8566 int x, int y, struct drm_framebuffer *fb)
8570 ret = __intel_set_mode(crtc, mode, x, y, fb);
8573 intel_modeset_check_state(crtc->dev);
8578 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8580 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8583 #undef for_each_intel_crtc_masked
8585 static void intel_set_config_free(struct intel_set_config *config)
8590 kfree(config->save_connector_encoders);
8591 kfree(config->save_encoder_crtcs);
8595 static int intel_set_config_save_state(struct drm_device *dev,
8596 struct intel_set_config *config)
8598 struct drm_encoder *encoder;
8599 struct drm_connector *connector;
8602 config->save_encoder_crtcs =
8603 kcalloc(dev->mode_config.num_encoder,
8604 sizeof(struct drm_crtc *), GFP_KERNEL);
8605 if (!config->save_encoder_crtcs)
8608 config->save_connector_encoders =
8609 kcalloc(dev->mode_config.num_connector,
8610 sizeof(struct drm_encoder *), GFP_KERNEL);
8611 if (!config->save_connector_encoders)
8614 /* Copy data. Note that driver private data is not affected.
8615 * Should anything bad happen only the expected state is
8616 * restored, not the drivers personal bookkeeping.
8619 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8620 config->save_encoder_crtcs[count++] = encoder->crtc;
8624 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8625 config->save_connector_encoders[count++] = connector->encoder;
8631 static void intel_set_config_restore_state(struct drm_device *dev,
8632 struct intel_set_config *config)
8634 struct intel_encoder *encoder;
8635 struct intel_connector *connector;
8639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8641 to_intel_crtc(config->save_encoder_crtcs[count++]);
8645 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8646 connector->new_encoder =
8647 to_intel_encoder(config->save_connector_encoders[count++]);
8652 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8657 for (i = 0; i < num_connectors; i++)
8658 if (connectors[i].encoder &&
8659 connectors[i].encoder->crtc == crtc &&
8660 connectors[i].dpms != DRM_MODE_DPMS_ON)
8667 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8668 struct intel_set_config *config)
8671 /* We should be able to check here if the fb has the same properties
8672 * and then just flip_or_move it */
8673 if (set->connectors != NULL &&
8674 is_crtc_connector_off(set->crtc, *set->connectors,
8675 set->num_connectors)) {
8676 config->mode_changed = true;
8677 } else if (set->crtc->fb != set->fb) {
8678 /* If we have no fb then treat it as a full mode set */
8679 if (set->crtc->fb == NULL) {
8680 struct intel_crtc *intel_crtc =
8681 to_intel_crtc(set->crtc);
8683 if (intel_crtc->active && i915_fastboot) {
8684 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8685 config->fb_changed = true;
8687 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8688 config->mode_changed = true;
8690 } else if (set->fb == NULL) {
8691 config->mode_changed = true;
8692 } else if (set->fb->pixel_format !=
8693 set->crtc->fb->pixel_format) {
8694 config->mode_changed = true;
8696 config->fb_changed = true;
8700 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8701 config->fb_changed = true;
8703 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8704 DRM_DEBUG_KMS("modes are different, full mode set\n");
8705 drm_mode_debug_printmodeline(&set->crtc->mode);
8706 drm_mode_debug_printmodeline(set->mode);
8707 config->mode_changed = true;
8712 intel_modeset_stage_output_state(struct drm_device *dev,
8713 struct drm_mode_set *set,
8714 struct intel_set_config *config)
8716 struct drm_crtc *new_crtc;
8717 struct intel_connector *connector;
8718 struct intel_encoder *encoder;
8721 /* The upper layers ensure that we either disable a crtc or have a list
8722 * of connectors. For paranoia, double-check this. */
8723 WARN_ON(!set->fb && (set->num_connectors != 0));
8724 WARN_ON(set->fb && (set->num_connectors == 0));
8727 list_for_each_entry(connector, &dev->mode_config.connector_list,
8729 /* Otherwise traverse passed in connector list and get encoders
8731 for (ro = 0; ro < set->num_connectors; ro++) {
8732 if (set->connectors[ro] == &connector->base) {
8733 connector->new_encoder = connector->encoder;
8738 /* If we disable the crtc, disable all its connectors. Also, if
8739 * the connector is on the changing crtc but not on the new
8740 * connector list, disable it. */
8741 if ((!set->fb || ro == set->num_connectors) &&
8742 connector->base.encoder &&
8743 connector->base.encoder->crtc == set->crtc) {
8744 connector->new_encoder = NULL;
8746 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8747 connector->base.base.id,
8748 drm_get_connector_name(&connector->base));
8752 if (&connector->new_encoder->base != connector->base.encoder) {
8753 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8754 config->mode_changed = true;
8757 /* connector->new_encoder is now updated for all connectors. */
8759 /* Update crtc of enabled connectors. */
8761 list_for_each_entry(connector, &dev->mode_config.connector_list,
8763 if (!connector->new_encoder)
8766 new_crtc = connector->new_encoder->base.crtc;
8768 for (ro = 0; ro < set->num_connectors; ro++) {
8769 if (set->connectors[ro] == &connector->base)
8770 new_crtc = set->crtc;
8773 /* Make sure the new CRTC will work with the encoder */
8774 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8778 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8780 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8781 connector->base.base.id,
8782 drm_get_connector_name(&connector->base),
8786 /* Check for any encoders that needs to be disabled. */
8787 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8789 list_for_each_entry(connector,
8790 &dev->mode_config.connector_list,
8792 if (connector->new_encoder == encoder) {
8793 WARN_ON(!connector->new_encoder->new_crtc);
8798 encoder->new_crtc = NULL;
8800 /* Only now check for crtc changes so we don't miss encoders
8801 * that will be disabled. */
8802 if (&encoder->new_crtc->base != encoder->base.crtc) {
8803 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8804 config->mode_changed = true;
8807 /* Now we've also updated encoder->new_crtc for all encoders. */
8812 static int intel_crtc_set_config(struct drm_mode_set *set)
8814 struct drm_device *dev;
8815 struct drm_mode_set save_set;
8816 struct intel_set_config *config;
8821 BUG_ON(!set->crtc->helper_private);
8823 /* Enforce sane interface api - has been abused by the fb helper. */
8824 BUG_ON(!set->mode && set->fb);
8825 BUG_ON(set->fb && set->num_connectors == 0);
8828 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8829 set->crtc->base.id, set->fb->base.id,
8830 (int)set->num_connectors, set->x, set->y);
8832 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8835 dev = set->crtc->dev;
8838 config = kzalloc(sizeof(*config), GFP_KERNEL);
8842 ret = intel_set_config_save_state(dev, config);
8846 save_set.crtc = set->crtc;
8847 save_set.mode = &set->crtc->mode;
8848 save_set.x = set->crtc->x;
8849 save_set.y = set->crtc->y;
8850 save_set.fb = set->crtc->fb;
8852 /* Compute whether we need a full modeset, only an fb base update or no
8853 * change at all. In the future we might also check whether only the
8854 * mode changed, e.g. for LVDS where we only change the panel fitter in
8856 intel_set_config_compute_mode_changes(set, config);
8858 ret = intel_modeset_stage_output_state(dev, set, config);
8862 if (config->mode_changed) {
8863 ret = intel_set_mode(set->crtc, set->mode,
8864 set->x, set->y, set->fb);
8865 } else if (config->fb_changed) {
8866 intel_crtc_wait_for_pending_flips(set->crtc);
8868 ret = intel_pipe_set_base(set->crtc,
8869 set->x, set->y, set->fb);
8873 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8874 set->crtc->base.id, ret);
8876 intel_set_config_restore_state(dev, config);
8878 /* Try to restore the config */
8879 if (config->mode_changed &&
8880 intel_set_mode(save_set.crtc, save_set.mode,
8881 save_set.x, save_set.y, save_set.fb))
8882 DRM_ERROR("failed to restore config after modeset failure\n");
8886 intel_set_config_free(config);
8890 static const struct drm_crtc_funcs intel_crtc_funcs = {
8891 .cursor_set = intel_crtc_cursor_set,
8892 .cursor_move = intel_crtc_cursor_move,
8893 .gamma_set = intel_crtc_gamma_set,
8894 .set_config = intel_crtc_set_config,
8895 .destroy = intel_crtc_destroy,
8896 .page_flip = intel_crtc_page_flip,
8899 static void intel_cpu_pll_init(struct drm_device *dev)
8902 intel_ddi_pll_init(dev);
8905 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8906 struct intel_shared_dpll *pll,
8907 struct intel_dpll_hw_state *hw_state)
8911 val = I915_READ(PCH_DPLL(pll->id));
8912 hw_state->dpll = val;
8913 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8914 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8916 return val & DPLL_VCO_ENABLE;
8919 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8920 struct intel_shared_dpll *pll)
8922 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8923 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8926 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8927 struct intel_shared_dpll *pll)
8929 /* PCH refclock must be enabled first */
8930 assert_pch_refclk_enabled(dev_priv);
8932 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8934 /* Wait for the clocks to stabilize. */
8935 POSTING_READ(PCH_DPLL(pll->id));
8938 /* The pixel multiplier can only be updated once the
8939 * DPLL is enabled and the clocks are stable.
8941 * So write it again.
8943 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8944 POSTING_READ(PCH_DPLL(pll->id));
8948 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8949 struct intel_shared_dpll *pll)
8951 struct drm_device *dev = dev_priv->dev;
8952 struct intel_crtc *crtc;
8954 /* Make sure no transcoder isn't still depending on us. */
8955 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8956 if (intel_crtc_to_shared_dpll(crtc) == pll)
8957 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8960 I915_WRITE(PCH_DPLL(pll->id), 0);
8961 POSTING_READ(PCH_DPLL(pll->id));
8965 static char *ibx_pch_dpll_names[] = {
8970 static void ibx_pch_dpll_init(struct drm_device *dev)
8972 struct drm_i915_private *dev_priv = dev->dev_private;
8975 dev_priv->num_shared_dpll = 2;
8977 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8978 dev_priv->shared_dplls[i].id = i;
8979 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8980 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8981 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8982 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8983 dev_priv->shared_dplls[i].get_hw_state =
8984 ibx_pch_dpll_get_hw_state;
8988 static void intel_shared_dpll_init(struct drm_device *dev)
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8992 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8993 ibx_pch_dpll_init(dev);
8995 dev_priv->num_shared_dpll = 0;
8997 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8998 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8999 dev_priv->num_shared_dpll);
9002 static void intel_crtc_init(struct drm_device *dev, int pipe)
9004 drm_i915_private_t *dev_priv = dev->dev_private;
9005 struct intel_crtc *intel_crtc;
9008 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9009 if (intel_crtc == NULL)
9012 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9014 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9015 for (i = 0; i < 256; i++) {
9016 intel_crtc->lut_r[i] = i;
9017 intel_crtc->lut_g[i] = i;
9018 intel_crtc->lut_b[i] = i;
9021 /* Swap pipes & planes for FBC on pre-965 */
9022 intel_crtc->pipe = pipe;
9023 intel_crtc->plane = pipe;
9024 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9025 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9026 intel_crtc->plane = !pipe;
9029 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9030 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9031 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9032 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9034 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9037 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9038 struct drm_file *file)
9040 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9041 struct drm_mode_object *drmmode_obj;
9042 struct intel_crtc *crtc;
9044 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9047 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9048 DRM_MODE_OBJECT_CRTC);
9051 DRM_ERROR("no such CRTC id\n");
9055 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9056 pipe_from_crtc_id->pipe = crtc->pipe;
9061 static int intel_encoder_clones(struct intel_encoder *encoder)
9063 struct drm_device *dev = encoder->base.dev;
9064 struct intel_encoder *source_encoder;
9068 list_for_each_entry(source_encoder,
9069 &dev->mode_config.encoder_list, base.head) {
9071 if (encoder == source_encoder)
9072 index_mask |= (1 << entry);
9074 /* Intel hw has only one MUX where enocoders could be cloned. */
9075 if (encoder->cloneable && source_encoder->cloneable)
9076 index_mask |= (1 << entry);
9084 static bool has_edp_a(struct drm_device *dev)
9086 struct drm_i915_private *dev_priv = dev->dev_private;
9088 if (!IS_MOBILE(dev))
9091 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9095 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9101 static void intel_setup_outputs(struct drm_device *dev)
9103 struct drm_i915_private *dev_priv = dev->dev_private;
9104 struct intel_encoder *encoder;
9105 bool dpd_is_edp = false;
9107 intel_lvds_init(dev);
9110 intel_crt_init(dev);
9115 /* Haswell uses DDI functions to detect digital outputs */
9116 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9117 /* DDI A only supports eDP */
9119 intel_ddi_init(dev, PORT_A);
9121 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9123 found = I915_READ(SFUSE_STRAP);
9125 if (found & SFUSE_STRAP_DDIB_DETECTED)
9126 intel_ddi_init(dev, PORT_B);
9127 if (found & SFUSE_STRAP_DDIC_DETECTED)
9128 intel_ddi_init(dev, PORT_C);
9129 if (found & SFUSE_STRAP_DDID_DETECTED)
9130 intel_ddi_init(dev, PORT_D);
9131 } else if (HAS_PCH_SPLIT(dev)) {
9133 dpd_is_edp = intel_dpd_is_edp(dev);
9136 intel_dp_init(dev, DP_A, PORT_A);
9138 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9139 /* PCH SDVOB multiplex with HDMIB */
9140 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9142 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9143 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9144 intel_dp_init(dev, PCH_DP_B, PORT_B);
9147 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9148 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9150 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9151 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9153 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9154 intel_dp_init(dev, PCH_DP_C, PORT_C);
9156 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9157 intel_dp_init(dev, PCH_DP_D, PORT_D);
9158 } else if (IS_VALLEYVIEW(dev)) {
9159 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9160 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9161 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9163 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9164 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9166 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9167 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9169 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9172 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9173 DRM_DEBUG_KMS("probing SDVOB\n");
9174 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9175 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9176 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9177 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9180 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9181 intel_dp_init(dev, DP_B, PORT_B);
9184 /* Before G4X SDVOC doesn't have its own detect register */
9186 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9187 DRM_DEBUG_KMS("probing SDVOC\n");
9188 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9191 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9193 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9194 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9195 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9197 if (SUPPORTS_INTEGRATED_DP(dev))
9198 intel_dp_init(dev, DP_C, PORT_C);
9201 if (SUPPORTS_INTEGRATED_DP(dev) &&
9202 (I915_READ(DP_D) & DP_DETECTED))
9203 intel_dp_init(dev, DP_D, PORT_D);
9204 } else if (IS_GEN2(dev))
9205 intel_dvo_init(dev);
9207 if (SUPPORTS_TV(dev))
9210 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9211 encoder->base.possible_crtcs = encoder->crtc_mask;
9212 encoder->base.possible_clones =
9213 intel_encoder_clones(encoder);
9216 intel_init_pch_refclk(dev);
9218 drm_helper_move_panel_connectors_to_head(dev);
9221 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9223 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9225 drm_framebuffer_cleanup(fb);
9226 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9231 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9232 struct drm_file *file,
9233 unsigned int *handle)
9235 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9236 struct drm_i915_gem_object *obj = intel_fb->obj;
9238 return drm_gem_handle_create(file, &obj->base, handle);
9241 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9242 .destroy = intel_user_framebuffer_destroy,
9243 .create_handle = intel_user_framebuffer_create_handle,
9246 int intel_framebuffer_init(struct drm_device *dev,
9247 struct intel_framebuffer *intel_fb,
9248 struct drm_mode_fb_cmd2 *mode_cmd,
9249 struct drm_i915_gem_object *obj)
9254 if (obj->tiling_mode == I915_TILING_Y) {
9255 DRM_DEBUG("hardware does not support tiling Y\n");
9259 if (mode_cmd->pitches[0] & 63) {
9260 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9261 mode_cmd->pitches[0]);
9265 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9266 pitch_limit = 32*1024;
9267 } else if (INTEL_INFO(dev)->gen >= 4) {
9268 if (obj->tiling_mode)
9269 pitch_limit = 16*1024;
9271 pitch_limit = 32*1024;
9272 } else if (INTEL_INFO(dev)->gen >= 3) {
9273 if (obj->tiling_mode)
9274 pitch_limit = 8*1024;
9276 pitch_limit = 16*1024;
9278 /* XXX DSPC is limited to 4k tiled */
9279 pitch_limit = 8*1024;
9281 if (mode_cmd->pitches[0] > pitch_limit) {
9282 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9283 obj->tiling_mode ? "tiled" : "linear",
9284 mode_cmd->pitches[0], pitch_limit);
9288 if (obj->tiling_mode != I915_TILING_NONE &&
9289 mode_cmd->pitches[0] != obj->stride) {
9290 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9291 mode_cmd->pitches[0], obj->stride);
9295 /* Reject formats not supported by any plane early. */
9296 switch (mode_cmd->pixel_format) {
9298 case DRM_FORMAT_RGB565:
9299 case DRM_FORMAT_XRGB8888:
9300 case DRM_FORMAT_ARGB8888:
9302 case DRM_FORMAT_XRGB1555:
9303 case DRM_FORMAT_ARGB1555:
9304 if (INTEL_INFO(dev)->gen > 3) {
9305 DRM_DEBUG("unsupported pixel format: %s\n",
9306 drm_get_format_name(mode_cmd->pixel_format));
9310 case DRM_FORMAT_XBGR8888:
9311 case DRM_FORMAT_ABGR8888:
9312 case DRM_FORMAT_XRGB2101010:
9313 case DRM_FORMAT_ARGB2101010:
9314 case DRM_FORMAT_XBGR2101010:
9315 case DRM_FORMAT_ABGR2101010:
9316 if (INTEL_INFO(dev)->gen < 4) {
9317 DRM_DEBUG("unsupported pixel format: %s\n",
9318 drm_get_format_name(mode_cmd->pixel_format));
9322 case DRM_FORMAT_YUYV:
9323 case DRM_FORMAT_UYVY:
9324 case DRM_FORMAT_YVYU:
9325 case DRM_FORMAT_VYUY:
9326 if (INTEL_INFO(dev)->gen < 5) {
9327 DRM_DEBUG("unsupported pixel format: %s\n",
9328 drm_get_format_name(mode_cmd->pixel_format));
9333 DRM_DEBUG("unsupported pixel format: %s\n",
9334 drm_get_format_name(mode_cmd->pixel_format));
9338 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9339 if (mode_cmd->offsets[0] != 0)
9342 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9343 intel_fb->obj = obj;
9345 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9347 DRM_ERROR("framebuffer init failed %d\n", ret);
9354 static struct drm_framebuffer *
9355 intel_user_framebuffer_create(struct drm_device *dev,
9356 struct drm_file *filp,
9357 struct drm_mode_fb_cmd2 *mode_cmd)
9359 struct drm_i915_gem_object *obj;
9361 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9362 mode_cmd->handles[0]));
9363 if (&obj->base == NULL)
9364 return ERR_PTR(-ENOENT);
9366 return intel_framebuffer_create(dev, mode_cmd, obj);
9369 static const struct drm_mode_config_funcs intel_mode_funcs = {
9370 .fb_create = intel_user_framebuffer_create,
9371 .output_poll_changed = intel_fb_output_poll_changed,
9374 /* Set up chip specific display functions */
9375 static void intel_init_display(struct drm_device *dev)
9377 struct drm_i915_private *dev_priv = dev->dev_private;
9379 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9380 dev_priv->display.find_dpll = g4x_find_best_dpll;
9381 else if (IS_VALLEYVIEW(dev))
9382 dev_priv->display.find_dpll = vlv_find_best_dpll;
9383 else if (IS_PINEVIEW(dev))
9384 dev_priv->display.find_dpll = pnv_find_best_dpll;
9386 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9389 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9390 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9391 dev_priv->display.crtc_enable = haswell_crtc_enable;
9392 dev_priv->display.crtc_disable = haswell_crtc_disable;
9393 dev_priv->display.off = haswell_crtc_off;
9394 dev_priv->display.update_plane = ironlake_update_plane;
9395 } else if (HAS_PCH_SPLIT(dev)) {
9396 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9397 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9398 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9399 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9400 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9401 dev_priv->display.off = ironlake_crtc_off;
9402 dev_priv->display.update_plane = ironlake_update_plane;
9403 } else if (IS_VALLEYVIEW(dev)) {
9404 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9405 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9406 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9407 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9408 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9409 dev_priv->display.off = i9xx_crtc_off;
9410 dev_priv->display.update_plane = i9xx_update_plane;
9412 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9413 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9414 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9415 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9416 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9417 dev_priv->display.off = i9xx_crtc_off;
9418 dev_priv->display.update_plane = i9xx_update_plane;
9421 /* Returns the core display clock speed */
9422 if (IS_VALLEYVIEW(dev))
9423 dev_priv->display.get_display_clock_speed =
9424 valleyview_get_display_clock_speed;
9425 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9426 dev_priv->display.get_display_clock_speed =
9427 i945_get_display_clock_speed;
9428 else if (IS_I915G(dev))
9429 dev_priv->display.get_display_clock_speed =
9430 i915_get_display_clock_speed;
9431 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9432 dev_priv->display.get_display_clock_speed =
9433 i9xx_misc_get_display_clock_speed;
9434 else if (IS_I915GM(dev))
9435 dev_priv->display.get_display_clock_speed =
9436 i915gm_get_display_clock_speed;
9437 else if (IS_I865G(dev))
9438 dev_priv->display.get_display_clock_speed =
9439 i865_get_display_clock_speed;
9440 else if (IS_I85X(dev))
9441 dev_priv->display.get_display_clock_speed =
9442 i855_get_display_clock_speed;
9444 dev_priv->display.get_display_clock_speed =
9445 i830_get_display_clock_speed;
9447 if (HAS_PCH_SPLIT(dev)) {
9449 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9450 dev_priv->display.write_eld = ironlake_write_eld;
9451 } else if (IS_GEN6(dev)) {
9452 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9453 dev_priv->display.write_eld = ironlake_write_eld;
9454 } else if (IS_IVYBRIDGE(dev)) {
9455 /* FIXME: detect B0+ stepping and use auto training */
9456 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9457 dev_priv->display.write_eld = ironlake_write_eld;
9458 dev_priv->display.modeset_global_resources =
9459 ivb_modeset_global_resources;
9460 } else if (IS_HASWELL(dev)) {
9461 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9462 dev_priv->display.write_eld = haswell_write_eld;
9463 dev_priv->display.modeset_global_resources =
9464 haswell_modeset_global_resources;
9466 } else if (IS_G4X(dev)) {
9467 dev_priv->display.write_eld = g4x_write_eld;
9470 /* Default just returns -ENODEV to indicate unsupported */
9471 dev_priv->display.queue_flip = intel_default_queue_flip;
9473 switch (INTEL_INFO(dev)->gen) {
9475 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9479 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9484 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9488 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9491 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9497 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9498 * resume, or other times. This quirk makes sure that's the case for
9501 static void quirk_pipea_force(struct drm_device *dev)
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9505 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9506 DRM_INFO("applying pipe a force quirk\n");
9510 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9512 static void quirk_ssc_force_disable(struct drm_device *dev)
9514 struct drm_i915_private *dev_priv = dev->dev_private;
9515 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9516 DRM_INFO("applying lvds SSC disable quirk\n");
9520 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9523 static void quirk_invert_brightness(struct drm_device *dev)
9525 struct drm_i915_private *dev_priv = dev->dev_private;
9526 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9527 DRM_INFO("applying inverted panel brightness quirk\n");
9530 struct intel_quirk {
9532 int subsystem_vendor;
9533 int subsystem_device;
9534 void (*hook)(struct drm_device *dev);
9537 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9538 struct intel_dmi_quirk {
9539 void (*hook)(struct drm_device *dev);
9540 const struct dmi_system_id (*dmi_id_list)[];
9543 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9545 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9549 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9551 .dmi_id_list = &(const struct dmi_system_id[]) {
9553 .callback = intel_dmi_reverse_brightness,
9554 .ident = "NCR Corporation",
9555 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9556 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9559 { } /* terminating entry */
9561 .hook = quirk_invert_brightness,
9565 static struct intel_quirk intel_quirks[] = {
9566 /* HP Mini needs pipe A force quirk (LP: #322104) */
9567 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9569 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9570 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9572 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9573 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9575 /* 830/845 need to leave pipe A & dpll A up */
9576 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9577 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9579 /* Lenovo U160 cannot use SSC on LVDS */
9580 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9582 /* Sony Vaio Y cannot use SSC on LVDS */
9583 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9585 /* Acer Aspire 5734Z must invert backlight brightness */
9586 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9588 /* Acer/eMachines G725 */
9589 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9591 /* Acer/eMachines e725 */
9592 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9594 /* Acer/Packard Bell NCL20 */
9595 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9597 /* Acer Aspire 4736Z */
9598 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9601 static void intel_init_quirks(struct drm_device *dev)
9603 struct pci_dev *d = dev->pdev;
9606 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9607 struct intel_quirk *q = &intel_quirks[i];
9609 if (d->device == q->device &&
9610 (d->subsystem_vendor == q->subsystem_vendor ||
9611 q->subsystem_vendor == PCI_ANY_ID) &&
9612 (d->subsystem_device == q->subsystem_device ||
9613 q->subsystem_device == PCI_ANY_ID))
9616 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9617 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9618 intel_dmi_quirks[i].hook(dev);
9622 /* Disable the VGA plane that we never use */
9623 static void i915_disable_vga(struct drm_device *dev)
9625 struct drm_i915_private *dev_priv = dev->dev_private;
9627 u32 vga_reg = i915_vgacntrl_reg(dev);
9629 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9630 outb(SR01, VGA_SR_INDEX);
9631 sr1 = inb(VGA_SR_DATA);
9632 outb(sr1 | 1<<5, VGA_SR_DATA);
9633 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9636 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9637 POSTING_READ(vga_reg);
9640 void intel_modeset_init_hw(struct drm_device *dev)
9642 intel_init_power_well(dev);
9644 intel_prepare_ddi(dev);
9646 intel_init_clock_gating(dev);
9648 mutex_lock(&dev->struct_mutex);
9649 intel_enable_gt_powersave(dev);
9650 mutex_unlock(&dev->struct_mutex);
9653 void intel_modeset_suspend_hw(struct drm_device *dev)
9655 intel_suspend_hw(dev);
9658 void intel_modeset_init(struct drm_device *dev)
9660 struct drm_i915_private *dev_priv = dev->dev_private;
9663 drm_mode_config_init(dev);
9665 dev->mode_config.min_width = 0;
9666 dev->mode_config.min_height = 0;
9668 dev->mode_config.preferred_depth = 24;
9669 dev->mode_config.prefer_shadow = 1;
9671 dev->mode_config.funcs = &intel_mode_funcs;
9673 intel_init_quirks(dev);
9677 if (INTEL_INFO(dev)->num_pipes == 0)
9680 intel_init_display(dev);
9683 dev->mode_config.max_width = 2048;
9684 dev->mode_config.max_height = 2048;
9685 } else if (IS_GEN3(dev)) {
9686 dev->mode_config.max_width = 4096;
9687 dev->mode_config.max_height = 4096;
9689 dev->mode_config.max_width = 8192;
9690 dev->mode_config.max_height = 8192;
9692 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9694 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9695 INTEL_INFO(dev)->num_pipes,
9696 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9698 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9699 intel_crtc_init(dev, i);
9700 for (j = 0; j < dev_priv->num_plane; j++) {
9701 ret = intel_plane_init(dev, i, j);
9703 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9704 pipe_name(i), sprite_name(i, j), ret);
9708 intel_cpu_pll_init(dev);
9709 intel_shared_dpll_init(dev);
9711 /* Just disable it once at startup */
9712 i915_disable_vga(dev);
9713 intel_setup_outputs(dev);
9715 /* Just in case the BIOS is doing something questionable. */
9716 intel_disable_fbc(dev);
9720 intel_connector_break_all_links(struct intel_connector *connector)
9722 connector->base.dpms = DRM_MODE_DPMS_OFF;
9723 connector->base.encoder = NULL;
9724 connector->encoder->connectors_active = false;
9725 connector->encoder->base.crtc = NULL;
9728 static void intel_enable_pipe_a(struct drm_device *dev)
9730 struct intel_connector *connector;
9731 struct drm_connector *crt = NULL;
9732 struct intel_load_detect_pipe load_detect_temp;
9734 /* We can't just switch on the pipe A, we need to set things up with a
9735 * proper mode and output configuration. As a gross hack, enable pipe A
9736 * by enabling the load detect pipe once. */
9737 list_for_each_entry(connector,
9738 &dev->mode_config.connector_list,
9740 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9741 crt = &connector->base;
9749 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9750 intel_release_load_detect_pipe(crt, &load_detect_temp);
9756 intel_check_plane_mapping(struct intel_crtc *crtc)
9758 struct drm_device *dev = crtc->base.dev;
9759 struct drm_i915_private *dev_priv = dev->dev_private;
9762 if (INTEL_INFO(dev)->num_pipes == 1)
9765 reg = DSPCNTR(!crtc->plane);
9766 val = I915_READ(reg);
9768 if ((val & DISPLAY_PLANE_ENABLE) &&
9769 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9775 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9777 struct drm_device *dev = crtc->base.dev;
9778 struct drm_i915_private *dev_priv = dev->dev_private;
9781 /* Clear any frame start delays used for debugging left by the BIOS */
9782 reg = PIPECONF(crtc->config.cpu_transcoder);
9783 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9785 /* We need to sanitize the plane -> pipe mapping first because this will
9786 * disable the crtc (and hence change the state) if it is wrong. Note
9787 * that gen4+ has a fixed plane -> pipe mapping. */
9788 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9789 struct intel_connector *connector;
9792 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9793 crtc->base.base.id);
9795 /* Pipe has the wrong plane attached and the plane is active.
9796 * Temporarily change the plane mapping and disable everything
9798 plane = crtc->plane;
9799 crtc->plane = !plane;
9800 dev_priv->display.crtc_disable(&crtc->base);
9801 crtc->plane = plane;
9803 /* ... and break all links. */
9804 list_for_each_entry(connector, &dev->mode_config.connector_list,
9806 if (connector->encoder->base.crtc != &crtc->base)
9809 intel_connector_break_all_links(connector);
9812 WARN_ON(crtc->active);
9813 crtc->base.enabled = false;
9816 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9817 crtc->pipe == PIPE_A && !crtc->active) {
9818 /* BIOS forgot to enable pipe A, this mostly happens after
9819 * resume. Force-enable the pipe to fix this, the update_dpms
9820 * call below we restore the pipe to the right state, but leave
9821 * the required bits on. */
9822 intel_enable_pipe_a(dev);
9825 /* Adjust the state of the output pipe according to whether we
9826 * have active connectors/encoders. */
9827 intel_crtc_update_dpms(&crtc->base);
9829 if (crtc->active != crtc->base.enabled) {
9830 struct intel_encoder *encoder;
9832 /* This can happen either due to bugs in the get_hw_state
9833 * functions or because the pipe is force-enabled due to the
9835 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9837 crtc->base.enabled ? "enabled" : "disabled",
9838 crtc->active ? "enabled" : "disabled");
9840 crtc->base.enabled = crtc->active;
9842 /* Because we only establish the connector -> encoder ->
9843 * crtc links if something is active, this means the
9844 * crtc is now deactivated. Break the links. connector
9845 * -> encoder links are only establish when things are
9846 * actually up, hence no need to break them. */
9847 WARN_ON(crtc->active);
9849 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9850 WARN_ON(encoder->connectors_active);
9851 encoder->base.crtc = NULL;
9856 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9858 struct intel_connector *connector;
9859 struct drm_device *dev = encoder->base.dev;
9861 /* We need to check both for a crtc link (meaning that the
9862 * encoder is active and trying to read from a pipe) and the
9863 * pipe itself being active. */
9864 bool has_active_crtc = encoder->base.crtc &&
9865 to_intel_crtc(encoder->base.crtc)->active;
9867 if (encoder->connectors_active && !has_active_crtc) {
9868 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9869 encoder->base.base.id,
9870 drm_get_encoder_name(&encoder->base));
9872 /* Connector is active, but has no active pipe. This is
9873 * fallout from our resume register restoring. Disable
9874 * the encoder manually again. */
9875 if (encoder->base.crtc) {
9876 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9877 encoder->base.base.id,
9878 drm_get_encoder_name(&encoder->base));
9879 encoder->disable(encoder);
9882 /* Inconsistent output/port/pipe state happens presumably due to
9883 * a bug in one of the get_hw_state functions. Or someplace else
9884 * in our code, like the register restore mess on resume. Clamp
9885 * things to off as a safer default. */
9886 list_for_each_entry(connector,
9887 &dev->mode_config.connector_list,
9889 if (connector->encoder != encoder)
9892 intel_connector_break_all_links(connector);
9895 /* Enabled encoders without active connectors will be fixed in
9896 * the crtc fixup. */
9899 void i915_redisable_vga(struct drm_device *dev)
9901 struct drm_i915_private *dev_priv = dev->dev_private;
9902 u32 vga_reg = i915_vgacntrl_reg(dev);
9904 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9905 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9906 i915_disable_vga(dev);
9910 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9912 struct drm_i915_private *dev_priv = dev->dev_private;
9914 struct intel_crtc *crtc;
9915 struct intel_encoder *encoder;
9916 struct intel_connector *connector;
9919 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9921 memset(&crtc->config, 0, sizeof(crtc->config));
9923 crtc->active = dev_priv->display.get_pipe_config(crtc,
9926 crtc->base.enabled = crtc->active;
9928 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9930 crtc->active ? "enabled" : "disabled");
9933 /* FIXME: Smash this into the new shared dpll infrastructure. */
9935 intel_ddi_setup_hw_pll_state(dev);
9937 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9938 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9940 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9942 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9944 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9947 pll->refcount = pll->active;
9949 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9950 pll->name, pll->refcount);
9953 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9957 if (encoder->get_hw_state(encoder, &pipe)) {
9958 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9959 encoder->base.crtc = &crtc->base;
9960 if (encoder->get_config)
9961 encoder->get_config(encoder, &crtc->config);
9963 encoder->base.crtc = NULL;
9966 encoder->connectors_active = false;
9967 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9968 encoder->base.base.id,
9969 drm_get_encoder_name(&encoder->base),
9970 encoder->base.crtc ? "enabled" : "disabled",
9974 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9978 if (dev_priv->display.get_clock)
9979 dev_priv->display.get_clock(crtc,
9983 list_for_each_entry(connector, &dev->mode_config.connector_list,
9985 if (connector->get_hw_state(connector)) {
9986 connector->base.dpms = DRM_MODE_DPMS_ON;
9987 connector->encoder->connectors_active = true;
9988 connector->base.encoder = &connector->encoder->base;
9990 connector->base.dpms = DRM_MODE_DPMS_OFF;
9991 connector->base.encoder = NULL;
9993 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9994 connector->base.base.id,
9995 drm_get_connector_name(&connector->base),
9996 connector->base.encoder ? "enabled" : "disabled");
10000 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10001 * and i915 state tracking structures. */
10002 void intel_modeset_setup_hw_state(struct drm_device *dev,
10003 bool force_restore)
10005 struct drm_i915_private *dev_priv = dev->dev_private;
10007 struct drm_plane *plane;
10008 struct intel_crtc *crtc;
10009 struct intel_encoder *encoder;
10011 intel_modeset_readout_hw_state(dev);
10014 * Now that we have the config, copy it to each CRTC struct
10015 * Note that this could go away if we move to using crtc_config
10016 * checking everywhere.
10018 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10020 if (crtc->active && i915_fastboot) {
10021 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10023 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10024 crtc->base.base.id);
10025 drm_mode_debug_printmodeline(&crtc->base.mode);
10029 /* HW state is read out, now we need to sanitize this mess. */
10030 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10032 intel_sanitize_encoder(encoder);
10035 for_each_pipe(pipe) {
10036 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10037 intel_sanitize_crtc(crtc);
10038 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10041 if (force_restore) {
10043 * We need to use raw interfaces for restoring state to avoid
10044 * checking (bogus) intermediate states.
10046 for_each_pipe(pipe) {
10047 struct drm_crtc *crtc =
10048 dev_priv->pipe_to_crtc_mapping[pipe];
10050 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10053 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10054 intel_plane_restore(plane);
10056 i915_redisable_vga(dev);
10058 intel_modeset_update_staged_output_state(dev);
10061 intel_modeset_check_state(dev);
10063 drm_mode_config_reset(dev);
10066 void intel_modeset_gem_init(struct drm_device *dev)
10068 intel_modeset_init_hw(dev);
10070 intel_setup_overlay(dev);
10072 intel_modeset_setup_hw_state(dev, false);
10075 void intel_modeset_cleanup(struct drm_device *dev)
10077 struct drm_i915_private *dev_priv = dev->dev_private;
10078 struct drm_crtc *crtc;
10079 struct intel_crtc *intel_crtc;
10082 * Interrupts and polling as the first thing to avoid creating havoc.
10083 * Too much stuff here (turning of rps, connectors, ...) would
10084 * experience fancy races otherwise.
10086 drm_irq_uninstall(dev);
10087 cancel_work_sync(&dev_priv->hotplug_work);
10089 * Due to the hpd irq storm handling the hotplug work can re-arm the
10090 * poll handlers. Hence disable polling after hpd handling is shut down.
10092 drm_kms_helper_poll_fini(dev);
10094 mutex_lock(&dev->struct_mutex);
10096 intel_unregister_dsm_handler();
10098 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10099 /* Skip inactive CRTCs */
10103 intel_crtc = to_intel_crtc(crtc);
10104 intel_increase_pllclock(crtc);
10107 intel_disable_fbc(dev);
10109 intel_disable_gt_powersave(dev);
10111 ironlake_teardown_rc6(dev);
10113 mutex_unlock(&dev->struct_mutex);
10115 /* flush any delayed tasks or pending work */
10116 flush_scheduled_work();
10118 /* destroy backlight, if any, before the connectors */
10119 intel_panel_destroy_backlight(dev);
10121 drm_mode_config_cleanup(dev);
10123 intel_cleanup_overlay(dev);
10127 * Return which encoder is currently attached for connector.
10129 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10131 return &intel_attached_encoder(connector)->base;
10134 void intel_connector_attach_encoder(struct intel_connector *connector,
10135 struct intel_encoder *encoder)
10137 connector->encoder = encoder;
10138 drm_mode_connector_attach_encoder(&connector->base,
10143 * set vga decode state - true == enable VGA decode
10145 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10147 struct drm_i915_private *dev_priv = dev->dev_private;
10150 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10152 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10154 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10155 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10159 #ifdef CONFIG_DEBUG_FS
10160 #include <linux/seq_file.h>
10162 struct intel_display_error_state {
10164 u32 power_well_driver;
10166 struct intel_cursor_error_state {
10171 } cursor[I915_MAX_PIPES];
10173 struct intel_pipe_error_state {
10174 enum transcoder cpu_transcoder;
10184 } pipe[I915_MAX_PIPES];
10186 struct intel_plane_error_state {
10194 } plane[I915_MAX_PIPES];
10197 struct intel_display_error_state *
10198 intel_display_capture_error_state(struct drm_device *dev)
10200 drm_i915_private_t *dev_priv = dev->dev_private;
10201 struct intel_display_error_state *error;
10202 enum transcoder cpu_transcoder;
10205 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10209 if (HAS_POWER_WELL(dev))
10210 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10213 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10214 error->pipe[i].cpu_transcoder = cpu_transcoder;
10216 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10217 error->cursor[i].control = I915_READ(CURCNTR(i));
10218 error->cursor[i].position = I915_READ(CURPOS(i));
10219 error->cursor[i].base = I915_READ(CURBASE(i));
10221 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10222 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10223 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10226 error->plane[i].control = I915_READ(DSPCNTR(i));
10227 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10228 if (INTEL_INFO(dev)->gen <= 3) {
10229 error->plane[i].size = I915_READ(DSPSIZE(i));
10230 error->plane[i].pos = I915_READ(DSPPOS(i));
10232 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10233 error->plane[i].addr = I915_READ(DSPADDR(i));
10234 if (INTEL_INFO(dev)->gen >= 4) {
10235 error->plane[i].surface = I915_READ(DSPSURF(i));
10236 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10239 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10240 error->pipe[i].source = I915_READ(PIPESRC(i));
10241 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10242 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10243 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10244 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10245 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10246 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10249 /* In the code above we read the registers without checking if the power
10250 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10251 * prevent the next I915_WRITE from detecting it and printing an error
10253 if (HAS_POWER_WELL(dev))
10254 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10259 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10262 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10263 struct drm_device *dev,
10264 struct intel_display_error_state *error)
10268 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10269 if (HAS_POWER_WELL(dev))
10270 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10271 error->power_well_driver);
10273 err_printf(m, "Pipe [%d]:\n", i);
10274 err_printf(m, " CPU transcoder: %c\n",
10275 transcoder_name(error->pipe[i].cpu_transcoder));
10276 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10277 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10278 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10279 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10280 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10281 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10282 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10283 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10285 err_printf(m, "Plane [%d]:\n", i);
10286 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10287 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10288 if (INTEL_INFO(dev)->gen <= 3) {
10289 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10290 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10292 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10293 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10294 if (INTEL_INFO(dev)->gen >= 4) {
10295 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10296 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10299 err_printf(m, "Cursor [%d]:\n", i);
10300 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10301 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10302 err_printf(m, " BASE: %08x\n", error->cursor[i].base);