Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         clock->vco = refclk * clock->m / clock->n;
 333         clock->dot = clock->vco / clock->p;
 334 }
 335
 336 /**
 337  * Returns whether any output on the specified pipe is of the specified type
 338  */
 339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 340 {
 341         struct drm_device *dev = crtc->dev;
 342         struct intel_encoder *encoder;
 343
 344         for_each_encoder_on_crtc(dev, crtc, encoder)
 345                 if (encoder->type == type)
 346                         return true;
 347
 348         return false;
 349 }
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 limit = &intel_limits_vlv;
 412         } else if (!IS_GEN2(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 414                         limit = &intel_limits_i9xx_lvds;
 415                 else
 416                         limit = &intel_limits_i9xx_sdvo;
 417         } else {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i8xx_lvds;
 420                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 421                         limit = &intel_limits_i8xx_dvo;
 422                 else
 423                         limit = &intel_limits_i8xx_dac;
 424         }
 425         return limit;
 426 }
 427
 428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 429 static void pineview_clock(int refclk, intel_clock_t *clock)
 430 {
 431         clock->m = clock->m2 + 2;
 432         clock->p = clock->p1 * clock->p2;
 433         clock->vco = refclk * clock->m / clock->n;
 434         clock->dot = clock->vco / clock->p;
 435 }
 436
 437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 438 {
 439         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 440 }
 441
 442 static void i9xx_clock(int refclk, intel_clock_t *clock)
 443 {
 444         clock->m = i9xx_dpll_compute_m(clock);
 445         clock->p = clock->p1 * clock->p2;
 446         clock->vco = refclk * clock->m / (clock->n + 2);
 447         clock->dot = clock->vco / clock->p;
 448 }
 449
 450 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 451 /**
 452  * Returns whether the given set of divisors are valid for a given refclk with
 453  * the given connectors.
 454  */
 455
 456 static bool intel_PLL_is_valid(struct drm_device *dev,
 457                                const intel_limit_t *limit,
 458                                const intel_clock_t *clock)
 459 {
 460         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 461                 INTELPllInvalid("n out of range\n");
 462         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 463                 INTELPllInvalid("p1 out of range\n");
 464         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 465                 INTELPllInvalid("m2 out of range\n");
 466         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 467                 INTELPllInvalid("m1 out of range\n");
 468
 469         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 470                 if (clock->m1 <= clock->m2)
 471                         INTELPllInvalid("m1 <= m2\n");
 472
 473         if (!IS_VALLEYVIEW(dev)) {
 474                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 475                         INTELPllInvalid("p out of range\n");
 476                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 477                         INTELPllInvalid("m out of range\n");
 478         }
 479
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         intel_clock_t clock;
 675         unsigned int bestppm = 1000000;
 676         /* min update 19.2 MHz */
 677         int max_n = min(limit->n.max, refclk / 19200);
 678         bool found = false;
 679
 680         target *= 5; /* fast clock */
 681
 682         memset(best_clock, 0, sizeof(*best_clock));
 683
 684         /* based on hardware requirement, prefer smaller n to precision */
 685         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 686                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 687                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 688                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 689                                 clock.p = clock.p1 * clock.p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                                         unsigned int ppm, diff;
 693
 694                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 695                                                                      refclk * clock.m1);
 696
 697                                         vlv_clock(refclk, &clock);
 698
 699                                         if (!intel_PLL_is_valid(dev, limit,
 700                                                                 &clock))
 701                                                 continue;
 702
 703                                         diff = abs(clock.dot - target);
 704                                         ppm = div_u64(1000000ULL * diff, target);
 705
 706                                         if (ppm < 100 && clock.p > best_clock->p) {
 707                                                 bestppm = 0;
 708                                                 *best_clock = clock;
 709                                                 found = true;
 710                                         }
 711
 712                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 713                                                 bestppm = ppm;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return found;
 723 }
 724
 725 bool intel_crtc_active(struct drm_crtc *crtc)
 726 {
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728
 729         /* Be paranoid as we can arrive here with only partial
 730          * state retrieved from the hardware during setup.
 731          *
 732          * We can ditch the adjusted_mode.crtc_clock check as soon
 733          * as Haswell has gained clock readout/fastboot support.
 734          *
 735          * We can ditch the crtc->fb check as soon as we can
 736          * properly reconstruct framebuffers.
 737          */
 738         return intel_crtc->active && crtc->fb &&
 739                 intel_crtc->config.adjusted_mode.crtc_clock;
 740 }
 741
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe)
 744 {
 745         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 747
 748         return intel_crtc->config.cpu_transcoder;
 749 }
 750
 751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 frame, frame_reg = PIPEFRAME(pipe);
 755
 756         frame = I915_READ(frame_reg);
 757
 758         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 759                 DRM_DEBUG_KMS("vblank wait timed out\n");
 760 }
 761
 762 /**
 763  * intel_wait_for_vblank - wait for vblank on a given pipe
 764  * @dev: drm device
 765  * @pipe: pipe to wait for
 766  *
 767  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 768  * mode setting code.
 769  */
 770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int pipestat_reg = PIPESTAT(pipe);
 774
 775         if (INTEL_INFO(dev)->gen >= 5) {
 776                 ironlake_wait_for_vblank(dev, pipe);
 777                 return;
 778         }
 779
 780         /* Clear existing vblank status. Note this will clear any other
 781          * sticky status fields as well.
 782          *
 783          * This races with i915_driver_irq_handler() with the result
 784          * that either function could miss a vblank event.  Here it is not
 785          * fatal, as we will either wait upon the next vblank interrupt or
 786          * timeout.  Generally speaking intel_wait_for_vblank() is only
 787          * called during modeset at which time the GPU should be idle and
 788          * should *not* be performing page flips and thus not waiting on
 789          * vblanks...
 790          * Currently, the result of us stealing a vblank from the irq
 791          * handler is that a single frame will be skipped during swapbuffers.
 792          */
 793         I915_WRITE(pipestat_reg,
 794                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 795
 796         /* Wait for vblank interrupt bit to set */
 797         if (wait_for(I915_READ(pipestat_reg) &
 798                      PIPE_VBLANK_INTERRUPT_STATUS,
 799                      50))
 800                 DRM_DEBUG_KMS("vblank wait timed out\n");
 801 }
 802
 803 /*
 804  * intel_wait_for_pipe_off - wait for pipe to turn off
 805  * @dev: drm device
 806  * @pipe: pipe to wait for
 807  *
 808  * After disabling a pipe, we can't wait for vblank in the usual way,
 809  * spinning on the vblank interrupt status bit, since we won't actually
 810  * see an interrupt when the pipe is disabled.
 811  *
 812  * On Gen4 and above:
 813  *   wait for the pipe register state bit to turn off
 814  *
 815  * Otherwise:
 816  *   wait for the display line value to settle (it usually
 817  *   ends up stopping at the start of the next frame).
 818  *
 819  */
 820 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 821 {
 822         struct drm_i915_private *dev_priv = dev->dev_private;
 823         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 824                                                                       pipe);
 825
 826         if (INTEL_INFO(dev)->gen >= 4) {
 827                 int reg = PIPECONF(cpu_transcoder);
 828
 829                 /* Wait for the Pipe State to go off */
 830                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 831                              100))
 832                         WARN(1, "pipe_off wait timed out\n");
 833         } else {
 834                 u32 last_line, line_mask;
 835                 int reg = PIPEDSL(pipe);
 836                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 837
 838                 if (IS_GEN2(dev))
 839                         line_mask = DSL_LINEMASK_GEN2;
 840                 else
 841                         line_mask = DSL_LINEMASK_GEN3;
 842
 843                 /* Wait for the display line to settle */
 844                 do {
 845                         last_line = I915_READ(reg) & line_mask;
 846                         mdelay(5);
 847                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 848                          time_after(timeout, jiffies));
 849                 if (time_after(jiffies, timeout))
 850                         WARN(1, "pipe_off wait timed out\n");
 851         }
 852 }
 853
 854 /*
 855  * ibx_digital_port_connected - is the specified port connected?
 856  * @dev_priv: i915 private structure
 857  * @port: the port to test
 858  *
 859  * Returns true if @port is connected, false otherwise.
 860  */
 861 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 862                                 struct intel_digital_port *port)
 863 {
 864         u32 bit;
 865
 866         if (HAS_PCH_IBX(dev_priv->dev)) {
 867                 switch(port->port) {
 868                 case PORT_B:
 869                         bit = SDE_PORTB_HOTPLUG;
 870                         break;
 871                 case PORT_C:
 872                         bit = SDE_PORTC_HOTPLUG;
 873                         break;
 874                 case PORT_D:
 875                         bit = SDE_PORTD_HOTPLUG;
 876                         break;
 877                 default:
 878                         return true;
 879                 }
 880         } else {
 881                 switch(port->port) {
 882                 case PORT_B:
 883                         bit = SDE_PORTB_HOTPLUG_CPT;
 884                         break;
 885                 case PORT_C:
 886                         bit = SDE_PORTC_HOTPLUG_CPT;
 887                         break;
 888                 case PORT_D:
 889                         bit = SDE_PORTD_HOTPLUG_CPT;
 890                         break;
 891                 default:
 892                         return true;
 893                 }
 894         }
 895
 896         return I915_READ(SDEISR) & bit;
 897 }
 898
 899 static const char *state_string(bool enabled)
 900 {
 901         return enabled ? "on" : "off";
 902 }
 903
 904 /* Only for pre-ILK configs */
 905 void assert_pll(struct drm_i915_private *dev_priv,
 906                 enum pipe pipe, bool state)
 907 {
 908         int reg;
 909         u32 val;
 910         bool cur_state;
 911
 912         reg = DPLL(pipe);
 913         val = I915_READ(reg);
 914         cur_state = !!(val & DPLL_VCO_ENABLE);
 915         WARN(cur_state != state,
 916              "PLL state assertion failure (expected %s, current %s)\n",
 917              state_string(state), state_string(cur_state));
 918 }
 919
 920 /* XXX: the dsi pll is shared between MIPI DSI ports */
 921 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 922 {
 923         u32 val;
 924         bool cur_state;
 925
 926         mutex_lock(&dev_priv->dpio_lock);
 927         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 928         mutex_unlock(&dev_priv->dpio_lock);
 929
 930         cur_state = val & DSI_PLL_VCO_EN;
 931         WARN(cur_state != state,
 932              "DSI PLL state assertion failure (expected %s, current %s)\n",
 933              state_string(state), state_string(cur_state));
 934 }
 935 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 936 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 937
 938 struct intel_shared_dpll *
 939 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 940 {
 941         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 942
 943         if (crtc->config.shared_dpll < 0)
 944                 return NULL;
 945
 946         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 947 }
 948
 949 /* For ILK+ */
 950 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 951                         struct intel_shared_dpll *pll,
 952                         bool state)
 953 {
 954         bool cur_state;
 955         struct intel_dpll_hw_state hw_state;
 956
 957         if (HAS_PCH_LPT(dev_priv->dev)) {
 958                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 959                 return;
 960         }
 961
 962         if (WARN (!pll,
 963                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 964                 return;
 965
 966         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 967         WARN(cur_state != state,
 968              "%s assertion failure (expected %s, current %s)\n",
 969              pll->name, state_string(state), state_string(cur_state));
 970 }
 971
 972 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 973                           enum pipe pipe, bool state)
 974 {
 975         int reg;
 976         u32 val;
 977         bool cur_state;
 978         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 979                                                                       pipe);
 980
 981         if (HAS_DDI(dev_priv->dev)) {
 982                 /* DDI does not have a specific FDI_TX register */
 983                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 984                 val = I915_READ(reg);
 985                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 986         } else {
 987                 reg = FDI_TX_CTL(pipe);
 988                 val = I915_READ(reg);
 989                 cur_state = !!(val & FDI_TX_ENABLE);
 990         }
 991         WARN(cur_state != state,
 992              "FDI TX state assertion failure (expected %s, current %s)\n",
 993              state_string(state), state_string(cur_state));
 994 }
 995 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 996 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 997
 998 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 999                           enum pipe pipe, bool state)
1000 {
1001         int reg;
1002         u32 val;
1003         bool cur_state;
1004
1005         reg = FDI_RX_CTL(pipe);
1006         val = I915_READ(reg);
1007         cur_state = !!(val & FDI_RX_ENABLE);
1008         WARN(cur_state != state,
1009              "FDI RX state assertion failure (expected %s, current %s)\n",
1010              state_string(state), state_string(cur_state));
1011 }
1012 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1014
1015 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1016                                       enum pipe pipe)
1017 {
1018         int reg;
1019         u32 val;
1020
1021         /* ILK FDI PLL is always enabled */
1022         if (dev_priv->info->gen == 5)
1023                 return;
1024
1025         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1026         if (HAS_DDI(dev_priv->dev))
1027                 return;
1028
1029         reg = FDI_TX_CTL(pipe);
1030         val = I915_READ(reg);
1031         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1032 }
1033
1034 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1035                        enum pipe pipe, bool state)
1036 {
1037         int reg;
1038         u32 val;
1039         bool cur_state;
1040
1041         reg = FDI_RX_CTL(pipe);
1042         val = I915_READ(reg);
1043         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1044         WARN(cur_state != state,
1045              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1046              state_string(state), state_string(cur_state));
1047 }
1048
1049 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1050                                   enum pipe pipe)
1051 {
1052         int pp_reg, lvds_reg;
1053         u32 val;
1054         enum pipe panel_pipe = PIPE_A;
1055         bool locked = true;
1056
1057         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1058                 pp_reg = PCH_PP_CONTROL;
1059                 lvds_reg = PCH_LVDS;
1060         } else {
1061                 pp_reg = PP_CONTROL;
1062                 lvds_reg = LVDS;
1063         }
1064
1065         val = I915_READ(pp_reg);
1066         if (!(val & PANEL_POWER_ON) ||
1067             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1068                 locked = false;
1069
1070         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1071                 panel_pipe = PIPE_B;
1072
1073         WARN(panel_pipe == pipe && locked,
1074              "panel assertion failure, pipe %c regs locked\n",
1075              pipe_name(pipe));
1076 }
1077
1078 static void assert_cursor(struct drm_i915_private *dev_priv,
1079                           enum pipe pipe, bool state)
1080 {
1081         struct drm_device *dev = dev_priv->dev;
1082         bool cur_state;
1083
1084         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1085                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1086         else if (IS_845G(dev) || IS_I865G(dev))
1087                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1088         else
1089                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1090
1091         WARN(cur_state != state,
1092              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1093              pipe_name(pipe), state_string(state), state_string(cur_state));
1094 }
1095 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1096 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1097
1098 void assert_pipe(struct drm_i915_private *dev_priv,
1099                  enum pipe pipe, bool state)
1100 {
1101         int reg;
1102         u32 val;
1103         bool cur_state;
1104         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1105                                                                       pipe);
1106
1107         /* if we need the pipe A quirk it must be always on */
1108         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1109                 state = true;
1110
1111         if (!intel_display_power_enabled(dev_priv->dev,
1112                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1113                 cur_state = false;
1114         } else {
1115                 reg = PIPECONF(cpu_transcoder);
1116                 val = I915_READ(reg);
1117                 cur_state = !!(val & PIPECONF_ENABLE);
1118         }
1119
1120         WARN(cur_state != state,
1121              "pipe %c assertion failure (expected %s, current %s)\n",
1122              pipe_name(pipe), state_string(state), state_string(cur_state));
1123 }
1124
1125 static void assert_plane(struct drm_i915_private *dev_priv,
1126                          enum plane plane, bool state)
1127 {
1128         int reg;
1129         u32 val;
1130         bool cur_state;
1131
1132         reg = DSPCNTR(plane);
1133         val = I915_READ(reg);
1134         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1135         WARN(cur_state != state,
1136              "plane %c assertion failure (expected %s, current %s)\n",
1137              plane_name(plane), state_string(state), state_string(cur_state));
1138 }
1139
1140 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1141 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1142
1143 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1144                                    enum pipe pipe)
1145 {
1146         struct drm_device *dev = dev_priv->dev;
1147         int reg, i;
1148         u32 val;
1149         int cur_pipe;
1150
1151         /* Primary planes are fixed to pipes on gen4+ */
1152         if (INTEL_INFO(dev)->gen >= 4) {
1153                 reg = DSPCNTR(pipe);
1154                 val = I915_READ(reg);
1155                 WARN((val & DISPLAY_PLANE_ENABLE),
1156                      "plane %c assertion failure, should be disabled but not\n",
1157                      plane_name(pipe));
1158                 return;
1159         }
1160
1161         /* Need to check both planes against the pipe */
1162         for_each_pipe(i) {
1163                 reg = DSPCNTR(i);
1164                 val = I915_READ(reg);
1165                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1166                         DISPPLANE_SEL_PIPE_SHIFT;
1167                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1168                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1169                      plane_name(i), pipe_name(pipe));
1170         }
1171 }
1172
1173 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1174                                     enum pipe pipe)
1175 {
1176         struct drm_device *dev = dev_priv->dev;
1177         int reg, i;
1178         u32 val;
1179
1180         if (IS_VALLEYVIEW(dev)) {
1181                 for (i = 0; i < dev_priv->num_plane; i++) {
1182                         reg = SPCNTR(pipe, i);
1183                         val = I915_READ(reg);
1184                         WARN((val & SP_ENABLE),
1185                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1186                              sprite_name(pipe, i), pipe_name(pipe));
1187                 }
1188         } else if (INTEL_INFO(dev)->gen >= 7) {
1189                 reg = SPRCTL(pipe);
1190                 val = I915_READ(reg);
1191                 WARN((val & SPRITE_ENABLE),
1192                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1193                      plane_name(pipe), pipe_name(pipe));
1194         } else if (INTEL_INFO(dev)->gen >= 5) {
1195                 reg = DVSCNTR(pipe);
1196                 val = I915_READ(reg);
1197                 WARN((val & DVS_ENABLE),
1198                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1199                      plane_name(pipe), pipe_name(pipe));
1200         }
1201 }
1202
1203 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1204 {
1205         u32 val;
1206         bool enabled;
1207
1208         if (HAS_PCH_LPT(dev_priv->dev)) {
1209                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1210                 return;
1211         }
1212
1213         val = I915_READ(PCH_DREF_CONTROL);
1214         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1215                             DREF_SUPERSPREAD_SOURCE_MASK));
1216         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1217 }
1218
1219 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1220                                            enum pipe pipe)
1221 {
1222         int reg;
1223         u32 val;
1224         bool enabled;
1225
1226         reg = PCH_TRANSCONF(pipe);
1227         val = I915_READ(reg);
1228         enabled = !!(val & TRANS_ENABLE);
1229         WARN(enabled,
1230              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1231              pipe_name(pipe));
1232 }
1233
1234 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1235                             enum pipe pipe, u32 port_sel, u32 val)
1236 {
1237         if ((val & DP_PORT_EN) == 0)
1238                 return false;
1239
1240         if (HAS_PCH_CPT(dev_priv->dev)) {
1241                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1242                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1243                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1244                         return false;
1245         } else {
1246                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1247                         return false;
1248         }
1249         return true;
1250 }
1251
1252 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1253                               enum pipe pipe, u32 val)
1254 {
1255         if ((val & SDVO_ENABLE) == 0)
1256                 return false;
1257
1258         if (HAS_PCH_CPT(dev_priv->dev)) {
1259                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1260                         return false;
1261         } else {
1262                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1263                         return false;
1264         }
1265         return true;
1266 }
1267
1268 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1269                               enum pipe pipe, u32 val)
1270 {
1271         if ((val & LVDS_PORT_EN) == 0)
1272                 return false;
1273
1274         if (HAS_PCH_CPT(dev_priv->dev)) {
1275                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1276                         return false;
1277         } else {
1278                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1279                         return false;
1280         }
1281         return true;
1282 }
1283
1284 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1285                               enum pipe pipe, u32 val)
1286 {
1287         if ((val & ADPA_DAC_ENABLE) == 0)
1288                 return false;
1289         if (HAS_PCH_CPT(dev_priv->dev)) {
1290                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1291                         return false;
1292         } else {
1293                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1294                         return false;
1295         }
1296         return true;
1297 }
1298
1299 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1300                                    enum pipe pipe, int reg, u32 port_sel)
1301 {
1302         u32 val = I915_READ(reg);
1303         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1304              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1305              reg, pipe_name(pipe));
1306
1307         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1308              && (val & DP_PIPEB_SELECT),
1309              "IBX PCH dp port still using transcoder B\n");
1310 }
1311
1312 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1313                                      enum pipe pipe, int reg)
1314 {
1315         u32 val = I915_READ(reg);
1316         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1317              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1318              reg, pipe_name(pipe));
1319
1320         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1321              && (val & SDVO_PIPE_B_SELECT),
1322              "IBX PCH hdmi port still using transcoder B\n");
1323 }
1324
1325 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1326                                       enum pipe pipe)
1327 {
1328         int reg;
1329         u32 val;
1330
1331         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1332         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1333         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1334
1335         reg = PCH_ADPA;
1336         val = I915_READ(reg);
1337         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1338              "PCH VGA enabled on transcoder %c, should be disabled\n",
1339              pipe_name(pipe));
1340
1341         reg = PCH_LVDS;
1342         val = I915_READ(reg);
1343         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1344              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1345              pipe_name(pipe));
1346
1347         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1348         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1349         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1350 }
1351
1352 static void intel_init_dpio(struct drm_device *dev)
1353 {
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355
1356         if (!IS_VALLEYVIEW(dev))
1357                 return;
1358
1359         /*
1360          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1361          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1362          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1363          *   b. The other bits such as sfr settings / modesel may all be set
1364          *      to 0.
1365          *
1366          * This should only be done on init and resume from S3 with both
1367          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1368          */
1369         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1370 }
1371
1372 static void vlv_enable_pll(struct intel_crtc *crtc)
1373 {
1374         struct drm_device *dev = crtc->base.dev;
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int reg = DPLL(crtc->pipe);
1377         u32 dpll = crtc->config.dpll_hw_state.dpll;
1378
1379         assert_pipe_disabled(dev_priv, crtc->pipe);
1380
1381         /* No really, not for ILK+ */
1382         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1383
1384         /* PLL is protected by panel, make sure we can write it */
1385         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1386                 assert_panel_unlocked(dev_priv, crtc->pipe);
1387
1388         I915_WRITE(reg, dpll);
1389         POSTING_READ(reg);
1390         udelay(150);
1391
1392         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1393                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1394
1395         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1396         POSTING_READ(DPLL_MD(crtc->pipe));
1397
1398         /* We do this three times for luck */
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150); /* wait for warmup */
1402         I915_WRITE(reg, dpll);
1403         POSTING_READ(reg);
1404         udelay(150); /* wait for warmup */
1405         I915_WRITE(reg, dpll);
1406         POSTING_READ(reg);
1407         udelay(150); /* wait for warmup */
1408 }
1409
1410 static void i9xx_enable_pll(struct intel_crtc *crtc)
1411 {
1412         struct drm_device *dev = crtc->base.dev;
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         int reg = DPLL(crtc->pipe);
1415         u32 dpll = crtc->config.dpll_hw_state.dpll;
1416
1417         assert_pipe_disabled(dev_priv, crtc->pipe);
1418
1419         /* No really, not for ILK+ */
1420         BUG_ON(dev_priv->info->gen >= 5);
1421
1422         /* PLL is protected by panel, make sure we can write it */
1423         if (IS_MOBILE(dev) && !IS_I830(dev))
1424                 assert_panel_unlocked(dev_priv, crtc->pipe);
1425
1426         I915_WRITE(reg, dpll);
1427
1428         /* Wait for the clocks to stabilize. */
1429         POSTING_READ(reg);
1430         udelay(150);
1431
1432         if (INTEL_INFO(dev)->gen >= 4) {
1433                 I915_WRITE(DPLL_MD(crtc->pipe),
1434                            crtc->config.dpll_hw_state.dpll_md);
1435         } else {
1436                 /* The pixel multiplier can only be updated once the
1437                  * DPLL is enabled and the clocks are stable.
1438                  *
1439                  * So write it again.
1440                  */
1441                 I915_WRITE(reg, dpll);
1442         }
1443
1444         /* We do this three times for luck */
1445         I915_WRITE(reg, dpll);
1446         POSTING_READ(reg);
1447         udelay(150); /* wait for warmup */
1448         I915_WRITE(reg, dpll);
1449         POSTING_READ(reg);
1450         udelay(150); /* wait for warmup */
1451         I915_WRITE(reg, dpll);
1452         POSTING_READ(reg);
1453         udelay(150); /* wait for warmup */
1454 }
1455
1456 /**
1457  * i9xx_disable_pll - disable a PLL
1458  * @dev_priv: i915 private structure
1459  * @pipe: pipe PLL to disable
1460  *
1461  * Disable the PLL for @pipe, making sure the pipe is off first.
1462  *
1463  * Note!  This is for pre-ILK only.
1464  */
1465 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1466 {
1467         /* Don't disable pipe A or pipe A PLLs if needed */
1468         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1469                 return;
1470
1471         /* Make sure the pipe isn't still relying on us */
1472         assert_pipe_disabled(dev_priv, pipe);
1473
1474         I915_WRITE(DPLL(pipe), 0);
1475         POSTING_READ(DPLL(pipe));
1476 }
1477
1478 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1479 {
1480         u32 val = 0;
1481
1482         /* Make sure the pipe isn't still relying on us */
1483         assert_pipe_disabled(dev_priv, pipe);
1484
1485         /* Leave integrated clock source enabled */
1486         if (pipe == PIPE_B)
1487                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1488         I915_WRITE(DPLL(pipe), val);
1489         POSTING_READ(DPLL(pipe));
1490 }
1491
1492 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1493 {
1494         u32 port_mask;
1495
1496         if (!port)
1497                 port_mask = DPLL_PORTB_READY_MASK;
1498         else
1499                 port_mask = DPLL_PORTC_READY_MASK;
1500
1501         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1502                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1503                      'B' + port, I915_READ(DPLL(0)));
1504 }
1505
1506 /**
1507  * ironlake_enable_shared_dpll - enable PCH PLL
1508  * @dev_priv: i915 private structure
1509  * @pipe: pipe PLL to enable
1510  *
1511  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1512  * drives the transcoder clock.
1513  */
1514 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1515 {
1516         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1517         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1518
1519         /* PCH PLLs only available on ILK, SNB and IVB */
1520         BUG_ON(dev_priv->info->gen < 5);
1521         if (WARN_ON(pll == NULL))
1522                 return;
1523
1524         if (WARN_ON(pll->refcount == 0))
1525                 return;
1526
1527         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1528                       pll->name, pll->active, pll->on,
1529                       crtc->base.base.id);
1530
1531         if (pll->active++) {
1532                 WARN_ON(!pll->on);
1533                 assert_shared_dpll_enabled(dev_priv, pll);
1534                 return;
1535         }
1536         WARN_ON(pll->on);
1537
1538         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1539         pll->enable(dev_priv, pll);
1540         pll->on = true;
1541 }
1542
1543 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1544 {
1545         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1546         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1547
1548         /* PCH only available on ILK+ */
1549         BUG_ON(dev_priv->info->gen < 5);
1550         if (WARN_ON(pll == NULL))
1551                return;
1552
1553         if (WARN_ON(pll->refcount == 0))
1554                 return;
1555
1556         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1557                       pll->name, pll->active, pll->on,
1558                       crtc->base.base.id);
1559
1560         if (WARN_ON(pll->active == 0)) {
1561                 assert_shared_dpll_disabled(dev_priv, pll);
1562                 return;
1563         }
1564
1565         assert_shared_dpll_enabled(dev_priv, pll);
1566         WARN_ON(!pll->on);
1567         if (--pll->active)
1568                 return;
1569
1570         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1571         pll->disable(dev_priv, pll);
1572         pll->on = false;
1573 }
1574
1575 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1576                                            enum pipe pipe)
1577 {
1578         struct drm_device *dev = dev_priv->dev;
1579         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1581         uint32_t reg, val, pipeconf_val;
1582
1583         /* PCH only available on ILK+ */
1584         BUG_ON(dev_priv->info->gen < 5);
1585
1586         /* Make sure PCH DPLL is enabled */
1587         assert_shared_dpll_enabled(dev_priv,
1588                                    intel_crtc_to_shared_dpll(intel_crtc));
1589
1590         /* FDI must be feeding us bits for PCH ports */
1591         assert_fdi_tx_enabled(dev_priv, pipe);
1592         assert_fdi_rx_enabled(dev_priv, pipe);
1593
1594         if (HAS_PCH_CPT(dev)) {
1595                 /* Workaround: Set the timing override bit before enabling the
1596                  * pch transcoder. */
1597                 reg = TRANS_CHICKEN2(pipe);
1598                 val = I915_READ(reg);
1599                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1600                 I915_WRITE(reg, val);
1601         }
1602
1603         reg = PCH_TRANSCONF(pipe);
1604         val = I915_READ(reg);
1605         pipeconf_val = I915_READ(PIPECONF(pipe));
1606
1607         if (HAS_PCH_IBX(dev_priv->dev)) {
1608                 /*
1609                  * make the BPC in transcoder be consistent with
1610                  * that in pipeconf reg.
1611                  */
1612                 val &= ~PIPECONF_BPC_MASK;
1613                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1614         }
1615
1616         val &= ~TRANS_INTERLACE_MASK;
1617         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1618                 if (HAS_PCH_IBX(dev_priv->dev) &&
1619                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1620                         val |= TRANS_LEGACY_INTERLACED_ILK;
1621                 else
1622                         val |= TRANS_INTERLACED;
1623         else
1624                 val |= TRANS_PROGRESSIVE;
1625
1626         I915_WRITE(reg, val | TRANS_ENABLE);
1627         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1628                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1629 }
1630
1631 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1632                                       enum transcoder cpu_transcoder)
1633 {
1634         u32 val, pipeconf_val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638
1639         /* FDI must be feeding us bits for PCH ports */
1640         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1641         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1642
1643         /* Workaround: set timing override bit. */
1644         val = I915_READ(_TRANSA_CHICKEN2);
1645         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1646         I915_WRITE(_TRANSA_CHICKEN2, val);
1647
1648         val = TRANS_ENABLE;
1649         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1650
1651         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1652             PIPECONF_INTERLACED_ILK)
1653                 val |= TRANS_INTERLACED;
1654         else
1655                 val |= TRANS_PROGRESSIVE;
1656
1657         I915_WRITE(LPT_TRANSCONF, val);
1658         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1659                 DRM_ERROR("Failed to enable PCH transcoder\n");
1660 }
1661
1662 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1663                                             enum pipe pipe)
1664 {
1665         struct drm_device *dev = dev_priv->dev;
1666         uint32_t reg, val;
1667
1668         /* FDI relies on the transcoder */
1669         assert_fdi_tx_disabled(dev_priv, pipe);
1670         assert_fdi_rx_disabled(dev_priv, pipe);
1671
1672         /* Ports must be off as well */
1673         assert_pch_ports_disabled(dev_priv, pipe);
1674
1675         reg = PCH_TRANSCONF(pipe);
1676         val = I915_READ(reg);
1677         val &= ~TRANS_ENABLE;
1678         I915_WRITE(reg, val);
1679         /* wait for PCH transcoder off, transcoder state */
1680         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1681                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1682
1683         if (!HAS_PCH_IBX(dev)) {
1684                 /* Workaround: Clear the timing override chicken bit again. */
1685                 reg = TRANS_CHICKEN2(pipe);
1686                 val = I915_READ(reg);
1687                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1688                 I915_WRITE(reg, val);
1689         }
1690 }
1691
1692 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1693 {
1694         u32 val;
1695
1696         val = I915_READ(LPT_TRANSCONF);
1697         val &= ~TRANS_ENABLE;
1698         I915_WRITE(LPT_TRANSCONF, val);
1699         /* wait for PCH transcoder off, transcoder state */
1700         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1701                 DRM_ERROR("Failed to disable PCH transcoder\n");
1702
1703         /* Workaround: clear timing override bit. */
1704         val = I915_READ(_TRANSA_CHICKEN2);
1705         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1706         I915_WRITE(_TRANSA_CHICKEN2, val);
1707 }
1708
1709 /**
1710  * intel_enable_pipe - enable a pipe, asserting requirements
1711  * @dev_priv: i915 private structure
1712  * @pipe: pipe to enable
1713  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1714  *
1715  * Enable @pipe, making sure that various hardware specific requirements
1716  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1717  *
1718  * @pipe should be %PIPE_A or %PIPE_B.
1719  *
1720  * Will wait until the pipe is actually running (i.e. first vblank) before
1721  * returning.
1722  */
1723 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1724                               bool pch_port, bool dsi)
1725 {
1726         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727                                                                       pipe);
1728         enum pipe pch_transcoder;
1729         int reg;
1730         u32 val;
1731
1732         assert_planes_disabled(dev_priv, pipe);
1733         assert_cursor_disabled(dev_priv, pipe);
1734         assert_sprites_disabled(dev_priv, pipe);
1735
1736         if (HAS_PCH_LPT(dev_priv->dev))
1737                 pch_transcoder = TRANSCODER_A;
1738         else
1739                 pch_transcoder = pipe;
1740
1741         /*
1742          * A pipe without a PLL won't actually be able to drive bits from
1743          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1744          * need the check.
1745          */
1746         if (!HAS_PCH_SPLIT(dev_priv->dev))
1747                 if (dsi)
1748                         assert_dsi_pll_enabled(dev_priv);
1749                 else
1750                         assert_pll_enabled(dev_priv, pipe);
1751         else {
1752                 if (pch_port) {
1753                         /* if driving the PCH, we need FDI enabled */
1754                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1755                         assert_fdi_tx_pll_enabled(dev_priv,
1756                                                   (enum pipe) cpu_transcoder);
1757                 }
1758                 /* FIXME: assert CPU port conditions for SNB+ */
1759         }
1760
1761         reg = PIPECONF(cpu_transcoder);
1762         val = I915_READ(reg);
1763         if (val & PIPECONF_ENABLE)
1764                 return;
1765
1766         I915_WRITE(reg, val | PIPECONF_ENABLE);
1767         intel_wait_for_vblank(dev_priv->dev, pipe);
1768 }
1769
1770 /**
1771  * intel_disable_pipe - disable a pipe, asserting requirements
1772  * @dev_priv: i915 private structure
1773  * @pipe: pipe to disable
1774  *
1775  * Disable @pipe, making sure that various hardware specific requirements
1776  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1777  *
1778  * @pipe should be %PIPE_A or %PIPE_B.
1779  *
1780  * Will wait until the pipe has shut down before returning.
1781  */
1782 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1783                                enum pipe pipe)
1784 {
1785         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1786                                                                       pipe);
1787         int reg;
1788         u32 val;
1789
1790         /*
1791          * Make sure planes won't keep trying to pump pixels to us,
1792          * or we might hang the display.
1793          */
1794         assert_planes_disabled(dev_priv, pipe);
1795         assert_cursor_disabled(dev_priv, pipe);
1796         assert_sprites_disabled(dev_priv, pipe);
1797
1798         /* Don't disable pipe A or pipe A PLLs if needed */
1799         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800                 return;
1801
1802         reg = PIPECONF(cpu_transcoder);
1803         val = I915_READ(reg);
1804         if ((val & PIPECONF_ENABLE) == 0)
1805                 return;
1806
1807         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809 }
1810
1811 /*
1812  * Plane regs are double buffered, going from enabled->disabled needs a
1813  * trigger in order to latch.  The display address reg provides this.
1814  */
1815 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1816                                enum plane plane)
1817 {
1818         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1819
1820         I915_WRITE(reg, I915_READ(reg));
1821         POSTING_READ(reg);
1822 }
1823
1824 /**
1825  * intel_enable_primary_plane - enable the primary plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1833                                        enum plane plane, enum pipe pipe)
1834 {
1835         struct intel_crtc *intel_crtc =
1836                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1837         int reg;
1838         u32 val;
1839
1840         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1841         assert_pipe_enabled(dev_priv, pipe);
1842
1843         WARN(!intel_crtc->primary_disabled, "Primary plane already enabled\n");
1844
1845         intel_crtc->primary_disabled = false;
1846
1847         reg = DSPCNTR(plane);
1848         val = I915_READ(reg);
1849         if (val & DISPLAY_PLANE_ENABLE)
1850                 return;
1851
1852         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1853         intel_flush_primary_plane(dev_priv, plane);
1854         intel_wait_for_vblank(dev_priv->dev, pipe);
1855 }
1856
1857 /**
1858  * intel_disable_primary_plane - disable the primary plane
1859  * @dev_priv: i915 private structure
1860  * @plane: plane to disable
1861  * @pipe: pipe consuming the data
1862  *
1863  * Disable @plane; should be an independent operation.
1864  */
1865 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1866                                         enum plane plane, enum pipe pipe)
1867 {
1868         struct intel_crtc *intel_crtc =
1869                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1870         int reg;
1871         u32 val;
1872
1873         WARN(intel_crtc->primary_disabled, "Primary plane already disabled\n");
1874
1875         intel_crtc->primary_disabled = true;
1876
1877         reg = DSPCNTR(plane);
1878         val = I915_READ(reg);
1879         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1880                 return;
1881
1882         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1883         intel_flush_primary_plane(dev_priv, plane);
1884         intel_wait_for_vblank(dev_priv->dev, pipe);
1885 }
1886
1887 static bool need_vtd_wa(struct drm_device *dev)
1888 {
1889 #ifdef CONFIG_INTEL_IOMMU
1890         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1891                 return true;
1892 #endif
1893         return false;
1894 }
1895
1896 int
1897 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1898                            struct drm_i915_gem_object *obj,
1899                            struct intel_ring_buffer *pipelined)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         u32 alignment;
1903         int ret;
1904
1905         switch (obj->tiling_mode) {
1906         case I915_TILING_NONE:
1907                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908                         alignment = 128 * 1024;
1909                 else if (INTEL_INFO(dev)->gen >= 4)
1910                         alignment = 4 * 1024;
1911                 else
1912                         alignment = 64 * 1024;
1913                 break;
1914         case I915_TILING_X:
1915                 /* pin() will align the object as required by fence */
1916                 alignment = 0;
1917                 break;
1918         case I915_TILING_Y:
1919                 /* Despite that we check this in framebuffer_init userspace can
1920                  * screw us over and change the tiling after the fact. Only
1921                  * pinned buffers can't change their tiling. */
1922                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1923                 return -EINVAL;
1924         default:
1925                 BUG();
1926         }
1927
1928         /* Note that the w/a also requires 64 PTE of padding following the
1929          * bo. We currently fill all unused PTE with the shadow page and so
1930          * we should always have valid PTE following the scanout preventing
1931          * the VT-d warning.
1932          */
1933         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1934                 alignment = 256 * 1024;
1935
1936         dev_priv->mm.interruptible = false;
1937         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1938         if (ret)
1939                 goto err_interruptible;
1940
1941         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1942          * fence, whereas 965+ only requires a fence if using
1943          * framebuffer compression.  For simplicity, we always install
1944          * a fence as the cost is not that onerous.
1945          */
1946         ret = i915_gem_object_get_fence(obj);
1947         if (ret)
1948                 goto err_unpin;
1949
1950         i915_gem_object_pin_fence(obj);
1951
1952         dev_priv->mm.interruptible = true;
1953         return 0;
1954
1955 err_unpin:
1956         i915_gem_object_unpin_from_display_plane(obj);
1957 err_interruptible:
1958         dev_priv->mm.interruptible = true;
1959         return ret;
1960 }
1961
1962 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1963 {
1964         i915_gem_object_unpin_fence(obj);
1965         i915_gem_object_unpin_from_display_plane(obj);
1966 }
1967
1968 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1969  * is assumed to be a power-of-two. */
1970 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1971                                              unsigned int tiling_mode,
1972                                              unsigned int cpp,
1973                                              unsigned int pitch)
1974 {
1975         if (tiling_mode != I915_TILING_NONE) {
1976                 unsigned int tile_rows, tiles;
1977
1978                 tile_rows = *y / 8;
1979                 *y %= 8;
1980
1981                 tiles = *x / (512/cpp);
1982                 *x %= 512/cpp;
1983
1984                 return tile_rows * pitch * 8 + tiles * 4096;
1985         } else {
1986                 unsigned int offset;
1987
1988                 offset = *y * pitch + *x * cpp;
1989                 *y = 0;
1990                 *x = (offset & 4095) / cpp;
1991                 return offset & -4096;
1992         }
1993 }
1994
1995 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1996                              int x, int y)
1997 {
1998         struct drm_device *dev = crtc->dev;
1999         struct drm_i915_private *dev_priv = dev->dev_private;
2000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2001         struct intel_framebuffer *intel_fb;
2002         struct drm_i915_gem_object *obj;
2003         int plane = intel_crtc->plane;
2004         unsigned long linear_offset;
2005         u32 dspcntr;
2006         u32 reg;
2007
2008         switch (plane) {
2009         case 0:
2010         case 1:
2011                 break;
2012         default:
2013                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2014                 return -EINVAL;
2015         }
2016
2017         intel_fb = to_intel_framebuffer(fb);
2018         obj = intel_fb->obj;
2019
2020         reg = DSPCNTR(plane);
2021         dspcntr = I915_READ(reg);
2022         /* Mask out pixel format bits in case we change it */
2023         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2024         switch (fb->pixel_format) {
2025         case DRM_FORMAT_C8:
2026                 dspcntr |= DISPPLANE_8BPP;
2027                 break;
2028         case DRM_FORMAT_XRGB1555:
2029         case DRM_FORMAT_ARGB1555:
2030                 dspcntr |= DISPPLANE_BGRX555;
2031                 break;
2032         case DRM_FORMAT_RGB565:
2033                 dspcntr |= DISPPLANE_BGRX565;
2034                 break;
2035         case DRM_FORMAT_XRGB8888:
2036         case DRM_FORMAT_ARGB8888:
2037                 dspcntr |= DISPPLANE_BGRX888;
2038                 break;
2039         case DRM_FORMAT_XBGR8888:
2040         case DRM_FORMAT_ABGR8888:
2041                 dspcntr |= DISPPLANE_RGBX888;
2042                 break;
2043         case DRM_FORMAT_XRGB2101010:
2044         case DRM_FORMAT_ARGB2101010:
2045                 dspcntr |= DISPPLANE_BGRX101010;
2046                 break;
2047         case DRM_FORMAT_XBGR2101010:
2048         case DRM_FORMAT_ABGR2101010:
2049                 dspcntr |= DISPPLANE_RGBX101010;
2050                 break;
2051         default:
2052                 BUG();
2053         }
2054
2055         if (INTEL_INFO(dev)->gen >= 4) {
2056                 if (obj->tiling_mode != I915_TILING_NONE)
2057                         dspcntr |= DISPPLANE_TILED;
2058                 else
2059                         dspcntr &= ~DISPPLANE_TILED;
2060         }
2061
2062         if (IS_G4X(dev))
2063                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2064
2065         I915_WRITE(reg, dspcntr);
2066
2067         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2068
2069         if (INTEL_INFO(dev)->gen >= 4) {
2070                 intel_crtc->dspaddr_offset =
2071                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2072                                                        fb->bits_per_pixel / 8,
2073                                                        fb->pitches[0]);
2074                 linear_offset -= intel_crtc->dspaddr_offset;
2075         } else {
2076                 intel_crtc->dspaddr_offset = linear_offset;
2077         }
2078
2079         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2080                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2081                       fb->pitches[0]);
2082         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2083         if (INTEL_INFO(dev)->gen >= 4) {
2084                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2085                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2086                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2087                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2088         } else
2089                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2090         POSTING_READ(reg);
2091
2092         return 0;
2093 }
2094
2095 static int ironlake_update_plane(struct drm_crtc *crtc,
2096                                  struct drm_framebuffer *fb, int x, int y)
2097 {
2098         struct drm_device *dev = crtc->dev;
2099         struct drm_i915_private *dev_priv = dev->dev_private;
2100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101         struct intel_framebuffer *intel_fb;
2102         struct drm_i915_gem_object *obj;
2103         int plane = intel_crtc->plane;
2104         unsigned long linear_offset;
2105         u32 dspcntr;
2106         u32 reg;
2107
2108         switch (plane) {
2109         case 0:
2110         case 1:
2111         case 2:
2112                 break;
2113         default:
2114                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2115                 return -EINVAL;
2116         }
2117
2118         intel_fb = to_intel_framebuffer(fb);
2119         obj = intel_fb->obj;
2120
2121         reg = DSPCNTR(plane);
2122         dspcntr = I915_READ(reg);
2123         /* Mask out pixel format bits in case we change it */
2124         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2125         switch (fb->pixel_format) {
2126         case DRM_FORMAT_C8:
2127                 dspcntr |= DISPPLANE_8BPP;
2128                 break;
2129         case DRM_FORMAT_RGB565:
2130                 dspcntr |= DISPPLANE_BGRX565;
2131                 break;
2132         case DRM_FORMAT_XRGB8888:
2133         case DRM_FORMAT_ARGB8888:
2134                 dspcntr |= DISPPLANE_BGRX888;
2135                 break;
2136         case DRM_FORMAT_XBGR8888:
2137         case DRM_FORMAT_ABGR8888:
2138                 dspcntr |= DISPPLANE_RGBX888;
2139                 break;
2140         case DRM_FORMAT_XRGB2101010:
2141         case DRM_FORMAT_ARGB2101010:
2142                 dspcntr |= DISPPLANE_BGRX101010;
2143                 break;
2144         case DRM_FORMAT_XBGR2101010:
2145         case DRM_FORMAT_ABGR2101010:
2146                 dspcntr |= DISPPLANE_RGBX101010;
2147                 break;
2148         default:
2149                 BUG();
2150         }
2151
2152         if (obj->tiling_mode != I915_TILING_NONE)
2153                 dspcntr |= DISPPLANE_TILED;
2154         else
2155                 dspcntr &= ~DISPPLANE_TILED;
2156
2157         if (IS_HASWELL(dev))
2158                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2159         else
2160                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2161
2162         I915_WRITE(reg, dspcntr);
2163
2164         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2165         intel_crtc->dspaddr_offset =
2166                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2167                                                fb->bits_per_pixel / 8,
2168                                                fb->pitches[0]);
2169         linear_offset -= intel_crtc->dspaddr_offset;
2170
2171         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2172                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2173                       fb->pitches[0]);
2174         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2175         I915_MODIFY_DISPBASE(DSPSURF(plane),
2176                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2177         if (IS_HASWELL(dev)) {
2178                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2179         } else {
2180                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2181                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2182         }
2183         POSTING_READ(reg);
2184
2185         return 0;
2186 }
2187
2188 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2189 static int
2190 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2191                            int x, int y, enum mode_set_atomic state)
2192 {
2193         struct drm_device *dev = crtc->dev;
2194         struct drm_i915_private *dev_priv = dev->dev_private;
2195
2196         if (dev_priv->display.disable_fbc)
2197                 dev_priv->display.disable_fbc(dev);
2198         intel_increase_pllclock(crtc);
2199
2200         return dev_priv->display.update_plane(crtc, fb, x, y);
2201 }
2202
2203 void intel_display_handle_reset(struct drm_device *dev)
2204 {
2205         struct drm_i915_private *dev_priv = dev->dev_private;
2206         struct drm_crtc *crtc;
2207
2208         /*
2209          * Flips in the rings have been nuked by the reset,
2210          * so complete all pending flips so that user space
2211          * will get its events and not get stuck.
2212          *
2213          * Also update the base address of all primary
2214          * planes to the the last fb to make sure we're
2215          * showing the correct fb after a reset.
2216          *
2217          * Need to make two loops over the crtcs so that we
2218          * don't try to grab a crtc mutex before the
2219          * pending_flip_queue really got woken up.
2220          */
2221
2222         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2223                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2224                 enum plane plane = intel_crtc->plane;
2225
2226                 intel_prepare_page_flip(dev, plane);
2227                 intel_finish_page_flip_plane(dev, plane);
2228         }
2229
2230         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2231                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2232
2233                 mutex_lock(&crtc->mutex);
2234                 if (intel_crtc->active)
2235                         dev_priv->display.update_plane(crtc, crtc->fb,
2236                                                        crtc->x, crtc->y);
2237                 mutex_unlock(&crtc->mutex);
2238         }
2239 }
2240
2241 static int
2242 intel_finish_fb(struct drm_framebuffer *old_fb)
2243 {
2244         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2245         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2246         bool was_interruptible = dev_priv->mm.interruptible;
2247         int ret;
2248
2249         /* Big Hammer, we also need to ensure that any pending
2250          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2251          * current scanout is retired before unpinning the old
2252          * framebuffer.
2253          *
2254          * This should only fail upon a hung GPU, in which case we
2255          * can safely continue.
2256          */
2257         dev_priv->mm.interruptible = false;
2258         ret = i915_gem_object_finish_gpu(obj);
2259         dev_priv->mm.interruptible = was_interruptible;
2260
2261         return ret;
2262 }
2263
2264 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_master_private *master_priv;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269
2270         if (!dev->primary->master)
2271                 return;
2272
2273         master_priv = dev->primary->master->driver_priv;
2274         if (!master_priv->sarea_priv)
2275                 return;
2276
2277         switch (intel_crtc->pipe) {
2278         case 0:
2279                 master_priv->sarea_priv->pipeA_x = x;
2280                 master_priv->sarea_priv->pipeA_y = y;
2281                 break;
2282         case 1:
2283                 master_priv->sarea_priv->pipeB_x = x;
2284                 master_priv->sarea_priv->pipeB_y = y;
2285                 break;
2286         default:
2287                 break;
2288         }
2289 }
2290
2291 static int
2292 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2293                     struct drm_framebuffer *fb)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298         struct drm_framebuffer *old_fb;
2299         int ret;
2300
2301         /* no fb bound */
2302         if (!fb) {
2303                 DRM_ERROR("No FB bound\n");
2304                 return 0;
2305         }
2306
2307         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2308                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2309                           plane_name(intel_crtc->plane),
2310                           INTEL_INFO(dev)->num_pipes);
2311                 return -EINVAL;
2312         }
2313
2314         mutex_lock(&dev->struct_mutex);
2315         ret = intel_pin_and_fence_fb_obj(dev,
2316                                          to_intel_framebuffer(fb)->obj,
2317                                          NULL);
2318         if (ret != 0) {
2319                 mutex_unlock(&dev->struct_mutex);
2320                 DRM_ERROR("pin & fence failed\n");
2321                 return ret;
2322         }
2323
2324         /*
2325          * Update pipe size and adjust fitter if needed: the reason for this is
2326          * that in compute_mode_changes we check the native mode (not the pfit
2327          * mode) to see if we can flip rather than do a full mode set. In the
2328          * fastboot case, we'll flip, but if we don't update the pipesrc and
2329          * pfit state, we'll end up with a big fb scanned out into the wrong
2330          * sized surface.
2331          *
2332          * To fix this properly, we need to hoist the checks up into
2333          * compute_mode_changes (or above), check the actual pfit state and
2334          * whether the platform allows pfit disable with pipe active, and only
2335          * then update the pipesrc and pfit state, even on the flip path.
2336          */
2337         if (i915_fastboot) {
2338                 const struct drm_display_mode *adjusted_mode =
2339                         &intel_crtc->config.adjusted_mode;
2340
2341                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2342                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2343                            (adjusted_mode->crtc_vdisplay - 1));
2344                 if (!intel_crtc->config.pch_pfit.enabled &&
2345                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2346                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2347                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2348                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2349                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2350                 }
2351         }
2352
2353         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2354         if (ret) {
2355                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2356                 mutex_unlock(&dev->struct_mutex);
2357                 DRM_ERROR("failed to update base address\n");
2358                 return ret;
2359         }
2360
2361         old_fb = crtc->fb;
2362         crtc->fb = fb;
2363         crtc->x = x;
2364         crtc->y = y;
2365
2366         if (old_fb) {
2367                 if (intel_crtc->active && old_fb != fb)
2368                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2369                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2370         }
2371
2372         intel_update_fbc(dev);
2373         intel_edp_psr_update(dev);
2374         mutex_unlock(&dev->struct_mutex);
2375
2376         intel_crtc_update_sarea_pos(crtc, x, y);
2377
2378         return 0;
2379 }
2380
2381 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2382 {
2383         struct drm_device *dev = crtc->dev;
2384         struct drm_i915_private *dev_priv = dev->dev_private;
2385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2386         int pipe = intel_crtc->pipe;
2387         u32 reg, temp;
2388
2389         /* enable normal train */
2390         reg = FDI_TX_CTL(pipe);
2391         temp = I915_READ(reg);
2392         if (IS_IVYBRIDGE(dev)) {
2393                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2394                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2395         } else {
2396                 temp &= ~FDI_LINK_TRAIN_NONE;
2397                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2398         }
2399         I915_WRITE(reg, temp);
2400
2401         reg = FDI_RX_CTL(pipe);
2402         temp = I915_READ(reg);
2403         if (HAS_PCH_CPT(dev)) {
2404                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2405                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2406         } else {
2407                 temp &= ~FDI_LINK_TRAIN_NONE;
2408                 temp |= FDI_LINK_TRAIN_NONE;
2409         }
2410         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2411
2412         /* wait one idle pattern time */
2413         POSTING_READ(reg);
2414         udelay(1000);
2415
2416         /* IVB wants error correction enabled */
2417         if (IS_IVYBRIDGE(dev))
2418                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2419                            FDI_FE_ERRC_ENABLE);
2420 }
2421
2422 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2423 {
2424         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2425 }
2426
2427 static void ivb_modeset_global_resources(struct drm_device *dev)
2428 {
2429         struct drm_i915_private *dev_priv = dev->dev_private;
2430         struct intel_crtc *pipe_B_crtc =
2431                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2432         struct intel_crtc *pipe_C_crtc =
2433                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2434         uint32_t temp;
2435
2436         /*
2437          * When everything is off disable fdi C so that we could enable fdi B
2438          * with all lanes. Note that we don't care about enabled pipes without
2439          * an enabled pch encoder.
2440          */
2441         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2442             !pipe_has_enabled_pch(pipe_C_crtc)) {
2443                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2444                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2445
2446                 temp = I915_READ(SOUTH_CHICKEN1);
2447                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2448                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2449                 I915_WRITE(SOUTH_CHICKEN1, temp);
2450         }
2451 }
2452
2453 /* The FDI link training functions for ILK/Ibexpeak. */
2454 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2455 {
2456         struct drm_device *dev = crtc->dev;
2457         struct drm_i915_private *dev_priv = dev->dev_private;
2458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2459         int pipe = intel_crtc->pipe;
2460         int plane = intel_crtc->plane;
2461         u32 reg, temp, tries;
2462
2463         /* FDI needs bits from pipe & plane first */
2464         assert_pipe_enabled(dev_priv, pipe);
2465         assert_plane_enabled(dev_priv, plane);
2466
2467         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468            for train result */
2469         reg = FDI_RX_IMR(pipe);
2470         temp = I915_READ(reg);
2471         temp &= ~FDI_RX_SYMBOL_LOCK;
2472         temp &= ~FDI_RX_BIT_LOCK;
2473         I915_WRITE(reg, temp);
2474         I915_READ(reg);
2475         udelay(150);
2476
2477         /* enable CPU FDI TX and PCH FDI RX */
2478         reg = FDI_TX_CTL(pipe);
2479         temp = I915_READ(reg);
2480         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2481         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2482         temp &= ~FDI_LINK_TRAIN_NONE;
2483         temp |= FDI_LINK_TRAIN_PATTERN_1;
2484         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2485
2486         reg = FDI_RX_CTL(pipe);
2487         temp = I915_READ(reg);
2488         temp &= ~FDI_LINK_TRAIN_NONE;
2489         temp |= FDI_LINK_TRAIN_PATTERN_1;
2490         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2491
2492         POSTING_READ(reg);
2493         udelay(150);
2494
2495         /* Ironlake workaround, enable clock pointer after FDI enable*/
2496         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2497         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2498                    FDI_RX_PHASE_SYNC_POINTER_EN);
2499
2500         reg = FDI_RX_IIR(pipe);
2501         for (tries = 0; tries < 5; tries++) {
2502                 temp = I915_READ(reg);
2503                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504
2505                 if ((temp & FDI_RX_BIT_LOCK)) {
2506                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2507                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2508                         break;
2509                 }
2510         }
2511         if (tries == 5)
2512                 DRM_ERROR("FDI train 1 fail!\n");
2513
2514         /* Train 2 */
2515         reg = FDI_TX_CTL(pipe);
2516         temp = I915_READ(reg);
2517         temp &= ~FDI_LINK_TRAIN_NONE;
2518         temp |= FDI_LINK_TRAIN_PATTERN_2;
2519         I915_WRITE(reg, temp);
2520
2521         reg = FDI_RX_CTL(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_LINK_TRAIN_NONE;
2524         temp |= FDI_LINK_TRAIN_PATTERN_2;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         reg = FDI_RX_IIR(pipe);
2531         for (tries = 0; tries < 5; tries++) {
2532                 temp = I915_READ(reg);
2533                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2534
2535                 if (temp & FDI_RX_SYMBOL_LOCK) {
2536                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2537                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2538                         break;
2539                 }
2540         }
2541         if (tries == 5)
2542                 DRM_ERROR("FDI train 2 fail!\n");
2543
2544         DRM_DEBUG_KMS("FDI train done\n");
2545
2546 }
2547
2548 static const int snb_b_fdi_train_param[] = {
2549         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2550         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2551         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2552         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2553 };
2554
2555 /* The FDI link training functions for SNB/Cougarpoint. */
2556 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2557 {
2558         struct drm_device *dev = crtc->dev;
2559         struct drm_i915_private *dev_priv = dev->dev_private;
2560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2561         int pipe = intel_crtc->pipe;
2562         u32 reg, temp, i, retry;
2563
2564         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2565            for train result */
2566         reg = FDI_RX_IMR(pipe);
2567         temp = I915_READ(reg);
2568         temp &= ~FDI_RX_SYMBOL_LOCK;
2569         temp &= ~FDI_RX_BIT_LOCK;
2570         I915_WRITE(reg, temp);
2571
2572         POSTING_READ(reg);
2573         udelay(150);
2574
2575         /* enable CPU FDI TX and PCH FDI RX */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2580         temp &= ~FDI_LINK_TRAIN_NONE;
2581         temp |= FDI_LINK_TRAIN_PATTERN_1;
2582         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583         /* SNB-B */
2584         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
2587         I915_WRITE(FDI_RX_MISC(pipe),
2588                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
2590         reg = FDI_RX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         if (HAS_PCH_CPT(dev)) {
2593                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2595         } else {
2596                 temp &= ~FDI_LINK_TRAIN_NONE;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2598         }
2599         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2600
2601         POSTING_READ(reg);
2602         udelay(150);
2603
2604         for (i = 0; i < 4; i++) {
2605                 reg = FDI_TX_CTL(pipe);
2606                 temp = I915_READ(reg);
2607                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608                 temp |= snb_b_fdi_train_param[i];
2609                 I915_WRITE(reg, temp);
2610
2611                 POSTING_READ(reg);
2612                 udelay(500);
2613
2614                 for (retry = 0; retry < 5; retry++) {
2615                         reg = FDI_RX_IIR(pipe);
2616                         temp = I915_READ(reg);
2617                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2618                         if (temp & FDI_RX_BIT_LOCK) {
2619                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2620                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2621                                 break;
2622                         }
2623                         udelay(50);
2624                 }
2625                 if (retry < 5)
2626                         break;
2627         }
2628         if (i == 4)
2629                 DRM_ERROR("FDI train 1 fail!\n");
2630
2631         /* Train 2 */
2632         reg = FDI_TX_CTL(pipe);
2633         temp = I915_READ(reg);
2634         temp &= ~FDI_LINK_TRAIN_NONE;
2635         temp |= FDI_LINK_TRAIN_PATTERN_2;
2636         if (IS_GEN6(dev)) {
2637                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638                 /* SNB-B */
2639                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         }
2641         I915_WRITE(reg, temp);
2642
2643         reg = FDI_RX_CTL(pipe);
2644         temp = I915_READ(reg);
2645         if (HAS_PCH_CPT(dev)) {
2646                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2647                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2648         } else {
2649                 temp &= ~FDI_LINK_TRAIN_NONE;
2650                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2651         }
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         for (i = 0; i < 4; i++) {
2658                 reg = FDI_TX_CTL(pipe);
2659                 temp = I915_READ(reg);
2660                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2661                 temp |= snb_b_fdi_train_param[i];
2662                 I915_WRITE(reg, temp);
2663
2664                 POSTING_READ(reg);
2665                 udelay(500);
2666
2667                 for (retry = 0; retry < 5; retry++) {
2668                         reg = FDI_RX_IIR(pipe);
2669                         temp = I915_READ(reg);
2670                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2671                         if (temp & FDI_RX_SYMBOL_LOCK) {
2672                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2673                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2674                                 break;
2675                         }
2676                         udelay(50);
2677                 }
2678                 if (retry < 5)
2679                         break;
2680         }
2681         if (i == 4)
2682                 DRM_ERROR("FDI train 2 fail!\n");
2683
2684         DRM_DEBUG_KMS("FDI train done.\n");
2685 }
2686
2687 /* Manual link training for Ivy Bridge A0 parts */
2688 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2689 {
2690         struct drm_device *dev = crtc->dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2693         int pipe = intel_crtc->pipe;
2694         u32 reg, temp, i, j;
2695
2696         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2697            for train result */
2698         reg = FDI_RX_IMR(pipe);
2699         temp = I915_READ(reg);
2700         temp &= ~FDI_RX_SYMBOL_LOCK;
2701         temp &= ~FDI_RX_BIT_LOCK;
2702         I915_WRITE(reg, temp);
2703
2704         POSTING_READ(reg);
2705         udelay(150);
2706
2707         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2708                       I915_READ(FDI_RX_IIR(pipe)));
2709
2710         /* Try each vswing and preemphasis setting twice before moving on */
2711         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2712                 /* disable first in case we need to retry */
2713                 reg = FDI_TX_CTL(pipe);
2714                 temp = I915_READ(reg);
2715                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2716                 temp &= ~FDI_TX_ENABLE;
2717                 I915_WRITE(reg, temp);
2718
2719                 reg = FDI_RX_CTL(pipe);
2720                 temp = I915_READ(reg);
2721                 temp &= ~FDI_LINK_TRAIN_AUTO;
2722                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2723                 temp &= ~FDI_RX_ENABLE;
2724                 I915_WRITE(reg, temp);
2725
2726                 /* enable CPU FDI TX and PCH FDI RX */
2727                 reg = FDI_TX_CTL(pipe);
2728                 temp = I915_READ(reg);
2729                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2730                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2731                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2732                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2733                 temp |= snb_b_fdi_train_param[j/2];
2734                 temp |= FDI_COMPOSITE_SYNC;
2735                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2736
2737                 I915_WRITE(FDI_RX_MISC(pipe),
2738                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2739
2740                 reg = FDI_RX_CTL(pipe);
2741                 temp = I915_READ(reg);
2742                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2743                 temp |= FDI_COMPOSITE_SYNC;
2744                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2745
2746                 POSTING_READ(reg);
2747                 udelay(1); /* should be 0.5us */
2748
2749                 for (i = 0; i < 4; i++) {
2750                         reg = FDI_RX_IIR(pipe);
2751                         temp = I915_READ(reg);
2752                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2753
2754                         if (temp & FDI_RX_BIT_LOCK ||
2755                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2756                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2757                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2758                                               i);
2759                                 break;
2760                         }
2761                         udelay(1); /* should be 0.5us */
2762                 }
2763                 if (i == 4) {
2764                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2765                         continue;
2766                 }
2767
2768                 /* Train 2 */
2769                 reg = FDI_TX_CTL(pipe);
2770                 temp = I915_READ(reg);
2771                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2772                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2773                 I915_WRITE(reg, temp);
2774
2775                 reg = FDI_RX_CTL(pipe);
2776                 temp = I915_READ(reg);
2777                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2778                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2779                 I915_WRITE(reg, temp);
2780
2781                 POSTING_READ(reg);
2782                 udelay(2); /* should be 1.5us */
2783
2784                 for (i = 0; i < 4; i++) {
2785                         reg = FDI_RX_IIR(pipe);
2786                         temp = I915_READ(reg);
2787                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2788
2789                         if (temp & FDI_RX_SYMBOL_LOCK ||
2790                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2791                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2792                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2793                                               i);
2794                                 goto train_done;
2795                         }
2796                         udelay(2); /* should be 1.5us */
2797                 }
2798                 if (i == 4)
2799                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2800         }
2801
2802 train_done:
2803         DRM_DEBUG_KMS("FDI train done.\n");
2804 }
2805
2806 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         int pipe = intel_crtc->pipe;
2811         u32 reg, temp;
2812
2813
2814         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2818         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2821
2822         POSTING_READ(reg);
2823         udelay(200);
2824
2825         /* Switch from Rawclk to PCDclk */
2826         temp = I915_READ(reg);
2827         I915_WRITE(reg, temp | FDI_PCDCLK);
2828
2829         POSTING_READ(reg);
2830         udelay(200);
2831
2832         /* Enable CPU FDI TX PLL, always on for Ironlake */
2833         reg = FDI_TX_CTL(pipe);
2834         temp = I915_READ(reg);
2835         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2836                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2837
2838                 POSTING_READ(reg);
2839                 udelay(100);
2840         }
2841 }
2842
2843 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2844 {
2845         struct drm_device *dev = intel_crtc->base.dev;
2846         struct drm_i915_private *dev_priv = dev->dev_private;
2847         int pipe = intel_crtc->pipe;
2848         u32 reg, temp;
2849
2850         /* Switch from PCDclk to Rawclk */
2851         reg = FDI_RX_CTL(pipe);
2852         temp = I915_READ(reg);
2853         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2854
2855         /* Disable CPU FDI TX PLL */
2856         reg = FDI_TX_CTL(pipe);
2857         temp = I915_READ(reg);
2858         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2859
2860         POSTING_READ(reg);
2861         udelay(100);
2862
2863         reg = FDI_RX_CTL(pipe);
2864         temp = I915_READ(reg);
2865         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2866
2867         /* Wait for the clocks to turn off. */
2868         POSTING_READ(reg);
2869         udelay(100);
2870 }
2871
2872 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2873 {
2874         struct drm_device *dev = crtc->dev;
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2877         int pipe = intel_crtc->pipe;
2878         u32 reg, temp;
2879
2880         /* disable CPU FDI tx and PCH FDI rx */
2881         reg = FDI_TX_CTL(pipe);
2882         temp = I915_READ(reg);
2883         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2884         POSTING_READ(reg);
2885
2886         reg = FDI_RX_CTL(pipe);
2887         temp = I915_READ(reg);
2888         temp &= ~(0x7 << 16);
2889         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2890         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2891
2892         POSTING_READ(reg);
2893         udelay(100);
2894
2895         /* Ironlake workaround, disable clock pointer after downing FDI */
2896         if (HAS_PCH_IBX(dev)) {
2897                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2898         }
2899
2900         /* still set train pattern 1 */
2901         reg = FDI_TX_CTL(pipe);
2902         temp = I915_READ(reg);
2903         temp &= ~FDI_LINK_TRAIN_NONE;
2904         temp |= FDI_LINK_TRAIN_PATTERN_1;
2905         I915_WRITE(reg, temp);
2906
2907         reg = FDI_RX_CTL(pipe);
2908         temp = I915_READ(reg);
2909         if (HAS_PCH_CPT(dev)) {
2910                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2911                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2912         } else {
2913                 temp &= ~FDI_LINK_TRAIN_NONE;
2914                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2915         }
2916         /* BPC in FDI rx is consistent with that in PIPECONF */
2917         temp &= ~(0x07 << 16);
2918         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2919         I915_WRITE(reg, temp);
2920
2921         POSTING_READ(reg);
2922         udelay(100);
2923 }
2924
2925 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2926 {
2927         struct drm_device *dev = crtc->dev;
2928         struct drm_i915_private *dev_priv = dev->dev_private;
2929         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930         unsigned long flags;
2931         bool pending;
2932
2933         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2934             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2935                 return false;
2936
2937         spin_lock_irqsave(&dev->event_lock, flags);
2938         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2939         spin_unlock_irqrestore(&dev->event_lock, flags);
2940
2941         return pending;
2942 }
2943
2944 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2945 {
2946         struct drm_device *dev = crtc->dev;
2947         struct drm_i915_private *dev_priv = dev->dev_private;
2948
2949         if (crtc->fb == NULL)
2950                 return;
2951
2952         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2953
2954         wait_event(dev_priv->pending_flip_queue,
2955                    !intel_crtc_has_pending_flip(crtc));
2956
2957         mutex_lock(&dev->struct_mutex);
2958         intel_finish_fb(crtc->fb);
2959         mutex_unlock(&dev->struct_mutex);
2960 }
2961
2962 /* Program iCLKIP clock to the desired frequency */
2963 static void lpt_program_iclkip(struct drm_crtc *crtc)
2964 {
2965         struct drm_device *dev = crtc->dev;
2966         struct drm_i915_private *dev_priv = dev->dev_private;
2967         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2968         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969         u32 temp;
2970
2971         mutex_lock(&dev_priv->dpio_lock);
2972
2973         /* It is necessary to ungate the pixclk gate prior to programming
2974          * the divisors, and gate it back when it is done.
2975          */
2976         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2977
2978         /* Disable SSCCTL */
2979         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2980                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2981                                 SBI_SSCCTL_DISABLE,
2982                         SBI_ICLK);
2983
2984         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2985         if (clock == 20000) {
2986                 auxdiv = 1;
2987                 divsel = 0x41;
2988                 phaseinc = 0x20;
2989         } else {
2990                 /* The iCLK virtual clock root frequency is in MHz,
2991                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2992                  * divisors, it is necessary to divide one by another, so we
2993                  * convert the virtual clock precision to KHz here for higher
2994                  * precision.
2995                  */
2996                 u32 iclk_virtual_root_freq = 172800 * 1000;
2997                 u32 iclk_pi_range = 64;
2998                 u32 desired_divisor, msb_divisor_value, pi_value;
2999
3000                 desired_divisor = (iclk_virtual_root_freq / clock);
3001                 msb_divisor_value = desired_divisor / iclk_pi_range;
3002                 pi_value = desired_divisor % iclk_pi_range;
3003
3004                 auxdiv = 0;
3005                 divsel = msb_divisor_value - 2;
3006                 phaseinc = pi_value;
3007         }
3008
3009         /* This should not happen with any sane values */
3010         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3011                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3012         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3013                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3014
3015         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3016                         clock,
3017                         auxdiv,
3018                         divsel,
3019                         phasedir,
3020                         phaseinc);
3021
3022         /* Program SSCDIVINTPHASE6 */
3023         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3024         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3025         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3026         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3027         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3028         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3029         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3030         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3031
3032         /* Program SSCAUXDIV */
3033         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3034         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3037
3038         /* Enable modulator and associated divider */
3039         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3040         temp &= ~SBI_SSCCTL_DISABLE;
3041         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3042
3043         /* Wait for initialization time */
3044         udelay(24);
3045
3046         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3047
3048         mutex_unlock(&dev_priv->dpio_lock);
3049 }
3050
3051 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3052                                                 enum pipe pch_transcoder)
3053 {
3054         struct drm_device *dev = crtc->base.dev;
3055         struct drm_i915_private *dev_priv = dev->dev_private;
3056         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3057
3058         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3059                    I915_READ(HTOTAL(cpu_transcoder)));
3060         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3061                    I915_READ(HBLANK(cpu_transcoder)));
3062         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3063                    I915_READ(HSYNC(cpu_transcoder)));
3064
3065         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3066                    I915_READ(VTOTAL(cpu_transcoder)));
3067         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3068                    I915_READ(VBLANK(cpu_transcoder)));
3069         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3070                    I915_READ(VSYNC(cpu_transcoder)));
3071         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3072                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3073 }
3074
3075 /*
3076  * Enable PCH resources required for PCH ports:
3077  *   - PCH PLLs
3078  *   - FDI training & RX/TX
3079  *   - update transcoder timings
3080  *   - DP transcoding bits
3081  *   - transcoder
3082  */
3083 static void ironlake_pch_enable(struct drm_crtc *crtc)
3084 {
3085         struct drm_device *dev = crtc->dev;
3086         struct drm_i915_private *dev_priv = dev->dev_private;
3087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3088         int pipe = intel_crtc->pipe;
3089         u32 reg, temp;
3090
3091         assert_pch_transcoder_disabled(dev_priv, pipe);
3092
3093         /* Write the TU size bits before fdi link training, so that error
3094          * detection works. */
3095         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3096                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3097
3098         /* For PCH output, training FDI link */
3099         dev_priv->display.fdi_link_train(crtc);
3100
3101         /* We need to program the right clock selection before writing the pixel
3102          * mutliplier into the DPLL. */
3103         if (HAS_PCH_CPT(dev)) {
3104                 u32 sel;
3105
3106                 temp = I915_READ(PCH_DPLL_SEL);
3107                 temp |= TRANS_DPLL_ENABLE(pipe);
3108                 sel = TRANS_DPLLB_SEL(pipe);
3109                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3110                         temp |= sel;
3111                 else
3112                         temp &= ~sel;
3113                 I915_WRITE(PCH_DPLL_SEL, temp);
3114         }
3115
3116         /* XXX: pch pll's can be enabled any time before we enable the PCH
3117          * transcoder, and we actually should do this to not upset any PCH
3118          * transcoder that already use the clock when we share it.
3119          *
3120          * Note that enable_shared_dpll tries to do the right thing, but
3121          * get_shared_dpll unconditionally resets the pll - we need that to have
3122          * the right LVDS enable sequence. */
3123         ironlake_enable_shared_dpll(intel_crtc);
3124
3125         /* set transcoder timing, panel must allow it */
3126         assert_panel_unlocked(dev_priv, pipe);
3127         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3128
3129         intel_fdi_normal_train(crtc);
3130
3131         /* For PCH DP, enable TRANS_DP_CTL */
3132         if (HAS_PCH_CPT(dev) &&
3133             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3134              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3135                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3136                 reg = TRANS_DP_CTL(pipe);
3137                 temp = I915_READ(reg);
3138                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3139                           TRANS_DP_SYNC_MASK |
3140                           TRANS_DP_BPC_MASK);
3141                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3142                          TRANS_DP_ENH_FRAMING);
3143                 temp |= bpc << 9; /* same format but at 11:9 */
3144
3145                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3146                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3147                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3148                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3149
3150                 switch (intel_trans_dp_port_sel(crtc)) {
3151                 case PCH_DP_B:
3152                         temp |= TRANS_DP_PORT_SEL_B;
3153                         break;
3154                 case PCH_DP_C:
3155                         temp |= TRANS_DP_PORT_SEL_C;
3156                         break;
3157                 case PCH_DP_D:
3158                         temp |= TRANS_DP_PORT_SEL_D;
3159                         break;
3160                 default:
3161                         BUG();
3162                 }
3163
3164                 I915_WRITE(reg, temp);
3165         }
3166
3167         ironlake_enable_pch_transcoder(dev_priv, pipe);
3168 }
3169
3170 static void lpt_pch_enable(struct drm_crtc *crtc)
3171 {
3172         struct drm_device *dev = crtc->dev;
3173         struct drm_i915_private *dev_priv = dev->dev_private;
3174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3175         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3176
3177         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3178
3179         lpt_program_iclkip(crtc);
3180
3181         /* Set transcoder timing. */
3182         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3183
3184         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3185 }
3186
3187 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3188 {
3189         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3190
3191         if (pll == NULL)
3192                 return;
3193
3194         if (pll->refcount == 0) {
3195                 WARN(1, "bad %s refcount\n", pll->name);
3196                 return;
3197         }
3198
3199         if (--pll->refcount == 0) {
3200                 WARN_ON(pll->on);
3201                 WARN_ON(pll->active);
3202         }
3203
3204         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3205 }
3206
3207 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3208 {
3209         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3210         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3211         enum intel_dpll_id i;
3212
3213         if (pll) {
3214                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3215                               crtc->base.base.id, pll->name);
3216                 intel_put_shared_dpll(crtc);
3217         }
3218
3219         if (HAS_PCH_IBX(dev_priv->dev)) {
3220                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3221                 i = (enum intel_dpll_id) crtc->pipe;
3222                 pll = &dev_priv->shared_dplls[i];
3223
3224                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3225                               crtc->base.base.id, pll->name);
3226
3227                 goto found;
3228         }
3229
3230         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3231                 pll = &dev_priv->shared_dplls[i];
3232
3233                 /* Only want to check enabled timings first */
3234                 if (pll->refcount == 0)
3235                         continue;
3236
3237                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3238                            sizeof(pll->hw_state)) == 0) {
3239                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3240                                       crtc->base.base.id,
3241                                       pll->name, pll->refcount, pll->active);
3242
3243                         goto found;
3244                 }
3245         }
3246
3247         /* Ok no matching timings, maybe there's a free one? */
3248         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3249                 pll = &dev_priv->shared_dplls[i];
3250                 if (pll->refcount == 0) {
3251                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3252                                       crtc->base.base.id, pll->name);
3253                         goto found;
3254                 }
3255         }
3256
3257         return NULL;
3258
3259 found:
3260         crtc->config.shared_dpll = i;
3261         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3262                          pipe_name(crtc->pipe));
3263
3264         if (pll->active == 0) {
3265                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3266                        sizeof(pll->hw_state));
3267
3268                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3269                 WARN_ON(pll->on);
3270                 assert_shared_dpll_disabled(dev_priv, pll);
3271
3272                 pll->mode_set(dev_priv, pll);
3273         }
3274         pll->refcount++;
3275
3276         return pll;
3277 }
3278
3279 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3280 {
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         int dslreg = PIPEDSL(pipe);
3283         u32 temp;
3284
3285         temp = I915_READ(dslreg);
3286         udelay(500);
3287         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3288                 if (wait_for(I915_READ(dslreg) != temp, 5))
3289                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3290         }
3291 }
3292
3293 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3294 {
3295         struct drm_device *dev = crtc->base.dev;
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297         int pipe = crtc->pipe;
3298
3299         if (crtc->config.pch_pfit.enabled) {
3300                 /* Force use of hard-coded filter coefficients
3301                  * as some pre-programmed values are broken,
3302                  * e.g. x201.
3303                  */
3304                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3305                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3306                                                  PF_PIPE_SEL_IVB(pipe));
3307                 else
3308                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3309                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3310                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3311         }
3312 }
3313
3314 static void intel_enable_planes(struct drm_crtc *crtc)
3315 {
3316         struct drm_device *dev = crtc->dev;
3317         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3318         struct intel_plane *intel_plane;
3319
3320         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3321                 if (intel_plane->pipe == pipe)
3322                         intel_plane_restore(&intel_plane->base);
3323 }
3324
3325 static void intel_disable_planes(struct drm_crtc *crtc)
3326 {
3327         struct drm_device *dev = crtc->dev;
3328         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3329         struct intel_plane *intel_plane;
3330
3331         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3332                 if (intel_plane->pipe == pipe)
3333                         intel_plane_disable(&intel_plane->base);
3334 }
3335
3336 void hsw_enable_ips(struct intel_crtc *crtc)
3337 {
3338         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3339
3340         if (!crtc->config.ips_enabled)
3341                 return;
3342
3343         /* We can only enable IPS after we enable a plane and wait for a vblank.
3344          * We guarantee that the plane is enabled by calling intel_enable_ips
3345          * only after intel_enable_plane. And intel_enable_plane already waits
3346          * for a vblank, so all we need to do here is to enable the IPS bit. */
3347         assert_plane_enabled(dev_priv, crtc->plane);
3348         I915_WRITE(IPS_CTL, IPS_ENABLE);
3349 }
3350
3351 void hsw_disable_ips(struct intel_crtc *crtc)
3352 {
3353         struct drm_device *dev = crtc->base.dev;
3354         struct drm_i915_private *dev_priv = dev->dev_private;
3355
3356         if (!crtc->config.ips_enabled)
3357                 return;
3358
3359         assert_plane_enabled(dev_priv, crtc->plane);
3360         I915_WRITE(IPS_CTL, 0);
3361         POSTING_READ(IPS_CTL);
3362
3363         /* We need to wait for a vblank before we can disable the plane. */
3364         intel_wait_for_vblank(dev, crtc->pipe);
3365 }
3366
3367 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3368 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3369 {
3370         struct drm_device *dev = crtc->dev;
3371         struct drm_i915_private *dev_priv = dev->dev_private;
3372         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3373         enum pipe pipe = intel_crtc->pipe;
3374         int palreg = PALETTE(pipe);
3375         int i;
3376         bool reenable_ips = false;
3377
3378         /* The clocks have to be on to load the palette. */
3379         if (!crtc->enabled || !intel_crtc->active)
3380                 return;
3381
3382         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3383                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3384                         assert_dsi_pll_enabled(dev_priv);
3385                 else
3386                         assert_pll_enabled(dev_priv, pipe);
3387         }
3388
3389         /* use legacy palette for Ironlake */
3390         if (HAS_PCH_SPLIT(dev))
3391                 palreg = LGC_PALETTE(pipe);
3392
3393         /* Workaround : Do not read or write the pipe palette/gamma data while
3394          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3395          */
3396         if (intel_crtc->config.ips_enabled &&
3397             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3398              GAMMA_MODE_MODE_SPLIT)) {
3399                 hsw_disable_ips(intel_crtc);
3400                 reenable_ips = true;
3401         }
3402
3403         for (i = 0; i < 256; i++) {
3404                 I915_WRITE(palreg + 4 * i,
3405                            (intel_crtc->lut_r[i] << 16) |
3406                            (intel_crtc->lut_g[i] << 8) |
3407                            intel_crtc->lut_b[i]);
3408         }
3409
3410         if (reenable_ips)
3411                 hsw_enable_ips(intel_crtc);
3412 }
3413
3414 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3415 {
3416         struct drm_device *dev = crtc->dev;
3417         struct drm_i915_private *dev_priv = dev->dev_private;
3418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3419         struct intel_encoder *encoder;
3420         int pipe = intel_crtc->pipe;
3421         int plane = intel_crtc->plane;
3422
3423         WARN_ON(!crtc->enabled);
3424
3425         if (intel_crtc->active)
3426                 return;
3427
3428         intel_crtc->active = true;
3429
3430         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3431         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3432
3433         for_each_encoder_on_crtc(dev, crtc, encoder)
3434                 if (encoder->pre_enable)
3435                         encoder->pre_enable(encoder);
3436
3437         if (intel_crtc->config.has_pch_encoder) {
3438                 /* Note: FDI PLL enabling _must_ be done before we enable the
3439                  * cpu pipes, hence this is separate from all the other fdi/pch
3440                  * enabling. */
3441                 ironlake_fdi_pll_enable(intel_crtc);
3442         } else {
3443                 assert_fdi_tx_disabled(dev_priv, pipe);
3444                 assert_fdi_rx_disabled(dev_priv, pipe);
3445         }
3446
3447         ironlake_pfit_enable(intel_crtc);
3448
3449         /*
3450          * On ILK+ LUT must be loaded before the pipe is running but with
3451          * clocks enabled
3452          */
3453         intel_crtc_load_lut(crtc);
3454
3455         intel_update_watermarks(crtc);
3456         intel_enable_pipe(dev_priv, pipe,
3457                           intel_crtc->config.has_pch_encoder, false);
3458         intel_enable_primary_plane(dev_priv, plane, pipe);
3459         intel_enable_planes(crtc);
3460         intel_crtc_update_cursor(crtc, true);
3461
3462         if (intel_crtc->config.has_pch_encoder)
3463                 ironlake_pch_enable(crtc);
3464
3465         mutex_lock(&dev->struct_mutex);
3466         intel_update_fbc(dev);
3467         mutex_unlock(&dev->struct_mutex);
3468
3469         for_each_encoder_on_crtc(dev, crtc, encoder)
3470                 encoder->enable(encoder);
3471
3472         if (HAS_PCH_CPT(dev))
3473                 cpt_verify_modeset(dev, intel_crtc->pipe);
3474
3475         /*
3476          * There seems to be a race in PCH platform hw (at least on some
3477          * outputs) where an enabled pipe still completes any pageflip right
3478          * away (as if the pipe is off) instead of waiting for vblank. As soon
3479          * as the first vblank happend, everything works as expected. Hence just
3480          * wait for one vblank before returning to avoid strange things
3481          * happening.
3482          */
3483         intel_wait_for_vblank(dev, intel_crtc->pipe);
3484 }
3485
3486 /* IPS only exists on ULT machines and is tied to pipe A. */
3487 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3488 {
3489         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3490 }
3491
3492 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3493 {
3494         struct drm_device *dev = crtc->dev;
3495         struct drm_i915_private *dev_priv = dev->dev_private;
3496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497         int pipe = intel_crtc->pipe;
3498         int plane = intel_crtc->plane;
3499
3500         intel_enable_primary_plane(dev_priv, plane, pipe);
3501         intel_enable_planes(crtc);
3502         intel_crtc_update_cursor(crtc, true);
3503
3504         hsw_enable_ips(intel_crtc);
3505
3506         mutex_lock(&dev->struct_mutex);
3507         intel_update_fbc(dev);
3508         mutex_unlock(&dev->struct_mutex);
3509 }
3510
3511 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3512 {
3513         struct drm_device *dev = crtc->dev;
3514         struct drm_i915_private *dev_priv = dev->dev_private;
3515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3516         int pipe = intel_crtc->pipe;
3517         int plane = intel_crtc->plane;
3518
3519         intel_crtc_wait_for_pending_flips(crtc);
3520         drm_vblank_off(dev, pipe);
3521
3522         /* FBC must be disabled before disabling the plane on HSW. */
3523         if (dev_priv->fbc.plane == plane)
3524                 intel_disable_fbc(dev);
3525
3526         hsw_disable_ips(intel_crtc);
3527
3528         intel_crtc_update_cursor(crtc, false);
3529         intel_disable_planes(crtc);
3530         intel_disable_primary_plane(dev_priv, plane, pipe);
3531 }
3532
3533 /*
3534  * This implements the workaround described in the "notes" section of the mode
3535  * set sequence documentation. When going from no pipes or single pipe to
3536  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3537  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3538  */
3539 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3540 {
3541         struct drm_device *dev = crtc->base.dev;
3542         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3543
3544         /* We want to get the other_active_crtc only if there's only 1 other
3545          * active crtc. */
3546         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3547                 if (!crtc_it->active || crtc_it == crtc)
3548                         continue;
3549
3550                 if (other_active_crtc)
3551                         return;
3552
3553                 other_active_crtc = crtc_it;
3554         }
3555         if (!other_active_crtc)
3556                 return;
3557
3558         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3559         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3560 }
3561
3562 static void haswell_crtc_enable(struct drm_crtc *crtc)
3563 {
3564         struct drm_device *dev = crtc->dev;
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567         struct intel_encoder *encoder;
3568         int pipe = intel_crtc->pipe;
3569
3570         WARN_ON(!crtc->enabled);
3571
3572         if (intel_crtc->active)
3573                 return;
3574
3575         intel_crtc->active = true;
3576
3577         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3578         if (intel_crtc->config.has_pch_encoder)
3579                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3580
3581         if (intel_crtc->config.has_pch_encoder)
3582                 dev_priv->display.fdi_link_train(crtc);
3583
3584         for_each_encoder_on_crtc(dev, crtc, encoder)
3585                 if (encoder->pre_enable)
3586                         encoder->pre_enable(encoder);
3587
3588         intel_ddi_enable_pipe_clock(intel_crtc);
3589
3590         ironlake_pfit_enable(intel_crtc);
3591
3592         /*
3593          * On ILK+ LUT must be loaded before the pipe is running but with
3594          * clocks enabled
3595          */
3596         intel_crtc_load_lut(crtc);
3597
3598         intel_ddi_set_pipe_settings(crtc);
3599         intel_ddi_enable_transcoder_func(crtc);
3600
3601         intel_update_watermarks(crtc);
3602         intel_enable_pipe(dev_priv, pipe,
3603                           intel_crtc->config.has_pch_encoder, false);
3604
3605         if (intel_crtc->config.has_pch_encoder)
3606                 lpt_pch_enable(crtc);
3607
3608         for_each_encoder_on_crtc(dev, crtc, encoder) {
3609                 encoder->enable(encoder);
3610                 intel_opregion_notify_encoder(encoder, true);
3611         }
3612
3613         /* If we change the relative order between pipe/planes enabling, we need
3614          * to change the workaround. */
3615         haswell_mode_set_planes_workaround(intel_crtc);
3616         haswell_crtc_enable_planes(crtc);
3617
3618         /*
3619          * There seems to be a race in PCH platform hw (at least on some
3620          * outputs) where an enabled pipe still completes any pageflip right
3621          * away (as if the pipe is off) instead of waiting for vblank. As soon
3622          * as the first vblank happend, everything works as expected. Hence just
3623          * wait for one vblank before returning to avoid strange things
3624          * happening.
3625          */
3626         intel_wait_for_vblank(dev, intel_crtc->pipe);
3627 }
3628
3629 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3630 {
3631         struct drm_device *dev = crtc->base.dev;
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         int pipe = crtc->pipe;
3634
3635         /* To avoid upsetting the power well on haswell only disable the pfit if
3636          * it's in use. The hw state code will make sure we get this right. */
3637         if (crtc->config.pch_pfit.enabled) {
3638                 I915_WRITE(PF_CTL(pipe), 0);
3639                 I915_WRITE(PF_WIN_POS(pipe), 0);
3640                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3641         }
3642 }
3643
3644 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3645 {
3646         struct drm_device *dev = crtc->dev;
3647         struct drm_i915_private *dev_priv = dev->dev_private;
3648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649         struct intel_encoder *encoder;
3650         int pipe = intel_crtc->pipe;
3651         int plane = intel_crtc->plane;
3652         u32 reg, temp;
3653
3654
3655         if (!intel_crtc->active)
3656                 return;
3657
3658         for_each_encoder_on_crtc(dev, crtc, encoder)
3659                 encoder->disable(encoder);
3660
3661         intel_crtc_wait_for_pending_flips(crtc);
3662         drm_vblank_off(dev, pipe);
3663
3664         if (dev_priv->fbc.plane == plane)
3665                 intel_disable_fbc(dev);
3666
3667         intel_crtc_update_cursor(crtc, false);
3668         intel_disable_planes(crtc);
3669         intel_disable_primary_plane(dev_priv, plane, pipe);
3670
3671         if (intel_crtc->config.has_pch_encoder)
3672                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3673
3674         intel_disable_pipe(dev_priv, pipe);
3675
3676         ironlake_pfit_disable(intel_crtc);
3677
3678         for_each_encoder_on_crtc(dev, crtc, encoder)
3679                 if (encoder->post_disable)
3680                         encoder->post_disable(encoder);
3681
3682         if (intel_crtc->config.has_pch_encoder) {
3683                 ironlake_fdi_disable(crtc);
3684
3685                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3686                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3687
3688                 if (HAS_PCH_CPT(dev)) {
3689                         /* disable TRANS_DP_CTL */
3690                         reg = TRANS_DP_CTL(pipe);
3691                         temp = I915_READ(reg);
3692                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3693                                   TRANS_DP_PORT_SEL_MASK);
3694                         temp |= TRANS_DP_PORT_SEL_NONE;
3695                         I915_WRITE(reg, temp);
3696
3697                         /* disable DPLL_SEL */
3698                         temp = I915_READ(PCH_DPLL_SEL);
3699                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3700                         I915_WRITE(PCH_DPLL_SEL, temp);
3701                 }
3702
3703                 /* disable PCH DPLL */
3704                 intel_disable_shared_dpll(intel_crtc);
3705
3706                 ironlake_fdi_pll_disable(intel_crtc);
3707         }
3708
3709         intel_crtc->active = false;
3710         intel_update_watermarks(crtc);
3711
3712         mutex_lock(&dev->struct_mutex);
3713         intel_update_fbc(dev);
3714         mutex_unlock(&dev->struct_mutex);
3715 }
3716
3717 static void haswell_crtc_disable(struct drm_crtc *crtc)
3718 {
3719         struct drm_device *dev = crtc->dev;
3720         struct drm_i915_private *dev_priv = dev->dev_private;
3721         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3722         struct intel_encoder *encoder;
3723         int pipe = intel_crtc->pipe;
3724         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3725
3726         if (!intel_crtc->active)
3727                 return;
3728
3729         haswell_crtc_disable_planes(crtc);
3730
3731         for_each_encoder_on_crtc(dev, crtc, encoder) {
3732                 intel_opregion_notify_encoder(encoder, false);
3733                 encoder->disable(encoder);
3734         }
3735
3736         if (intel_crtc->config.has_pch_encoder)
3737                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3738         intel_disable_pipe(dev_priv, pipe);
3739
3740         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3741
3742         ironlake_pfit_disable(intel_crtc);
3743
3744         intel_ddi_disable_pipe_clock(intel_crtc);
3745
3746         for_each_encoder_on_crtc(dev, crtc, encoder)
3747                 if (encoder->post_disable)
3748                         encoder->post_disable(encoder);
3749
3750         if (intel_crtc->config.has_pch_encoder) {
3751                 lpt_disable_pch_transcoder(dev_priv);
3752                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3753                 intel_ddi_fdi_disable(crtc);
3754         }
3755
3756         intel_crtc->active = false;
3757         intel_update_watermarks(crtc);
3758
3759         mutex_lock(&dev->struct_mutex);
3760         intel_update_fbc(dev);
3761         mutex_unlock(&dev->struct_mutex);
3762 }
3763
3764 static void ironlake_crtc_off(struct drm_crtc *crtc)
3765 {
3766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767         intel_put_shared_dpll(intel_crtc);
3768 }
3769
3770 static void haswell_crtc_off(struct drm_crtc *crtc)
3771 {
3772         intel_ddi_put_crtc_pll(crtc);
3773 }
3774
3775 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3776 {
3777         if (!enable && intel_crtc->overlay) {
3778                 struct drm_device *dev = intel_crtc->base.dev;
3779                 struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781                 mutex_lock(&dev->struct_mutex);
3782                 dev_priv->mm.interruptible = false;
3783                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3784                 dev_priv->mm.interruptible = true;
3785                 mutex_unlock(&dev->struct_mutex);
3786         }
3787
3788         /* Let userspace switch the overlay on again. In most cases userspace
3789          * has to recompute where to put it anyway.
3790          */
3791 }
3792
3793 /**
3794  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3795  * cursor plane briefly if not already running after enabling the display
3796  * plane.
3797  * This workaround avoids occasional blank screens when self refresh is
3798  * enabled.
3799  */
3800 static void
3801 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3802 {
3803         u32 cntl = I915_READ(CURCNTR(pipe));
3804
3805         if ((cntl & CURSOR_MODE) == 0) {
3806                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3807
3808                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3809                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3810                 intel_wait_for_vblank(dev_priv->dev, pipe);
3811                 I915_WRITE(CURCNTR(pipe), cntl);
3812                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3813                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3814         }
3815 }
3816
3817 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3818 {
3819         struct drm_device *dev = crtc->base.dev;
3820         struct drm_i915_private *dev_priv = dev->dev_private;
3821         struct intel_crtc_config *pipe_config = &crtc->config;
3822
3823         if (!crtc->config.gmch_pfit.control)
3824                 return;
3825
3826         /*
3827          * The panel fitter should only be adjusted whilst the pipe is disabled,
3828          * according to register description and PRM.
3829          */
3830         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3831         assert_pipe_disabled(dev_priv, crtc->pipe);
3832
3833         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3834         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3835
3836         /* Border color in case we don't scale up to the full screen. Black by
3837          * default, change to something else for debugging. */
3838         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3839 }
3840
3841 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_i915_private *dev_priv = dev->dev_private;
3845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846         struct intel_encoder *encoder;
3847         int pipe = intel_crtc->pipe;
3848         int plane = intel_crtc->plane;
3849         bool is_dsi;
3850
3851         WARN_ON(!crtc->enabled);
3852
3853         if (intel_crtc->active)
3854                 return;
3855
3856         intel_crtc->active = true;
3857
3858         for_each_encoder_on_crtc(dev, crtc, encoder)
3859                 if (encoder->pre_pll_enable)
3860                         encoder->pre_pll_enable(encoder);
3861
3862         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3863
3864         if (!is_dsi)
3865                 vlv_enable_pll(intel_crtc);
3866
3867         for_each_encoder_on_crtc(dev, crtc, encoder)
3868                 if (encoder->pre_enable)
3869                         encoder->pre_enable(encoder);
3870
3871         i9xx_pfit_enable(intel_crtc);
3872
3873         intel_crtc_load_lut(crtc);
3874
3875         intel_update_watermarks(crtc);
3876         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3877         intel_enable_primary_plane(dev_priv, plane, pipe);
3878         intel_enable_planes(crtc);
3879         intel_crtc_update_cursor(crtc, true);
3880
3881         intel_update_fbc(dev);
3882
3883         for_each_encoder_on_crtc(dev, crtc, encoder)
3884                 encoder->enable(encoder);
3885 }
3886
3887 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3888 {
3889         struct drm_device *dev = crtc->dev;
3890         struct drm_i915_private *dev_priv = dev->dev_private;
3891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3892         struct intel_encoder *encoder;
3893         int pipe = intel_crtc->pipe;
3894         int plane = intel_crtc->plane;
3895
3896         WARN_ON(!crtc->enabled);
3897
3898         if (intel_crtc->active)
3899                 return;
3900
3901         intel_crtc->active = true;
3902
3903         for_each_encoder_on_crtc(dev, crtc, encoder)
3904                 if (encoder->pre_enable)
3905                         encoder->pre_enable(encoder);
3906
3907         i9xx_enable_pll(intel_crtc);
3908
3909         i9xx_pfit_enable(intel_crtc);
3910
3911         intel_crtc_load_lut(crtc);
3912
3913         intel_update_watermarks(crtc);
3914         intel_enable_pipe(dev_priv, pipe, false, false);
3915         intel_enable_primary_plane(dev_priv, plane, pipe);
3916         intel_enable_planes(crtc);
3917         /* The fixup needs to happen before cursor is enabled */
3918         if (IS_G4X(dev))
3919                 g4x_fixup_plane(dev_priv, pipe);
3920         intel_crtc_update_cursor(crtc, true);
3921
3922         /* Give the overlay scaler a chance to enable if it's on this pipe */
3923         intel_crtc_dpms_overlay(intel_crtc, true);
3924
3925         intel_update_fbc(dev);
3926
3927         for_each_encoder_on_crtc(dev, crtc, encoder)
3928                 encoder->enable(encoder);
3929 }
3930
3931 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3932 {
3933         struct drm_device *dev = crtc->base.dev;
3934         struct drm_i915_private *dev_priv = dev->dev_private;
3935
3936         if (!crtc->config.gmch_pfit.control)
3937                 return;
3938
3939         assert_pipe_disabled(dev_priv, crtc->pipe);
3940
3941         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3942                          I915_READ(PFIT_CONTROL));
3943         I915_WRITE(PFIT_CONTROL, 0);
3944 }
3945
3946 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3947 {
3948         struct drm_device *dev = crtc->dev;
3949         struct drm_i915_private *dev_priv = dev->dev_private;
3950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3951         struct intel_encoder *encoder;
3952         int pipe = intel_crtc->pipe;
3953         int plane = intel_crtc->plane;
3954
3955         if (!intel_crtc->active)
3956                 return;
3957
3958         for_each_encoder_on_crtc(dev, crtc, encoder)
3959                 encoder->disable(encoder);
3960
3961         /* Give the overlay scaler a chance to disable if it's on this pipe */
3962         intel_crtc_wait_for_pending_flips(crtc);
3963         drm_vblank_off(dev, pipe);
3964
3965         if (dev_priv->fbc.plane == plane)
3966                 intel_disable_fbc(dev);
3967
3968         intel_crtc_dpms_overlay(intel_crtc, false);
3969         intel_crtc_update_cursor(crtc, false);
3970         intel_disable_planes(crtc);
3971         intel_disable_primary_plane(dev_priv, plane, pipe);
3972
3973         intel_disable_pipe(dev_priv, pipe);
3974
3975         i9xx_pfit_disable(intel_crtc);
3976
3977         for_each_encoder_on_crtc(dev, crtc, encoder)
3978                 if (encoder->post_disable)
3979                         encoder->post_disable(encoder);
3980
3981         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3982                 vlv_disable_pll(dev_priv, pipe);
3983         else if (!IS_VALLEYVIEW(dev))
3984                 i9xx_disable_pll(dev_priv, pipe);
3985
3986         intel_crtc->active = false;
3987         intel_update_watermarks(crtc);
3988
3989         intel_update_fbc(dev);
3990 }
3991
3992 static void i9xx_crtc_off(struct drm_crtc *crtc)
3993 {
3994 }
3995
3996 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3997                                     bool enabled)
3998 {
3999         struct drm_device *dev = crtc->dev;
4000         struct drm_i915_master_private *master_priv;
4001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4002         int pipe = intel_crtc->pipe;
4003
4004         if (!dev->primary->master)
4005                 return;
4006
4007         master_priv = dev->primary->master->driver_priv;
4008         if (!master_priv->sarea_priv)
4009                 return;
4010
4011         switch (pipe) {
4012         case 0:
4013                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4014                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4015                 break;
4016         case 1:
4017                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4018                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4019                 break;
4020         default:
4021                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4022                 break;
4023         }
4024 }
4025
4026 /**
4027  * Sets the power management mode of the pipe and plane.
4028  */
4029 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4030 {
4031         struct drm_device *dev = crtc->dev;
4032         struct drm_i915_private *dev_priv = dev->dev_private;
4033         struct intel_encoder *intel_encoder;
4034         bool enable = false;
4035
4036         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4037                 enable |= intel_encoder->connectors_active;
4038
4039         if (enable)
4040                 dev_priv->display.crtc_enable(crtc);
4041         else
4042                 dev_priv->display.crtc_disable(crtc);
4043
4044         intel_crtc_update_sarea(crtc, enable);
4045 }
4046
4047 static void intel_crtc_disable(struct drm_crtc *crtc)
4048 {
4049         struct drm_device *dev = crtc->dev;
4050         struct drm_connector *connector;
4051         struct drm_i915_private *dev_priv = dev->dev_private;
4052         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4053
4054         /* crtc should still be enabled when we disable it. */
4055         WARN_ON(!crtc->enabled);
4056
4057         dev_priv->display.crtc_disable(crtc);
4058         intel_crtc->eld_vld = false;
4059         intel_crtc_update_sarea(crtc, false);
4060         dev_priv->display.off(crtc);
4061
4062         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4063         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4064         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4065
4066         if (crtc->fb) {
4067                 mutex_lock(&dev->struct_mutex);
4068                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4069                 mutex_unlock(&dev->struct_mutex);
4070                 crtc->fb = NULL;
4071         }
4072
4073         /* Update computed state. */
4074         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4075                 if (!connector->encoder || !connector->encoder->crtc)
4076                         continue;
4077
4078                 if (connector->encoder->crtc != crtc)
4079                         continue;
4080
4081                 connector->dpms = DRM_MODE_DPMS_OFF;
4082                 to_intel_encoder(connector->encoder)->connectors_active = false;
4083         }
4084 }
4085
4086 void intel_encoder_destroy(struct drm_encoder *encoder)
4087 {
4088         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4089
4090         drm_encoder_cleanup(encoder);
4091         kfree(intel_encoder);
4092 }
4093
4094 /* Simple dpms helper for encoders with just one connector, no cloning and only
4095  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4096  * state of the entire output pipe. */
4097 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4098 {
4099         if (mode == DRM_MODE_DPMS_ON) {
4100                 encoder->connectors_active = true;
4101
4102                 intel_crtc_update_dpms(encoder->base.crtc);
4103         } else {
4104                 encoder->connectors_active = false;
4105
4106                 intel_crtc_update_dpms(encoder->base.crtc);
4107         }
4108 }
4109
4110 /* Cross check the actual hw state with our own modeset state tracking (and it's
4111  * internal consistency). */
4112 static void intel_connector_check_state(struct intel_connector *connector)
4113 {
4114         if (connector->get_hw_state(connector)) {
4115                 struct intel_encoder *encoder = connector->encoder;
4116                 struct drm_crtc *crtc;
4117                 bool encoder_enabled;
4118                 enum pipe pipe;
4119
4120                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4121                               connector->base.base.id,
4122                               drm_get_connector_name(&connector->base));
4123
4124                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4125                      "wrong connector dpms state\n");
4126                 WARN(connector->base.encoder != &encoder->base,
4127                      "active connector not linked to encoder\n");
4128                 WARN(!encoder->connectors_active,
4129                      "encoder->connectors_active not set\n");
4130
4131                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4132                 WARN(!encoder_enabled, "encoder not enabled\n");
4133                 if (WARN_ON(!encoder->base.crtc))
4134                         return;
4135
4136                 crtc = encoder->base.crtc;
4137
4138                 WARN(!crtc->enabled, "crtc not enabled\n");
4139                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4140                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4141                      "encoder active on the wrong pipe\n");
4142         }
4143 }
4144
4145 /* Even simpler default implementation, if there's really no special case to
4146  * consider. */
4147 void intel_connector_dpms(struct drm_connector *connector, int mode)
4148 {
4149         struct intel_encoder *encoder = intel_attached_encoder(connector);
4150
4151         /* All the simple cases only support two dpms states. */
4152         if (mode != DRM_MODE_DPMS_ON)
4153                 mode = DRM_MODE_DPMS_OFF;
4154
4155         if (mode == connector->dpms)
4156                 return;
4157
4158         connector->dpms = mode;
4159
4160         /* Only need to change hw state when actually enabled */
4161         if (encoder->base.crtc)
4162                 intel_encoder_dpms(encoder, mode);
4163         else
4164                 WARN_ON(encoder->connectors_active != false);
4165
4166         intel_modeset_check_state(connector->dev);
4167 }
4168
4169 /* Simple connector->get_hw_state implementation for encoders that support only
4170  * one connector and no cloning and hence the encoder state determines the state
4171  * of the connector. */
4172 bool intel_connector_get_hw_state(struct intel_connector *connector)
4173 {
4174         enum pipe pipe = 0;
4175         struct intel_encoder *encoder = connector->encoder;
4176
4177         return encoder->get_hw_state(encoder, &pipe);
4178 }
4179
4180 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4181                                      struct intel_crtc_config *pipe_config)
4182 {
4183         struct drm_i915_private *dev_priv = dev->dev_private;
4184         struct intel_crtc *pipe_B_crtc =
4185                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4186
4187         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4188                       pipe_name(pipe), pipe_config->fdi_lanes);
4189         if (pipe_config->fdi_lanes > 4) {
4190                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4191                               pipe_name(pipe), pipe_config->fdi_lanes);
4192                 return false;
4193         }
4194
4195         if (IS_HASWELL(dev)) {
4196                 if (pipe_config->fdi_lanes > 2) {
4197                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4198                                       pipe_config->fdi_lanes);
4199                         return false;
4200                 } else {
4201                         return true;
4202                 }
4203         }
4204
4205         if (INTEL_INFO(dev)->num_pipes == 2)
4206                 return true;
4207
4208         /* Ivybridge 3 pipe is really complicated */
4209         switch (pipe) {
4210         case PIPE_A:
4211                 return true;
4212         case PIPE_B:
4213                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4214                     pipe_config->fdi_lanes > 2) {
4215                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4216                                       pipe_name(pipe), pipe_config->fdi_lanes);
4217                         return false;
4218                 }
4219                 return true;
4220         case PIPE_C:
4221                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4222                     pipe_B_crtc->config.fdi_lanes <= 2) {
4223                         if (pipe_config->fdi_lanes > 2) {
4224                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4225                                               pipe_name(pipe), pipe_config->fdi_lanes);
4226                                 return false;
4227                         }
4228                 } else {
4229                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4230                         return false;
4231                 }
4232                 return true;
4233         default:
4234                 BUG();
4235         }
4236 }
4237
4238 #define RETRY 1
4239 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4240                                        struct intel_crtc_config *pipe_config)
4241 {
4242         struct drm_device *dev = intel_crtc->base.dev;
4243         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4244         int lane, link_bw, fdi_dotclock;
4245         bool setup_ok, needs_recompute = false;
4246
4247 retry:
4248         /* FDI is a binary signal running at ~2.7GHz, encoding
4249          * each output octet as 10 bits. The actual frequency
4250          * is stored as a divider into a 100MHz clock, and the
4251          * mode pixel clock is stored in units of 1KHz.
4252          * Hence the bw of each lane in terms of the mode signal
4253          * is:
4254          */
4255         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4256
4257         fdi_dotclock = adjusted_mode->crtc_clock;
4258
4259         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4260                                            pipe_config->pipe_bpp);
4261
4262         pipe_config->fdi_lanes = lane;
4263
4264         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4265                                link_bw, &pipe_config->fdi_m_n);
4266
4267         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4268                                             intel_crtc->pipe, pipe_config);
4269         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4270                 pipe_config->pipe_bpp -= 2*3;
4271                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4272                               pipe_config->pipe_bpp);
4273                 needs_recompute = true;
4274                 pipe_config->bw_constrained = true;
4275
4276                 goto retry;
4277         }
4278
4279         if (needs_recompute)
4280                 return RETRY;
4281
4282         return setup_ok ? 0 : -EINVAL;
4283 }
4284
4285 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4286                                    struct intel_crtc_config *pipe_config)
4287 {
4288         pipe_config->ips_enabled = i915_enable_ips &&
4289                                    hsw_crtc_supports_ips(crtc) &&
4290                                    pipe_config->pipe_bpp <= 24;
4291 }
4292
4293 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4294                                      struct intel_crtc_config *pipe_config)
4295 {
4296         struct drm_device *dev = crtc->base.dev;
4297         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4298
4299         /* FIXME should check pixel clock limits on all platforms */
4300         if (INTEL_INFO(dev)->gen < 4) {
4301                 struct drm_i915_private *dev_priv = dev->dev_private;
4302                 int clock_limit =
4303                         dev_priv->display.get_display_clock_speed(dev);
4304
4305                 /*
4306                  * Enable pixel doubling when the dot clock
4307                  * is > 90% of the (display) core speed.
4308                  *
4309                  * GDG double wide on either pipe,
4310                  * otherwise pipe A only.
4311                  */
4312                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4313                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4314                         clock_limit *= 2;
4315                         pipe_config->double_wide = true;
4316                 }
4317
4318                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4319                         return -EINVAL;
4320         }
4321
4322         /*
4323          * Pipe horizontal size must be even in:
4324          * - DVO ganged mode
4325          * - LVDS dual channel mode
4326          * - Double wide pipe
4327          */
4328         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4329              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4330                 pipe_config->pipe_src_w &= ~1;
4331
4332         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4333          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4334          */
4335         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4336                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4337                 return -EINVAL;
4338
4339         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4340                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4341         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4342                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4343                  * for lvds. */
4344                 pipe_config->pipe_bpp = 8*3;
4345         }
4346
4347         if (HAS_IPS(dev))
4348                 hsw_compute_ips_config(crtc, pipe_config);
4349
4350         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4351          * clock survives for now. */
4352         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4353                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4354
4355         if (pipe_config->has_pch_encoder)
4356                 return ironlake_fdi_compute_config(crtc, pipe_config);
4357
4358         return 0;
4359 }
4360
4361 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4362 {
4363         return 400000; /* FIXME */
4364 }
4365
4366 static int i945_get_display_clock_speed(struct drm_device *dev)
4367 {
4368         return 400000;
4369 }
4370
4371 static int i915_get_display_clock_speed(struct drm_device *dev)
4372 {
4373         return 333000;
4374 }
4375
4376 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4377 {
4378         return 200000;
4379 }
4380
4381 static int pnv_get_display_clock_speed(struct drm_device *dev)
4382 {
4383         u16 gcfgc = 0;
4384
4385         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4386
4387         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4388         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4389                 return 267000;
4390         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4391                 return 333000;
4392         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4393                 return 444000;
4394         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4395                 return 200000;
4396         default:
4397                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4398         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4399                 return 133000;
4400         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4401                 return 167000;
4402         }
4403 }
4404
4405 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4406 {
4407         u16 gcfgc = 0;
4408
4409         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4410
4411         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4412                 return 133000;
4413         else {
4414                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4415                 case GC_DISPLAY_CLOCK_333_MHZ:
4416                         return 333000;
4417                 default:
4418                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4419                         return 190000;
4420                 }
4421         }
4422 }
4423
4424 static int i865_get_display_clock_speed(struct drm_device *dev)
4425 {
4426         return 266000;
4427 }
4428
4429 static int i855_get_display_clock_speed(struct drm_device *dev)
4430 {
4431         u16 hpllcc = 0;
4432         /* Assume that the hardware is in the high speed state.  This
4433          * should be the default.
4434          */
4435         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4436         case GC_CLOCK_133_200:
4437         case GC_CLOCK_100_200:
4438                 return 200000;
4439         case GC_CLOCK_166_250:
4440                 return 250000;
4441         case GC_CLOCK_100_133:
4442                 return 133000;
4443         }
4444
4445         /* Shouldn't happen */
4446         return 0;
4447 }
4448
4449 static int i830_get_display_clock_speed(struct drm_device *dev)
4450 {
4451         return 133000;
4452 }
4453
4454 static void
4455 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4456 {
4457         while (*num > DATA_LINK_M_N_MASK ||
4458                *den > DATA_LINK_M_N_MASK) {
4459                 *num >>= 1;
4460                 *den >>= 1;
4461         }
4462 }
4463
4464 static void compute_m_n(unsigned int m, unsigned int n,
4465                         uint32_t *ret_m, uint32_t *ret_n)
4466 {
4467         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4468         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4469         intel_reduce_m_n_ratio(ret_m, ret_n);
4470 }
4471
4472 void
4473 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4474                        int pixel_clock, int link_clock,
4475                        struct intel_link_m_n *m_n)
4476 {
4477         m_n->tu = 64;
4478
4479         compute_m_n(bits_per_pixel * pixel_clock,
4480                     link_clock * nlanes * 8,
4481                     &m_n->gmch_m, &m_n->gmch_n);
4482
4483         compute_m_n(pixel_clock, link_clock,
4484                     &m_n->link_m, &m_n->link_n);
4485 }
4486
4487 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4488 {
4489         if (i915_panel_use_ssc >= 0)
4490                 return i915_panel_use_ssc != 0;
4491         return dev_priv->vbt.lvds_use_ssc
4492                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4493 }
4494
4495 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4496 {
4497         struct drm_device *dev = crtc->dev;
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         int refclk;
4500
4501         if (IS_VALLEYVIEW(dev)) {
4502                 refclk = 100000;
4503         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4504             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4505                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4506                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4507                               refclk / 1000);
4508         } else if (!IS_GEN2(dev)) {
4509                 refclk = 96000;
4510         } else {
4511                 refclk = 48000;
4512         }
4513
4514         return refclk;
4515 }
4516
4517 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4518 {
4519         return (1 << dpll->n) << 16 | dpll->m2;
4520 }
4521
4522 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4523 {
4524         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4525 }
4526
4527 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4528                                      intel_clock_t *reduced_clock)
4529 {
4530         struct drm_device *dev = crtc->base.dev;
4531         struct drm_i915_private *dev_priv = dev->dev_private;
4532         int pipe = crtc->pipe;
4533         u32 fp, fp2 = 0;
4534
4535         if (IS_PINEVIEW(dev)) {
4536                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4537                 if (reduced_clock)
4538                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4539         } else {
4540                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4541                 if (reduced_clock)
4542                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4543         }
4544
4545         I915_WRITE(FP0(pipe), fp);
4546         crtc->config.dpll_hw_state.fp0 = fp;
4547
4548         crtc->lowfreq_avail = false;
4549         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4550             reduced_clock && i915_powersave) {
4551                 I915_WRITE(FP1(pipe), fp2);
4552                 crtc->config.dpll_hw_state.fp1 = fp2;
4553                 crtc->lowfreq_avail = true;
4554         } else {
4555                 I915_WRITE(FP1(pipe), fp);
4556                 crtc->config.dpll_hw_state.fp1 = fp;
4557         }
4558 }
4559
4560 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4561                 pipe)
4562 {
4563         u32 reg_val;
4564
4565         /*
4566          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4567          * and set it to a reasonable value instead.
4568          */
4569         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4570         reg_val &= 0xffffff00;
4571         reg_val |= 0x00000030;
4572         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4573
4574         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4575         reg_val &= 0x8cffffff;
4576         reg_val = 0x8c000000;
4577         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4578
4579         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4580         reg_val &= 0xffffff00;
4581         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4582
4583         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4584         reg_val &= 0x00ffffff;
4585         reg_val |= 0xb0000000;
4586         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4587 }
4588
4589 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4590                                          struct intel_link_m_n *m_n)
4591 {
4592         struct drm_device *dev = crtc->base.dev;
4593         struct drm_i915_private *dev_priv = dev->dev_private;
4594         int pipe = crtc->pipe;
4595
4596         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4597         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4598         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4599         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4600 }
4601
4602 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4603                                          struct intel_link_m_n *m_n)
4604 {
4605         struct drm_device *dev = crtc->base.dev;
4606         struct drm_i915_private *dev_priv = dev->dev_private;
4607         int pipe = crtc->pipe;
4608         enum transcoder transcoder = crtc->config.cpu_transcoder;
4609
4610         if (INTEL_INFO(dev)->gen >= 5) {
4611                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4612                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4613                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4614                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4615         } else {
4616                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4617                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4618                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4619                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4620         }
4621 }
4622
4623 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4624 {
4625         if (crtc->config.has_pch_encoder)
4626                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4627         else
4628                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4629 }
4630
4631 static void vlv_update_pll(struct intel_crtc *crtc)
4632 {
4633         struct drm_device *dev = crtc->base.dev;
4634         struct drm_i915_private *dev_priv = dev->dev_private;
4635         int pipe = crtc->pipe;
4636         u32 dpll, mdiv;
4637         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4638         u32 coreclk, reg_val, dpll_md;
4639
4640         mutex_lock(&dev_priv->dpio_lock);
4641
4642         bestn = crtc->config.dpll.n;
4643         bestm1 = crtc->config.dpll.m1;
4644         bestm2 = crtc->config.dpll.m2;
4645         bestp1 = crtc->config.dpll.p1;
4646         bestp2 = crtc->config.dpll.p2;
4647
4648         /* See eDP HDMI DPIO driver vbios notes doc */
4649
4650         /* PLL B needs special handling */
4651         if (pipe)
4652                 vlv_pllb_recal_opamp(dev_priv, pipe);
4653
4654         /* Set up Tx target for periodic Rcomp update */
4655         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4656
4657         /* Disable target IRef on PLL */
4658         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4659         reg_val &= 0x00ffffff;
4660         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4661
4662         /* Disable fast lock */
4663         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4664
4665         /* Set idtafcrecal before PLL is enabled */
4666         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4667         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4668         mdiv |= ((bestn << DPIO_N_SHIFT));
4669         mdiv |= (1 << DPIO_K_SHIFT);
4670
4671         /*
4672          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4673          * but we don't support that).
4674          * Note: don't use the DAC post divider as it seems unstable.
4675          */
4676         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4677         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4678
4679         mdiv |= DPIO_ENABLE_CALIBRATION;
4680         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4681
4682         /* Set HBR and RBR LPF coefficients */
4683         if (crtc->config.port_clock == 162000 ||
4684             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4685             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4686                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4687                                  0x009f0003);
4688         else
4689                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4690                                  0x00d0000f);
4691
4692         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4693             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4694                 /* Use SSC source */
4695                 if (!pipe)
4696                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4697                                          0x0df40000);
4698                 else
4699                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4700                                          0x0df70000);
4701         } else { /* HDMI or VGA */
4702                 /* Use bend source */
4703                 if (!pipe)
4704                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4705                                          0x0df70000);
4706                 else
4707                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4708                                          0x0df40000);
4709         }
4710
4711         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4712         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4713         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4714             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4715                 coreclk |= 0x01000000;
4716         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4717
4718         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4719
4720         /* Enable DPIO clock input */
4721         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4722                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4723         /* We should never disable this, set it here for state tracking */
4724         if (pipe == PIPE_B)
4725                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4726         dpll |= DPLL_VCO_ENABLE;
4727         crtc->config.dpll_hw_state.dpll = dpll;
4728
4729         dpll_md = (crtc->config.pixel_multiplier - 1)
4730                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4731         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4732
4733         if (crtc->config.has_dp_encoder)
4734                 intel_dp_set_m_n(crtc);
4735
4736         mutex_unlock(&dev_priv->dpio_lock);
4737 }
4738
4739 static void i9xx_update_pll(struct intel_crtc *crtc,
4740                             intel_clock_t *reduced_clock,
4741                             int num_connectors)
4742 {
4743         struct drm_device *dev = crtc->base.dev;
4744         struct drm_i915_private *dev_priv = dev->dev_private;
4745         u32 dpll;
4746         bool is_sdvo;
4747         struct dpll *clock = &crtc->config.dpll;
4748
4749         i9xx_update_pll_dividers(crtc, reduced_clock);
4750
4751         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4752                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4753
4754         dpll = DPLL_VGA_MODE_DIS;
4755
4756         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4757                 dpll |= DPLLB_MODE_LVDS;
4758         else
4759                 dpll |= DPLLB_MODE_DAC_SERIAL;
4760
4761         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4762                 dpll |= (crtc->config.pixel_multiplier - 1)
4763                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4764         }
4765
4766         if (is_sdvo)
4767                 dpll |= DPLL_SDVO_HIGH_SPEED;
4768
4769         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4770                 dpll |= DPLL_SDVO_HIGH_SPEED;
4771
4772         /* compute bitmask from p1 value */
4773         if (IS_PINEVIEW(dev))
4774                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4775         else {
4776                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4777                 if (IS_G4X(dev) && reduced_clock)
4778                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4779         }
4780         switch (clock->p2) {
4781         case 5:
4782                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4783                 break;
4784         case 7:
4785                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4786                 break;
4787         case 10:
4788                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4789                 break;
4790         case 14:
4791                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4792                 break;
4793         }
4794         if (INTEL_INFO(dev)->gen >= 4)
4795                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4796
4797         if (crtc->config.sdvo_tv_clock)
4798                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4799         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4800                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4801                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4802         else
4803                 dpll |= PLL_REF_INPUT_DREFCLK;
4804
4805         dpll |= DPLL_VCO_ENABLE;
4806         crtc->config.dpll_hw_state.dpll = dpll;
4807
4808         if (INTEL_INFO(dev)->gen >= 4) {
4809                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4810                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4811                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4812         }
4813
4814         if (crtc->config.has_dp_encoder)
4815                 intel_dp_set_m_n(crtc);
4816 }
4817
4818 static void i8xx_update_pll(struct intel_crtc *crtc,
4819                             intel_clock_t *reduced_clock,
4820                             int num_connectors)
4821 {
4822         struct drm_device *dev = crtc->base.dev;
4823         struct drm_i915_private *dev_priv = dev->dev_private;
4824         u32 dpll;
4825         struct dpll *clock = &crtc->config.dpll;
4826
4827         i9xx_update_pll_dividers(crtc, reduced_clock);
4828
4829         dpll = DPLL_VGA_MODE_DIS;
4830
4831         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4832                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4833         } else {
4834                 if (clock->p1 == 2)
4835                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4836                 else
4837                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4838                 if (clock->p2 == 4)
4839                         dpll |= PLL_P2_DIVIDE_BY_4;
4840         }
4841
4842         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4843                 dpll |= DPLL_DVO_2X_MODE;
4844
4845         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4846                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4847                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4848         else
4849                 dpll |= PLL_REF_INPUT_DREFCLK;
4850
4851         dpll |= DPLL_VCO_ENABLE;
4852         crtc->config.dpll_hw_state.dpll = dpll;
4853 }
4854
4855 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4856 {
4857         struct drm_device *dev = intel_crtc->base.dev;
4858         struct drm_i915_private *dev_priv = dev->dev_private;
4859         enum pipe pipe = intel_crtc->pipe;
4860         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4861         struct drm_display_mode *adjusted_mode =
4862                 &intel_crtc->config.adjusted_mode;
4863         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4864
4865         /* We need to be careful not to changed the adjusted mode, for otherwise
4866          * the hw state checker will get angry at the mismatch. */
4867         crtc_vtotal = adjusted_mode->crtc_vtotal;
4868         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4869
4870         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4871                 /* the chip adds 2 halflines automatically */
4872                 crtc_vtotal -= 1;
4873                 crtc_vblank_end -= 1;
4874                 vsyncshift = adjusted_mode->crtc_hsync_start
4875                              - adjusted_mode->crtc_htotal / 2;
4876         } else {
4877                 vsyncshift = 0;
4878         }
4879
4880         if (INTEL_INFO(dev)->gen > 3)
4881                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4882
4883         I915_WRITE(HTOTAL(cpu_transcoder),
4884                    (adjusted_mode->crtc_hdisplay - 1) |
4885                    ((adjusted_mode->crtc_htotal - 1) << 16));
4886         I915_WRITE(HBLANK(cpu_transcoder),
4887                    (adjusted_mode->crtc_hblank_start - 1) |
4888                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4889         I915_WRITE(HSYNC(cpu_transcoder),
4890                    (adjusted_mode->crtc_hsync_start - 1) |
4891                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4892
4893         I915_WRITE(VTOTAL(cpu_transcoder),
4894                    (adjusted_mode->crtc_vdisplay - 1) |
4895                    ((crtc_vtotal - 1) << 16));
4896         I915_WRITE(VBLANK(cpu_transcoder),
4897                    (adjusted_mode->crtc_vblank_start - 1) |
4898                    ((crtc_vblank_end - 1) << 16));
4899         I915_WRITE(VSYNC(cpu_transcoder),
4900                    (adjusted_mode->crtc_vsync_start - 1) |
4901                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4902
4903         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4904          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4905          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4906          * bits. */
4907         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4908             (pipe == PIPE_B || pipe == PIPE_C))
4909                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4910
4911         /* pipesrc controls the size that is scaled from, which should
4912          * always be the user's requested size.
4913          */
4914         I915_WRITE(PIPESRC(pipe),
4915                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4916                    (intel_crtc->config.pipe_src_h - 1));
4917 }
4918
4919 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4920                                    struct intel_crtc_config *pipe_config)
4921 {
4922         struct drm_device *dev = crtc->base.dev;
4923         struct drm_i915_private *dev_priv = dev->dev_private;
4924         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4925         uint32_t tmp;
4926
4927         tmp = I915_READ(HTOTAL(cpu_transcoder));
4928         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4929         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4930         tmp = I915_READ(HBLANK(cpu_transcoder));
4931         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4932         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4933         tmp = I915_READ(HSYNC(cpu_transcoder));
4934         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4935         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4936
4937         tmp = I915_READ(VTOTAL(cpu_transcoder));
4938         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4939         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4940         tmp = I915_READ(VBLANK(cpu_transcoder));
4941         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4942         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4943         tmp = I915_READ(VSYNC(cpu_transcoder));
4944         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4945         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4946
4947         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4948                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4949                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4950                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4951         }
4952
4953         tmp = I915_READ(PIPESRC(crtc->pipe));
4954         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4955         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4956
4957         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4958         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4959 }
4960
4961 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4962                                              struct intel_crtc_config *pipe_config)
4963 {
4964         struct drm_crtc *crtc = &intel_crtc->base;
4965
4966         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4967         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4968         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4969         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4970
4971         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4972         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4973         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4974         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4975
4976         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4977
4978         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4979         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4980 }
4981
4982 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4983 {
4984         struct drm_device *dev = intel_crtc->base.dev;
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986         uint32_t pipeconf;
4987
4988         pipeconf = 0;
4989
4990         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4991             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4992                 pipeconf |= PIPECONF_ENABLE;
4993
4994         if (intel_crtc->config.double_wide)
4995                 pipeconf |= PIPECONF_DOUBLE_WIDE;
4996
4997         /* only g4x and later have fancy bpc/dither controls */
4998         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4999                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5000                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5001                         pipeconf |= PIPECONF_DITHER_EN |
5002                                     PIPECONF_DITHER_TYPE_SP;
5003
5004                 switch (intel_crtc->config.pipe_bpp) {
5005                 case 18:
5006                         pipeconf |= PIPECONF_6BPC;
5007                         break;
5008                 case 24:
5009                         pipeconf |= PIPECONF_8BPC;
5010                         break;
5011                 case 30:
5012                         pipeconf |= PIPECONF_10BPC;
5013                         break;
5014                 default:
5015                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5016                         BUG();
5017                 }
5018         }
5019
5020         if (HAS_PIPE_CXSR(dev)) {
5021                 if (intel_crtc->lowfreq_avail) {
5022                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5023                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5024                 } else {
5025                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5026                 }
5027         }
5028
5029         if (!IS_GEN2(dev) &&
5030             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5031                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5032         else
5033                 pipeconf |= PIPECONF_PROGRESSIVE;
5034
5035         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5036                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5037
5038         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5039         POSTING_READ(PIPECONF(intel_crtc->pipe));
5040 }
5041
5042 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5043                               int x, int y,
5044                               struct drm_framebuffer *fb)
5045 {
5046         struct drm_device *dev = crtc->dev;
5047         struct drm_i915_private *dev_priv = dev->dev_private;
5048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5049         int pipe = intel_crtc->pipe;
5050         int plane = intel_crtc->plane;
5051         int refclk, num_connectors = 0;
5052         intel_clock_t clock, reduced_clock;
5053         u32 dspcntr;
5054         bool ok, has_reduced_clock = false;
5055         bool is_lvds = false, is_dsi = false;
5056         struct intel_encoder *encoder;
5057         const intel_limit_t *limit;
5058         int ret;
5059
5060         for_each_encoder_on_crtc(dev, crtc, encoder) {
5061                 switch (encoder->type) {
5062                 case INTEL_OUTPUT_LVDS:
5063                         is_lvds = true;
5064                         break;
5065                 case INTEL_OUTPUT_DSI:
5066                         is_dsi = true;
5067                         break;
5068                 }
5069
5070                 num_connectors++;
5071         }
5072
5073         if (is_dsi)
5074                 goto skip_dpll;
5075
5076         if (!intel_crtc->config.clock_set) {
5077                 refclk = i9xx_get_refclk(crtc, num_connectors);
5078
5079                 /*
5080                  * Returns a set of divisors for the desired target clock with
5081                  * the given refclk, or FALSE.  The returned values represent
5082                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5083                  * 2) / p1 / p2.
5084                  */
5085                 limit = intel_limit(crtc, refclk);
5086                 ok = dev_priv->display.find_dpll(limit, crtc,
5087                                                  intel_crtc->config.port_clock,
5088                                                  refclk, NULL, &clock);
5089                 if (!ok) {
5090                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5091                         return -EINVAL;
5092                 }
5093
5094                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5095                         /*
5096                          * Ensure we match the reduced clock's P to the target
5097                          * clock.  If the clocks don't match, we can't switch
5098                          * the display clock by using the FP0/FP1. In such case
5099                          * we will disable the LVDS downclock feature.
5100                          */
5101                         has_reduced_clock =
5102                                 dev_priv->display.find_dpll(limit, crtc,
5103                                                             dev_priv->lvds_downclock,
5104                                                             refclk, &clock,
5105                                                             &reduced_clock);
5106                 }
5107                 /* Compat-code for transition, will disappear. */
5108                 intel_crtc->config.dpll.n = clock.n;
5109                 intel_crtc->config.dpll.m1 = clock.m1;
5110                 intel_crtc->config.dpll.m2 = clock.m2;
5111                 intel_crtc->config.dpll.p1 = clock.p1;
5112                 intel_crtc->config.dpll.p2 = clock.p2;
5113         }
5114
5115         if (IS_GEN2(dev)) {
5116                 i8xx_update_pll(intel_crtc,
5117                                 has_reduced_clock ? &reduced_clock : NULL,
5118                                 num_connectors);
5119         } else if (IS_VALLEYVIEW(dev)) {
5120                 vlv_update_pll(intel_crtc);
5121         } else {
5122                 i9xx_update_pll(intel_crtc,
5123                                 has_reduced_clock ? &reduced_clock : NULL,
5124                                 num_connectors);
5125         }
5126
5127 skip_dpll:
5128         /* Set up the display plane register */
5129         dspcntr = DISPPLANE_GAMMA_ENABLE;
5130
5131         if (!IS_VALLEYVIEW(dev)) {
5132                 if (pipe == 0)
5133                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5134                 else
5135                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5136         }
5137
5138         intel_set_pipe_timings(intel_crtc);
5139
5140         /* pipesrc and dspsize control the size that is scaled from,
5141          * which should always be the user's requested size.
5142          */
5143         I915_WRITE(DSPSIZE(plane),
5144                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5145                    (intel_crtc->config.pipe_src_w - 1));
5146         I915_WRITE(DSPPOS(plane), 0);
5147
5148         i9xx_set_pipeconf(intel_crtc);
5149
5150         I915_WRITE(DSPCNTR(plane), dspcntr);
5151         POSTING_READ(DSPCNTR(plane));
5152
5153         ret = intel_pipe_set_base(crtc, x, y, fb);
5154
5155         return ret;
5156 }
5157
5158 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5159                                  struct intel_crtc_config *pipe_config)
5160 {
5161         struct drm_device *dev = crtc->base.dev;
5162         struct drm_i915_private *dev_priv = dev->dev_private;
5163         uint32_t tmp;
5164
5165         tmp = I915_READ(PFIT_CONTROL);
5166         if (!(tmp & PFIT_ENABLE))
5167                 return;
5168
5169         /* Check whether the pfit is attached to our pipe. */
5170         if (INTEL_INFO(dev)->gen < 4) {
5171                 if (crtc->pipe != PIPE_B)
5172                         return;
5173         } else {
5174                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5175                         return;
5176         }
5177
5178         pipe_config->gmch_pfit.control = tmp;
5179         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5180         if (INTEL_INFO(dev)->gen < 5)
5181                 pipe_config->gmch_pfit.lvds_border_bits =
5182                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5183 }
5184
5185 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5186                                struct intel_crtc_config *pipe_config)
5187 {
5188         struct drm_device *dev = crtc->base.dev;
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190         int pipe = pipe_config->cpu_transcoder;
5191         intel_clock_t clock;
5192         u32 mdiv;
5193         int refclk = 100000;
5194
5195         mutex_lock(&dev_priv->dpio_lock);
5196         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5197         mutex_unlock(&dev_priv->dpio_lock);
5198
5199         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5200         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5201         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5202         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5203         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5204
5205         clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5206         clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
5207
5208         pipe_config->port_clock = clock.dot / 10;
5209 }
5210
5211 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5212                                  struct intel_crtc_config *pipe_config)
5213 {
5214         struct drm_device *dev = crtc->base.dev;
5215         struct drm_i915_private *dev_priv = dev->dev_private;
5216         uint32_t tmp;
5217
5218         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5219         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5220
5221         tmp = I915_READ(PIPECONF(crtc->pipe));
5222         if (!(tmp & PIPECONF_ENABLE))
5223                 return false;
5224
5225         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5226                 switch (tmp & PIPECONF_BPC_MASK) {
5227                 case PIPECONF_6BPC:
5228                         pipe_config->pipe_bpp = 18;
5229                         break;
5230                 case PIPECONF_8BPC:
5231                         pipe_config->pipe_bpp = 24;
5232                         break;
5233                 case PIPECONF_10BPC:
5234                         pipe_config->pipe_bpp = 30;
5235                         break;
5236                 default:
5237                         break;
5238                 }
5239         }
5240
5241         if (INTEL_INFO(dev)->gen < 4)
5242                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5243
5244         intel_get_pipe_timings(crtc, pipe_config);
5245
5246         i9xx_get_pfit_config(crtc, pipe_config);
5247
5248         if (INTEL_INFO(dev)->gen >= 4) {
5249                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5250                 pipe_config->pixel_multiplier =
5251                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5252                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5253                 pipe_config->dpll_hw_state.dpll_md = tmp;
5254         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5255                 tmp = I915_READ(DPLL(crtc->pipe));
5256                 pipe_config->pixel_multiplier =
5257                         ((tmp & SDVO_MULTIPLIER_MASK)
5258                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5259         } else {
5260                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5261                  * port and will be fixed up in the encoder->get_config
5262                  * function. */
5263                 pipe_config->pixel_multiplier = 1;
5264         }
5265         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5266         if (!IS_VALLEYVIEW(dev)) {
5267                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5268                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5269         } else {
5270                 /* Mask out read-only status bits. */
5271                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5272                                                      DPLL_PORTC_READY_MASK |
5273                                                      DPLL_PORTB_READY_MASK);
5274         }
5275
5276         if (IS_VALLEYVIEW(dev))
5277                 vlv_crtc_clock_get(crtc, pipe_config);
5278         else
5279                 i9xx_crtc_clock_get(crtc, pipe_config);
5280
5281         return true;
5282 }
5283
5284 static void ironlake_init_pch_refclk(struct drm_device *dev)
5285 {
5286         struct drm_i915_private *dev_priv = dev->dev_private;
5287         struct drm_mode_config *mode_config = &dev->mode_config;
5288         struct intel_encoder *encoder;
5289         u32 val, final;
5290         bool has_lvds = false;
5291         bool has_cpu_edp = false;
5292         bool has_panel = false;
5293         bool has_ck505 = false;
5294         bool can_ssc = false;
5295
5296         /* We need to take the global config into account */
5297         list_for_each_entry(encoder, &mode_config->encoder_list,
5298                             base.head) {
5299                 switch (encoder->type) {
5300                 case INTEL_OUTPUT_LVDS:
5301                         has_panel = true;
5302                         has_lvds = true;
5303                         break;
5304                 case INTEL_OUTPUT_EDP:
5305                         has_panel = true;
5306                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5307                                 has_cpu_edp = true;
5308                         break;
5309                 }
5310         }
5311
5312         if (HAS_PCH_IBX(dev)) {
5313                 has_ck505 = dev_priv->vbt.display_clock_mode;
5314                 can_ssc = has_ck505;
5315         } else {
5316                 has_ck505 = false;
5317                 can_ssc = true;
5318         }
5319
5320         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5321                       has_panel, has_lvds, has_ck505);
5322
5323         /* Ironlake: try to setup display ref clock before DPLL
5324          * enabling. This is only under driver's control after
5325          * PCH B stepping, previous chipset stepping should be
5326          * ignoring this setting.
5327          */
5328         val = I915_READ(PCH_DREF_CONTROL);
5329
5330         /* As we must carefully and slowly disable/enable each source in turn,
5331          * compute the final state we want first and check if we need to
5332          * make any changes at all.
5333          */
5334         final = val;
5335         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5336         if (has_ck505)
5337                 final |= DREF_NONSPREAD_CK505_ENABLE;
5338         else
5339                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5340
5341         final &= ~DREF_SSC_SOURCE_MASK;
5342         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5343         final &= ~DREF_SSC1_ENABLE;
5344
5345         if (has_panel) {
5346                 final |= DREF_SSC_SOURCE_ENABLE;
5347
5348                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5349                         final |= DREF_SSC1_ENABLE;
5350
5351                 if (has_cpu_edp) {
5352                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5353                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5354                         else
5355                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5356                 } else
5357                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5358         } else {
5359                 final |= DREF_SSC_SOURCE_DISABLE;
5360                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5361         }
5362
5363         if (final == val)
5364                 return;
5365
5366         /* Always enable nonspread source */
5367         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5368
5369         if (has_ck505)
5370                 val |= DREF_NONSPREAD_CK505_ENABLE;
5371         else
5372                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5373
5374         if (has_panel) {
5375                 val &= ~DREF_SSC_SOURCE_MASK;
5376                 val |= DREF_SSC_SOURCE_ENABLE;
5377
5378                 /* SSC must be turned on before enabling the CPU output  */
5379                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5380                         DRM_DEBUG_KMS("Using SSC on panel\n");
5381                         val |= DREF_SSC1_ENABLE;
5382                 } else
5383                         val &= ~DREF_SSC1_ENABLE;
5384
5385                 /* Get SSC going before enabling the outputs */
5386                 I915_WRITE(PCH_DREF_CONTROL, val);
5387                 POSTING_READ(PCH_DREF_CONTROL);
5388                 udelay(200);
5389
5390                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5391
5392                 /* Enable CPU source on CPU attached eDP */
5393                 if (has_cpu_edp) {
5394                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5395                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5396                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5397                         }
5398                         else
5399                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5400                 } else
5401                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5402
5403                 I915_WRITE(PCH_DREF_CONTROL, val);
5404                 POSTING_READ(PCH_DREF_CONTROL);
5405                 udelay(200);
5406         } else {
5407                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5408
5409                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5410
5411                 /* Turn off CPU output */
5412                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5413
5414                 I915_WRITE(PCH_DREF_CONTROL, val);
5415                 POSTING_READ(PCH_DREF_CONTROL);
5416                 udelay(200);
5417
5418                 /* Turn off the SSC source */
5419                 val &= ~DREF_SSC_SOURCE_MASK;
5420                 val |= DREF_SSC_SOURCE_DISABLE;
5421
5422                 /* Turn off SSC1 */
5423                 val &= ~DREF_SSC1_ENABLE;
5424
5425                 I915_WRITE(PCH_DREF_CONTROL, val);
5426                 POSTING_READ(PCH_DREF_CONTROL);
5427                 udelay(200);
5428         }
5429
5430         BUG_ON(val != final);
5431 }
5432
5433 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5434 {
5435         uint32_t tmp;
5436
5437         tmp = I915_READ(SOUTH_CHICKEN2);
5438         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5439         I915_WRITE(SOUTH_CHICKEN2, tmp);
5440
5441         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5442                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5443                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5444
5445         tmp = I915_READ(SOUTH_CHICKEN2);
5446         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5447         I915_WRITE(SOUTH_CHICKEN2, tmp);
5448
5449         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5450                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5451                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5452 }
5453
5454 /* WaMPhyProgramming:hsw */
5455 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5456 {
5457         uint32_t tmp;
5458
5459         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5460         tmp &= ~(0xFF << 24);
5461         tmp |= (0x12 << 24);
5462         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5463
5464         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5465         tmp |= (1 << 11);
5466         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5467
5468         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5469         tmp |= (1 << 11);
5470         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5471
5472         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5473         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5474         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5475
5476         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5477         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5478         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5479
5480         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5481         tmp &= ~(7 << 13);
5482         tmp |= (5 << 13);
5483         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5484
5485         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5486         tmp &= ~(7 << 13);
5487         tmp |= (5 << 13);
5488         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5489
5490         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5491         tmp &= ~0xFF;
5492         tmp |= 0x1C;
5493         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5494
5495         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5496         tmp &= ~0xFF;
5497         tmp |= 0x1C;
5498         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5499
5500         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5501         tmp &= ~(0xFF << 16);
5502         tmp |= (0x1C << 16);
5503         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5504
5505         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5506         tmp &= ~(0xFF << 16);
5507         tmp |= (0x1C << 16);
5508         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5509
5510         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5511         tmp |= (1 << 27);
5512         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5513
5514         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5515         tmp |= (1 << 27);
5516         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5517
5518         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5519         tmp &= ~(0xF << 28);
5520         tmp |= (4 << 28);
5521         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5522
5523         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5524         tmp &= ~(0xF << 28);
5525         tmp |= (4 << 28);
5526         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5527 }
5528
5529 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5530  * Programming" based on the parameters passed:
5531  * - Sequence to enable CLKOUT_DP
5532  * - Sequence to enable CLKOUT_DP without spread
5533  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5534  */
5535 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5536                                  bool with_fdi)
5537 {
5538         struct drm_i915_private *dev_priv = dev->dev_private;
5539         uint32_t reg, tmp;
5540
5541         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5542                 with_spread = true;
5543         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5544                  with_fdi, "LP PCH doesn't have FDI\n"))
5545                 with_fdi = false;
5546
5547         mutex_lock(&dev_priv->dpio_lock);
5548
5549         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5550         tmp &= ~SBI_SSCCTL_DISABLE;
5551         tmp |= SBI_SSCCTL_PATHALT;
5552         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5553
5554         udelay(24);
5555
5556         if (with_spread) {
5557                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5558                 tmp &= ~SBI_SSCCTL_PATHALT;
5559                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5560
5561                 if (with_fdi) {
5562                         lpt_reset_fdi_mphy(dev_priv);
5563                         lpt_program_fdi_mphy(dev_priv);
5564                 }
5565         }
5566
5567         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5568                SBI_GEN0 : SBI_DBUFF0;
5569         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5570         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5571         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5572
5573         mutex_unlock(&dev_priv->dpio_lock);
5574 }
5575
5576 /* Sequence to disable CLKOUT_DP */
5577 static void lpt_disable_clkout_dp(struct drm_device *dev)
5578 {
5579         struct drm_i915_private *dev_priv = dev->dev_private;
5580         uint32_t reg, tmp;
5581
5582         mutex_lock(&dev_priv->dpio_lock);
5583
5584         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5585                SBI_GEN0 : SBI_DBUFF0;
5586         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5587         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5588         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5589
5590         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5591         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5592                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5593                         tmp |= SBI_SSCCTL_PATHALT;
5594                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5595                         udelay(32);
5596                 }
5597                 tmp |= SBI_SSCCTL_DISABLE;
5598                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5599         }
5600
5601         mutex_unlock(&dev_priv->dpio_lock);
5602 }
5603
5604 static void lpt_init_pch_refclk(struct drm_device *dev)
5605 {
5606         struct drm_mode_config *mode_config = &dev->mode_config;
5607         struct intel_encoder *encoder;
5608         bool has_vga = false;
5609
5610         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5611                 switch (encoder->type) {
5612                 case INTEL_OUTPUT_ANALOG:
5613                         has_vga = true;
5614                         break;
5615                 }
5616         }
5617
5618         if (has_vga)
5619                 lpt_enable_clkout_dp(dev, true, true);
5620         else
5621                 lpt_disable_clkout_dp(dev);
5622 }
5623
5624 /*
5625  * Initialize reference clocks when the driver loads
5626  */
5627 void intel_init_pch_refclk(struct drm_device *dev)
5628 {
5629         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5630                 ironlake_init_pch_refclk(dev);
5631         else if (HAS_PCH_LPT(dev))
5632                 lpt_init_pch_refclk(dev);
5633 }
5634
5635 static int ironlake_get_refclk(struct drm_crtc *crtc)
5636 {
5637         struct drm_device *dev = crtc->dev;
5638         struct drm_i915_private *dev_priv = dev->dev_private;
5639         struct intel_encoder *encoder;
5640         int num_connectors = 0;
5641         bool is_lvds = false;
5642
5643         for_each_encoder_on_crtc(dev, crtc, encoder) {
5644                 switch (encoder->type) {
5645                 case INTEL_OUTPUT_LVDS:
5646                         is_lvds = true;
5647                         break;
5648                 }
5649                 num_connectors++;
5650         }
5651
5652         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5653                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5654                               dev_priv->vbt.lvds_ssc_freq);
5655                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5656         }
5657
5658         return 120000;
5659 }
5660
5661 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5662 {
5663         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5665         int pipe = intel_crtc->pipe;
5666         uint32_t val;
5667
5668         val = 0;
5669
5670         switch (intel_crtc->config.pipe_bpp) {
5671         case 18:
5672                 val |= PIPECONF_6BPC;
5673                 break;
5674         case 24:
5675                 val |= PIPECONF_8BPC;
5676                 break;
5677         case 30:
5678                 val |= PIPECONF_10BPC;
5679                 break;
5680         case 36:
5681                 val |= PIPECONF_12BPC;
5682                 break;
5683         default:
5684                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5685                 BUG();
5686         }
5687
5688         if (intel_crtc->config.dither)
5689                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5690
5691         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5692                 val |= PIPECONF_INTERLACED_ILK;
5693         else
5694                 val |= PIPECONF_PROGRESSIVE;
5695
5696         if (intel_crtc->config.limited_color_range)
5697                 val |= PIPECONF_COLOR_RANGE_SELECT;
5698
5699         I915_WRITE(PIPECONF(pipe), val);
5700         POSTING_READ(PIPECONF(pipe));
5701 }
5702
5703 /*
5704  * Set up the pipe CSC unit.
5705  *
5706  * Currently only full range RGB to limited range RGB conversion
5707  * is supported, but eventually this should handle various
5708  * RGB<->YCbCr scenarios as well.
5709  */
5710 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5711 {
5712         struct drm_device *dev = crtc->dev;
5713         struct drm_i915_private *dev_priv = dev->dev_private;
5714         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5715         int pipe = intel_crtc->pipe;
5716         uint16_t coeff = 0x7800; /* 1.0 */
5717
5718         /*
5719          * TODO: Check what kind of values actually come out of the pipe
5720          * with these coeff/postoff values and adjust to get the best
5721          * accuracy. Perhaps we even need to take the bpc value into
5722          * consideration.
5723          */
5724
5725         if (intel_crtc->config.limited_color_range)
5726                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5727
5728         /*
5729          * GY/GU and RY/RU should be the other way around according
5730          * to BSpec, but reality doesn't agree. Just set them up in
5731          * a way that results in the correct picture.
5732          */
5733         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5734         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5735
5736         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5737         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5738
5739         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5740         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5741
5742         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5743         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5744         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5745
5746         if (INTEL_INFO(dev)->gen > 6) {
5747                 uint16_t postoff = 0;
5748
5749                 if (intel_crtc->config.limited_color_range)
5750                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5751
5752                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5753                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5754                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5755
5756                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5757         } else {
5758                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5759
5760                 if (intel_crtc->config.limited_color_range)
5761                         mode |= CSC_BLACK_SCREEN_OFFSET;
5762
5763                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5764         }
5765 }
5766
5767 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5768 {
5769         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5770         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5771         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5772         uint32_t val;
5773
5774         val = 0;
5775
5776         if (intel_crtc->config.dither)
5777                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5778
5779         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5780                 val |= PIPECONF_INTERLACED_ILK;
5781         else
5782                 val |= PIPECONF_PROGRESSIVE;
5783
5784         I915_WRITE(PIPECONF(cpu_transcoder), val);
5785         POSTING_READ(PIPECONF(cpu_transcoder));
5786
5787         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5788         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5789 }
5790
5791 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5792                                     intel_clock_t *clock,
5793                                     bool *has_reduced_clock,
5794                                     intel_clock_t *reduced_clock)
5795 {
5796         struct drm_device *dev = crtc->dev;
5797         struct drm_i915_private *dev_priv = dev->dev_private;
5798         struct intel_encoder *intel_encoder;
5799         int refclk;
5800         const intel_limit_t *limit;
5801         bool ret, is_lvds = false;
5802
5803         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5804                 switch (intel_encoder->type) {
5805                 case INTEL_OUTPUT_LVDS:
5806                         is_lvds = true;
5807                         break;
5808                 }
5809         }
5810
5811         refclk = ironlake_get_refclk(crtc);
5812
5813         /*
5814          * Returns a set of divisors for the desired target clock with the given
5815          * refclk, or FALSE.  The returned values represent the clock equation:
5816          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5817          */
5818         limit = intel_limit(crtc, refclk);
5819         ret = dev_priv->display.find_dpll(limit, crtc,
5820                                           to_intel_crtc(crtc)->config.port_clock,
5821                                           refclk, NULL, clock);
5822         if (!ret)
5823                 return false;
5824
5825         if (is_lvds && dev_priv->lvds_downclock_avail) {
5826                 /*
5827                  * Ensure we match the reduced clock's P to the target clock.
5828                  * If the clocks don't match, we can't switch the display clock
5829                  * by using the FP0/FP1. In such case we will disable the LVDS
5830                  * downclock feature.
5831                 */
5832                 *has_reduced_clock =
5833                         dev_priv->display.find_dpll(limit, crtc,
5834                                                     dev_priv->lvds_downclock,
5835                                                     refclk, clock,
5836                                                     reduced_clock);
5837         }
5838
5839         return true;
5840 }
5841
5842 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5843 {
5844         struct drm_i915_private *dev_priv = dev->dev_private;
5845         uint32_t temp;
5846
5847         temp = I915_READ(SOUTH_CHICKEN1);
5848         if (temp & FDI_BC_BIFURCATION_SELECT)
5849                 return;
5850
5851         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5852         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5853
5854         temp |= FDI_BC_BIFURCATION_SELECT;
5855         DRM_DEBUG_KMS("enabling fdi C rx\n");
5856         I915_WRITE(SOUTH_CHICKEN1, temp);
5857         POSTING_READ(SOUTH_CHICKEN1);
5858 }
5859
5860 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5861 {
5862         struct drm_device *dev = intel_crtc->base.dev;
5863         struct drm_i915_private *dev_priv = dev->dev_private;
5864
5865         switch (intel_crtc->pipe) {
5866         case PIPE_A:
5867                 break;
5868         case PIPE_B:
5869                 if (intel_crtc->config.fdi_lanes > 2)
5870                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5871                 else
5872                         cpt_enable_fdi_bc_bifurcation(dev);
5873
5874                 break;
5875         case PIPE_C:
5876                 cpt_enable_fdi_bc_bifurcation(dev);
5877
5878                 break;
5879         default:
5880                 BUG();
5881         }
5882 }
5883
5884 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5885 {
5886         /*
5887          * Account for spread spectrum to avoid
5888          * oversubscribing the link. Max center spread
5889          * is 2.5%; use 5% for safety's sake.
5890          */
5891         u32 bps = target_clock * bpp * 21 / 20;
5892         return bps / (link_bw * 8) + 1;
5893 }
5894
5895 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5896 {
5897         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5898 }
5899
5900 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5901                                       u32 *fp,
5902                                       intel_clock_t *reduced_clock, u32 *fp2)
5903 {
5904         struct drm_crtc *crtc = &intel_crtc->base;
5905         struct drm_device *dev = crtc->dev;
5906         struct drm_i915_private *dev_priv = dev->dev_private;
5907         struct intel_encoder *intel_encoder;
5908         uint32_t dpll;
5909         int factor, num_connectors = 0;
5910         bool is_lvds = false, is_sdvo = false;
5911
5912         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5913                 switch (intel_encoder->type) {
5914                 case INTEL_OUTPUT_LVDS:
5915                         is_lvds = true;
5916                         break;
5917                 case INTEL_OUTPUT_SDVO:
5918                 case INTEL_OUTPUT_HDMI:
5919                         is_sdvo = true;
5920                         break;
5921                 }
5922
5923                 num_connectors++;
5924         }
5925
5926         /* Enable autotuning of the PLL clock (if permissible) */
5927         factor = 21;
5928         if (is_lvds) {
5929                 if ((intel_panel_use_ssc(dev_priv) &&
5930                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5931                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5932                         factor = 25;
5933         } else if (intel_crtc->config.sdvo_tv_clock)
5934                 factor = 20;
5935
5936         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5937                 *fp |= FP_CB_TUNE;
5938
5939         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5940                 *fp2 |= FP_CB_TUNE;
5941
5942         dpll = 0;
5943
5944         if (is_lvds)
5945                 dpll |= DPLLB_MODE_LVDS;
5946         else
5947                 dpll |= DPLLB_MODE_DAC_SERIAL;
5948
5949         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5950                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5951
5952         if (is_sdvo)
5953                 dpll |= DPLL_SDVO_HIGH_SPEED;
5954         if (intel_crtc->config.has_dp_encoder)
5955                 dpll |= DPLL_SDVO_HIGH_SPEED;
5956
5957         /* compute bitmask from p1 value */
5958         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5959         /* also FPA1 */
5960         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5961
5962         switch (intel_crtc->config.dpll.p2) {
5963         case 5:
5964                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5965                 break;
5966         case 7:
5967                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5968                 break;
5969         case 10:
5970                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5971                 break;
5972         case 14:
5973                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5974                 break;
5975         }
5976
5977         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5978                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5979         else
5980                 dpll |= PLL_REF_INPUT_DREFCLK;
5981
5982         return dpll | DPLL_VCO_ENABLE;
5983 }
5984
5985 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5986                                   int x, int y,
5987                                   struct drm_framebuffer *fb)
5988 {
5989         struct drm_device *dev = crtc->dev;
5990         struct drm_i915_private *dev_priv = dev->dev_private;
5991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5992         int pipe = intel_crtc->pipe;
5993         int plane = intel_crtc->plane;
5994         int num_connectors = 0;
5995         intel_clock_t clock, reduced_clock;
5996         u32 dpll = 0, fp = 0, fp2 = 0;
5997         bool ok, has_reduced_clock = false;
5998         bool is_lvds = false;
5999         struct intel_encoder *encoder;
6000         struct intel_shared_dpll *pll;
6001         int ret;
6002
6003         for_each_encoder_on_crtc(dev, crtc, encoder) {
6004                 switch (encoder->type) {
6005                 case INTEL_OUTPUT_LVDS:
6006                         is_lvds = true;
6007                         break;
6008                 }
6009
6010                 num_connectors++;
6011         }
6012
6013         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6014              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6015
6016         ok = ironlake_compute_clocks(crtc, &clock,
6017                                      &has_reduced_clock, &reduced_clock);
6018         if (!ok && !intel_crtc->config.clock_set) {
6019                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6020                 return -EINVAL;
6021         }
6022         /* Compat-code for transition, will disappear. */
6023         if (!intel_crtc->config.clock_set) {
6024                 intel_crtc->config.dpll.n = clock.n;
6025                 intel_crtc->config.dpll.m1 = clock.m1;
6026                 intel_crtc->config.dpll.m2 = clock.m2;
6027                 intel_crtc->config.dpll.p1 = clock.p1;
6028                 intel_crtc->config.dpll.p2 = clock.p2;
6029         }
6030
6031         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6032         if (intel_crtc->config.has_pch_encoder) {
6033                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6034                 if (has_reduced_clock)
6035                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6036
6037                 dpll = ironlake_compute_dpll(intel_crtc,
6038                                              &fp, &reduced_clock,
6039                                              has_reduced_clock ? &fp2 : NULL);
6040
6041                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6042                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6043                 if (has_reduced_clock)
6044                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6045                 else
6046                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6047
6048                 pll = intel_get_shared_dpll(intel_crtc);
6049                 if (pll == NULL) {
6050                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6051                                          pipe_name(pipe));
6052                         return -EINVAL;
6053                 }
6054         } else
6055                 intel_put_shared_dpll(intel_crtc);
6056
6057         if (intel_crtc->config.has_dp_encoder)
6058                 intel_dp_set_m_n(intel_crtc);
6059
6060         if (is_lvds && has_reduced_clock && i915_powersave)
6061                 intel_crtc->lowfreq_avail = true;
6062         else
6063                 intel_crtc->lowfreq_avail = false;
6064
6065         if (intel_crtc->config.has_pch_encoder) {
6066                 pll = intel_crtc_to_shared_dpll(intel_crtc);
6067
6068         }
6069
6070         intel_set_pipe_timings(intel_crtc);
6071
6072         if (intel_crtc->config.has_pch_encoder) {
6073                 intel_cpu_transcoder_set_m_n(intel_crtc,
6074                                              &intel_crtc->config.fdi_m_n);
6075         }
6076
6077         if (IS_IVYBRIDGE(dev))
6078                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6079
6080         ironlake_set_pipeconf(crtc);
6081
6082         /* Set up the display plane register */
6083         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6084         POSTING_READ(DSPCNTR(plane));
6085
6086         ret = intel_pipe_set_base(crtc, x, y, fb);
6087
6088         return ret;
6089 }
6090
6091 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6092                                          struct intel_link_m_n *m_n)
6093 {
6094         struct drm_device *dev = crtc->base.dev;
6095         struct drm_i915_private *dev_priv = dev->dev_private;
6096         enum pipe pipe = crtc->pipe;
6097
6098         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6099         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6100         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6101                 & ~TU_SIZE_MASK;
6102         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6103         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6104                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6105 }
6106
6107 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6108                                          enum transcoder transcoder,
6109                                          struct intel_link_m_n *m_n)
6110 {
6111         struct drm_device *dev = crtc->base.dev;
6112         struct drm_i915_private *dev_priv = dev->dev_private;
6113         enum pipe pipe = crtc->pipe;
6114
6115         if (INTEL_INFO(dev)->gen >= 5) {
6116                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6117                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6118                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6119                         & ~TU_SIZE_MASK;
6120                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6121                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6122                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6123         } else {
6124                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6125                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6126                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6127                         & ~TU_SIZE_MASK;
6128                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6129                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6130                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6131         }
6132 }
6133
6134 void intel_dp_get_m_n(struct intel_crtc *crtc,
6135                       struct intel_crtc_config *pipe_config)
6136 {
6137         if (crtc->config.has_pch_encoder)
6138                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6139         else
6140                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6141                                              &pipe_config->dp_m_n);
6142 }
6143
6144 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6145                                         struct intel_crtc_config *pipe_config)
6146 {
6147         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6148                                      &pipe_config->fdi_m_n);
6149 }
6150
6151 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6152                                      struct intel_crtc_config *pipe_config)
6153 {
6154         struct drm_device *dev = crtc->base.dev;
6155         struct drm_i915_private *dev_priv = dev->dev_private;
6156         uint32_t tmp;
6157
6158         tmp = I915_READ(PF_CTL(crtc->pipe));
6159
6160         if (tmp & PF_ENABLE) {
6161                 pipe_config->pch_pfit.enabled = true;
6162                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6163                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6164
6165                 /* We currently do not free assignements of panel fitters on
6166                  * ivb/hsw (since we don't use the higher upscaling modes which
6167                  * differentiates them) so just WARN about this case for now. */
6168                 if (IS_GEN7(dev)) {
6169                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6170                                 PF_PIPE_SEL_IVB(crtc->pipe));
6171                 }
6172         }
6173 }
6174
6175 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6176                                      struct intel_crtc_config *pipe_config)
6177 {
6178         struct drm_device *dev = crtc->base.dev;
6179         struct drm_i915_private *dev_priv = dev->dev_private;
6180         uint32_t tmp;
6181
6182         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6183         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6184
6185         tmp = I915_READ(PIPECONF(crtc->pipe));
6186         if (!(tmp & PIPECONF_ENABLE))
6187                 return false;
6188
6189         switch (tmp & PIPECONF_BPC_MASK) {
6190         case PIPECONF_6BPC:
6191                 pipe_config->pipe_bpp = 18;
6192                 break;
6193         case PIPECONF_8BPC:
6194                 pipe_config->pipe_bpp = 24;
6195                 break;
6196         case PIPECONF_10BPC:
6197                 pipe_config->pipe_bpp = 30;
6198                 break;
6199         case PIPECONF_12BPC:
6200                 pipe_config->pipe_bpp = 36;
6201                 break;
6202         default:
6203                 break;
6204         }
6205
6206         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6207                 struct intel_shared_dpll *pll;
6208
6209                 pipe_config->has_pch_encoder = true;
6210
6211                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6212                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6213                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6214
6215                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6216
6217                 if (HAS_PCH_IBX(dev_priv->dev)) {
6218                         pipe_config->shared_dpll =
6219                                 (enum intel_dpll_id) crtc->pipe;
6220                 } else {
6221                         tmp = I915_READ(PCH_DPLL_SEL);
6222                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6223                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6224                         else
6225                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6226                 }
6227
6228                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6229
6230                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6231                                            &pipe_config->dpll_hw_state));
6232
6233                 tmp = pipe_config->dpll_hw_state.dpll;
6234                 pipe_config->pixel_multiplier =
6235                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6236                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6237
6238                 ironlake_pch_clock_get(crtc, pipe_config);
6239         } else {
6240                 pipe_config->pixel_multiplier = 1;
6241         }
6242
6243         intel_get_pipe_timings(crtc, pipe_config);
6244
6245         ironlake_get_pfit_config(crtc, pipe_config);
6246
6247         return true;
6248 }
6249
6250 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6251 {
6252         struct drm_device *dev = dev_priv->dev;
6253         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6254         struct intel_crtc *crtc;
6255         unsigned long irqflags;
6256         uint32_t val;
6257
6258         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6259                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6260                      pipe_name(crtc->pipe));
6261
6262         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6263         WARN(plls->spll_refcount, "SPLL enabled\n");
6264         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6265         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6266         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6267         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6268              "CPU PWM1 enabled\n");
6269         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6270              "CPU PWM2 enabled\n");
6271         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6272              "PCH PWM1 enabled\n");
6273         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6274              "Utility pin enabled\n");
6275         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6276
6277         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6278         val = I915_READ(DEIMR);
6279         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6280              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6281         val = I915_READ(SDEIMR);
6282         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6283              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6284         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6285 }
6286
6287 /*
6288  * This function implements pieces of two sequences from BSpec:
6289  * - Sequence for display software to disable LCPLL
6290  * - Sequence for display software to allow package C8+
6291  * The steps implemented here are just the steps that actually touch the LCPLL
6292  * register. Callers should take care of disabling all the display engine
6293  * functions, doing the mode unset, fixing interrupts, etc.
6294  */
6295 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6296                               bool switch_to_fclk, bool allow_power_down)
6297 {
6298         uint32_t val;
6299
6300         assert_can_disable_lcpll(dev_priv);
6301
6302         val = I915_READ(LCPLL_CTL);
6303
6304         if (switch_to_fclk) {
6305                 val |= LCPLL_CD_SOURCE_FCLK;
6306                 I915_WRITE(LCPLL_CTL, val);
6307
6308                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6309                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6310                         DRM_ERROR("Switching to FCLK failed\n");
6311
6312                 val = I915_READ(LCPLL_CTL);
6313         }
6314
6315         val |= LCPLL_PLL_DISABLE;
6316         I915_WRITE(LCPLL_CTL, val);
6317         POSTING_READ(LCPLL_CTL);
6318
6319         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6320                 DRM_ERROR("LCPLL still locked\n");
6321
6322         val = I915_READ(D_COMP);
6323         val |= D_COMP_COMP_DISABLE;
6324         mutex_lock(&dev_priv->rps.hw_lock);
6325         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6326                 DRM_ERROR("Failed to disable D_COMP\n");
6327         mutex_unlock(&dev_priv->rps.hw_lock);
6328         POSTING_READ(D_COMP);
6329         ndelay(100);
6330
6331         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6332                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6333
6334         if (allow_power_down) {
6335                 val = I915_READ(LCPLL_CTL);
6336                 val |= LCPLL_POWER_DOWN_ALLOW;
6337                 I915_WRITE(LCPLL_CTL, val);
6338                 POSTING_READ(LCPLL_CTL);
6339         }
6340 }
6341
6342 /*
6343  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6344  * source.
6345  */
6346 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6347 {
6348         uint32_t val;
6349
6350         val = I915_READ(LCPLL_CTL);
6351
6352         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6353                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6354                 return;
6355
6356         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6357          * we'll hang the machine! */
6358         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6359
6360         if (val & LCPLL_POWER_DOWN_ALLOW) {
6361                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6362                 I915_WRITE(LCPLL_CTL, val);
6363                 POSTING_READ(LCPLL_CTL);
6364         }
6365
6366         val = I915_READ(D_COMP);
6367         val |= D_COMP_COMP_FORCE;
6368         val &= ~D_COMP_COMP_DISABLE;
6369         mutex_lock(&dev_priv->rps.hw_lock);
6370         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6371                 DRM_ERROR("Failed to enable D_COMP\n");
6372         mutex_unlock(&dev_priv->rps.hw_lock);
6373         POSTING_READ(D_COMP);
6374
6375         val = I915_READ(LCPLL_CTL);
6376         val &= ~LCPLL_PLL_DISABLE;
6377         I915_WRITE(LCPLL_CTL, val);
6378
6379         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6380                 DRM_ERROR("LCPLL not locked yet\n");
6381
6382         if (val & LCPLL_CD_SOURCE_FCLK) {
6383                 val = I915_READ(LCPLL_CTL);
6384                 val &= ~LCPLL_CD_SOURCE_FCLK;
6385                 I915_WRITE(LCPLL_CTL, val);
6386
6387                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6388                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6389                         DRM_ERROR("Switching back to LCPLL failed\n");
6390         }
6391
6392         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6393 }
6394
6395 void hsw_enable_pc8_work(struct work_struct *__work)
6396 {
6397         struct drm_i915_private *dev_priv =
6398                 container_of(to_delayed_work(__work), struct drm_i915_private,
6399                              pc8.enable_work);
6400         struct drm_device *dev = dev_priv->dev;
6401         uint32_t val;
6402
6403         if (dev_priv->pc8.enabled)
6404                 return;
6405
6406         DRM_DEBUG_KMS("Enabling package C8+\n");
6407
6408         dev_priv->pc8.enabled = true;
6409
6410         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6411                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6412                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6413                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6414         }
6415
6416         lpt_disable_clkout_dp(dev);
6417         hsw_pc8_disable_interrupts(dev);
6418         hsw_disable_lcpll(dev_priv, true, true);
6419 }
6420
6421 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6422 {
6423         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6424         WARN(dev_priv->pc8.disable_count < 1,
6425              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6426
6427         dev_priv->pc8.disable_count--;
6428         if (dev_priv->pc8.disable_count != 0)
6429                 return;
6430
6431         schedule_delayed_work(&dev_priv->pc8.enable_work,
6432                               msecs_to_jiffies(i915_pc8_timeout));
6433 }
6434
6435 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6436 {
6437         struct drm_device *dev = dev_priv->dev;
6438         uint32_t val;
6439
6440         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6441         WARN(dev_priv->pc8.disable_count < 0,
6442              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6443
6444         dev_priv->pc8.disable_count++;
6445         if (dev_priv->pc8.disable_count != 1)
6446                 return;
6447
6448         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6449         if (!dev_priv->pc8.enabled)
6450                 return;
6451
6452         DRM_DEBUG_KMS("Disabling package C8+\n");
6453
6454         hsw_restore_lcpll(dev_priv);
6455         hsw_pc8_restore_interrupts(dev);
6456         lpt_init_pch_refclk(dev);
6457
6458         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6459                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6460                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6461                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6462         }
6463
6464         intel_prepare_ddi(dev);
6465         i915_gem_init_swizzling(dev);
6466         mutex_lock(&dev_priv->rps.hw_lock);
6467         gen6_update_ring_freq(dev);
6468         mutex_unlock(&dev_priv->rps.hw_lock);
6469         dev_priv->pc8.enabled = false;
6470 }
6471
6472 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6473 {
6474         mutex_lock(&dev_priv->pc8.lock);
6475         __hsw_enable_package_c8(dev_priv);
6476         mutex_unlock(&dev_priv->pc8.lock);
6477 }
6478
6479 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6480 {
6481         mutex_lock(&dev_priv->pc8.lock);
6482         __hsw_disable_package_c8(dev_priv);
6483         mutex_unlock(&dev_priv->pc8.lock);
6484 }
6485
6486 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6487 {
6488         struct drm_device *dev = dev_priv->dev;
6489         struct intel_crtc *crtc;
6490         uint32_t val;
6491
6492         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6493                 if (crtc->base.enabled)
6494                         return false;
6495
6496         /* This case is still possible since we have the i915.disable_power_well
6497          * parameter and also the KVMr or something else might be requesting the
6498          * power well. */
6499         val = I915_READ(HSW_PWR_WELL_DRIVER);
6500         if (val != 0) {
6501                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6502                 return false;
6503         }
6504
6505         return true;
6506 }
6507
6508 /* Since we're called from modeset_global_resources there's no way to
6509  * symmetrically increase and decrease the refcount, so we use
6510  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6511  * or not.
6512  */
6513 static void hsw_update_package_c8(struct drm_device *dev)
6514 {
6515         struct drm_i915_private *dev_priv = dev->dev_private;
6516         bool allow;
6517
6518         if (!i915_enable_pc8)
6519                 return;
6520
6521         mutex_lock(&dev_priv->pc8.lock);
6522
6523         allow = hsw_can_enable_package_c8(dev_priv);
6524
6525         if (allow == dev_priv->pc8.requirements_met)
6526                 goto done;
6527
6528         dev_priv->pc8.requirements_met = allow;
6529
6530         if (allow)
6531                 __hsw_enable_package_c8(dev_priv);
6532         else
6533                 __hsw_disable_package_c8(dev_priv);
6534
6535 done:
6536         mutex_unlock(&dev_priv->pc8.lock);
6537 }
6538
6539 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6540 {
6541         if (!dev_priv->pc8.gpu_idle) {
6542                 dev_priv->pc8.gpu_idle = true;
6543                 hsw_enable_package_c8(dev_priv);
6544         }
6545 }
6546
6547 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6548 {
6549         if (dev_priv->pc8.gpu_idle) {
6550                 dev_priv->pc8.gpu_idle = false;
6551                 hsw_disable_package_c8(dev_priv);
6552         }
6553 }
6554
6555 static void haswell_modeset_global_resources(struct drm_device *dev)
6556 {
6557         bool enable = false;
6558         struct intel_crtc *crtc;
6559
6560         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6561                 if (!crtc->base.enabled)
6562                         continue;
6563
6564                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
6565                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6566                         enable = true;
6567         }
6568
6569         intel_set_power_well(dev, enable);
6570
6571         hsw_update_package_c8(dev);
6572 }
6573
6574 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6575                                  int x, int y,
6576                                  struct drm_framebuffer *fb)
6577 {
6578         struct drm_device *dev = crtc->dev;
6579         struct drm_i915_private *dev_priv = dev->dev_private;
6580         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6581         int plane = intel_crtc->plane;
6582         int ret;
6583
6584         if (!intel_ddi_pll_mode_set(crtc))
6585                 return -EINVAL;
6586
6587         if (intel_crtc->config.has_dp_encoder)
6588                 intel_dp_set_m_n(intel_crtc);
6589
6590         intel_crtc->lowfreq_avail = false;
6591
6592         intel_set_pipe_timings(intel_crtc);
6593
6594         if (intel_crtc->config.has_pch_encoder) {
6595                 intel_cpu_transcoder_set_m_n(intel_crtc,
6596                                              &intel_crtc->config.fdi_m_n);
6597         }
6598
6599         haswell_set_pipeconf(crtc);
6600
6601         intel_set_pipe_csc(crtc);
6602
6603         /* Set up the display plane register */
6604         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6605         POSTING_READ(DSPCNTR(plane));
6606
6607         ret = intel_pipe_set_base(crtc, x, y, fb);
6608
6609         return ret;
6610 }
6611
6612 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6613                                     struct intel_crtc_config *pipe_config)
6614 {
6615         struct drm_device *dev = crtc->base.dev;
6616         struct drm_i915_private *dev_priv = dev->dev_private;
6617         enum intel_display_power_domain pfit_domain;
6618         uint32_t tmp;
6619
6620         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6621         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6622
6623         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6624         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6625                 enum pipe trans_edp_pipe;
6626                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6627                 default:
6628                         WARN(1, "unknown pipe linked to edp transcoder\n");
6629                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6630                 case TRANS_DDI_EDP_INPUT_A_ON:
6631                         trans_edp_pipe = PIPE_A;
6632                         break;
6633                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6634                         trans_edp_pipe = PIPE_B;
6635                         break;
6636                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6637                         trans_edp_pipe = PIPE_C;
6638                         break;
6639                 }
6640
6641                 if (trans_edp_pipe == crtc->pipe)
6642                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6643         }
6644
6645         if (!intel_display_power_enabled(dev,
6646                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6647                 return false;
6648
6649         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6650         if (!(tmp & PIPECONF_ENABLE))
6651                 return false;
6652
6653         /*
6654          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6655          * DDI E. So just check whether this pipe is wired to DDI E and whether
6656          * the PCH transcoder is on.
6657          */
6658         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6659         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6660             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6661                 pipe_config->has_pch_encoder = true;
6662
6663                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6664                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6665                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6666
6667                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6668         }
6669
6670         intel_get_pipe_timings(crtc, pipe_config);
6671
6672         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6673         if (intel_display_power_enabled(dev, pfit_domain))
6674                 ironlake_get_pfit_config(crtc, pipe_config);
6675
6676         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6677                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6678
6679         pipe_config->pixel_multiplier = 1;
6680
6681         return true;
6682 }
6683
6684 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6685                                int x, int y,
6686                                struct drm_framebuffer *fb)
6687 {
6688         struct drm_device *dev = crtc->dev;
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         struct intel_encoder *encoder;
6691         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6692         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6693         int pipe = intel_crtc->pipe;
6694         int ret;
6695
6696         drm_vblank_pre_modeset(dev, pipe);
6697
6698         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6699
6700         drm_vblank_post_modeset(dev, pipe);
6701
6702         if (ret != 0)
6703                 return ret;
6704
6705         for_each_encoder_on_crtc(dev, crtc, encoder) {
6706                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6707                         encoder->base.base.id,
6708                         drm_get_encoder_name(&encoder->base),
6709                         mode->base.id, mode->name);
6710                 encoder->mode_set(encoder);
6711         }
6712
6713         return 0;
6714 }
6715
6716 static bool intel_eld_uptodate(struct drm_connector *connector,
6717                                int reg_eldv, uint32_t bits_eldv,
6718                                int reg_elda, uint32_t bits_elda,
6719                                int reg_edid)
6720 {
6721         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6722         uint8_t *eld = connector->eld;
6723         uint32_t i;
6724
6725         i = I915_READ(reg_eldv);
6726         i &= bits_eldv;
6727
6728         if (!eld[0])
6729                 return !i;
6730
6731         if (!i)
6732                 return false;
6733
6734         i = I915_READ(reg_elda);
6735         i &= ~bits_elda;
6736         I915_WRITE(reg_elda, i);
6737
6738         for (i = 0; i < eld[2]; i++)
6739                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6740                         return false;
6741
6742         return true;
6743 }
6744
6745 static void g4x_write_eld(struct drm_connector *connector,
6746                           struct drm_crtc *crtc)
6747 {
6748         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6749         uint8_t *eld = connector->eld;
6750         uint32_t eldv;
6751         uint32_t len;
6752         uint32_t i;
6753
6754         i = I915_READ(G4X_AUD_VID_DID);
6755
6756         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6757                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6758         else
6759                 eldv = G4X_ELDV_DEVCTG;
6760
6761         if (intel_eld_uptodate(connector,
6762                                G4X_AUD_CNTL_ST, eldv,
6763                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6764                                G4X_HDMIW_HDMIEDID))
6765                 return;
6766
6767         i = I915_READ(G4X_AUD_CNTL_ST);
6768         i &= ~(eldv | G4X_ELD_ADDR);
6769         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6770         I915_WRITE(G4X_AUD_CNTL_ST, i);
6771
6772         if (!eld[0])
6773                 return;
6774
6775         len = min_t(uint8_t, eld[2], len);
6776         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6777         for (i = 0; i < len; i++)
6778                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6779
6780         i = I915_READ(G4X_AUD_CNTL_ST);
6781         i |= eldv;
6782         I915_WRITE(G4X_AUD_CNTL_ST, i);
6783 }
6784
6785 static void haswell_write_eld(struct drm_connector *connector,
6786                                      struct drm_crtc *crtc)
6787 {
6788         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6789         uint8_t *eld = connector->eld;
6790         struct drm_device *dev = crtc->dev;
6791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6792         uint32_t eldv;
6793         uint32_t i;
6794         int len;
6795         int pipe = to_intel_crtc(crtc)->pipe;
6796         int tmp;
6797
6798         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6799         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6800         int aud_config = HSW_AUD_CFG(pipe);
6801         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6802
6803
6804         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6805
6806         /* Audio output enable */
6807         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6808         tmp = I915_READ(aud_cntrl_st2);
6809         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6810         I915_WRITE(aud_cntrl_st2, tmp);
6811
6812         /* Wait for 1 vertical blank */
6813         intel_wait_for_vblank(dev, pipe);
6814
6815         /* Set ELD valid state */
6816         tmp = I915_READ(aud_cntrl_st2);
6817         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6818         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6819         I915_WRITE(aud_cntrl_st2, tmp);
6820         tmp = I915_READ(aud_cntrl_st2);
6821         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6822
6823         /* Enable HDMI mode */
6824         tmp = I915_READ(aud_config);
6825         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6826         /* clear N_programing_enable and N_value_index */
6827         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6828         I915_WRITE(aud_config, tmp);
6829
6830         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6831
6832         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6833         intel_crtc->eld_vld = true;
6834
6835         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6836                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6837                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6838                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6839         } else
6840                 I915_WRITE(aud_config, 0);
6841
6842         if (intel_eld_uptodate(connector,
6843                                aud_cntrl_st2, eldv,
6844                                aud_cntl_st, IBX_ELD_ADDRESS,
6845                                hdmiw_hdmiedid))
6846                 return;
6847
6848         i = I915_READ(aud_cntrl_st2);
6849         i &= ~eldv;
6850         I915_WRITE(aud_cntrl_st2, i);
6851
6852         if (!eld[0])
6853                 return;
6854
6855         i = I915_READ(aud_cntl_st);
6856         i &= ~IBX_ELD_ADDRESS;
6857         I915_WRITE(aud_cntl_st, i);
6858         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6859         DRM_DEBUG_DRIVER("port num:%d\n", i);
6860
6861         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6862         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6863         for (i = 0; i < len; i++)
6864                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6865
6866         i = I915_READ(aud_cntrl_st2);
6867         i |= eldv;
6868         I915_WRITE(aud_cntrl_st2, i);
6869
6870 }
6871
6872 static void ironlake_write_eld(struct drm_connector *connector,
6873                                      struct drm_crtc *crtc)
6874 {
6875         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6876         uint8_t *eld = connector->eld;
6877         uint32_t eldv;
6878         uint32_t i;
6879         int len;
6880         int hdmiw_hdmiedid;
6881         int aud_config;
6882         int aud_cntl_st;
6883         int aud_cntrl_st2;
6884         int pipe = to_intel_crtc(crtc)->pipe;
6885
6886         if (HAS_PCH_IBX(connector->dev)) {
6887                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6888                 aud_config = IBX_AUD_CFG(pipe);
6889                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6890                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6891         } else {
6892                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6893                 aud_config = CPT_AUD_CFG(pipe);
6894                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6895                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6896         }
6897
6898         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6899
6900         i = I915_READ(aud_cntl_st);
6901         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6902         if (!i) {
6903                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6904                 /* operate blindly on all ports */
6905                 eldv = IBX_ELD_VALIDB;
6906                 eldv |= IBX_ELD_VALIDB << 4;
6907                 eldv |= IBX_ELD_VALIDB << 8;
6908         } else {
6909                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6910                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6911         }
6912
6913         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6914                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6915                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6916                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6917         } else
6918                 I915_WRITE(aud_config, 0);
6919
6920         if (intel_eld_uptodate(connector,
6921                                aud_cntrl_st2, eldv,
6922                                aud_cntl_st, IBX_ELD_ADDRESS,
6923                                hdmiw_hdmiedid))
6924                 return;
6925
6926         i = I915_READ(aud_cntrl_st2);
6927         i &= ~eldv;
6928         I915_WRITE(aud_cntrl_st2, i);
6929
6930         if (!eld[0])
6931                 return;
6932
6933         i = I915_READ(aud_cntl_st);
6934         i &= ~IBX_ELD_ADDRESS;
6935         I915_WRITE(aud_cntl_st, i);
6936
6937         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6938         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6939         for (i = 0; i < len; i++)
6940                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6941
6942         i = I915_READ(aud_cntrl_st2);
6943         i |= eldv;
6944         I915_WRITE(aud_cntrl_st2, i);
6945 }
6946
6947 void intel_write_eld(struct drm_encoder *encoder,
6948                      struct drm_display_mode *mode)
6949 {
6950         struct drm_crtc *crtc = encoder->crtc;
6951         struct drm_connector *connector;
6952         struct drm_device *dev = encoder->dev;
6953         struct drm_i915_private *dev_priv = dev->dev_private;
6954
6955         connector = drm_select_eld(encoder, mode);
6956         if (!connector)
6957                 return;
6958
6959         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6960                          connector->base.id,
6961                          drm_get_connector_name(connector),
6962                          connector->encoder->base.id,
6963                          drm_get_encoder_name(connector->encoder));
6964
6965         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6966
6967         if (dev_priv->display.write_eld)
6968                 dev_priv->display.write_eld(connector, crtc);
6969 }
6970
6971 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6972 {
6973         struct drm_device *dev = crtc->dev;
6974         struct drm_i915_private *dev_priv = dev->dev_private;
6975         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6976         bool visible = base != 0;
6977         u32 cntl;
6978
6979         if (intel_crtc->cursor_visible == visible)
6980                 return;
6981
6982         cntl = I915_READ(_CURACNTR);
6983         if (visible) {
6984                 /* On these chipsets we can only modify the base whilst
6985                  * the cursor is disabled.
6986                  */
6987                 I915_WRITE(_CURABASE, base);
6988
6989                 cntl &= ~(CURSOR_FORMAT_MASK);
6990                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6991                 cntl |= CURSOR_ENABLE |
6992                         CURSOR_GAMMA_ENABLE |
6993                         CURSOR_FORMAT_ARGB;
6994         } else
6995                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6996         I915_WRITE(_CURACNTR, cntl);
6997
6998         intel_crtc->cursor_visible = visible;
6999 }
7000
7001 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7002 {
7003         struct drm_device *dev = crtc->dev;
7004         struct drm_i915_private *dev_priv = dev->dev_private;
7005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006         int pipe = intel_crtc->pipe;
7007         bool visible = base != 0;
7008
7009         if (intel_crtc->cursor_visible != visible) {
7010                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7011                 if (base) {
7012                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7013                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7014                         cntl |= pipe << 28; /* Connect to correct pipe */
7015                 } else {
7016                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7017                         cntl |= CURSOR_MODE_DISABLE;
7018                 }
7019                 I915_WRITE(CURCNTR(pipe), cntl);
7020
7021                 intel_crtc->cursor_visible = visible;
7022         }
7023         /* and commit changes on next vblank */
7024         I915_WRITE(CURBASE(pipe), base);
7025 }
7026
7027 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7028 {
7029         struct drm_device *dev = crtc->dev;
7030         struct drm_i915_private *dev_priv = dev->dev_private;
7031         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7032         int pipe = intel_crtc->pipe;
7033         bool visible = base != 0;
7034
7035         if (intel_crtc->cursor_visible != visible) {
7036                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7037                 if (base) {
7038                         cntl &= ~CURSOR_MODE;
7039                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7040                 } else {
7041                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7042                         cntl |= CURSOR_MODE_DISABLE;
7043                 }
7044                 if (IS_HASWELL(dev)) {
7045                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7046                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7047                 }
7048                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7049
7050                 intel_crtc->cursor_visible = visible;
7051         }
7052         /* and commit changes on next vblank */
7053         I915_WRITE(CURBASE_IVB(pipe), base);
7054 }
7055
7056 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7057 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7058                                      bool on)
7059 {
7060         struct drm_device *dev = crtc->dev;
7061         struct drm_i915_private *dev_priv = dev->dev_private;
7062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7063         int pipe = intel_crtc->pipe;
7064         int x = intel_crtc->cursor_x;
7065         int y = intel_crtc->cursor_y;
7066         u32 base = 0, pos = 0;
7067         bool visible;
7068
7069         if (on)
7070                 base = intel_crtc->cursor_addr;
7071
7072         if (x >= intel_crtc->config.pipe_src_w)
7073                 base = 0;
7074
7075         if (y >= intel_crtc->config.pipe_src_h)
7076                 base = 0;
7077
7078         if (x < 0) {
7079                 if (x + intel_crtc->cursor_width <= 0)
7080                         base = 0;
7081
7082                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7083                 x = -x;
7084         }
7085         pos |= x << CURSOR_X_SHIFT;
7086
7087         if (y < 0) {
7088                 if (y + intel_crtc->cursor_height <= 0)
7089                         base = 0;
7090
7091                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7092                 y = -y;
7093         }
7094         pos |= y << CURSOR_Y_SHIFT;
7095
7096         visible = base != 0;
7097         if (!visible && !intel_crtc->cursor_visible)
7098                 return;
7099
7100         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7101                 I915_WRITE(CURPOS_IVB(pipe), pos);
7102                 ivb_update_cursor(crtc, base);
7103         } else {
7104                 I915_WRITE(CURPOS(pipe), pos);
7105                 if (IS_845G(dev) || IS_I865G(dev))
7106                         i845_update_cursor(crtc, base);
7107                 else
7108                         i9xx_update_cursor(crtc, base);
7109         }
7110 }
7111
7112 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7113                                  struct drm_file *file,
7114                                  uint32_t handle,
7115                                  uint32_t width, uint32_t height)
7116 {
7117         struct drm_device *dev = crtc->dev;
7118         struct drm_i915_private *dev_priv = dev->dev_private;
7119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7120         struct drm_i915_gem_object *obj;
7121         uint32_t addr;
7122         int ret;
7123
7124         /* if we want to turn off the cursor ignore width and height */
7125         if (!handle) {
7126                 DRM_DEBUG_KMS("cursor off\n");
7127                 addr = 0;
7128                 obj = NULL;
7129                 mutex_lock(&dev->struct_mutex);
7130                 goto finish;
7131         }
7132
7133         /* Currently we only support 64x64 cursors */
7134         if (width != 64 || height != 64) {
7135                 DRM_ERROR("we currently only support 64x64 cursors\n");
7136                 return -EINVAL;
7137         }
7138
7139         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7140         if (&obj->base == NULL)
7141                 return -ENOENT;
7142
7143         if (obj->base.size < width * height * 4) {
7144                 DRM_ERROR("buffer is to small\n");
7145                 ret = -ENOMEM;
7146                 goto fail;
7147         }
7148
7149         /* we only need to pin inside GTT if cursor is non-phy */
7150         mutex_lock(&dev->struct_mutex);
7151         if (!dev_priv->info->cursor_needs_physical) {
7152                 unsigned alignment;
7153
7154                 if (obj->tiling_mode) {
7155                         DRM_ERROR("cursor cannot be tiled\n");
7156                         ret = -EINVAL;
7157                         goto fail_locked;
7158                 }
7159
7160                 /* Note that the w/a also requires 2 PTE of padding following
7161                  * the bo. We currently fill all unused PTE with the shadow
7162                  * page and so we should always have valid PTE following the
7163                  * cursor preventing the VT-d warning.
7164                  */
7165                 alignment = 0;
7166                 if (need_vtd_wa(dev))
7167                         alignment = 64*1024;
7168
7169                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7170                 if (ret) {
7171                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7172                         goto fail_locked;
7173                 }
7174
7175                 ret = i915_gem_object_put_fence(obj);
7176                 if (ret) {
7177                         DRM_ERROR("failed to release fence for cursor");
7178                         goto fail_unpin;
7179                 }
7180
7181                 addr = i915_gem_obj_ggtt_offset(obj);
7182         } else {
7183                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7184                 ret = i915_gem_attach_phys_object(dev, obj,
7185                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7186                                                   align);
7187                 if (ret) {
7188                         DRM_ERROR("failed to attach phys object\n");
7189                         goto fail_locked;
7190                 }
7191                 addr = obj->phys_obj->handle->busaddr;
7192         }
7193
7194         if (IS_GEN2(dev))
7195                 I915_WRITE(CURSIZE, (height << 12) | width);
7196
7197  finish:
7198         if (intel_crtc->cursor_bo) {
7199                 if (dev_priv->info->cursor_needs_physical) {
7200                         if (intel_crtc->cursor_bo != obj)
7201                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7202                 } else
7203                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7204                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7205         }
7206
7207         mutex_unlock(&dev->struct_mutex);
7208
7209         intel_crtc->cursor_addr = addr;
7210         intel_crtc->cursor_bo = obj;
7211         intel_crtc->cursor_width = width;
7212         intel_crtc->cursor_height = height;
7213
7214         if (intel_crtc->active)
7215                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7216
7217         return 0;
7218 fail_unpin:
7219         i915_gem_object_unpin_from_display_plane(obj);
7220 fail_locked:
7221         mutex_unlock(&dev->struct_mutex);
7222 fail:
7223         drm_gem_object_unreference_unlocked(&obj->base);
7224         return ret;
7225 }
7226
7227 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7228 {
7229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7230
7231         intel_crtc->cursor_x = x;
7232         intel_crtc->cursor_y = y;
7233
7234         if (intel_crtc->active)
7235                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7236
7237         return 0;
7238 }
7239
7240 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7241                                  u16 *blue, uint32_t start, uint32_t size)
7242 {
7243         int end = (start + size > 256) ? 256 : start + size, i;
7244         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7245
7246         for (i = start; i < end; i++) {
7247                 intel_crtc->lut_r[i] = red[i] >> 8;
7248                 intel_crtc->lut_g[i] = green[i] >> 8;
7249                 intel_crtc->lut_b[i] = blue[i] >> 8;
7250         }
7251
7252         intel_crtc_load_lut(crtc);
7253 }
7254
7255 /* VESA 640x480x72Hz mode to set on the pipe */
7256 static struct drm_display_mode load_detect_mode = {
7257         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7258                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7259 };
7260
7261 static struct drm_framebuffer *
7262 intel_framebuffer_create(struct drm_device *dev,
7263                          struct drm_mode_fb_cmd2 *mode_cmd,
7264                          struct drm_i915_gem_object *obj)
7265 {
7266         struct intel_framebuffer *intel_fb;
7267         int ret;
7268
7269         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7270         if (!intel_fb) {
7271                 drm_gem_object_unreference_unlocked(&obj->base);
7272                 return ERR_PTR(-ENOMEM);
7273         }
7274
7275         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7276         if (ret) {
7277                 drm_gem_object_unreference_unlocked(&obj->base);
7278                 kfree(intel_fb);
7279                 return ERR_PTR(ret);
7280         }
7281
7282         return &intel_fb->base;
7283 }
7284
7285 static u32
7286 intel_framebuffer_pitch_for_width(int width, int bpp)
7287 {
7288         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7289         return ALIGN(pitch, 64);
7290 }
7291
7292 static u32
7293 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7294 {
7295         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7296         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7297 }
7298
7299 static struct drm_framebuffer *
7300 intel_framebuffer_create_for_mode(struct drm_device *dev,
7301                                   struct drm_display_mode *mode,
7302                                   int depth, int bpp)
7303 {
7304         struct drm_i915_gem_object *obj;
7305         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7306
7307         obj = i915_gem_alloc_object(dev,
7308                                     intel_framebuffer_size_for_mode(mode, bpp));
7309         if (obj == NULL)
7310                 return ERR_PTR(-ENOMEM);
7311
7312         mode_cmd.width = mode->hdisplay;
7313         mode_cmd.height = mode->vdisplay;
7314         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7315                                                                 bpp);
7316         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7317
7318         return intel_framebuffer_create(dev, &mode_cmd, obj);
7319 }
7320
7321 static struct drm_framebuffer *
7322 mode_fits_in_fbdev(struct drm_device *dev,
7323                    struct drm_display_mode *mode)
7324 {
7325         struct drm_i915_private *dev_priv = dev->dev_private;
7326         struct drm_i915_gem_object *obj;
7327         struct drm_framebuffer *fb;
7328
7329         if (dev_priv->fbdev == NULL)
7330                 return NULL;
7331
7332         obj = dev_priv->fbdev->ifb.obj;
7333         if (obj == NULL)
7334                 return NULL;
7335
7336         fb = &dev_priv->fbdev->ifb.base;
7337         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7338                                                                fb->bits_per_pixel))
7339                 return NULL;
7340
7341         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7342                 return NULL;
7343
7344         return fb;
7345 }
7346
7347 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7348                                 struct drm_display_mode *mode,
7349                                 struct intel_load_detect_pipe *old)
7350 {
7351         struct intel_crtc *intel_crtc;
7352         struct intel_encoder *intel_encoder =
7353                 intel_attached_encoder(connector);
7354         struct drm_crtc *possible_crtc;
7355         struct drm_encoder *encoder = &intel_encoder->base;
7356         struct drm_crtc *crtc = NULL;
7357         struct drm_device *dev = encoder->dev;
7358         struct drm_framebuffer *fb;
7359         int i = -1;
7360
7361         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7362                       connector->base.id, drm_get_connector_name(connector),
7363                       encoder->base.id, drm_get_encoder_name(encoder));
7364
7365         /*
7366          * Algorithm gets a little messy:
7367          *
7368          *   - if the connector already has an assigned crtc, use it (but make
7369          *     sure it's on first)
7370          *
7371          *   - try to find the first unused crtc that can drive this connector,
7372          *     and use that if we find one
7373          */
7374
7375         /* See if we already have a CRTC for this connector */
7376         if (encoder->crtc) {
7377                 crtc = encoder->crtc;
7378
7379                 mutex_lock(&crtc->mutex);
7380
7381                 old->dpms_mode = connector->dpms;
7382                 old->load_detect_temp = false;
7383
7384                 /* Make sure the crtc and connector are running */
7385                 if (connector->dpms != DRM_MODE_DPMS_ON)
7386                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7387
7388                 return true;
7389         }
7390
7391         /* Find an unused one (if possible) */
7392         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7393                 i++;
7394                 if (!(encoder->possible_crtcs & (1 << i)))
7395                         continue;
7396                 if (!possible_crtc->enabled) {
7397                         crtc = possible_crtc;
7398                         break;
7399                 }
7400         }
7401
7402         /*
7403          * If we didn't find an unused CRTC, don't use any.
7404          */
7405         if (!crtc) {
7406                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7407                 return false;
7408         }
7409
7410         mutex_lock(&crtc->mutex);
7411         intel_encoder->new_crtc = to_intel_crtc(crtc);
7412         to_intel_connector(connector)->new_encoder = intel_encoder;
7413
7414         intel_crtc = to_intel_crtc(crtc);
7415         old->dpms_mode = connector->dpms;
7416         old->load_detect_temp = true;
7417         old->release_fb = NULL;
7418
7419         if (!mode)
7420                 mode = &load_detect_mode;
7421
7422         /* We need a framebuffer large enough to accommodate all accesses
7423          * that the plane may generate whilst we perform load detection.
7424          * We can not rely on the fbcon either being present (we get called
7425          * during its initialisation to detect all boot displays, or it may
7426          * not even exist) or that it is large enough to satisfy the
7427          * requested mode.
7428          */
7429         fb = mode_fits_in_fbdev(dev, mode);
7430         if (fb == NULL) {
7431                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7432                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7433                 old->release_fb = fb;
7434         } else
7435                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7436         if (IS_ERR(fb)) {
7437                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7438                 mutex_unlock(&crtc->mutex);
7439                 return false;
7440         }
7441
7442         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7443                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7444                 if (old->release_fb)
7445                         old->release_fb->funcs->destroy(old->release_fb);
7446                 mutex_unlock(&crtc->mutex);
7447                 return false;
7448         }
7449
7450         /* let the connector get through one full cycle before testing */
7451         intel_wait_for_vblank(dev, intel_crtc->pipe);
7452         return true;
7453 }
7454
7455 void intel_release_load_detect_pipe(struct drm_connector *connector,
7456                                     struct intel_load_detect_pipe *old)
7457 {
7458         struct intel_encoder *intel_encoder =
7459                 intel_attached_encoder(connector);
7460         struct drm_encoder *encoder = &intel_encoder->base;
7461         struct drm_crtc *crtc = encoder->crtc;
7462
7463         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7464                       connector->base.id, drm_get_connector_name(connector),
7465                       encoder->base.id, drm_get_encoder_name(encoder));
7466
7467         if (old->load_detect_temp) {
7468                 to_intel_connector(connector)->new_encoder = NULL;
7469                 intel_encoder->new_crtc = NULL;
7470                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7471
7472                 if (old->release_fb) {
7473                         drm_framebuffer_unregister_private(old->release_fb);
7474                         drm_framebuffer_unreference(old->release_fb);
7475                 }
7476
7477                 mutex_unlock(&crtc->mutex);
7478                 return;
7479         }
7480
7481         /* Switch crtc and encoder back off if necessary */
7482         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7483                 connector->funcs->dpms(connector, old->dpms_mode);
7484
7485         mutex_unlock(&crtc->mutex);
7486 }
7487
7488 static int i9xx_pll_refclk(struct drm_device *dev,
7489                            const struct intel_crtc_config *pipe_config)
7490 {
7491         struct drm_i915_private *dev_priv = dev->dev_private;
7492         u32 dpll = pipe_config->dpll_hw_state.dpll;
7493
7494         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7495                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7496         else if (HAS_PCH_SPLIT(dev))
7497                 return 120000;
7498         else if (!IS_GEN2(dev))
7499                 return 96000;
7500         else
7501                 return 48000;
7502 }
7503
7504 /* Returns the clock of the currently programmed mode of the given pipe. */
7505 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7506                                 struct intel_crtc_config *pipe_config)
7507 {
7508         struct drm_device *dev = crtc->base.dev;
7509         struct drm_i915_private *dev_priv = dev->dev_private;
7510         int pipe = pipe_config->cpu_transcoder;
7511         u32 dpll = pipe_config->dpll_hw_state.dpll;
7512         u32 fp;
7513         intel_clock_t clock;
7514         int refclk = i9xx_pll_refclk(dev, pipe_config);
7515
7516         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7517                 fp = pipe_config->dpll_hw_state.fp0;
7518         else
7519                 fp = pipe_config->dpll_hw_state.fp1;
7520
7521         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7522         if (IS_PINEVIEW(dev)) {
7523                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7524                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7525         } else {
7526                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7527                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7528         }
7529
7530         if (!IS_GEN2(dev)) {
7531                 if (IS_PINEVIEW(dev))
7532                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7533                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7534                 else
7535                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7536                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7537
7538                 switch (dpll & DPLL_MODE_MASK) {
7539                 case DPLLB_MODE_DAC_SERIAL:
7540                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7541                                 5 : 10;
7542                         break;
7543                 case DPLLB_MODE_LVDS:
7544                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7545                                 7 : 14;
7546                         break;
7547                 default:
7548                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7549                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7550                         return;
7551                 }
7552
7553                 if (IS_PINEVIEW(dev))
7554                         pineview_clock(refclk, &clock);
7555                 else
7556                         i9xx_clock(refclk, &clock);
7557         } else {
7558                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7559
7560                 if (is_lvds) {
7561                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7562                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7563                         clock.p2 = 14;
7564                 } else {
7565                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7566                                 clock.p1 = 2;
7567                         else {
7568                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7569                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7570                         }
7571                         if (dpll & PLL_P2_DIVIDE_BY_4)
7572                                 clock.p2 = 4;
7573                         else
7574                                 clock.p2 = 2;
7575                 }
7576
7577                 i9xx_clock(refclk, &clock);
7578         }
7579
7580         /*
7581          * This value includes pixel_multiplier. We will use
7582          * port_clock to compute adjusted_mode.crtc_clock in the
7583          * encoder's get_config() function.
7584          */
7585         pipe_config->port_clock = clock.dot;
7586 }
7587
7588 int intel_dotclock_calculate(int link_freq,
7589                              const struct intel_link_m_n *m_n)
7590 {
7591         /*
7592          * The calculation for the data clock is:
7593          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7594          * But we want to avoid losing precison if possible, so:
7595          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7596          *
7597          * and the link clock is simpler:
7598          * link_clock = (m * link_clock) / n
7599          */
7600
7601         if (!m_n->link_n)
7602                 return 0;
7603
7604         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7605 }
7606
7607 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7608                                    struct intel_crtc_config *pipe_config)
7609 {
7610         struct drm_device *dev = crtc->base.dev;
7611
7612         /* read out port_clock from the DPLL */
7613         i9xx_crtc_clock_get(crtc, pipe_config);
7614
7615         /*
7616          * This value does not include pixel_multiplier.
7617          * We will check that port_clock and adjusted_mode.crtc_clock
7618          * agree once we know their relationship in the encoder's
7619          * get_config() function.
7620          */
7621         pipe_config->adjusted_mode.crtc_clock =
7622                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7623                                          &pipe_config->fdi_m_n);
7624 }
7625
7626 /** Returns the currently programmed mode of the given pipe. */
7627 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7628                                              struct drm_crtc *crtc)
7629 {
7630         struct drm_i915_private *dev_priv = dev->dev_private;
7631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7632         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7633         struct drm_display_mode *mode;
7634         struct intel_crtc_config pipe_config;
7635         int htot = I915_READ(HTOTAL(cpu_transcoder));
7636         int hsync = I915_READ(HSYNC(cpu_transcoder));
7637         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7638         int vsync = I915_READ(VSYNC(cpu_transcoder));
7639         enum pipe pipe = intel_crtc->pipe;
7640
7641         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7642         if (!mode)
7643                 return NULL;
7644
7645         /*
7646          * Construct a pipe_config sufficient for getting the clock info
7647          * back out of crtc_clock_get.
7648          *
7649          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7650          * to use a real value here instead.
7651          */
7652         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7653         pipe_config.pixel_multiplier = 1;
7654         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7655         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7656         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7657         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7658
7659         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7660         mode->hdisplay = (htot & 0xffff) + 1;
7661         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7662         mode->hsync_start = (hsync & 0xffff) + 1;
7663         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7664         mode->vdisplay = (vtot & 0xffff) + 1;
7665         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7666         mode->vsync_start = (vsync & 0xffff) + 1;
7667         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7668
7669         drm_mode_set_name(mode);
7670
7671         return mode;
7672 }
7673
7674 static void intel_increase_pllclock(struct drm_crtc *crtc)
7675 {
7676         struct drm_device *dev = crtc->dev;
7677         drm_i915_private_t *dev_priv = dev->dev_private;
7678         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7679         int pipe = intel_crtc->pipe;
7680         int dpll_reg = DPLL(pipe);
7681         int dpll;
7682
7683         if (HAS_PCH_SPLIT(dev))
7684                 return;
7685
7686         if (!dev_priv->lvds_downclock_avail)
7687                 return;
7688
7689         dpll = I915_READ(dpll_reg);
7690         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7691                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7692
7693                 assert_panel_unlocked(dev_priv, pipe);
7694
7695                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7696                 I915_WRITE(dpll_reg, dpll);
7697                 intel_wait_for_vblank(dev, pipe);
7698
7699                 dpll = I915_READ(dpll_reg);
7700                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7701                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7702         }
7703 }
7704
7705 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7706 {
7707         struct drm_device *dev = crtc->dev;
7708         drm_i915_private_t *dev_priv = dev->dev_private;
7709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7710
7711         if (HAS_PCH_SPLIT(dev))
7712                 return;
7713
7714         if (!dev_priv->lvds_downclock_avail)
7715                 return;
7716
7717         /*
7718          * Since this is called by a timer, we should never get here in
7719          * the manual case.
7720          */
7721         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7722                 int pipe = intel_crtc->pipe;
7723                 int dpll_reg = DPLL(pipe);
7724                 int dpll;
7725
7726                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7727
7728                 assert_panel_unlocked(dev_priv, pipe);
7729
7730                 dpll = I915_READ(dpll_reg);
7731                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7732                 I915_WRITE(dpll_reg, dpll);
7733                 intel_wait_for_vblank(dev, pipe);
7734                 dpll = I915_READ(dpll_reg);
7735                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7736                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7737         }
7738
7739 }
7740
7741 void intel_mark_busy(struct drm_device *dev)
7742 {
7743         struct drm_i915_private *dev_priv = dev->dev_private;
7744
7745         hsw_package_c8_gpu_busy(dev_priv);
7746         i915_update_gfx_val(dev_priv);
7747 }
7748
7749 void intel_mark_idle(struct drm_device *dev)
7750 {
7751         struct drm_i915_private *dev_priv = dev->dev_private;
7752         struct drm_crtc *crtc;
7753
7754         hsw_package_c8_gpu_idle(dev_priv);
7755
7756         if (!i915_powersave)
7757                 return;
7758
7759         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7760                 if (!crtc->fb)
7761                         continue;
7762
7763                 intel_decrease_pllclock(crtc);
7764         }
7765
7766         if (dev_priv->info->gen >= 6)
7767                 gen6_rps_idle(dev->dev_private);
7768 }
7769
7770 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7771                         struct intel_ring_buffer *ring)
7772 {
7773         struct drm_device *dev = obj->base.dev;
7774         struct drm_crtc *crtc;
7775
7776         if (!i915_powersave)
7777                 return;
7778
7779         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7780                 if (!crtc->fb)
7781                         continue;
7782
7783                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7784                         continue;
7785
7786                 intel_increase_pllclock(crtc);
7787                 if (ring && intel_fbc_enabled(dev))
7788                         ring->fbc_dirty = true;
7789         }
7790 }
7791
7792 static void intel_crtc_destroy(struct drm_crtc *crtc)
7793 {
7794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7795         struct drm_device *dev = crtc->dev;
7796         struct intel_unpin_work *work;
7797         unsigned long flags;
7798
7799         spin_lock_irqsave(&dev->event_lock, flags);
7800         work = intel_crtc->unpin_work;
7801         intel_crtc->unpin_work = NULL;
7802         spin_unlock_irqrestore(&dev->event_lock, flags);
7803
7804         if (work) {
7805                 cancel_work_sync(&work->work);
7806                 kfree(work);
7807         }
7808
7809         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7810
7811         drm_crtc_cleanup(crtc);
7812
7813         kfree(intel_crtc);
7814 }
7815
7816 static void intel_unpin_work_fn(struct work_struct *__work)
7817 {
7818         struct intel_unpin_work *work =
7819                 container_of(__work, struct intel_unpin_work, work);
7820         struct drm_device *dev = work->crtc->dev;
7821
7822         mutex_lock(&dev->struct_mutex);
7823         intel_unpin_fb_obj(work->old_fb_obj);
7824         drm_gem_object_unreference(&work->pending_flip_obj->base);
7825         drm_gem_object_unreference(&work->old_fb_obj->base);
7826
7827         intel_update_fbc(dev);
7828         mutex_unlock(&dev->struct_mutex);
7829
7830         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7831         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7832
7833         kfree(work);
7834 }
7835
7836 static void do_intel_finish_page_flip(struct drm_device *dev,
7837                                       struct drm_crtc *crtc)
7838 {
7839         drm_i915_private_t *dev_priv = dev->dev_private;
7840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7841         struct intel_unpin_work *work;
7842         unsigned long flags;
7843
7844         /* Ignore early vblank irqs */
7845         if (intel_crtc == NULL)
7846                 return;
7847
7848         spin_lock_irqsave(&dev->event_lock, flags);
7849         work = intel_crtc->unpin_work;
7850
7851         /* Ensure we don't miss a work->pending update ... */
7852         smp_rmb();
7853
7854         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7855                 spin_unlock_irqrestore(&dev->event_lock, flags);
7856                 return;
7857         }
7858
7859         /* and that the unpin work is consistent wrt ->pending. */
7860         smp_rmb();
7861
7862         intel_crtc->unpin_work = NULL;
7863
7864         if (work->event)
7865                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7866
7867         drm_vblank_put(dev, intel_crtc->pipe);
7868
7869         spin_unlock_irqrestore(&dev->event_lock, flags);
7870
7871         wake_up_all(&dev_priv->pending_flip_queue);
7872
7873         queue_work(dev_priv->wq, &work->work);
7874
7875         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7876 }
7877
7878 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7879 {
7880         drm_i915_private_t *dev_priv = dev->dev_private;
7881         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7882
7883         do_intel_finish_page_flip(dev, crtc);
7884 }
7885
7886 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7887 {
7888         drm_i915_private_t *dev_priv = dev->dev_private;
7889         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7890
7891         do_intel_finish_page_flip(dev, crtc);
7892 }
7893
7894 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7895 {
7896         drm_i915_private_t *dev_priv = dev->dev_private;
7897         struct intel_crtc *intel_crtc =
7898                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7899         unsigned long flags;
7900
7901         /* NB: An MMIO update of the plane base pointer will also
7902          * generate a page-flip completion irq, i.e. every modeset
7903          * is also accompanied by a spurious intel_prepare_page_flip().
7904          */
7905         spin_lock_irqsave(&dev->event_lock, flags);
7906         if (intel_crtc->unpin_work)
7907                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7908         spin_unlock_irqrestore(&dev->event_lock, flags);
7909 }
7910
7911 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7912 {
7913         /* Ensure that the work item is consistent when activating it ... */
7914         smp_wmb();
7915         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7916         /* and that it is marked active as soon as the irq could fire. */
7917         smp_wmb();
7918 }
7919
7920 static int intel_gen2_queue_flip(struct drm_device *dev,
7921                                  struct drm_crtc *crtc,
7922                                  struct drm_framebuffer *fb,
7923                                  struct drm_i915_gem_object *obj,
7924                                  uint32_t flags)
7925 {
7926         struct drm_i915_private *dev_priv = dev->dev_private;
7927         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7928         u32 flip_mask;
7929         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7930         int ret;
7931
7932         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7933         if (ret)
7934                 goto err;
7935
7936         ret = intel_ring_begin(ring, 6);
7937         if (ret)
7938                 goto err_unpin;
7939
7940         /* Can't queue multiple flips, so wait for the previous
7941          * one to finish before executing the next.
7942          */
7943         if (intel_crtc->plane)
7944                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7945         else
7946                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7947         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7948         intel_ring_emit(ring, MI_NOOP);
7949         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7950                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7951         intel_ring_emit(ring, fb->pitches[0]);
7952         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7953         intel_ring_emit(ring, 0); /* aux display base address, unused */
7954
7955         intel_mark_page_flip_active(intel_crtc);
7956         __intel_ring_advance(ring);
7957         return 0;
7958
7959 err_unpin:
7960         intel_unpin_fb_obj(obj);
7961 err:
7962         return ret;
7963 }
7964
7965 static int intel_gen3_queue_flip(struct drm_device *dev,
7966                                  struct drm_crtc *crtc,
7967                                  struct drm_framebuffer *fb,
7968                                  struct drm_i915_gem_object *obj,
7969                                  uint32_t flags)
7970 {
7971         struct drm_i915_private *dev_priv = dev->dev_private;
7972         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7973         u32 flip_mask;
7974         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7975         int ret;
7976
7977         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7978         if (ret)
7979                 goto err;
7980
7981         ret = intel_ring_begin(ring, 6);
7982         if (ret)
7983                 goto err_unpin;
7984
7985         if (intel_crtc->plane)
7986                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7987         else
7988                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7989         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7990         intel_ring_emit(ring, MI_NOOP);
7991         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7992                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7993         intel_ring_emit(ring, fb->pitches[0]);
7994         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7995         intel_ring_emit(ring, MI_NOOP);
7996
7997         intel_mark_page_flip_active(intel_crtc);
7998         __intel_ring_advance(ring);
7999         return 0;
8000
8001 err_unpin:
8002         intel_unpin_fb_obj(obj);
8003 err:
8004         return ret;
8005 }
8006
8007 static int intel_gen4_queue_flip(struct drm_device *dev,
8008                                  struct drm_crtc *crtc,
8009                                  struct drm_framebuffer *fb,
8010                                  struct drm_i915_gem_object *obj,
8011                                  uint32_t flags)
8012 {
8013         struct drm_i915_private *dev_priv = dev->dev_private;
8014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8015         uint32_t pf, pipesrc;
8016         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8017         int ret;
8018
8019         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8020         if (ret)
8021                 goto err;
8022
8023         ret = intel_ring_begin(ring, 4);
8024         if (ret)
8025                 goto err_unpin;
8026
8027         /* i965+ uses the linear or tiled offsets from the
8028          * Display Registers (which do not change across a page-flip)
8029          * so we need only reprogram the base address.
8030          */
8031         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8032                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8033         intel_ring_emit(ring, fb->pitches[0]);
8034         intel_ring_emit(ring,
8035                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8036                         obj->tiling_mode);
8037
8038         /* XXX Enabling the panel-fitter across page-flip is so far
8039          * untested on non-native modes, so ignore it for now.
8040          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8041          */
8042         pf = 0;
8043         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8044         intel_ring_emit(ring, pf | pipesrc);
8045
8046         intel_mark_page_flip_active(intel_crtc);
8047         __intel_ring_advance(ring);
8048         return 0;
8049
8050 err_unpin:
8051         intel_unpin_fb_obj(obj);
8052 err:
8053         return ret;
8054 }
8055
8056 static int intel_gen6_queue_flip(struct drm_device *dev,
8057                                  struct drm_crtc *crtc,
8058                                  struct drm_framebuffer *fb,
8059                                  struct drm_i915_gem_object *obj,
8060                                  uint32_t flags)
8061 {
8062         struct drm_i915_private *dev_priv = dev->dev_private;
8063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8064         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8065         uint32_t pf, pipesrc;
8066         int ret;
8067
8068         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8069         if (ret)
8070                 goto err;
8071
8072         ret = intel_ring_begin(ring, 4);
8073         if (ret)
8074                 goto err_unpin;
8075
8076         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8077                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8078         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8079         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8080
8081         /* Contrary to the suggestions in the documentation,
8082          * "Enable Panel Fitter" does not seem to be required when page
8083          * flipping with a non-native mode, and worse causes a normal
8084          * modeset to fail.
8085          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8086          */
8087         pf = 0;
8088         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8089         intel_ring_emit(ring, pf | pipesrc);
8090
8091         intel_mark_page_flip_active(intel_crtc);
8092         __intel_ring_advance(ring);
8093         return 0;
8094
8095 err_unpin:
8096         intel_unpin_fb_obj(obj);
8097 err:
8098         return ret;
8099 }
8100
8101 static int intel_gen7_queue_flip(struct drm_device *dev,
8102                                  struct drm_crtc *crtc,
8103                                  struct drm_framebuffer *fb,
8104                                  struct drm_i915_gem_object *obj,
8105                                  uint32_t flags)
8106 {
8107         struct drm_i915_private *dev_priv = dev->dev_private;
8108         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8109         struct intel_ring_buffer *ring;
8110         uint32_t plane_bit = 0;
8111         int len, ret;
8112
8113         ring = obj->ring;
8114         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8115                 ring = &dev_priv->ring[BCS];
8116
8117         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8118         if (ret)
8119                 goto err;
8120
8121         switch(intel_crtc->plane) {
8122         case PLANE_A:
8123                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8124                 break;
8125         case PLANE_B:
8126                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8127                 break;
8128         case PLANE_C:
8129                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8130                 break;
8131         default:
8132                 WARN_ONCE(1, "unknown plane in flip command\n");
8133                 ret = -ENODEV;
8134                 goto err_unpin;
8135         }
8136
8137         len = 4;
8138         if (ring->id == RCS)
8139                 len += 6;
8140
8141         ret = intel_ring_begin(ring, len);
8142         if (ret)
8143                 goto err_unpin;
8144
8145         /* Unmask the flip-done completion message. Note that the bspec says that
8146          * we should do this for both the BCS and RCS, and that we must not unmask
8147          * more than one flip event at any time (or ensure that one flip message
8148          * can be sent by waiting for flip-done prior to queueing new flips).
8149          * Experimentation says that BCS works despite DERRMR masking all
8150          * flip-done completion events and that unmasking all planes at once
8151          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8152          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8153          */
8154         if (ring->id == RCS) {
8155                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8156                 intel_ring_emit(ring, DERRMR);
8157                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8158                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8159                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8160                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8161                 intel_ring_emit(ring, DERRMR);
8162                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8163         }
8164
8165         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8166         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8167         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8168         intel_ring_emit(ring, (MI_NOOP));
8169
8170         intel_mark_page_flip_active(intel_crtc);
8171         __intel_ring_advance(ring);
8172         return 0;
8173
8174 err_unpin:
8175         intel_unpin_fb_obj(obj);
8176 err:
8177         return ret;
8178 }
8179
8180 static int intel_default_queue_flip(struct drm_device *dev,
8181                                     struct drm_crtc *crtc,
8182                                     struct drm_framebuffer *fb,
8183                                     struct drm_i915_gem_object *obj,
8184                                     uint32_t flags)
8185 {
8186         return -ENODEV;
8187 }
8188
8189 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8190                                 struct drm_framebuffer *fb,
8191                                 struct drm_pending_vblank_event *event,
8192                                 uint32_t page_flip_flags)
8193 {
8194         struct drm_device *dev = crtc->dev;
8195         struct drm_i915_private *dev_priv = dev->dev_private;
8196         struct drm_framebuffer *old_fb = crtc->fb;
8197         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8199         struct intel_unpin_work *work;
8200         unsigned long flags;
8201         int ret;
8202
8203         /* Can't change pixel format via MI display flips. */
8204         if (fb->pixel_format != crtc->fb->pixel_format)
8205                 return -EINVAL;
8206
8207         /*
8208          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8209          * Note that pitch changes could also affect these register.
8210          */
8211         if (INTEL_INFO(dev)->gen > 3 &&
8212             (fb->offsets[0] != crtc->fb->offsets[0] ||
8213              fb->pitches[0] != crtc->fb->pitches[0]))
8214                 return -EINVAL;
8215
8216         work = kzalloc(sizeof(*work), GFP_KERNEL);
8217         if (work == NULL)
8218                 return -ENOMEM;
8219
8220         work->event = event;
8221         work->crtc = crtc;
8222         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8223         INIT_WORK(&work->work, intel_unpin_work_fn);
8224
8225         ret = drm_vblank_get(dev, intel_crtc->pipe);
8226         if (ret)
8227                 goto free_work;
8228
8229         /* We borrow the event spin lock for protecting unpin_work */
8230         spin_lock_irqsave(&dev->event_lock, flags);
8231         if (intel_crtc->unpin_work) {
8232                 spin_unlock_irqrestore(&dev->event_lock, flags);
8233                 kfree(work);
8234                 drm_vblank_put(dev, intel_crtc->pipe);
8235
8236                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8237                 return -EBUSY;
8238         }
8239         intel_crtc->unpin_work = work;
8240         spin_unlock_irqrestore(&dev->event_lock, flags);
8241
8242         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8243                 flush_workqueue(dev_priv->wq);
8244
8245         ret = i915_mutex_lock_interruptible(dev);
8246         if (ret)
8247                 goto cleanup;
8248
8249         /* Reference the objects for the scheduled work. */
8250         drm_gem_object_reference(&work->old_fb_obj->base);
8251         drm_gem_object_reference(&obj->base);
8252
8253         crtc->fb = fb;
8254
8255         work->pending_flip_obj = obj;
8256
8257         work->enable_stall_check = true;
8258
8259         atomic_inc(&intel_crtc->unpin_work_count);
8260         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8261
8262         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8263         if (ret)
8264                 goto cleanup_pending;
8265
8266         intel_disable_fbc(dev);
8267         intel_mark_fb_busy(obj, NULL);
8268         mutex_unlock(&dev->struct_mutex);
8269
8270         trace_i915_flip_request(intel_crtc->plane, obj);
8271
8272         return 0;
8273
8274 cleanup_pending:
8275         atomic_dec(&intel_crtc->unpin_work_count);
8276         crtc->fb = old_fb;
8277         drm_gem_object_unreference(&work->old_fb_obj->base);
8278         drm_gem_object_unreference(&obj->base);
8279         mutex_unlock(&dev->struct_mutex);
8280
8281 cleanup:
8282         spin_lock_irqsave(&dev->event_lock, flags);
8283         intel_crtc->unpin_work = NULL;
8284         spin_unlock_irqrestore(&dev->event_lock, flags);
8285
8286         drm_vblank_put(dev, intel_crtc->pipe);
8287 free_work:
8288         kfree(work);
8289
8290         return ret;
8291 }
8292
8293 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8294         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8295         .load_lut = intel_crtc_load_lut,
8296 };
8297
8298 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8299                                   struct drm_crtc *crtc)
8300 {
8301         struct drm_device *dev;
8302         struct drm_crtc *tmp;
8303         int crtc_mask = 1;
8304
8305         WARN(!crtc, "checking null crtc?\n");
8306
8307         dev = crtc->dev;
8308
8309         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8310                 if (tmp == crtc)
8311                         break;
8312                 crtc_mask <<= 1;
8313         }
8314
8315         if (encoder->possible_crtcs & crtc_mask)
8316                 return true;
8317         return false;
8318 }
8319
8320 /**
8321  * intel_modeset_update_staged_output_state
8322  *
8323  * Updates the staged output configuration state, e.g. after we've read out the
8324  * current hw state.
8325  */
8326 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8327 {
8328         struct intel_encoder *encoder;
8329         struct intel_connector *connector;
8330
8331         list_for_each_entry(connector, &dev->mode_config.connector_list,
8332                             base.head) {
8333                 connector->new_encoder =
8334                         to_intel_encoder(connector->base.encoder);
8335         }
8336
8337         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8338                             base.head) {
8339                 encoder->new_crtc =
8340                         to_intel_crtc(encoder->base.crtc);
8341         }
8342 }
8343
8344 /**
8345  * intel_modeset_commit_output_state
8346  *
8347  * This function copies the stage display pipe configuration to the real one.
8348  */
8349 static void intel_modeset_commit_output_state(struct drm_device *dev)
8350 {
8351         struct intel_encoder *encoder;
8352         struct intel_connector *connector;
8353
8354         list_for_each_entry(connector, &dev->mode_config.connector_list,
8355                             base.head) {
8356                 connector->base.encoder = &connector->new_encoder->base;
8357         }
8358
8359         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8360                             base.head) {
8361                 encoder->base.crtc = &encoder->new_crtc->base;
8362         }
8363 }
8364
8365 static void
8366 connected_sink_compute_bpp(struct intel_connector * connector,
8367                            struct intel_crtc_config *pipe_config)
8368 {
8369         int bpp = pipe_config->pipe_bpp;
8370
8371         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8372                 connector->base.base.id,
8373                 drm_get_connector_name(&connector->base));
8374
8375         /* Don't use an invalid EDID bpc value */
8376         if (connector->base.display_info.bpc &&
8377             connector->base.display_info.bpc * 3 < bpp) {
8378                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8379                               bpp, connector->base.display_info.bpc*3);
8380                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8381         }
8382
8383         /* Clamp bpp to 8 on screens without EDID 1.4 */
8384         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8385                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8386                               bpp);
8387                 pipe_config->pipe_bpp = 24;
8388         }
8389 }
8390
8391 static int
8392 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8393                           struct drm_framebuffer *fb,
8394                           struct intel_crtc_config *pipe_config)
8395 {
8396         struct drm_device *dev = crtc->base.dev;
8397         struct intel_connector *connector;
8398         int bpp;
8399
8400         switch (fb->pixel_format) {
8401         case DRM_FORMAT_C8:
8402                 bpp = 8*3; /* since we go through a colormap */
8403                 break;
8404         case DRM_FORMAT_XRGB1555:
8405         case DRM_FORMAT_ARGB1555:
8406                 /* checked in intel_framebuffer_init already */
8407                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8408                         return -EINVAL;
8409         case DRM_FORMAT_RGB565:
8410                 bpp = 6*3; /* min is 18bpp */
8411                 break;
8412         case DRM_FORMAT_XBGR8888:
8413         case DRM_FORMAT_ABGR8888:
8414                 /* checked in intel_framebuffer_init already */
8415                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8416                         return -EINVAL;
8417         case DRM_FORMAT_XRGB8888:
8418         case DRM_FORMAT_ARGB8888:
8419                 bpp = 8*3;
8420                 break;
8421         case DRM_FORMAT_XRGB2101010:
8422         case DRM_FORMAT_ARGB2101010:
8423         case DRM_FORMAT_XBGR2101010:
8424         case DRM_FORMAT_ABGR2101010:
8425                 /* checked in intel_framebuffer_init already */
8426                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8427                         return -EINVAL;
8428                 bpp = 10*3;
8429                 break;
8430         /* TODO: gen4+ supports 16 bpc floating point, too. */
8431         default:
8432                 DRM_DEBUG_KMS("unsupported depth\n");
8433                 return -EINVAL;
8434         }
8435
8436         pipe_config->pipe_bpp = bpp;
8437
8438         /* Clamp display bpp to EDID value */
8439         list_for_each_entry(connector, &dev->mode_config.connector_list,
8440                             base.head) {
8441                 if (!connector->new_encoder ||
8442                     connector->new_encoder->new_crtc != crtc)
8443                         continue;
8444
8445                 connected_sink_compute_bpp(connector, pipe_config);
8446         }
8447
8448         return bpp;
8449 }
8450
8451 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8452 {
8453         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8454                         "type: 0x%x flags: 0x%x\n",
8455                 mode->crtc_clock,
8456                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8457                 mode->crtc_hsync_end, mode->crtc_htotal,
8458                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8459                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8460 }
8461
8462 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8463                                    struct intel_crtc_config *pipe_config,
8464                                    const char *context)
8465 {
8466         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8467                       context, pipe_name(crtc->pipe));
8468
8469         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8470         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8471                       pipe_config->pipe_bpp, pipe_config->dither);
8472         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8473                       pipe_config->has_pch_encoder,
8474                       pipe_config->fdi_lanes,
8475                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8476                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8477                       pipe_config->fdi_m_n.tu);
8478         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8479                       pipe_config->has_dp_encoder,
8480                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8481                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8482                       pipe_config->dp_m_n.tu);
8483         DRM_DEBUG_KMS("requested mode:\n");
8484         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8485         DRM_DEBUG_KMS("adjusted mode:\n");
8486         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8487         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8488         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8489         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8490                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8491         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8492                       pipe_config->gmch_pfit.control,
8493                       pipe_config->gmch_pfit.pgm_ratios,
8494                       pipe_config->gmch_pfit.lvds_border_bits);
8495         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8496                       pipe_config->pch_pfit.pos,
8497                       pipe_config->pch_pfit.size,
8498                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8499         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8500         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8501 }
8502
8503 static bool check_encoder_cloning(struct drm_crtc *crtc)
8504 {
8505         int num_encoders = 0;
8506         bool uncloneable_encoders = false;
8507         struct intel_encoder *encoder;
8508
8509         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8510                             base.head) {
8511                 if (&encoder->new_crtc->base != crtc)
8512                         continue;
8513
8514                 num_encoders++;
8515                 if (!encoder->cloneable)
8516                         uncloneable_encoders = true;
8517         }
8518
8519         return !(num_encoders > 1 && uncloneable_encoders);
8520 }
8521
8522 static struct intel_crtc_config *
8523 intel_modeset_pipe_config(struct drm_crtc *crtc,
8524                           struct drm_framebuffer *fb,
8525                           struct drm_display_mode *mode)
8526 {
8527         struct drm_device *dev = crtc->dev;
8528         struct intel_encoder *encoder;
8529         struct intel_crtc_config *pipe_config;
8530         int plane_bpp, ret = -EINVAL;
8531         bool retry = true;
8532
8533         if (!check_encoder_cloning(crtc)) {
8534                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8535                 return ERR_PTR(-EINVAL);
8536         }
8537
8538         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8539         if (!pipe_config)
8540                 return ERR_PTR(-ENOMEM);
8541
8542         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8543         drm_mode_copy(&pipe_config->requested_mode, mode);
8544
8545         pipe_config->cpu_transcoder =
8546                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8547         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8548
8549         /*
8550          * Sanitize sync polarity flags based on requested ones. If neither
8551          * positive or negative polarity is requested, treat this as meaning
8552          * negative polarity.
8553          */
8554         if (!(pipe_config->adjusted_mode.flags &
8555               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8556                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8557
8558         if (!(pipe_config->adjusted_mode.flags &
8559               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8560                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8561
8562         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8563          * plane pixel format and any sink constraints into account. Returns the
8564          * source plane bpp so that dithering can be selected on mismatches
8565          * after encoders and crtc also have had their say. */
8566         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8567                                               fb, pipe_config);
8568         if (plane_bpp < 0)
8569                 goto fail;
8570
8571         /*
8572          * Determine the real pipe dimensions. Note that stereo modes can
8573          * increase the actual pipe size due to the frame doubling and
8574          * insertion of additional space for blanks between the frame. This
8575          * is stored in the crtc timings. We use the requested mode to do this
8576          * computation to clearly distinguish it from the adjusted mode, which
8577          * can be changed by the connectors in the below retry loop.
8578          */
8579         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8580         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8581         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8582
8583 encoder_retry:
8584         /* Ensure the port clock defaults are reset when retrying. */
8585         pipe_config->port_clock = 0;
8586         pipe_config->pixel_multiplier = 1;
8587
8588         /* Fill in default crtc timings, allow encoders to overwrite them. */
8589         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8590
8591         /* Pass our mode to the connectors and the CRTC to give them a chance to
8592          * adjust it according to limitations or connector properties, and also
8593          * a chance to reject the mode entirely.
8594          */
8595         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8596                             base.head) {
8597
8598                 if (&encoder->new_crtc->base != crtc)
8599                         continue;
8600
8601                 if (!(encoder->compute_config(encoder, pipe_config))) {
8602                         DRM_DEBUG_KMS("Encoder config failure\n");
8603                         goto fail;
8604                 }
8605         }
8606
8607         /* Set default port clock if not overwritten by the encoder. Needs to be
8608          * done afterwards in case the encoder adjusts the mode. */
8609         if (!pipe_config->port_clock)
8610                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8611                         * pipe_config->pixel_multiplier;
8612
8613         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8614         if (ret < 0) {
8615                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8616                 goto fail;
8617         }
8618
8619         if (ret == RETRY) {
8620                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8621                         ret = -EINVAL;
8622                         goto fail;
8623                 }
8624
8625                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8626                 retry = false;
8627                 goto encoder_retry;
8628         }
8629
8630         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8631         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8632                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8633
8634         return pipe_config;
8635 fail:
8636         kfree(pipe_config);
8637         return ERR_PTR(ret);
8638 }
8639
8640 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8641  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8642 static void
8643 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8644                              unsigned *prepare_pipes, unsigned *disable_pipes)
8645 {
8646         struct intel_crtc *intel_crtc;
8647         struct drm_device *dev = crtc->dev;
8648         struct intel_encoder *encoder;
8649         struct intel_connector *connector;
8650         struct drm_crtc *tmp_crtc;
8651
8652         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8653
8654         /* Check which crtcs have changed outputs connected to them, these need
8655          * to be part of the prepare_pipes mask. We don't (yet) support global
8656          * modeset across multiple crtcs, so modeset_pipes will only have one
8657          * bit set at most. */
8658         list_for_each_entry(connector, &dev->mode_config.connector_list,
8659                             base.head) {
8660                 if (connector->base.encoder == &connector->new_encoder->base)
8661                         continue;
8662
8663                 if (connector->base.encoder) {
8664                         tmp_crtc = connector->base.encoder->crtc;
8665
8666                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8667                 }
8668
8669                 if (connector->new_encoder)
8670                         *prepare_pipes |=
8671                                 1 << connector->new_encoder->new_crtc->pipe;
8672         }
8673
8674         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8675                             base.head) {
8676                 if (encoder->base.crtc == &encoder->new_crtc->base)
8677                         continue;
8678
8679                 if (encoder->base.crtc) {
8680                         tmp_crtc = encoder->base.crtc;
8681
8682                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8683                 }
8684
8685                 if (encoder->new_crtc)
8686                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8687         }
8688
8689         /* Check for any pipes that will be fully disabled ... */
8690         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8691                             base.head) {
8692                 bool used = false;
8693
8694                 /* Don't try to disable disabled crtcs. */
8695                 if (!intel_crtc->base.enabled)
8696                         continue;
8697
8698                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8699                                     base.head) {
8700                         if (encoder->new_crtc == intel_crtc)
8701                                 used = true;
8702                 }
8703
8704                 if (!used)
8705                         *disable_pipes |= 1 << intel_crtc->pipe;
8706         }
8707
8708
8709         /* set_mode is also used to update properties on life display pipes. */
8710         intel_crtc = to_intel_crtc(crtc);
8711         if (crtc->enabled)
8712                 *prepare_pipes |= 1 << intel_crtc->pipe;
8713
8714         /*
8715          * For simplicity do a full modeset on any pipe where the output routing
8716          * changed. We could be more clever, but that would require us to be
8717          * more careful with calling the relevant encoder->mode_set functions.
8718          */
8719         if (*prepare_pipes)
8720                 *modeset_pipes = *prepare_pipes;
8721
8722         /* ... and mask these out. */
8723         *modeset_pipes &= ~(*disable_pipes);
8724         *prepare_pipes &= ~(*disable_pipes);
8725
8726         /*
8727          * HACK: We don't (yet) fully support global modesets. intel_set_config
8728          * obies this rule, but the modeset restore mode of
8729          * intel_modeset_setup_hw_state does not.
8730          */
8731         *modeset_pipes &= 1 << intel_crtc->pipe;
8732         *prepare_pipes &= 1 << intel_crtc->pipe;
8733
8734         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8735                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8736 }
8737
8738 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8739 {
8740         struct drm_encoder *encoder;
8741         struct drm_device *dev = crtc->dev;
8742
8743         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8744                 if (encoder->crtc == crtc)
8745                         return true;
8746
8747         return false;
8748 }
8749
8750 static void
8751 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8752 {
8753         struct intel_encoder *intel_encoder;
8754         struct intel_crtc *intel_crtc;
8755         struct drm_connector *connector;
8756
8757         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8758                             base.head) {
8759                 if (!intel_encoder->base.crtc)
8760                         continue;
8761
8762                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8763
8764                 if (prepare_pipes & (1 << intel_crtc->pipe))
8765                         intel_encoder->connectors_active = false;
8766         }
8767
8768         intel_modeset_commit_output_state(dev);
8769
8770         /* Update computed state. */
8771         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8772                             base.head) {
8773                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8774         }
8775
8776         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8777                 if (!connector->encoder || !connector->encoder->crtc)
8778                         continue;
8779
8780                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8781
8782                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8783                         struct drm_property *dpms_property =
8784                                 dev->mode_config.dpms_property;
8785
8786                         connector->dpms = DRM_MODE_DPMS_ON;
8787                         drm_object_property_set_value(&connector->base,
8788                                                          dpms_property,
8789                                                          DRM_MODE_DPMS_ON);
8790
8791                         intel_encoder = to_intel_encoder(connector->encoder);
8792                         intel_encoder->connectors_active = true;
8793                 }
8794         }
8795
8796 }
8797
8798 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8799 {
8800         int diff;
8801
8802         if (clock1 == clock2)
8803                 return true;
8804
8805         if (!clock1 || !clock2)
8806                 return false;
8807
8808         diff = abs(clock1 - clock2);
8809
8810         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8811                 return true;
8812
8813         return false;
8814 }
8815
8816 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8817         list_for_each_entry((intel_crtc), \
8818                             &(dev)->mode_config.crtc_list, \
8819                             base.head) \
8820                 if (mask & (1 <<(intel_crtc)->pipe))
8821
8822 static bool
8823 intel_pipe_config_compare(struct drm_device *dev,
8824                           struct intel_crtc_config *current_config,
8825                           struct intel_crtc_config *pipe_config)
8826 {
8827 #define PIPE_CONF_CHECK_X(name) \
8828         if (current_config->name != pipe_config->name) { \
8829                 DRM_ERROR("mismatch in " #name " " \
8830                           "(expected 0x%08x, found 0x%08x)\n", \
8831                           current_config->name, \
8832                           pipe_config->name); \
8833                 return false; \
8834         }
8835
8836 #define PIPE_CONF_CHECK_I(name) \
8837         if (current_config->name != pipe_config->name) { \
8838                 DRM_ERROR("mismatch in " #name " " \
8839                           "(expected %i, found %i)\n", \
8840                           current_config->name, \
8841                           pipe_config->name); \
8842                 return false; \
8843         }
8844
8845 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8846         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8847                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8848                           "(expected %i, found %i)\n", \
8849                           current_config->name & (mask), \
8850                           pipe_config->name & (mask)); \
8851                 return false; \
8852         }
8853
8854 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8855         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8856                 DRM_ERROR("mismatch in " #name " " \
8857                           "(expected %i, found %i)\n", \
8858                           current_config->name, \
8859                           pipe_config->name); \
8860                 return false; \
8861         }
8862
8863 #define PIPE_CONF_QUIRK(quirk)  \
8864         ((current_config->quirks | pipe_config->quirks) & (quirk))
8865
8866         PIPE_CONF_CHECK_I(cpu_transcoder);
8867
8868         PIPE_CONF_CHECK_I(has_pch_encoder);
8869         PIPE_CONF_CHECK_I(fdi_lanes);
8870         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8871         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8872         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8873         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8874         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8875
8876         PIPE_CONF_CHECK_I(has_dp_encoder);
8877         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8878         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8879         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8880         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8881         PIPE_CONF_CHECK_I(dp_m_n.tu);
8882
8883         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8884         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8885         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8886         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8887         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8888         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8889
8890         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8891         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8892         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8893         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8894         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8895         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8896
8897         PIPE_CONF_CHECK_I(pixel_multiplier);
8898
8899         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8900                               DRM_MODE_FLAG_INTERLACE);
8901
8902         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8903                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8904                                       DRM_MODE_FLAG_PHSYNC);
8905                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8906                                       DRM_MODE_FLAG_NHSYNC);
8907                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8908                                       DRM_MODE_FLAG_PVSYNC);
8909                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8910                                       DRM_MODE_FLAG_NVSYNC);
8911         }
8912
8913         PIPE_CONF_CHECK_I(pipe_src_w);
8914         PIPE_CONF_CHECK_I(pipe_src_h);
8915
8916         PIPE_CONF_CHECK_I(gmch_pfit.control);
8917         /* pfit ratios are autocomputed by the hw on gen4+ */
8918         if (INTEL_INFO(dev)->gen < 4)
8919                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8920         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8921         PIPE_CONF_CHECK_I(pch_pfit.enabled);
8922         if (current_config->pch_pfit.enabled) {
8923                 PIPE_CONF_CHECK_I(pch_pfit.pos);
8924                 PIPE_CONF_CHECK_I(pch_pfit.size);
8925         }
8926
8927         PIPE_CONF_CHECK_I(ips_enabled);
8928
8929         PIPE_CONF_CHECK_I(double_wide);
8930
8931         PIPE_CONF_CHECK_I(shared_dpll);
8932         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8933         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8934         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8935         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8936
8937         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8938                 PIPE_CONF_CHECK_I(pipe_bpp);
8939
8940         if (!IS_HASWELL(dev)) {
8941                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
8942                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8943         }
8944
8945 #undef PIPE_CONF_CHECK_X
8946 #undef PIPE_CONF_CHECK_I
8947 #undef PIPE_CONF_CHECK_FLAGS
8948 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8949 #undef PIPE_CONF_QUIRK
8950
8951         return true;
8952 }
8953
8954 static void
8955 check_connector_state(struct drm_device *dev)
8956 {
8957         struct intel_connector *connector;
8958
8959         list_for_each_entry(connector, &dev->mode_config.connector_list,
8960                             base.head) {
8961                 /* This also checks the encoder/connector hw state with the
8962                  * ->get_hw_state callbacks. */
8963                 intel_connector_check_state(connector);
8964
8965                 WARN(&connector->new_encoder->base != connector->base.encoder,
8966                      "connector's staged encoder doesn't match current encoder\n");
8967         }
8968 }
8969
8970 static void
8971 check_encoder_state(struct drm_device *dev)
8972 {
8973         struct intel_encoder *encoder;
8974         struct intel_connector *connector;
8975
8976         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8977                             base.head) {
8978                 bool enabled = false;
8979                 bool active = false;
8980                 enum pipe pipe, tracked_pipe;
8981
8982                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8983                               encoder->base.base.id,
8984                               drm_get_encoder_name(&encoder->base));
8985
8986                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8987                      "encoder's stage crtc doesn't match current crtc\n");
8988                 WARN(encoder->connectors_active && !encoder->base.crtc,
8989                      "encoder's active_connectors set, but no crtc\n");
8990
8991                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8992                                     base.head) {
8993                         if (connector->base.encoder != &encoder->base)
8994                                 continue;
8995                         enabled = true;
8996                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8997                                 active = true;
8998                 }
8999                 WARN(!!encoder->base.crtc != enabled,
9000                      "encoder's enabled state mismatch "
9001                      "(expected %i, found %i)\n",
9002                      !!encoder->base.crtc, enabled);
9003                 WARN(active && !encoder->base.crtc,
9004                      "active encoder with no crtc\n");
9005
9006                 WARN(encoder->connectors_active != active,
9007                      "encoder's computed active state doesn't match tracked active state "
9008                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9009
9010                 active = encoder->get_hw_state(encoder, &pipe);
9011                 WARN(active != encoder->connectors_active,
9012                      "encoder's hw state doesn't match sw tracking "
9013                      "(expected %i, found %i)\n",
9014                      encoder->connectors_active, active);
9015
9016                 if (!encoder->base.crtc)
9017                         continue;
9018
9019                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9020                 WARN(active && pipe != tracked_pipe,
9021                      "active encoder's pipe doesn't match"
9022                      "(expected %i, found %i)\n",
9023                      tracked_pipe, pipe);
9024
9025         }
9026 }
9027
9028 static void
9029 check_crtc_state(struct drm_device *dev)
9030 {
9031         drm_i915_private_t *dev_priv = dev->dev_private;
9032         struct intel_crtc *crtc;
9033         struct intel_encoder *encoder;
9034         struct intel_crtc_config pipe_config;
9035
9036         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9037                             base.head) {
9038                 bool enabled = false;
9039                 bool active = false;
9040
9041                 memset(&pipe_config, 0, sizeof(pipe_config));
9042
9043                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9044                               crtc->base.base.id);
9045
9046                 WARN(crtc->active && !crtc->base.enabled,
9047                      "active crtc, but not enabled in sw tracking\n");
9048
9049                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9050                                     base.head) {
9051                         if (encoder->base.crtc != &crtc->base)
9052                                 continue;
9053                         enabled = true;
9054                         if (encoder->connectors_active)
9055                                 active = true;
9056                 }
9057
9058                 WARN(active != crtc->active,
9059                      "crtc's computed active state doesn't match tracked active state "
9060                      "(expected %i, found %i)\n", active, crtc->active);
9061                 WARN(enabled != crtc->base.enabled,
9062                      "crtc's computed enabled state doesn't match tracked enabled state "
9063                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9064
9065                 active = dev_priv->display.get_pipe_config(crtc,
9066                                                            &pipe_config);
9067
9068                 /* hw state is inconsistent with the pipe A quirk */
9069                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9070                         active = crtc->active;
9071
9072                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9073                                     base.head) {
9074                         enum pipe pipe;
9075                         if (encoder->base.crtc != &crtc->base)
9076                                 continue;
9077                         if (encoder->get_config &&
9078                             encoder->get_hw_state(encoder, &pipe))
9079                                 encoder->get_config(encoder, &pipe_config);
9080                 }
9081
9082                 WARN(crtc->active != active,
9083                      "crtc active state doesn't match with hw state "
9084                      "(expected %i, found %i)\n", crtc->active, active);
9085
9086                 if (active &&
9087                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9088                         WARN(1, "pipe state doesn't match!\n");
9089                         intel_dump_pipe_config(crtc, &pipe_config,
9090                                                "[hw state]");
9091                         intel_dump_pipe_config(crtc, &crtc->config,
9092                                                "[sw state]");
9093                 }
9094         }
9095 }
9096
9097 static void
9098 check_shared_dpll_state(struct drm_device *dev)
9099 {
9100         drm_i915_private_t *dev_priv = dev->dev_private;
9101         struct intel_crtc *crtc;
9102         struct intel_dpll_hw_state dpll_hw_state;
9103         int i;
9104
9105         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9106                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9107                 int enabled_crtcs = 0, active_crtcs = 0;
9108                 bool active;
9109
9110                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9111
9112                 DRM_DEBUG_KMS("%s\n", pll->name);
9113
9114                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9115
9116                 WARN(pll->active > pll->refcount,
9117                      "more active pll users than references: %i vs %i\n",
9118                      pll->active, pll->refcount);
9119                 WARN(pll->active && !pll->on,
9120                      "pll in active use but not on in sw tracking\n");
9121                 WARN(pll->on && !pll->active,
9122                      "pll in on but not on in use in sw tracking\n");
9123                 WARN(pll->on != active,
9124                      "pll on state mismatch (expected %i, found %i)\n",
9125                      pll->on, active);
9126
9127                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9128                                     base.head) {
9129                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9130                                 enabled_crtcs++;
9131                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9132                                 active_crtcs++;
9133                 }
9134                 WARN(pll->active != active_crtcs,
9135                      "pll active crtcs mismatch (expected %i, found %i)\n",
9136                      pll->active, active_crtcs);
9137                 WARN(pll->refcount != enabled_crtcs,
9138                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9139                      pll->refcount, enabled_crtcs);
9140
9141                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9142                                        sizeof(dpll_hw_state)),
9143                      "pll hw state mismatch\n");
9144         }
9145 }
9146
9147 void
9148 intel_modeset_check_state(struct drm_device *dev)
9149 {
9150         check_connector_state(dev);
9151         check_encoder_state(dev);
9152         check_crtc_state(dev);
9153         check_shared_dpll_state(dev);
9154 }
9155
9156 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9157                                      int dotclock)
9158 {
9159         /*
9160          * FDI already provided one idea for the dotclock.
9161          * Yell if the encoder disagrees.
9162          */
9163         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9164              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9165              pipe_config->adjusted_mode.crtc_clock, dotclock);
9166 }
9167
9168 static int __intel_set_mode(struct drm_crtc *crtc,
9169                             struct drm_display_mode *mode,
9170                             int x, int y, struct drm_framebuffer *fb)
9171 {
9172         struct drm_device *dev = crtc->dev;
9173         drm_i915_private_t *dev_priv = dev->dev_private;
9174         struct drm_display_mode *saved_mode, *saved_hwmode;
9175         struct intel_crtc_config *pipe_config = NULL;
9176         struct intel_crtc *intel_crtc;
9177         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9178         int ret = 0;
9179
9180         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9181         if (!saved_mode)
9182                 return -ENOMEM;
9183         saved_hwmode = saved_mode + 1;
9184
9185         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9186                                      &prepare_pipes, &disable_pipes);
9187
9188         *saved_hwmode = crtc->hwmode;
9189         *saved_mode = crtc->mode;
9190
9191         /* Hack: Because we don't (yet) support global modeset on multiple
9192          * crtcs, we don't keep track of the new mode for more than one crtc.
9193          * Hence simply check whether any bit is set in modeset_pipes in all the
9194          * pieces of code that are not yet converted to deal with mutliple crtcs
9195          * changing their mode at the same time. */
9196         if (modeset_pipes) {
9197                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9198                 if (IS_ERR(pipe_config)) {
9199                         ret = PTR_ERR(pipe_config);
9200                         pipe_config = NULL;
9201
9202                         goto out;
9203                 }
9204                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9205                                        "[modeset]");
9206         }
9207
9208         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9209                 intel_crtc_disable(&intel_crtc->base);
9210
9211         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9212                 if (intel_crtc->base.enabled)
9213                         dev_priv->display.crtc_disable(&intel_crtc->base);
9214         }
9215
9216         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9217          * to set it here already despite that we pass it down the callchain.
9218          */
9219         if (modeset_pipes) {
9220                 crtc->mode = *mode;
9221                 /* mode_set/enable/disable functions rely on a correct pipe
9222                  * config. */
9223                 to_intel_crtc(crtc)->config = *pipe_config;
9224         }
9225
9226         /* Only after disabling all output pipelines that will be changed can we
9227          * update the the output configuration. */
9228         intel_modeset_update_state(dev, prepare_pipes);
9229
9230         if (dev_priv->display.modeset_global_resources)
9231                 dev_priv->display.modeset_global_resources(dev);
9232
9233         /* Set up the DPLL and any encoders state that needs to adjust or depend
9234          * on the DPLL.
9235          */
9236         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9237                 ret = intel_crtc_mode_set(&intel_crtc->base,
9238                                           x, y, fb);
9239                 if (ret)
9240                         goto done;
9241         }
9242
9243         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9244         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9245                 dev_priv->display.crtc_enable(&intel_crtc->base);
9246
9247         if (modeset_pipes) {
9248                 /* Store real post-adjustment hardware mode. */
9249                 crtc->hwmode = pipe_config->adjusted_mode;
9250
9251                 /* Calculate and store various constants which
9252                  * are later needed by vblank and swap-completion
9253                  * timestamping. They are derived from true hwmode.
9254                  */
9255                 drm_calc_timestamping_constants(crtc);
9256         }
9257
9258         /* FIXME: add subpixel order */
9259 done:
9260         if (ret && crtc->enabled) {
9261                 crtc->hwmode = *saved_hwmode;
9262                 crtc->mode = *saved_mode;
9263         }
9264
9265 out:
9266         kfree(pipe_config);
9267         kfree(saved_mode);
9268         return ret;
9269 }
9270
9271 static int intel_set_mode(struct drm_crtc *crtc,
9272                           struct drm_display_mode *mode,
9273                           int x, int y, struct drm_framebuffer *fb)
9274 {
9275         int ret;
9276
9277         ret = __intel_set_mode(crtc, mode, x, y, fb);
9278
9279         if (ret == 0)
9280                 intel_modeset_check_state(crtc->dev);
9281
9282         return ret;
9283 }
9284
9285 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9286 {
9287         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9288 }
9289
9290 #undef for_each_intel_crtc_masked
9291
9292 static void intel_set_config_free(struct intel_set_config *config)
9293 {
9294         if (!config)
9295                 return;
9296
9297         kfree(config->save_connector_encoders);
9298         kfree(config->save_encoder_crtcs);
9299         kfree(config);
9300 }
9301
9302 static int intel_set_config_save_state(struct drm_device *dev,
9303                                        struct intel_set_config *config)
9304 {
9305         struct drm_encoder *encoder;
9306         struct drm_connector *connector;
9307         int count;
9308
9309         config->save_encoder_crtcs =
9310                 kcalloc(dev->mode_config.num_encoder,
9311                         sizeof(struct drm_crtc *), GFP_KERNEL);
9312         if (!config->save_encoder_crtcs)
9313                 return -ENOMEM;
9314
9315         config->save_connector_encoders =
9316                 kcalloc(dev->mode_config.num_connector,
9317                         sizeof(struct drm_encoder *), GFP_KERNEL);
9318         if (!config->save_connector_encoders)
9319                 return -ENOMEM;
9320
9321         /* Copy data. Note that driver private data is not affected.
9322          * Should anything bad happen only the expected state is
9323          * restored, not the drivers personal bookkeeping.
9324          */
9325         count = 0;
9326         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9327                 config->save_encoder_crtcs[count++] = encoder->crtc;
9328         }
9329
9330         count = 0;
9331         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9332                 config->save_connector_encoders[count++] = connector->encoder;
9333         }
9334
9335         return 0;
9336 }
9337
9338 static void intel_set_config_restore_state(struct drm_device *dev,
9339                                            struct intel_set_config *config)
9340 {
9341         struct intel_encoder *encoder;
9342         struct intel_connector *connector;
9343         int count;
9344
9345         count = 0;
9346         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9347                 encoder->new_crtc =
9348                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9349         }
9350
9351         count = 0;
9352         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9353                 connector->new_encoder =
9354                         to_intel_encoder(config->save_connector_encoders[count++]);
9355         }
9356 }
9357
9358 static bool
9359 is_crtc_connector_off(struct drm_mode_set *set)
9360 {
9361         int i;
9362
9363         if (set->num_connectors == 0)
9364                 return false;
9365
9366         if (WARN_ON(set->connectors == NULL))
9367                 return false;
9368
9369         for (i = 0; i < set->num_connectors; i++)
9370                 if (set->connectors[i]->encoder &&
9371                     set->connectors[i]->encoder->crtc == set->crtc &&
9372                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9373                         return true;
9374
9375         return false;
9376 }
9377
9378 static void
9379 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9380                                       struct intel_set_config *config)
9381 {
9382
9383         /* We should be able to check here if the fb has the same properties
9384          * and then just flip_or_move it */
9385         if (is_crtc_connector_off(set)) {
9386                 config->mode_changed = true;
9387         } else if (set->crtc->fb != set->fb) {
9388                 /* If we have no fb then treat it as a full mode set */
9389                 if (set->crtc->fb == NULL) {
9390                         struct intel_crtc *intel_crtc =
9391                                 to_intel_crtc(set->crtc);
9392
9393                         if (intel_crtc->active && i915_fastboot) {
9394                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9395                                 config->fb_changed = true;
9396                         } else {
9397                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9398                                 config->mode_changed = true;
9399                         }
9400                 } else if (set->fb == NULL) {
9401                         config->mode_changed = true;
9402                 } else if (set->fb->pixel_format !=
9403                            set->crtc->fb->pixel_format) {
9404                         config->mode_changed = true;
9405                 } else {
9406                         config->fb_changed = true;
9407                 }
9408         }
9409
9410         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9411                 config->fb_changed = true;
9412
9413         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9414                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9415                 drm_mode_debug_printmodeline(&set->crtc->mode);
9416                 drm_mode_debug_printmodeline(set->mode);
9417                 config->mode_changed = true;
9418         }
9419
9420         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9421                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9422 }
9423
9424 static int
9425 intel_modeset_stage_output_state(struct drm_device *dev,
9426                                  struct drm_mode_set *set,
9427                                  struct intel_set_config *config)
9428 {
9429         struct drm_crtc *new_crtc;
9430         struct intel_connector *connector;
9431         struct intel_encoder *encoder;
9432         int ro;
9433
9434         /* The upper layers ensure that we either disable a crtc or have a list
9435          * of connectors. For paranoia, double-check this. */
9436         WARN_ON(!set->fb && (set->num_connectors != 0));
9437         WARN_ON(set->fb && (set->num_connectors == 0));
9438
9439         list_for_each_entry(connector, &dev->mode_config.connector_list,
9440                             base.head) {
9441                 /* Otherwise traverse passed in connector list and get encoders
9442                  * for them. */
9443                 for (ro = 0; ro < set->num_connectors; ro++) {
9444                         if (set->connectors[ro] == &connector->base) {
9445                                 connector->new_encoder = connector->encoder;
9446                                 break;
9447                         }
9448                 }
9449
9450                 /* If we disable the crtc, disable all its connectors. Also, if
9451                  * the connector is on the changing crtc but not on the new
9452                  * connector list, disable it. */
9453                 if ((!set->fb || ro == set->num_connectors) &&
9454                     connector->base.encoder &&
9455                     connector->base.encoder->crtc == set->crtc) {
9456                         connector->new_encoder = NULL;
9457
9458                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9459                                 connector->base.base.id,
9460                                 drm_get_connector_name(&connector->base));
9461                 }
9462
9463
9464                 if (&connector->new_encoder->base != connector->base.encoder) {
9465                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9466                         config->mode_changed = true;
9467                 }
9468         }
9469         /* connector->new_encoder is now updated for all connectors. */
9470
9471         /* Update crtc of enabled connectors. */
9472         list_for_each_entry(connector, &dev->mode_config.connector_list,
9473                             base.head) {
9474                 if (!connector->new_encoder)
9475                         continue;
9476
9477                 new_crtc = connector->new_encoder->base.crtc;
9478
9479                 for (ro = 0; ro < set->num_connectors; ro++) {
9480                         if (set->connectors[ro] == &connector->base)
9481                                 new_crtc = set->crtc;
9482                 }
9483
9484                 /* Make sure the new CRTC will work with the encoder */
9485                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9486                                            new_crtc)) {
9487                         return -EINVAL;
9488                 }
9489                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9490
9491                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9492                         connector->base.base.id,
9493                         drm_get_connector_name(&connector->base),
9494                         new_crtc->base.id);
9495         }
9496
9497         /* Check for any encoders that needs to be disabled. */
9498         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9499                             base.head) {
9500                 list_for_each_entry(connector,
9501                                     &dev->mode_config.connector_list,
9502                                     base.head) {
9503                         if (connector->new_encoder == encoder) {
9504                                 WARN_ON(!connector->new_encoder->new_crtc);
9505
9506                                 goto next_encoder;
9507                         }
9508                 }
9509                 encoder->new_crtc = NULL;
9510 next_encoder:
9511                 /* Only now check for crtc changes so we don't miss encoders
9512                  * that will be disabled. */
9513                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9514                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9515                         config->mode_changed = true;
9516                 }
9517         }
9518         /* Now we've also updated encoder->new_crtc for all encoders. */
9519
9520         return 0;
9521 }
9522
9523 static int intel_crtc_set_config(struct drm_mode_set *set)
9524 {
9525         struct drm_device *dev;
9526         struct drm_mode_set save_set;
9527         struct intel_set_config *config;
9528         int ret;
9529
9530         BUG_ON(!set);
9531         BUG_ON(!set->crtc);
9532         BUG_ON(!set->crtc->helper_private);
9533
9534         /* Enforce sane interface api - has been abused by the fb helper. */
9535         BUG_ON(!set->mode && set->fb);
9536         BUG_ON(set->fb && set->num_connectors == 0);
9537
9538         if (set->fb) {
9539                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9540                                 set->crtc->base.id, set->fb->base.id,
9541                                 (int)set->num_connectors, set->x, set->y);
9542         } else {
9543                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9544         }
9545
9546         dev = set->crtc->dev;
9547
9548         ret = -ENOMEM;
9549         config = kzalloc(sizeof(*config), GFP_KERNEL);
9550         if (!config)
9551                 goto out_config;
9552
9553         ret = intel_set_config_save_state(dev, config);
9554         if (ret)
9555                 goto out_config;
9556
9557         save_set.crtc = set->crtc;
9558         save_set.mode = &set->crtc->mode;
9559         save_set.x = set->crtc->x;
9560         save_set.y = set->crtc->y;
9561         save_set.fb = set->crtc->fb;
9562
9563         /* Compute whether we need a full modeset, only an fb base update or no
9564          * change at all. In the future we might also check whether only the
9565          * mode changed, e.g. for LVDS where we only change the panel fitter in
9566          * such cases. */
9567         intel_set_config_compute_mode_changes(set, config);
9568
9569         ret = intel_modeset_stage_output_state(dev, set, config);
9570         if (ret)
9571                 goto fail;
9572
9573         if (config->mode_changed) {
9574                 ret = intel_set_mode(set->crtc, set->mode,
9575                                      set->x, set->y, set->fb);
9576         } else if (config->fb_changed) {
9577                 intel_crtc_wait_for_pending_flips(set->crtc);
9578
9579                 ret = intel_pipe_set_base(set->crtc,
9580                                           set->x, set->y, set->fb);
9581         }
9582
9583         if (ret) {
9584                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9585                               set->crtc->base.id, ret);
9586 fail:
9587                 intel_set_config_restore_state(dev, config);
9588
9589                 /* Try to restore the config */
9590                 if (config->mode_changed &&
9591                     intel_set_mode(save_set.crtc, save_set.mode,
9592                                    save_set.x, save_set.y, save_set.fb))
9593                         DRM_ERROR("failed to restore config after modeset failure\n");
9594         }
9595
9596 out_config:
9597         intel_set_config_free(config);
9598         return ret;
9599 }
9600
9601 static const struct drm_crtc_funcs intel_crtc_funcs = {
9602         .cursor_set = intel_crtc_cursor_set,
9603         .cursor_move = intel_crtc_cursor_move,
9604         .gamma_set = intel_crtc_gamma_set,
9605         .set_config = intel_crtc_set_config,
9606         .destroy = intel_crtc_destroy,
9607         .page_flip = intel_crtc_page_flip,
9608 };
9609
9610 static void intel_cpu_pll_init(struct drm_device *dev)
9611 {
9612         if (HAS_DDI(dev))
9613                 intel_ddi_pll_init(dev);
9614 }
9615
9616 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9617                                       struct intel_shared_dpll *pll,
9618                                       struct intel_dpll_hw_state *hw_state)
9619 {
9620         uint32_t val;
9621
9622         val = I915_READ(PCH_DPLL(pll->id));
9623         hw_state->dpll = val;
9624         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9625         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9626
9627         return val & DPLL_VCO_ENABLE;
9628 }
9629
9630 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9631                                   struct intel_shared_dpll *pll)
9632 {
9633         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9634         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9635 }
9636
9637 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9638                                 struct intel_shared_dpll *pll)
9639 {
9640         /* PCH refclock must be enabled first */
9641         assert_pch_refclk_enabled(dev_priv);
9642
9643         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9644
9645         /* Wait for the clocks to stabilize. */
9646         POSTING_READ(PCH_DPLL(pll->id));
9647         udelay(150);
9648
9649         /* The pixel multiplier can only be updated once the
9650          * DPLL is enabled and the clocks are stable.
9651          *
9652          * So write it again.
9653          */
9654         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9655         POSTING_READ(PCH_DPLL(pll->id));
9656         udelay(200);
9657 }
9658
9659 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9660                                  struct intel_shared_dpll *pll)
9661 {
9662         struct drm_device *dev = dev_priv->dev;
9663         struct intel_crtc *crtc;
9664
9665         /* Make sure no transcoder isn't still depending on us. */
9666         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9667                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9668                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9669         }
9670
9671         I915_WRITE(PCH_DPLL(pll->id), 0);
9672         POSTING_READ(PCH_DPLL(pll->id));
9673         udelay(200);
9674 }
9675
9676 static char *ibx_pch_dpll_names[] = {
9677         "PCH DPLL A",
9678         "PCH DPLL B",
9679 };
9680
9681 static void ibx_pch_dpll_init(struct drm_device *dev)
9682 {
9683         struct drm_i915_private *dev_priv = dev->dev_private;
9684         int i;
9685
9686         dev_priv->num_shared_dpll = 2;
9687
9688         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9689                 dev_priv->shared_dplls[i].id = i;
9690                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9691                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9692                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9693                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9694                 dev_priv->shared_dplls[i].get_hw_state =
9695                         ibx_pch_dpll_get_hw_state;
9696         }
9697 }
9698
9699 static void intel_shared_dpll_init(struct drm_device *dev)
9700 {
9701         struct drm_i915_private *dev_priv = dev->dev_private;
9702
9703         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9704                 ibx_pch_dpll_init(dev);
9705         else
9706                 dev_priv->num_shared_dpll = 0;
9707
9708         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9709         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9710                       dev_priv->num_shared_dpll);
9711 }
9712
9713 static void intel_crtc_init(struct drm_device *dev, int pipe)
9714 {
9715         drm_i915_private_t *dev_priv = dev->dev_private;
9716         struct intel_crtc *intel_crtc;
9717         int i;
9718
9719         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9720         if (intel_crtc == NULL)
9721                 return;
9722
9723         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9724
9725         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9726         for (i = 0; i < 256; i++) {
9727                 intel_crtc->lut_r[i] = i;
9728                 intel_crtc->lut_g[i] = i;
9729                 intel_crtc->lut_b[i] = i;
9730         }
9731
9732         /* Swap pipes & planes for FBC on pre-965 */
9733         intel_crtc->pipe = pipe;
9734         intel_crtc->plane = pipe;
9735         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9736                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9737                 intel_crtc->plane = !pipe;
9738         }
9739
9740         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9741                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9742         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9743         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9744
9745         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9746 }
9747
9748 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9749                                 struct drm_file *file)
9750 {
9751         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9752         struct drm_mode_object *drmmode_obj;
9753         struct intel_crtc *crtc;
9754
9755         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9756                 return -ENODEV;
9757
9758         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9759                         DRM_MODE_OBJECT_CRTC);
9760
9761         if (!drmmode_obj) {
9762                 DRM_ERROR("no such CRTC id\n");
9763                 return -EINVAL;
9764         }
9765
9766         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9767         pipe_from_crtc_id->pipe = crtc->pipe;
9768
9769         return 0;
9770 }
9771
9772 static int intel_encoder_clones(struct intel_encoder *encoder)
9773 {
9774         struct drm_device *dev = encoder->base.dev;
9775         struct intel_encoder *source_encoder;
9776         int index_mask = 0;
9777         int entry = 0;
9778
9779         list_for_each_entry(source_encoder,
9780                             &dev->mode_config.encoder_list, base.head) {
9781
9782                 if (encoder == source_encoder)
9783                         index_mask |= (1 << entry);
9784
9785                 /* Intel hw has only one MUX where enocoders could be cloned. */
9786                 if (encoder->cloneable && source_encoder->cloneable)
9787                         index_mask |= (1 << entry);
9788
9789                 entry++;
9790         }
9791
9792         return index_mask;
9793 }
9794
9795 static bool has_edp_a(struct drm_device *dev)
9796 {
9797         struct drm_i915_private *dev_priv = dev->dev_private;
9798
9799         if (!IS_MOBILE(dev))
9800                 return false;
9801
9802         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9803                 return false;
9804
9805         if (IS_GEN5(dev) &&
9806             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9807                 return false;
9808
9809         return true;
9810 }
9811
9812 static void intel_setup_outputs(struct drm_device *dev)
9813 {
9814         struct drm_i915_private *dev_priv = dev->dev_private;
9815         struct intel_encoder *encoder;
9816         bool dpd_is_edp = false;
9817
9818         intel_lvds_init(dev);
9819
9820         if (!IS_ULT(dev))
9821                 intel_crt_init(dev);
9822
9823         if (HAS_DDI(dev)) {
9824                 int found;
9825
9826                 /* Haswell uses DDI functions to detect digital outputs */
9827                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9828                 /* DDI A only supports eDP */
9829                 if (found)
9830                         intel_ddi_init(dev, PORT_A);
9831
9832                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9833                  * register */
9834                 found = I915_READ(SFUSE_STRAP);
9835
9836                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9837                         intel_ddi_init(dev, PORT_B);
9838                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9839                         intel_ddi_init(dev, PORT_C);
9840                 if (found & SFUSE_STRAP_DDID_DETECTED)
9841                         intel_ddi_init(dev, PORT_D);
9842         } else if (HAS_PCH_SPLIT(dev)) {
9843                 int found;
9844                 dpd_is_edp = intel_dpd_is_edp(dev);
9845
9846                 if (has_edp_a(dev))
9847                         intel_dp_init(dev, DP_A, PORT_A);
9848
9849                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9850                         /* PCH SDVOB multiplex with HDMIB */
9851                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9852                         if (!found)
9853                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9854                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9855                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9856                 }
9857
9858                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9859                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9860
9861                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9862                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9863
9864                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9865                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9866
9867                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9868                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9869         } else if (IS_VALLEYVIEW(dev)) {
9870                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9871                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9872                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9873                                         PORT_C);
9874                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9875                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9876                                               PORT_C);
9877                 }
9878
9879                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9880                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9881                                         PORT_B);
9882                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9883                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9884                 }
9885
9886                 intel_dsi_init(dev);
9887         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9888                 bool found = false;
9889
9890                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9891                         DRM_DEBUG_KMS("probing SDVOB\n");
9892                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9893                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9894                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9895                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9896                         }
9897
9898                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9899                                 intel_dp_init(dev, DP_B, PORT_B);
9900                 }
9901
9902                 /* Before G4X SDVOC doesn't have its own detect register */
9903
9904                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9905                         DRM_DEBUG_KMS("probing SDVOC\n");
9906                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9907                 }
9908
9909                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9910
9911                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9912                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9913                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9914                         }
9915                         if (SUPPORTS_INTEGRATED_DP(dev))
9916                                 intel_dp_init(dev, DP_C, PORT_C);
9917                 }
9918
9919                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9920                     (I915_READ(DP_D) & DP_DETECTED))
9921                         intel_dp_init(dev, DP_D, PORT_D);
9922         } else if (IS_GEN2(dev))
9923                 intel_dvo_init(dev);
9924
9925         if (SUPPORTS_TV(dev))
9926                 intel_tv_init(dev);
9927
9928         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9929                 encoder->base.possible_crtcs = encoder->crtc_mask;
9930                 encoder->base.possible_clones =
9931                         intel_encoder_clones(encoder);
9932         }
9933
9934         intel_init_pch_refclk(dev);
9935
9936         drm_helper_move_panel_connectors_to_head(dev);
9937 }
9938
9939 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9940 {
9941         drm_framebuffer_cleanup(&fb->base);
9942         drm_gem_object_unreference_unlocked(&fb->obj->base);
9943 }
9944
9945 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9946 {
9947         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9948
9949         intel_framebuffer_fini(intel_fb);
9950         kfree(intel_fb);
9951 }
9952
9953 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9954                                                 struct drm_file *file,
9955                                                 unsigned int *handle)
9956 {
9957         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9958         struct drm_i915_gem_object *obj = intel_fb->obj;
9959
9960         return drm_gem_handle_create(file, &obj->base, handle);
9961 }
9962
9963 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9964         .destroy = intel_user_framebuffer_destroy,
9965         .create_handle = intel_user_framebuffer_create_handle,
9966 };
9967
9968 int intel_framebuffer_init(struct drm_device *dev,
9969                            struct intel_framebuffer *intel_fb,
9970                            struct drm_mode_fb_cmd2 *mode_cmd,
9971                            struct drm_i915_gem_object *obj)
9972 {
9973         int pitch_limit;
9974         int ret;
9975
9976         if (obj->tiling_mode == I915_TILING_Y) {
9977                 DRM_DEBUG("hardware does not support tiling Y\n");
9978                 return -EINVAL;
9979         }
9980
9981         if (mode_cmd->pitches[0] & 63) {
9982                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9983                           mode_cmd->pitches[0]);
9984                 return -EINVAL;
9985         }
9986
9987         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9988                 pitch_limit = 32*1024;
9989         } else if (INTEL_INFO(dev)->gen >= 4) {
9990                 if (obj->tiling_mode)
9991                         pitch_limit = 16*1024;
9992                 else
9993                         pitch_limit = 32*1024;
9994         } else if (INTEL_INFO(dev)->gen >= 3) {
9995                 if (obj->tiling_mode)
9996                         pitch_limit = 8*1024;
9997                 else
9998                         pitch_limit = 16*1024;
9999         } else
10000                 /* XXX DSPC is limited to 4k tiled */
10001                 pitch_limit = 8*1024;
10002
10003         if (mode_cmd->pitches[0] > pitch_limit) {
10004                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10005                           obj->tiling_mode ? "tiled" : "linear",
10006                           mode_cmd->pitches[0], pitch_limit);
10007                 return -EINVAL;
10008         }
10009
10010         if (obj->tiling_mode != I915_TILING_NONE &&
10011             mode_cmd->pitches[0] != obj->stride) {
10012                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10013                           mode_cmd->pitches[0], obj->stride);
10014                 return -EINVAL;
10015         }
10016
10017         /* Reject formats not supported by any plane early. */
10018         switch (mode_cmd->pixel_format) {
10019         case DRM_FORMAT_C8:
10020         case DRM_FORMAT_RGB565:
10021         case DRM_FORMAT_XRGB8888:
10022         case DRM_FORMAT_ARGB8888:
10023                 break;
10024         case DRM_FORMAT_XRGB1555:
10025         case DRM_FORMAT_ARGB1555:
10026                 if (INTEL_INFO(dev)->gen > 3) {
10027                         DRM_DEBUG("unsupported pixel format: %s\n",
10028                                   drm_get_format_name(mode_cmd->pixel_format));
10029                         return -EINVAL;
10030                 }
10031                 break;
10032         case DRM_FORMAT_XBGR8888:
10033         case DRM_FORMAT_ABGR8888:
10034         case DRM_FORMAT_XRGB2101010:
10035         case DRM_FORMAT_ARGB2101010:
10036         case DRM_FORMAT_XBGR2101010:
10037         case DRM_FORMAT_ABGR2101010:
10038                 if (INTEL_INFO(dev)->gen < 4) {
10039                         DRM_DEBUG("unsupported pixel format: %s\n",
10040                                   drm_get_format_name(mode_cmd->pixel_format));
10041                         return -EINVAL;
10042                 }
10043                 break;
10044         case DRM_FORMAT_YUYV:
10045         case DRM_FORMAT_UYVY:
10046         case DRM_FORMAT_YVYU:
10047         case DRM_FORMAT_VYUY:
10048                 if (INTEL_INFO(dev)->gen < 5) {
10049                         DRM_DEBUG("unsupported pixel format: %s\n",
10050                                   drm_get_format_name(mode_cmd->pixel_format));
10051                         return -EINVAL;
10052                 }
10053                 break;
10054         default:
10055                 DRM_DEBUG("unsupported pixel format: %s\n",
10056                           drm_get_format_name(mode_cmd->pixel_format));
10057                 return -EINVAL;
10058         }
10059
10060         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10061         if (mode_cmd->offsets[0] != 0)
10062                 return -EINVAL;
10063
10064         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10065         intel_fb->obj = obj;
10066
10067         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10068         if (ret) {
10069                 DRM_ERROR("framebuffer init failed %d\n", ret);
10070                 return ret;
10071         }
10072
10073         return 0;
10074 }
10075
10076 static struct drm_framebuffer *
10077 intel_user_framebuffer_create(struct drm_device *dev,
10078                               struct drm_file *filp,
10079                               struct drm_mode_fb_cmd2 *mode_cmd)
10080 {
10081         struct drm_i915_gem_object *obj;
10082
10083         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10084                                                 mode_cmd->handles[0]));
10085         if (&obj->base == NULL)
10086                 return ERR_PTR(-ENOENT);
10087
10088         return intel_framebuffer_create(dev, mode_cmd, obj);
10089 }
10090
10091 static const struct drm_mode_config_funcs intel_mode_funcs = {
10092         .fb_create = intel_user_framebuffer_create,
10093         .output_poll_changed = intel_fb_output_poll_changed,
10094 };
10095
10096 /* Set up chip specific display functions */
10097 static void intel_init_display(struct drm_device *dev)
10098 {
10099         struct drm_i915_private *dev_priv = dev->dev_private;
10100
10101         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10102                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10103         else if (IS_VALLEYVIEW(dev))
10104                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10105         else if (IS_PINEVIEW(dev))
10106                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10107         else
10108                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10109
10110         if (HAS_DDI(dev)) {
10111                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10112                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10113                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10114                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10115                 dev_priv->display.off = haswell_crtc_off;
10116                 dev_priv->display.update_plane = ironlake_update_plane;
10117         } else if (HAS_PCH_SPLIT(dev)) {
10118                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10119                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10120                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10121                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10122                 dev_priv->display.off = ironlake_crtc_off;
10123                 dev_priv->display.update_plane = ironlake_update_plane;
10124         } else if (IS_VALLEYVIEW(dev)) {
10125                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10126                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10127                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10128                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10129                 dev_priv->display.off = i9xx_crtc_off;
10130                 dev_priv->display.update_plane = i9xx_update_plane;
10131         } else {
10132                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10133                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10134                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10135                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10136                 dev_priv->display.off = i9xx_crtc_off;
10137                 dev_priv->display.update_plane = i9xx_update_plane;
10138         }
10139
10140         /* Returns the core display clock speed */
10141         if (IS_VALLEYVIEW(dev))
10142                 dev_priv->display.get_display_clock_speed =
10143                         valleyview_get_display_clock_speed;
10144         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10145                 dev_priv->display.get_display_clock_speed =
10146                         i945_get_display_clock_speed;
10147         else if (IS_I915G(dev))
10148                 dev_priv->display.get_display_clock_speed =
10149                         i915_get_display_clock_speed;
10150         else if (IS_I945GM(dev) || IS_845G(dev))
10151                 dev_priv->display.get_display_clock_speed =
10152                         i9xx_misc_get_display_clock_speed;
10153         else if (IS_PINEVIEW(dev))
10154                 dev_priv->display.get_display_clock_speed =
10155                         pnv_get_display_clock_speed;
10156         else if (IS_I915GM(dev))
10157                 dev_priv->display.get_display_clock_speed =
10158                         i915gm_get_display_clock_speed;
10159         else if (IS_I865G(dev))
10160                 dev_priv->display.get_display_clock_speed =
10161                         i865_get_display_clock_speed;
10162         else if (IS_I85X(dev))
10163                 dev_priv->display.get_display_clock_speed =
10164                         i855_get_display_clock_speed;
10165         else /* 852, 830 */
10166                 dev_priv->display.get_display_clock_speed =
10167                         i830_get_display_clock_speed;
10168
10169         if (HAS_PCH_SPLIT(dev)) {
10170                 if (IS_GEN5(dev)) {
10171                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10172                         dev_priv->display.write_eld = ironlake_write_eld;
10173                 } else if (IS_GEN6(dev)) {
10174                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10175                         dev_priv->display.write_eld = ironlake_write_eld;
10176                 } else if (IS_IVYBRIDGE(dev)) {
10177                         /* FIXME: detect B0+ stepping and use auto training */
10178                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10179                         dev_priv->display.write_eld = ironlake_write_eld;
10180                         dev_priv->display.modeset_global_resources =
10181                                 ivb_modeset_global_resources;
10182                 } else if (IS_HASWELL(dev)) {
10183                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10184                         dev_priv->display.write_eld = haswell_write_eld;
10185                         dev_priv->display.modeset_global_resources =
10186                                 haswell_modeset_global_resources;
10187                 }
10188         } else if (IS_G4X(dev)) {
10189                 dev_priv->display.write_eld = g4x_write_eld;
10190         }
10191
10192         /* Default just returns -ENODEV to indicate unsupported */
10193         dev_priv->display.queue_flip = intel_default_queue_flip;
10194
10195         switch (INTEL_INFO(dev)->gen) {
10196         case 2:
10197                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10198                 break;
10199
10200         case 3:
10201                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10202                 break;
10203
10204         case 4:
10205         case 5:
10206                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10207                 break;
10208
10209         case 6:
10210                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10211                 break;
10212         case 7:
10213                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10214                 break;
10215         }
10216 }
10217
10218 /*
10219  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10220  * resume, or other times.  This quirk makes sure that's the case for
10221  * affected systems.
10222  */
10223 static void quirk_pipea_force(struct drm_device *dev)
10224 {
10225         struct drm_i915_private *dev_priv = dev->dev_private;
10226
10227         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10228         DRM_INFO("applying pipe a force quirk\n");
10229 }
10230
10231 /*
10232  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10233  */
10234 static void quirk_ssc_force_disable(struct drm_device *dev)
10235 {
10236         struct drm_i915_private *dev_priv = dev->dev_private;
10237         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10238         DRM_INFO("applying lvds SSC disable quirk\n");
10239 }
10240
10241 /*
10242  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10243  * brightness value
10244  */
10245 static void quirk_invert_brightness(struct drm_device *dev)
10246 {
10247         struct drm_i915_private *dev_priv = dev->dev_private;
10248         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10249         DRM_INFO("applying inverted panel brightness quirk\n");
10250 }
10251
10252 /*
10253  * Some machines (Dell XPS13) suffer broken backlight controls if
10254  * BLM_PCH_PWM_ENABLE is set.
10255  */
10256 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10257 {
10258         struct drm_i915_private *dev_priv = dev->dev_private;
10259         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10260         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10261 }
10262
10263 struct intel_quirk {
10264         int device;
10265         int subsystem_vendor;
10266         int subsystem_device;
10267         void (*hook)(struct drm_device *dev);
10268 };
10269
10270 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10271 struct intel_dmi_quirk {
10272         void (*hook)(struct drm_device *dev);
10273         const struct dmi_system_id (*dmi_id_list)[];
10274 };
10275
10276 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10277 {
10278         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10279         return 1;
10280 }
10281
10282 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10283         {
10284                 .dmi_id_list = &(const struct dmi_system_id[]) {
10285                         {
10286                                 .callback = intel_dmi_reverse_brightness,
10287                                 .ident = "NCR Corporation",
10288                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10289                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10290                                 },
10291                         },
10292                         { }  /* terminating entry */
10293                 },
10294                 .hook = quirk_invert_brightness,
10295         },
10296 };
10297
10298 static struct intel_quirk intel_quirks[] = {
10299         /* HP Mini needs pipe A force quirk (LP: #322104) */
10300         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10301
10302         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10303         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10304
10305         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10306         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10307
10308         /* 830 needs to leave pipe A & dpll A up */
10309         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10310
10311         /* Lenovo U160 cannot use SSC on LVDS */
10312         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10313
10314         /* Sony Vaio Y cannot use SSC on LVDS */
10315         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10316
10317         /*
10318          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10319          * seem to use inverted backlight PWM.
10320          */
10321         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10322
10323         /* Dell XPS13 HD Sandy Bridge */
10324         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10325         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10326         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10327 };
10328
10329 static void intel_init_quirks(struct drm_device *dev)
10330 {
10331         struct pci_dev *d = dev->pdev;
10332         int i;
10333
10334         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10335                 struct intel_quirk *q = &intel_quirks[i];
10336
10337                 if (d->device == q->device &&
10338                     (d->subsystem_vendor == q->subsystem_vendor ||
10339                      q->subsystem_vendor == PCI_ANY_ID) &&
10340                     (d->subsystem_device == q->subsystem_device ||
10341                      q->subsystem_device == PCI_ANY_ID))
10342                         q->hook(dev);
10343         }
10344         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10345                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10346                         intel_dmi_quirks[i].hook(dev);
10347         }
10348 }
10349
10350 /* Disable the VGA plane that we never use */
10351 static void i915_disable_vga(struct drm_device *dev)
10352 {
10353         struct drm_i915_private *dev_priv = dev->dev_private;
10354         u8 sr1;
10355         u32 vga_reg = i915_vgacntrl_reg(dev);
10356
10357         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10358         outb(SR01, VGA_SR_INDEX);
10359         sr1 = inb(VGA_SR_DATA);
10360         outb(sr1 | 1<<5, VGA_SR_DATA);
10361         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10362         udelay(300);
10363
10364         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10365         POSTING_READ(vga_reg);
10366 }
10367
10368 static void i915_enable_vga_mem(struct drm_device *dev)
10369 {
10370         /* Enable VGA memory on Intel HD */
10371         if (HAS_PCH_SPLIT(dev)) {
10372                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10373                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10374                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10375                                                    VGA_RSRC_LEGACY_MEM |
10376                                                    VGA_RSRC_NORMAL_IO |
10377                                                    VGA_RSRC_NORMAL_MEM);
10378                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10379         }
10380 }
10381
10382 void i915_disable_vga_mem(struct drm_device *dev)
10383 {
10384         /* Disable VGA memory on Intel HD */
10385         if (HAS_PCH_SPLIT(dev)) {
10386                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10387                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10388                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10389                                                    VGA_RSRC_NORMAL_IO |
10390                                                    VGA_RSRC_NORMAL_MEM);
10391                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10392         }
10393 }
10394
10395 void intel_modeset_init_hw(struct drm_device *dev)
10396 {
10397         struct drm_i915_private *dev_priv = dev->dev_private;
10398
10399         intel_prepare_ddi(dev);
10400
10401         intel_init_clock_gating(dev);
10402
10403         /* Enable the CRI clock source so we can get at the display */
10404         if (IS_VALLEYVIEW(dev))
10405                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10406                            DPLL_INTEGRATED_CRI_CLK_VLV);
10407
10408         intel_init_dpio(dev);
10409
10410         mutex_lock(&dev->struct_mutex);
10411         intel_enable_gt_powersave(dev);
10412         mutex_unlock(&dev->struct_mutex);
10413 }
10414
10415 void intel_modeset_suspend_hw(struct drm_device *dev)
10416 {
10417         intel_suspend_hw(dev);
10418 }
10419
10420 void intel_modeset_init(struct drm_device *dev)
10421 {
10422         struct drm_i915_private *dev_priv = dev->dev_private;
10423         int i, j, ret;
10424
10425         drm_mode_config_init(dev);
10426
10427         dev->mode_config.min_width = 0;
10428         dev->mode_config.min_height = 0;
10429
10430         dev->mode_config.preferred_depth = 24;
10431         dev->mode_config.prefer_shadow = 1;
10432
10433         dev->mode_config.funcs = &intel_mode_funcs;
10434
10435         intel_init_quirks(dev);
10436
10437         intel_init_pm(dev);
10438
10439         if (INTEL_INFO(dev)->num_pipes == 0)
10440                 return;
10441
10442         intel_init_display(dev);
10443
10444         if (IS_GEN2(dev)) {
10445                 dev->mode_config.max_width = 2048;
10446                 dev->mode_config.max_height = 2048;
10447         } else if (IS_GEN3(dev)) {
10448                 dev->mode_config.max_width = 4096;
10449                 dev->mode_config.max_height = 4096;
10450         } else {
10451                 dev->mode_config.max_width = 8192;
10452                 dev->mode_config.max_height = 8192;
10453         }
10454         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10455
10456         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10457                       INTEL_INFO(dev)->num_pipes,
10458                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10459
10460         for_each_pipe(i) {
10461                 intel_crtc_init(dev, i);
10462                 for (j = 0; j < dev_priv->num_plane; j++) {
10463                         ret = intel_plane_init(dev, i, j);
10464                         if (ret)
10465                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10466                                               pipe_name(i), sprite_name(i, j), ret);
10467                 }
10468         }
10469
10470         intel_cpu_pll_init(dev);
10471         intel_shared_dpll_init(dev);
10472
10473         /* Just disable it once at startup */
10474         i915_disable_vga(dev);
10475         intel_setup_outputs(dev);
10476
10477         /* Just in case the BIOS is doing something questionable. */
10478         intel_disable_fbc(dev);
10479 }
10480
10481 static void
10482 intel_connector_break_all_links(struct intel_connector *connector)
10483 {
10484         connector->base.dpms = DRM_MODE_DPMS_OFF;
10485         connector->base.encoder = NULL;
10486         connector->encoder->connectors_active = false;
10487         connector->encoder->base.crtc = NULL;
10488 }
10489
10490 static void intel_enable_pipe_a(struct drm_device *dev)
10491 {
10492         struct intel_connector *connector;
10493         struct drm_connector *crt = NULL;
10494         struct intel_load_detect_pipe load_detect_temp;
10495
10496         /* We can't just switch on the pipe A, we need to set things up with a
10497          * proper mode and output configuration. As a gross hack, enable pipe A
10498          * by enabling the load detect pipe once. */
10499         list_for_each_entry(connector,
10500                             &dev->mode_config.connector_list,
10501                             base.head) {
10502                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10503                         crt = &connector->base;
10504                         break;
10505                 }
10506         }
10507
10508         if (!crt)
10509                 return;
10510
10511         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10512                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10513
10514
10515 }
10516
10517 static bool
10518 intel_check_plane_mapping(struct intel_crtc *crtc)
10519 {
10520         struct drm_device *dev = crtc->base.dev;
10521         struct drm_i915_private *dev_priv = dev->dev_private;
10522         u32 reg, val;
10523
10524         if (INTEL_INFO(dev)->num_pipes == 1)
10525                 return true;
10526
10527         reg = DSPCNTR(!crtc->plane);
10528         val = I915_READ(reg);
10529
10530         if ((val & DISPLAY_PLANE_ENABLE) &&
10531             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10532                 return false;
10533
10534         return true;
10535 }
10536
10537 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10538 {
10539         struct drm_device *dev = crtc->base.dev;
10540         struct drm_i915_private *dev_priv = dev->dev_private;
10541         u32 reg;
10542
10543         /* Clear any frame start delays used for debugging left by the BIOS */
10544         reg = PIPECONF(crtc->config.cpu_transcoder);
10545         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10546
10547         /* We need to sanitize the plane -> pipe mapping first because this will
10548          * disable the crtc (and hence change the state) if it is wrong. Note
10549          * that gen4+ has a fixed plane -> pipe mapping.  */
10550         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10551                 struct intel_connector *connector;
10552                 bool plane;
10553
10554                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10555                               crtc->base.base.id);
10556
10557                 /* Pipe has the wrong plane attached and the plane is active.
10558                  * Temporarily change the plane mapping and disable everything
10559                  * ...  */
10560                 plane = crtc->plane;
10561                 crtc->plane = !plane;
10562                 dev_priv->display.crtc_disable(&crtc->base);
10563                 crtc->plane = plane;
10564
10565                 /* ... and break all links. */
10566                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10567                                     base.head) {
10568                         if (connector->encoder->base.crtc != &crtc->base)
10569                                 continue;
10570
10571                         intel_connector_break_all_links(connector);
10572                 }
10573
10574                 WARN_ON(crtc->active);
10575                 crtc->base.enabled = false;
10576         }
10577
10578         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10579             crtc->pipe == PIPE_A && !crtc->active) {
10580                 /* BIOS forgot to enable pipe A, this mostly happens after
10581                  * resume. Force-enable the pipe to fix this, the update_dpms
10582                  * call below we restore the pipe to the right state, but leave
10583                  * the required bits on. */
10584                 intel_enable_pipe_a(dev);
10585         }
10586
10587         /* Adjust the state of the output pipe according to whether we
10588          * have active connectors/encoders. */
10589         intel_crtc_update_dpms(&crtc->base);
10590
10591         if (crtc->active != crtc->base.enabled) {
10592                 struct intel_encoder *encoder;
10593
10594                 /* This can happen either due to bugs in the get_hw_state
10595                  * functions or because the pipe is force-enabled due to the
10596                  * pipe A quirk. */
10597                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10598                               crtc->base.base.id,
10599                               crtc->base.enabled ? "enabled" : "disabled",
10600                               crtc->active ? "enabled" : "disabled");
10601
10602                 crtc->base.enabled = crtc->active;
10603
10604                 /* Because we only establish the connector -> encoder ->
10605                  * crtc links if something is active, this means the
10606                  * crtc is now deactivated. Break the links. connector
10607                  * -> encoder links are only establish when things are
10608                  *  actually up, hence no need to break them. */
10609                 WARN_ON(crtc->active);
10610
10611                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10612                         WARN_ON(encoder->connectors_active);
10613                         encoder->base.crtc = NULL;
10614                 }
10615         }
10616 }
10617
10618 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10619 {
10620         struct intel_connector *connector;
10621         struct drm_device *dev = encoder->base.dev;
10622
10623         /* We need to check both for a crtc link (meaning that the
10624          * encoder is active and trying to read from a pipe) and the
10625          * pipe itself being active. */
10626         bool has_active_crtc = encoder->base.crtc &&
10627                 to_intel_crtc(encoder->base.crtc)->active;
10628
10629         if (encoder->connectors_active && !has_active_crtc) {
10630                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10631                               encoder->base.base.id,
10632                               drm_get_encoder_name(&encoder->base));
10633
10634                 /* Connector is active, but has no active pipe. This is
10635                  * fallout from our resume register restoring. Disable
10636                  * the encoder manually again. */
10637                 if (encoder->base.crtc) {
10638                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10639                                       encoder->base.base.id,
10640                                       drm_get_encoder_name(&encoder->base));
10641                         encoder->disable(encoder);
10642                 }
10643
10644                 /* Inconsistent output/port/pipe state happens presumably due to
10645                  * a bug in one of the get_hw_state functions. Or someplace else
10646                  * in our code, like the register restore mess on resume. Clamp
10647                  * things to off as a safer default. */
10648                 list_for_each_entry(connector,
10649                                     &dev->mode_config.connector_list,
10650                                     base.head) {
10651                         if (connector->encoder != encoder)
10652                                 continue;
10653
10654                         intel_connector_break_all_links(connector);
10655                 }
10656         }
10657         /* Enabled encoders without active connectors will be fixed in
10658          * the crtc fixup. */
10659 }
10660
10661 void i915_redisable_vga(struct drm_device *dev)
10662 {
10663         struct drm_i915_private *dev_priv = dev->dev_private;
10664         u32 vga_reg = i915_vgacntrl_reg(dev);
10665
10666         /* This function can be called both from intel_modeset_setup_hw_state or
10667          * at a very early point in our resume sequence, where the power well
10668          * structures are not yet restored. Since this function is at a very
10669          * paranoid "someone might have enabled VGA while we were not looking"
10670          * level, just check if the power well is enabled instead of trying to
10671          * follow the "don't touch the power well if we don't need it" policy
10672          * the rest of the driver uses. */
10673         if (HAS_POWER_WELL(dev) &&
10674             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10675                 return;
10676
10677         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10678                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10679                 i915_disable_vga(dev);
10680                 i915_disable_vga_mem(dev);
10681         }
10682 }
10683
10684 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10685 {
10686         struct drm_i915_private *dev_priv = dev->dev_private;
10687         enum pipe pipe;
10688         struct intel_crtc *crtc;
10689         struct intel_encoder *encoder;
10690         struct intel_connector *connector;
10691         int i;
10692
10693         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10694                             base.head) {
10695                 memset(&crtc->config, 0, sizeof(crtc->config));
10696
10697                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10698                                                                  &crtc->config);
10699
10700                 crtc->base.enabled = crtc->active;
10701
10702                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10703                               crtc->base.base.id,
10704                               crtc->active ? "enabled" : "disabled");
10705         }
10706
10707         /* FIXME: Smash this into the new shared dpll infrastructure. */
10708         if (HAS_DDI(dev))
10709                 intel_ddi_setup_hw_pll_state(dev);
10710
10711         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10712                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10713
10714                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10715                 pll->active = 0;
10716                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10717                                     base.head) {
10718                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10719                                 pll->active++;
10720                 }
10721                 pll->refcount = pll->active;
10722
10723                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10724                               pll->name, pll->refcount, pll->on);
10725         }
10726
10727         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10728                             base.head) {
10729                 pipe = 0;
10730
10731                 if (encoder->get_hw_state(encoder, &pipe)) {
10732                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10733                         encoder->base.crtc = &crtc->base;
10734                         if (encoder->get_config)
10735                                 encoder->get_config(encoder, &crtc->config);
10736                 } else {
10737                         encoder->base.crtc = NULL;
10738                 }
10739
10740                 encoder->connectors_active = false;
10741                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10742                               encoder->base.base.id,
10743                               drm_get_encoder_name(&encoder->base),
10744                               encoder->base.crtc ? "enabled" : "disabled",
10745                               pipe);
10746         }
10747
10748         list_for_each_entry(connector, &dev->mode_config.connector_list,
10749                             base.head) {
10750                 if (connector->get_hw_state(connector)) {
10751                         connector->base.dpms = DRM_MODE_DPMS_ON;
10752                         connector->encoder->connectors_active = true;
10753                         connector->base.encoder = &connector->encoder->base;
10754                 } else {
10755                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10756                         connector->base.encoder = NULL;
10757                 }
10758                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10759                               connector->base.base.id,
10760                               drm_get_connector_name(&connector->base),
10761                               connector->base.encoder ? "enabled" : "disabled");
10762         }
10763 }
10764
10765 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10766  * and i915 state tracking structures. */
10767 void intel_modeset_setup_hw_state(struct drm_device *dev,
10768                                   bool force_restore)
10769 {
10770         struct drm_i915_private *dev_priv = dev->dev_private;
10771         enum pipe pipe;
10772         struct intel_crtc *crtc;
10773         struct intel_encoder *encoder;
10774         int i;
10775
10776         intel_modeset_readout_hw_state(dev);
10777
10778         /*
10779          * Now that we have the config, copy it to each CRTC struct
10780          * Note that this could go away if we move to using crtc_config
10781          * checking everywhere.
10782          */
10783         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10784                             base.head) {
10785                 if (crtc->active && i915_fastboot) {
10786                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10787
10788                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10789                                       crtc->base.base.id);
10790                         drm_mode_debug_printmodeline(&crtc->base.mode);
10791                 }
10792         }
10793
10794         /* HW state is read out, now we need to sanitize this mess. */
10795         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10796                             base.head) {
10797                 intel_sanitize_encoder(encoder);
10798         }
10799
10800         for_each_pipe(pipe) {
10801                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10802                 intel_sanitize_crtc(crtc);
10803                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10804         }
10805
10806         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10807                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10808
10809                 if (!pll->on || pll->active)
10810                         continue;
10811
10812                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10813
10814                 pll->disable(dev_priv, pll);
10815                 pll->on = false;
10816         }
10817
10818         if (force_restore) {
10819                 i915_redisable_vga(dev);
10820
10821                 /*
10822                  * We need to use raw interfaces for restoring state to avoid
10823                  * checking (bogus) intermediate states.
10824                  */
10825                 for_each_pipe(pipe) {
10826                         struct drm_crtc *crtc =
10827                                 dev_priv->pipe_to_crtc_mapping[pipe];
10828
10829                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10830                                          crtc->fb);
10831                 }
10832         } else {
10833                 intel_modeset_update_staged_output_state(dev);
10834         }
10835
10836         intel_modeset_check_state(dev);
10837
10838         drm_mode_config_reset(dev);
10839 }
10840
10841 void intel_modeset_gem_init(struct drm_device *dev)
10842 {
10843         intel_modeset_init_hw(dev);
10844
10845         intel_setup_overlay(dev);
10846
10847         intel_modeset_setup_hw_state(dev, false);
10848 }
10849
10850 void intel_modeset_cleanup(struct drm_device *dev)
10851 {
10852         struct drm_i915_private *dev_priv = dev->dev_private;
10853         struct drm_crtc *crtc;
10854         struct drm_connector *connector;
10855
10856         /*
10857          * Interrupts and polling as the first thing to avoid creating havoc.
10858          * Too much stuff here (turning of rps, connectors, ...) would
10859          * experience fancy races otherwise.
10860          */
10861         drm_irq_uninstall(dev);
10862         cancel_work_sync(&dev_priv->hotplug_work);
10863         /*
10864          * Due to the hpd irq storm handling the hotplug work can re-arm the
10865          * poll handlers. Hence disable polling after hpd handling is shut down.
10866          */
10867         drm_kms_helper_poll_fini(dev);
10868
10869         mutex_lock(&dev->struct_mutex);
10870
10871         intel_unregister_dsm_handler();
10872
10873         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10874                 /* Skip inactive CRTCs */
10875                 if (!crtc->fb)
10876                         continue;
10877
10878                 intel_increase_pllclock(crtc);
10879         }
10880
10881         intel_disable_fbc(dev);
10882
10883         i915_enable_vga_mem(dev);
10884
10885         intel_disable_gt_powersave(dev);
10886
10887         ironlake_teardown_rc6(dev);
10888
10889         mutex_unlock(&dev->struct_mutex);
10890
10891         /* flush any delayed tasks or pending work */
10892         flush_scheduled_work();
10893
10894         /* destroy backlight, if any, before the connectors */
10895         intel_panel_destroy_backlight(dev);
10896
10897         /* destroy the sysfs files before encoders/connectors */
10898         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10899                 drm_sysfs_connector_remove(connector);
10900
10901         drm_mode_config_cleanup(dev);
10902
10903         intel_cleanup_overlay(dev);
10904 }
10905
10906 /*
10907  * Return which encoder is currently attached for connector.
10908  */
10909 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10910 {
10911         return &intel_attached_encoder(connector)->base;
10912 }
10913
10914 void intel_connector_attach_encoder(struct intel_connector *connector,
10915                                     struct intel_encoder *encoder)
10916 {
10917         connector->encoder = encoder;
10918         drm_mode_connector_attach_encoder(&connector->base,
10919                                           &encoder->base);
10920 }
10921
10922 /*
10923  * set vga decode state - true == enable VGA decode
10924  */
10925 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10926 {
10927         struct drm_i915_private *dev_priv = dev->dev_private;
10928         u16 gmch_ctrl;
10929
10930         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10931         if (state)
10932                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10933         else
10934                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10935         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10936         return 0;
10937 }
10938
10939 struct intel_display_error_state {
10940
10941         u32 power_well_driver;
10942
10943         int num_transcoders;
10944
10945         struct intel_cursor_error_state {
10946                 u32 control;
10947                 u32 position;
10948                 u32 base;
10949                 u32 size;
10950         } cursor[I915_MAX_PIPES];
10951
10952         struct intel_pipe_error_state {
10953                 u32 source;
10954         } pipe[I915_MAX_PIPES];
10955
10956         struct intel_plane_error_state {
10957                 u32 control;
10958                 u32 stride;
10959                 u32 size;
10960                 u32 pos;
10961                 u32 addr;
10962                 u32 surface;
10963                 u32 tile_offset;
10964         } plane[I915_MAX_PIPES];
10965
10966         struct intel_transcoder_error_state {
10967                 enum transcoder cpu_transcoder;
10968
10969                 u32 conf;
10970
10971                 u32 htotal;
10972                 u32 hblank;
10973                 u32 hsync;
10974                 u32 vtotal;
10975                 u32 vblank;
10976                 u32 vsync;
10977         } transcoder[4];
10978 };
10979
10980 struct intel_display_error_state *
10981 intel_display_capture_error_state(struct drm_device *dev)
10982 {
10983         drm_i915_private_t *dev_priv = dev->dev_private;
10984         struct intel_display_error_state *error;
10985         int transcoders[] = {
10986                 TRANSCODER_A,
10987                 TRANSCODER_B,
10988                 TRANSCODER_C,
10989                 TRANSCODER_EDP,
10990         };
10991         int i;
10992
10993         if (INTEL_INFO(dev)->num_pipes == 0)
10994                 return NULL;
10995
10996         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10997         if (error == NULL)
10998                 return NULL;
10999
11000         if (HAS_POWER_WELL(dev))
11001                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11002
11003         for_each_pipe(i) {
11004                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11005                         error->cursor[i].control = I915_READ(CURCNTR(i));
11006                         error->cursor[i].position = I915_READ(CURPOS(i));
11007                         error->cursor[i].base = I915_READ(CURBASE(i));
11008                 } else {
11009                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11010                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11011                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11012                 }
11013
11014                 error->plane[i].control = I915_READ(DSPCNTR(i));
11015                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11016                 if (INTEL_INFO(dev)->gen <= 3) {
11017                         error->plane[i].size = I915_READ(DSPSIZE(i));
11018                         error->plane[i].pos = I915_READ(DSPPOS(i));
11019                 }
11020                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11021                         error->plane[i].addr = I915_READ(DSPADDR(i));
11022                 if (INTEL_INFO(dev)->gen >= 4) {
11023                         error->plane[i].surface = I915_READ(DSPSURF(i));
11024                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11025                 }
11026
11027                 error->pipe[i].source = I915_READ(PIPESRC(i));
11028         }
11029
11030         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11031         if (HAS_DDI(dev_priv->dev))
11032                 error->num_transcoders++; /* Account for eDP. */
11033
11034         for (i = 0; i < error->num_transcoders; i++) {
11035                 enum transcoder cpu_transcoder = transcoders[i];
11036
11037                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11038
11039                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11040                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11041                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11042                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11043                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11044                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11045                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11046         }
11047
11048         /* In the code above we read the registers without checking if the power
11049          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11050          * prevent the next I915_WRITE from detecting it and printing an error
11051          * message. */
11052         intel_uncore_clear_errors(dev);
11053
11054         return error;
11055 }
11056
11057 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11058
11059 void
11060 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11061                                 struct drm_device *dev,
11062                                 struct intel_display_error_state *error)
11063 {
11064         int i;
11065
11066         if (!error)
11067                 return;
11068
11069         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11070         if (HAS_POWER_WELL(dev))
11071                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11072                            error->power_well_driver);
11073         for_each_pipe(i) {
11074                 err_printf(m, "Pipe [%d]:\n", i);
11075                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11076
11077                 err_printf(m, "Plane [%d]:\n", i);
11078                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11079                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11080                 if (INTEL_INFO(dev)->gen <= 3) {
11081                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11082                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11083                 }
11084                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11085                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11086                 if (INTEL_INFO(dev)->gen >= 4) {
11087                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11088                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11089                 }
11090
11091                 err_printf(m, "Cursor [%d]:\n", i);
11092                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11093                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11094                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11095         }
11096
11097         for (i = 0; i < error->num_transcoders; i++) {
11098                 err_printf(m, "  CPU transcoder: %c\n",
11099                            transcoder_name(error->transcoder[i].cpu_transcoder));
11100                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11101                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11102                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11103                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11104                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11105                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11106                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11107         }
11108 }