Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 static void assert_pll(struct drm_i915_private *dev_priv,
 896                        enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 910 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 911
 912 /* For ILK+ */
 913 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 914                            struct intel_pch_pll *pll,
 915                            struct intel_crtc *crtc,
 916                            bool state)
 917 {
 918         u32 val;
 919         bool cur_state;
 920
 921         if (HAS_PCH_LPT(dev_priv->dev)) {
 922                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 923                 return;
 924         }
 925
 926         if (WARN (!pll,
 927                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 928                 return;
 929
 930         val = I915_READ(pll->pll_reg);
 931         cur_state = !!(val & DPLL_VCO_ENABLE);
 932         WARN(cur_state != state,
 933              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 934              pll->pll_reg, state_string(state), state_string(cur_state), val);
 935
 936         /* Make sure the selected PLL is correctly attached to the transcoder */
 937         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 938                 u32 pch_dpll;
 939
 940                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 941                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 942                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 943                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 944                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 945                         cur_state = !!(val >> (4*crtc->pipe + 3));
 946                         WARN(cur_state != state,
 947                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 948                              pll->pll_reg == _PCH_DPLL_B,
 949                              state_string(state),
 950                              pipe_name(crtc->pipe),
 951                              val);
 952                 }
 953         }
 954 }
 955 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 956 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 957
 958 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 959                           enum pipe pipe, bool state)
 960 {
 961         int reg;
 962         u32 val;
 963         bool cur_state;
 964         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 965                                                                       pipe);
 966
 967         if (HAS_DDI(dev_priv->dev)) {
 968                 /* DDI does not have a specific FDI_TX register */
 969                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 970                 val = I915_READ(reg);
 971                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 972         } else {
 973                 reg = FDI_TX_CTL(pipe);
 974                 val = I915_READ(reg);
 975                 cur_state = !!(val & FDI_TX_ENABLE);
 976         }
 977         WARN(cur_state != state,
 978              "FDI TX state assertion failure (expected %s, current %s)\n",
 979              state_string(state), state_string(cur_state));
 980 }
 981 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 982 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 983
 984 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 985                           enum pipe pipe, bool state)
 986 {
 987         int reg;
 988         u32 val;
 989         bool cur_state;
 990
 991         reg = FDI_RX_CTL(pipe);
 992         val = I915_READ(reg);
 993         cur_state = !!(val & FDI_RX_ENABLE);
 994         WARN(cur_state != state,
 995              "FDI RX state assertion failure (expected %s, current %s)\n",
 996              state_string(state), state_string(cur_state));
 997 }
 998 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 999 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002                                       enum pipe pipe)
1003 {
1004         int reg;
1005         u32 val;
1006
1007         /* ILK FDI PLL is always enabled */
1008         if (dev_priv->info->gen == 5)
1009                 return;
1010
1011         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1012         if (HAS_DDI(dev_priv->dev))
1013                 return;
1014
1015         reg = FDI_TX_CTL(pipe);
1016         val = I915_READ(reg);
1017         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018 }
1019
1020 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         reg = FDI_RX_CTL(pipe);
1027         val = I915_READ(reg);
1028         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029 }
1030
1031 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032                                   enum pipe pipe)
1033 {
1034         int pp_reg, lvds_reg;
1035         u32 val;
1036         enum pipe panel_pipe = PIPE_A;
1037         bool locked = true;
1038
1039         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040                 pp_reg = PCH_PP_CONTROL;
1041                 lvds_reg = PCH_LVDS;
1042         } else {
1043                 pp_reg = PP_CONTROL;
1044                 lvds_reg = LVDS;
1045         }
1046
1047         val = I915_READ(pp_reg);
1048         if (!(val & PANEL_POWER_ON) ||
1049             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050                 locked = false;
1051
1052         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053                 panel_pipe = PIPE_B;
1054
1055         WARN(panel_pipe == pipe && locked,
1056              "panel assertion failure, pipe %c regs locked\n",
1057              pipe_name(pipe));
1058 }
1059
1060 void assert_pipe(struct drm_i915_private *dev_priv,
1061                  enum pipe pipe, bool state)
1062 {
1063         int reg;
1064         u32 val;
1065         bool cur_state;
1066         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067                                                                       pipe);
1068
1069         /* if we need the pipe A quirk it must be always on */
1070         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071                 state = true;
1072
1073         if (!intel_display_power_enabled(dev_priv->dev,
1074                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1075                 cur_state = false;
1076         } else {
1077                 reg = PIPECONF(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & PIPECONF_ENABLE);
1080         }
1081
1082         WARN(cur_state != state,
1083              "pipe %c assertion failure (expected %s, current %s)\n",
1084              pipe_name(pipe), state_string(state), state_string(cur_state));
1085 }
1086
1087 static void assert_plane(struct drm_i915_private *dev_priv,
1088                          enum plane plane, bool state)
1089 {
1090         int reg;
1091         u32 val;
1092         bool cur_state;
1093
1094         reg = DSPCNTR(plane);
1095         val = I915_READ(reg);
1096         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097         WARN(cur_state != state,
1098              "plane %c assertion failure (expected %s, current %s)\n",
1099              plane_name(plane), state_string(state), state_string(cur_state));
1100 }
1101
1102 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
1105 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106                                    enum pipe pipe)
1107 {
1108         struct drm_device *dev = dev_priv->dev;
1109         int reg, i;
1110         u32 val;
1111         int cur_pipe;
1112
1113         /* Primary planes are fixed to pipes on gen4+ */
1114         if (INTEL_INFO(dev)->gen >= 4) {
1115                 reg = DSPCNTR(pipe);
1116                 val = I915_READ(reg);
1117                 WARN((val & DISPLAY_PLANE_ENABLE),
1118                      "plane %c assertion failure, should be disabled but not\n",
1119                      plane_name(pipe));
1120                 return;
1121         }
1122
1123         /* Need to check both planes against the pipe */
1124         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1125                 reg = DSPCNTR(i);
1126                 val = I915_READ(reg);
1127                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1128                         DISPPLANE_SEL_PIPE_SHIFT;
1129                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1130                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1131                      plane_name(i), pipe_name(pipe));
1132         }
1133 }
1134
1135 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1136                                     enum pipe pipe)
1137 {
1138         struct drm_device *dev = dev_priv->dev;
1139         int reg, i;
1140         u32 val;
1141
1142         if (IS_VALLEYVIEW(dev)) {
1143                 for (i = 0; i < dev_priv->num_plane; i++) {
1144                         reg = SPCNTR(pipe, i);
1145                         val = I915_READ(reg);
1146                         WARN((val & SP_ENABLE),
1147                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1148                              sprite_name(pipe, i), pipe_name(pipe));
1149                 }
1150         } else if (INTEL_INFO(dev)->gen >= 7) {
1151                 reg = SPRCTL(pipe);
1152                 val = I915_READ(reg);
1153                 WARN((val & SPRITE_ENABLE),
1154                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1155                      plane_name(pipe), pipe_name(pipe));
1156         } else if (INTEL_INFO(dev)->gen >= 5) {
1157                 reg = DVSCNTR(pipe);
1158                 val = I915_READ(reg);
1159                 WARN((val & DVS_ENABLE),
1160                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1161                      plane_name(pipe), pipe_name(pipe));
1162         }
1163 }
1164
1165 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1166 {
1167         u32 val;
1168         bool enabled;
1169
1170         if (HAS_PCH_LPT(dev_priv->dev)) {
1171                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1172                 return;
1173         }
1174
1175         val = I915_READ(PCH_DREF_CONTROL);
1176         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1177                             DREF_SUPERSPREAD_SOURCE_MASK));
1178         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1179 }
1180
1181 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1182                                            enum pipe pipe)
1183 {
1184         int reg;
1185         u32 val;
1186         bool enabled;
1187
1188         reg = PCH_TRANSCONF(pipe);
1189         val = I915_READ(reg);
1190         enabled = !!(val & TRANS_ENABLE);
1191         WARN(enabled,
1192              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1193              pipe_name(pipe));
1194 }
1195
1196 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1197                             enum pipe pipe, u32 port_sel, u32 val)
1198 {
1199         if ((val & DP_PORT_EN) == 0)
1200                 return false;
1201
1202         if (HAS_PCH_CPT(dev_priv->dev)) {
1203                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1204                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1205                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1206                         return false;
1207         } else {
1208                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209                         return false;
1210         }
1211         return true;
1212 }
1213
1214 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1215                               enum pipe pipe, u32 val)
1216 {
1217         if ((val & SDVO_ENABLE) == 0)
1218                 return false;
1219
1220         if (HAS_PCH_CPT(dev_priv->dev)) {
1221                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1222                         return false;
1223         } else {
1224                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1225                         return false;
1226         }
1227         return true;
1228 }
1229
1230 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1231                               enum pipe pipe, u32 val)
1232 {
1233         if ((val & LVDS_PORT_EN) == 0)
1234                 return false;
1235
1236         if (HAS_PCH_CPT(dev_priv->dev)) {
1237                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238                         return false;
1239         } else {
1240                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241                         return false;
1242         }
1243         return true;
1244 }
1245
1246 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1247                               enum pipe pipe, u32 val)
1248 {
1249         if ((val & ADPA_DAC_ENABLE) == 0)
1250                 return false;
1251         if (HAS_PCH_CPT(dev_priv->dev)) {
1252                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1253                         return false;
1254         } else {
1255                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256                         return false;
1257         }
1258         return true;
1259 }
1260
1261 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1262                                    enum pipe pipe, int reg, u32 port_sel)
1263 {
1264         u32 val = I915_READ(reg);
1265         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1266              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1267              reg, pipe_name(pipe));
1268
1269         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1270              && (val & DP_PIPEB_SELECT),
1271              "IBX PCH dp port still using transcoder B\n");
1272 }
1273
1274 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1275                                      enum pipe pipe, int reg)
1276 {
1277         u32 val = I915_READ(reg);
1278         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1279              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1280              reg, pipe_name(pipe));
1281
1282         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1283              && (val & SDVO_PIPE_B_SELECT),
1284              "IBX PCH hdmi port still using transcoder B\n");
1285 }
1286
1287 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288                                       enum pipe pipe)
1289 {
1290         int reg;
1291         u32 val;
1292
1293         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1294         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1295         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1296
1297         reg = PCH_ADPA;
1298         val = I915_READ(reg);
1299         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1300              "PCH VGA enabled on transcoder %c, should be disabled\n",
1301              pipe_name(pipe));
1302
1303         reg = PCH_LVDS;
1304         val = I915_READ(reg);
1305         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1306              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1307              pipe_name(pipe));
1308
1309         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1310         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1311         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1312 }
1313
1314 /**
1315  * intel_enable_pll - enable a PLL
1316  * @dev_priv: i915 private structure
1317  * @pipe: pipe PLL to enable
1318  *
1319  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1320  * make sure the PLL reg is writable first though, since the panel write
1321  * protect mechanism may be enabled.
1322  *
1323  * Note!  This is for pre-ILK only.
1324  *
1325  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1326  */
1327 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328 {
1329         int reg;
1330         u32 val;
1331
1332         assert_pipe_disabled(dev_priv, pipe);
1333
1334         /* No really, not for ILK+ */
1335         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1336
1337         /* PLL is protected by panel, make sure we can write it */
1338         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1339                 assert_panel_unlocked(dev_priv, pipe);
1340
1341         reg = DPLL(pipe);
1342         val = I915_READ(reg);
1343         val |= DPLL_VCO_ENABLE;
1344
1345         /* We do this three times for luck */
1346         I915_WRITE(reg, val);
1347         POSTING_READ(reg);
1348         udelay(150); /* wait for warmup */
1349         I915_WRITE(reg, val);
1350         POSTING_READ(reg);
1351         udelay(150); /* wait for warmup */
1352         I915_WRITE(reg, val);
1353         POSTING_READ(reg);
1354         udelay(150); /* wait for warmup */
1355 }
1356
1357 /**
1358  * intel_disable_pll - disable a PLL
1359  * @dev_priv: i915 private structure
1360  * @pipe: pipe PLL to disable
1361  *
1362  * Disable the PLL for @pipe, making sure the pipe is off first.
1363  *
1364  * Note!  This is for pre-ILK only.
1365  */
1366 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1367 {
1368         int reg;
1369         u32 val;
1370
1371         /* Don't disable pipe A or pipe A PLLs if needed */
1372         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373                 return;
1374
1375         /* Make sure the pipe isn't still relying on us */
1376         assert_pipe_disabled(dev_priv, pipe);
1377
1378         reg = DPLL(pipe);
1379         val = I915_READ(reg);
1380         val &= ~DPLL_VCO_ENABLE;
1381         I915_WRITE(reg, val);
1382         POSTING_READ(reg);
1383 }
1384
1385 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1386 {
1387         u32 port_mask;
1388
1389         if (!port)
1390                 port_mask = DPLL_PORTB_READY_MASK;
1391         else
1392                 port_mask = DPLL_PORTC_READY_MASK;
1393
1394         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1395                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1396                      'B' + port, I915_READ(DPLL(0)));
1397 }
1398
1399 /**
1400  * ironlake_enable_pch_pll - enable PCH PLL
1401  * @dev_priv: i915 private structure
1402  * @pipe: pipe PLL to enable
1403  *
1404  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1405  * drives the transcoder clock.
1406  */
1407 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1408 {
1409         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1410         struct intel_pch_pll *pll;
1411         int reg;
1412         u32 val;
1413
1414         /* PCH PLLs only available on ILK, SNB and IVB */
1415         BUG_ON(dev_priv->info->gen < 5);
1416         pll = intel_crtc->pch_pll;
1417         if (pll == NULL)
1418                 return;
1419
1420         if (WARN_ON(pll->refcount == 0))
1421                 return;
1422
1423         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1424                       pll->pll_reg, pll->active, pll->on,
1425                       intel_crtc->base.base.id);
1426
1427         /* PCH refclock must be enabled first */
1428         assert_pch_refclk_enabled(dev_priv);
1429
1430         if (pll->active++ && pll->on) {
1431                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1432                 return;
1433         }
1434
1435         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1436
1437         reg = pll->pll_reg;
1438         val = I915_READ(reg);
1439         val |= DPLL_VCO_ENABLE;
1440         I915_WRITE(reg, val);
1441         POSTING_READ(reg);
1442         udelay(200);
1443
1444         pll->on = true;
1445 }
1446
1447 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1448 {
1449         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1450         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1451         int reg;
1452         u32 val;
1453
1454         /* PCH only available on ILK+ */
1455         BUG_ON(dev_priv->info->gen < 5);
1456         if (pll == NULL)
1457                return;
1458
1459         if (WARN_ON(pll->refcount == 0))
1460                 return;
1461
1462         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1463                       pll->pll_reg, pll->active, pll->on,
1464                       intel_crtc->base.base.id);
1465
1466         if (WARN_ON(pll->active == 0)) {
1467                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1468                 return;
1469         }
1470
1471         if (--pll->active) {
1472                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1473                 return;
1474         }
1475
1476         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1477
1478         /* Make sure transcoder isn't still depending on us */
1479         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1480
1481         reg = pll->pll_reg;
1482         val = I915_READ(reg);
1483         val &= ~DPLL_VCO_ENABLE;
1484         I915_WRITE(reg, val);
1485         POSTING_READ(reg);
1486         udelay(200);
1487
1488         pll->on = false;
1489 }
1490
1491 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492                                            enum pipe pipe)
1493 {
1494         struct drm_device *dev = dev_priv->dev;
1495         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1496         uint32_t reg, val, pipeconf_val;
1497
1498         /* PCH only available on ILK+ */
1499         BUG_ON(dev_priv->info->gen < 5);
1500
1501         /* Make sure PCH DPLL is enabled */
1502         assert_pch_pll_enabled(dev_priv,
1503                                to_intel_crtc(crtc)->pch_pll,
1504                                to_intel_crtc(crtc));
1505
1506         /* FDI must be feeding us bits for PCH ports */
1507         assert_fdi_tx_enabled(dev_priv, pipe);
1508         assert_fdi_rx_enabled(dev_priv, pipe);
1509
1510         if (HAS_PCH_CPT(dev)) {
1511                 /* Workaround: Set the timing override bit before enabling the
1512                  * pch transcoder. */
1513                 reg = TRANS_CHICKEN2(pipe);
1514                 val = I915_READ(reg);
1515                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516                 I915_WRITE(reg, val);
1517         }
1518
1519         reg = PCH_TRANSCONF(pipe);
1520         val = I915_READ(reg);
1521         pipeconf_val = I915_READ(PIPECONF(pipe));
1522
1523         if (HAS_PCH_IBX(dev_priv->dev)) {
1524                 /*
1525                  * make the BPC in transcoder be consistent with
1526                  * that in pipeconf reg.
1527                  */
1528                 val &= ~PIPECONF_BPC_MASK;
1529                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1530         }
1531
1532         val &= ~TRANS_INTERLACE_MASK;
1533         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1534                 if (HAS_PCH_IBX(dev_priv->dev) &&
1535                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536                         val |= TRANS_LEGACY_INTERLACED_ILK;
1537                 else
1538                         val |= TRANS_INTERLACED;
1539         else
1540                 val |= TRANS_PROGRESSIVE;
1541
1542         I915_WRITE(reg, val | TRANS_ENABLE);
1543         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1544                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1545 }
1546
1547 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1548                                       enum transcoder cpu_transcoder)
1549 {
1550         u32 val, pipeconf_val;
1551
1552         /* PCH only available on ILK+ */
1553         BUG_ON(dev_priv->info->gen < 5);
1554
1555         /* FDI must be feeding us bits for PCH ports */
1556         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1557         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1558
1559         /* Workaround: set timing override bit. */
1560         val = I915_READ(_TRANSA_CHICKEN2);
1561         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1562         I915_WRITE(_TRANSA_CHICKEN2, val);
1563
1564         val = TRANS_ENABLE;
1565         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1566
1567         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568             PIPECONF_INTERLACED_ILK)
1569                 val |= TRANS_INTERLACED;
1570         else
1571                 val |= TRANS_PROGRESSIVE;
1572
1573         I915_WRITE(LPT_TRANSCONF, val);
1574         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1575                 DRM_ERROR("Failed to enable PCH transcoder\n");
1576 }
1577
1578 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579                                             enum pipe pipe)
1580 {
1581         struct drm_device *dev = dev_priv->dev;
1582         uint32_t reg, val;
1583
1584         /* FDI relies on the transcoder */
1585         assert_fdi_tx_disabled(dev_priv, pipe);
1586         assert_fdi_rx_disabled(dev_priv, pipe);
1587
1588         /* Ports must be off as well */
1589         assert_pch_ports_disabled(dev_priv, pipe);
1590
1591         reg = PCH_TRANSCONF(pipe);
1592         val = I915_READ(reg);
1593         val &= ~TRANS_ENABLE;
1594         I915_WRITE(reg, val);
1595         /* wait for PCH transcoder off, transcoder state */
1596         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1597                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1598
1599         if (!HAS_PCH_IBX(dev)) {
1600                 /* Workaround: Clear the timing override chicken bit again. */
1601                 reg = TRANS_CHICKEN2(pipe);
1602                 val = I915_READ(reg);
1603                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604                 I915_WRITE(reg, val);
1605         }
1606 }
1607
1608 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1609 {
1610         u32 val;
1611
1612         val = I915_READ(LPT_TRANSCONF);
1613         val &= ~TRANS_ENABLE;
1614         I915_WRITE(LPT_TRANSCONF, val);
1615         /* wait for PCH transcoder off, transcoder state */
1616         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1617                 DRM_ERROR("Failed to disable PCH transcoder\n");
1618
1619         /* Workaround: clear timing override bit. */
1620         val = I915_READ(_TRANSA_CHICKEN2);
1621         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1622         I915_WRITE(_TRANSA_CHICKEN2, val);
1623 }
1624
1625 /**
1626  * intel_enable_pipe - enable a pipe, asserting requirements
1627  * @dev_priv: i915 private structure
1628  * @pipe: pipe to enable
1629  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1630  *
1631  * Enable @pipe, making sure that various hardware specific requirements
1632  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633  *
1634  * @pipe should be %PIPE_A or %PIPE_B.
1635  *
1636  * Will wait until the pipe is actually running (i.e. first vblank) before
1637  * returning.
1638  */
1639 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640                               bool pch_port)
1641 {
1642         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643                                                                       pipe);
1644         enum pipe pch_transcoder;
1645         int reg;
1646         u32 val;
1647
1648         assert_planes_disabled(dev_priv, pipe);
1649         assert_sprites_disabled(dev_priv, pipe);
1650
1651         if (HAS_PCH_LPT(dev_priv->dev))
1652                 pch_transcoder = TRANSCODER_A;
1653         else
1654                 pch_transcoder = pipe;
1655
1656         /*
1657          * A pipe without a PLL won't actually be able to drive bits from
1658          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1659          * need the check.
1660          */
1661         if (!HAS_PCH_SPLIT(dev_priv->dev))
1662                 assert_pll_enabled(dev_priv, pipe);
1663         else {
1664                 if (pch_port) {
1665                         /* if driving the PCH, we need FDI enabled */
1666                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1667                         assert_fdi_tx_pll_enabled(dev_priv,
1668                                                   (enum pipe) cpu_transcoder);
1669                 }
1670                 /* FIXME: assert CPU port conditions for SNB+ */
1671         }
1672
1673         reg = PIPECONF(cpu_transcoder);
1674         val = I915_READ(reg);
1675         if (val & PIPECONF_ENABLE)
1676                 return;
1677
1678         I915_WRITE(reg, val | PIPECONF_ENABLE);
1679         intel_wait_for_vblank(dev_priv->dev, pipe);
1680 }
1681
1682 /**
1683  * intel_disable_pipe - disable a pipe, asserting requirements
1684  * @dev_priv: i915 private structure
1685  * @pipe: pipe to disable
1686  *
1687  * Disable @pipe, making sure that various hardware specific requirements
1688  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689  *
1690  * @pipe should be %PIPE_A or %PIPE_B.
1691  *
1692  * Will wait until the pipe has shut down before returning.
1693  */
1694 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695                                enum pipe pipe)
1696 {
1697         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698                                                                       pipe);
1699         int reg;
1700         u32 val;
1701
1702         /*
1703          * Make sure planes won't keep trying to pump pixels to us,
1704          * or we might hang the display.
1705          */
1706         assert_planes_disabled(dev_priv, pipe);
1707         assert_sprites_disabled(dev_priv, pipe);
1708
1709         /* Don't disable pipe A or pipe A PLLs if needed */
1710         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711                 return;
1712
1713         reg = PIPECONF(cpu_transcoder);
1714         val = I915_READ(reg);
1715         if ((val & PIPECONF_ENABLE) == 0)
1716                 return;
1717
1718         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1719         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720 }
1721
1722 /*
1723  * Plane regs are double buffered, going from enabled->disabled needs a
1724  * trigger in order to latch.  The display address reg provides this.
1725  */
1726 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1727                                       enum plane plane)
1728 {
1729         if (dev_priv->info->gen >= 4)
1730                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731         else
1732                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1733 }
1734
1735 /**
1736  * intel_enable_plane - enable a display plane on a given pipe
1737  * @dev_priv: i915 private structure
1738  * @plane: plane to enable
1739  * @pipe: pipe being fed
1740  *
1741  * Enable @plane on @pipe, making sure that @pipe is running first.
1742  */
1743 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744                                enum plane plane, enum pipe pipe)
1745 {
1746         int reg;
1747         u32 val;
1748
1749         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750         assert_pipe_enabled(dev_priv, pipe);
1751
1752         reg = DSPCNTR(plane);
1753         val = I915_READ(reg);
1754         if (val & DISPLAY_PLANE_ENABLE)
1755                 return;
1756
1757         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1758         intel_flush_display_plane(dev_priv, plane);
1759         intel_wait_for_vblank(dev_priv->dev, pipe);
1760 }
1761
1762 /**
1763  * intel_disable_plane - disable a display plane
1764  * @dev_priv: i915 private structure
1765  * @plane: plane to disable
1766  * @pipe: pipe consuming the data
1767  *
1768  * Disable @plane; should be an independent operation.
1769  */
1770 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771                                 enum plane plane, enum pipe pipe)
1772 {
1773         int reg;
1774         u32 val;
1775
1776         reg = DSPCNTR(plane);
1777         val = I915_READ(reg);
1778         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779                 return;
1780
1781         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1782         intel_flush_display_plane(dev_priv, plane);
1783         intel_wait_for_vblank(dev_priv->dev, pipe);
1784 }
1785
1786 static bool need_vtd_wa(struct drm_device *dev)
1787 {
1788 #ifdef CONFIG_INTEL_IOMMU
1789         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790                 return true;
1791 #endif
1792         return false;
1793 }
1794
1795 int
1796 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1797                            struct drm_i915_gem_object *obj,
1798                            struct intel_ring_buffer *pipelined)
1799 {
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         u32 alignment;
1802         int ret;
1803
1804         switch (obj->tiling_mode) {
1805         case I915_TILING_NONE:
1806                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807                         alignment = 128 * 1024;
1808                 else if (INTEL_INFO(dev)->gen >= 4)
1809                         alignment = 4 * 1024;
1810                 else
1811                         alignment = 64 * 1024;
1812                 break;
1813         case I915_TILING_X:
1814                 /* pin() will align the object as required by fence */
1815                 alignment = 0;
1816                 break;
1817         case I915_TILING_Y:
1818                 /* Despite that we check this in framebuffer_init userspace can
1819                  * screw us over and change the tiling after the fact. Only
1820                  * pinned buffers can't change their tiling. */
1821                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1822                 return -EINVAL;
1823         default:
1824                 BUG();
1825         }
1826
1827         /* Note that the w/a also requires 64 PTE of padding following the
1828          * bo. We currently fill all unused PTE with the shadow page and so
1829          * we should always have valid PTE following the scanout preventing
1830          * the VT-d warning.
1831          */
1832         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833                 alignment = 256 * 1024;
1834
1835         dev_priv->mm.interruptible = false;
1836         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1837         if (ret)
1838                 goto err_interruptible;
1839
1840         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841          * fence, whereas 965+ only requires a fence if using
1842          * framebuffer compression.  For simplicity, we always install
1843          * a fence as the cost is not that onerous.
1844          */
1845         ret = i915_gem_object_get_fence(obj);
1846         if (ret)
1847                 goto err_unpin;
1848
1849         i915_gem_object_pin_fence(obj);
1850
1851         dev_priv->mm.interruptible = true;
1852         return 0;
1853
1854 err_unpin:
1855         i915_gem_object_unpin(obj);
1856 err_interruptible:
1857         dev_priv->mm.interruptible = true;
1858         return ret;
1859 }
1860
1861 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862 {
1863         i915_gem_object_unpin_fence(obj);
1864         i915_gem_object_unpin(obj);
1865 }
1866
1867 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868  * is assumed to be a power-of-two. */
1869 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870                                              unsigned int tiling_mode,
1871                                              unsigned int cpp,
1872                                              unsigned int pitch)
1873 {
1874         if (tiling_mode != I915_TILING_NONE) {
1875                 unsigned int tile_rows, tiles;
1876
1877                 tile_rows = *y / 8;
1878                 *y %= 8;
1879
1880                 tiles = *x / (512/cpp);
1881                 *x %= 512/cpp;
1882
1883                 return tile_rows * pitch * 8 + tiles * 4096;
1884         } else {
1885                 unsigned int offset;
1886
1887                 offset = *y * pitch + *x * cpp;
1888                 *y = 0;
1889                 *x = (offset & 4095) / cpp;
1890                 return offset & -4096;
1891         }
1892 }
1893
1894 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895                              int x, int y)
1896 {
1897         struct drm_device *dev = crtc->dev;
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900         struct intel_framebuffer *intel_fb;
1901         struct drm_i915_gem_object *obj;
1902         int plane = intel_crtc->plane;
1903         unsigned long linear_offset;
1904         u32 dspcntr;
1905         u32 reg;
1906
1907         switch (plane) {
1908         case 0:
1909         case 1:
1910                 break;
1911         default:
1912                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1913                 return -EINVAL;
1914         }
1915
1916         intel_fb = to_intel_framebuffer(fb);
1917         obj = intel_fb->obj;
1918
1919         reg = DSPCNTR(plane);
1920         dspcntr = I915_READ(reg);
1921         /* Mask out pixel format bits in case we change it */
1922         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1923         switch (fb->pixel_format) {
1924         case DRM_FORMAT_C8:
1925                 dspcntr |= DISPPLANE_8BPP;
1926                 break;
1927         case DRM_FORMAT_XRGB1555:
1928         case DRM_FORMAT_ARGB1555:
1929                 dspcntr |= DISPPLANE_BGRX555;
1930                 break;
1931         case DRM_FORMAT_RGB565:
1932                 dspcntr |= DISPPLANE_BGRX565;
1933                 break;
1934         case DRM_FORMAT_XRGB8888:
1935         case DRM_FORMAT_ARGB8888:
1936                 dspcntr |= DISPPLANE_BGRX888;
1937                 break;
1938         case DRM_FORMAT_XBGR8888:
1939         case DRM_FORMAT_ABGR8888:
1940                 dspcntr |= DISPPLANE_RGBX888;
1941                 break;
1942         case DRM_FORMAT_XRGB2101010:
1943         case DRM_FORMAT_ARGB2101010:
1944                 dspcntr |= DISPPLANE_BGRX101010;
1945                 break;
1946         case DRM_FORMAT_XBGR2101010:
1947         case DRM_FORMAT_ABGR2101010:
1948                 dspcntr |= DISPPLANE_RGBX101010;
1949                 break;
1950         default:
1951                 BUG();
1952         }
1953
1954         if (INTEL_INFO(dev)->gen >= 4) {
1955                 if (obj->tiling_mode != I915_TILING_NONE)
1956                         dspcntr |= DISPPLANE_TILED;
1957                 else
1958                         dspcntr &= ~DISPPLANE_TILED;
1959         }
1960
1961         if (IS_G4X(dev))
1962                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1963
1964         I915_WRITE(reg, dspcntr);
1965
1966         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1967
1968         if (INTEL_INFO(dev)->gen >= 4) {
1969                 intel_crtc->dspaddr_offset =
1970                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1971                                                        fb->bits_per_pixel / 8,
1972                                                        fb->pitches[0]);
1973                 linear_offset -= intel_crtc->dspaddr_offset;
1974         } else {
1975                 intel_crtc->dspaddr_offset = linear_offset;
1976         }
1977
1978         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1980         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1981         if (INTEL_INFO(dev)->gen >= 4) {
1982                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1983                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1984                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1985                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1986         } else
1987                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1988         POSTING_READ(reg);
1989
1990         return 0;
1991 }
1992
1993 static int ironlake_update_plane(struct drm_crtc *crtc,
1994                                  struct drm_framebuffer *fb, int x, int y)
1995 {
1996         struct drm_device *dev = crtc->dev;
1997         struct drm_i915_private *dev_priv = dev->dev_private;
1998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999         struct intel_framebuffer *intel_fb;
2000         struct drm_i915_gem_object *obj;
2001         int plane = intel_crtc->plane;
2002         unsigned long linear_offset;
2003         u32 dspcntr;
2004         u32 reg;
2005
2006         switch (plane) {
2007         case 0:
2008         case 1:
2009         case 2:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->pixel_format) {
2024         case DRM_FORMAT_C8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case DRM_FORMAT_RGB565:
2028                 dspcntr |= DISPPLANE_BGRX565;
2029                 break;
2030         case DRM_FORMAT_XRGB8888:
2031         case DRM_FORMAT_ARGB8888:
2032                 dspcntr |= DISPPLANE_BGRX888;
2033                 break;
2034         case DRM_FORMAT_XBGR8888:
2035         case DRM_FORMAT_ABGR8888:
2036                 dspcntr |= DISPPLANE_RGBX888;
2037                 break;
2038         case DRM_FORMAT_XRGB2101010:
2039         case DRM_FORMAT_ARGB2101010:
2040                 dspcntr |= DISPPLANE_BGRX101010;
2041                 break;
2042         case DRM_FORMAT_XBGR2101010:
2043         case DRM_FORMAT_ABGR2101010:
2044                 dspcntr |= DISPPLANE_RGBX101010;
2045                 break;
2046         default:
2047                 BUG();
2048         }
2049
2050         if (obj->tiling_mode != I915_TILING_NONE)
2051                 dspcntr |= DISPPLANE_TILED;
2052         else
2053                 dspcntr &= ~DISPPLANE_TILED;
2054
2055         /* must disable */
2056         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058         I915_WRITE(reg, dspcntr);
2059
2060         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2061         intel_crtc->dspaddr_offset =
2062                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063                                                fb->bits_per_pixel / 8,
2064                                                fb->pitches[0]);
2065         linear_offset -= intel_crtc->dspaddr_offset;
2066
2067         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2069         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2070         I915_MODIFY_DISPBASE(DSPSURF(plane),
2071                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2072         if (IS_HASWELL(dev)) {
2073                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2074         } else {
2075                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2076                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2077         }
2078         POSTING_READ(reg);
2079
2080         return 0;
2081 }
2082
2083 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2084 static int
2085 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2086                            int x, int y, enum mode_set_atomic state)
2087 {
2088         struct drm_device *dev = crtc->dev;
2089         struct drm_i915_private *dev_priv = dev->dev_private;
2090
2091         if (dev_priv->display.disable_fbc)
2092                 dev_priv->display.disable_fbc(dev);
2093         intel_increase_pllclock(crtc);
2094
2095         return dev_priv->display.update_plane(crtc, fb, x, y);
2096 }
2097
2098 void intel_display_handle_reset(struct drm_device *dev)
2099 {
2100         struct drm_i915_private *dev_priv = dev->dev_private;
2101         struct drm_crtc *crtc;
2102
2103         /*
2104          * Flips in the rings have been nuked by the reset,
2105          * so complete all pending flips so that user space
2106          * will get its events and not get stuck.
2107          *
2108          * Also update the base address of all primary
2109          * planes to the the last fb to make sure we're
2110          * showing the correct fb after a reset.
2111          *
2112          * Need to make two loops over the crtcs so that we
2113          * don't try to grab a crtc mutex before the
2114          * pending_flip_queue really got woken up.
2115          */
2116
2117         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2118                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119                 enum plane plane = intel_crtc->plane;
2120
2121                 intel_prepare_page_flip(dev, plane);
2122                 intel_finish_page_flip_plane(dev, plane);
2123         }
2124
2125         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2126                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127
2128                 mutex_lock(&crtc->mutex);
2129                 if (intel_crtc->active)
2130                         dev_priv->display.update_plane(crtc, crtc->fb,
2131                                                        crtc->x, crtc->y);
2132                 mutex_unlock(&crtc->mutex);
2133         }
2134 }
2135
2136 static int
2137 intel_finish_fb(struct drm_framebuffer *old_fb)
2138 {
2139         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2140         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141         bool was_interruptible = dev_priv->mm.interruptible;
2142         int ret;
2143
2144         /* Big Hammer, we also need to ensure that any pending
2145          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146          * current scanout is retired before unpinning the old
2147          * framebuffer.
2148          *
2149          * This should only fail upon a hung GPU, in which case we
2150          * can safely continue.
2151          */
2152         dev_priv->mm.interruptible = false;
2153         ret = i915_gem_object_finish_gpu(obj);
2154         dev_priv->mm.interruptible = was_interruptible;
2155
2156         return ret;
2157 }
2158
2159 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2160 {
2161         struct drm_device *dev = crtc->dev;
2162         struct drm_i915_master_private *master_priv;
2163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164
2165         if (!dev->primary->master)
2166                 return;
2167
2168         master_priv = dev->primary->master->driver_priv;
2169         if (!master_priv->sarea_priv)
2170                 return;
2171
2172         switch (intel_crtc->pipe) {
2173         case 0:
2174                 master_priv->sarea_priv->pipeA_x = x;
2175                 master_priv->sarea_priv->pipeA_y = y;
2176                 break;
2177         case 1:
2178                 master_priv->sarea_priv->pipeB_x = x;
2179                 master_priv->sarea_priv->pipeB_y = y;
2180                 break;
2181         default:
2182                 break;
2183         }
2184 }
2185
2186 static int
2187 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2188                     struct drm_framebuffer *fb)
2189 {
2190         struct drm_device *dev = crtc->dev;
2191         struct drm_i915_private *dev_priv = dev->dev_private;
2192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2193         struct drm_framebuffer *old_fb;
2194         int ret;
2195
2196         /* no fb bound */
2197         if (!fb) {
2198                 DRM_ERROR("No FB bound\n");
2199                 return 0;
2200         }
2201
2202         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2203                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204                           plane_name(intel_crtc->plane),
2205                           INTEL_INFO(dev)->num_pipes);
2206                 return -EINVAL;
2207         }
2208
2209         mutex_lock(&dev->struct_mutex);
2210         ret = intel_pin_and_fence_fb_obj(dev,
2211                                          to_intel_framebuffer(fb)->obj,
2212                                          NULL);
2213         if (ret != 0) {
2214                 mutex_unlock(&dev->struct_mutex);
2215                 DRM_ERROR("pin & fence failed\n");
2216                 return ret;
2217         }
2218
2219         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2220         if (ret) {
2221                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2222                 mutex_unlock(&dev->struct_mutex);
2223                 DRM_ERROR("failed to update base address\n");
2224                 return ret;
2225         }
2226
2227         old_fb = crtc->fb;
2228         crtc->fb = fb;
2229         crtc->x = x;
2230         crtc->y = y;
2231
2232         if (old_fb) {
2233                 if (intel_crtc->active && old_fb != fb)
2234                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2235                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2236         }
2237
2238         intel_update_fbc(dev);
2239         mutex_unlock(&dev->struct_mutex);
2240
2241         intel_crtc_update_sarea_pos(crtc, x, y);
2242
2243         return 0;
2244 }
2245
2246 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2247 {
2248         struct drm_device *dev = crtc->dev;
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251         int pipe = intel_crtc->pipe;
2252         u32 reg, temp;
2253
2254         /* enable normal train */
2255         reg = FDI_TX_CTL(pipe);
2256         temp = I915_READ(reg);
2257         if (IS_IVYBRIDGE(dev)) {
2258                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2259                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2260         } else {
2261                 temp &= ~FDI_LINK_TRAIN_NONE;
2262                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2263         }
2264         I915_WRITE(reg, temp);
2265
2266         reg = FDI_RX_CTL(pipe);
2267         temp = I915_READ(reg);
2268         if (HAS_PCH_CPT(dev)) {
2269                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2270                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2271         } else {
2272                 temp &= ~FDI_LINK_TRAIN_NONE;
2273                 temp |= FDI_LINK_TRAIN_NONE;
2274         }
2275         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276
2277         /* wait one idle pattern time */
2278         POSTING_READ(reg);
2279         udelay(1000);
2280
2281         /* IVB wants error correction enabled */
2282         if (IS_IVYBRIDGE(dev))
2283                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2284                            FDI_FE_ERRC_ENABLE);
2285 }
2286
2287 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2288 {
2289         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2290 }
2291
2292 static void ivb_modeset_global_resources(struct drm_device *dev)
2293 {
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         struct intel_crtc *pipe_B_crtc =
2296                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2297         struct intel_crtc *pipe_C_crtc =
2298                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2299         uint32_t temp;
2300
2301         /*
2302          * When everything is off disable fdi C so that we could enable fdi B
2303          * with all lanes. Note that we don't care about enabled pipes without
2304          * an enabled pch encoder.
2305          */
2306         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2307             !pipe_has_enabled_pch(pipe_C_crtc)) {
2308                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2309                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2310
2311                 temp = I915_READ(SOUTH_CHICKEN1);
2312                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2313                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314                 I915_WRITE(SOUTH_CHICKEN1, temp);
2315         }
2316 }
2317
2318 /* The FDI link training functions for ILK/Ibexpeak. */
2319 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320 {
2321         struct drm_device *dev = crtc->dev;
2322         struct drm_i915_private *dev_priv = dev->dev_private;
2323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324         int pipe = intel_crtc->pipe;
2325         int plane = intel_crtc->plane;
2326         u32 reg, temp, tries;
2327
2328         /* FDI needs bits from pipe & plane first */
2329         assert_pipe_enabled(dev_priv, pipe);
2330         assert_plane_enabled(dev_priv, plane);
2331
2332         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333            for train result */
2334         reg = FDI_RX_IMR(pipe);
2335         temp = I915_READ(reg);
2336         temp &= ~FDI_RX_SYMBOL_LOCK;
2337         temp &= ~FDI_RX_BIT_LOCK;
2338         I915_WRITE(reg, temp);
2339         I915_READ(reg);
2340         udelay(150);
2341
2342         /* enable CPU FDI TX and PCH FDI RX */
2343         reg = FDI_TX_CTL(pipe);
2344         temp = I915_READ(reg);
2345         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2346         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2347         temp &= ~FDI_LINK_TRAIN_NONE;
2348         temp |= FDI_LINK_TRAIN_PATTERN_1;
2349         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         temp &= ~FDI_LINK_TRAIN_NONE;
2354         temp |= FDI_LINK_TRAIN_PATTERN_1;
2355         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2356
2357         POSTING_READ(reg);
2358         udelay(150);
2359
2360         /* Ironlake workaround, enable clock pointer after FDI enable*/
2361         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363                    FDI_RX_PHASE_SYNC_POINTER_EN);
2364
2365         reg = FDI_RX_IIR(pipe);
2366         for (tries = 0; tries < 5; tries++) {
2367                 temp = I915_READ(reg);
2368                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2369
2370                 if ((temp & FDI_RX_BIT_LOCK)) {
2371                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2372                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2373                         break;
2374                 }
2375         }
2376         if (tries == 5)
2377                 DRM_ERROR("FDI train 1 fail!\n");
2378
2379         /* Train 2 */
2380         reg = FDI_TX_CTL(pipe);
2381         temp = I915_READ(reg);
2382         temp &= ~FDI_LINK_TRAIN_NONE;
2383         temp |= FDI_LINK_TRAIN_PATTERN_2;
2384         I915_WRITE(reg, temp);
2385
2386         reg = FDI_RX_CTL(pipe);
2387         temp = I915_READ(reg);
2388         temp &= ~FDI_LINK_TRAIN_NONE;
2389         temp |= FDI_LINK_TRAIN_PATTERN_2;
2390         I915_WRITE(reg, temp);
2391
2392         POSTING_READ(reg);
2393         udelay(150);
2394
2395         reg = FDI_RX_IIR(pipe);
2396         for (tries = 0; tries < 5; tries++) {
2397                 temp = I915_READ(reg);
2398                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400                 if (temp & FDI_RX_SYMBOL_LOCK) {
2401                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2402                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2403                         break;
2404                 }
2405         }
2406         if (tries == 5)
2407                 DRM_ERROR("FDI train 2 fail!\n");
2408
2409         DRM_DEBUG_KMS("FDI train done\n");
2410
2411 }
2412
2413 static const int snb_b_fdi_train_param[] = {
2414         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2415         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2416         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2417         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2418 };
2419
2420 /* The FDI link training functions for SNB/Cougarpoint. */
2421 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         int pipe = intel_crtc->pipe;
2427         u32 reg, temp, i, retry;
2428
2429         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430            for train result */
2431         reg = FDI_RX_IMR(pipe);
2432         temp = I915_READ(reg);
2433         temp &= ~FDI_RX_SYMBOL_LOCK;
2434         temp &= ~FDI_RX_BIT_LOCK;
2435         I915_WRITE(reg, temp);
2436
2437         POSTING_READ(reg);
2438         udelay(150);
2439
2440         /* enable CPU FDI TX and PCH FDI RX */
2441         reg = FDI_TX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2444         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2445         temp &= ~FDI_LINK_TRAIN_NONE;
2446         temp |= FDI_LINK_TRAIN_PATTERN_1;
2447         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448         /* SNB-B */
2449         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2450         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2451
2452         I915_WRITE(FDI_RX_MISC(pipe),
2453                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2454
2455         reg = FDI_RX_CTL(pipe);
2456         temp = I915_READ(reg);
2457         if (HAS_PCH_CPT(dev)) {
2458                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2459                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2460         } else {
2461                 temp &= ~FDI_LINK_TRAIN_NONE;
2462                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463         }
2464         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2465
2466         POSTING_READ(reg);
2467         udelay(150);
2468
2469         for (i = 0; i < 4; i++) {
2470                 reg = FDI_TX_CTL(pipe);
2471                 temp = I915_READ(reg);
2472                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473                 temp |= snb_b_fdi_train_param[i];
2474                 I915_WRITE(reg, temp);
2475
2476                 POSTING_READ(reg);
2477                 udelay(500);
2478
2479                 for (retry = 0; retry < 5; retry++) {
2480                         reg = FDI_RX_IIR(pipe);
2481                         temp = I915_READ(reg);
2482                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483                         if (temp & FDI_RX_BIT_LOCK) {
2484                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486                                 break;
2487                         }
2488                         udelay(50);
2489                 }
2490                 if (retry < 5)
2491                         break;
2492         }
2493         if (i == 4)
2494                 DRM_ERROR("FDI train 1 fail!\n");
2495
2496         /* Train 2 */
2497         reg = FDI_TX_CTL(pipe);
2498         temp = I915_READ(reg);
2499         temp &= ~FDI_LINK_TRAIN_NONE;
2500         temp |= FDI_LINK_TRAIN_PATTERN_2;
2501         if (IS_GEN6(dev)) {
2502                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503                 /* SNB-B */
2504                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505         }
2506         I915_WRITE(reg, temp);
2507
2508         reg = FDI_RX_CTL(pipe);
2509         temp = I915_READ(reg);
2510         if (HAS_PCH_CPT(dev)) {
2511                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2513         } else {
2514                 temp &= ~FDI_LINK_TRAIN_NONE;
2515                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2516         }
2517         I915_WRITE(reg, temp);
2518
2519         POSTING_READ(reg);
2520         udelay(150);
2521
2522         for (i = 0; i < 4; i++) {
2523                 reg = FDI_TX_CTL(pipe);
2524                 temp = I915_READ(reg);
2525                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526                 temp |= snb_b_fdi_train_param[i];
2527                 I915_WRITE(reg, temp);
2528
2529                 POSTING_READ(reg);
2530                 udelay(500);
2531
2532                 for (retry = 0; retry < 5; retry++) {
2533                         reg = FDI_RX_IIR(pipe);
2534                         temp = I915_READ(reg);
2535                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536                         if (temp & FDI_RX_SYMBOL_LOCK) {
2537                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539                                 break;
2540                         }
2541                         udelay(50);
2542                 }
2543                 if (retry < 5)
2544                         break;
2545         }
2546         if (i == 4)
2547                 DRM_ERROR("FDI train 2 fail!\n");
2548
2549         DRM_DEBUG_KMS("FDI train done.\n");
2550 }
2551
2552 /* Manual link training for Ivy Bridge A0 parts */
2553 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2554 {
2555         struct drm_device *dev = crtc->dev;
2556         struct drm_i915_private *dev_priv = dev->dev_private;
2557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558         int pipe = intel_crtc->pipe;
2559         u32 reg, temp, i;
2560
2561         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562            for train result */
2563         reg = FDI_RX_IMR(pipe);
2564         temp = I915_READ(reg);
2565         temp &= ~FDI_RX_SYMBOL_LOCK;
2566         temp &= ~FDI_RX_BIT_LOCK;
2567         I915_WRITE(reg, temp);
2568
2569         POSTING_READ(reg);
2570         udelay(150);
2571
2572         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573                       I915_READ(FDI_RX_IIR(pipe)));
2574
2575         /* enable CPU FDI TX and PCH FDI RX */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2580         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2581         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2582         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584         temp |= FDI_COMPOSITE_SYNC;
2585         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
2587         I915_WRITE(FDI_RX_MISC(pipe),
2588                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
2590         reg = FDI_RX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         temp &= ~FDI_LINK_TRAIN_AUTO;
2593         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2595         temp |= FDI_COMPOSITE_SYNC;
2596         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         for (i = 0; i < 4; i++) {
2602                 reg = FDI_TX_CTL(pipe);
2603                 temp = I915_READ(reg);
2604                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605                 temp |= snb_b_fdi_train_param[i];
2606                 I915_WRITE(reg, temp);
2607
2608                 POSTING_READ(reg);
2609                 udelay(500);
2610
2611                 reg = FDI_RX_IIR(pipe);
2612                 temp = I915_READ(reg);
2613                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614
2615                 if (temp & FDI_RX_BIT_LOCK ||
2616                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2617                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2618                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2619                         break;
2620                 }
2621         }
2622         if (i == 4)
2623                 DRM_ERROR("FDI train 1 fail!\n");
2624
2625         /* Train 2 */
2626         reg = FDI_TX_CTL(pipe);
2627         temp = I915_READ(reg);
2628         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2629         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2630         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632         I915_WRITE(reg, temp);
2633
2634         reg = FDI_RX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638         I915_WRITE(reg, temp);
2639
2640         POSTING_READ(reg);
2641         udelay(150);
2642
2643         for (i = 0; i < 4; i++) {
2644                 reg = FDI_TX_CTL(pipe);
2645                 temp = I915_READ(reg);
2646                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647                 temp |= snb_b_fdi_train_param[i];
2648                 I915_WRITE(reg, temp);
2649
2650                 POSTING_READ(reg);
2651                 udelay(500);
2652
2653                 reg = FDI_RX_IIR(pipe);
2654                 temp = I915_READ(reg);
2655                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657                 if (temp & FDI_RX_SYMBOL_LOCK) {
2658                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2659                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2660                         break;
2661                 }
2662         }
2663         if (i == 4)
2664                 DRM_ERROR("FDI train 2 fail!\n");
2665
2666         DRM_DEBUG_KMS("FDI train done.\n");
2667 }
2668
2669 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2670 {
2671         struct drm_device *dev = intel_crtc->base.dev;
2672         struct drm_i915_private *dev_priv = dev->dev_private;
2673         int pipe = intel_crtc->pipe;
2674         u32 reg, temp;
2675
2676
2677         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2678         reg = FDI_RX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2681         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2682         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2683         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2684
2685         POSTING_READ(reg);
2686         udelay(200);
2687
2688         /* Switch from Rawclk to PCDclk */
2689         temp = I915_READ(reg);
2690         I915_WRITE(reg, temp | FDI_PCDCLK);
2691
2692         POSTING_READ(reg);
2693         udelay(200);
2694
2695         /* Enable CPU FDI TX PLL, always on for Ironlake */
2696         reg = FDI_TX_CTL(pipe);
2697         temp = I915_READ(reg);
2698         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2699                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2700
2701                 POSTING_READ(reg);
2702                 udelay(100);
2703         }
2704 }
2705
2706 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2707 {
2708         struct drm_device *dev = intel_crtc->base.dev;
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710         int pipe = intel_crtc->pipe;
2711         u32 reg, temp;
2712
2713         /* Switch from PCDclk to Rawclk */
2714         reg = FDI_RX_CTL(pipe);
2715         temp = I915_READ(reg);
2716         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2717
2718         /* Disable CPU FDI TX PLL */
2719         reg = FDI_TX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2722
2723         POSTING_READ(reg);
2724         udelay(100);
2725
2726         reg = FDI_RX_CTL(pipe);
2727         temp = I915_READ(reg);
2728         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2729
2730         /* Wait for the clocks to turn off. */
2731         POSTING_READ(reg);
2732         udelay(100);
2733 }
2734
2735 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int pipe = intel_crtc->pipe;
2741         u32 reg, temp;
2742
2743         /* disable CPU FDI tx and PCH FDI rx */
2744         reg = FDI_TX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747         POSTING_READ(reg);
2748
2749         reg = FDI_RX_CTL(pipe);
2750         temp = I915_READ(reg);
2751         temp &= ~(0x7 << 16);
2752         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2753         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755         POSTING_READ(reg);
2756         udelay(100);
2757
2758         /* Ironlake workaround, disable clock pointer after downing FDI */
2759         if (HAS_PCH_IBX(dev)) {
2760                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2761         }
2762
2763         /* still set train pattern 1 */
2764         reg = FDI_TX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         temp &= ~FDI_LINK_TRAIN_NONE;
2767         temp |= FDI_LINK_TRAIN_PATTERN_1;
2768         I915_WRITE(reg, temp);
2769
2770         reg = FDI_RX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         if (HAS_PCH_CPT(dev)) {
2773                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775         } else {
2776                 temp &= ~FDI_LINK_TRAIN_NONE;
2777                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778         }
2779         /* BPC in FDI rx is consistent with that in PIPECONF */
2780         temp &= ~(0x07 << 16);
2781         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2782         I915_WRITE(reg, temp);
2783
2784         POSTING_READ(reg);
2785         udelay(100);
2786 }
2787
2788 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2789 {
2790         struct drm_device *dev = crtc->dev;
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2793         unsigned long flags;
2794         bool pending;
2795
2796         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2797             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2798                 return false;
2799
2800         spin_lock_irqsave(&dev->event_lock, flags);
2801         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2802         spin_unlock_irqrestore(&dev->event_lock, flags);
2803
2804         return pending;
2805 }
2806
2807 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808 {
2809         struct drm_device *dev = crtc->dev;
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811
2812         if (crtc->fb == NULL)
2813                 return;
2814
2815         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2816
2817         wait_event(dev_priv->pending_flip_queue,
2818                    !intel_crtc_has_pending_flip(crtc));
2819
2820         mutex_lock(&dev->struct_mutex);
2821         intel_finish_fb(crtc->fb);
2822         mutex_unlock(&dev->struct_mutex);
2823 }
2824
2825 /* Program iCLKIP clock to the desired frequency */
2826 static void lpt_program_iclkip(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2831         u32 temp;
2832
2833         mutex_lock(&dev_priv->dpio_lock);
2834
2835         /* It is necessary to ungate the pixclk gate prior to programming
2836          * the divisors, and gate it back when it is done.
2837          */
2838         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2839
2840         /* Disable SSCCTL */
2841         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2842                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2843                                 SBI_SSCCTL_DISABLE,
2844                         SBI_ICLK);
2845
2846         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847         if (crtc->mode.clock == 20000) {
2848                 auxdiv = 1;
2849                 divsel = 0x41;
2850                 phaseinc = 0x20;
2851         } else {
2852                 /* The iCLK virtual clock root frequency is in MHz,
2853                  * but the crtc->mode.clock in in KHz. To get the divisors,
2854                  * it is necessary to divide one by another, so we
2855                  * convert the virtual clock precision to KHz here for higher
2856                  * precision.
2857                  */
2858                 u32 iclk_virtual_root_freq = 172800 * 1000;
2859                 u32 iclk_pi_range = 64;
2860                 u32 desired_divisor, msb_divisor_value, pi_value;
2861
2862                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2863                 msb_divisor_value = desired_divisor / iclk_pi_range;
2864                 pi_value = desired_divisor % iclk_pi_range;
2865
2866                 auxdiv = 0;
2867                 divsel = msb_divisor_value - 2;
2868                 phaseinc = pi_value;
2869         }
2870
2871         /* This should not happen with any sane values */
2872         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2873                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2874         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2875                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2876
2877         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2878                         crtc->mode.clock,
2879                         auxdiv,
2880                         divsel,
2881                         phasedir,
2882                         phaseinc);
2883
2884         /* Program SSCDIVINTPHASE6 */
2885         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2886         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2887         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2888         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2889         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2890         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2891         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2892         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2893
2894         /* Program SSCAUXDIV */
2895         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2896         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2898         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2899
2900         /* Enable modulator and associated divider */
2901         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2902         temp &= ~SBI_SSCCTL_DISABLE;
2903         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2904
2905         /* Wait for initialization time */
2906         udelay(24);
2907
2908         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2909
2910         mutex_unlock(&dev_priv->dpio_lock);
2911 }
2912
2913 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2914                                                 enum pipe pch_transcoder)
2915 {
2916         struct drm_device *dev = crtc->base.dev;
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2919
2920         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2921                    I915_READ(HTOTAL(cpu_transcoder)));
2922         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2923                    I915_READ(HBLANK(cpu_transcoder)));
2924         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2925                    I915_READ(HSYNC(cpu_transcoder)));
2926
2927         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2928                    I915_READ(VTOTAL(cpu_transcoder)));
2929         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2930                    I915_READ(VBLANK(cpu_transcoder)));
2931         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2932                    I915_READ(VSYNC(cpu_transcoder)));
2933         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2934                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2935 }
2936
2937 /*
2938  * Enable PCH resources required for PCH ports:
2939  *   - PCH PLLs
2940  *   - FDI training & RX/TX
2941  *   - update transcoder timings
2942  *   - DP transcoding bits
2943  *   - transcoder
2944  */
2945 static void ironlake_pch_enable(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950         int pipe = intel_crtc->pipe;
2951         u32 reg, temp;
2952
2953         assert_pch_transcoder_disabled(dev_priv, pipe);
2954
2955         /* Write the TU size bits before fdi link training, so that error
2956          * detection works. */
2957         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2958                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2959
2960         /* For PCH output, training FDI link */
2961         dev_priv->display.fdi_link_train(crtc);
2962
2963         /* XXX: pch pll's can be enabled any time before we enable the PCH
2964          * transcoder, and we actually should do this to not upset any PCH
2965          * transcoder that already use the clock when we share it.
2966          *
2967          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2968          * unconditionally resets the pll - we need that to have the right LVDS
2969          * enable sequence. */
2970         ironlake_enable_pch_pll(intel_crtc);
2971
2972         if (HAS_PCH_CPT(dev)) {
2973                 u32 sel;
2974
2975                 temp = I915_READ(PCH_DPLL_SEL);
2976                 switch (pipe) {
2977                 default:
2978                 case 0:
2979                         temp |= TRANSA_DPLL_ENABLE;
2980                         sel = TRANSA_DPLLB_SEL;
2981                         break;
2982                 case 1:
2983                         temp |= TRANSB_DPLL_ENABLE;
2984                         sel = TRANSB_DPLLB_SEL;
2985                         break;
2986                 case 2:
2987                         temp |= TRANSC_DPLL_ENABLE;
2988                         sel = TRANSC_DPLLB_SEL;
2989                         break;
2990                 }
2991                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2992                         temp |= sel;
2993                 else
2994                         temp &= ~sel;
2995                 I915_WRITE(PCH_DPLL_SEL, temp);
2996         }
2997
2998         /* set transcoder timing, panel must allow it */
2999         assert_panel_unlocked(dev_priv, pipe);
3000         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3001
3002         intel_fdi_normal_train(crtc);
3003
3004         /* For PCH DP, enable TRANS_DP_CTL */
3005         if (HAS_PCH_CPT(dev) &&
3006             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3007              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3008                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3009                 reg = TRANS_DP_CTL(pipe);
3010                 temp = I915_READ(reg);
3011                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3012                           TRANS_DP_SYNC_MASK |
3013                           TRANS_DP_BPC_MASK);
3014                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3015                          TRANS_DP_ENH_FRAMING);
3016                 temp |= bpc << 9; /* same format but at 11:9 */
3017
3018                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3019                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3020                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3021                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3022
3023                 switch (intel_trans_dp_port_sel(crtc)) {
3024                 case PCH_DP_B:
3025                         temp |= TRANS_DP_PORT_SEL_B;
3026                         break;
3027                 case PCH_DP_C:
3028                         temp |= TRANS_DP_PORT_SEL_C;
3029                         break;
3030                 case PCH_DP_D:
3031                         temp |= TRANS_DP_PORT_SEL_D;
3032                         break;
3033                 default:
3034                         BUG();
3035                 }
3036
3037                 I915_WRITE(reg, temp);
3038         }
3039
3040         ironlake_enable_pch_transcoder(dev_priv, pipe);
3041 }
3042
3043 static void lpt_pch_enable(struct drm_crtc *crtc)
3044 {
3045         struct drm_device *dev = crtc->dev;
3046         struct drm_i915_private *dev_priv = dev->dev_private;
3047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3048         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3049
3050         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3051
3052         lpt_program_iclkip(crtc);
3053
3054         /* Set transcoder timing. */
3055         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3056
3057         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3058 }
3059
3060 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3061 {
3062         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3063
3064         if (pll == NULL)
3065                 return;
3066
3067         if (pll->refcount == 0) {
3068                 WARN(1, "bad PCH PLL refcount\n");
3069                 return;
3070         }
3071
3072         --pll->refcount;
3073         intel_crtc->pch_pll = NULL;
3074 }
3075
3076 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3077 {
3078         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3079         struct intel_pch_pll *pll;
3080         int i;
3081
3082         pll = intel_crtc->pch_pll;
3083         if (pll) {
3084                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3085                               intel_crtc->base.base.id, pll->pll_reg);
3086                 goto prepare;
3087         }
3088
3089         if (HAS_PCH_IBX(dev_priv->dev)) {
3090                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3091                 i = intel_crtc->pipe;
3092                 pll = &dev_priv->pch_plls[i];
3093
3094                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3095                               intel_crtc->base.base.id, pll->pll_reg);
3096
3097                 goto found;
3098         }
3099
3100         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3101                 pll = &dev_priv->pch_plls[i];
3102
3103                 /* Only want to check enabled timings first */
3104                 if (pll->refcount == 0)
3105                         continue;
3106
3107                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3108                     fp == I915_READ(pll->fp0_reg)) {
3109                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3110                                       intel_crtc->base.base.id,
3111                                       pll->pll_reg, pll->refcount, pll->active);
3112
3113                         goto found;
3114                 }
3115         }
3116
3117         /* Ok no matching timings, maybe there's a free one? */
3118         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119                 pll = &dev_priv->pch_plls[i];
3120                 if (pll->refcount == 0) {
3121                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3122                                       intel_crtc->base.base.id, pll->pll_reg);
3123                         goto found;
3124                 }
3125         }
3126
3127         return NULL;
3128
3129 found:
3130         intel_crtc->pch_pll = pll;
3131         pll->refcount++;
3132         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3133 prepare: /* separate function? */
3134         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3135
3136         /* Wait for the clocks to stabilize before rewriting the regs */
3137         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3138         POSTING_READ(pll->pll_reg);
3139         udelay(150);
3140
3141         I915_WRITE(pll->fp0_reg, fp);
3142         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3143         pll->on = false;
3144         return pll;
3145 }
3146
3147 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3148 {
3149         struct drm_i915_private *dev_priv = dev->dev_private;
3150         int dslreg = PIPEDSL(pipe);
3151         u32 temp;
3152
3153         temp = I915_READ(dslreg);
3154         udelay(500);
3155         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3156                 if (wait_for(I915_READ(dslreg) != temp, 5))
3157                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3158         }
3159 }
3160
3161 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3162 {
3163         struct drm_device *dev = crtc->base.dev;
3164         struct drm_i915_private *dev_priv = dev->dev_private;
3165         int pipe = crtc->pipe;
3166
3167         if (crtc->config.pch_pfit.size) {
3168                 /* Force use of hard-coded filter coefficients
3169                  * as some pre-programmed values are broken,
3170                  * e.g. x201.
3171                  */
3172                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3173                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3174                                                  PF_PIPE_SEL_IVB(pipe));
3175                 else
3176                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3177                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3178                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3179         }
3180 }
3181
3182 static void intel_enable_planes(struct drm_crtc *crtc)
3183 {
3184         struct drm_device *dev = crtc->dev;
3185         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3186         struct intel_plane *intel_plane;
3187
3188         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3189                 if (intel_plane->pipe == pipe)
3190                         intel_plane_restore(&intel_plane->base);
3191 }
3192
3193 static void intel_disable_planes(struct drm_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->dev;
3196         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3197         struct intel_plane *intel_plane;
3198
3199         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3200                 if (intel_plane->pipe == pipe)
3201                         intel_plane_disable(&intel_plane->base);
3202 }
3203
3204 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3205 {
3206         struct drm_device *dev = crtc->dev;
3207         struct drm_i915_private *dev_priv = dev->dev_private;
3208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3209         struct intel_encoder *encoder;
3210         int pipe = intel_crtc->pipe;
3211         int plane = intel_crtc->plane;
3212         u32 temp;
3213
3214         WARN_ON(!crtc->enabled);
3215
3216         if (intel_crtc->active)
3217                 return;
3218
3219         intel_crtc->active = true;
3220
3221         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3222         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3223
3224         intel_update_watermarks(dev);
3225
3226         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3227                 temp = I915_READ(PCH_LVDS);
3228                 if ((temp & LVDS_PORT_EN) == 0)
3229                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3230         }
3231
3232
3233         if (intel_crtc->config.has_pch_encoder) {
3234                 /* Note: FDI PLL enabling _must_ be done before we enable the
3235                  * cpu pipes, hence this is separate from all the other fdi/pch
3236                  * enabling. */
3237                 ironlake_fdi_pll_enable(intel_crtc);
3238         } else {
3239                 assert_fdi_tx_disabled(dev_priv, pipe);
3240                 assert_fdi_rx_disabled(dev_priv, pipe);
3241         }
3242
3243         for_each_encoder_on_crtc(dev, crtc, encoder)
3244                 if (encoder->pre_enable)
3245                         encoder->pre_enable(encoder);
3246
3247         /* Enable panel fitting for LVDS */
3248         ironlake_pfit_enable(intel_crtc);
3249
3250         /*
3251          * On ILK+ LUT must be loaded before the pipe is running but with
3252          * clocks enabled
3253          */
3254         intel_crtc_load_lut(crtc);
3255
3256         intel_enable_pipe(dev_priv, pipe,
3257                           intel_crtc->config.has_pch_encoder);
3258         intel_enable_plane(dev_priv, plane, pipe);
3259         intel_enable_planes(crtc);
3260         intel_crtc_update_cursor(crtc, true);
3261
3262         if (intel_crtc->config.has_pch_encoder)
3263                 ironlake_pch_enable(crtc);
3264
3265         mutex_lock(&dev->struct_mutex);
3266         intel_update_fbc(dev);
3267         mutex_unlock(&dev->struct_mutex);
3268
3269         for_each_encoder_on_crtc(dev, crtc, encoder)
3270                 encoder->enable(encoder);
3271
3272         if (HAS_PCH_CPT(dev))
3273                 cpt_verify_modeset(dev, intel_crtc->pipe);
3274
3275         /*
3276          * There seems to be a race in PCH platform hw (at least on some
3277          * outputs) where an enabled pipe still completes any pageflip right
3278          * away (as if the pipe is off) instead of waiting for vblank. As soon
3279          * as the first vblank happend, everything works as expected. Hence just
3280          * wait for one vblank before returning to avoid strange things
3281          * happening.
3282          */
3283         intel_wait_for_vblank(dev, intel_crtc->pipe);
3284 }
3285
3286 /* IPS only exists on ULT machines and is tied to pipe A. */
3287 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3288 {
3289         return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3290 }
3291
3292 static void hsw_enable_ips(struct intel_crtc *crtc)
3293 {
3294         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3295
3296         if (!crtc->config.ips_enabled)
3297                 return;
3298
3299         /* We can only enable IPS after we enable a plane and wait for a vblank.
3300          * We guarantee that the plane is enabled by calling intel_enable_ips
3301          * only after intel_enable_plane. And intel_enable_plane already waits
3302          * for a vblank, so all we need to do here is to enable the IPS bit. */
3303         assert_plane_enabled(dev_priv, crtc->plane);
3304         I915_WRITE(IPS_CTL, IPS_ENABLE);
3305 }
3306
3307 static void hsw_disable_ips(struct intel_crtc *crtc)
3308 {
3309         struct drm_device *dev = crtc->base.dev;
3310         struct drm_i915_private *dev_priv = dev->dev_private;
3311
3312         if (!crtc->config.ips_enabled)
3313                 return;
3314
3315         assert_plane_enabled(dev_priv, crtc->plane);
3316         I915_WRITE(IPS_CTL, 0);
3317
3318         /* We need to wait for a vblank before we can disable the plane. */
3319         intel_wait_for_vblank(dev, crtc->pipe);
3320 }
3321
3322 static void haswell_crtc_enable(struct drm_crtc *crtc)
3323 {
3324         struct drm_device *dev = crtc->dev;
3325         struct drm_i915_private *dev_priv = dev->dev_private;
3326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3327         struct intel_encoder *encoder;
3328         int pipe = intel_crtc->pipe;
3329         int plane = intel_crtc->plane;
3330
3331         WARN_ON(!crtc->enabled);
3332
3333         if (intel_crtc->active)
3334                 return;
3335
3336         intel_crtc->active = true;
3337
3338         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3339         if (intel_crtc->config.has_pch_encoder)
3340                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3341
3342         intel_update_watermarks(dev);
3343
3344         if (intel_crtc->config.has_pch_encoder)
3345                 dev_priv->display.fdi_link_train(crtc);
3346
3347         for_each_encoder_on_crtc(dev, crtc, encoder)
3348                 if (encoder->pre_enable)
3349                         encoder->pre_enable(encoder);
3350
3351         intel_ddi_enable_pipe_clock(intel_crtc);
3352
3353         /* Enable panel fitting for eDP */
3354         ironlake_pfit_enable(intel_crtc);
3355
3356         /*
3357          * On ILK+ LUT must be loaded before the pipe is running but with
3358          * clocks enabled
3359          */
3360         intel_crtc_load_lut(crtc);
3361
3362         intel_ddi_set_pipe_settings(crtc);
3363         intel_ddi_enable_transcoder_func(crtc);
3364
3365         intel_enable_pipe(dev_priv, pipe,
3366                           intel_crtc->config.has_pch_encoder);
3367         intel_enable_plane(dev_priv, plane, pipe);
3368         intel_enable_planes(crtc);
3369         intel_crtc_update_cursor(crtc, true);
3370
3371         hsw_enable_ips(intel_crtc);
3372
3373         if (intel_crtc->config.has_pch_encoder)
3374                 lpt_pch_enable(crtc);
3375
3376         mutex_lock(&dev->struct_mutex);
3377         intel_update_fbc(dev);
3378         mutex_unlock(&dev->struct_mutex);
3379
3380         for_each_encoder_on_crtc(dev, crtc, encoder)
3381                 encoder->enable(encoder);
3382
3383         /*
3384          * There seems to be a race in PCH platform hw (at least on some
3385          * outputs) where an enabled pipe still completes any pageflip right
3386          * away (as if the pipe is off) instead of waiting for vblank. As soon
3387          * as the first vblank happend, everything works as expected. Hence just
3388          * wait for one vblank before returning to avoid strange things
3389          * happening.
3390          */
3391         intel_wait_for_vblank(dev, intel_crtc->pipe);
3392 }
3393
3394 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->base.dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         int pipe = crtc->pipe;
3399
3400         /* To avoid upsetting the power well on haswell only disable the pfit if
3401          * it's in use. The hw state code will make sure we get this right. */
3402         if (crtc->config.pch_pfit.size) {
3403                 I915_WRITE(PF_CTL(pipe), 0);
3404                 I915_WRITE(PF_WIN_POS(pipe), 0);
3405                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3406         }
3407 }
3408
3409 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3410 {
3411         struct drm_device *dev = crtc->dev;
3412         struct drm_i915_private *dev_priv = dev->dev_private;
3413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3414         struct intel_encoder *encoder;
3415         int pipe = intel_crtc->pipe;
3416         int plane = intel_crtc->plane;
3417         u32 reg, temp;
3418
3419
3420         if (!intel_crtc->active)
3421                 return;
3422
3423         for_each_encoder_on_crtc(dev, crtc, encoder)
3424                 encoder->disable(encoder);
3425
3426         intel_crtc_wait_for_pending_flips(crtc);
3427         drm_vblank_off(dev, pipe);
3428
3429         if (dev_priv->cfb_plane == plane)
3430                 intel_disable_fbc(dev);
3431
3432         intel_crtc_update_cursor(crtc, false);
3433         intel_disable_planes(crtc);
3434         intel_disable_plane(dev_priv, plane, pipe);
3435
3436         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3437         intel_disable_pipe(dev_priv, pipe);
3438
3439         ironlake_pfit_disable(intel_crtc);
3440
3441         for_each_encoder_on_crtc(dev, crtc, encoder)
3442                 if (encoder->post_disable)
3443                         encoder->post_disable(encoder);
3444
3445         ironlake_fdi_disable(crtc);
3446
3447         ironlake_disable_pch_transcoder(dev_priv, pipe);
3448         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3449
3450         if (HAS_PCH_CPT(dev)) {
3451                 /* disable TRANS_DP_CTL */
3452                 reg = TRANS_DP_CTL(pipe);
3453                 temp = I915_READ(reg);
3454                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3455                 temp |= TRANS_DP_PORT_SEL_NONE;
3456                 I915_WRITE(reg, temp);
3457
3458                 /* disable DPLL_SEL */
3459                 temp = I915_READ(PCH_DPLL_SEL);
3460                 switch (pipe) {
3461                 case 0:
3462                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3463                         break;
3464                 case 1:
3465                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3466                         break;
3467                 case 2:
3468                         /* C shares PLL A or B */
3469                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3470                         break;
3471                 default:
3472                         BUG(); /* wtf */
3473                 }
3474                 I915_WRITE(PCH_DPLL_SEL, temp);
3475         }
3476
3477         /* disable PCH DPLL */
3478         intel_disable_pch_pll(intel_crtc);
3479
3480         ironlake_fdi_pll_disable(intel_crtc);
3481
3482         intel_crtc->active = false;
3483         intel_update_watermarks(dev);
3484
3485         mutex_lock(&dev->struct_mutex);
3486         intel_update_fbc(dev);
3487         mutex_unlock(&dev->struct_mutex);
3488 }
3489
3490 static void haswell_crtc_disable(struct drm_crtc *crtc)
3491 {
3492         struct drm_device *dev = crtc->dev;
3493         struct drm_i915_private *dev_priv = dev->dev_private;
3494         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3495         struct intel_encoder *encoder;
3496         int pipe = intel_crtc->pipe;
3497         int plane = intel_crtc->plane;
3498         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3499
3500         if (!intel_crtc->active)
3501                 return;
3502
3503         for_each_encoder_on_crtc(dev, crtc, encoder)
3504                 encoder->disable(encoder);
3505
3506         intel_crtc_wait_for_pending_flips(crtc);
3507         drm_vblank_off(dev, pipe);
3508
3509         /* FBC must be disabled before disabling the plane on HSW. */
3510         if (dev_priv->cfb_plane == plane)
3511                 intel_disable_fbc(dev);
3512
3513         hsw_disable_ips(intel_crtc);
3514
3515         intel_crtc_update_cursor(crtc, false);
3516         intel_disable_planes(crtc);
3517         intel_disable_plane(dev_priv, plane, pipe);
3518
3519         if (intel_crtc->config.has_pch_encoder)
3520                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3521         intel_disable_pipe(dev_priv, pipe);
3522
3523         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3524
3525         ironlake_pfit_disable(intel_crtc);
3526
3527         intel_ddi_disable_pipe_clock(intel_crtc);
3528
3529         for_each_encoder_on_crtc(dev, crtc, encoder)
3530                 if (encoder->post_disable)
3531                         encoder->post_disable(encoder);
3532
3533         if (intel_crtc->config.has_pch_encoder) {
3534                 lpt_disable_pch_transcoder(dev_priv);
3535                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3536                 intel_ddi_fdi_disable(crtc);
3537         }
3538
3539         intel_crtc->active = false;
3540         intel_update_watermarks(dev);
3541
3542         mutex_lock(&dev->struct_mutex);
3543         intel_update_fbc(dev);
3544         mutex_unlock(&dev->struct_mutex);
3545 }
3546
3547 static void ironlake_crtc_off(struct drm_crtc *crtc)
3548 {
3549         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3550         intel_put_pch_pll(intel_crtc);
3551 }
3552
3553 static void haswell_crtc_off(struct drm_crtc *crtc)
3554 {
3555         intel_ddi_put_crtc_pll(crtc);
3556 }
3557
3558 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3559 {
3560         if (!enable && intel_crtc->overlay) {
3561                 struct drm_device *dev = intel_crtc->base.dev;
3562                 struct drm_i915_private *dev_priv = dev->dev_private;
3563
3564                 mutex_lock(&dev->struct_mutex);
3565                 dev_priv->mm.interruptible = false;
3566                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3567                 dev_priv->mm.interruptible = true;
3568                 mutex_unlock(&dev->struct_mutex);
3569         }
3570
3571         /* Let userspace switch the overlay on again. In most cases userspace
3572          * has to recompute where to put it anyway.
3573          */
3574 }
3575
3576 /**
3577  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3578  * cursor plane briefly if not already running after enabling the display
3579  * plane.
3580  * This workaround avoids occasional blank screens when self refresh is
3581  * enabled.
3582  */
3583 static void
3584 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3585 {
3586         u32 cntl = I915_READ(CURCNTR(pipe));
3587
3588         if ((cntl & CURSOR_MODE) == 0) {
3589                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3590
3591                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3592                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3593                 intel_wait_for_vblank(dev_priv->dev, pipe);
3594                 I915_WRITE(CURCNTR(pipe), cntl);
3595                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3596                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3597         }
3598 }
3599
3600 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3601 {
3602         struct drm_device *dev = crtc->base.dev;
3603         struct drm_i915_private *dev_priv = dev->dev_private;
3604         struct intel_crtc_config *pipe_config = &crtc->config;
3605
3606         if (!crtc->config.gmch_pfit.control)
3607                 return;
3608
3609         /*
3610          * The panel fitter should only be adjusted whilst the pipe is disabled,
3611          * according to register description and PRM.
3612          */
3613         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3614         assert_pipe_disabled(dev_priv, crtc->pipe);
3615
3616         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3617         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3618
3619         /* Border color in case we don't scale up to the full screen. Black by
3620          * default, change to something else for debugging. */
3621         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3622 }
3623
3624 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629         struct intel_encoder *encoder;
3630         int pipe = intel_crtc->pipe;
3631         int plane = intel_crtc->plane;
3632
3633         WARN_ON(!crtc->enabled);
3634
3635         if (intel_crtc->active)
3636                 return;
3637
3638         intel_crtc->active = true;
3639         intel_update_watermarks(dev);
3640
3641         mutex_lock(&dev_priv->dpio_lock);
3642
3643         for_each_encoder_on_crtc(dev, crtc, encoder)
3644                 if (encoder->pre_pll_enable)
3645                         encoder->pre_pll_enable(encoder);
3646
3647         intel_enable_pll(dev_priv, pipe);
3648
3649         for_each_encoder_on_crtc(dev, crtc, encoder)
3650                 if (encoder->pre_enable)
3651                         encoder->pre_enable(encoder);
3652
3653         /* VLV wants encoder enabling _before_ the pipe is up. */
3654         for_each_encoder_on_crtc(dev, crtc, encoder)
3655                 encoder->enable(encoder);
3656
3657         /* Enable panel fitting for eDP */
3658         i9xx_pfit_enable(intel_crtc);
3659
3660         intel_crtc_load_lut(crtc);
3661
3662         intel_enable_pipe(dev_priv, pipe, false);
3663         intel_enable_plane(dev_priv, plane, pipe);
3664         intel_enable_planes(crtc);
3665         intel_crtc_update_cursor(crtc, true);
3666
3667         intel_update_fbc(dev);
3668
3669         mutex_unlock(&dev_priv->dpio_lock);
3670 }
3671
3672 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3673 {
3674         struct drm_device *dev = crtc->dev;
3675         struct drm_i915_private *dev_priv = dev->dev_private;
3676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677         struct intel_encoder *encoder;
3678         int pipe = intel_crtc->pipe;
3679         int plane = intel_crtc->plane;
3680
3681         WARN_ON(!crtc->enabled);
3682
3683         if (intel_crtc->active)
3684                 return;
3685
3686         intel_crtc->active = true;
3687         intel_update_watermarks(dev);
3688
3689         intel_enable_pll(dev_priv, pipe);
3690
3691         for_each_encoder_on_crtc(dev, crtc, encoder)
3692                 if (encoder->pre_enable)
3693                         encoder->pre_enable(encoder);
3694
3695         /* Enable panel fitting for LVDS */
3696         i9xx_pfit_enable(intel_crtc);
3697
3698         intel_crtc_load_lut(crtc);
3699
3700         intel_enable_pipe(dev_priv, pipe, false);
3701         intel_enable_plane(dev_priv, plane, pipe);
3702         intel_enable_planes(crtc);
3703         intel_crtc_update_cursor(crtc, true);
3704         if (IS_G4X(dev))
3705                 g4x_fixup_plane(dev_priv, pipe);
3706
3707         /* Give the overlay scaler a chance to enable if it's on this pipe */
3708         intel_crtc_dpms_overlay(intel_crtc, true);
3709
3710         intel_update_fbc(dev);
3711
3712         for_each_encoder_on_crtc(dev, crtc, encoder)
3713                 encoder->enable(encoder);
3714 }
3715
3716 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->base.dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720
3721         if (!crtc->config.gmch_pfit.control)
3722                 return;
3723
3724         assert_pipe_disabled(dev_priv, crtc->pipe);
3725
3726         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3727                          I915_READ(PFIT_CONTROL));
3728         I915_WRITE(PFIT_CONTROL, 0);
3729 }
3730
3731 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3732 {
3733         struct drm_device *dev = crtc->dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3736         struct intel_encoder *encoder;
3737         int pipe = intel_crtc->pipe;
3738         int plane = intel_crtc->plane;
3739
3740         if (!intel_crtc->active)
3741                 return;
3742
3743         for_each_encoder_on_crtc(dev, crtc, encoder)
3744                 encoder->disable(encoder);
3745
3746         /* Give the overlay scaler a chance to disable if it's on this pipe */
3747         intel_crtc_wait_for_pending_flips(crtc);
3748         drm_vblank_off(dev, pipe);
3749
3750         if (dev_priv->cfb_plane == plane)
3751                 intel_disable_fbc(dev);
3752
3753         intel_crtc_dpms_overlay(intel_crtc, false);
3754         intel_crtc_update_cursor(crtc, false);
3755         intel_disable_planes(crtc);
3756         intel_disable_plane(dev_priv, plane, pipe);
3757
3758         intel_disable_pipe(dev_priv, pipe);
3759
3760         i9xx_pfit_disable(intel_crtc);
3761
3762         for_each_encoder_on_crtc(dev, crtc, encoder)
3763                 if (encoder->post_disable)
3764                         encoder->post_disable(encoder);
3765
3766         intel_disable_pll(dev_priv, pipe);
3767
3768         intel_crtc->active = false;
3769         intel_update_fbc(dev);
3770         intel_update_watermarks(dev);
3771 }
3772
3773 static void i9xx_crtc_off(struct drm_crtc *crtc)
3774 {
3775 }
3776
3777 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3778                                     bool enabled)
3779 {
3780         struct drm_device *dev = crtc->dev;
3781         struct drm_i915_master_private *master_priv;
3782         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3783         int pipe = intel_crtc->pipe;
3784
3785         if (!dev->primary->master)
3786                 return;
3787
3788         master_priv = dev->primary->master->driver_priv;
3789         if (!master_priv->sarea_priv)
3790                 return;
3791
3792         switch (pipe) {
3793         case 0:
3794                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3795                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3796                 break;
3797         case 1:
3798                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3799                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3800                 break;
3801         default:
3802                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3803                 break;
3804         }
3805 }
3806
3807 /**
3808  * Sets the power management mode of the pipe and plane.
3809  */
3810 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3811 {
3812         struct drm_device *dev = crtc->dev;
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814         struct intel_encoder *intel_encoder;
3815         bool enable = false;
3816
3817         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3818                 enable |= intel_encoder->connectors_active;
3819
3820         if (enable)
3821                 dev_priv->display.crtc_enable(crtc);
3822         else
3823                 dev_priv->display.crtc_disable(crtc);
3824
3825         intel_crtc_update_sarea(crtc, enable);
3826 }
3827
3828 static void intel_crtc_disable(struct drm_crtc *crtc)
3829 {
3830         struct drm_device *dev = crtc->dev;
3831         struct drm_connector *connector;
3832         struct drm_i915_private *dev_priv = dev->dev_private;
3833         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3834
3835         /* crtc should still be enabled when we disable it. */
3836         WARN_ON(!crtc->enabled);
3837
3838         dev_priv->display.crtc_disable(crtc);
3839         intel_crtc->eld_vld = false;
3840         intel_crtc_update_sarea(crtc, false);
3841         dev_priv->display.off(crtc);
3842
3843         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3844         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3845
3846         if (crtc->fb) {
3847                 mutex_lock(&dev->struct_mutex);
3848                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3849                 mutex_unlock(&dev->struct_mutex);
3850                 crtc->fb = NULL;
3851         }
3852
3853         /* Update computed state. */
3854         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3855                 if (!connector->encoder || !connector->encoder->crtc)
3856                         continue;
3857
3858                 if (connector->encoder->crtc != crtc)
3859                         continue;
3860
3861                 connector->dpms = DRM_MODE_DPMS_OFF;
3862                 to_intel_encoder(connector->encoder)->connectors_active = false;
3863         }
3864 }
3865
3866 void intel_modeset_disable(struct drm_device *dev)
3867 {
3868         struct drm_crtc *crtc;
3869
3870         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3871                 if (crtc->enabled)
3872                         intel_crtc_disable(crtc);
3873         }
3874 }
3875
3876 void intel_encoder_destroy(struct drm_encoder *encoder)
3877 {
3878         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3879
3880         drm_encoder_cleanup(encoder);
3881         kfree(intel_encoder);
3882 }
3883
3884 /* Simple dpms helper for encodres with just one connector, no cloning and only
3885  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3886  * state of the entire output pipe. */
3887 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3888 {
3889         if (mode == DRM_MODE_DPMS_ON) {
3890                 encoder->connectors_active = true;
3891
3892                 intel_crtc_update_dpms(encoder->base.crtc);
3893         } else {
3894                 encoder->connectors_active = false;
3895
3896                 intel_crtc_update_dpms(encoder->base.crtc);
3897         }
3898 }
3899
3900 /* Cross check the actual hw state with our own modeset state tracking (and it's
3901  * internal consistency). */
3902 static void intel_connector_check_state(struct intel_connector *connector)
3903 {
3904         if (connector->get_hw_state(connector)) {
3905                 struct intel_encoder *encoder = connector->encoder;
3906                 struct drm_crtc *crtc;
3907                 bool encoder_enabled;
3908                 enum pipe pipe;
3909
3910                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3911                               connector->base.base.id,
3912                               drm_get_connector_name(&connector->base));
3913
3914                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3915                      "wrong connector dpms state\n");
3916                 WARN(connector->base.encoder != &encoder->base,
3917                      "active connector not linked to encoder\n");
3918                 WARN(!encoder->connectors_active,
3919                      "encoder->connectors_active not set\n");
3920
3921                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3922                 WARN(!encoder_enabled, "encoder not enabled\n");
3923                 if (WARN_ON(!encoder->base.crtc))
3924                         return;
3925
3926                 crtc = encoder->base.crtc;
3927
3928                 WARN(!crtc->enabled, "crtc not enabled\n");
3929                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3930                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3931                      "encoder active on the wrong pipe\n");
3932         }
3933 }
3934
3935 /* Even simpler default implementation, if there's really no special case to
3936  * consider. */
3937 void intel_connector_dpms(struct drm_connector *connector, int mode)
3938 {
3939         struct intel_encoder *encoder = intel_attached_encoder(connector);
3940
3941         /* All the simple cases only support two dpms states. */
3942         if (mode != DRM_MODE_DPMS_ON)
3943                 mode = DRM_MODE_DPMS_OFF;
3944
3945         if (mode == connector->dpms)
3946                 return;
3947
3948         connector->dpms = mode;
3949
3950         /* Only need to change hw state when actually enabled */
3951         if (encoder->base.crtc)
3952                 intel_encoder_dpms(encoder, mode);
3953         else
3954                 WARN_ON(encoder->connectors_active != false);
3955
3956         intel_modeset_check_state(connector->dev);
3957 }
3958
3959 /* Simple connector->get_hw_state implementation for encoders that support only
3960  * one connector and no cloning and hence the encoder state determines the state
3961  * of the connector. */
3962 bool intel_connector_get_hw_state(struct intel_connector *connector)
3963 {
3964         enum pipe pipe = 0;
3965         struct intel_encoder *encoder = connector->encoder;
3966
3967         return encoder->get_hw_state(encoder, &pipe);
3968 }
3969
3970 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3971                                      struct intel_crtc_config *pipe_config)
3972 {
3973         struct drm_i915_private *dev_priv = dev->dev_private;
3974         struct intel_crtc *pipe_B_crtc =
3975                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3976
3977         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3978                       pipe_name(pipe), pipe_config->fdi_lanes);
3979         if (pipe_config->fdi_lanes > 4) {
3980                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3981                               pipe_name(pipe), pipe_config->fdi_lanes);
3982                 return false;
3983         }
3984
3985         if (IS_HASWELL(dev)) {
3986                 if (pipe_config->fdi_lanes > 2) {
3987                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3988                                       pipe_config->fdi_lanes);
3989                         return false;
3990                 } else {
3991                         return true;
3992                 }
3993         }
3994
3995         if (INTEL_INFO(dev)->num_pipes == 2)
3996                 return true;
3997
3998         /* Ivybridge 3 pipe is really complicated */
3999         switch (pipe) {
4000         case PIPE_A:
4001                 return true;
4002         case PIPE_B:
4003                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4004                     pipe_config->fdi_lanes > 2) {
4005                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4006                                       pipe_name(pipe), pipe_config->fdi_lanes);
4007                         return false;
4008                 }
4009                 return true;
4010         case PIPE_C:
4011                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4012                     pipe_B_crtc->config.fdi_lanes <= 2) {
4013                         if (pipe_config->fdi_lanes > 2) {
4014                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4015                                               pipe_name(pipe), pipe_config->fdi_lanes);
4016                                 return false;
4017                         }
4018                 } else {
4019                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4020                         return false;
4021                 }
4022                 return true;
4023         default:
4024                 BUG();
4025         }
4026 }
4027
4028 #define RETRY 1
4029 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4030                                        struct intel_crtc_config *pipe_config)
4031 {
4032         struct drm_device *dev = intel_crtc->base.dev;
4033         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4034         int lane, link_bw, fdi_dotclock;
4035         bool setup_ok, needs_recompute = false;
4036
4037 retry:
4038         /* FDI is a binary signal running at ~2.7GHz, encoding
4039          * each output octet as 10 bits. The actual frequency
4040          * is stored as a divider into a 100MHz clock, and the
4041          * mode pixel clock is stored in units of 1KHz.
4042          * Hence the bw of each lane in terms of the mode signal
4043          * is:
4044          */
4045         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4046
4047         fdi_dotclock = adjusted_mode->clock;
4048         fdi_dotclock /= pipe_config->pixel_multiplier;
4049
4050         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4051                                            pipe_config->pipe_bpp);
4052
4053         pipe_config->fdi_lanes = lane;
4054
4055         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4056                                link_bw, &pipe_config->fdi_m_n);
4057
4058         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4059                                             intel_crtc->pipe, pipe_config);
4060         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4061                 pipe_config->pipe_bpp -= 2*3;
4062                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4063                               pipe_config->pipe_bpp);
4064                 needs_recompute = true;
4065                 pipe_config->bw_constrained = true;
4066
4067                 goto retry;
4068         }
4069
4070         if (needs_recompute)
4071                 return RETRY;
4072
4073         return setup_ok ? 0 : -EINVAL;
4074 }
4075
4076 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4077                                    struct intel_crtc_config *pipe_config)
4078 {
4079         pipe_config->ips_enabled = i915_enable_ips &&
4080                                    hsw_crtc_supports_ips(crtc) &&
4081                                    pipe_config->pipe_bpp == 24;
4082 }
4083
4084 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4085                                      struct intel_crtc_config *pipe_config)
4086 {
4087         struct drm_device *dev = crtc->dev;
4088         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4090
4091         if (HAS_PCH_SPLIT(dev)) {
4092                 /* FDI link clock is fixed at 2.7G */
4093                 if (pipe_config->requested_mode.clock * 3
4094                     > IRONLAKE_FDI_FREQ * 4)
4095                         return -EINVAL;
4096         }
4097
4098         /* All interlaced capable intel hw wants timings in frames. Note though
4099          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4100          * timings, so we need to be careful not to clobber these.*/
4101         if (!pipe_config->timings_set)
4102                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4103
4104         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4105          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4106          */
4107         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4108                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4109                 return -EINVAL;
4110
4111         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4112                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4113         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4114                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4115                  * for lvds. */
4116                 pipe_config->pipe_bpp = 8*3;
4117         }
4118
4119         if (IS_HASWELL(dev))
4120                 hsw_compute_ips_config(intel_crtc, pipe_config);
4121
4122         if (pipe_config->has_pch_encoder)
4123                 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
4124
4125         return 0;
4126 }
4127
4128 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4129 {
4130         return 400000; /* FIXME */
4131 }
4132
4133 static int i945_get_display_clock_speed(struct drm_device *dev)
4134 {
4135         return 400000;
4136 }
4137
4138 static int i915_get_display_clock_speed(struct drm_device *dev)
4139 {
4140         return 333000;
4141 }
4142
4143 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4144 {
4145         return 200000;
4146 }
4147
4148 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4149 {
4150         u16 gcfgc = 0;
4151
4152         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4153
4154         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4155                 return 133000;
4156         else {
4157                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4158                 case GC_DISPLAY_CLOCK_333_MHZ:
4159                         return 333000;
4160                 default:
4161                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4162                         return 190000;
4163                 }
4164         }
4165 }
4166
4167 static int i865_get_display_clock_speed(struct drm_device *dev)
4168 {
4169         return 266000;
4170 }
4171
4172 static int i855_get_display_clock_speed(struct drm_device *dev)
4173 {
4174         u16 hpllcc = 0;
4175         /* Assume that the hardware is in the high speed state.  This
4176          * should be the default.
4177          */
4178         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4179         case GC_CLOCK_133_200:
4180         case GC_CLOCK_100_200:
4181                 return 200000;
4182         case GC_CLOCK_166_250:
4183                 return 250000;
4184         case GC_CLOCK_100_133:
4185                 return 133000;
4186         }
4187
4188         /* Shouldn't happen */
4189         return 0;
4190 }
4191
4192 static int i830_get_display_clock_speed(struct drm_device *dev)
4193 {
4194         return 133000;
4195 }
4196
4197 static void
4198 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4199 {
4200         while (*num > DATA_LINK_M_N_MASK ||
4201                *den > DATA_LINK_M_N_MASK) {
4202                 *num >>= 1;
4203                 *den >>= 1;
4204         }
4205 }
4206
4207 static void compute_m_n(unsigned int m, unsigned int n,
4208                         uint32_t *ret_m, uint32_t *ret_n)
4209 {
4210         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4211         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4212         intel_reduce_m_n_ratio(ret_m, ret_n);
4213 }
4214
4215 void
4216 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4217                        int pixel_clock, int link_clock,
4218                        struct intel_link_m_n *m_n)
4219 {
4220         m_n->tu = 64;
4221
4222         compute_m_n(bits_per_pixel * pixel_clock,
4223                     link_clock * nlanes * 8,
4224                     &m_n->gmch_m, &m_n->gmch_n);
4225
4226         compute_m_n(pixel_clock, link_clock,
4227                     &m_n->link_m, &m_n->link_n);
4228 }
4229
4230 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4231 {
4232         if (i915_panel_use_ssc >= 0)
4233                 return i915_panel_use_ssc != 0;
4234         return dev_priv->vbt.lvds_use_ssc
4235                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4236 }
4237
4238 static int vlv_get_refclk(struct drm_crtc *crtc)
4239 {
4240         struct drm_device *dev = crtc->dev;
4241         struct drm_i915_private *dev_priv = dev->dev_private;
4242         int refclk = 27000; /* for DP & HDMI */
4243
4244         return 100000; /* only one validated so far */
4245
4246         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4247                 refclk = 96000;
4248         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4249                 if (intel_panel_use_ssc(dev_priv))
4250                         refclk = 100000;
4251                 else
4252                         refclk = 96000;
4253         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4254                 refclk = 100000;
4255         }
4256
4257         return refclk;
4258 }
4259
4260 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4261 {
4262         struct drm_device *dev = crtc->dev;
4263         struct drm_i915_private *dev_priv = dev->dev_private;
4264         int refclk;
4265
4266         if (IS_VALLEYVIEW(dev)) {
4267                 refclk = vlv_get_refclk(crtc);
4268         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4269             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4270                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4271                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4272                               refclk / 1000);
4273         } else if (!IS_GEN2(dev)) {
4274                 refclk = 96000;
4275         } else {
4276                 refclk = 48000;
4277         }
4278
4279         return refclk;
4280 }
4281
4282 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4283 {
4284         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4285 }
4286
4287 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4288 {
4289         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4290 }
4291
4292 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4293                                      intel_clock_t *reduced_clock)
4294 {
4295         struct drm_device *dev = crtc->base.dev;
4296         struct drm_i915_private *dev_priv = dev->dev_private;
4297         int pipe = crtc->pipe;
4298         u32 fp, fp2 = 0;
4299
4300         if (IS_PINEVIEW(dev)) {
4301                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4302                 if (reduced_clock)
4303                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4304         } else {
4305                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4306                 if (reduced_clock)
4307                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4308         }
4309
4310         I915_WRITE(FP0(pipe), fp);
4311
4312         crtc->lowfreq_avail = false;
4313         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4314             reduced_clock && i915_powersave) {
4315                 I915_WRITE(FP1(pipe), fp2);
4316                 crtc->lowfreq_avail = true;
4317         } else {
4318                 I915_WRITE(FP1(pipe), fp);
4319         }
4320 }
4321
4322 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4323 {
4324         u32 reg_val;
4325
4326         /*
4327          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4328          * and set it to a reasonable value instead.
4329          */
4330         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4331         reg_val &= 0xffffff00;
4332         reg_val |= 0x00000030;
4333         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4334
4335         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4336         reg_val &= 0x8cffffff;
4337         reg_val = 0x8c000000;
4338         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4339
4340         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4341         reg_val &= 0xffffff00;
4342         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4343
4344         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4345         reg_val &= 0x00ffffff;
4346         reg_val |= 0xb0000000;
4347         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4348 }
4349
4350 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4351                                          struct intel_link_m_n *m_n)
4352 {
4353         struct drm_device *dev = crtc->base.dev;
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         int pipe = crtc->pipe;
4356
4357         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4359         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4360         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4361 }
4362
4363 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4364                                          struct intel_link_m_n *m_n)
4365 {
4366         struct drm_device *dev = crtc->base.dev;
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368         int pipe = crtc->pipe;
4369         enum transcoder transcoder = crtc->config.cpu_transcoder;
4370
4371         if (INTEL_INFO(dev)->gen >= 5) {
4372                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4373                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4374                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4375                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4376         } else {
4377                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4378                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4379                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4380                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4381         }
4382 }
4383
4384 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4385 {
4386         if (crtc->config.has_pch_encoder)
4387                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4388         else
4389                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4390 }
4391
4392 static void vlv_update_pll(struct intel_crtc *crtc)
4393 {
4394         struct drm_device *dev = crtc->base.dev;
4395         struct drm_i915_private *dev_priv = dev->dev_private;
4396         struct intel_encoder *encoder;
4397         int pipe = crtc->pipe;
4398         u32 dpll, mdiv;
4399         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4400         bool is_hdmi;
4401         u32 coreclk, reg_val, dpll_md;
4402
4403         mutex_lock(&dev_priv->dpio_lock);
4404
4405         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4406
4407         bestn = crtc->config.dpll.n;
4408         bestm1 = crtc->config.dpll.m1;
4409         bestm2 = crtc->config.dpll.m2;
4410         bestp1 = crtc->config.dpll.p1;
4411         bestp2 = crtc->config.dpll.p2;
4412
4413         /* See eDP HDMI DPIO driver vbios notes doc */
4414
4415         /* PLL B needs special handling */
4416         if (pipe)
4417                 vlv_pllb_recal_opamp(dev_priv);
4418
4419         /* Set up Tx target for periodic Rcomp update */
4420         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4421
4422         /* Disable target IRef on PLL */
4423         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4424         reg_val &= 0x00ffffff;
4425         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4426
4427         /* Disable fast lock */
4428         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4429
4430         /* Set idtafcrecal before PLL is enabled */
4431         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4432         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4433         mdiv |= ((bestn << DPIO_N_SHIFT));
4434         mdiv |= (1 << DPIO_K_SHIFT);
4435
4436         /*
4437          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4438          * but we don't support that).
4439          * Note: don't use the DAC post divider as it seems unstable.
4440          */
4441         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4442         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4443
4444         mdiv |= DPIO_ENABLE_CALIBRATION;
4445         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4446
4447         /* Set HBR and RBR LPF coefficients */
4448         if (crtc->config.port_clock == 162000 ||
4449             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4450                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4451                                  0x005f0021);
4452         else
4453                 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4454                                  0x00d0000f);
4455
4456         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4457             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4458                 /* Use SSC source */
4459                 if (!pipe)
4460                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4461                                          0x0df40000);
4462                 else
4463                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4464                                          0x0df70000);
4465         } else { /* HDMI or VGA */
4466                 /* Use bend source */
4467                 if (!pipe)
4468                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4469                                          0x0df70000);
4470                 else
4471                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4472                                          0x0df40000);
4473         }
4474
4475         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4476         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4477         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4478             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4479                 coreclk |= 0x01000000;
4480         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4481
4482         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4483
4484         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4485                 if (encoder->pre_pll_enable)
4486                         encoder->pre_pll_enable(encoder);
4487
4488         /* Enable DPIO clock input */
4489         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4490                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4491         if (pipe)
4492                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4493
4494         dpll |= DPLL_VCO_ENABLE;
4495         I915_WRITE(DPLL(pipe), dpll);
4496         POSTING_READ(DPLL(pipe));
4497         udelay(150);
4498
4499         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4500                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4501
4502         dpll_md = (crtc->config.pixel_multiplier - 1)
4503                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4504         I915_WRITE(DPLL_MD(pipe), dpll_md);
4505         POSTING_READ(DPLL_MD(pipe));
4506
4507         if (crtc->config.has_dp_encoder)
4508                 intel_dp_set_m_n(crtc);
4509
4510         mutex_unlock(&dev_priv->dpio_lock);
4511 }
4512
4513 static void i9xx_update_pll(struct intel_crtc *crtc,
4514                             intel_clock_t *reduced_clock,
4515                             int num_connectors)
4516 {
4517         struct drm_device *dev = crtc->base.dev;
4518         struct drm_i915_private *dev_priv = dev->dev_private;
4519         struct intel_encoder *encoder;
4520         int pipe = crtc->pipe;
4521         u32 dpll;
4522         bool is_sdvo;
4523         struct dpll *clock = &crtc->config.dpll;
4524
4525         i9xx_update_pll_dividers(crtc, reduced_clock);
4526
4527         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4528                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4529
4530         dpll = DPLL_VGA_MODE_DIS;
4531
4532         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4533                 dpll |= DPLLB_MODE_LVDS;
4534         else
4535                 dpll |= DPLLB_MODE_DAC_SERIAL;
4536
4537         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4538                 dpll |= (crtc->config.pixel_multiplier - 1)
4539                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4540         }
4541
4542         if (is_sdvo)
4543                 dpll |= DPLL_DVO_HIGH_SPEED;
4544
4545         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4546                 dpll |= DPLL_DVO_HIGH_SPEED;
4547
4548         /* compute bitmask from p1 value */
4549         if (IS_PINEVIEW(dev))
4550                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4551         else {
4552                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4553                 if (IS_G4X(dev) && reduced_clock)
4554                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4555         }
4556         switch (clock->p2) {
4557         case 5:
4558                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4559                 break;
4560         case 7:
4561                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4562                 break;
4563         case 10:
4564                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4565                 break;
4566         case 14:
4567                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4568                 break;
4569         }
4570         if (INTEL_INFO(dev)->gen >= 4)
4571                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4572
4573         if (crtc->config.sdvo_tv_clock)
4574                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4575         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4576                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4577                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4578         else
4579                 dpll |= PLL_REF_INPUT_DREFCLK;
4580
4581         dpll |= DPLL_VCO_ENABLE;
4582         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4583         POSTING_READ(DPLL(pipe));
4584         udelay(150);
4585
4586         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4587                 if (encoder->pre_pll_enable)
4588                         encoder->pre_pll_enable(encoder);
4589
4590         if (crtc->config.has_dp_encoder)
4591                 intel_dp_set_m_n(crtc);
4592
4593         I915_WRITE(DPLL(pipe), dpll);
4594
4595         /* Wait for the clocks to stabilize. */
4596         POSTING_READ(DPLL(pipe));
4597         udelay(150);
4598
4599         if (INTEL_INFO(dev)->gen >= 4) {
4600                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4601                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4602                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4603         } else {
4604                 /* The pixel multiplier can only be updated once the
4605                  * DPLL is enabled and the clocks are stable.
4606                  *
4607                  * So write it again.
4608                  */
4609                 I915_WRITE(DPLL(pipe), dpll);
4610         }
4611 }
4612
4613 static void i8xx_update_pll(struct intel_crtc *crtc,
4614                             intel_clock_t *reduced_clock,
4615                             int num_connectors)
4616 {
4617         struct drm_device *dev = crtc->base.dev;
4618         struct drm_i915_private *dev_priv = dev->dev_private;
4619         struct intel_encoder *encoder;
4620         int pipe = crtc->pipe;
4621         u32 dpll;
4622         struct dpll *clock = &crtc->config.dpll;
4623
4624         i9xx_update_pll_dividers(crtc, reduced_clock);
4625
4626         dpll = DPLL_VGA_MODE_DIS;
4627
4628         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4629                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4630         } else {
4631                 if (clock->p1 == 2)
4632                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4633                 else
4634                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4635                 if (clock->p2 == 4)
4636                         dpll |= PLL_P2_DIVIDE_BY_4;
4637         }
4638
4639         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4640                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4641                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4642         else
4643                 dpll |= PLL_REF_INPUT_DREFCLK;
4644
4645         dpll |= DPLL_VCO_ENABLE;
4646         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4647         POSTING_READ(DPLL(pipe));
4648         udelay(150);
4649
4650         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4651                 if (encoder->pre_pll_enable)
4652                         encoder->pre_pll_enable(encoder);
4653
4654         I915_WRITE(DPLL(pipe), dpll);
4655
4656         /* Wait for the clocks to stabilize. */
4657         POSTING_READ(DPLL(pipe));
4658         udelay(150);
4659
4660         /* The pixel multiplier can only be updated once the
4661          * DPLL is enabled and the clocks are stable.
4662          *
4663          * So write it again.
4664          */
4665         I915_WRITE(DPLL(pipe), dpll);
4666 }
4667
4668 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4669 {
4670         struct drm_device *dev = intel_crtc->base.dev;
4671         struct drm_i915_private *dev_priv = dev->dev_private;
4672         enum pipe pipe = intel_crtc->pipe;
4673         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4674         struct drm_display_mode *adjusted_mode =
4675                 &intel_crtc->config.adjusted_mode;
4676         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4677         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4678
4679         /* We need to be careful not to changed the adjusted mode, for otherwise
4680          * the hw state checker will get angry at the mismatch. */
4681         crtc_vtotal = adjusted_mode->crtc_vtotal;
4682         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4683
4684         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4685                 /* the chip adds 2 halflines automatically */
4686                 crtc_vtotal -= 1;
4687                 crtc_vblank_end -= 1;
4688                 vsyncshift = adjusted_mode->crtc_hsync_start
4689                              - adjusted_mode->crtc_htotal / 2;
4690         } else {
4691                 vsyncshift = 0;
4692         }
4693
4694         if (INTEL_INFO(dev)->gen > 3)
4695                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4696
4697         I915_WRITE(HTOTAL(cpu_transcoder),
4698                    (adjusted_mode->crtc_hdisplay - 1) |
4699                    ((adjusted_mode->crtc_htotal - 1) << 16));
4700         I915_WRITE(HBLANK(cpu_transcoder),
4701                    (adjusted_mode->crtc_hblank_start - 1) |
4702                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4703         I915_WRITE(HSYNC(cpu_transcoder),
4704                    (adjusted_mode->crtc_hsync_start - 1) |
4705                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4706
4707         I915_WRITE(VTOTAL(cpu_transcoder),
4708                    (adjusted_mode->crtc_vdisplay - 1) |
4709                    ((crtc_vtotal - 1) << 16));
4710         I915_WRITE(VBLANK(cpu_transcoder),
4711                    (adjusted_mode->crtc_vblank_start - 1) |
4712                    ((crtc_vblank_end - 1) << 16));
4713         I915_WRITE(VSYNC(cpu_transcoder),
4714                    (adjusted_mode->crtc_vsync_start - 1) |
4715                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4716
4717         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4718          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4719          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4720          * bits. */
4721         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4722             (pipe == PIPE_B || pipe == PIPE_C))
4723                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4724
4725         /* pipesrc controls the size that is scaled from, which should
4726          * always be the user's requested size.
4727          */
4728         I915_WRITE(PIPESRC(pipe),
4729                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4730 }
4731
4732 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4733                                    struct intel_crtc_config *pipe_config)
4734 {
4735         struct drm_device *dev = crtc->base.dev;
4736         struct drm_i915_private *dev_priv = dev->dev_private;
4737         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4738         uint32_t tmp;
4739
4740         tmp = I915_READ(HTOTAL(cpu_transcoder));
4741         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4742         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4743         tmp = I915_READ(HBLANK(cpu_transcoder));
4744         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4745         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4746         tmp = I915_READ(HSYNC(cpu_transcoder));
4747         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4748         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4749
4750         tmp = I915_READ(VTOTAL(cpu_transcoder));
4751         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4752         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4753         tmp = I915_READ(VBLANK(cpu_transcoder));
4754         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4755         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4756         tmp = I915_READ(VSYNC(cpu_transcoder));
4757         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4758         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4759
4760         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4761                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4762                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4763                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4764         }
4765
4766         tmp = I915_READ(PIPESRC(crtc->pipe));
4767         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4768         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4769 }
4770
4771 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4772 {
4773         struct drm_device *dev = intel_crtc->base.dev;
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775         uint32_t pipeconf;
4776
4777         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4778
4779         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4780                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4781                  * core speed.
4782                  *
4783                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4784                  * pipe == 0 check?
4785                  */
4786                 if (intel_crtc->config.requested_mode.clock >
4787                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4788                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4789                 else
4790                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4791         }
4792
4793         /* only g4x and later have fancy bpc/dither controls */
4794         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4795                 pipeconf &= ~(PIPECONF_BPC_MASK |
4796                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4797
4798                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4799                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4800                         pipeconf |= PIPECONF_DITHER_EN |
4801                                     PIPECONF_DITHER_TYPE_SP;
4802
4803                 switch (intel_crtc->config.pipe_bpp) {
4804                 case 18:
4805                         pipeconf |= PIPECONF_6BPC;
4806                         break;
4807                 case 24:
4808                         pipeconf |= PIPECONF_8BPC;
4809                         break;
4810                 case 30:
4811                         pipeconf |= PIPECONF_10BPC;
4812                         break;
4813                 default:
4814                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4815                         BUG();
4816                 }
4817         }
4818
4819         if (HAS_PIPE_CXSR(dev)) {
4820                 if (intel_crtc->lowfreq_avail) {
4821                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4822                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4823                 } else {
4824                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4825                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4826                 }
4827         }
4828
4829         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4830         if (!IS_GEN2(dev) &&
4831             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4832                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4833         else
4834                 pipeconf |= PIPECONF_PROGRESSIVE;
4835
4836         if (IS_VALLEYVIEW(dev)) {
4837                 if (intel_crtc->config.limited_color_range)
4838                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4839                 else
4840                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4841         }
4842
4843         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4844         POSTING_READ(PIPECONF(intel_crtc->pipe));
4845 }
4846
4847 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4848                               int x, int y,
4849                               struct drm_framebuffer *fb)
4850 {
4851         struct drm_device *dev = crtc->dev;
4852         struct drm_i915_private *dev_priv = dev->dev_private;
4853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4855         int pipe = intel_crtc->pipe;
4856         int plane = intel_crtc->plane;
4857         int refclk, num_connectors = 0;
4858         intel_clock_t clock, reduced_clock;
4859         u32 dspcntr;
4860         bool ok, has_reduced_clock = false;
4861         bool is_lvds = false;
4862         struct intel_encoder *encoder;
4863         const intel_limit_t *limit;
4864         int ret;
4865
4866         for_each_encoder_on_crtc(dev, crtc, encoder) {
4867                 switch (encoder->type) {
4868                 case INTEL_OUTPUT_LVDS:
4869                         is_lvds = true;
4870                         break;
4871                 }
4872
4873                 num_connectors++;
4874         }
4875
4876         refclk = i9xx_get_refclk(crtc, num_connectors);
4877
4878         /*
4879          * Returns a set of divisors for the desired target clock with the given
4880          * refclk, or FALSE.  The returned values represent the clock equation:
4881          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4882          */
4883         limit = intel_limit(crtc, refclk);
4884         ok = dev_priv->display.find_dpll(limit, crtc,
4885                                          intel_crtc->config.port_clock,
4886                                          refclk, NULL, &clock);
4887         if (!ok && !intel_crtc->config.clock_set) {
4888                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4889                 return -EINVAL;
4890         }
4891
4892         /* Ensure that the cursor is valid for the new mode before changing... */
4893         intel_crtc_update_cursor(crtc, true);
4894
4895         if (is_lvds && dev_priv->lvds_downclock_avail) {
4896                 /*
4897                  * Ensure we match the reduced clock's P to the target clock.
4898                  * If the clocks don't match, we can't switch the display clock
4899                  * by using the FP0/FP1. In such case we will disable the LVDS
4900                  * downclock feature.
4901                 */
4902                 has_reduced_clock =
4903                         dev_priv->display.find_dpll(limit, crtc,
4904                                                     dev_priv->lvds_downclock,
4905                                                     refclk, &clock,
4906                                                     &reduced_clock);
4907         }
4908         /* Compat-code for transition, will disappear. */
4909         if (!intel_crtc->config.clock_set) {
4910                 intel_crtc->config.dpll.n = clock.n;
4911                 intel_crtc->config.dpll.m1 = clock.m1;
4912                 intel_crtc->config.dpll.m2 = clock.m2;
4913                 intel_crtc->config.dpll.p1 = clock.p1;
4914                 intel_crtc->config.dpll.p2 = clock.p2;
4915         }
4916
4917         if (IS_GEN2(dev))
4918                 i8xx_update_pll(intel_crtc,
4919                                 has_reduced_clock ? &reduced_clock : NULL,
4920                                 num_connectors);
4921         else if (IS_VALLEYVIEW(dev))
4922                 vlv_update_pll(intel_crtc);
4923         else
4924                 i9xx_update_pll(intel_crtc,
4925                                 has_reduced_clock ? &reduced_clock : NULL,
4926                                 num_connectors);
4927
4928         /* Set up the display plane register */
4929         dspcntr = DISPPLANE_GAMMA_ENABLE;
4930
4931         if (!IS_VALLEYVIEW(dev)) {
4932                 if (pipe == 0)
4933                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4934                 else
4935                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4936         }
4937
4938         intel_set_pipe_timings(intel_crtc);
4939
4940         /* pipesrc and dspsize control the size that is scaled from,
4941          * which should always be the user's requested size.
4942          */
4943         I915_WRITE(DSPSIZE(plane),
4944                    ((mode->vdisplay - 1) << 16) |
4945                    (mode->hdisplay - 1));
4946         I915_WRITE(DSPPOS(plane), 0);
4947
4948         i9xx_set_pipeconf(intel_crtc);
4949
4950         I915_WRITE(DSPCNTR(plane), dspcntr);
4951         POSTING_READ(DSPCNTR(plane));
4952
4953         ret = intel_pipe_set_base(crtc, x, y, fb);
4954
4955         intel_update_watermarks(dev);
4956
4957         return ret;
4958 }
4959
4960 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4961                                  struct intel_crtc_config *pipe_config)
4962 {
4963         struct drm_device *dev = crtc->base.dev;
4964         struct drm_i915_private *dev_priv = dev->dev_private;
4965         uint32_t tmp;
4966
4967         tmp = I915_READ(PFIT_CONTROL);
4968
4969         if (INTEL_INFO(dev)->gen < 4) {
4970                 if (crtc->pipe != PIPE_B)
4971                         return;
4972
4973                 /* gen2/3 store dither state in pfit control, needs to match */
4974                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4975         } else {
4976                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4977                         return;
4978         }
4979
4980         if (!(tmp & PFIT_ENABLE))
4981                 return;
4982
4983         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4984         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4985         if (INTEL_INFO(dev)->gen < 5)
4986                 pipe_config->gmch_pfit.lvds_border_bits =
4987                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4988 }
4989
4990 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4991                                  struct intel_crtc_config *pipe_config)
4992 {
4993         struct drm_device *dev = crtc->base.dev;
4994         struct drm_i915_private *dev_priv = dev->dev_private;
4995         uint32_t tmp;
4996
4997         pipe_config->cpu_transcoder = crtc->pipe;
4998
4999         tmp = I915_READ(PIPECONF(crtc->pipe));
5000         if (!(tmp & PIPECONF_ENABLE))
5001                 return false;
5002
5003         intel_get_pipe_timings(crtc, pipe_config);
5004
5005         i9xx_get_pfit_config(crtc, pipe_config);
5006
5007         if (INTEL_INFO(dev)->gen >= 4) {
5008                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5009                 pipe_config->pixel_multiplier =
5010                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5011                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5012         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5013                 tmp = I915_READ(DPLL(crtc->pipe));
5014                 pipe_config->pixel_multiplier =
5015                         ((tmp & SDVO_MULTIPLIER_MASK)
5016                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5017         } else {
5018                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5019                  * port and will be fixed up in the encoder->get_config
5020                  * function. */
5021                 pipe_config->pixel_multiplier = 1;
5022         }
5023
5024         return true;
5025 }
5026
5027 static void ironlake_init_pch_refclk(struct drm_device *dev)
5028 {
5029         struct drm_i915_private *dev_priv = dev->dev_private;
5030         struct drm_mode_config *mode_config = &dev->mode_config;
5031         struct intel_encoder *encoder;
5032         u32 val, final;
5033         bool has_lvds = false;
5034         bool has_cpu_edp = false;
5035         bool has_panel = false;
5036         bool has_ck505 = false;
5037         bool can_ssc = false;
5038
5039         /* We need to take the global config into account */
5040         list_for_each_entry(encoder, &mode_config->encoder_list,
5041                             base.head) {
5042                 switch (encoder->type) {
5043                 case INTEL_OUTPUT_LVDS:
5044                         has_panel = true;
5045                         has_lvds = true;
5046                         break;
5047                 case INTEL_OUTPUT_EDP:
5048                         has_panel = true;
5049                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5050                                 has_cpu_edp = true;
5051                         break;
5052                 }
5053         }
5054
5055         if (HAS_PCH_IBX(dev)) {
5056                 has_ck505 = dev_priv->vbt.display_clock_mode;
5057                 can_ssc = has_ck505;
5058         } else {
5059                 has_ck505 = false;
5060                 can_ssc = true;
5061         }
5062
5063         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5064                       has_panel, has_lvds, has_ck505);
5065
5066         /* Ironlake: try to setup display ref clock before DPLL
5067          * enabling. This is only under driver's control after
5068          * PCH B stepping, previous chipset stepping should be
5069          * ignoring this setting.
5070          */
5071         val = I915_READ(PCH_DREF_CONTROL);
5072
5073         /* As we must carefully and slowly disable/enable each source in turn,
5074          * compute the final state we want first and check if we need to
5075          * make any changes at all.
5076          */
5077         final = val;
5078         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5079         if (has_ck505)
5080                 final |= DREF_NONSPREAD_CK505_ENABLE;
5081         else
5082                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5083
5084         final &= ~DREF_SSC_SOURCE_MASK;
5085         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5086         final &= ~DREF_SSC1_ENABLE;
5087
5088         if (has_panel) {
5089                 final |= DREF_SSC_SOURCE_ENABLE;
5090
5091                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5092                         final |= DREF_SSC1_ENABLE;
5093
5094                 if (has_cpu_edp) {
5095                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5096                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5097                         else
5098                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5099                 } else
5100                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5101         } else {
5102                 final |= DREF_SSC_SOURCE_DISABLE;
5103                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5104         }
5105
5106         if (final == val)
5107                 return;
5108
5109         /* Always enable nonspread source */
5110         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5111
5112         if (has_ck505)
5113                 val |= DREF_NONSPREAD_CK505_ENABLE;
5114         else
5115                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5116
5117         if (has_panel) {
5118                 val &= ~DREF_SSC_SOURCE_MASK;
5119                 val |= DREF_SSC_SOURCE_ENABLE;
5120
5121                 /* SSC must be turned on before enabling the CPU output  */
5122                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5123                         DRM_DEBUG_KMS("Using SSC on panel\n");
5124                         val |= DREF_SSC1_ENABLE;
5125                 } else
5126                         val &= ~DREF_SSC1_ENABLE;
5127
5128                 /* Get SSC going before enabling the outputs */
5129                 I915_WRITE(PCH_DREF_CONTROL, val);
5130                 POSTING_READ(PCH_DREF_CONTROL);
5131                 udelay(200);
5132
5133                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5134
5135                 /* Enable CPU source on CPU attached eDP */
5136                 if (has_cpu_edp) {
5137                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5138                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5139                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5140                         }
5141                         else
5142                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5143                 } else
5144                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5145
5146                 I915_WRITE(PCH_DREF_CONTROL, val);
5147                 POSTING_READ(PCH_DREF_CONTROL);
5148                 udelay(200);
5149         } else {
5150                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5151
5152                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5153
5154                 /* Turn off CPU output */
5155                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5156
5157                 I915_WRITE(PCH_DREF_CONTROL, val);
5158                 POSTING_READ(PCH_DREF_CONTROL);
5159                 udelay(200);
5160
5161                 /* Turn off the SSC source */
5162                 val &= ~DREF_SSC_SOURCE_MASK;
5163                 val |= DREF_SSC_SOURCE_DISABLE;
5164
5165                 /* Turn off SSC1 */
5166                 val &= ~DREF_SSC1_ENABLE;
5167
5168                 I915_WRITE(PCH_DREF_CONTROL, val);
5169                 POSTING_READ(PCH_DREF_CONTROL);
5170                 udelay(200);
5171         }
5172
5173         BUG_ON(val != final);
5174 }
5175
5176 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5177 static void lpt_init_pch_refclk(struct drm_device *dev)
5178 {
5179         struct drm_i915_private *dev_priv = dev->dev_private;
5180         struct drm_mode_config *mode_config = &dev->mode_config;
5181         struct intel_encoder *encoder;
5182         bool has_vga = false;
5183         bool is_sdv = false;
5184         u32 tmp;
5185
5186         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5187                 switch (encoder->type) {
5188                 case INTEL_OUTPUT_ANALOG:
5189                         has_vga = true;
5190                         break;
5191                 }
5192         }
5193
5194         if (!has_vga)
5195                 return;
5196
5197         mutex_lock(&dev_priv->dpio_lock);
5198
5199         /* XXX: Rip out SDV support once Haswell ships for real. */
5200         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5201                 is_sdv = true;
5202
5203         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5204         tmp &= ~SBI_SSCCTL_DISABLE;
5205         tmp |= SBI_SSCCTL_PATHALT;
5206         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5207
5208         udelay(24);
5209
5210         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5211         tmp &= ~SBI_SSCCTL_PATHALT;
5212         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5213
5214         if (!is_sdv) {
5215                 tmp = I915_READ(SOUTH_CHICKEN2);
5216                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5217                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5218
5219                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5220                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5221                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5222
5223                 tmp = I915_READ(SOUTH_CHICKEN2);
5224                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5225                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5226
5227                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5228                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5229                                        100))
5230                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5231         }
5232
5233         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5234         tmp &= ~(0xFF << 24);
5235         tmp |= (0x12 << 24);
5236         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5237
5238         if (is_sdv) {
5239                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5240                 tmp |= 0x7FFF;
5241                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5242         }
5243
5244         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5245         tmp |= (1 << 11);
5246         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5247
5248         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5249         tmp |= (1 << 11);
5250         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5251
5252         if (is_sdv) {
5253                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5254                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5255                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5256
5257                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5258                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5259                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5260
5261                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5262                 tmp |= (0x3F << 8);
5263                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5264
5265                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5266                 tmp |= (0x3F << 8);
5267                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5268         }
5269
5270         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5271         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5272         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5273
5274         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5275         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5276         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5277
5278         if (!is_sdv) {
5279                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5280                 tmp &= ~(7 << 13);
5281                 tmp |= (5 << 13);
5282                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5283
5284                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5285                 tmp &= ~(7 << 13);
5286                 tmp |= (5 << 13);
5287                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5288         }
5289
5290         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5291         tmp &= ~0xFF;
5292         tmp |= 0x1C;
5293         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5294
5295         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5296         tmp &= ~0xFF;
5297         tmp |= 0x1C;
5298         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5299
5300         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5301         tmp &= ~(0xFF << 16);
5302         tmp |= (0x1C << 16);
5303         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5304
5305         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5306         tmp &= ~(0xFF << 16);
5307         tmp |= (0x1C << 16);
5308         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5309
5310         if (!is_sdv) {
5311                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5312                 tmp |= (1 << 27);
5313                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5314
5315                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5316                 tmp |= (1 << 27);
5317                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5318
5319                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5320                 tmp &= ~(0xF << 28);
5321                 tmp |= (4 << 28);
5322                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5323
5324                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5325                 tmp &= ~(0xF << 28);
5326                 tmp |= (4 << 28);
5327                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5328         }
5329
5330         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5331         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5332         tmp |= SBI_DBUFF0_ENABLE;
5333         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5334
5335         mutex_unlock(&dev_priv->dpio_lock);
5336 }
5337
5338 /*
5339  * Initialize reference clocks when the driver loads
5340  */
5341 void intel_init_pch_refclk(struct drm_device *dev)
5342 {
5343         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5344                 ironlake_init_pch_refclk(dev);
5345         else if (HAS_PCH_LPT(dev))
5346                 lpt_init_pch_refclk(dev);
5347 }
5348
5349 static int ironlake_get_refclk(struct drm_crtc *crtc)
5350 {
5351         struct drm_device *dev = crtc->dev;
5352         struct drm_i915_private *dev_priv = dev->dev_private;
5353         struct intel_encoder *encoder;
5354         int num_connectors = 0;
5355         bool is_lvds = false;
5356
5357         for_each_encoder_on_crtc(dev, crtc, encoder) {
5358                 switch (encoder->type) {
5359                 case INTEL_OUTPUT_LVDS:
5360                         is_lvds = true;
5361                         break;
5362                 }
5363                 num_connectors++;
5364         }
5365
5366         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5367                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5368                               dev_priv->vbt.lvds_ssc_freq);
5369                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5370         }
5371
5372         return 120000;
5373 }
5374
5375 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5376 {
5377         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5379         int pipe = intel_crtc->pipe;
5380         uint32_t val;
5381
5382         val = I915_READ(PIPECONF(pipe));
5383
5384         val &= ~PIPECONF_BPC_MASK;
5385         switch (intel_crtc->config.pipe_bpp) {
5386         case 18:
5387                 val |= PIPECONF_6BPC;
5388                 break;
5389         case 24:
5390                 val |= PIPECONF_8BPC;
5391                 break;
5392         case 30:
5393                 val |= PIPECONF_10BPC;
5394                 break;
5395         case 36:
5396                 val |= PIPECONF_12BPC;
5397                 break;
5398         default:
5399                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5400                 BUG();
5401         }
5402
5403         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5404         if (intel_crtc->config.dither)
5405                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5406
5407         val &= ~PIPECONF_INTERLACE_MASK;
5408         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5409                 val |= PIPECONF_INTERLACED_ILK;
5410         else
5411                 val |= PIPECONF_PROGRESSIVE;
5412
5413         if (intel_crtc->config.limited_color_range)
5414                 val |= PIPECONF_COLOR_RANGE_SELECT;
5415         else
5416                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5417
5418         I915_WRITE(PIPECONF(pipe), val);
5419         POSTING_READ(PIPECONF(pipe));
5420 }
5421
5422 /*
5423  * Set up the pipe CSC unit.
5424  *
5425  * Currently only full range RGB to limited range RGB conversion
5426  * is supported, but eventually this should handle various
5427  * RGB<->YCbCr scenarios as well.
5428  */
5429 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5430 {
5431         struct drm_device *dev = crtc->dev;
5432         struct drm_i915_private *dev_priv = dev->dev_private;
5433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5434         int pipe = intel_crtc->pipe;
5435         uint16_t coeff = 0x7800; /* 1.0 */
5436
5437         /*
5438          * TODO: Check what kind of values actually come out of the pipe
5439          * with these coeff/postoff values and adjust to get the best
5440          * accuracy. Perhaps we even need to take the bpc value into
5441          * consideration.
5442          */
5443
5444         if (intel_crtc->config.limited_color_range)
5445                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5446
5447         /*
5448          * GY/GU and RY/RU should be the other way around according
5449          * to BSpec, but reality doesn't agree. Just set them up in
5450          * a way that results in the correct picture.
5451          */
5452         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5453         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5454
5455         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5456         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5457
5458         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5459         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5460
5461         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5462         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5463         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5464
5465         if (INTEL_INFO(dev)->gen > 6) {
5466                 uint16_t postoff = 0;
5467
5468                 if (intel_crtc->config.limited_color_range)
5469                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5470
5471                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5472                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5473                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5474
5475                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5476         } else {
5477                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5478
5479                 if (intel_crtc->config.limited_color_range)
5480                         mode |= CSC_BLACK_SCREEN_OFFSET;
5481
5482                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5483         }
5484 }
5485
5486 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5487 {
5488         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5490         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5491         uint32_t val;
5492
5493         val = I915_READ(PIPECONF(cpu_transcoder));
5494
5495         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5496         if (intel_crtc->config.dither)
5497                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5498
5499         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5500         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5501                 val |= PIPECONF_INTERLACED_ILK;
5502         else
5503                 val |= PIPECONF_PROGRESSIVE;
5504
5505         I915_WRITE(PIPECONF(cpu_transcoder), val);
5506         POSTING_READ(PIPECONF(cpu_transcoder));
5507 }
5508
5509 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5510                                     intel_clock_t *clock,
5511                                     bool *has_reduced_clock,
5512                                     intel_clock_t *reduced_clock)
5513 {
5514         struct drm_device *dev = crtc->dev;
5515         struct drm_i915_private *dev_priv = dev->dev_private;
5516         struct intel_encoder *intel_encoder;
5517         int refclk;
5518         const intel_limit_t *limit;
5519         bool ret, is_lvds = false;
5520
5521         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5522                 switch (intel_encoder->type) {
5523                 case INTEL_OUTPUT_LVDS:
5524                         is_lvds = true;
5525                         break;
5526                 }
5527         }
5528
5529         refclk = ironlake_get_refclk(crtc);
5530
5531         /*
5532          * Returns a set of divisors for the desired target clock with the given
5533          * refclk, or FALSE.  The returned values represent the clock equation:
5534          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5535          */
5536         limit = intel_limit(crtc, refclk);
5537         ret = dev_priv->display.find_dpll(limit, crtc,
5538                                           to_intel_crtc(crtc)->config.port_clock,
5539                                           refclk, NULL, clock);
5540         if (!ret)
5541                 return false;
5542
5543         if (is_lvds && dev_priv->lvds_downclock_avail) {
5544                 /*
5545                  * Ensure we match the reduced clock's P to the target clock.
5546                  * If the clocks don't match, we can't switch the display clock
5547                  * by using the FP0/FP1. In such case we will disable the LVDS
5548                  * downclock feature.
5549                 */
5550                 *has_reduced_clock =
5551                         dev_priv->display.find_dpll(limit, crtc,
5552                                                     dev_priv->lvds_downclock,
5553                                                     refclk, clock,
5554                                                     reduced_clock);
5555         }
5556
5557         return true;
5558 }
5559
5560 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5561 {
5562         struct drm_i915_private *dev_priv = dev->dev_private;
5563         uint32_t temp;
5564
5565         temp = I915_READ(SOUTH_CHICKEN1);
5566         if (temp & FDI_BC_BIFURCATION_SELECT)
5567                 return;
5568
5569         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5570         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5571
5572         temp |= FDI_BC_BIFURCATION_SELECT;
5573         DRM_DEBUG_KMS("enabling fdi C rx\n");
5574         I915_WRITE(SOUTH_CHICKEN1, temp);
5575         POSTING_READ(SOUTH_CHICKEN1);
5576 }
5577
5578 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5579 {
5580         struct drm_device *dev = intel_crtc->base.dev;
5581         struct drm_i915_private *dev_priv = dev->dev_private;
5582
5583         switch (intel_crtc->pipe) {
5584         case PIPE_A:
5585                 break;
5586         case PIPE_B:
5587                 if (intel_crtc->config.fdi_lanes > 2)
5588                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5589                 else
5590                         cpt_enable_fdi_bc_bifurcation(dev);
5591
5592                 break;
5593         case PIPE_C:
5594                 cpt_enable_fdi_bc_bifurcation(dev);
5595
5596                 break;
5597         default:
5598                 BUG();
5599         }
5600 }
5601
5602 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5603 {
5604         /*
5605          * Account for spread spectrum to avoid
5606          * oversubscribing the link. Max center spread
5607          * is 2.5%; use 5% for safety's sake.
5608          */
5609         u32 bps = target_clock * bpp * 21 / 20;
5610         return bps / (link_bw * 8) + 1;
5611 }
5612
5613 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5614 {
5615         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5616 }
5617
5618 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5619                                       u32 *fp,
5620                                       intel_clock_t *reduced_clock, u32 *fp2)
5621 {
5622         struct drm_crtc *crtc = &intel_crtc->base;
5623         struct drm_device *dev = crtc->dev;
5624         struct drm_i915_private *dev_priv = dev->dev_private;
5625         struct intel_encoder *intel_encoder;
5626         uint32_t dpll;
5627         int factor, num_connectors = 0;
5628         bool is_lvds = false, is_sdvo = false;
5629
5630         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5631                 switch (intel_encoder->type) {
5632                 case INTEL_OUTPUT_LVDS:
5633                         is_lvds = true;
5634                         break;
5635                 case INTEL_OUTPUT_SDVO:
5636                 case INTEL_OUTPUT_HDMI:
5637                         is_sdvo = true;
5638                         break;
5639                 }
5640
5641                 num_connectors++;
5642         }
5643
5644         /* Enable autotuning of the PLL clock (if permissible) */
5645         factor = 21;
5646         if (is_lvds) {
5647                 if ((intel_panel_use_ssc(dev_priv) &&
5648                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5649                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5650                         factor = 25;
5651         } else if (intel_crtc->config.sdvo_tv_clock)
5652                 factor = 20;
5653
5654         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5655                 *fp |= FP_CB_TUNE;
5656
5657         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5658                 *fp2 |= FP_CB_TUNE;
5659
5660         dpll = 0;
5661
5662         if (is_lvds)
5663                 dpll |= DPLLB_MODE_LVDS;
5664         else
5665                 dpll |= DPLLB_MODE_DAC_SERIAL;
5666
5667         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5668                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5669
5670         if (is_sdvo)
5671                 dpll |= DPLL_DVO_HIGH_SPEED;
5672         if (intel_crtc->config.has_dp_encoder)
5673                 dpll |= DPLL_DVO_HIGH_SPEED;
5674
5675         /* compute bitmask from p1 value */
5676         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5677         /* also FPA1 */
5678         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5679
5680         switch (intel_crtc->config.dpll.p2) {
5681         case 5:
5682                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5683                 break;
5684         case 7:
5685                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5686                 break;
5687         case 10:
5688                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5689                 break;
5690         case 14:
5691                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5692                 break;
5693         }
5694
5695         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5696                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5697         else
5698                 dpll |= PLL_REF_INPUT_DREFCLK;
5699
5700         return dpll;
5701 }
5702
5703 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5704                                   int x, int y,
5705                                   struct drm_framebuffer *fb)
5706 {
5707         struct drm_device *dev = crtc->dev;
5708         struct drm_i915_private *dev_priv = dev->dev_private;
5709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5710         int pipe = intel_crtc->pipe;
5711         int plane = intel_crtc->plane;
5712         int num_connectors = 0;
5713         intel_clock_t clock, reduced_clock;
5714         u32 dpll = 0, fp = 0, fp2 = 0;
5715         bool ok, has_reduced_clock = false;
5716         bool is_lvds = false;
5717         struct intel_encoder *encoder;
5718         int ret;
5719
5720         for_each_encoder_on_crtc(dev, crtc, encoder) {
5721                 switch (encoder->type) {
5722                 case INTEL_OUTPUT_LVDS:
5723                         is_lvds = true;
5724                         break;
5725                 }
5726
5727                 num_connectors++;
5728         }
5729
5730         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5731              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5732
5733         ok = ironlake_compute_clocks(crtc, &clock,
5734                                      &has_reduced_clock, &reduced_clock);
5735         if (!ok && !intel_crtc->config.clock_set) {
5736                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5737                 return -EINVAL;
5738         }
5739         /* Compat-code for transition, will disappear. */
5740         if (!intel_crtc->config.clock_set) {
5741                 intel_crtc->config.dpll.n = clock.n;
5742                 intel_crtc->config.dpll.m1 = clock.m1;
5743                 intel_crtc->config.dpll.m2 = clock.m2;
5744                 intel_crtc->config.dpll.p1 = clock.p1;
5745                 intel_crtc->config.dpll.p2 = clock.p2;
5746         }
5747
5748         /* Ensure that the cursor is valid for the new mode before changing... */
5749         intel_crtc_update_cursor(crtc, true);
5750
5751         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5752         if (intel_crtc->config.has_pch_encoder) {
5753                 struct intel_pch_pll *pll;
5754
5755                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5756                 if (has_reduced_clock)
5757                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5758
5759                 dpll = ironlake_compute_dpll(intel_crtc,
5760                                              &fp, &reduced_clock,
5761                                              has_reduced_clock ? &fp2 : NULL);
5762
5763                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5764                 if (pll == NULL) {
5765                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5766                                          pipe_name(pipe));
5767                         return -EINVAL;
5768                 }
5769         } else
5770                 intel_put_pch_pll(intel_crtc);
5771
5772         if (intel_crtc->config.has_dp_encoder)
5773                 intel_dp_set_m_n(intel_crtc);
5774
5775         for_each_encoder_on_crtc(dev, crtc, encoder)
5776                 if (encoder->pre_pll_enable)
5777                         encoder->pre_pll_enable(encoder);
5778
5779         if (intel_crtc->pch_pll) {
5780                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5781
5782                 /* Wait for the clocks to stabilize. */
5783                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5784                 udelay(150);
5785
5786                 /* The pixel multiplier can only be updated once the
5787                  * DPLL is enabled and the clocks are stable.
5788                  *
5789                  * So write it again.
5790                  */
5791                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5792         }
5793
5794         intel_crtc->lowfreq_avail = false;
5795         if (intel_crtc->pch_pll) {
5796                 if (is_lvds && has_reduced_clock && i915_powersave) {
5797                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5798                         intel_crtc->lowfreq_avail = true;
5799                 } else {
5800                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5801                 }
5802         }
5803
5804         intel_set_pipe_timings(intel_crtc);
5805
5806         if (intel_crtc->config.has_pch_encoder) {
5807                 intel_cpu_transcoder_set_m_n(intel_crtc,
5808                                              &intel_crtc->config.fdi_m_n);
5809         }
5810
5811         if (IS_IVYBRIDGE(dev))
5812                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5813
5814         ironlake_set_pipeconf(crtc);
5815
5816         /* Set up the display plane register */
5817         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5818         POSTING_READ(DSPCNTR(plane));
5819
5820         ret = intel_pipe_set_base(crtc, x, y, fb);
5821
5822         intel_update_watermarks(dev);
5823
5824         return ret;
5825 }
5826
5827 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5828                                         struct intel_crtc_config *pipe_config)
5829 {
5830         struct drm_device *dev = crtc->base.dev;
5831         struct drm_i915_private *dev_priv = dev->dev_private;
5832         enum transcoder transcoder = pipe_config->cpu_transcoder;
5833
5834         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5835         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5836         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5837                                         & ~TU_SIZE_MASK;
5838         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5839         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5840                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5841 }
5842
5843 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5844                                      struct intel_crtc_config *pipe_config)
5845 {
5846         struct drm_device *dev = crtc->base.dev;
5847         struct drm_i915_private *dev_priv = dev->dev_private;
5848         uint32_t tmp;
5849
5850         tmp = I915_READ(PF_CTL(crtc->pipe));
5851
5852         if (tmp & PF_ENABLE) {
5853                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5854                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5855
5856                 /* We currently do not free assignements of panel fitters on
5857                  * ivb/hsw (since we don't use the higher upscaling modes which
5858                  * differentiates them) so just WARN about this case for now. */
5859                 if (IS_GEN7(dev)) {
5860                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5861                                 PF_PIPE_SEL_IVB(crtc->pipe));
5862                 }
5863         }
5864 }
5865
5866 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5867                                      struct intel_crtc_config *pipe_config)
5868 {
5869         struct drm_device *dev = crtc->base.dev;
5870         struct drm_i915_private *dev_priv = dev->dev_private;
5871         uint32_t tmp;
5872
5873         pipe_config->cpu_transcoder = crtc->pipe;
5874
5875         tmp = I915_READ(PIPECONF(crtc->pipe));
5876         if (!(tmp & PIPECONF_ENABLE))
5877                 return false;
5878
5879         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5880                 pipe_config->has_pch_encoder = true;
5881
5882                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5883                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5884                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5885
5886                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5887
5888                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5889                  * since we don't have state tracking for pch clocks yet. */
5890                 pipe_config->pixel_multiplier = 1;
5891         } else {
5892                 pipe_config->pixel_multiplier = 1;
5893         }
5894
5895         intel_get_pipe_timings(crtc, pipe_config);
5896
5897         ironlake_get_pfit_config(crtc, pipe_config);
5898
5899         return true;
5900 }
5901
5902 static void haswell_modeset_global_resources(struct drm_device *dev)
5903 {
5904         bool enable = false;
5905         struct intel_crtc *crtc;
5906
5907         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5908                 if (!crtc->base.enabled)
5909                         continue;
5910
5911                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5912                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5913                         enable = true;
5914         }
5915
5916         intel_set_power_well(dev, enable);
5917 }
5918
5919 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5920                                  int x, int y,
5921                                  struct drm_framebuffer *fb)
5922 {
5923         struct drm_device *dev = crtc->dev;
5924         struct drm_i915_private *dev_priv = dev->dev_private;
5925         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5926         int plane = intel_crtc->plane;
5927         int ret;
5928
5929         if (!intel_ddi_pll_mode_set(crtc))
5930                 return -EINVAL;
5931
5932         /* Ensure that the cursor is valid for the new mode before changing... */
5933         intel_crtc_update_cursor(crtc, true);
5934
5935         if (intel_crtc->config.has_dp_encoder)
5936                 intel_dp_set_m_n(intel_crtc);
5937
5938         intel_crtc->lowfreq_avail = false;
5939
5940         intel_set_pipe_timings(intel_crtc);
5941
5942         if (intel_crtc->config.has_pch_encoder) {
5943                 intel_cpu_transcoder_set_m_n(intel_crtc,
5944                                              &intel_crtc->config.fdi_m_n);
5945         }
5946
5947         haswell_set_pipeconf(crtc);
5948
5949         intel_set_pipe_csc(crtc);
5950
5951         /* Set up the display plane register */
5952         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5953         POSTING_READ(DSPCNTR(plane));
5954
5955         ret = intel_pipe_set_base(crtc, x, y, fb);
5956
5957         intel_update_watermarks(dev);
5958
5959         return ret;
5960 }
5961
5962 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5963                                     struct intel_crtc_config *pipe_config)
5964 {
5965         struct drm_device *dev = crtc->base.dev;
5966         struct drm_i915_private *dev_priv = dev->dev_private;
5967         enum intel_display_power_domain pfit_domain;
5968         uint32_t tmp;
5969
5970         pipe_config->cpu_transcoder = crtc->pipe;
5971         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5972         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5973                 enum pipe trans_edp_pipe;
5974                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5975                 default:
5976                         WARN(1, "unknown pipe linked to edp transcoder\n");
5977                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5978                 case TRANS_DDI_EDP_INPUT_A_ON:
5979                         trans_edp_pipe = PIPE_A;
5980                         break;
5981                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5982                         trans_edp_pipe = PIPE_B;
5983                         break;
5984                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5985                         trans_edp_pipe = PIPE_C;
5986                         break;
5987                 }
5988
5989                 if (trans_edp_pipe == crtc->pipe)
5990                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5991         }
5992
5993         if (!intel_display_power_enabled(dev,
5994                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5995                 return false;
5996
5997         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5998         if (!(tmp & PIPECONF_ENABLE))
5999                 return false;
6000
6001         /*
6002          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6003          * DDI E. So just check whether this pipe is wired to DDI E and whether
6004          * the PCH transcoder is on.
6005          */
6006         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6007         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6008             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6009                 pipe_config->has_pch_encoder = true;
6010
6011                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6012                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6013                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6014
6015                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6016         }
6017
6018         intel_get_pipe_timings(crtc, pipe_config);
6019
6020         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6021         if (intel_display_power_enabled(dev, pfit_domain))
6022                 ironlake_get_pfit_config(crtc, pipe_config);
6023
6024         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6025                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6026
6027         pipe_config->pixel_multiplier = 1;
6028
6029         return true;
6030 }
6031
6032 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6033                                int x, int y,
6034                                struct drm_framebuffer *fb)
6035 {
6036         struct drm_device *dev = crtc->dev;
6037         struct drm_i915_private *dev_priv = dev->dev_private;
6038         struct drm_encoder_helper_funcs *encoder_funcs;
6039         struct intel_encoder *encoder;
6040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6041         struct drm_display_mode *adjusted_mode =
6042                 &intel_crtc->config.adjusted_mode;
6043         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6044         int pipe = intel_crtc->pipe;
6045         int ret;
6046
6047         drm_vblank_pre_modeset(dev, pipe);
6048
6049         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6050
6051         drm_vblank_post_modeset(dev, pipe);
6052
6053         if (ret != 0)
6054                 return ret;
6055
6056         for_each_encoder_on_crtc(dev, crtc, encoder) {
6057                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6058                         encoder->base.base.id,
6059                         drm_get_encoder_name(&encoder->base),
6060                         mode->base.id, mode->name);
6061                 if (encoder->mode_set) {
6062                         encoder->mode_set(encoder);
6063                 } else {
6064                         encoder_funcs = encoder->base.helper_private;
6065                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6066                 }
6067         }
6068
6069         return 0;
6070 }
6071
6072 static bool intel_eld_uptodate(struct drm_connector *connector,
6073                                int reg_eldv, uint32_t bits_eldv,
6074                                int reg_elda, uint32_t bits_elda,
6075                                int reg_edid)
6076 {
6077         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078         uint8_t *eld = connector->eld;
6079         uint32_t i;
6080
6081         i = I915_READ(reg_eldv);
6082         i &= bits_eldv;
6083
6084         if (!eld[0])
6085                 return !i;
6086
6087         if (!i)
6088                 return false;
6089
6090         i = I915_READ(reg_elda);
6091         i &= ~bits_elda;
6092         I915_WRITE(reg_elda, i);
6093
6094         for (i = 0; i < eld[2]; i++)
6095                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6096                         return false;
6097
6098         return true;
6099 }
6100
6101 static void g4x_write_eld(struct drm_connector *connector,
6102                           struct drm_crtc *crtc)
6103 {
6104         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6105         uint8_t *eld = connector->eld;
6106         uint32_t eldv;
6107         uint32_t len;
6108         uint32_t i;
6109
6110         i = I915_READ(G4X_AUD_VID_DID);
6111
6112         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6113                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6114         else
6115                 eldv = G4X_ELDV_DEVCTG;
6116
6117         if (intel_eld_uptodate(connector,
6118                                G4X_AUD_CNTL_ST, eldv,
6119                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6120                                G4X_HDMIW_HDMIEDID))
6121                 return;
6122
6123         i = I915_READ(G4X_AUD_CNTL_ST);
6124         i &= ~(eldv | G4X_ELD_ADDR);
6125         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6126         I915_WRITE(G4X_AUD_CNTL_ST, i);
6127
6128         if (!eld[0])
6129                 return;
6130
6131         len = min_t(uint8_t, eld[2], len);
6132         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6133         for (i = 0; i < len; i++)
6134                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6135
6136         i = I915_READ(G4X_AUD_CNTL_ST);
6137         i |= eldv;
6138         I915_WRITE(G4X_AUD_CNTL_ST, i);
6139 }
6140
6141 static void haswell_write_eld(struct drm_connector *connector,
6142                                      struct drm_crtc *crtc)
6143 {
6144         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6145         uint8_t *eld = connector->eld;
6146         struct drm_device *dev = crtc->dev;
6147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6148         uint32_t eldv;
6149         uint32_t i;
6150         int len;
6151         int pipe = to_intel_crtc(crtc)->pipe;
6152         int tmp;
6153
6154         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6155         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6156         int aud_config = HSW_AUD_CFG(pipe);
6157         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6158
6159
6160         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6161
6162         /* Audio output enable */
6163         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6164         tmp = I915_READ(aud_cntrl_st2);
6165         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6166         I915_WRITE(aud_cntrl_st2, tmp);
6167
6168         /* Wait for 1 vertical blank */
6169         intel_wait_for_vblank(dev, pipe);
6170
6171         /* Set ELD valid state */
6172         tmp = I915_READ(aud_cntrl_st2);
6173         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6174         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6175         I915_WRITE(aud_cntrl_st2, tmp);
6176         tmp = I915_READ(aud_cntrl_st2);
6177         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6178
6179         /* Enable HDMI mode */
6180         tmp = I915_READ(aud_config);
6181         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6182         /* clear N_programing_enable and N_value_index */
6183         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6184         I915_WRITE(aud_config, tmp);
6185
6186         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6187
6188         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6189         intel_crtc->eld_vld = true;
6190
6191         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6192                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6193                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6194                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6195         } else
6196                 I915_WRITE(aud_config, 0);
6197
6198         if (intel_eld_uptodate(connector,
6199                                aud_cntrl_st2, eldv,
6200                                aud_cntl_st, IBX_ELD_ADDRESS,
6201                                hdmiw_hdmiedid))
6202                 return;
6203
6204         i = I915_READ(aud_cntrl_st2);
6205         i &= ~eldv;
6206         I915_WRITE(aud_cntrl_st2, i);
6207
6208         if (!eld[0])
6209                 return;
6210
6211         i = I915_READ(aud_cntl_st);
6212         i &= ~IBX_ELD_ADDRESS;
6213         I915_WRITE(aud_cntl_st, i);
6214         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6215         DRM_DEBUG_DRIVER("port num:%d\n", i);
6216
6217         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6218         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6219         for (i = 0; i < len; i++)
6220                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6221
6222         i = I915_READ(aud_cntrl_st2);
6223         i |= eldv;
6224         I915_WRITE(aud_cntrl_st2, i);
6225
6226 }
6227
6228 static void ironlake_write_eld(struct drm_connector *connector,
6229                                      struct drm_crtc *crtc)
6230 {
6231         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6232         uint8_t *eld = connector->eld;
6233         uint32_t eldv;
6234         uint32_t i;
6235         int len;
6236         int hdmiw_hdmiedid;
6237         int aud_config;
6238         int aud_cntl_st;
6239         int aud_cntrl_st2;
6240         int pipe = to_intel_crtc(crtc)->pipe;
6241
6242         if (HAS_PCH_IBX(connector->dev)) {
6243                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6244                 aud_config = IBX_AUD_CFG(pipe);
6245                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6246                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6247         } else {
6248                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6249                 aud_config = CPT_AUD_CFG(pipe);
6250                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6251                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6252         }
6253
6254         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6255
6256         i = I915_READ(aud_cntl_st);
6257         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6258         if (!i) {
6259                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6260                 /* operate blindly on all ports */
6261                 eldv = IBX_ELD_VALIDB;
6262                 eldv |= IBX_ELD_VALIDB << 4;
6263                 eldv |= IBX_ELD_VALIDB << 8;
6264         } else {
6265                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6266                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6267         }
6268
6269         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6270                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6271                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6272                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6273         } else
6274                 I915_WRITE(aud_config, 0);
6275
6276         if (intel_eld_uptodate(connector,
6277                                aud_cntrl_st2, eldv,
6278                                aud_cntl_st, IBX_ELD_ADDRESS,
6279                                hdmiw_hdmiedid))
6280                 return;
6281
6282         i = I915_READ(aud_cntrl_st2);
6283         i &= ~eldv;
6284         I915_WRITE(aud_cntrl_st2, i);
6285
6286         if (!eld[0])
6287                 return;
6288
6289         i = I915_READ(aud_cntl_st);
6290         i &= ~IBX_ELD_ADDRESS;
6291         I915_WRITE(aud_cntl_st, i);
6292
6293         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6294         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6295         for (i = 0; i < len; i++)
6296                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6297
6298         i = I915_READ(aud_cntrl_st2);
6299         i |= eldv;
6300         I915_WRITE(aud_cntrl_st2, i);
6301 }
6302
6303 void intel_write_eld(struct drm_encoder *encoder,
6304                      struct drm_display_mode *mode)
6305 {
6306         struct drm_crtc *crtc = encoder->crtc;
6307         struct drm_connector *connector;
6308         struct drm_device *dev = encoder->dev;
6309         struct drm_i915_private *dev_priv = dev->dev_private;
6310
6311         connector = drm_select_eld(encoder, mode);
6312         if (!connector)
6313                 return;
6314
6315         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6316                          connector->base.id,
6317                          drm_get_connector_name(connector),
6318                          connector->encoder->base.id,
6319                          drm_get_encoder_name(connector->encoder));
6320
6321         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6322
6323         if (dev_priv->display.write_eld)
6324                 dev_priv->display.write_eld(connector, crtc);
6325 }
6326
6327 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6328 void intel_crtc_load_lut(struct drm_crtc *crtc)
6329 {
6330         struct drm_device *dev = crtc->dev;
6331         struct drm_i915_private *dev_priv = dev->dev_private;
6332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6333         enum pipe pipe = intel_crtc->pipe;
6334         int palreg = PALETTE(pipe);
6335         int i;
6336         bool reenable_ips = false;
6337
6338         /* The clocks have to be on to load the palette. */
6339         if (!crtc->enabled || !intel_crtc->active)
6340                 return;
6341
6342         if (!HAS_PCH_SPLIT(dev_priv->dev))
6343                 assert_pll_enabled(dev_priv, pipe);
6344
6345         /* use legacy palette for Ironlake */
6346         if (HAS_PCH_SPLIT(dev))
6347                 palreg = LGC_PALETTE(pipe);
6348
6349         /* Workaround : Do not read or write the pipe palette/gamma data while
6350          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6351          */
6352         if (intel_crtc->config.ips_enabled &&
6353             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6354              GAMMA_MODE_MODE_SPLIT)) {
6355                 hsw_disable_ips(intel_crtc);
6356                 reenable_ips = true;
6357         }
6358
6359         for (i = 0; i < 256; i++) {
6360                 I915_WRITE(palreg + 4 * i,
6361                            (intel_crtc->lut_r[i] << 16) |
6362                            (intel_crtc->lut_g[i] << 8) |
6363                            intel_crtc->lut_b[i]);
6364         }
6365
6366         if (reenable_ips)
6367                 hsw_enable_ips(intel_crtc);
6368 }
6369
6370 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6371 {
6372         struct drm_device *dev = crtc->dev;
6373         struct drm_i915_private *dev_priv = dev->dev_private;
6374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375         bool visible = base != 0;
6376         u32 cntl;
6377
6378         if (intel_crtc->cursor_visible == visible)
6379                 return;
6380
6381         cntl = I915_READ(_CURACNTR);
6382         if (visible) {
6383                 /* On these chipsets we can only modify the base whilst
6384                  * the cursor is disabled.
6385                  */
6386                 I915_WRITE(_CURABASE, base);
6387
6388                 cntl &= ~(CURSOR_FORMAT_MASK);
6389                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6390                 cntl |= CURSOR_ENABLE |
6391                         CURSOR_GAMMA_ENABLE |
6392                         CURSOR_FORMAT_ARGB;
6393         } else
6394                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6395         I915_WRITE(_CURACNTR, cntl);
6396
6397         intel_crtc->cursor_visible = visible;
6398 }
6399
6400 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6401 {
6402         struct drm_device *dev = crtc->dev;
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405         int pipe = intel_crtc->pipe;
6406         bool visible = base != 0;
6407
6408         if (intel_crtc->cursor_visible != visible) {
6409                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6410                 if (base) {
6411                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6412                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6413                         cntl |= pipe << 28; /* Connect to correct pipe */
6414                 } else {
6415                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6416                         cntl |= CURSOR_MODE_DISABLE;
6417                 }
6418                 I915_WRITE(CURCNTR(pipe), cntl);
6419
6420                 intel_crtc->cursor_visible = visible;
6421         }
6422         /* and commit changes on next vblank */
6423         I915_WRITE(CURBASE(pipe), base);
6424 }
6425
6426 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6427 {
6428         struct drm_device *dev = crtc->dev;
6429         struct drm_i915_private *dev_priv = dev->dev_private;
6430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6431         int pipe = intel_crtc->pipe;
6432         bool visible = base != 0;
6433
6434         if (intel_crtc->cursor_visible != visible) {
6435                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6436                 if (base) {
6437                         cntl &= ~CURSOR_MODE;
6438                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6439                 } else {
6440                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6441                         cntl |= CURSOR_MODE_DISABLE;
6442                 }
6443                 if (IS_HASWELL(dev))
6444                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6445                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6446
6447                 intel_crtc->cursor_visible = visible;
6448         }
6449         /* and commit changes on next vblank */
6450         I915_WRITE(CURBASE_IVB(pipe), base);
6451 }
6452
6453 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6454 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6455                                      bool on)
6456 {
6457         struct drm_device *dev = crtc->dev;
6458         struct drm_i915_private *dev_priv = dev->dev_private;
6459         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6460         int pipe = intel_crtc->pipe;
6461         int x = intel_crtc->cursor_x;
6462         int y = intel_crtc->cursor_y;
6463         u32 base, pos;
6464         bool visible;
6465
6466         pos = 0;
6467
6468         if (on && crtc->enabled && crtc->fb) {
6469                 base = intel_crtc->cursor_addr;
6470                 if (x > (int) crtc->fb->width)
6471                         base = 0;
6472
6473                 if (y > (int) crtc->fb->height)
6474                         base = 0;
6475         } else
6476                 base = 0;
6477
6478         if (x < 0) {
6479                 if (x + intel_crtc->cursor_width < 0)
6480                         base = 0;
6481
6482                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6483                 x = -x;
6484         }
6485         pos |= x << CURSOR_X_SHIFT;
6486
6487         if (y < 0) {
6488                 if (y + intel_crtc->cursor_height < 0)
6489                         base = 0;
6490
6491                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6492                 y = -y;
6493         }
6494         pos |= y << CURSOR_Y_SHIFT;
6495
6496         visible = base != 0;
6497         if (!visible && !intel_crtc->cursor_visible)
6498                 return;
6499
6500         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6501                 I915_WRITE(CURPOS_IVB(pipe), pos);
6502                 ivb_update_cursor(crtc, base);
6503         } else {
6504                 I915_WRITE(CURPOS(pipe), pos);
6505                 if (IS_845G(dev) || IS_I865G(dev))
6506                         i845_update_cursor(crtc, base);
6507                 else
6508                         i9xx_update_cursor(crtc, base);
6509         }
6510 }
6511
6512 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6513                                  struct drm_file *file,
6514                                  uint32_t handle,
6515                                  uint32_t width, uint32_t height)
6516 {
6517         struct drm_device *dev = crtc->dev;
6518         struct drm_i915_private *dev_priv = dev->dev_private;
6519         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6520         struct drm_i915_gem_object *obj;
6521         uint32_t addr;
6522         int ret;
6523
6524         /* if we want to turn off the cursor ignore width and height */
6525         if (!handle) {
6526                 DRM_DEBUG_KMS("cursor off\n");
6527                 addr = 0;
6528                 obj = NULL;
6529                 mutex_lock(&dev->struct_mutex);
6530                 goto finish;
6531         }
6532
6533         /* Currently we only support 64x64 cursors */
6534         if (width != 64 || height != 64) {
6535                 DRM_ERROR("we currently only support 64x64 cursors\n");
6536                 return -EINVAL;
6537         }
6538
6539         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6540         if (&obj->base == NULL)
6541                 return -ENOENT;
6542
6543         if (obj->base.size < width * height * 4) {
6544                 DRM_ERROR("buffer is to small\n");
6545                 ret = -ENOMEM;
6546                 goto fail;
6547         }
6548
6549         /* we only need to pin inside GTT if cursor is non-phy */
6550         mutex_lock(&dev->struct_mutex);
6551         if (!dev_priv->info->cursor_needs_physical) {
6552                 unsigned alignment;
6553
6554                 if (obj->tiling_mode) {
6555                         DRM_ERROR("cursor cannot be tiled\n");
6556                         ret = -EINVAL;
6557                         goto fail_locked;
6558                 }
6559
6560                 /* Note that the w/a also requires 2 PTE of padding following
6561                  * the bo. We currently fill all unused PTE with the shadow
6562                  * page and so we should always have valid PTE following the
6563                  * cursor preventing the VT-d warning.
6564                  */
6565                 alignment = 0;
6566                 if (need_vtd_wa(dev))
6567                         alignment = 64*1024;
6568
6569                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6570                 if (ret) {
6571                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6572                         goto fail_locked;
6573                 }
6574
6575                 ret = i915_gem_object_put_fence(obj);
6576                 if (ret) {
6577                         DRM_ERROR("failed to release fence for cursor");
6578                         goto fail_unpin;
6579                 }
6580
6581                 addr = obj->gtt_offset;
6582         } else {
6583                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6584                 ret = i915_gem_attach_phys_object(dev, obj,
6585                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6586                                                   align);
6587                 if (ret) {
6588                         DRM_ERROR("failed to attach phys object\n");
6589                         goto fail_locked;
6590                 }
6591                 addr = obj->phys_obj->handle->busaddr;
6592         }
6593
6594         if (IS_GEN2(dev))
6595                 I915_WRITE(CURSIZE, (height << 12) | width);
6596
6597  finish:
6598         if (intel_crtc->cursor_bo) {
6599                 if (dev_priv->info->cursor_needs_physical) {
6600                         if (intel_crtc->cursor_bo != obj)
6601                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6602                 } else
6603                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6604                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6605         }
6606
6607         mutex_unlock(&dev->struct_mutex);
6608
6609         intel_crtc->cursor_addr = addr;
6610         intel_crtc->cursor_bo = obj;
6611         intel_crtc->cursor_width = width;
6612         intel_crtc->cursor_height = height;
6613
6614         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6615
6616         return 0;
6617 fail_unpin:
6618         i915_gem_object_unpin(obj);
6619 fail_locked:
6620         mutex_unlock(&dev->struct_mutex);
6621 fail:
6622         drm_gem_object_unreference_unlocked(&obj->base);
6623         return ret;
6624 }
6625
6626 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6627 {
6628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6629
6630         intel_crtc->cursor_x = x;
6631         intel_crtc->cursor_y = y;
6632
6633         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6634
6635         return 0;
6636 }
6637
6638 /** Sets the color ramps on behalf of RandR */
6639 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6640                                  u16 blue, int regno)
6641 {
6642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643
6644         intel_crtc->lut_r[regno] = red >> 8;
6645         intel_crtc->lut_g[regno] = green >> 8;
6646         intel_crtc->lut_b[regno] = blue >> 8;
6647 }
6648
6649 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6650                              u16 *blue, int regno)
6651 {
6652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6653
6654         *red = intel_crtc->lut_r[regno] << 8;
6655         *green = intel_crtc->lut_g[regno] << 8;
6656         *blue = intel_crtc->lut_b[regno] << 8;
6657 }
6658
6659 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6660                                  u16 *blue, uint32_t start, uint32_t size)
6661 {
6662         int end = (start + size > 256) ? 256 : start + size, i;
6663         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6664
6665         for (i = start; i < end; i++) {
6666                 intel_crtc->lut_r[i] = red[i] >> 8;
6667                 intel_crtc->lut_g[i] = green[i] >> 8;
6668                 intel_crtc->lut_b[i] = blue[i] >> 8;
6669         }
6670
6671         intel_crtc_load_lut(crtc);
6672 }
6673
6674 /* VESA 640x480x72Hz mode to set on the pipe */
6675 static struct drm_display_mode load_detect_mode = {
6676         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6677                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6678 };
6679
6680 static struct drm_framebuffer *
6681 intel_framebuffer_create(struct drm_device *dev,
6682                          struct drm_mode_fb_cmd2 *mode_cmd,
6683                          struct drm_i915_gem_object *obj)
6684 {
6685         struct intel_framebuffer *intel_fb;
6686         int ret;
6687
6688         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6689         if (!intel_fb) {
6690                 drm_gem_object_unreference_unlocked(&obj->base);
6691                 return ERR_PTR(-ENOMEM);
6692         }
6693
6694         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6695         if (ret) {
6696                 drm_gem_object_unreference_unlocked(&obj->base);
6697                 kfree(intel_fb);
6698                 return ERR_PTR(ret);
6699         }
6700
6701         return &intel_fb->base;
6702 }
6703
6704 static u32
6705 intel_framebuffer_pitch_for_width(int width, int bpp)
6706 {
6707         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6708         return ALIGN(pitch, 64);
6709 }
6710
6711 static u32
6712 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6713 {
6714         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6715         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6716 }
6717
6718 static struct drm_framebuffer *
6719 intel_framebuffer_create_for_mode(struct drm_device *dev,
6720                                   struct drm_display_mode *mode,
6721                                   int depth, int bpp)
6722 {
6723         struct drm_i915_gem_object *obj;
6724         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6725
6726         obj = i915_gem_alloc_object(dev,
6727                                     intel_framebuffer_size_for_mode(mode, bpp));
6728         if (obj == NULL)
6729                 return ERR_PTR(-ENOMEM);
6730
6731         mode_cmd.width = mode->hdisplay;
6732         mode_cmd.height = mode->vdisplay;
6733         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6734                                                                 bpp);
6735         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6736
6737         return intel_framebuffer_create(dev, &mode_cmd, obj);
6738 }
6739
6740 static struct drm_framebuffer *
6741 mode_fits_in_fbdev(struct drm_device *dev,
6742                    struct drm_display_mode *mode)
6743 {
6744         struct drm_i915_private *dev_priv = dev->dev_private;
6745         struct drm_i915_gem_object *obj;
6746         struct drm_framebuffer *fb;
6747
6748         if (dev_priv->fbdev == NULL)
6749                 return NULL;
6750
6751         obj = dev_priv->fbdev->ifb.obj;
6752         if (obj == NULL)
6753                 return NULL;
6754
6755         fb = &dev_priv->fbdev->ifb.base;
6756         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6757                                                                fb->bits_per_pixel))
6758                 return NULL;
6759
6760         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6761                 return NULL;
6762
6763         return fb;
6764 }
6765
6766 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6767                                 struct drm_display_mode *mode,
6768                                 struct intel_load_detect_pipe *old)
6769 {
6770         struct intel_crtc *intel_crtc;
6771         struct intel_encoder *intel_encoder =
6772                 intel_attached_encoder(connector);
6773         struct drm_crtc *possible_crtc;
6774         struct drm_encoder *encoder = &intel_encoder->base;
6775         struct drm_crtc *crtc = NULL;
6776         struct drm_device *dev = encoder->dev;
6777         struct drm_framebuffer *fb;
6778         int i = -1;
6779
6780         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6781                       connector->base.id, drm_get_connector_name(connector),
6782                       encoder->base.id, drm_get_encoder_name(encoder));
6783
6784         /*
6785          * Algorithm gets a little messy:
6786          *
6787          *   - if the connector already has an assigned crtc, use it (but make
6788          *     sure it's on first)
6789          *
6790          *   - try to find the first unused crtc that can drive this connector,
6791          *     and use that if we find one
6792          */
6793
6794         /* See if we already have a CRTC for this connector */
6795         if (encoder->crtc) {
6796                 crtc = encoder->crtc;
6797
6798                 mutex_lock(&crtc->mutex);
6799
6800                 old->dpms_mode = connector->dpms;
6801                 old->load_detect_temp = false;
6802
6803                 /* Make sure the crtc and connector are running */
6804                 if (connector->dpms != DRM_MODE_DPMS_ON)
6805                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6806
6807                 return true;
6808         }
6809
6810         /* Find an unused one (if possible) */
6811         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6812                 i++;
6813                 if (!(encoder->possible_crtcs & (1 << i)))
6814                         continue;
6815                 if (!possible_crtc->enabled) {
6816                         crtc = possible_crtc;
6817                         break;
6818                 }
6819         }
6820
6821         /*
6822          * If we didn't find an unused CRTC, don't use any.
6823          */
6824         if (!crtc) {
6825                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6826                 return false;
6827         }
6828
6829         mutex_lock(&crtc->mutex);
6830         intel_encoder->new_crtc = to_intel_crtc(crtc);
6831         to_intel_connector(connector)->new_encoder = intel_encoder;
6832
6833         intel_crtc = to_intel_crtc(crtc);
6834         old->dpms_mode = connector->dpms;
6835         old->load_detect_temp = true;
6836         old->release_fb = NULL;
6837
6838         if (!mode)
6839                 mode = &load_detect_mode;
6840
6841         /* We need a framebuffer large enough to accommodate all accesses
6842          * that the plane may generate whilst we perform load detection.
6843          * We can not rely on the fbcon either being present (we get called
6844          * during its initialisation to detect all boot displays, or it may
6845          * not even exist) or that it is large enough to satisfy the
6846          * requested mode.
6847          */
6848         fb = mode_fits_in_fbdev(dev, mode);
6849         if (fb == NULL) {
6850                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6851                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6852                 old->release_fb = fb;
6853         } else
6854                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6855         if (IS_ERR(fb)) {
6856                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6857                 mutex_unlock(&crtc->mutex);
6858                 return false;
6859         }
6860
6861         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6862                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6863                 if (old->release_fb)
6864                         old->release_fb->funcs->destroy(old->release_fb);
6865                 mutex_unlock(&crtc->mutex);
6866                 return false;
6867         }
6868
6869         /* let the connector get through one full cycle before testing */
6870         intel_wait_for_vblank(dev, intel_crtc->pipe);
6871         return true;
6872 }
6873
6874 void intel_release_load_detect_pipe(struct drm_connector *connector,
6875                                     struct intel_load_detect_pipe *old)
6876 {
6877         struct intel_encoder *intel_encoder =
6878                 intel_attached_encoder(connector);
6879         struct drm_encoder *encoder = &intel_encoder->base;
6880         struct drm_crtc *crtc = encoder->crtc;
6881
6882         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6883                       connector->base.id, drm_get_connector_name(connector),
6884                       encoder->base.id, drm_get_encoder_name(encoder));
6885
6886         if (old->load_detect_temp) {
6887                 to_intel_connector(connector)->new_encoder = NULL;
6888                 intel_encoder->new_crtc = NULL;
6889                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6890
6891                 if (old->release_fb) {
6892                         drm_framebuffer_unregister_private(old->release_fb);
6893                         drm_framebuffer_unreference(old->release_fb);
6894                 }
6895
6896                 mutex_unlock(&crtc->mutex);
6897                 return;
6898         }
6899
6900         /* Switch crtc and encoder back off if necessary */
6901         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6902                 connector->funcs->dpms(connector, old->dpms_mode);
6903
6904         mutex_unlock(&crtc->mutex);
6905 }
6906
6907 /* Returns the clock of the currently programmed mode of the given pipe. */
6908 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6909 {
6910         struct drm_i915_private *dev_priv = dev->dev_private;
6911         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6912         int pipe = intel_crtc->pipe;
6913         u32 dpll = I915_READ(DPLL(pipe));
6914         u32 fp;
6915         intel_clock_t clock;
6916
6917         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6918                 fp = I915_READ(FP0(pipe));
6919         else
6920                 fp = I915_READ(FP1(pipe));
6921
6922         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6923         if (IS_PINEVIEW(dev)) {
6924                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6925                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6926         } else {
6927                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6928                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6929         }
6930
6931         if (!IS_GEN2(dev)) {
6932                 if (IS_PINEVIEW(dev))
6933                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6934                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6935                 else
6936                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6937                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6938
6939                 switch (dpll & DPLL_MODE_MASK) {
6940                 case DPLLB_MODE_DAC_SERIAL:
6941                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6942                                 5 : 10;
6943                         break;
6944                 case DPLLB_MODE_LVDS:
6945                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6946                                 7 : 14;
6947                         break;
6948                 default:
6949                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6950                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6951                         return 0;
6952                 }
6953
6954                 if (IS_PINEVIEW(dev))
6955                         pineview_clock(96000, &clock);
6956                 else
6957                         i9xx_clock(96000, &clock);
6958         } else {
6959                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6960
6961                 if (is_lvds) {
6962                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6963                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6964                         clock.p2 = 14;
6965
6966                         if ((dpll & PLL_REF_INPUT_MASK) ==
6967                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6968                                 /* XXX: might not be 66MHz */
6969                                 i9xx_clock(66000, &clock);
6970                         } else
6971                                 i9xx_clock(48000, &clock);
6972                 } else {
6973                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6974                                 clock.p1 = 2;
6975                         else {
6976                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6977                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6978                         }
6979                         if (dpll & PLL_P2_DIVIDE_BY_4)
6980                                 clock.p2 = 4;
6981                         else
6982                                 clock.p2 = 2;
6983
6984                         i9xx_clock(48000, &clock);
6985                 }
6986         }
6987
6988         /* XXX: It would be nice to validate the clocks, but we can't reuse
6989          * i830PllIsValid() because it relies on the xf86_config connector
6990          * configuration being accurate, which it isn't necessarily.
6991          */
6992
6993         return clock.dot;
6994 }
6995
6996 /** Returns the currently programmed mode of the given pipe. */
6997 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6998                                              struct drm_crtc *crtc)
6999 {
7000         struct drm_i915_private *dev_priv = dev->dev_private;
7001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7002         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7003         struct drm_display_mode *mode;
7004         int htot = I915_READ(HTOTAL(cpu_transcoder));
7005         int hsync = I915_READ(HSYNC(cpu_transcoder));
7006         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7007         int vsync = I915_READ(VSYNC(cpu_transcoder));
7008
7009         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7010         if (!mode)
7011                 return NULL;
7012
7013         mode->clock = intel_crtc_clock_get(dev, crtc);
7014         mode->hdisplay = (htot & 0xffff) + 1;
7015         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7016         mode->hsync_start = (hsync & 0xffff) + 1;
7017         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7018         mode->vdisplay = (vtot & 0xffff) + 1;
7019         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7020         mode->vsync_start = (vsync & 0xffff) + 1;
7021         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7022
7023         drm_mode_set_name(mode);
7024
7025         return mode;
7026 }
7027
7028 static void intel_increase_pllclock(struct drm_crtc *crtc)
7029 {
7030         struct drm_device *dev = crtc->dev;
7031         drm_i915_private_t *dev_priv = dev->dev_private;
7032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7033         int pipe = intel_crtc->pipe;
7034         int dpll_reg = DPLL(pipe);
7035         int dpll;
7036
7037         if (HAS_PCH_SPLIT(dev))
7038                 return;
7039
7040         if (!dev_priv->lvds_downclock_avail)
7041                 return;
7042
7043         dpll = I915_READ(dpll_reg);
7044         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7045                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7046
7047                 assert_panel_unlocked(dev_priv, pipe);
7048
7049                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7050                 I915_WRITE(dpll_reg, dpll);
7051                 intel_wait_for_vblank(dev, pipe);
7052
7053                 dpll = I915_READ(dpll_reg);
7054                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7055                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7056         }
7057 }
7058
7059 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7060 {
7061         struct drm_device *dev = crtc->dev;
7062         drm_i915_private_t *dev_priv = dev->dev_private;
7063         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7064
7065         if (HAS_PCH_SPLIT(dev))
7066                 return;
7067
7068         if (!dev_priv->lvds_downclock_avail)
7069                 return;
7070
7071         /*
7072          * Since this is called by a timer, we should never get here in
7073          * the manual case.
7074          */
7075         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7076                 int pipe = intel_crtc->pipe;
7077                 int dpll_reg = DPLL(pipe);
7078                 int dpll;
7079
7080                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7081
7082                 assert_panel_unlocked(dev_priv, pipe);
7083
7084                 dpll = I915_READ(dpll_reg);
7085                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7086                 I915_WRITE(dpll_reg, dpll);
7087                 intel_wait_for_vblank(dev, pipe);
7088                 dpll = I915_READ(dpll_reg);
7089                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7090                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7091         }
7092
7093 }
7094
7095 void intel_mark_busy(struct drm_device *dev)
7096 {
7097         i915_update_gfx_val(dev->dev_private);
7098 }
7099
7100 void intel_mark_idle(struct drm_device *dev)
7101 {
7102         struct drm_crtc *crtc;
7103
7104         if (!i915_powersave)
7105                 return;
7106
7107         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7108                 if (!crtc->fb)
7109                         continue;
7110
7111                 intel_decrease_pllclock(crtc);
7112         }
7113 }
7114
7115 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7116                         struct intel_ring_buffer *ring)
7117 {
7118         struct drm_device *dev = obj->base.dev;
7119         struct drm_crtc *crtc;
7120
7121         if (!i915_powersave)
7122                 return;
7123
7124         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7125                 if (!crtc->fb)
7126                         continue;
7127
7128                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7129                         continue;
7130
7131                 intel_increase_pllclock(crtc);
7132                 if (ring && intel_fbc_enabled(dev))
7133                         ring->fbc_dirty = true;
7134         }
7135 }
7136
7137 static void intel_crtc_destroy(struct drm_crtc *crtc)
7138 {
7139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7140         struct drm_device *dev = crtc->dev;
7141         struct intel_unpin_work *work;
7142         unsigned long flags;
7143
7144         spin_lock_irqsave(&dev->event_lock, flags);
7145         work = intel_crtc->unpin_work;
7146         intel_crtc->unpin_work = NULL;
7147         spin_unlock_irqrestore(&dev->event_lock, flags);
7148
7149         if (work) {
7150                 cancel_work_sync(&work->work);
7151                 kfree(work);
7152         }
7153
7154         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7155
7156         drm_crtc_cleanup(crtc);
7157
7158         kfree(intel_crtc);
7159 }
7160
7161 static void intel_unpin_work_fn(struct work_struct *__work)
7162 {
7163         struct intel_unpin_work *work =
7164                 container_of(__work, struct intel_unpin_work, work);
7165         struct drm_device *dev = work->crtc->dev;
7166
7167         mutex_lock(&dev->struct_mutex);
7168         intel_unpin_fb_obj(work->old_fb_obj);
7169         drm_gem_object_unreference(&work->pending_flip_obj->base);
7170         drm_gem_object_unreference(&work->old_fb_obj->base);
7171
7172         intel_update_fbc(dev);
7173         mutex_unlock(&dev->struct_mutex);
7174
7175         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7176         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7177
7178         kfree(work);
7179 }
7180
7181 static void do_intel_finish_page_flip(struct drm_device *dev,
7182                                       struct drm_crtc *crtc)
7183 {
7184         drm_i915_private_t *dev_priv = dev->dev_private;
7185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7186         struct intel_unpin_work *work;
7187         unsigned long flags;
7188
7189         /* Ignore early vblank irqs */
7190         if (intel_crtc == NULL)
7191                 return;
7192
7193         spin_lock_irqsave(&dev->event_lock, flags);
7194         work = intel_crtc->unpin_work;
7195
7196         /* Ensure we don't miss a work->pending update ... */
7197         smp_rmb();
7198
7199         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7200                 spin_unlock_irqrestore(&dev->event_lock, flags);
7201                 return;
7202         }
7203
7204         /* and that the unpin work is consistent wrt ->pending. */
7205         smp_rmb();
7206
7207         intel_crtc->unpin_work = NULL;
7208
7209         if (work->event)
7210                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7211
7212         drm_vblank_put(dev, intel_crtc->pipe);
7213
7214         spin_unlock_irqrestore(&dev->event_lock, flags);
7215
7216         wake_up_all(&dev_priv->pending_flip_queue);
7217
7218         queue_work(dev_priv->wq, &work->work);
7219
7220         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7221 }
7222
7223 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7224 {
7225         drm_i915_private_t *dev_priv = dev->dev_private;
7226         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7227
7228         do_intel_finish_page_flip(dev, crtc);
7229 }
7230
7231 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7232 {
7233         drm_i915_private_t *dev_priv = dev->dev_private;
7234         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7235
7236         do_intel_finish_page_flip(dev, crtc);
7237 }
7238
7239 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7240 {
7241         drm_i915_private_t *dev_priv = dev->dev_private;
7242         struct intel_crtc *intel_crtc =
7243                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7244         unsigned long flags;
7245
7246         /* NB: An MMIO update of the plane base pointer will also
7247          * generate a page-flip completion irq, i.e. every modeset
7248          * is also accompanied by a spurious intel_prepare_page_flip().
7249          */
7250         spin_lock_irqsave(&dev->event_lock, flags);
7251         if (intel_crtc->unpin_work)
7252                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7253         spin_unlock_irqrestore(&dev->event_lock, flags);
7254 }
7255
7256 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7257 {
7258         /* Ensure that the work item is consistent when activating it ... */
7259         smp_wmb();
7260         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7261         /* and that it is marked active as soon as the irq could fire. */
7262         smp_wmb();
7263 }
7264
7265 static int intel_gen2_queue_flip(struct drm_device *dev,
7266                                  struct drm_crtc *crtc,
7267                                  struct drm_framebuffer *fb,
7268                                  struct drm_i915_gem_object *obj)
7269 {
7270         struct drm_i915_private *dev_priv = dev->dev_private;
7271         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7272         u32 flip_mask;
7273         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7274         int ret;
7275
7276         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7277         if (ret)
7278                 goto err;
7279
7280         ret = intel_ring_begin(ring, 6);
7281         if (ret)
7282                 goto err_unpin;
7283
7284         /* Can't queue multiple flips, so wait for the previous
7285          * one to finish before executing the next.
7286          */
7287         if (intel_crtc->plane)
7288                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7289         else
7290                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7291         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7292         intel_ring_emit(ring, MI_NOOP);
7293         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7294                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7295         intel_ring_emit(ring, fb->pitches[0]);
7296         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7297         intel_ring_emit(ring, 0); /* aux display base address, unused */
7298
7299         intel_mark_page_flip_active(intel_crtc);
7300         intel_ring_advance(ring);
7301         return 0;
7302
7303 err_unpin:
7304         intel_unpin_fb_obj(obj);
7305 err:
7306         return ret;
7307 }
7308
7309 static int intel_gen3_queue_flip(struct drm_device *dev,
7310                                  struct drm_crtc *crtc,
7311                                  struct drm_framebuffer *fb,
7312                                  struct drm_i915_gem_object *obj)
7313 {
7314         struct drm_i915_private *dev_priv = dev->dev_private;
7315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7316         u32 flip_mask;
7317         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7318         int ret;
7319
7320         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7321         if (ret)
7322                 goto err;
7323
7324         ret = intel_ring_begin(ring, 6);
7325         if (ret)
7326                 goto err_unpin;
7327
7328         if (intel_crtc->plane)
7329                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7330         else
7331                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7332         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7333         intel_ring_emit(ring, MI_NOOP);
7334         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7335                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7336         intel_ring_emit(ring, fb->pitches[0]);
7337         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7338         intel_ring_emit(ring, MI_NOOP);
7339
7340         intel_mark_page_flip_active(intel_crtc);
7341         intel_ring_advance(ring);
7342         return 0;
7343
7344 err_unpin:
7345         intel_unpin_fb_obj(obj);
7346 err:
7347         return ret;
7348 }
7349
7350 static int intel_gen4_queue_flip(struct drm_device *dev,
7351                                  struct drm_crtc *crtc,
7352                                  struct drm_framebuffer *fb,
7353                                  struct drm_i915_gem_object *obj)
7354 {
7355         struct drm_i915_private *dev_priv = dev->dev_private;
7356         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7357         uint32_t pf, pipesrc;
7358         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7359         int ret;
7360
7361         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7362         if (ret)
7363                 goto err;
7364
7365         ret = intel_ring_begin(ring, 4);
7366         if (ret)
7367                 goto err_unpin;
7368
7369         /* i965+ uses the linear or tiled offsets from the
7370          * Display Registers (which do not change across a page-flip)
7371          * so we need only reprogram the base address.
7372          */
7373         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7374                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7375         intel_ring_emit(ring, fb->pitches[0]);
7376         intel_ring_emit(ring,
7377                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7378                         obj->tiling_mode);
7379
7380         /* XXX Enabling the panel-fitter across page-flip is so far
7381          * untested on non-native modes, so ignore it for now.
7382          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7383          */
7384         pf = 0;
7385         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7386         intel_ring_emit(ring, pf | pipesrc);
7387
7388         intel_mark_page_flip_active(intel_crtc);
7389         intel_ring_advance(ring);
7390         return 0;
7391
7392 err_unpin:
7393         intel_unpin_fb_obj(obj);
7394 err:
7395         return ret;
7396 }
7397
7398 static int intel_gen6_queue_flip(struct drm_device *dev,
7399                                  struct drm_crtc *crtc,
7400                                  struct drm_framebuffer *fb,
7401                                  struct drm_i915_gem_object *obj)
7402 {
7403         struct drm_i915_private *dev_priv = dev->dev_private;
7404         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7405         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7406         uint32_t pf, pipesrc;
7407         int ret;
7408
7409         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7410         if (ret)
7411                 goto err;
7412
7413         ret = intel_ring_begin(ring, 4);
7414         if (ret)
7415                 goto err_unpin;
7416
7417         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7418                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7419         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7420         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7421
7422         /* Contrary to the suggestions in the documentation,
7423          * "Enable Panel Fitter" does not seem to be required when page
7424          * flipping with a non-native mode, and worse causes a normal
7425          * modeset to fail.
7426          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7427          */
7428         pf = 0;
7429         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7430         intel_ring_emit(ring, pf | pipesrc);
7431
7432         intel_mark_page_flip_active(intel_crtc);
7433         intel_ring_advance(ring);
7434         return 0;
7435
7436 err_unpin:
7437         intel_unpin_fb_obj(obj);
7438 err:
7439         return ret;
7440 }
7441
7442 /*
7443  * On gen7 we currently use the blit ring because (in early silicon at least)
7444  * the render ring doesn't give us interrpts for page flip completion, which
7445  * means clients will hang after the first flip is queued.  Fortunately the
7446  * blit ring generates interrupts properly, so use it instead.
7447  */
7448 static int intel_gen7_queue_flip(struct drm_device *dev,
7449                                  struct drm_crtc *crtc,
7450                                  struct drm_framebuffer *fb,
7451                                  struct drm_i915_gem_object *obj)
7452 {
7453         struct drm_i915_private *dev_priv = dev->dev_private;
7454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7455         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7456         uint32_t plane_bit = 0;
7457         int ret;
7458
7459         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7460         if (ret)
7461                 goto err;
7462
7463         switch(intel_crtc->plane) {
7464         case PLANE_A:
7465                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7466                 break;
7467         case PLANE_B:
7468                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7469                 break;
7470         case PLANE_C:
7471                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7472                 break;
7473         default:
7474                 WARN_ONCE(1, "unknown plane in flip command\n");
7475                 ret = -ENODEV;
7476                 goto err_unpin;
7477         }
7478
7479         ret = intel_ring_begin(ring, 4);
7480         if (ret)
7481                 goto err_unpin;
7482
7483         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7484         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7485         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7486         intel_ring_emit(ring, (MI_NOOP));
7487
7488         intel_mark_page_flip_active(intel_crtc);
7489         intel_ring_advance(ring);
7490         return 0;
7491
7492 err_unpin:
7493         intel_unpin_fb_obj(obj);
7494 err:
7495         return ret;
7496 }
7497
7498 static int intel_default_queue_flip(struct drm_device *dev,
7499                                     struct drm_crtc *crtc,
7500                                     struct drm_framebuffer *fb,
7501                                     struct drm_i915_gem_object *obj)
7502 {
7503         return -ENODEV;
7504 }
7505
7506 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7507                                 struct drm_framebuffer *fb,
7508                                 struct drm_pending_vblank_event *event)
7509 {
7510         struct drm_device *dev = crtc->dev;
7511         struct drm_i915_private *dev_priv = dev->dev_private;
7512         struct drm_framebuffer *old_fb = crtc->fb;
7513         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7514         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7515         struct intel_unpin_work *work;
7516         unsigned long flags;
7517         int ret;
7518
7519         /* Can't change pixel format via MI display flips. */
7520         if (fb->pixel_format != crtc->fb->pixel_format)
7521                 return -EINVAL;
7522
7523         /*
7524          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7525          * Note that pitch changes could also affect these register.
7526          */
7527         if (INTEL_INFO(dev)->gen > 3 &&
7528             (fb->offsets[0] != crtc->fb->offsets[0] ||
7529              fb->pitches[0] != crtc->fb->pitches[0]))
7530                 return -EINVAL;
7531
7532         work = kzalloc(sizeof *work, GFP_KERNEL);
7533         if (work == NULL)
7534                 return -ENOMEM;
7535
7536         work->event = event;
7537         work->crtc = crtc;
7538         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7539         INIT_WORK(&work->work, intel_unpin_work_fn);
7540
7541         ret = drm_vblank_get(dev, intel_crtc->pipe);
7542         if (ret)
7543                 goto free_work;
7544
7545         /* We borrow the event spin lock for protecting unpin_work */
7546         spin_lock_irqsave(&dev->event_lock, flags);
7547         if (intel_crtc->unpin_work) {
7548                 spin_unlock_irqrestore(&dev->event_lock, flags);
7549                 kfree(work);
7550                 drm_vblank_put(dev, intel_crtc->pipe);
7551
7552                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7553                 return -EBUSY;
7554         }
7555         intel_crtc->unpin_work = work;
7556         spin_unlock_irqrestore(&dev->event_lock, flags);
7557
7558         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7559                 flush_workqueue(dev_priv->wq);
7560
7561         ret = i915_mutex_lock_interruptible(dev);
7562         if (ret)
7563                 goto cleanup;
7564
7565         /* Reference the objects for the scheduled work. */
7566         drm_gem_object_reference(&work->old_fb_obj->base);
7567         drm_gem_object_reference(&obj->base);
7568
7569         crtc->fb = fb;
7570
7571         work->pending_flip_obj = obj;
7572
7573         work->enable_stall_check = true;
7574
7575         atomic_inc(&intel_crtc->unpin_work_count);
7576         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7577
7578         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7579         if (ret)
7580                 goto cleanup_pending;
7581
7582         intel_disable_fbc(dev);
7583         intel_mark_fb_busy(obj, NULL);
7584         mutex_unlock(&dev->struct_mutex);
7585
7586         trace_i915_flip_request(intel_crtc->plane, obj);
7587
7588         return 0;
7589
7590 cleanup_pending:
7591         atomic_dec(&intel_crtc->unpin_work_count);
7592         crtc->fb = old_fb;
7593         drm_gem_object_unreference(&work->old_fb_obj->base);
7594         drm_gem_object_unreference(&obj->base);
7595         mutex_unlock(&dev->struct_mutex);
7596
7597 cleanup:
7598         spin_lock_irqsave(&dev->event_lock, flags);
7599         intel_crtc->unpin_work = NULL;
7600         spin_unlock_irqrestore(&dev->event_lock, flags);
7601
7602         drm_vblank_put(dev, intel_crtc->pipe);
7603 free_work:
7604         kfree(work);
7605
7606         return ret;
7607 }
7608
7609 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7610         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7611         .load_lut = intel_crtc_load_lut,
7612 };
7613
7614 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7615                                   struct drm_crtc *crtc)
7616 {
7617         struct drm_device *dev;
7618         struct drm_crtc *tmp;
7619         int crtc_mask = 1;
7620
7621         WARN(!crtc, "checking null crtc?\n");
7622
7623         dev = crtc->dev;
7624
7625         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7626                 if (tmp == crtc)
7627                         break;
7628                 crtc_mask <<= 1;
7629         }
7630
7631         if (encoder->possible_crtcs & crtc_mask)
7632                 return true;
7633         return false;
7634 }
7635
7636 /**
7637  * intel_modeset_update_staged_output_state
7638  *
7639  * Updates the staged output configuration state, e.g. after we've read out the
7640  * current hw state.
7641  */
7642 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7643 {
7644         struct intel_encoder *encoder;
7645         struct intel_connector *connector;
7646
7647         list_for_each_entry(connector, &dev->mode_config.connector_list,
7648                             base.head) {
7649                 connector->new_encoder =
7650                         to_intel_encoder(connector->base.encoder);
7651         }
7652
7653         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7654                             base.head) {
7655                 encoder->new_crtc =
7656                         to_intel_crtc(encoder->base.crtc);
7657         }
7658 }
7659
7660 /**
7661  * intel_modeset_commit_output_state
7662  *
7663  * This function copies the stage display pipe configuration to the real one.
7664  */
7665 static void intel_modeset_commit_output_state(struct drm_device *dev)
7666 {
7667         struct intel_encoder *encoder;
7668         struct intel_connector *connector;
7669
7670         list_for_each_entry(connector, &dev->mode_config.connector_list,
7671                             base.head) {
7672                 connector->base.encoder = &connector->new_encoder->base;
7673         }
7674
7675         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7676                             base.head) {
7677                 encoder->base.crtc = &encoder->new_crtc->base;
7678         }
7679 }
7680
7681 static void
7682 connected_sink_compute_bpp(struct intel_connector * connector,
7683                            struct intel_crtc_config *pipe_config)
7684 {
7685         int bpp = pipe_config->pipe_bpp;
7686
7687         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7688                 connector->base.base.id,
7689                 drm_get_connector_name(&connector->base));
7690
7691         /* Don't use an invalid EDID bpc value */
7692         if (connector->base.display_info.bpc &&
7693             connector->base.display_info.bpc * 3 < bpp) {
7694                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7695                               bpp, connector->base.display_info.bpc*3);
7696                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7697         }
7698
7699         /* Clamp bpp to 8 on screens without EDID 1.4 */
7700         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7701                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7702                               bpp);
7703                 pipe_config->pipe_bpp = 24;
7704         }
7705 }
7706
7707 static int
7708 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7709                           struct drm_framebuffer *fb,
7710                           struct intel_crtc_config *pipe_config)
7711 {
7712         struct drm_device *dev = crtc->base.dev;
7713         struct intel_connector *connector;
7714         int bpp;
7715
7716         switch (fb->pixel_format) {
7717         case DRM_FORMAT_C8:
7718                 bpp = 8*3; /* since we go through a colormap */
7719                 break;
7720         case DRM_FORMAT_XRGB1555:
7721         case DRM_FORMAT_ARGB1555:
7722                 /* checked in intel_framebuffer_init already */
7723                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7724                         return -EINVAL;
7725         case DRM_FORMAT_RGB565:
7726                 bpp = 6*3; /* min is 18bpp */
7727                 break;
7728         case DRM_FORMAT_XBGR8888:
7729         case DRM_FORMAT_ABGR8888:
7730                 /* checked in intel_framebuffer_init already */
7731                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7732                         return -EINVAL;
7733         case DRM_FORMAT_XRGB8888:
7734         case DRM_FORMAT_ARGB8888:
7735                 bpp = 8*3;
7736                 break;
7737         case DRM_FORMAT_XRGB2101010:
7738         case DRM_FORMAT_ARGB2101010:
7739         case DRM_FORMAT_XBGR2101010:
7740         case DRM_FORMAT_ABGR2101010:
7741                 /* checked in intel_framebuffer_init already */
7742                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7743                         return -EINVAL;
7744                 bpp = 10*3;
7745                 break;
7746         /* TODO: gen4+ supports 16 bpc floating point, too. */
7747         default:
7748                 DRM_DEBUG_KMS("unsupported depth\n");
7749                 return -EINVAL;
7750         }
7751
7752         pipe_config->pipe_bpp = bpp;
7753
7754         /* Clamp display bpp to EDID value */
7755         list_for_each_entry(connector, &dev->mode_config.connector_list,
7756                             base.head) {
7757                 if (!connector->new_encoder ||
7758                     connector->new_encoder->new_crtc != crtc)
7759                         continue;
7760
7761                 connected_sink_compute_bpp(connector, pipe_config);
7762         }
7763
7764         return bpp;
7765 }
7766
7767 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7768                                    struct intel_crtc_config *pipe_config,
7769                                    const char *context)
7770 {
7771         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7772                       context, pipe_name(crtc->pipe));
7773
7774         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7775         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7776                       pipe_config->pipe_bpp, pipe_config->dither);
7777         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7778                       pipe_config->has_pch_encoder,
7779                       pipe_config->fdi_lanes,
7780                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7781                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7782                       pipe_config->fdi_m_n.tu);
7783         DRM_DEBUG_KMS("requested mode:\n");
7784         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7785         DRM_DEBUG_KMS("adjusted mode:\n");
7786         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7787         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7788                       pipe_config->gmch_pfit.control,
7789                       pipe_config->gmch_pfit.pgm_ratios,
7790                       pipe_config->gmch_pfit.lvds_border_bits);
7791         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7792                       pipe_config->pch_pfit.pos,
7793                       pipe_config->pch_pfit.size);
7794         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7795 }
7796
7797 static bool check_encoder_cloning(struct drm_crtc *crtc)
7798 {
7799         int num_encoders = 0;
7800         bool uncloneable_encoders = false;
7801         struct intel_encoder *encoder;
7802
7803         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7804                             base.head) {
7805                 if (&encoder->new_crtc->base != crtc)
7806                         continue;
7807
7808                 num_encoders++;
7809                 if (!encoder->cloneable)
7810                         uncloneable_encoders = true;
7811         }
7812
7813         return !(num_encoders > 1 && uncloneable_encoders);
7814 }
7815
7816 static struct intel_crtc_config *
7817 intel_modeset_pipe_config(struct drm_crtc *crtc,
7818                           struct drm_framebuffer *fb,
7819                           struct drm_display_mode *mode)
7820 {
7821         struct drm_device *dev = crtc->dev;
7822         struct drm_encoder_helper_funcs *encoder_funcs;
7823         struct intel_encoder *encoder;
7824         struct intel_crtc_config *pipe_config;
7825         int plane_bpp, ret = -EINVAL;
7826         bool retry = true;
7827
7828         if (!check_encoder_cloning(crtc)) {
7829                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7830                 return ERR_PTR(-EINVAL);
7831         }
7832
7833         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7834         if (!pipe_config)
7835                 return ERR_PTR(-ENOMEM);
7836
7837         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7838         drm_mode_copy(&pipe_config->requested_mode, mode);
7839         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7840
7841         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7842          * plane pixel format and any sink constraints into account. Returns the
7843          * source plane bpp so that dithering can be selected on mismatches
7844          * after encoders and crtc also have had their say. */
7845         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7846                                               fb, pipe_config);
7847         if (plane_bpp < 0)
7848                 goto fail;
7849
7850 encoder_retry:
7851         /* Ensure the port clock defaults are reset when retrying. */
7852         pipe_config->port_clock = 0;
7853         pipe_config->pixel_multiplier = 1;
7854
7855         /* Pass our mode to the connectors and the CRTC to give them a chance to
7856          * adjust it according to limitations or connector properties, and also
7857          * a chance to reject the mode entirely.
7858          */
7859         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7860                             base.head) {
7861
7862                 if (&encoder->new_crtc->base != crtc)
7863                         continue;
7864
7865                 if (encoder->compute_config) {
7866                         if (!(encoder->compute_config(encoder, pipe_config))) {
7867                                 DRM_DEBUG_KMS("Encoder config failure\n");
7868                                 goto fail;
7869                         }
7870
7871                         continue;
7872                 }
7873
7874                 encoder_funcs = encoder->base.helper_private;
7875                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7876                                                 &pipe_config->requested_mode,
7877                                                 &pipe_config->adjusted_mode))) {
7878                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7879                         goto fail;
7880                 }
7881         }
7882
7883         /* Set default port clock if not overwritten by the encoder. Needs to be
7884          * done afterwards in case the encoder adjusts the mode. */
7885         if (!pipe_config->port_clock)
7886                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7887
7888         ret = intel_crtc_compute_config(crtc, pipe_config);
7889         if (ret < 0) {
7890                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7891                 goto fail;
7892         }
7893
7894         if (ret == RETRY) {
7895                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7896                         ret = -EINVAL;
7897                         goto fail;
7898                 }
7899
7900                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7901                 retry = false;
7902                 goto encoder_retry;
7903         }
7904
7905         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7906         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7907                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7908
7909         return pipe_config;
7910 fail:
7911         kfree(pipe_config);
7912         return ERR_PTR(ret);
7913 }
7914
7915 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7916  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7917 static void
7918 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7919                              unsigned *prepare_pipes, unsigned *disable_pipes)
7920 {
7921         struct intel_crtc *intel_crtc;
7922         struct drm_device *dev = crtc->dev;
7923         struct intel_encoder *encoder;
7924         struct intel_connector *connector;
7925         struct drm_crtc *tmp_crtc;
7926
7927         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7928
7929         /* Check which crtcs have changed outputs connected to them, these need
7930          * to be part of the prepare_pipes mask. We don't (yet) support global
7931          * modeset across multiple crtcs, so modeset_pipes will only have one
7932          * bit set at most. */
7933         list_for_each_entry(connector, &dev->mode_config.connector_list,
7934                             base.head) {
7935                 if (connector->base.encoder == &connector->new_encoder->base)
7936                         continue;
7937
7938                 if (connector->base.encoder) {
7939                         tmp_crtc = connector->base.encoder->crtc;
7940
7941                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7942                 }
7943
7944                 if (connector->new_encoder)
7945                         *prepare_pipes |=
7946                                 1 << connector->new_encoder->new_crtc->pipe;
7947         }
7948
7949         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7950                             base.head) {
7951                 if (encoder->base.crtc == &encoder->new_crtc->base)
7952                         continue;
7953
7954                 if (encoder->base.crtc) {
7955                         tmp_crtc = encoder->base.crtc;
7956
7957                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7958                 }
7959
7960                 if (encoder->new_crtc)
7961                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7962         }
7963
7964         /* Check for any pipes that will be fully disabled ... */
7965         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7966                             base.head) {
7967                 bool used = false;
7968
7969                 /* Don't try to disable disabled crtcs. */
7970                 if (!intel_crtc->base.enabled)
7971                         continue;
7972
7973                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7974                                     base.head) {
7975                         if (encoder->new_crtc == intel_crtc)
7976                                 used = true;
7977                 }
7978
7979                 if (!used)
7980                         *disable_pipes |= 1 << intel_crtc->pipe;
7981         }
7982
7983
7984         /* set_mode is also used to update properties on life display pipes. */
7985         intel_crtc = to_intel_crtc(crtc);
7986         if (crtc->enabled)
7987                 *prepare_pipes |= 1 << intel_crtc->pipe;
7988
7989         /*
7990          * For simplicity do a full modeset on any pipe where the output routing
7991          * changed. We could be more clever, but that would require us to be
7992          * more careful with calling the relevant encoder->mode_set functions.
7993          */
7994         if (*prepare_pipes)
7995                 *modeset_pipes = *prepare_pipes;
7996
7997         /* ... and mask these out. */
7998         *modeset_pipes &= ~(*disable_pipes);
7999         *prepare_pipes &= ~(*disable_pipes);
8000
8001         /*
8002          * HACK: We don't (yet) fully support global modesets. intel_set_config
8003          * obies this rule, but the modeset restore mode of
8004          * intel_modeset_setup_hw_state does not.
8005          */
8006         *modeset_pipes &= 1 << intel_crtc->pipe;
8007         *prepare_pipes &= 1 << intel_crtc->pipe;
8008
8009         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8010                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8011 }
8012
8013 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8014 {
8015         struct drm_encoder *encoder;
8016         struct drm_device *dev = crtc->dev;
8017
8018         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8019                 if (encoder->crtc == crtc)
8020                         return true;
8021
8022         return false;
8023 }
8024
8025 static void
8026 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8027 {
8028         struct intel_encoder *intel_encoder;
8029         struct intel_crtc *intel_crtc;
8030         struct drm_connector *connector;
8031
8032         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8033                             base.head) {
8034                 if (!intel_encoder->base.crtc)
8035                         continue;
8036
8037                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8038
8039                 if (prepare_pipes & (1 << intel_crtc->pipe))
8040                         intel_encoder->connectors_active = false;
8041         }
8042
8043         intel_modeset_commit_output_state(dev);
8044
8045         /* Update computed state. */
8046         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8047                             base.head) {
8048                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8049         }
8050
8051         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8052                 if (!connector->encoder || !connector->encoder->crtc)
8053                         continue;
8054
8055                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8056
8057                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8058                         struct drm_property *dpms_property =
8059                                 dev->mode_config.dpms_property;
8060
8061                         connector->dpms = DRM_MODE_DPMS_ON;
8062                         drm_object_property_set_value(&connector->base,
8063                                                          dpms_property,
8064                                                          DRM_MODE_DPMS_ON);
8065
8066                         intel_encoder = to_intel_encoder(connector->encoder);
8067                         intel_encoder->connectors_active = true;
8068                 }
8069         }
8070
8071 }
8072
8073 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8074         list_for_each_entry((intel_crtc), \
8075                             &(dev)->mode_config.crtc_list, \
8076                             base.head) \
8077                 if (mask & (1 <<(intel_crtc)->pipe))
8078
8079 static bool
8080 intel_pipe_config_compare(struct drm_device *dev,
8081                           struct intel_crtc_config *current_config,
8082                           struct intel_crtc_config *pipe_config)
8083 {
8084 #define PIPE_CONF_CHECK_I(name) \
8085         if (current_config->name != pipe_config->name) { \
8086                 DRM_ERROR("mismatch in " #name " " \
8087                           "(expected %i, found %i)\n", \
8088                           current_config->name, \
8089                           pipe_config->name); \
8090                 return false; \
8091         }
8092
8093 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8094         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8095                 DRM_ERROR("mismatch in " #name " " \
8096                           "(expected %i, found %i)\n", \
8097                           current_config->name & (mask), \
8098                           pipe_config->name & (mask)); \
8099                 return false; \
8100         }
8101
8102 #define PIPE_CONF_QUIRK(quirk)  \
8103         ((current_config->quirks | pipe_config->quirks) & (quirk))
8104
8105         PIPE_CONF_CHECK_I(cpu_transcoder);
8106
8107         PIPE_CONF_CHECK_I(has_pch_encoder);
8108         PIPE_CONF_CHECK_I(fdi_lanes);
8109         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8110         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8111         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8112         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8113         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8114
8115         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8116         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8117         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8118         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8119         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8120         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8121
8122         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8123         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8124         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8125         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8126         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8127         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8128
8129         if (!HAS_PCH_SPLIT(dev))
8130                 PIPE_CONF_CHECK_I(pixel_multiplier);
8131
8132         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8133                               DRM_MODE_FLAG_INTERLACE);
8134
8135         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8136                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8137                                       DRM_MODE_FLAG_PHSYNC);
8138                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8139                                       DRM_MODE_FLAG_NHSYNC);
8140                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8141                                       DRM_MODE_FLAG_PVSYNC);
8142                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8143                                       DRM_MODE_FLAG_NVSYNC);
8144         }
8145
8146         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8147         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8148
8149         PIPE_CONF_CHECK_I(gmch_pfit.control);
8150         /* pfit ratios are autocomputed by the hw on gen4+ */
8151         if (INTEL_INFO(dev)->gen < 4)
8152                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8153         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8154         PIPE_CONF_CHECK_I(pch_pfit.pos);
8155         PIPE_CONF_CHECK_I(pch_pfit.size);
8156
8157         PIPE_CONF_CHECK_I(ips_enabled);
8158
8159 #undef PIPE_CONF_CHECK_I
8160 #undef PIPE_CONF_CHECK_FLAGS
8161 #undef PIPE_CONF_QUIRK
8162
8163         return true;
8164 }
8165
8166 void
8167 intel_modeset_check_state(struct drm_device *dev)
8168 {
8169         drm_i915_private_t *dev_priv = dev->dev_private;
8170         struct intel_crtc *crtc;
8171         struct intel_encoder *encoder;
8172         struct intel_connector *connector;
8173         struct intel_crtc_config pipe_config;
8174
8175         list_for_each_entry(connector, &dev->mode_config.connector_list,
8176                             base.head) {
8177                 /* This also checks the encoder/connector hw state with the
8178                  * ->get_hw_state callbacks. */
8179                 intel_connector_check_state(connector);
8180
8181                 WARN(&connector->new_encoder->base != connector->base.encoder,
8182                      "connector's staged encoder doesn't match current encoder\n");
8183         }
8184
8185         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8186                             base.head) {
8187                 bool enabled = false;
8188                 bool active = false;
8189                 enum pipe pipe, tracked_pipe;
8190
8191                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8192                               encoder->base.base.id,
8193                               drm_get_encoder_name(&encoder->base));
8194
8195                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8196                      "encoder's stage crtc doesn't match current crtc\n");
8197                 WARN(encoder->connectors_active && !encoder->base.crtc,
8198                      "encoder's active_connectors set, but no crtc\n");
8199
8200                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8201                                     base.head) {
8202                         if (connector->base.encoder != &encoder->base)
8203                                 continue;
8204                         enabled = true;
8205                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8206                                 active = true;
8207                 }
8208                 WARN(!!encoder->base.crtc != enabled,
8209                      "encoder's enabled state mismatch "
8210                      "(expected %i, found %i)\n",
8211                      !!encoder->base.crtc, enabled);
8212                 WARN(active && !encoder->base.crtc,
8213                      "active encoder with no crtc\n");
8214
8215                 WARN(encoder->connectors_active != active,
8216                      "encoder's computed active state doesn't match tracked active state "
8217                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8218
8219                 active = encoder->get_hw_state(encoder, &pipe);
8220                 WARN(active != encoder->connectors_active,
8221                      "encoder's hw state doesn't match sw tracking "
8222                      "(expected %i, found %i)\n",
8223                      encoder->connectors_active, active);
8224
8225                 if (!encoder->base.crtc)
8226                         continue;
8227
8228                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8229                 WARN(active && pipe != tracked_pipe,
8230                      "active encoder's pipe doesn't match"
8231                      "(expected %i, found %i)\n",
8232                      tracked_pipe, pipe);
8233
8234         }
8235
8236         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8237                             base.head) {
8238                 bool enabled = false;
8239                 bool active = false;
8240
8241                 memset(&pipe_config, 0, sizeof(pipe_config));
8242
8243                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8244                               crtc->base.base.id);
8245
8246                 WARN(crtc->active && !crtc->base.enabled,
8247                      "active crtc, but not enabled in sw tracking\n");
8248
8249                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8250                                     base.head) {
8251                         if (encoder->base.crtc != &crtc->base)
8252                                 continue;
8253                         enabled = true;
8254                         if (encoder->connectors_active)
8255                                 active = true;
8256                 }
8257
8258                 WARN(active != crtc->active,
8259                      "crtc's computed active state doesn't match tracked active state "
8260                      "(expected %i, found %i)\n", active, crtc->active);
8261                 WARN(enabled != crtc->base.enabled,
8262                      "crtc's computed enabled state doesn't match tracked enabled state "
8263                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8264
8265                 active = dev_priv->display.get_pipe_config(crtc,
8266                                                            &pipe_config);
8267                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8268                                     base.head) {
8269                         if (encoder->base.crtc != &crtc->base)
8270                                 continue;
8271                         if (encoder->get_config)
8272                                 encoder->get_config(encoder, &pipe_config);
8273                 }
8274
8275                 WARN(crtc->active != active,
8276                      "crtc active state doesn't match with hw state "
8277                      "(expected %i, found %i)\n", crtc->active, active);
8278
8279                 if (active &&
8280                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8281                         WARN(1, "pipe state doesn't match!\n");
8282                         intel_dump_pipe_config(crtc, &pipe_config,
8283                                                "[hw state]");
8284                         intel_dump_pipe_config(crtc, &crtc->config,
8285                                                "[sw state]");
8286                 }
8287         }
8288 }
8289
8290 static int __intel_set_mode(struct drm_crtc *crtc,
8291                             struct drm_display_mode *mode,
8292                             int x, int y, struct drm_framebuffer *fb)
8293 {
8294         struct drm_device *dev = crtc->dev;
8295         drm_i915_private_t *dev_priv = dev->dev_private;
8296         struct drm_display_mode *saved_mode, *saved_hwmode;
8297         struct intel_crtc_config *pipe_config = NULL;
8298         struct intel_crtc *intel_crtc;
8299         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8300         int ret = 0;
8301
8302         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8303         if (!saved_mode)
8304                 return -ENOMEM;
8305         saved_hwmode = saved_mode + 1;
8306
8307         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8308                                      &prepare_pipes, &disable_pipes);
8309
8310         *saved_hwmode = crtc->hwmode;
8311         *saved_mode = crtc->mode;
8312
8313         /* Hack: Because we don't (yet) support global modeset on multiple
8314          * crtcs, we don't keep track of the new mode for more than one crtc.
8315          * Hence simply check whether any bit is set in modeset_pipes in all the
8316          * pieces of code that are not yet converted to deal with mutliple crtcs
8317          * changing their mode at the same time. */
8318         if (modeset_pipes) {
8319                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8320                 if (IS_ERR(pipe_config)) {
8321                         ret = PTR_ERR(pipe_config);
8322                         pipe_config = NULL;
8323
8324                         goto out;
8325                 }
8326                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8327                                        "[modeset]");
8328         }
8329
8330         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8331                 intel_crtc_disable(&intel_crtc->base);
8332
8333         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8334                 if (intel_crtc->base.enabled)
8335                         dev_priv->display.crtc_disable(&intel_crtc->base);
8336         }
8337
8338         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8339          * to set it here already despite that we pass it down the callchain.
8340          */
8341         if (modeset_pipes) {
8342                 crtc->mode = *mode;
8343                 /* mode_set/enable/disable functions rely on a correct pipe
8344                  * config. */
8345                 to_intel_crtc(crtc)->config = *pipe_config;
8346         }
8347
8348         /* Only after disabling all output pipelines that will be changed can we
8349          * update the the output configuration. */
8350         intel_modeset_update_state(dev, prepare_pipes);
8351
8352         if (dev_priv->display.modeset_global_resources)
8353                 dev_priv->display.modeset_global_resources(dev);
8354
8355         /* Set up the DPLL and any encoders state that needs to adjust or depend
8356          * on the DPLL.
8357          */
8358         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8359                 ret = intel_crtc_mode_set(&intel_crtc->base,
8360                                           x, y, fb);
8361                 if (ret)
8362                         goto done;
8363         }
8364
8365         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8366         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8367                 dev_priv->display.crtc_enable(&intel_crtc->base);
8368
8369         if (modeset_pipes) {
8370                 /* Store real post-adjustment hardware mode. */
8371                 crtc->hwmode = pipe_config->adjusted_mode;
8372
8373                 /* Calculate and store various constants which
8374                  * are later needed by vblank and swap-completion
8375                  * timestamping. They are derived from true hwmode.
8376                  */
8377                 drm_calc_timestamping_constants(crtc);
8378         }
8379
8380         /* FIXME: add subpixel order */
8381 done:
8382         if (ret && crtc->enabled) {
8383                 crtc->hwmode = *saved_hwmode;
8384                 crtc->mode = *saved_mode;
8385         }
8386
8387 out:
8388         kfree(pipe_config);
8389         kfree(saved_mode);
8390         return ret;
8391 }
8392
8393 int intel_set_mode(struct drm_crtc *crtc,
8394                      struct drm_display_mode *mode,
8395                      int x, int y, struct drm_framebuffer *fb)
8396 {
8397         int ret;
8398
8399         ret = __intel_set_mode(crtc, mode, x, y, fb);
8400
8401         if (ret == 0)
8402                 intel_modeset_check_state(crtc->dev);
8403
8404         return ret;
8405 }
8406
8407 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8408 {
8409         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8410 }
8411
8412 #undef for_each_intel_crtc_masked
8413
8414 static void intel_set_config_free(struct intel_set_config *config)
8415 {
8416         if (!config)
8417                 return;
8418
8419         kfree(config->save_connector_encoders);
8420         kfree(config->save_encoder_crtcs);
8421         kfree(config);
8422 }
8423
8424 static int intel_set_config_save_state(struct drm_device *dev,
8425                                        struct intel_set_config *config)
8426 {
8427         struct drm_encoder *encoder;
8428         struct drm_connector *connector;
8429         int count;
8430
8431         config->save_encoder_crtcs =
8432                 kcalloc(dev->mode_config.num_encoder,
8433                         sizeof(struct drm_crtc *), GFP_KERNEL);
8434         if (!config->save_encoder_crtcs)
8435                 return -ENOMEM;
8436
8437         config->save_connector_encoders =
8438                 kcalloc(dev->mode_config.num_connector,
8439                         sizeof(struct drm_encoder *), GFP_KERNEL);
8440         if (!config->save_connector_encoders)
8441                 return -ENOMEM;
8442
8443         /* Copy data. Note that driver private data is not affected.
8444          * Should anything bad happen only the expected state is
8445          * restored, not the drivers personal bookkeeping.
8446          */
8447         count = 0;
8448         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8449                 config->save_encoder_crtcs[count++] = encoder->crtc;
8450         }
8451
8452         count = 0;
8453         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8454                 config->save_connector_encoders[count++] = connector->encoder;
8455         }
8456
8457         return 0;
8458 }
8459
8460 static void intel_set_config_restore_state(struct drm_device *dev,
8461                                            struct intel_set_config *config)
8462 {
8463         struct intel_encoder *encoder;
8464         struct intel_connector *connector;
8465         int count;
8466
8467         count = 0;
8468         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8469                 encoder->new_crtc =
8470                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8471         }
8472
8473         count = 0;
8474         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8475                 connector->new_encoder =
8476                         to_intel_encoder(config->save_connector_encoders[count++]);
8477         }
8478 }
8479
8480 static void
8481 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8482                                       struct intel_set_config *config)
8483 {
8484
8485         /* We should be able to check here if the fb has the same properties
8486          * and then just flip_or_move it */
8487         if (set->crtc->fb != set->fb) {
8488                 /* If we have no fb then treat it as a full mode set */
8489                 if (set->crtc->fb == NULL) {
8490                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8491                         config->mode_changed = true;
8492                 } else if (set->fb == NULL) {
8493                         config->mode_changed = true;
8494                 } else if (set->fb->pixel_format !=
8495                            set->crtc->fb->pixel_format) {
8496                         config->mode_changed = true;
8497                 } else
8498                         config->fb_changed = true;
8499         }
8500
8501         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8502                 config->fb_changed = true;
8503
8504         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8505                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8506                 drm_mode_debug_printmodeline(&set->crtc->mode);
8507                 drm_mode_debug_printmodeline(set->mode);
8508                 config->mode_changed = true;
8509         }
8510 }
8511
8512 static int
8513 intel_modeset_stage_output_state(struct drm_device *dev,
8514                                  struct drm_mode_set *set,
8515                                  struct intel_set_config *config)
8516 {
8517         struct drm_crtc *new_crtc;
8518         struct intel_connector *connector;
8519         struct intel_encoder *encoder;
8520         int count, ro;
8521
8522         /* The upper layers ensure that we either disable a crtc or have a list
8523          * of connectors. For paranoia, double-check this. */
8524         WARN_ON(!set->fb && (set->num_connectors != 0));
8525         WARN_ON(set->fb && (set->num_connectors == 0));
8526
8527         count = 0;
8528         list_for_each_entry(connector, &dev->mode_config.connector_list,
8529                             base.head) {
8530                 /* Otherwise traverse passed in connector list and get encoders
8531                  * for them. */
8532                 for (ro = 0; ro < set->num_connectors; ro++) {
8533                         if (set->connectors[ro] == &connector->base) {
8534                                 connector->new_encoder = connector->encoder;
8535                                 break;
8536                         }
8537                 }
8538
8539                 /* If we disable the crtc, disable all its connectors. Also, if
8540                  * the connector is on the changing crtc but not on the new
8541                  * connector list, disable it. */
8542                 if ((!set->fb || ro == set->num_connectors) &&
8543                     connector->base.encoder &&
8544                     connector->base.encoder->crtc == set->crtc) {
8545                         connector->new_encoder = NULL;
8546
8547                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8548                                 connector->base.base.id,
8549                                 drm_get_connector_name(&connector->base));
8550                 }
8551
8552
8553                 if (&connector->new_encoder->base != connector->base.encoder) {
8554                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8555                         config->mode_changed = true;
8556                 }
8557         }
8558         /* connector->new_encoder is now updated for all connectors. */
8559
8560         /* Update crtc of enabled connectors. */
8561         count = 0;
8562         list_for_each_entry(connector, &dev->mode_config.connector_list,
8563                             base.head) {
8564                 if (!connector->new_encoder)
8565                         continue;
8566
8567                 new_crtc = connector->new_encoder->base.crtc;
8568
8569                 for (ro = 0; ro < set->num_connectors; ro++) {
8570                         if (set->connectors[ro] == &connector->base)
8571                                 new_crtc = set->crtc;
8572                 }
8573
8574                 /* Make sure the new CRTC will work with the encoder */
8575                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8576                                            new_crtc)) {
8577                         return -EINVAL;
8578                 }
8579                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8580
8581                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8582                         connector->base.base.id,
8583                         drm_get_connector_name(&connector->base),
8584                         new_crtc->base.id);
8585         }
8586
8587         /* Check for any encoders that needs to be disabled. */
8588         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8589                             base.head) {
8590                 list_for_each_entry(connector,
8591                                     &dev->mode_config.connector_list,
8592                                     base.head) {
8593                         if (connector->new_encoder == encoder) {
8594                                 WARN_ON(!connector->new_encoder->new_crtc);
8595
8596                                 goto next_encoder;
8597                         }
8598                 }
8599                 encoder->new_crtc = NULL;
8600 next_encoder:
8601                 /* Only now check for crtc changes so we don't miss encoders
8602                  * that will be disabled. */
8603                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8604                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8605                         config->mode_changed = true;
8606                 }
8607         }
8608         /* Now we've also updated encoder->new_crtc for all encoders. */
8609
8610         return 0;
8611 }
8612
8613 static int intel_crtc_set_config(struct drm_mode_set *set)
8614 {
8615         struct drm_device *dev;
8616         struct drm_mode_set save_set;
8617         struct intel_set_config *config;
8618         int ret;
8619
8620         BUG_ON(!set);
8621         BUG_ON(!set->crtc);
8622         BUG_ON(!set->crtc->helper_private);
8623
8624         /* Enforce sane interface api - has been abused by the fb helper. */
8625         BUG_ON(!set->mode && set->fb);
8626         BUG_ON(set->fb && set->num_connectors == 0);
8627
8628         if (set->fb) {
8629                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8630                                 set->crtc->base.id, set->fb->base.id,
8631                                 (int)set->num_connectors, set->x, set->y);
8632         } else {
8633                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8634         }
8635
8636         dev = set->crtc->dev;
8637
8638         ret = -ENOMEM;
8639         config = kzalloc(sizeof(*config), GFP_KERNEL);
8640         if (!config)
8641                 goto out_config;
8642
8643         ret = intel_set_config_save_state(dev, config);
8644         if (ret)
8645                 goto out_config;
8646
8647         save_set.crtc = set->crtc;
8648         save_set.mode = &set->crtc->mode;
8649         save_set.x = set->crtc->x;
8650         save_set.y = set->crtc->y;
8651         save_set.fb = set->crtc->fb;
8652
8653         /* Compute whether we need a full modeset, only an fb base update or no
8654          * change at all. In the future we might also check whether only the
8655          * mode changed, e.g. for LVDS where we only change the panel fitter in
8656          * such cases. */
8657         intel_set_config_compute_mode_changes(set, config);
8658
8659         ret = intel_modeset_stage_output_state(dev, set, config);
8660         if (ret)
8661                 goto fail;
8662
8663         if (config->mode_changed) {
8664                 ret = intel_set_mode(set->crtc, set->mode,
8665                                      set->x, set->y, set->fb);
8666                 if (ret) {
8667                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8668                                   set->crtc->base.id, ret);
8669                         goto fail;
8670                 }
8671         } else if (config->fb_changed) {
8672                 intel_crtc_wait_for_pending_flips(set->crtc);
8673
8674                 ret = intel_pipe_set_base(set->crtc,
8675                                           set->x, set->y, set->fb);
8676         }
8677
8678         intel_set_config_free(config);
8679
8680         return 0;
8681
8682 fail:
8683         intel_set_config_restore_state(dev, config);
8684
8685         /* Try to restore the config */
8686         if (config->mode_changed &&
8687             intel_set_mode(save_set.crtc, save_set.mode,
8688                            save_set.x, save_set.y, save_set.fb))
8689                 DRM_ERROR("failed to restore config after modeset failure\n");
8690
8691 out_config:
8692         intel_set_config_free(config);
8693         return ret;
8694 }
8695
8696 static const struct drm_crtc_funcs intel_crtc_funcs = {
8697         .cursor_set = intel_crtc_cursor_set,
8698         .cursor_move = intel_crtc_cursor_move,
8699         .gamma_set = intel_crtc_gamma_set,
8700         .set_config = intel_crtc_set_config,
8701         .destroy = intel_crtc_destroy,
8702         .page_flip = intel_crtc_page_flip,
8703 };
8704
8705 static void intel_cpu_pll_init(struct drm_device *dev)
8706 {
8707         if (HAS_DDI(dev))
8708                 intel_ddi_pll_init(dev);
8709 }
8710
8711 static void intel_pch_pll_init(struct drm_device *dev)
8712 {
8713         drm_i915_private_t *dev_priv = dev->dev_private;
8714         int i;
8715
8716         if (dev_priv->num_pch_pll == 0) {
8717                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8718                 return;
8719         }
8720
8721         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8722                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8723                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8724                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8725         }
8726 }
8727
8728 static void intel_crtc_init(struct drm_device *dev, int pipe)
8729 {
8730         drm_i915_private_t *dev_priv = dev->dev_private;
8731         struct intel_crtc *intel_crtc;
8732         int i;
8733
8734         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8735         if (intel_crtc == NULL)
8736                 return;
8737
8738         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8739
8740         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8741         for (i = 0; i < 256; i++) {
8742                 intel_crtc->lut_r[i] = i;
8743                 intel_crtc->lut_g[i] = i;
8744                 intel_crtc->lut_b[i] = i;
8745         }
8746
8747         /* Swap pipes & planes for FBC on pre-965 */
8748         intel_crtc->pipe = pipe;
8749         intel_crtc->plane = pipe;
8750         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8751                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8752                 intel_crtc->plane = !pipe;
8753         }
8754
8755         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8756                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8757         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8758         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8759
8760         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8761 }
8762
8763 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8764                                 struct drm_file *file)
8765 {
8766         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8767         struct drm_mode_object *drmmode_obj;
8768         struct intel_crtc *crtc;
8769
8770         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8771                 return -ENODEV;
8772
8773         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8774                         DRM_MODE_OBJECT_CRTC);
8775
8776         if (!drmmode_obj) {
8777                 DRM_ERROR("no such CRTC id\n");
8778                 return -EINVAL;
8779         }
8780
8781         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8782         pipe_from_crtc_id->pipe = crtc->pipe;
8783
8784         return 0;
8785 }
8786
8787 static int intel_encoder_clones(struct intel_encoder *encoder)
8788 {
8789         struct drm_device *dev = encoder->base.dev;
8790         struct intel_encoder *source_encoder;
8791         int index_mask = 0;
8792         int entry = 0;
8793
8794         list_for_each_entry(source_encoder,
8795                             &dev->mode_config.encoder_list, base.head) {
8796
8797                 if (encoder == source_encoder)
8798                         index_mask |= (1 << entry);
8799
8800                 /* Intel hw has only one MUX where enocoders could be cloned. */
8801                 if (encoder->cloneable && source_encoder->cloneable)
8802                         index_mask |= (1 << entry);
8803
8804                 entry++;
8805         }
8806
8807         return index_mask;
8808 }
8809
8810 static bool has_edp_a(struct drm_device *dev)
8811 {
8812         struct drm_i915_private *dev_priv = dev->dev_private;
8813
8814         if (!IS_MOBILE(dev))
8815                 return false;
8816
8817         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8818                 return false;
8819
8820         if (IS_GEN5(dev) &&
8821             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8822                 return false;
8823
8824         return true;
8825 }
8826
8827 static void intel_setup_outputs(struct drm_device *dev)
8828 {
8829         struct drm_i915_private *dev_priv = dev->dev_private;
8830         struct intel_encoder *encoder;
8831         bool dpd_is_edp = false;
8832         bool has_lvds;
8833
8834         has_lvds = intel_lvds_init(dev);
8835         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8836                 /* disable the panel fitter on everything but LVDS */
8837                 I915_WRITE(PFIT_CONTROL, 0);
8838         }
8839
8840         if (!IS_ULT(dev))
8841                 intel_crt_init(dev);
8842
8843         if (HAS_DDI(dev)) {
8844                 int found;
8845
8846                 /* Haswell uses DDI functions to detect digital outputs */
8847                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8848                 /* DDI A only supports eDP */
8849                 if (found)
8850                         intel_ddi_init(dev, PORT_A);
8851
8852                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8853                  * register */
8854                 found = I915_READ(SFUSE_STRAP);
8855
8856                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8857                         intel_ddi_init(dev, PORT_B);
8858                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8859                         intel_ddi_init(dev, PORT_C);
8860                 if (found & SFUSE_STRAP_DDID_DETECTED)
8861                         intel_ddi_init(dev, PORT_D);
8862         } else if (HAS_PCH_SPLIT(dev)) {
8863                 int found;
8864                 dpd_is_edp = intel_dpd_is_edp(dev);
8865
8866                 if (has_edp_a(dev))
8867                         intel_dp_init(dev, DP_A, PORT_A);
8868
8869                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8870                         /* PCH SDVOB multiplex with HDMIB */
8871                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8872                         if (!found)
8873                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8874                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8875                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8876                 }
8877
8878                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8879                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8880
8881                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8882                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8883
8884                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8885                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8886
8887                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8888                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8889         } else if (IS_VALLEYVIEW(dev)) {
8890                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8891                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8892                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8893
8894                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8895                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8896                                         PORT_B);
8897                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8898                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8899                 }
8900         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8901                 bool found = false;
8902
8903                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8904                         DRM_DEBUG_KMS("probing SDVOB\n");
8905                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8906                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8907                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8908                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8909                         }
8910
8911                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
8912                                 intel_dp_init(dev, DP_B, PORT_B);
8913                 }
8914
8915                 /* Before G4X SDVOC doesn't have its own detect register */
8916
8917                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8918                         DRM_DEBUG_KMS("probing SDVOC\n");
8919                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8920                 }
8921
8922                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8923
8924                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8925                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8926                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8927                         }
8928                         if (SUPPORTS_INTEGRATED_DP(dev))
8929                                 intel_dp_init(dev, DP_C, PORT_C);
8930                 }
8931
8932                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8933                     (I915_READ(DP_D) & DP_DETECTED))
8934                         intel_dp_init(dev, DP_D, PORT_D);
8935         } else if (IS_GEN2(dev))
8936                 intel_dvo_init(dev);
8937
8938         if (SUPPORTS_TV(dev))
8939                 intel_tv_init(dev);
8940
8941         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8942                 encoder->base.possible_crtcs = encoder->crtc_mask;
8943                 encoder->base.possible_clones =
8944                         intel_encoder_clones(encoder);
8945         }
8946
8947         intel_init_pch_refclk(dev);
8948
8949         drm_helper_move_panel_connectors_to_head(dev);
8950 }
8951
8952 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8953 {
8954         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8955
8956         drm_framebuffer_cleanup(fb);
8957         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8958
8959         kfree(intel_fb);
8960 }
8961
8962 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8963                                                 struct drm_file *file,
8964                                                 unsigned int *handle)
8965 {
8966         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8967         struct drm_i915_gem_object *obj = intel_fb->obj;
8968
8969         return drm_gem_handle_create(file, &obj->base, handle);
8970 }
8971
8972 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8973         .destroy = intel_user_framebuffer_destroy,
8974         .create_handle = intel_user_framebuffer_create_handle,
8975 };
8976
8977 int intel_framebuffer_init(struct drm_device *dev,
8978                            struct intel_framebuffer *intel_fb,
8979                            struct drm_mode_fb_cmd2 *mode_cmd,
8980                            struct drm_i915_gem_object *obj)
8981 {
8982         int ret;
8983
8984         if (obj->tiling_mode == I915_TILING_Y) {
8985                 DRM_DEBUG("hardware does not support tiling Y\n");
8986                 return -EINVAL;
8987         }
8988
8989         if (mode_cmd->pitches[0] & 63) {
8990                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8991                           mode_cmd->pitches[0]);
8992                 return -EINVAL;
8993         }
8994
8995         /* FIXME <= Gen4 stride limits are bit unclear */
8996         if (mode_cmd->pitches[0] > 32768) {
8997                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8998                           mode_cmd->pitches[0]);
8999                 return -EINVAL;
9000         }
9001
9002         if (obj->tiling_mode != I915_TILING_NONE &&
9003             mode_cmd->pitches[0] != obj->stride) {
9004                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9005                           mode_cmd->pitches[0], obj->stride);
9006                 return -EINVAL;
9007         }
9008
9009         /* Reject formats not supported by any plane early. */
9010         switch (mode_cmd->pixel_format) {
9011         case DRM_FORMAT_C8:
9012         case DRM_FORMAT_RGB565:
9013         case DRM_FORMAT_XRGB8888:
9014         case DRM_FORMAT_ARGB8888:
9015                 break;
9016         case DRM_FORMAT_XRGB1555:
9017         case DRM_FORMAT_ARGB1555:
9018                 if (INTEL_INFO(dev)->gen > 3) {
9019                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9020                         return -EINVAL;
9021                 }
9022                 break;
9023         case DRM_FORMAT_XBGR8888:
9024         case DRM_FORMAT_ABGR8888:
9025         case DRM_FORMAT_XRGB2101010:
9026         case DRM_FORMAT_ARGB2101010:
9027         case DRM_FORMAT_XBGR2101010:
9028         case DRM_FORMAT_ABGR2101010:
9029                 if (INTEL_INFO(dev)->gen < 4) {
9030                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9031                         return -EINVAL;
9032                 }
9033                 break;
9034         case DRM_FORMAT_YUYV:
9035         case DRM_FORMAT_UYVY:
9036         case DRM_FORMAT_YVYU:
9037         case DRM_FORMAT_VYUY:
9038                 if (INTEL_INFO(dev)->gen < 5) {
9039                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
9040                         return -EINVAL;
9041                 }
9042                 break;
9043         default:
9044                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
9045                 return -EINVAL;
9046         }
9047
9048         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9049         if (mode_cmd->offsets[0] != 0)
9050                 return -EINVAL;
9051
9052         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9053         intel_fb->obj = obj;
9054
9055         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9056         if (ret) {
9057                 DRM_ERROR("framebuffer init failed %d\n", ret);
9058                 return ret;
9059         }
9060
9061         return 0;
9062 }
9063
9064 static struct drm_framebuffer *
9065 intel_user_framebuffer_create(struct drm_device *dev,
9066                               struct drm_file *filp,
9067                               struct drm_mode_fb_cmd2 *mode_cmd)
9068 {
9069         struct drm_i915_gem_object *obj;
9070
9071         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9072                                                 mode_cmd->handles[0]));
9073         if (&obj->base == NULL)
9074                 return ERR_PTR(-ENOENT);
9075
9076         return intel_framebuffer_create(dev, mode_cmd, obj);
9077 }
9078
9079 static const struct drm_mode_config_funcs intel_mode_funcs = {
9080         .fb_create = intel_user_framebuffer_create,
9081         .output_poll_changed = intel_fb_output_poll_changed,
9082 };
9083
9084 /* Set up chip specific display functions */
9085 static void intel_init_display(struct drm_device *dev)
9086 {
9087         struct drm_i915_private *dev_priv = dev->dev_private;
9088
9089         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9090                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9091         else if (IS_VALLEYVIEW(dev))
9092                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9093         else if (IS_PINEVIEW(dev))
9094                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9095         else
9096                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9097
9098         if (HAS_DDI(dev)) {
9099                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9100                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9101                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9102                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9103                 dev_priv->display.off = haswell_crtc_off;
9104                 dev_priv->display.update_plane = ironlake_update_plane;
9105         } else if (HAS_PCH_SPLIT(dev)) {
9106                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9107                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9108                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9109                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9110                 dev_priv->display.off = ironlake_crtc_off;
9111                 dev_priv->display.update_plane = ironlake_update_plane;
9112         } else if (IS_VALLEYVIEW(dev)) {
9113                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9114                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9115                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9116                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9117                 dev_priv->display.off = i9xx_crtc_off;
9118                 dev_priv->display.update_plane = i9xx_update_plane;
9119         } else {
9120                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9121                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9122                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9123                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9124                 dev_priv->display.off = i9xx_crtc_off;
9125                 dev_priv->display.update_plane = i9xx_update_plane;
9126         }
9127
9128         /* Returns the core display clock speed */
9129         if (IS_VALLEYVIEW(dev))
9130                 dev_priv->display.get_display_clock_speed =
9131                         valleyview_get_display_clock_speed;
9132         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9133                 dev_priv->display.get_display_clock_speed =
9134                         i945_get_display_clock_speed;
9135         else if (IS_I915G(dev))
9136                 dev_priv->display.get_display_clock_speed =
9137                         i915_get_display_clock_speed;
9138         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9139                 dev_priv->display.get_display_clock_speed =
9140                         i9xx_misc_get_display_clock_speed;
9141         else if (IS_I915GM(dev))
9142                 dev_priv->display.get_display_clock_speed =
9143                         i915gm_get_display_clock_speed;
9144         else if (IS_I865G(dev))
9145                 dev_priv->display.get_display_clock_speed =
9146                         i865_get_display_clock_speed;
9147         else if (IS_I85X(dev))
9148                 dev_priv->display.get_display_clock_speed =
9149                         i855_get_display_clock_speed;
9150         else /* 852, 830 */
9151                 dev_priv->display.get_display_clock_speed =
9152                         i830_get_display_clock_speed;
9153
9154         if (HAS_PCH_SPLIT(dev)) {
9155                 if (IS_GEN5(dev)) {
9156                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9157                         dev_priv->display.write_eld = ironlake_write_eld;
9158                 } else if (IS_GEN6(dev)) {
9159                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9160                         dev_priv->display.write_eld = ironlake_write_eld;
9161                 } else if (IS_IVYBRIDGE(dev)) {
9162                         /* FIXME: detect B0+ stepping and use auto training */
9163                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9164                         dev_priv->display.write_eld = ironlake_write_eld;
9165                         dev_priv->display.modeset_global_resources =
9166                                 ivb_modeset_global_resources;
9167                 } else if (IS_HASWELL(dev)) {
9168                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9169                         dev_priv->display.write_eld = haswell_write_eld;
9170                         dev_priv->display.modeset_global_resources =
9171                                 haswell_modeset_global_resources;
9172                 }
9173         } else if (IS_G4X(dev)) {
9174                 dev_priv->display.write_eld = g4x_write_eld;
9175         }
9176
9177         /* Default just returns -ENODEV to indicate unsupported */
9178         dev_priv->display.queue_flip = intel_default_queue_flip;
9179
9180         switch (INTEL_INFO(dev)->gen) {
9181         case 2:
9182                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9183                 break;
9184
9185         case 3:
9186                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9187                 break;
9188
9189         case 4:
9190         case 5:
9191                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9192                 break;
9193
9194         case 6:
9195                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9196                 break;
9197         case 7:
9198                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9199                 break;
9200         }
9201 }
9202
9203 /*
9204  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9205  * resume, or other times.  This quirk makes sure that's the case for
9206  * affected systems.
9207  */
9208 static void quirk_pipea_force(struct drm_device *dev)
9209 {
9210         struct drm_i915_private *dev_priv = dev->dev_private;
9211
9212         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9213         DRM_INFO("applying pipe a force quirk\n");
9214 }
9215
9216 /*
9217  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9218  */
9219 static void quirk_ssc_force_disable(struct drm_device *dev)
9220 {
9221         struct drm_i915_private *dev_priv = dev->dev_private;
9222         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9223         DRM_INFO("applying lvds SSC disable quirk\n");
9224 }
9225
9226 /*
9227  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9228  * brightness value
9229  */
9230 static void quirk_invert_brightness(struct drm_device *dev)
9231 {
9232         struct drm_i915_private *dev_priv = dev->dev_private;
9233         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9234         DRM_INFO("applying inverted panel brightness quirk\n");
9235 }
9236
9237 struct intel_quirk {
9238         int device;
9239         int subsystem_vendor;
9240         int subsystem_device;
9241         void (*hook)(struct drm_device *dev);
9242 };
9243
9244 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9245 struct intel_dmi_quirk {
9246         void (*hook)(struct drm_device *dev);
9247         const struct dmi_system_id (*dmi_id_list)[];
9248 };
9249
9250 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9251 {
9252         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9253         return 1;
9254 }
9255
9256 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9257         {
9258                 .dmi_id_list = &(const struct dmi_system_id[]) {
9259                         {
9260                                 .callback = intel_dmi_reverse_brightness,
9261                                 .ident = "NCR Corporation",
9262                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9263                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9264                                 },
9265                         },
9266                         { }  /* terminating entry */
9267                 },
9268                 .hook = quirk_invert_brightness,
9269         },
9270 };
9271
9272 static struct intel_quirk intel_quirks[] = {
9273         /* HP Mini needs pipe A force quirk (LP: #322104) */
9274         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9275
9276         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9277         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9278
9279         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9280         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9281
9282         /* 830/845 need to leave pipe A & dpll A up */
9283         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9284         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9285
9286         /* Lenovo U160 cannot use SSC on LVDS */
9287         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9288
9289         /* Sony Vaio Y cannot use SSC on LVDS */
9290         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9291
9292         /* Acer Aspire 5734Z must invert backlight brightness */
9293         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9294
9295         /* Acer/eMachines G725 */
9296         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9297
9298         /* Acer/eMachines e725 */
9299         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9300
9301         /* Acer/Packard Bell NCL20 */
9302         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9303
9304         /* Acer Aspire 4736Z */
9305         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9306 };
9307
9308 static void intel_init_quirks(struct drm_device *dev)
9309 {
9310         struct pci_dev *d = dev->pdev;
9311         int i;
9312
9313         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9314                 struct intel_quirk *q = &intel_quirks[i];
9315
9316                 if (d->device == q->device &&
9317                     (d->subsystem_vendor == q->subsystem_vendor ||
9318                      q->subsystem_vendor == PCI_ANY_ID) &&
9319                     (d->subsystem_device == q->subsystem_device ||
9320                      q->subsystem_device == PCI_ANY_ID))
9321                         q->hook(dev);
9322         }
9323         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9324                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9325                         intel_dmi_quirks[i].hook(dev);
9326         }
9327 }
9328
9329 /* Disable the VGA plane that we never use */
9330 static void i915_disable_vga(struct drm_device *dev)
9331 {
9332         struct drm_i915_private *dev_priv = dev->dev_private;
9333         u8 sr1;
9334         u32 vga_reg = i915_vgacntrl_reg(dev);
9335
9336         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9337         outb(SR01, VGA_SR_INDEX);
9338         sr1 = inb(VGA_SR_DATA);
9339         outb(sr1 | 1<<5, VGA_SR_DATA);
9340         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9341         udelay(300);
9342
9343         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9344         POSTING_READ(vga_reg);
9345 }
9346
9347 void intel_modeset_init_hw(struct drm_device *dev)
9348 {
9349         intel_init_power_well(dev);
9350
9351         intel_prepare_ddi(dev);
9352
9353         intel_init_clock_gating(dev);
9354
9355         mutex_lock(&dev->struct_mutex);
9356         intel_enable_gt_powersave(dev);
9357         mutex_unlock(&dev->struct_mutex);
9358 }
9359
9360 void intel_modeset_suspend_hw(struct drm_device *dev)
9361 {
9362         intel_suspend_hw(dev);
9363 }
9364
9365 void intel_modeset_init(struct drm_device *dev)
9366 {
9367         struct drm_i915_private *dev_priv = dev->dev_private;
9368         int i, j, ret;
9369
9370         drm_mode_config_init(dev);
9371
9372         dev->mode_config.min_width = 0;
9373         dev->mode_config.min_height = 0;
9374
9375         dev->mode_config.preferred_depth = 24;
9376         dev->mode_config.prefer_shadow = 1;
9377
9378         dev->mode_config.funcs = &intel_mode_funcs;
9379
9380         intel_init_quirks(dev);
9381
9382         intel_init_pm(dev);
9383
9384         if (INTEL_INFO(dev)->num_pipes == 0)
9385                 return;
9386
9387         intel_init_display(dev);
9388
9389         if (IS_GEN2(dev)) {
9390                 dev->mode_config.max_width = 2048;
9391                 dev->mode_config.max_height = 2048;
9392         } else if (IS_GEN3(dev)) {
9393                 dev->mode_config.max_width = 4096;
9394                 dev->mode_config.max_height = 4096;
9395         } else {
9396                 dev->mode_config.max_width = 8192;
9397                 dev->mode_config.max_height = 8192;
9398         }
9399         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9400
9401         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9402                       INTEL_INFO(dev)->num_pipes,
9403                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9404
9405         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9406                 intel_crtc_init(dev, i);
9407                 for (j = 0; j < dev_priv->num_plane; j++) {
9408                         ret = intel_plane_init(dev, i, j);
9409                         if (ret)
9410                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9411                                               pipe_name(i), sprite_name(i, j), ret);
9412                 }
9413         }
9414
9415         intel_cpu_pll_init(dev);
9416         intel_pch_pll_init(dev);
9417
9418         /* Just disable it once at startup */
9419         i915_disable_vga(dev);
9420         intel_setup_outputs(dev);
9421
9422         /* Just in case the BIOS is doing something questionable. */
9423         intel_disable_fbc(dev);
9424 }
9425
9426 static void
9427 intel_connector_break_all_links(struct intel_connector *connector)
9428 {
9429         connector->base.dpms = DRM_MODE_DPMS_OFF;
9430         connector->base.encoder = NULL;
9431         connector->encoder->connectors_active = false;
9432         connector->encoder->base.crtc = NULL;
9433 }
9434
9435 static void intel_enable_pipe_a(struct drm_device *dev)
9436 {
9437         struct intel_connector *connector;
9438         struct drm_connector *crt = NULL;
9439         struct intel_load_detect_pipe load_detect_temp;
9440
9441         /* We can't just switch on the pipe A, we need to set things up with a
9442          * proper mode and output configuration. As a gross hack, enable pipe A
9443          * by enabling the load detect pipe once. */
9444         list_for_each_entry(connector,
9445                             &dev->mode_config.connector_list,
9446                             base.head) {
9447                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9448                         crt = &connector->base;
9449                         break;
9450                 }
9451         }
9452
9453         if (!crt)
9454                 return;
9455
9456         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9457                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9458
9459
9460 }
9461
9462 static bool
9463 intel_check_plane_mapping(struct intel_crtc *crtc)
9464 {
9465         struct drm_device *dev = crtc->base.dev;
9466         struct drm_i915_private *dev_priv = dev->dev_private;
9467         u32 reg, val;
9468
9469         if (INTEL_INFO(dev)->num_pipes == 1)
9470                 return true;
9471
9472         reg = DSPCNTR(!crtc->plane);
9473         val = I915_READ(reg);
9474
9475         if ((val & DISPLAY_PLANE_ENABLE) &&
9476             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9477                 return false;
9478
9479         return true;
9480 }
9481
9482 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9483 {
9484         struct drm_device *dev = crtc->base.dev;
9485         struct drm_i915_private *dev_priv = dev->dev_private;
9486         u32 reg;
9487
9488         /* Clear any frame start delays used for debugging left by the BIOS */
9489         reg = PIPECONF(crtc->config.cpu_transcoder);
9490         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9491
9492         /* We need to sanitize the plane -> pipe mapping first because this will
9493          * disable the crtc (and hence change the state) if it is wrong. Note
9494          * that gen4+ has a fixed plane -> pipe mapping.  */
9495         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9496                 struct intel_connector *connector;
9497                 bool plane;
9498
9499                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9500                               crtc->base.base.id);
9501
9502                 /* Pipe has the wrong plane attached and the plane is active.
9503                  * Temporarily change the plane mapping and disable everything
9504                  * ...  */
9505                 plane = crtc->plane;
9506                 crtc->plane = !plane;
9507                 dev_priv->display.crtc_disable(&crtc->base);
9508                 crtc->plane = plane;
9509
9510                 /* ... and break all links. */
9511                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9512                                     base.head) {
9513                         if (connector->encoder->base.crtc != &crtc->base)
9514                                 continue;
9515
9516                         intel_connector_break_all_links(connector);
9517                 }
9518
9519                 WARN_ON(crtc->active);
9520                 crtc->base.enabled = false;
9521         }
9522
9523         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9524             crtc->pipe == PIPE_A && !crtc->active) {
9525                 /* BIOS forgot to enable pipe A, this mostly happens after
9526                  * resume. Force-enable the pipe to fix this, the update_dpms
9527                  * call below we restore the pipe to the right state, but leave
9528                  * the required bits on. */
9529                 intel_enable_pipe_a(dev);
9530         }
9531
9532         /* Adjust the state of the output pipe according to whether we
9533          * have active connectors/encoders. */
9534         intel_crtc_update_dpms(&crtc->base);
9535
9536         if (crtc->active != crtc->base.enabled) {
9537                 struct intel_encoder *encoder;
9538
9539                 /* This can happen either due to bugs in the get_hw_state
9540                  * functions or because the pipe is force-enabled due to the
9541                  * pipe A quirk. */
9542                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9543                               crtc->base.base.id,
9544                               crtc->base.enabled ? "enabled" : "disabled",
9545                               crtc->active ? "enabled" : "disabled");
9546
9547                 crtc->base.enabled = crtc->active;
9548
9549                 /* Because we only establish the connector -> encoder ->
9550                  * crtc links if something is active, this means the
9551                  * crtc is now deactivated. Break the links. connector
9552                  * -> encoder links are only establish when things are
9553                  *  actually up, hence no need to break them. */
9554                 WARN_ON(crtc->active);
9555
9556                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9557                         WARN_ON(encoder->connectors_active);
9558                         encoder->base.crtc = NULL;
9559                 }
9560         }
9561 }
9562
9563 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9564 {
9565         struct intel_connector *connector;
9566         struct drm_device *dev = encoder->base.dev;
9567
9568         /* We need to check both for a crtc link (meaning that the
9569          * encoder is active and trying to read from a pipe) and the
9570          * pipe itself being active. */
9571         bool has_active_crtc = encoder->base.crtc &&
9572                 to_intel_crtc(encoder->base.crtc)->active;
9573
9574         if (encoder->connectors_active && !has_active_crtc) {
9575                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9576                               encoder->base.base.id,
9577                               drm_get_encoder_name(&encoder->base));
9578
9579                 /* Connector is active, but has no active pipe. This is
9580                  * fallout from our resume register restoring. Disable
9581                  * the encoder manually again. */
9582                 if (encoder->base.crtc) {
9583                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9584                                       encoder->base.base.id,
9585                                       drm_get_encoder_name(&encoder->base));
9586                         encoder->disable(encoder);
9587                 }
9588
9589                 /* Inconsistent output/port/pipe state happens presumably due to
9590                  * a bug in one of the get_hw_state functions. Or someplace else
9591                  * in our code, like the register restore mess on resume. Clamp
9592                  * things to off as a safer default. */
9593                 list_for_each_entry(connector,
9594                                     &dev->mode_config.connector_list,
9595                                     base.head) {
9596                         if (connector->encoder != encoder)
9597                                 continue;
9598
9599                         intel_connector_break_all_links(connector);
9600                 }
9601         }
9602         /* Enabled encoders without active connectors will be fixed in
9603          * the crtc fixup. */
9604 }
9605
9606 void i915_redisable_vga(struct drm_device *dev)
9607 {
9608         struct drm_i915_private *dev_priv = dev->dev_private;
9609         u32 vga_reg = i915_vgacntrl_reg(dev);
9610
9611         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9612                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9613                 i915_disable_vga(dev);
9614         }
9615 }
9616
9617 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9618  * and i915 state tracking structures. */
9619 void intel_modeset_setup_hw_state(struct drm_device *dev,
9620                                   bool force_restore)
9621 {
9622         struct drm_i915_private *dev_priv = dev->dev_private;
9623         enum pipe pipe;
9624         struct drm_plane *plane;
9625         struct intel_crtc *crtc;
9626         struct intel_encoder *encoder;
9627         struct intel_connector *connector;
9628
9629         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9630                             base.head) {
9631                 memset(&crtc->config, 0, sizeof(crtc->config));
9632
9633                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9634                                                                  &crtc->config);
9635
9636                 crtc->base.enabled = crtc->active;
9637
9638                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9639                               crtc->base.base.id,
9640                               crtc->active ? "enabled" : "disabled");
9641         }
9642
9643         if (HAS_DDI(dev))
9644                 intel_ddi_setup_hw_pll_state(dev);
9645
9646         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9647                             base.head) {
9648                 pipe = 0;
9649
9650                 if (encoder->get_hw_state(encoder, &pipe)) {
9651                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9652                         encoder->base.crtc = &crtc->base;
9653                         if (encoder->get_config)
9654                                 encoder->get_config(encoder, &crtc->config);
9655                 } else {
9656                         encoder->base.crtc = NULL;
9657                 }
9658
9659                 encoder->connectors_active = false;
9660                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9661                               encoder->base.base.id,
9662                               drm_get_encoder_name(&encoder->base),
9663                               encoder->base.crtc ? "enabled" : "disabled",
9664                               pipe);
9665         }
9666
9667         list_for_each_entry(connector, &dev->mode_config.connector_list,
9668                             base.head) {
9669                 if (connector->get_hw_state(connector)) {
9670                         connector->base.dpms = DRM_MODE_DPMS_ON;
9671                         connector->encoder->connectors_active = true;
9672                         connector->base.encoder = &connector->encoder->base;
9673                 } else {
9674                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9675                         connector->base.encoder = NULL;
9676                 }
9677                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9678                               connector->base.base.id,
9679                               drm_get_connector_name(&connector->base),
9680                               connector->base.encoder ? "enabled" : "disabled");
9681         }
9682
9683         /* HW state is read out, now we need to sanitize this mess. */
9684         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9685                             base.head) {
9686                 intel_sanitize_encoder(encoder);
9687         }
9688
9689         for_each_pipe(pipe) {
9690                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9691                 intel_sanitize_crtc(crtc);
9692                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9693         }
9694
9695         if (force_restore) {
9696                 /*
9697                  * We need to use raw interfaces for restoring state to avoid
9698                  * checking (bogus) intermediate states.
9699                  */
9700                 for_each_pipe(pipe) {
9701                         struct drm_crtc *crtc =
9702                                 dev_priv->pipe_to_crtc_mapping[pipe];
9703
9704                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9705                                          crtc->fb);
9706                 }
9707                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9708                         intel_plane_restore(plane);
9709
9710                 i915_redisable_vga(dev);
9711         } else {
9712                 intel_modeset_update_staged_output_state(dev);
9713         }
9714
9715         intel_modeset_check_state(dev);
9716
9717         drm_mode_config_reset(dev);
9718 }
9719
9720 void intel_modeset_gem_init(struct drm_device *dev)
9721 {
9722         intel_modeset_init_hw(dev);
9723
9724         intel_setup_overlay(dev);
9725
9726         intel_modeset_setup_hw_state(dev, false);
9727 }
9728
9729 void intel_modeset_cleanup(struct drm_device *dev)
9730 {
9731         struct drm_i915_private *dev_priv = dev->dev_private;
9732         struct drm_crtc *crtc;
9733         struct intel_crtc *intel_crtc;
9734
9735         /*
9736          * Interrupts and polling as the first thing to avoid creating havoc.
9737          * Too much stuff here (turning of rps, connectors, ...) would
9738          * experience fancy races otherwise.
9739          */
9740         drm_irq_uninstall(dev);
9741         cancel_work_sync(&dev_priv->hotplug_work);
9742         /*
9743          * Due to the hpd irq storm handling the hotplug work can re-arm the
9744          * poll handlers. Hence disable polling after hpd handling is shut down.
9745          */
9746         drm_kms_helper_poll_fini(dev);
9747
9748         mutex_lock(&dev->struct_mutex);
9749
9750         intel_unregister_dsm_handler();
9751
9752         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9753                 /* Skip inactive CRTCs */
9754                 if (!crtc->fb)
9755                         continue;
9756
9757                 intel_crtc = to_intel_crtc(crtc);
9758                 intel_increase_pllclock(crtc);
9759         }
9760
9761         intel_disable_fbc(dev);
9762
9763         intel_disable_gt_powersave(dev);
9764
9765         ironlake_teardown_rc6(dev);
9766
9767         mutex_unlock(&dev->struct_mutex);
9768
9769         /* flush any delayed tasks or pending work */
9770         flush_scheduled_work();
9771
9772         /* destroy backlight, if any, before the connectors */
9773         intel_panel_destroy_backlight(dev);
9774
9775         drm_mode_config_cleanup(dev);
9776
9777         intel_cleanup_overlay(dev);
9778 }
9779
9780 /*
9781  * Return which encoder is currently attached for connector.
9782  */
9783 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9784 {
9785         return &intel_attached_encoder(connector)->base;
9786 }
9787
9788 void intel_connector_attach_encoder(struct intel_connector *connector,
9789                                     struct intel_encoder *encoder)
9790 {
9791         connector->encoder = encoder;
9792         drm_mode_connector_attach_encoder(&connector->base,
9793                                           &encoder->base);
9794 }
9795
9796 /*
9797  * set vga decode state - true == enable VGA decode
9798  */
9799 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9800 {
9801         struct drm_i915_private *dev_priv = dev->dev_private;
9802         u16 gmch_ctrl;
9803
9804         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9805         if (state)
9806                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9807         else
9808                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9809         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9810         return 0;
9811 }
9812
9813 #ifdef CONFIG_DEBUG_FS
9814 #include <linux/seq_file.h>
9815
9816 struct intel_display_error_state {
9817
9818         u32 power_well_driver;
9819
9820         struct intel_cursor_error_state {
9821                 u32 control;
9822                 u32 position;
9823                 u32 base;
9824                 u32 size;
9825         } cursor[I915_MAX_PIPES];
9826
9827         struct intel_pipe_error_state {
9828                 enum transcoder cpu_transcoder;
9829                 u32 conf;
9830                 u32 source;
9831
9832                 u32 htotal;
9833                 u32 hblank;
9834                 u32 hsync;
9835                 u32 vtotal;
9836                 u32 vblank;
9837                 u32 vsync;
9838         } pipe[I915_MAX_PIPES];
9839
9840         struct intel_plane_error_state {
9841                 u32 control;
9842                 u32 stride;
9843                 u32 size;
9844                 u32 pos;
9845                 u32 addr;
9846                 u32 surface;
9847                 u32 tile_offset;
9848         } plane[I915_MAX_PIPES];
9849 };
9850
9851 struct intel_display_error_state *
9852 intel_display_capture_error_state(struct drm_device *dev)
9853 {
9854         drm_i915_private_t *dev_priv = dev->dev_private;
9855         struct intel_display_error_state *error;
9856         enum transcoder cpu_transcoder;
9857         int i;
9858
9859         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9860         if (error == NULL)
9861                 return NULL;
9862
9863         if (HAS_POWER_WELL(dev))
9864                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9865
9866         for_each_pipe(i) {
9867                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9868                 error->pipe[i].cpu_transcoder = cpu_transcoder;
9869
9870                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9871                         error->cursor[i].control = I915_READ(CURCNTR(i));
9872                         error->cursor[i].position = I915_READ(CURPOS(i));
9873                         error->cursor[i].base = I915_READ(CURBASE(i));
9874                 } else {
9875                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9876                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9877                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9878                 }
9879
9880                 error->plane[i].control = I915_READ(DSPCNTR(i));
9881                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9882                 if (INTEL_INFO(dev)->gen <= 3) {
9883                         error->plane[i].size = I915_READ(DSPSIZE(i));
9884                         error->plane[i].pos = I915_READ(DSPPOS(i));
9885                 }
9886                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9887                         error->plane[i].addr = I915_READ(DSPADDR(i));
9888                 if (INTEL_INFO(dev)->gen >= 4) {
9889                         error->plane[i].surface = I915_READ(DSPSURF(i));
9890                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9891                 }
9892
9893                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9894                 error->pipe[i].source = I915_READ(PIPESRC(i));
9895                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9896                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9897                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9898                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9899                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9900                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9901         }
9902
9903         /* In the code above we read the registers without checking if the power
9904          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9905          * prevent the next I915_WRITE from detecting it and printing an error
9906          * message. */
9907         if (HAS_POWER_WELL(dev))
9908                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9909
9910         return error;
9911 }
9912
9913 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9914
9915 void
9916 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
9917                                 struct drm_device *dev,
9918                                 struct intel_display_error_state *error)
9919 {
9920         int i;
9921
9922         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9923         if (HAS_POWER_WELL(dev))
9924                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
9925                            error->power_well_driver);
9926         for_each_pipe(i) {
9927                 err_printf(m, "Pipe [%d]:\n", i);
9928                 err_printf(m, "  CPU transcoder: %c\n",
9929                            transcoder_name(error->pipe[i].cpu_transcoder));
9930                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9931                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9932                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9933                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9934                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9935                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9936                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9937                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9938
9939                 err_printf(m, "Plane [%d]:\n", i);
9940                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9941                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9942                 if (INTEL_INFO(dev)->gen <= 3) {
9943                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9944                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
9945                 }
9946                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9947                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9948                 if (INTEL_INFO(dev)->gen >= 4) {
9949                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9950                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9951                 }
9952
9953                 err_printf(m, "Cursor [%d]:\n", i);
9954                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9955                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
9956                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9957         }
9958 }
9959 #endif