Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 void assert_pll(struct drm_i915_private *dev_priv,
 896                 enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909
 910 struct intel_shared_dpll *
 911 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 912 {
 913         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 914
 915         if (crtc->config.shared_dpll < 0)
 916                 return NULL;
 917
 918         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 919 }
 920
 921 /* For ILK+ */
 922 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 923                         struct intel_shared_dpll *pll,
 924                         bool state)
 925 {
 926         bool cur_state;
 927         struct intel_dpll_hw_state hw_state;
 928
 929         if (HAS_PCH_LPT(dev_priv->dev)) {
 930                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 931                 return;
 932         }
 933
 934         if (WARN (!pll,
 935                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 936                 return;
 937
 938         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 939         WARN(cur_state != state,
 940              "%s assertion failure (expected %s, current %s)\n",
 941              pll->name, state_string(state), state_string(cur_state));
 942 }
 943
 944 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 945                           enum pipe pipe, bool state)
 946 {
 947         int reg;
 948         u32 val;
 949         bool cur_state;
 950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 951                                                                       pipe);
 952
 953         if (HAS_DDI(dev_priv->dev)) {
 954                 /* DDI does not have a specific FDI_TX register */
 955                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 956                 val = I915_READ(reg);
 957                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 958         } else {
 959                 reg = FDI_TX_CTL(pipe);
 960                 val = I915_READ(reg);
 961                 cur_state = !!(val & FDI_TX_ENABLE);
 962         }
 963         WARN(cur_state != state,
 964              "FDI TX state assertion failure (expected %s, current %s)\n",
 965              state_string(state), state_string(cur_state));
 966 }
 967 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 968 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 969
 970 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 971                           enum pipe pipe, bool state)
 972 {
 973         int reg;
 974         u32 val;
 975         bool cur_state;
 976
 977         reg = FDI_RX_CTL(pipe);
 978         val = I915_READ(reg);
 979         cur_state = !!(val & FDI_RX_ENABLE);
 980         WARN(cur_state != state,
 981              "FDI RX state assertion failure (expected %s, current %s)\n",
 982              state_string(state), state_string(cur_state));
 983 }
 984 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 985 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 986
 987 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 988                                       enum pipe pipe)
 989 {
 990         int reg;
 991         u32 val;
 992
 993         /* ILK FDI PLL is always enabled */
 994         if (dev_priv->info->gen == 5)
 995                 return;
 996
 997         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
 998         if (HAS_DDI(dev_priv->dev))
 999                 return;
1000
1001         reg = FDI_TX_CTL(pipe);
1002         val = I915_READ(reg);
1003         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1004 }
1005
1006 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1007                        enum pipe pipe, bool state)
1008 {
1009         int reg;
1010         u32 val;
1011         bool cur_state;
1012
1013         reg = FDI_RX_CTL(pipe);
1014         val = I915_READ(reg);
1015         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1016         WARN(cur_state != state,
1017              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1018              state_string(state), state_string(cur_state));
1019 }
1020
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022                                   enum pipe pipe)
1023 {
1024         int pp_reg, lvds_reg;
1025         u32 val;
1026         enum pipe panel_pipe = PIPE_A;
1027         bool locked = true;
1028
1029         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030                 pp_reg = PCH_PP_CONTROL;
1031                 lvds_reg = PCH_LVDS;
1032         } else {
1033                 pp_reg = PP_CONTROL;
1034                 lvds_reg = LVDS;
1035         }
1036
1037         val = I915_READ(pp_reg);
1038         if (!(val & PANEL_POWER_ON) ||
1039             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040                 locked = false;
1041
1042         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043                 panel_pipe = PIPE_B;
1044
1045         WARN(panel_pipe == pipe && locked,
1046              "panel assertion failure, pipe %c regs locked\n",
1047              pipe_name(pipe));
1048 }
1049
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051                  enum pipe pipe, bool state)
1052 {
1053         int reg;
1054         u32 val;
1055         bool cur_state;
1056         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057                                                                       pipe);
1058
1059         /* if we need the pipe A quirk it must be always on */
1060         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061                 state = true;
1062
1063         if (!intel_display_power_enabled(dev_priv->dev,
1064                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1065                 cur_state = false;
1066         } else {
1067                 reg = PIPECONF(cpu_transcoder);
1068                 val = I915_READ(reg);
1069                 cur_state = !!(val & PIPECONF_ENABLE);
1070         }
1071
1072         WARN(cur_state != state,
1073              "pipe %c assertion failure (expected %s, current %s)\n",
1074              pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078                          enum plane plane, bool state)
1079 {
1080         int reg;
1081         u32 val;
1082         bool cur_state;
1083
1084         reg = DSPCNTR(plane);
1085         val = I915_READ(reg);
1086         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087         WARN(cur_state != state,
1088              "plane %c assertion failure (expected %s, current %s)\n",
1089              plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096                                    enum pipe pipe)
1097 {
1098         struct drm_device *dev = dev_priv->dev;
1099         int reg, i;
1100         u32 val;
1101         int cur_pipe;
1102
1103         /* Primary planes are fixed to pipes on gen4+ */
1104         if (INTEL_INFO(dev)->gen >= 4) {
1105                 reg = DSPCNTR(pipe);
1106                 val = I915_READ(reg);
1107                 WARN((val & DISPLAY_PLANE_ENABLE),
1108                      "plane %c assertion failure, should be disabled but not\n",
1109                      plane_name(pipe));
1110                 return;
1111         }
1112
1113         /* Need to check both planes against the pipe */
1114         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1115                 reg = DSPCNTR(i);
1116                 val = I915_READ(reg);
1117                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118                         DISPPLANE_SEL_PIPE_SHIFT;
1119                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121                      plane_name(i), pipe_name(pipe));
1122         }
1123 }
1124
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126                                     enum pipe pipe)
1127 {
1128         struct drm_device *dev = dev_priv->dev;
1129         int reg, i;
1130         u32 val;
1131
1132         if (IS_VALLEYVIEW(dev)) {
1133                 for (i = 0; i < dev_priv->num_plane; i++) {
1134                         reg = SPCNTR(pipe, i);
1135                         val = I915_READ(reg);
1136                         WARN((val & SP_ENABLE),
1137                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138                              sprite_name(pipe, i), pipe_name(pipe));
1139                 }
1140         } else if (INTEL_INFO(dev)->gen >= 7) {
1141                 reg = SPRCTL(pipe);
1142                 val = I915_READ(reg);
1143                 WARN((val & SPRITE_ENABLE),
1144                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145                      plane_name(pipe), pipe_name(pipe));
1146         } else if (INTEL_INFO(dev)->gen >= 5) {
1147                 reg = DVSCNTR(pipe);
1148                 val = I915_READ(reg);
1149                 WARN((val & DVS_ENABLE),
1150                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151                      plane_name(pipe), pipe_name(pipe));
1152         }
1153 }
1154
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156 {
1157         u32 val;
1158         bool enabled;
1159
1160         if (HAS_PCH_LPT(dev_priv->dev)) {
1161                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162                 return;
1163         }
1164
1165         val = I915_READ(PCH_DREF_CONTROL);
1166         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167                             DREF_SUPERSPREAD_SOURCE_MASK));
1168         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172                                            enum pipe pipe)
1173 {
1174         int reg;
1175         u32 val;
1176         bool enabled;
1177
1178         reg = PCH_TRANSCONF(pipe);
1179         val = I915_READ(reg);
1180         enabled = !!(val & TRANS_ENABLE);
1181         WARN(enabled,
1182              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183              pipe_name(pipe));
1184 }
1185
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187                             enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189         if ((val & DP_PORT_EN) == 0)
1190                 return false;
1191
1192         if (HAS_PCH_CPT(dev_priv->dev)) {
1193                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196                         return false;
1197         } else {
1198                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199                         return false;
1200         }
1201         return true;
1202 }
1203
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205                               enum pipe pipe, u32 val)
1206 {
1207         if ((val & SDVO_ENABLE) == 0)
1208                 return false;
1209
1210         if (HAS_PCH_CPT(dev_priv->dev)) {
1211                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212                         return false;
1213         } else {
1214                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215                         return false;
1216         }
1217         return true;
1218 }
1219
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221                               enum pipe pipe, u32 val)
1222 {
1223         if ((val & LVDS_PORT_EN) == 0)
1224                 return false;
1225
1226         if (HAS_PCH_CPT(dev_priv->dev)) {
1227                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228                         return false;
1229         } else {
1230                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231                         return false;
1232         }
1233         return true;
1234 }
1235
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237                               enum pipe pipe, u32 val)
1238 {
1239         if ((val & ADPA_DAC_ENABLE) == 0)
1240                 return false;
1241         if (HAS_PCH_CPT(dev_priv->dev)) {
1242                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243                         return false;
1244         } else {
1245                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246                         return false;
1247         }
1248         return true;
1249 }
1250
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252                                    enum pipe pipe, int reg, u32 port_sel)
1253 {
1254         u32 val = I915_READ(reg);
1255         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257              reg, pipe_name(pipe));
1258
1259         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260              && (val & DP_PIPEB_SELECT),
1261              "IBX PCH dp port still using transcoder B\n");
1262 }
1263
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265                                      enum pipe pipe, int reg)
1266 {
1267         u32 val = I915_READ(reg);
1268         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270              reg, pipe_name(pipe));
1271
1272         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273              && (val & SDVO_PIPE_B_SELECT),
1274              "IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278                                       enum pipe pipe)
1279 {
1280         int reg;
1281         u32 val;
1282
1283         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287         reg = PCH_ADPA;
1288         val = I915_READ(reg);
1289         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290              "PCH VGA enabled on transcoder %c, should be disabled\n",
1291              pipe_name(pipe));
1292
1293         reg = PCH_LVDS;
1294         val = I915_READ(reg);
1295         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1297              pipe_name(pipe));
1298
1299         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1305 {
1306         int reg;
1307         u32 val;
1308
1309         assert_pipe_disabled(dev_priv, pipe);
1310
1311         /* No really, not for ILK+ */
1312         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1313
1314         /* PLL is protected by panel, make sure we can write it */
1315         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1316                 assert_panel_unlocked(dev_priv, pipe);
1317
1318         reg = DPLL(pipe);
1319         val = I915_READ(reg);
1320         val |= DPLL_VCO_ENABLE;
1321
1322         /* We do this three times for luck */
1323         I915_WRITE(reg, val);
1324         POSTING_READ(reg);
1325         udelay(150); /* wait for warmup */
1326         I915_WRITE(reg, val);
1327         POSTING_READ(reg);
1328         udelay(150); /* wait for warmup */
1329         I915_WRITE(reg, val);
1330         POSTING_READ(reg);
1331         udelay(150); /* wait for warmup */
1332 }
1333
1334 static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val;
1338
1339         assert_pipe_disabled(dev_priv, pipe);
1340
1341         /* No really, not for ILK+ */
1342         BUG_ON(dev_priv->info->gen >= 5);
1343
1344         /* PLL is protected by panel, make sure we can write it */
1345         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1346                 assert_panel_unlocked(dev_priv, pipe);
1347
1348         reg = DPLL(pipe);
1349         val = I915_READ(reg);
1350         val |= DPLL_VCO_ENABLE;
1351
1352         /* We do this three times for luck */
1353         I915_WRITE(reg, val);
1354         POSTING_READ(reg);
1355         udelay(150); /* wait for warmup */
1356         I915_WRITE(reg, val);
1357         POSTING_READ(reg);
1358         udelay(150); /* wait for warmup */
1359         I915_WRITE(reg, val);
1360         POSTING_READ(reg);
1361         udelay(150); /* wait for warmup */
1362 }
1363
1364 /**
1365  * intel_disable_pll - disable a PLL
1366  * @dev_priv: i915 private structure
1367  * @pipe: pipe PLL to disable
1368  *
1369  * Disable the PLL for @pipe, making sure the pipe is off first.
1370  *
1371  * Note!  This is for pre-ILK only.
1372  */
1373 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1374 {
1375         int reg;
1376         u32 val;
1377
1378         /* Don't disable pipe A or pipe A PLLs if needed */
1379         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1380                 return;
1381
1382         /* Make sure the pipe isn't still relying on us */
1383         assert_pipe_disabled(dev_priv, pipe);
1384
1385         reg = DPLL(pipe);
1386         val = I915_READ(reg);
1387         val &= ~DPLL_VCO_ENABLE;
1388         I915_WRITE(reg, val);
1389         POSTING_READ(reg);
1390 }
1391
1392 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1393 {
1394         u32 port_mask;
1395
1396         if (!port)
1397                 port_mask = DPLL_PORTB_READY_MASK;
1398         else
1399                 port_mask = DPLL_PORTC_READY_MASK;
1400
1401         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1402                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1403                      'B' + port, I915_READ(DPLL(0)));
1404 }
1405
1406 /**
1407  * ironlake_enable_shared_dpll - enable PCH PLL
1408  * @dev_priv: i915 private structure
1409  * @pipe: pipe PLL to enable
1410  *
1411  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1412  * drives the transcoder clock.
1413  */
1414 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1415 {
1416         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1417         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1418
1419         /* PCH PLLs only available on ILK, SNB and IVB */
1420         BUG_ON(dev_priv->info->gen < 5);
1421         if (WARN_ON(pll == NULL))
1422                 return;
1423
1424         if (WARN_ON(pll->refcount == 0))
1425                 return;
1426
1427         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1428                       pll->name, pll->active, pll->on,
1429                       crtc->base.base.id);
1430
1431         if (pll->active++) {
1432                 WARN_ON(!pll->on);
1433                 assert_shared_dpll_enabled(dev_priv, pll);
1434                 return;
1435         }
1436         WARN_ON(pll->on);
1437
1438         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1439         pll->enable(dev_priv, pll);
1440         pll->on = true;
1441 }
1442
1443 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1444 {
1445         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1446         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1447
1448         /* PCH only available on ILK+ */
1449         BUG_ON(dev_priv->info->gen < 5);
1450         if (WARN_ON(pll == NULL))
1451                return;
1452
1453         if (WARN_ON(pll->refcount == 0))
1454                 return;
1455
1456         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1457                       pll->name, pll->active, pll->on,
1458                       crtc->base.base.id);
1459
1460         if (WARN_ON(pll->active == 0)) {
1461                 assert_shared_dpll_disabled(dev_priv, pll);
1462                 return;
1463         }
1464
1465         assert_shared_dpll_enabled(dev_priv, pll);
1466         WARN_ON(!pll->on);
1467         if (--pll->active)
1468                 return;
1469
1470         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1471         pll->disable(dev_priv, pll);
1472         pll->on = false;
1473 }
1474
1475 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1476                                            enum pipe pipe)
1477 {
1478         struct drm_device *dev = dev_priv->dev;
1479         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1481         uint32_t reg, val, pipeconf_val;
1482
1483         /* PCH only available on ILK+ */
1484         BUG_ON(dev_priv->info->gen < 5);
1485
1486         /* Make sure PCH DPLL is enabled */
1487         assert_shared_dpll_enabled(dev_priv,
1488                                    intel_crtc_to_shared_dpll(intel_crtc));
1489
1490         /* FDI must be feeding us bits for PCH ports */
1491         assert_fdi_tx_enabled(dev_priv, pipe);
1492         assert_fdi_rx_enabled(dev_priv, pipe);
1493
1494         if (HAS_PCH_CPT(dev)) {
1495                 /* Workaround: Set the timing override bit before enabling the
1496                  * pch transcoder. */
1497                 reg = TRANS_CHICKEN2(pipe);
1498                 val = I915_READ(reg);
1499                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1500                 I915_WRITE(reg, val);
1501         }
1502
1503         reg = PCH_TRANSCONF(pipe);
1504         val = I915_READ(reg);
1505         pipeconf_val = I915_READ(PIPECONF(pipe));
1506
1507         if (HAS_PCH_IBX(dev_priv->dev)) {
1508                 /*
1509                  * make the BPC in transcoder be consistent with
1510                  * that in pipeconf reg.
1511                  */
1512                 val &= ~PIPECONF_BPC_MASK;
1513                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1514         }
1515
1516         val &= ~TRANS_INTERLACE_MASK;
1517         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1518                 if (HAS_PCH_IBX(dev_priv->dev) &&
1519                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1520                         val |= TRANS_LEGACY_INTERLACED_ILK;
1521                 else
1522                         val |= TRANS_INTERLACED;
1523         else
1524                 val |= TRANS_PROGRESSIVE;
1525
1526         I915_WRITE(reg, val | TRANS_ENABLE);
1527         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1528                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1529 }
1530
1531 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1532                                       enum transcoder cpu_transcoder)
1533 {
1534         u32 val, pipeconf_val;
1535
1536         /* PCH only available on ILK+ */
1537         BUG_ON(dev_priv->info->gen < 5);
1538
1539         /* FDI must be feeding us bits for PCH ports */
1540         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1541         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1542
1543         /* Workaround: set timing override bit. */
1544         val = I915_READ(_TRANSA_CHICKEN2);
1545         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1546         I915_WRITE(_TRANSA_CHICKEN2, val);
1547
1548         val = TRANS_ENABLE;
1549         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1550
1551         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1552             PIPECONF_INTERLACED_ILK)
1553                 val |= TRANS_INTERLACED;
1554         else
1555                 val |= TRANS_PROGRESSIVE;
1556
1557         I915_WRITE(LPT_TRANSCONF, val);
1558         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1559                 DRM_ERROR("Failed to enable PCH transcoder\n");
1560 }
1561
1562 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1563                                             enum pipe pipe)
1564 {
1565         struct drm_device *dev = dev_priv->dev;
1566         uint32_t reg, val;
1567
1568         /* FDI relies on the transcoder */
1569         assert_fdi_tx_disabled(dev_priv, pipe);
1570         assert_fdi_rx_disabled(dev_priv, pipe);
1571
1572         /* Ports must be off as well */
1573         assert_pch_ports_disabled(dev_priv, pipe);
1574
1575         reg = PCH_TRANSCONF(pipe);
1576         val = I915_READ(reg);
1577         val &= ~TRANS_ENABLE;
1578         I915_WRITE(reg, val);
1579         /* wait for PCH transcoder off, transcoder state */
1580         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1581                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1582
1583         if (!HAS_PCH_IBX(dev)) {
1584                 /* Workaround: Clear the timing override chicken bit again. */
1585                 reg = TRANS_CHICKEN2(pipe);
1586                 val = I915_READ(reg);
1587                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1588                 I915_WRITE(reg, val);
1589         }
1590 }
1591
1592 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1593 {
1594         u32 val;
1595
1596         val = I915_READ(LPT_TRANSCONF);
1597         val &= ~TRANS_ENABLE;
1598         I915_WRITE(LPT_TRANSCONF, val);
1599         /* wait for PCH transcoder off, transcoder state */
1600         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1601                 DRM_ERROR("Failed to disable PCH transcoder\n");
1602
1603         /* Workaround: clear timing override bit. */
1604         val = I915_READ(_TRANSA_CHICKEN2);
1605         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1606         I915_WRITE(_TRANSA_CHICKEN2, val);
1607 }
1608
1609 /**
1610  * intel_enable_pipe - enable a pipe, asserting requirements
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe to enable
1613  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1614  *
1615  * Enable @pipe, making sure that various hardware specific requirements
1616  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1617  *
1618  * @pipe should be %PIPE_A or %PIPE_B.
1619  *
1620  * Will wait until the pipe is actually running (i.e. first vblank) before
1621  * returning.
1622  */
1623 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1624                               bool pch_port)
1625 {
1626         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1627                                                                       pipe);
1628         enum pipe pch_transcoder;
1629         int reg;
1630         u32 val;
1631
1632         assert_planes_disabled(dev_priv, pipe);
1633         assert_sprites_disabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_LPT(dev_priv->dev))
1636                 pch_transcoder = TRANSCODER_A;
1637         else
1638                 pch_transcoder = pipe;
1639
1640         /*
1641          * A pipe without a PLL won't actually be able to drive bits from
1642          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1643          * need the check.
1644          */
1645         if (!HAS_PCH_SPLIT(dev_priv->dev))
1646                 assert_pll_enabled(dev_priv, pipe);
1647         else {
1648                 if (pch_port) {
1649                         /* if driving the PCH, we need FDI enabled */
1650                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1651                         assert_fdi_tx_pll_enabled(dev_priv,
1652                                                   (enum pipe) cpu_transcoder);
1653                 }
1654                 /* FIXME: assert CPU port conditions for SNB+ */
1655         }
1656
1657         reg = PIPECONF(cpu_transcoder);
1658         val = I915_READ(reg);
1659         if (val & PIPECONF_ENABLE)
1660                 return;
1661
1662         I915_WRITE(reg, val | PIPECONF_ENABLE);
1663         intel_wait_for_vblank(dev_priv->dev, pipe);
1664 }
1665
1666 /**
1667  * intel_disable_pipe - disable a pipe, asserting requirements
1668  * @dev_priv: i915 private structure
1669  * @pipe: pipe to disable
1670  *
1671  * Disable @pipe, making sure that various hardware specific requirements
1672  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1673  *
1674  * @pipe should be %PIPE_A or %PIPE_B.
1675  *
1676  * Will wait until the pipe has shut down before returning.
1677  */
1678 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1679                                enum pipe pipe)
1680 {
1681         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1682                                                                       pipe);
1683         int reg;
1684         u32 val;
1685
1686         /*
1687          * Make sure planes won't keep trying to pump pixels to us,
1688          * or we might hang the display.
1689          */
1690         assert_planes_disabled(dev_priv, pipe);
1691         assert_sprites_disabled(dev_priv, pipe);
1692
1693         /* Don't disable pipe A or pipe A PLLs if needed */
1694         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1695                 return;
1696
1697         reg = PIPECONF(cpu_transcoder);
1698         val = I915_READ(reg);
1699         if ((val & PIPECONF_ENABLE) == 0)
1700                 return;
1701
1702         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1703         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1704 }
1705
1706 /*
1707  * Plane regs are double buffered, going from enabled->disabled needs a
1708  * trigger in order to latch.  The display address reg provides this.
1709  */
1710 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1711                                       enum plane plane)
1712 {
1713         if (dev_priv->info->gen >= 4)
1714                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1715         else
1716                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1717 }
1718
1719 /**
1720  * intel_enable_plane - enable a display plane on a given pipe
1721  * @dev_priv: i915 private structure
1722  * @plane: plane to enable
1723  * @pipe: pipe being fed
1724  *
1725  * Enable @plane on @pipe, making sure that @pipe is running first.
1726  */
1727 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1728                                enum plane plane, enum pipe pipe)
1729 {
1730         int reg;
1731         u32 val;
1732
1733         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1734         assert_pipe_enabled(dev_priv, pipe);
1735
1736         reg = DSPCNTR(plane);
1737         val = I915_READ(reg);
1738         if (val & DISPLAY_PLANE_ENABLE)
1739                 return;
1740
1741         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1742         intel_flush_display_plane(dev_priv, plane);
1743         intel_wait_for_vblank(dev_priv->dev, pipe);
1744 }
1745
1746 /**
1747  * intel_disable_plane - disable a display plane
1748  * @dev_priv: i915 private structure
1749  * @plane: plane to disable
1750  * @pipe: pipe consuming the data
1751  *
1752  * Disable @plane; should be an independent operation.
1753  */
1754 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1755                                 enum plane plane, enum pipe pipe)
1756 {
1757         int reg;
1758         u32 val;
1759
1760         reg = DSPCNTR(plane);
1761         val = I915_READ(reg);
1762         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1763                 return;
1764
1765         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1766         intel_flush_display_plane(dev_priv, plane);
1767         intel_wait_for_vblank(dev_priv->dev, pipe);
1768 }
1769
1770 static bool need_vtd_wa(struct drm_device *dev)
1771 {
1772 #ifdef CONFIG_INTEL_IOMMU
1773         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1774                 return true;
1775 #endif
1776         return false;
1777 }
1778
1779 int
1780 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1781                            struct drm_i915_gem_object *obj,
1782                            struct intel_ring_buffer *pipelined)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785         u32 alignment;
1786         int ret;
1787
1788         switch (obj->tiling_mode) {
1789         case I915_TILING_NONE:
1790                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1791                         alignment = 128 * 1024;
1792                 else if (INTEL_INFO(dev)->gen >= 4)
1793                         alignment = 4 * 1024;
1794                 else
1795                         alignment = 64 * 1024;
1796                 break;
1797         case I915_TILING_X:
1798                 /* pin() will align the object as required by fence */
1799                 alignment = 0;
1800                 break;
1801         case I915_TILING_Y:
1802                 /* Despite that we check this in framebuffer_init userspace can
1803                  * screw us over and change the tiling after the fact. Only
1804                  * pinned buffers can't change their tiling. */
1805                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1806                 return -EINVAL;
1807         default:
1808                 BUG();
1809         }
1810
1811         /* Note that the w/a also requires 64 PTE of padding following the
1812          * bo. We currently fill all unused PTE with the shadow page and so
1813          * we should always have valid PTE following the scanout preventing
1814          * the VT-d warning.
1815          */
1816         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1817                 alignment = 256 * 1024;
1818
1819         dev_priv->mm.interruptible = false;
1820         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1821         if (ret)
1822                 goto err_interruptible;
1823
1824         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1825          * fence, whereas 965+ only requires a fence if using
1826          * framebuffer compression.  For simplicity, we always install
1827          * a fence as the cost is not that onerous.
1828          */
1829         ret = i915_gem_object_get_fence(obj);
1830         if (ret)
1831                 goto err_unpin;
1832
1833         i915_gem_object_pin_fence(obj);
1834
1835         dev_priv->mm.interruptible = true;
1836         return 0;
1837
1838 err_unpin:
1839         i915_gem_object_unpin(obj);
1840 err_interruptible:
1841         dev_priv->mm.interruptible = true;
1842         return ret;
1843 }
1844
1845 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1846 {
1847         i915_gem_object_unpin_fence(obj);
1848         i915_gem_object_unpin(obj);
1849 }
1850
1851 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1852  * is assumed to be a power-of-two. */
1853 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1854                                              unsigned int tiling_mode,
1855                                              unsigned int cpp,
1856                                              unsigned int pitch)
1857 {
1858         if (tiling_mode != I915_TILING_NONE) {
1859                 unsigned int tile_rows, tiles;
1860
1861                 tile_rows = *y / 8;
1862                 *y %= 8;
1863
1864                 tiles = *x / (512/cpp);
1865                 *x %= 512/cpp;
1866
1867                 return tile_rows * pitch * 8 + tiles * 4096;
1868         } else {
1869                 unsigned int offset;
1870
1871                 offset = *y * pitch + *x * cpp;
1872                 *y = 0;
1873                 *x = (offset & 4095) / cpp;
1874                 return offset & -4096;
1875         }
1876 }
1877
1878 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1879                              int x, int y)
1880 {
1881         struct drm_device *dev = crtc->dev;
1882         struct drm_i915_private *dev_priv = dev->dev_private;
1883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1884         struct intel_framebuffer *intel_fb;
1885         struct drm_i915_gem_object *obj;
1886         int plane = intel_crtc->plane;
1887         unsigned long linear_offset;
1888         u32 dspcntr;
1889         u32 reg;
1890
1891         switch (plane) {
1892         case 0:
1893         case 1:
1894                 break;
1895         default:
1896                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1897                 return -EINVAL;
1898         }
1899
1900         intel_fb = to_intel_framebuffer(fb);
1901         obj = intel_fb->obj;
1902
1903         reg = DSPCNTR(plane);
1904         dspcntr = I915_READ(reg);
1905         /* Mask out pixel format bits in case we change it */
1906         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1907         switch (fb->pixel_format) {
1908         case DRM_FORMAT_C8:
1909                 dspcntr |= DISPPLANE_8BPP;
1910                 break;
1911         case DRM_FORMAT_XRGB1555:
1912         case DRM_FORMAT_ARGB1555:
1913                 dspcntr |= DISPPLANE_BGRX555;
1914                 break;
1915         case DRM_FORMAT_RGB565:
1916                 dspcntr |= DISPPLANE_BGRX565;
1917                 break;
1918         case DRM_FORMAT_XRGB8888:
1919         case DRM_FORMAT_ARGB8888:
1920                 dspcntr |= DISPPLANE_BGRX888;
1921                 break;
1922         case DRM_FORMAT_XBGR8888:
1923         case DRM_FORMAT_ABGR8888:
1924                 dspcntr |= DISPPLANE_RGBX888;
1925                 break;
1926         case DRM_FORMAT_XRGB2101010:
1927         case DRM_FORMAT_ARGB2101010:
1928                 dspcntr |= DISPPLANE_BGRX101010;
1929                 break;
1930         case DRM_FORMAT_XBGR2101010:
1931         case DRM_FORMAT_ABGR2101010:
1932                 dspcntr |= DISPPLANE_RGBX101010;
1933                 break;
1934         default:
1935                 BUG();
1936         }
1937
1938         if (INTEL_INFO(dev)->gen >= 4) {
1939                 if (obj->tiling_mode != I915_TILING_NONE)
1940                         dspcntr |= DISPPLANE_TILED;
1941                 else
1942                         dspcntr &= ~DISPPLANE_TILED;
1943         }
1944
1945         if (IS_G4X(dev))
1946                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1947
1948         I915_WRITE(reg, dspcntr);
1949
1950         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1951
1952         if (INTEL_INFO(dev)->gen >= 4) {
1953                 intel_crtc->dspaddr_offset =
1954                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1955                                                        fb->bits_per_pixel / 8,
1956                                                        fb->pitches[0]);
1957                 linear_offset -= intel_crtc->dspaddr_offset;
1958         } else {
1959                 intel_crtc->dspaddr_offset = linear_offset;
1960         }
1961
1962         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1963                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1964         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1965         if (INTEL_INFO(dev)->gen >= 4) {
1966                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1967                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1968                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1969                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1970         } else
1971                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1972         POSTING_READ(reg);
1973
1974         return 0;
1975 }
1976
1977 static int ironlake_update_plane(struct drm_crtc *crtc,
1978                                  struct drm_framebuffer *fb, int x, int y)
1979 {
1980         struct drm_device *dev = crtc->dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         struct intel_framebuffer *intel_fb;
1984         struct drm_i915_gem_object *obj;
1985         int plane = intel_crtc->plane;
1986         unsigned long linear_offset;
1987         u32 dspcntr;
1988         u32 reg;
1989
1990         switch (plane) {
1991         case 0:
1992         case 1:
1993         case 2:
1994                 break;
1995         default:
1996                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1997                 return -EINVAL;
1998         }
1999
2000         intel_fb = to_intel_framebuffer(fb);
2001         obj = intel_fb->obj;
2002
2003         reg = DSPCNTR(plane);
2004         dspcntr = I915_READ(reg);
2005         /* Mask out pixel format bits in case we change it */
2006         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2007         switch (fb->pixel_format) {
2008         case DRM_FORMAT_C8:
2009                 dspcntr |= DISPPLANE_8BPP;
2010                 break;
2011         case DRM_FORMAT_RGB565:
2012                 dspcntr |= DISPPLANE_BGRX565;
2013                 break;
2014         case DRM_FORMAT_XRGB8888:
2015         case DRM_FORMAT_ARGB8888:
2016                 dspcntr |= DISPPLANE_BGRX888;
2017                 break;
2018         case DRM_FORMAT_XBGR8888:
2019         case DRM_FORMAT_ABGR8888:
2020                 dspcntr |= DISPPLANE_RGBX888;
2021                 break;
2022         case DRM_FORMAT_XRGB2101010:
2023         case DRM_FORMAT_ARGB2101010:
2024                 dspcntr |= DISPPLANE_BGRX101010;
2025                 break;
2026         case DRM_FORMAT_XBGR2101010:
2027         case DRM_FORMAT_ABGR2101010:
2028                 dspcntr |= DISPPLANE_RGBX101010;
2029                 break;
2030         default:
2031                 BUG();
2032         }
2033
2034         if (obj->tiling_mode != I915_TILING_NONE)
2035                 dspcntr |= DISPPLANE_TILED;
2036         else
2037                 dspcntr &= ~DISPPLANE_TILED;
2038
2039         /* must disable */
2040         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2041
2042         I915_WRITE(reg, dspcntr);
2043
2044         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2045         intel_crtc->dspaddr_offset =
2046                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2047                                                fb->bits_per_pixel / 8,
2048                                                fb->pitches[0]);
2049         linear_offset -= intel_crtc->dspaddr_offset;
2050
2051         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2052                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2053         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2054         I915_MODIFY_DISPBASE(DSPSURF(plane),
2055                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2056         if (IS_HASWELL(dev)) {
2057                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2058         } else {
2059                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2060                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2061         }
2062         POSTING_READ(reg);
2063
2064         return 0;
2065 }
2066
2067 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2068 static int
2069 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2070                            int x, int y, enum mode_set_atomic state)
2071 {
2072         struct drm_device *dev = crtc->dev;
2073         struct drm_i915_private *dev_priv = dev->dev_private;
2074
2075         if (dev_priv->display.disable_fbc)
2076                 dev_priv->display.disable_fbc(dev);
2077         intel_increase_pllclock(crtc);
2078
2079         return dev_priv->display.update_plane(crtc, fb, x, y);
2080 }
2081
2082 void intel_display_handle_reset(struct drm_device *dev)
2083 {
2084         struct drm_i915_private *dev_priv = dev->dev_private;
2085         struct drm_crtc *crtc;
2086
2087         /*
2088          * Flips in the rings have been nuked by the reset,
2089          * so complete all pending flips so that user space
2090          * will get its events and not get stuck.
2091          *
2092          * Also update the base address of all primary
2093          * planes to the the last fb to make sure we're
2094          * showing the correct fb after a reset.
2095          *
2096          * Need to make two loops over the crtcs so that we
2097          * don't try to grab a crtc mutex before the
2098          * pending_flip_queue really got woken up.
2099          */
2100
2101         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2102                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103                 enum plane plane = intel_crtc->plane;
2104
2105                 intel_prepare_page_flip(dev, plane);
2106                 intel_finish_page_flip_plane(dev, plane);
2107         }
2108
2109         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2110                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112                 mutex_lock(&crtc->mutex);
2113                 if (intel_crtc->active)
2114                         dev_priv->display.update_plane(crtc, crtc->fb,
2115                                                        crtc->x, crtc->y);
2116                 mutex_unlock(&crtc->mutex);
2117         }
2118 }
2119
2120 static int
2121 intel_finish_fb(struct drm_framebuffer *old_fb)
2122 {
2123         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2124         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2125         bool was_interruptible = dev_priv->mm.interruptible;
2126         int ret;
2127
2128         /* Big Hammer, we also need to ensure that any pending
2129          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2130          * current scanout is retired before unpinning the old
2131          * framebuffer.
2132          *
2133          * This should only fail upon a hung GPU, in which case we
2134          * can safely continue.
2135          */
2136         dev_priv->mm.interruptible = false;
2137         ret = i915_gem_object_finish_gpu(obj);
2138         dev_priv->mm.interruptible = was_interruptible;
2139
2140         return ret;
2141 }
2142
2143 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2144 {
2145         struct drm_device *dev = crtc->dev;
2146         struct drm_i915_master_private *master_priv;
2147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2148
2149         if (!dev->primary->master)
2150                 return;
2151
2152         master_priv = dev->primary->master->driver_priv;
2153         if (!master_priv->sarea_priv)
2154                 return;
2155
2156         switch (intel_crtc->pipe) {
2157         case 0:
2158                 master_priv->sarea_priv->pipeA_x = x;
2159                 master_priv->sarea_priv->pipeA_y = y;
2160                 break;
2161         case 1:
2162                 master_priv->sarea_priv->pipeB_x = x;
2163                 master_priv->sarea_priv->pipeB_y = y;
2164                 break;
2165         default:
2166                 break;
2167         }
2168 }
2169
2170 static int
2171 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2172                     struct drm_framebuffer *fb)
2173 {
2174         struct drm_device *dev = crtc->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2177         struct drm_framebuffer *old_fb;
2178         int ret;
2179
2180         /* no fb bound */
2181         if (!fb) {
2182                 DRM_ERROR("No FB bound\n");
2183                 return 0;
2184         }
2185
2186         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2187                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2188                           plane_name(intel_crtc->plane),
2189                           INTEL_INFO(dev)->num_pipes);
2190                 return -EINVAL;
2191         }
2192
2193         mutex_lock(&dev->struct_mutex);
2194         ret = intel_pin_and_fence_fb_obj(dev,
2195                                          to_intel_framebuffer(fb)->obj,
2196                                          NULL);
2197         if (ret != 0) {
2198                 mutex_unlock(&dev->struct_mutex);
2199                 DRM_ERROR("pin & fence failed\n");
2200                 return ret;
2201         }
2202
2203         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2204         if (ret) {
2205                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2206                 mutex_unlock(&dev->struct_mutex);
2207                 DRM_ERROR("failed to update base address\n");
2208                 return ret;
2209         }
2210
2211         old_fb = crtc->fb;
2212         crtc->fb = fb;
2213         crtc->x = x;
2214         crtc->y = y;
2215
2216         if (old_fb) {
2217                 if (intel_crtc->active && old_fb != fb)
2218                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2219                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2220         }
2221
2222         intel_update_fbc(dev);
2223         mutex_unlock(&dev->struct_mutex);
2224
2225         intel_crtc_update_sarea_pos(crtc, x, y);
2226
2227         return 0;
2228 }
2229
2230 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2231 {
2232         struct drm_device *dev = crtc->dev;
2233         struct drm_i915_private *dev_priv = dev->dev_private;
2234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235         int pipe = intel_crtc->pipe;
2236         u32 reg, temp;
2237
2238         /* enable normal train */
2239         reg = FDI_TX_CTL(pipe);
2240         temp = I915_READ(reg);
2241         if (IS_IVYBRIDGE(dev)) {
2242                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2243                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2244         } else {
2245                 temp &= ~FDI_LINK_TRAIN_NONE;
2246                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2247         }
2248         I915_WRITE(reg, temp);
2249
2250         reg = FDI_RX_CTL(pipe);
2251         temp = I915_READ(reg);
2252         if (HAS_PCH_CPT(dev)) {
2253                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2254                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2255         } else {
2256                 temp &= ~FDI_LINK_TRAIN_NONE;
2257                 temp |= FDI_LINK_TRAIN_NONE;
2258         }
2259         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2260
2261         /* wait one idle pattern time */
2262         POSTING_READ(reg);
2263         udelay(1000);
2264
2265         /* IVB wants error correction enabled */
2266         if (IS_IVYBRIDGE(dev))
2267                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2268                            FDI_FE_ERRC_ENABLE);
2269 }
2270
2271 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2272 {
2273         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2274 }
2275
2276 static void ivb_modeset_global_resources(struct drm_device *dev)
2277 {
2278         struct drm_i915_private *dev_priv = dev->dev_private;
2279         struct intel_crtc *pipe_B_crtc =
2280                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2281         struct intel_crtc *pipe_C_crtc =
2282                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2283         uint32_t temp;
2284
2285         /*
2286          * When everything is off disable fdi C so that we could enable fdi B
2287          * with all lanes. Note that we don't care about enabled pipes without
2288          * an enabled pch encoder.
2289          */
2290         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2291             !pipe_has_enabled_pch(pipe_C_crtc)) {
2292                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2293                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2294
2295                 temp = I915_READ(SOUTH_CHICKEN1);
2296                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2297                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2298                 I915_WRITE(SOUTH_CHICKEN1, temp);
2299         }
2300 }
2301
2302 /* The FDI link training functions for ILK/Ibexpeak. */
2303 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2304 {
2305         struct drm_device *dev = crtc->dev;
2306         struct drm_i915_private *dev_priv = dev->dev_private;
2307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2308         int pipe = intel_crtc->pipe;
2309         int plane = intel_crtc->plane;
2310         u32 reg, temp, tries;
2311
2312         /* FDI needs bits from pipe & plane first */
2313         assert_pipe_enabled(dev_priv, pipe);
2314         assert_plane_enabled(dev_priv, plane);
2315
2316         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2317            for train result */
2318         reg = FDI_RX_IMR(pipe);
2319         temp = I915_READ(reg);
2320         temp &= ~FDI_RX_SYMBOL_LOCK;
2321         temp &= ~FDI_RX_BIT_LOCK;
2322         I915_WRITE(reg, temp);
2323         I915_READ(reg);
2324         udelay(150);
2325
2326         /* enable CPU FDI TX and PCH FDI RX */
2327         reg = FDI_TX_CTL(pipe);
2328         temp = I915_READ(reg);
2329         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2330         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2331         temp &= ~FDI_LINK_TRAIN_NONE;
2332         temp |= FDI_LINK_TRAIN_PATTERN_1;
2333         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2334
2335         reg = FDI_RX_CTL(pipe);
2336         temp = I915_READ(reg);
2337         temp &= ~FDI_LINK_TRAIN_NONE;
2338         temp |= FDI_LINK_TRAIN_PATTERN_1;
2339         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2340
2341         POSTING_READ(reg);
2342         udelay(150);
2343
2344         /* Ironlake workaround, enable clock pointer after FDI enable*/
2345         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2346         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2347                    FDI_RX_PHASE_SYNC_POINTER_EN);
2348
2349         reg = FDI_RX_IIR(pipe);
2350         for (tries = 0; tries < 5; tries++) {
2351                 temp = I915_READ(reg);
2352                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2353
2354                 if ((temp & FDI_RX_BIT_LOCK)) {
2355                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2356                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2357                         break;
2358                 }
2359         }
2360         if (tries == 5)
2361                 DRM_ERROR("FDI train 1 fail!\n");
2362
2363         /* Train 2 */
2364         reg = FDI_TX_CTL(pipe);
2365         temp = I915_READ(reg);
2366         temp &= ~FDI_LINK_TRAIN_NONE;
2367         temp |= FDI_LINK_TRAIN_PATTERN_2;
2368         I915_WRITE(reg, temp);
2369
2370         reg = FDI_RX_CTL(pipe);
2371         temp = I915_READ(reg);
2372         temp &= ~FDI_LINK_TRAIN_NONE;
2373         temp |= FDI_LINK_TRAIN_PATTERN_2;
2374         I915_WRITE(reg, temp);
2375
2376         POSTING_READ(reg);
2377         udelay(150);
2378
2379         reg = FDI_RX_IIR(pipe);
2380         for (tries = 0; tries < 5; tries++) {
2381                 temp = I915_READ(reg);
2382                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2383
2384                 if (temp & FDI_RX_SYMBOL_LOCK) {
2385                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2386                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2387                         break;
2388                 }
2389         }
2390         if (tries == 5)
2391                 DRM_ERROR("FDI train 2 fail!\n");
2392
2393         DRM_DEBUG_KMS("FDI train done\n");
2394
2395 }
2396
2397 static const int snb_b_fdi_train_param[] = {
2398         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2399         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2400         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2401         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2402 };
2403
2404 /* The FDI link training functions for SNB/Cougarpoint. */
2405 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2406 {
2407         struct drm_device *dev = crtc->dev;
2408         struct drm_i915_private *dev_priv = dev->dev_private;
2409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410         int pipe = intel_crtc->pipe;
2411         u32 reg, temp, i, retry;
2412
2413         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2414            for train result */
2415         reg = FDI_RX_IMR(pipe);
2416         temp = I915_READ(reg);
2417         temp &= ~FDI_RX_SYMBOL_LOCK;
2418         temp &= ~FDI_RX_BIT_LOCK;
2419         I915_WRITE(reg, temp);
2420
2421         POSTING_READ(reg);
2422         udelay(150);
2423
2424         /* enable CPU FDI TX and PCH FDI RX */
2425         reg = FDI_TX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2428         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2429         temp &= ~FDI_LINK_TRAIN_NONE;
2430         temp |= FDI_LINK_TRAIN_PATTERN_1;
2431         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2432         /* SNB-B */
2433         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         I915_WRITE(FDI_RX_MISC(pipe),
2437                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2438
2439         reg = FDI_RX_CTL(pipe);
2440         temp = I915_READ(reg);
2441         if (HAS_PCH_CPT(dev)) {
2442                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2444         } else {
2445                 temp &= ~FDI_LINK_TRAIN_NONE;
2446                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447         }
2448         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2449
2450         POSTING_READ(reg);
2451         udelay(150);
2452
2453         for (i = 0; i < 4; i++) {
2454                 reg = FDI_TX_CTL(pipe);
2455                 temp = I915_READ(reg);
2456                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2457                 temp |= snb_b_fdi_train_param[i];
2458                 I915_WRITE(reg, temp);
2459
2460                 POSTING_READ(reg);
2461                 udelay(500);
2462
2463                 for (retry = 0; retry < 5; retry++) {
2464                         reg = FDI_RX_IIR(pipe);
2465                         temp = I915_READ(reg);
2466                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2467                         if (temp & FDI_RX_BIT_LOCK) {
2468                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2469                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2470                                 break;
2471                         }
2472                         udelay(50);
2473                 }
2474                 if (retry < 5)
2475                         break;
2476         }
2477         if (i == 4)
2478                 DRM_ERROR("FDI train 1 fail!\n");
2479
2480         /* Train 2 */
2481         reg = FDI_TX_CTL(pipe);
2482         temp = I915_READ(reg);
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_2;
2485         if (IS_GEN6(dev)) {
2486                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487                 /* SNB-B */
2488                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2489         }
2490         I915_WRITE(reg, temp);
2491
2492         reg = FDI_RX_CTL(pipe);
2493         temp = I915_READ(reg);
2494         if (HAS_PCH_CPT(dev)) {
2495                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2496                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2497         } else {
2498                 temp &= ~FDI_LINK_TRAIN_NONE;
2499                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2500         }
2501         I915_WRITE(reg, temp);
2502
2503         POSTING_READ(reg);
2504         udelay(150);
2505
2506         for (i = 0; i < 4; i++) {
2507                 reg = FDI_TX_CTL(pipe);
2508                 temp = I915_READ(reg);
2509                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2510                 temp |= snb_b_fdi_train_param[i];
2511                 I915_WRITE(reg, temp);
2512
2513                 POSTING_READ(reg);
2514                 udelay(500);
2515
2516                 for (retry = 0; retry < 5; retry++) {
2517                         reg = FDI_RX_IIR(pipe);
2518                         temp = I915_READ(reg);
2519                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2520                         if (temp & FDI_RX_SYMBOL_LOCK) {
2521                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2522                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2523                                 break;
2524                         }
2525                         udelay(50);
2526                 }
2527                 if (retry < 5)
2528                         break;
2529         }
2530         if (i == 4)
2531                 DRM_ERROR("FDI train 2 fail!\n");
2532
2533         DRM_DEBUG_KMS("FDI train done.\n");
2534 }
2535
2536 /* Manual link training for Ivy Bridge A0 parts */
2537 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2538 {
2539         struct drm_device *dev = crtc->dev;
2540         struct drm_i915_private *dev_priv = dev->dev_private;
2541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2542         int pipe = intel_crtc->pipe;
2543         u32 reg, temp, i;
2544
2545         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2546            for train result */
2547         reg = FDI_RX_IMR(pipe);
2548         temp = I915_READ(reg);
2549         temp &= ~FDI_RX_SYMBOL_LOCK;
2550         temp &= ~FDI_RX_BIT_LOCK;
2551         I915_WRITE(reg, temp);
2552
2553         POSTING_READ(reg);
2554         udelay(150);
2555
2556         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2557                       I915_READ(FDI_RX_IIR(pipe)));
2558
2559         /* enable CPU FDI TX and PCH FDI RX */
2560         reg = FDI_TX_CTL(pipe);
2561         temp = I915_READ(reg);
2562         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2563         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2564         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2565         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2566         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2568         temp |= FDI_COMPOSITE_SYNC;
2569         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2570
2571         I915_WRITE(FDI_RX_MISC(pipe),
2572                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2573
2574         reg = FDI_RX_CTL(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~FDI_LINK_TRAIN_AUTO;
2577         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2578         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2579         temp |= FDI_COMPOSITE_SYNC;
2580         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2581
2582         POSTING_READ(reg);
2583         udelay(150);
2584
2585         for (i = 0; i < 4; i++) {
2586                 reg = FDI_TX_CTL(pipe);
2587                 temp = I915_READ(reg);
2588                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589                 temp |= snb_b_fdi_train_param[i];
2590                 I915_WRITE(reg, temp);
2591
2592                 POSTING_READ(reg);
2593                 udelay(500);
2594
2595                 reg = FDI_RX_IIR(pipe);
2596                 temp = I915_READ(reg);
2597                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2598
2599                 if (temp & FDI_RX_BIT_LOCK ||
2600                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2601                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2602                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2603                         break;
2604                 }
2605         }
2606         if (i == 4)
2607                 DRM_ERROR("FDI train 1 fail!\n");
2608
2609         /* Train 2 */
2610         reg = FDI_TX_CTL(pipe);
2611         temp = I915_READ(reg);
2612         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2613         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2614         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2616         I915_WRITE(reg, temp);
2617
2618         reg = FDI_RX_CTL(pipe);
2619         temp = I915_READ(reg);
2620         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2621         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2622         I915_WRITE(reg, temp);
2623
2624         POSTING_READ(reg);
2625         udelay(150);
2626
2627         for (i = 0; i < 4; i++) {
2628                 reg = FDI_TX_CTL(pipe);
2629                 temp = I915_READ(reg);
2630                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631                 temp |= snb_b_fdi_train_param[i];
2632                 I915_WRITE(reg, temp);
2633
2634                 POSTING_READ(reg);
2635                 udelay(500);
2636
2637                 reg = FDI_RX_IIR(pipe);
2638                 temp = I915_READ(reg);
2639                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2640
2641                 if (temp & FDI_RX_SYMBOL_LOCK) {
2642                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2643                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2644                         break;
2645                 }
2646         }
2647         if (i == 4)
2648                 DRM_ERROR("FDI train 2 fail!\n");
2649
2650         DRM_DEBUG_KMS("FDI train done.\n");
2651 }
2652
2653 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2654 {
2655         struct drm_device *dev = intel_crtc->base.dev;
2656         struct drm_i915_private *dev_priv = dev->dev_private;
2657         int pipe = intel_crtc->pipe;
2658         u32 reg, temp;
2659
2660
2661         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2662         reg = FDI_RX_CTL(pipe);
2663         temp = I915_READ(reg);
2664         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2665         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2666         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2667         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2668
2669         POSTING_READ(reg);
2670         udelay(200);
2671
2672         /* Switch from Rawclk to PCDclk */
2673         temp = I915_READ(reg);
2674         I915_WRITE(reg, temp | FDI_PCDCLK);
2675
2676         POSTING_READ(reg);
2677         udelay(200);
2678
2679         /* Enable CPU FDI TX PLL, always on for Ironlake */
2680         reg = FDI_TX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2683                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2684
2685                 POSTING_READ(reg);
2686                 udelay(100);
2687         }
2688 }
2689
2690 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2691 {
2692         struct drm_device *dev = intel_crtc->base.dev;
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         int pipe = intel_crtc->pipe;
2695         u32 reg, temp;
2696
2697         /* Switch from PCDclk to Rawclk */
2698         reg = FDI_RX_CTL(pipe);
2699         temp = I915_READ(reg);
2700         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2701
2702         /* Disable CPU FDI TX PLL */
2703         reg = FDI_TX_CTL(pipe);
2704         temp = I915_READ(reg);
2705         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2706
2707         POSTING_READ(reg);
2708         udelay(100);
2709
2710         reg = FDI_RX_CTL(pipe);
2711         temp = I915_READ(reg);
2712         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2713
2714         /* Wait for the clocks to turn off. */
2715         POSTING_READ(reg);
2716         udelay(100);
2717 }
2718
2719 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2720 {
2721         struct drm_device *dev = crtc->dev;
2722         struct drm_i915_private *dev_priv = dev->dev_private;
2723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2724         int pipe = intel_crtc->pipe;
2725         u32 reg, temp;
2726
2727         /* disable CPU FDI tx and PCH FDI rx */
2728         reg = FDI_TX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2731         POSTING_READ(reg);
2732
2733         reg = FDI_RX_CTL(pipe);
2734         temp = I915_READ(reg);
2735         temp &= ~(0x7 << 16);
2736         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2737         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2738
2739         POSTING_READ(reg);
2740         udelay(100);
2741
2742         /* Ironlake workaround, disable clock pointer after downing FDI */
2743         if (HAS_PCH_IBX(dev)) {
2744                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2745         }
2746
2747         /* still set train pattern 1 */
2748         reg = FDI_TX_CTL(pipe);
2749         temp = I915_READ(reg);
2750         temp &= ~FDI_LINK_TRAIN_NONE;
2751         temp |= FDI_LINK_TRAIN_PATTERN_1;
2752         I915_WRITE(reg, temp);
2753
2754         reg = FDI_RX_CTL(pipe);
2755         temp = I915_READ(reg);
2756         if (HAS_PCH_CPT(dev)) {
2757                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2758                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2759         } else {
2760                 temp &= ~FDI_LINK_TRAIN_NONE;
2761                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2762         }
2763         /* BPC in FDI rx is consistent with that in PIPECONF */
2764         temp &= ~(0x07 << 16);
2765         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2766         I915_WRITE(reg, temp);
2767
2768         POSTING_READ(reg);
2769         udelay(100);
2770 }
2771
2772 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2773 {
2774         struct drm_device *dev = crtc->dev;
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777         unsigned long flags;
2778         bool pending;
2779
2780         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2781             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2782                 return false;
2783
2784         spin_lock_irqsave(&dev->event_lock, flags);
2785         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2786         spin_unlock_irqrestore(&dev->event_lock, flags);
2787
2788         return pending;
2789 }
2790
2791 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2792 {
2793         struct drm_device *dev = crtc->dev;
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795
2796         if (crtc->fb == NULL)
2797                 return;
2798
2799         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2800
2801         wait_event(dev_priv->pending_flip_queue,
2802                    !intel_crtc_has_pending_flip(crtc));
2803
2804         mutex_lock(&dev->struct_mutex);
2805         intel_finish_fb(crtc->fb);
2806         mutex_unlock(&dev->struct_mutex);
2807 }
2808
2809 /* Program iCLKIP clock to the desired frequency */
2810 static void lpt_program_iclkip(struct drm_crtc *crtc)
2811 {
2812         struct drm_device *dev = crtc->dev;
2813         struct drm_i915_private *dev_priv = dev->dev_private;
2814         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2815         u32 temp;
2816
2817         mutex_lock(&dev_priv->dpio_lock);
2818
2819         /* It is necessary to ungate the pixclk gate prior to programming
2820          * the divisors, and gate it back when it is done.
2821          */
2822         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2823
2824         /* Disable SSCCTL */
2825         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2826                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2827                                 SBI_SSCCTL_DISABLE,
2828                         SBI_ICLK);
2829
2830         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2831         if (crtc->mode.clock == 20000) {
2832                 auxdiv = 1;
2833                 divsel = 0x41;
2834                 phaseinc = 0x20;
2835         } else {
2836                 /* The iCLK virtual clock root frequency is in MHz,
2837                  * but the crtc->mode.clock in in KHz. To get the divisors,
2838                  * it is necessary to divide one by another, so we
2839                  * convert the virtual clock precision to KHz here for higher
2840                  * precision.
2841                  */
2842                 u32 iclk_virtual_root_freq = 172800 * 1000;
2843                 u32 iclk_pi_range = 64;
2844                 u32 desired_divisor, msb_divisor_value, pi_value;
2845
2846                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2847                 msb_divisor_value = desired_divisor / iclk_pi_range;
2848                 pi_value = desired_divisor % iclk_pi_range;
2849
2850                 auxdiv = 0;
2851                 divsel = msb_divisor_value - 2;
2852                 phaseinc = pi_value;
2853         }
2854
2855         /* This should not happen with any sane values */
2856         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2857                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2858         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2859                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2860
2861         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2862                         crtc->mode.clock,
2863                         auxdiv,
2864                         divsel,
2865                         phasedir,
2866                         phaseinc);
2867
2868         /* Program SSCDIVINTPHASE6 */
2869         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2870         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2871         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2872         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2873         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2874         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2875         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2876         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2877
2878         /* Program SSCAUXDIV */
2879         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2880         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2881         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2882         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2883
2884         /* Enable modulator and associated divider */
2885         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2886         temp &= ~SBI_SSCCTL_DISABLE;
2887         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2888
2889         /* Wait for initialization time */
2890         udelay(24);
2891
2892         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2893
2894         mutex_unlock(&dev_priv->dpio_lock);
2895 }
2896
2897 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2898                                                 enum pipe pch_transcoder)
2899 {
2900         struct drm_device *dev = crtc->base.dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2903
2904         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2905                    I915_READ(HTOTAL(cpu_transcoder)));
2906         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2907                    I915_READ(HBLANK(cpu_transcoder)));
2908         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2909                    I915_READ(HSYNC(cpu_transcoder)));
2910
2911         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2912                    I915_READ(VTOTAL(cpu_transcoder)));
2913         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2914                    I915_READ(VBLANK(cpu_transcoder)));
2915         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2916                    I915_READ(VSYNC(cpu_transcoder)));
2917         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2918                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2919 }
2920
2921 /*
2922  * Enable PCH resources required for PCH ports:
2923  *   - PCH PLLs
2924  *   - FDI training & RX/TX
2925  *   - update transcoder timings
2926  *   - DP transcoding bits
2927  *   - transcoder
2928  */
2929 static void ironlake_pch_enable(struct drm_crtc *crtc)
2930 {
2931         struct drm_device *dev = crtc->dev;
2932         struct drm_i915_private *dev_priv = dev->dev_private;
2933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2934         int pipe = intel_crtc->pipe;
2935         u32 reg, temp;
2936
2937         assert_pch_transcoder_disabled(dev_priv, pipe);
2938
2939         /* Write the TU size bits before fdi link training, so that error
2940          * detection works. */
2941         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2942                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2943
2944         /* For PCH output, training FDI link */
2945         dev_priv->display.fdi_link_train(crtc);
2946
2947         /* XXX: pch pll's can be enabled any time before we enable the PCH
2948          * transcoder, and we actually should do this to not upset any PCH
2949          * transcoder that already use the clock when we share it.
2950          *
2951          * Note that enable_shared_dpll tries to do the right thing, but
2952          * get_shared_dpll unconditionally resets the pll - we need that to have
2953          * the right LVDS enable sequence. */
2954         ironlake_enable_shared_dpll(intel_crtc);
2955
2956         if (HAS_PCH_CPT(dev)) {
2957                 u32 sel;
2958
2959                 temp = I915_READ(PCH_DPLL_SEL);
2960                 temp |= TRANS_DPLL_ENABLE(pipe);
2961                 sel = TRANS_DPLLB_SEL(pipe);
2962                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2963                         temp |= sel;
2964                 else
2965                         temp &= ~sel;
2966                 I915_WRITE(PCH_DPLL_SEL, temp);
2967         }
2968
2969         /* set transcoder timing, panel must allow it */
2970         assert_panel_unlocked(dev_priv, pipe);
2971         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2972
2973         intel_fdi_normal_train(crtc);
2974
2975         /* For PCH DP, enable TRANS_DP_CTL */
2976         if (HAS_PCH_CPT(dev) &&
2977             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2978              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2979                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2980                 reg = TRANS_DP_CTL(pipe);
2981                 temp = I915_READ(reg);
2982                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2983                           TRANS_DP_SYNC_MASK |
2984                           TRANS_DP_BPC_MASK);
2985                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2986                          TRANS_DP_ENH_FRAMING);
2987                 temp |= bpc << 9; /* same format but at 11:9 */
2988
2989                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2990                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2991                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2992                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2993
2994                 switch (intel_trans_dp_port_sel(crtc)) {
2995                 case PCH_DP_B:
2996                         temp |= TRANS_DP_PORT_SEL_B;
2997                         break;
2998                 case PCH_DP_C:
2999                         temp |= TRANS_DP_PORT_SEL_C;
3000                         break;
3001                 case PCH_DP_D:
3002                         temp |= TRANS_DP_PORT_SEL_D;
3003                         break;
3004                 default:
3005                         BUG();
3006                 }
3007
3008                 I915_WRITE(reg, temp);
3009         }
3010
3011         ironlake_enable_pch_transcoder(dev_priv, pipe);
3012 }
3013
3014 static void lpt_pch_enable(struct drm_crtc *crtc)
3015 {
3016         struct drm_device *dev = crtc->dev;
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3020
3021         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3022
3023         lpt_program_iclkip(crtc);
3024
3025         /* Set transcoder timing. */
3026         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3027
3028         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3029 }
3030
3031 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3032 {
3033         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3034
3035         if (pll == NULL)
3036                 return;
3037
3038         if (pll->refcount == 0) {
3039                 WARN(1, "bad %s refcount\n", pll->name);
3040                 return;
3041         }
3042
3043         if (--pll->refcount == 0) {
3044                 WARN_ON(pll->on);
3045                 WARN_ON(pll->active);
3046         }
3047
3048         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3049 }
3050
3051 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3052 {
3053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3054         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3055         enum intel_dpll_id i;
3056
3057         if (pll) {
3058                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3059                               crtc->base.base.id, pll->name);
3060                 intel_put_shared_dpll(crtc);
3061         }
3062
3063         if (HAS_PCH_IBX(dev_priv->dev)) {
3064                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3065                 i = crtc->pipe;
3066                 pll = &dev_priv->shared_dplls[i];
3067
3068                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3069                               crtc->base.base.id, pll->name);
3070
3071                 goto found;
3072         }
3073
3074         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3075                 pll = &dev_priv->shared_dplls[i];
3076
3077                 /* Only want to check enabled timings first */
3078                 if (pll->refcount == 0)
3079                         continue;
3080
3081                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3082                            sizeof(pll->hw_state)) == 0) {
3083                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3084                                       crtc->base.base.id,
3085                                       pll->name, pll->refcount, pll->active);
3086
3087                         goto found;
3088                 }
3089         }
3090
3091         /* Ok no matching timings, maybe there's a free one? */
3092         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3093                 pll = &dev_priv->shared_dplls[i];
3094                 if (pll->refcount == 0) {
3095                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3096                                       crtc->base.base.id, pll->name);
3097                         goto found;
3098                 }
3099         }
3100
3101         return NULL;
3102
3103 found:
3104         crtc->config.shared_dpll = i;
3105         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3106                          pipe_name(crtc->pipe));
3107
3108         if (pll->active == 0) {
3109                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3110                        sizeof(pll->hw_state));
3111
3112                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3113                 WARN_ON(pll->on);
3114                 assert_shared_dpll_disabled(dev_priv, pll);
3115
3116                 pll->mode_set(dev_priv, pll);
3117         }
3118         pll->refcount++;
3119
3120         return pll;
3121 }
3122
3123 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3124 {
3125         struct drm_i915_private *dev_priv = dev->dev_private;
3126         int dslreg = PIPEDSL(pipe);
3127         u32 temp;
3128
3129         temp = I915_READ(dslreg);
3130         udelay(500);
3131         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3132                 if (wait_for(I915_READ(dslreg) != temp, 5))
3133                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3134         }
3135 }
3136
3137 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3138 {
3139         struct drm_device *dev = crtc->base.dev;
3140         struct drm_i915_private *dev_priv = dev->dev_private;
3141         int pipe = crtc->pipe;
3142
3143         if (crtc->config.pch_pfit.size) {
3144                 /* Force use of hard-coded filter coefficients
3145                  * as some pre-programmed values are broken,
3146                  * e.g. x201.
3147                  */
3148                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3149                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3150                                                  PF_PIPE_SEL_IVB(pipe));
3151                 else
3152                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3153                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3154                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3155         }
3156 }
3157
3158 static void intel_enable_planes(struct drm_crtc *crtc)
3159 {
3160         struct drm_device *dev = crtc->dev;
3161         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162         struct intel_plane *intel_plane;
3163
3164         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165                 if (intel_plane->pipe == pipe)
3166                         intel_plane_restore(&intel_plane->base);
3167 }
3168
3169 static void intel_disable_planes(struct drm_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->dev;
3172         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3173         struct intel_plane *intel_plane;
3174
3175         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3176                 if (intel_plane->pipe == pipe)
3177                         intel_plane_disable(&intel_plane->base);
3178 }
3179
3180 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3181 {
3182         struct drm_device *dev = crtc->dev;
3183         struct drm_i915_private *dev_priv = dev->dev_private;
3184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3185         struct intel_encoder *encoder;
3186         int pipe = intel_crtc->pipe;
3187         int plane = intel_crtc->plane;
3188
3189         WARN_ON(!crtc->enabled);
3190
3191         if (intel_crtc->active)
3192                 return;
3193
3194         intel_crtc->active = true;
3195
3196         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3197         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3198
3199         intel_update_watermarks(dev);
3200
3201         for_each_encoder_on_crtc(dev, crtc, encoder)
3202                 if (encoder->pre_pll_enable)
3203                         encoder->pre_pll_enable(encoder);
3204
3205         if (intel_crtc->config.has_pch_encoder) {
3206                 /* Note: FDI PLL enabling _must_ be done before we enable the
3207                  * cpu pipes, hence this is separate from all the other fdi/pch
3208                  * enabling. */
3209                 ironlake_fdi_pll_enable(intel_crtc);
3210         } else {
3211                 assert_fdi_tx_disabled(dev_priv, pipe);
3212                 assert_fdi_rx_disabled(dev_priv, pipe);
3213         }
3214
3215         for_each_encoder_on_crtc(dev, crtc, encoder)
3216                 if (encoder->pre_enable)
3217                         encoder->pre_enable(encoder);
3218
3219         ironlake_pfit_enable(intel_crtc);
3220
3221         /*
3222          * On ILK+ LUT must be loaded before the pipe is running but with
3223          * clocks enabled
3224          */
3225         intel_crtc_load_lut(crtc);
3226
3227         intel_enable_pipe(dev_priv, pipe,
3228                           intel_crtc->config.has_pch_encoder);
3229         intel_enable_plane(dev_priv, plane, pipe);
3230         intel_enable_planes(crtc);
3231         intel_crtc_update_cursor(crtc, true);
3232
3233         if (intel_crtc->config.has_pch_encoder)
3234                 ironlake_pch_enable(crtc);
3235
3236         mutex_lock(&dev->struct_mutex);
3237         intel_update_fbc(dev);
3238         mutex_unlock(&dev->struct_mutex);
3239
3240         for_each_encoder_on_crtc(dev, crtc, encoder)
3241                 encoder->enable(encoder);
3242
3243         if (HAS_PCH_CPT(dev))
3244                 cpt_verify_modeset(dev, intel_crtc->pipe);
3245
3246         /*
3247          * There seems to be a race in PCH platform hw (at least on some
3248          * outputs) where an enabled pipe still completes any pageflip right
3249          * away (as if the pipe is off) instead of waiting for vblank. As soon
3250          * as the first vblank happend, everything works as expected. Hence just
3251          * wait for one vblank before returning to avoid strange things
3252          * happening.
3253          */
3254         intel_wait_for_vblank(dev, intel_crtc->pipe);
3255 }
3256
3257 /* IPS only exists on ULT machines and is tied to pipe A. */
3258 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3259 {
3260         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3261 }
3262
3263 static void hsw_enable_ips(struct intel_crtc *crtc)
3264 {
3265         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3266
3267         if (!crtc->config.ips_enabled)
3268                 return;
3269
3270         /* We can only enable IPS after we enable a plane and wait for a vblank.
3271          * We guarantee that the plane is enabled by calling intel_enable_ips
3272          * only after intel_enable_plane. And intel_enable_plane already waits
3273          * for a vblank, so all we need to do here is to enable the IPS bit. */
3274         assert_plane_enabled(dev_priv, crtc->plane);
3275         I915_WRITE(IPS_CTL, IPS_ENABLE);
3276 }
3277
3278 static void hsw_disable_ips(struct intel_crtc *crtc)
3279 {
3280         struct drm_device *dev = crtc->base.dev;
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282
3283         if (!crtc->config.ips_enabled)
3284                 return;
3285
3286         assert_plane_enabled(dev_priv, crtc->plane);
3287         I915_WRITE(IPS_CTL, 0);
3288
3289         /* We need to wait for a vblank before we can disable the plane. */
3290         intel_wait_for_vblank(dev, crtc->pipe);
3291 }
3292
3293 static void haswell_crtc_enable(struct drm_crtc *crtc)
3294 {
3295         struct drm_device *dev = crtc->dev;
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3298         struct intel_encoder *encoder;
3299         int pipe = intel_crtc->pipe;
3300         int plane = intel_crtc->plane;
3301
3302         WARN_ON(!crtc->enabled);
3303
3304         if (intel_crtc->active)
3305                 return;
3306
3307         intel_crtc->active = true;
3308
3309         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3310         if (intel_crtc->config.has_pch_encoder)
3311                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3312
3313         intel_update_watermarks(dev);
3314
3315         if (intel_crtc->config.has_pch_encoder)
3316                 dev_priv->display.fdi_link_train(crtc);
3317
3318         for_each_encoder_on_crtc(dev, crtc, encoder)
3319                 if (encoder->pre_enable)
3320                         encoder->pre_enable(encoder);
3321
3322         intel_ddi_enable_pipe_clock(intel_crtc);
3323
3324         ironlake_pfit_enable(intel_crtc);
3325
3326         /*
3327          * On ILK+ LUT must be loaded before the pipe is running but with
3328          * clocks enabled
3329          */
3330         intel_crtc_load_lut(crtc);
3331
3332         intel_ddi_set_pipe_settings(crtc);
3333         intel_ddi_enable_transcoder_func(crtc);
3334
3335         intel_enable_pipe(dev_priv, pipe,
3336                           intel_crtc->config.has_pch_encoder);
3337         intel_enable_plane(dev_priv, plane, pipe);
3338         intel_enable_planes(crtc);
3339         intel_crtc_update_cursor(crtc, true);
3340
3341         hsw_enable_ips(intel_crtc);
3342
3343         if (intel_crtc->config.has_pch_encoder)
3344                 lpt_pch_enable(crtc);
3345
3346         mutex_lock(&dev->struct_mutex);
3347         intel_update_fbc(dev);
3348         mutex_unlock(&dev->struct_mutex);
3349
3350         for_each_encoder_on_crtc(dev, crtc, encoder)
3351                 encoder->enable(encoder);
3352
3353         /*
3354          * There seems to be a race in PCH platform hw (at least on some
3355          * outputs) where an enabled pipe still completes any pageflip right
3356          * away (as if the pipe is off) instead of waiting for vblank. As soon
3357          * as the first vblank happend, everything works as expected. Hence just
3358          * wait for one vblank before returning to avoid strange things
3359          * happening.
3360          */
3361         intel_wait_for_vblank(dev, intel_crtc->pipe);
3362 }
3363
3364 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3365 {
3366         struct drm_device *dev = crtc->base.dev;
3367         struct drm_i915_private *dev_priv = dev->dev_private;
3368         int pipe = crtc->pipe;
3369
3370         /* To avoid upsetting the power well on haswell only disable the pfit if
3371          * it's in use. The hw state code will make sure we get this right. */
3372         if (crtc->config.pch_pfit.size) {
3373                 I915_WRITE(PF_CTL(pipe), 0);
3374                 I915_WRITE(PF_WIN_POS(pipe), 0);
3375                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3376         }
3377 }
3378
3379 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3380 {
3381         struct drm_device *dev = crtc->dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3384         struct intel_encoder *encoder;
3385         int pipe = intel_crtc->pipe;
3386         int plane = intel_crtc->plane;
3387         u32 reg, temp;
3388
3389
3390         if (!intel_crtc->active)
3391                 return;
3392
3393         for_each_encoder_on_crtc(dev, crtc, encoder)
3394                 encoder->disable(encoder);
3395
3396         intel_crtc_wait_for_pending_flips(crtc);
3397         drm_vblank_off(dev, pipe);
3398
3399         if (dev_priv->cfb_plane == plane)
3400                 intel_disable_fbc(dev);
3401
3402         intel_crtc_update_cursor(crtc, false);
3403         intel_disable_planes(crtc);
3404         intel_disable_plane(dev_priv, plane, pipe);
3405
3406         if (intel_crtc->config.has_pch_encoder)
3407                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3408
3409         intel_disable_pipe(dev_priv, pipe);
3410
3411         ironlake_pfit_disable(intel_crtc);
3412
3413         for_each_encoder_on_crtc(dev, crtc, encoder)
3414                 if (encoder->post_disable)
3415                         encoder->post_disable(encoder);
3416
3417         if (intel_crtc->config.has_pch_encoder) {
3418                 ironlake_fdi_disable(crtc);
3419
3420                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3421                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3422
3423                 if (HAS_PCH_CPT(dev)) {
3424                         /* disable TRANS_DP_CTL */
3425                         reg = TRANS_DP_CTL(pipe);
3426                         temp = I915_READ(reg);
3427                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3428                                   TRANS_DP_PORT_SEL_MASK);
3429                         temp |= TRANS_DP_PORT_SEL_NONE;
3430                         I915_WRITE(reg, temp);
3431
3432                         /* disable DPLL_SEL */
3433                         temp = I915_READ(PCH_DPLL_SEL);
3434                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3435                         I915_WRITE(PCH_DPLL_SEL, temp);
3436                 }
3437
3438                 /* disable PCH DPLL */
3439                 intel_disable_shared_dpll(intel_crtc);
3440
3441                 ironlake_fdi_pll_disable(intel_crtc);
3442         }
3443
3444         intel_crtc->active = false;
3445         intel_update_watermarks(dev);
3446
3447         mutex_lock(&dev->struct_mutex);
3448         intel_update_fbc(dev);
3449         mutex_unlock(&dev->struct_mutex);
3450 }
3451
3452 static void haswell_crtc_disable(struct drm_crtc *crtc)
3453 {
3454         struct drm_device *dev = crtc->dev;
3455         struct drm_i915_private *dev_priv = dev->dev_private;
3456         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3457         struct intel_encoder *encoder;
3458         int pipe = intel_crtc->pipe;
3459         int plane = intel_crtc->plane;
3460         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3461
3462         if (!intel_crtc->active)
3463                 return;
3464
3465         for_each_encoder_on_crtc(dev, crtc, encoder)
3466                 encoder->disable(encoder);
3467
3468         intel_crtc_wait_for_pending_flips(crtc);
3469         drm_vblank_off(dev, pipe);
3470
3471         /* FBC must be disabled before disabling the plane on HSW. */
3472         if (dev_priv->cfb_plane == plane)
3473                 intel_disable_fbc(dev);
3474
3475         hsw_disable_ips(intel_crtc);
3476
3477         intel_crtc_update_cursor(crtc, false);
3478         intel_disable_planes(crtc);
3479         intel_disable_plane(dev_priv, plane, pipe);
3480
3481         if (intel_crtc->config.has_pch_encoder)
3482                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3483         intel_disable_pipe(dev_priv, pipe);
3484
3485         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3486
3487         ironlake_pfit_disable(intel_crtc);
3488
3489         intel_ddi_disable_pipe_clock(intel_crtc);
3490
3491         for_each_encoder_on_crtc(dev, crtc, encoder)
3492                 if (encoder->post_disable)
3493                         encoder->post_disable(encoder);
3494
3495         if (intel_crtc->config.has_pch_encoder) {
3496                 lpt_disable_pch_transcoder(dev_priv);
3497                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3498                 intel_ddi_fdi_disable(crtc);
3499         }
3500
3501         intel_crtc->active = false;
3502         intel_update_watermarks(dev);
3503
3504         mutex_lock(&dev->struct_mutex);
3505         intel_update_fbc(dev);
3506         mutex_unlock(&dev->struct_mutex);
3507 }
3508
3509 static void ironlake_crtc_off(struct drm_crtc *crtc)
3510 {
3511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3512         intel_put_shared_dpll(intel_crtc);
3513 }
3514
3515 static void haswell_crtc_off(struct drm_crtc *crtc)
3516 {
3517         intel_ddi_put_crtc_pll(crtc);
3518 }
3519
3520 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3521 {
3522         if (!enable && intel_crtc->overlay) {
3523                 struct drm_device *dev = intel_crtc->base.dev;
3524                 struct drm_i915_private *dev_priv = dev->dev_private;
3525
3526                 mutex_lock(&dev->struct_mutex);
3527                 dev_priv->mm.interruptible = false;
3528                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3529                 dev_priv->mm.interruptible = true;
3530                 mutex_unlock(&dev->struct_mutex);
3531         }
3532
3533         /* Let userspace switch the overlay on again. In most cases userspace
3534          * has to recompute where to put it anyway.
3535          */
3536 }
3537
3538 /**
3539  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3540  * cursor plane briefly if not already running after enabling the display
3541  * plane.
3542  * This workaround avoids occasional blank screens when self refresh is
3543  * enabled.
3544  */
3545 static void
3546 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3547 {
3548         u32 cntl = I915_READ(CURCNTR(pipe));
3549
3550         if ((cntl & CURSOR_MODE) == 0) {
3551                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3552
3553                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3554                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3555                 intel_wait_for_vblank(dev_priv->dev, pipe);
3556                 I915_WRITE(CURCNTR(pipe), cntl);
3557                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3558                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3559         }
3560 }
3561
3562 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3563 {
3564         struct drm_device *dev = crtc->base.dev;
3565         struct drm_i915_private *dev_priv = dev->dev_private;
3566         struct intel_crtc_config *pipe_config = &crtc->config;
3567
3568         if (!crtc->config.gmch_pfit.control)
3569                 return;
3570
3571         /*
3572          * The panel fitter should only be adjusted whilst the pipe is disabled,
3573          * according to register description and PRM.
3574          */
3575         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3576         assert_pipe_disabled(dev_priv, crtc->pipe);
3577
3578         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3579         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3580
3581         /* Border color in case we don't scale up to the full screen. Black by
3582          * default, change to something else for debugging. */
3583         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3584 }
3585
3586 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3587 {
3588         struct drm_device *dev = crtc->dev;
3589         struct drm_i915_private *dev_priv = dev->dev_private;
3590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3591         struct intel_encoder *encoder;
3592         int pipe = intel_crtc->pipe;
3593         int plane = intel_crtc->plane;
3594
3595         WARN_ON(!crtc->enabled);
3596
3597         if (intel_crtc->active)
3598                 return;
3599
3600         intel_crtc->active = true;
3601         intel_update_watermarks(dev);
3602
3603         mutex_lock(&dev_priv->dpio_lock);
3604
3605         for_each_encoder_on_crtc(dev, crtc, encoder)
3606                 if (encoder->pre_pll_enable)
3607                         encoder->pre_pll_enable(encoder);
3608
3609         vlv_enable_pll(dev_priv, pipe);
3610
3611         for_each_encoder_on_crtc(dev, crtc, encoder)
3612                 if (encoder->pre_enable)
3613                         encoder->pre_enable(encoder);
3614
3615         /* VLV wants encoder enabling _before_ the pipe is up. */
3616         for_each_encoder_on_crtc(dev, crtc, encoder)
3617                 encoder->enable(encoder);
3618
3619         i9xx_pfit_enable(intel_crtc);
3620
3621         intel_crtc_load_lut(crtc);
3622
3623         intel_enable_pipe(dev_priv, pipe, false);
3624         intel_enable_plane(dev_priv, plane, pipe);
3625         intel_enable_planes(crtc);
3626         intel_crtc_update_cursor(crtc, true);
3627
3628         intel_update_fbc(dev);
3629
3630         mutex_unlock(&dev_priv->dpio_lock);
3631 }
3632
3633 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3634 {
3635         struct drm_device *dev = crtc->dev;
3636         struct drm_i915_private *dev_priv = dev->dev_private;
3637         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3638         struct intel_encoder *encoder;
3639         int pipe = intel_crtc->pipe;
3640         int plane = intel_crtc->plane;
3641
3642         WARN_ON(!crtc->enabled);
3643
3644         if (intel_crtc->active)
3645                 return;
3646
3647         intel_crtc->active = true;
3648         intel_update_watermarks(dev);
3649
3650         i9xx_enable_pll(dev_priv, pipe);
3651
3652         for_each_encoder_on_crtc(dev, crtc, encoder)
3653                 if (encoder->pre_enable)
3654                         encoder->pre_enable(encoder);
3655
3656         i9xx_pfit_enable(intel_crtc);
3657
3658         intel_crtc_load_lut(crtc);
3659
3660         intel_enable_pipe(dev_priv, pipe, false);
3661         intel_enable_plane(dev_priv, plane, pipe);
3662         intel_enable_planes(crtc);
3663         /* The fixup needs to happen before cursor is enabled */
3664         if (IS_G4X(dev))
3665                 g4x_fixup_plane(dev_priv, pipe);
3666         intel_crtc_update_cursor(crtc, true);
3667
3668         /* Give the overlay scaler a chance to enable if it's on this pipe */
3669         intel_crtc_dpms_overlay(intel_crtc, true);
3670
3671         intel_update_fbc(dev);
3672
3673         for_each_encoder_on_crtc(dev, crtc, encoder)
3674                 encoder->enable(encoder);
3675 }
3676
3677 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3678 {
3679         struct drm_device *dev = crtc->base.dev;
3680         struct drm_i915_private *dev_priv = dev->dev_private;
3681
3682         if (!crtc->config.gmch_pfit.control)
3683                 return;
3684
3685         assert_pipe_disabled(dev_priv, crtc->pipe);
3686
3687         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3688                          I915_READ(PFIT_CONTROL));
3689         I915_WRITE(PFIT_CONTROL, 0);
3690 }
3691
3692 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3693 {
3694         struct drm_device *dev = crtc->dev;
3695         struct drm_i915_private *dev_priv = dev->dev_private;
3696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697         struct intel_encoder *encoder;
3698         int pipe = intel_crtc->pipe;
3699         int plane = intel_crtc->plane;
3700
3701         if (!intel_crtc->active)
3702                 return;
3703
3704         for_each_encoder_on_crtc(dev, crtc, encoder)
3705                 encoder->disable(encoder);
3706
3707         /* Give the overlay scaler a chance to disable if it's on this pipe */
3708         intel_crtc_wait_for_pending_flips(crtc);
3709         drm_vblank_off(dev, pipe);
3710
3711         if (dev_priv->cfb_plane == plane)
3712                 intel_disable_fbc(dev);
3713
3714         intel_crtc_dpms_overlay(intel_crtc, false);
3715         intel_crtc_update_cursor(crtc, false);
3716         intel_disable_planes(crtc);
3717         intel_disable_plane(dev_priv, plane, pipe);
3718
3719         intel_disable_pipe(dev_priv, pipe);
3720
3721         i9xx_pfit_disable(intel_crtc);
3722
3723         for_each_encoder_on_crtc(dev, crtc, encoder)
3724                 if (encoder->post_disable)
3725                         encoder->post_disable(encoder);
3726
3727         intel_disable_pll(dev_priv, pipe);
3728
3729         intel_crtc->active = false;
3730         intel_update_fbc(dev);
3731         intel_update_watermarks(dev);
3732 }
3733
3734 static void i9xx_crtc_off(struct drm_crtc *crtc)
3735 {
3736 }
3737
3738 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3739                                     bool enabled)
3740 {
3741         struct drm_device *dev = crtc->dev;
3742         struct drm_i915_master_private *master_priv;
3743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744         int pipe = intel_crtc->pipe;
3745
3746         if (!dev->primary->master)
3747                 return;
3748
3749         master_priv = dev->primary->master->driver_priv;
3750         if (!master_priv->sarea_priv)
3751                 return;
3752
3753         switch (pipe) {
3754         case 0:
3755                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3756                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3757                 break;
3758         case 1:
3759                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3760                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3761                 break;
3762         default:
3763                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3764                 break;
3765         }
3766 }
3767
3768 /**
3769  * Sets the power management mode of the pipe and plane.
3770  */
3771 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3772 {
3773         struct drm_device *dev = crtc->dev;
3774         struct drm_i915_private *dev_priv = dev->dev_private;
3775         struct intel_encoder *intel_encoder;
3776         bool enable = false;
3777
3778         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3779                 enable |= intel_encoder->connectors_active;
3780
3781         if (enable)
3782                 dev_priv->display.crtc_enable(crtc);
3783         else
3784                 dev_priv->display.crtc_disable(crtc);
3785
3786         intel_crtc_update_sarea(crtc, enable);
3787 }
3788
3789 static void intel_crtc_disable(struct drm_crtc *crtc)
3790 {
3791         struct drm_device *dev = crtc->dev;
3792         struct drm_connector *connector;
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795
3796         /* crtc should still be enabled when we disable it. */
3797         WARN_ON(!crtc->enabled);
3798
3799         dev_priv->display.crtc_disable(crtc);
3800         intel_crtc->eld_vld = false;
3801         intel_crtc_update_sarea(crtc, false);
3802         dev_priv->display.off(crtc);
3803
3804         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3805         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3806
3807         if (crtc->fb) {
3808                 mutex_lock(&dev->struct_mutex);
3809                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3810                 mutex_unlock(&dev->struct_mutex);
3811                 crtc->fb = NULL;
3812         }
3813
3814         /* Update computed state. */
3815         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3816                 if (!connector->encoder || !connector->encoder->crtc)
3817                         continue;
3818
3819                 if (connector->encoder->crtc != crtc)
3820                         continue;
3821
3822                 connector->dpms = DRM_MODE_DPMS_OFF;
3823                 to_intel_encoder(connector->encoder)->connectors_active = false;
3824         }
3825 }
3826
3827 void intel_modeset_disable(struct drm_device *dev)
3828 {
3829         struct drm_crtc *crtc;
3830
3831         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3832                 if (crtc->enabled)
3833                         intel_crtc_disable(crtc);
3834         }
3835 }
3836
3837 void intel_encoder_destroy(struct drm_encoder *encoder)
3838 {
3839         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3840
3841         drm_encoder_cleanup(encoder);
3842         kfree(intel_encoder);
3843 }
3844
3845 /* Simple dpms helper for encodres with just one connector, no cloning and only
3846  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3847  * state of the entire output pipe. */
3848 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3849 {
3850         if (mode == DRM_MODE_DPMS_ON) {
3851                 encoder->connectors_active = true;
3852
3853                 intel_crtc_update_dpms(encoder->base.crtc);
3854         } else {
3855                 encoder->connectors_active = false;
3856
3857                 intel_crtc_update_dpms(encoder->base.crtc);
3858         }
3859 }
3860
3861 /* Cross check the actual hw state with our own modeset state tracking (and it's
3862  * internal consistency). */
3863 static void intel_connector_check_state(struct intel_connector *connector)
3864 {
3865         if (connector->get_hw_state(connector)) {
3866                 struct intel_encoder *encoder = connector->encoder;
3867                 struct drm_crtc *crtc;
3868                 bool encoder_enabled;
3869                 enum pipe pipe;
3870
3871                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3872                               connector->base.base.id,
3873                               drm_get_connector_name(&connector->base));
3874
3875                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3876                      "wrong connector dpms state\n");
3877                 WARN(connector->base.encoder != &encoder->base,
3878                      "active connector not linked to encoder\n");
3879                 WARN(!encoder->connectors_active,
3880                      "encoder->connectors_active not set\n");
3881
3882                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3883                 WARN(!encoder_enabled, "encoder not enabled\n");
3884                 if (WARN_ON(!encoder->base.crtc))
3885                         return;
3886
3887                 crtc = encoder->base.crtc;
3888
3889                 WARN(!crtc->enabled, "crtc not enabled\n");
3890                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3891                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3892                      "encoder active on the wrong pipe\n");
3893         }
3894 }
3895
3896 /* Even simpler default implementation, if there's really no special case to
3897  * consider. */
3898 void intel_connector_dpms(struct drm_connector *connector, int mode)
3899 {
3900         struct intel_encoder *encoder = intel_attached_encoder(connector);
3901
3902         /* All the simple cases only support two dpms states. */
3903         if (mode != DRM_MODE_DPMS_ON)
3904                 mode = DRM_MODE_DPMS_OFF;
3905
3906         if (mode == connector->dpms)
3907                 return;
3908
3909         connector->dpms = mode;
3910
3911         /* Only need to change hw state when actually enabled */
3912         if (encoder->base.crtc)
3913                 intel_encoder_dpms(encoder, mode);
3914         else
3915                 WARN_ON(encoder->connectors_active != false);
3916
3917         intel_modeset_check_state(connector->dev);
3918 }
3919
3920 /* Simple connector->get_hw_state implementation for encoders that support only
3921  * one connector and no cloning and hence the encoder state determines the state
3922  * of the connector. */
3923 bool intel_connector_get_hw_state(struct intel_connector *connector)
3924 {
3925         enum pipe pipe = 0;
3926         struct intel_encoder *encoder = connector->encoder;
3927
3928         return encoder->get_hw_state(encoder, &pipe);
3929 }
3930
3931 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3932                                      struct intel_crtc_config *pipe_config)
3933 {
3934         struct drm_i915_private *dev_priv = dev->dev_private;
3935         struct intel_crtc *pipe_B_crtc =
3936                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3937
3938         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3939                       pipe_name(pipe), pipe_config->fdi_lanes);
3940         if (pipe_config->fdi_lanes > 4) {
3941                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3942                               pipe_name(pipe), pipe_config->fdi_lanes);
3943                 return false;
3944         }
3945
3946         if (IS_HASWELL(dev)) {
3947                 if (pipe_config->fdi_lanes > 2) {
3948                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3949                                       pipe_config->fdi_lanes);
3950                         return false;
3951                 } else {
3952                         return true;
3953                 }
3954         }
3955
3956         if (INTEL_INFO(dev)->num_pipes == 2)
3957                 return true;
3958
3959         /* Ivybridge 3 pipe is really complicated */
3960         switch (pipe) {
3961         case PIPE_A:
3962                 return true;
3963         case PIPE_B:
3964                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3965                     pipe_config->fdi_lanes > 2) {
3966                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3967                                       pipe_name(pipe), pipe_config->fdi_lanes);
3968                         return false;
3969                 }
3970                 return true;
3971         case PIPE_C:
3972                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3973                     pipe_B_crtc->config.fdi_lanes <= 2) {
3974                         if (pipe_config->fdi_lanes > 2) {
3975                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3976                                               pipe_name(pipe), pipe_config->fdi_lanes);
3977                                 return false;
3978                         }
3979                 } else {
3980                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3981                         return false;
3982                 }
3983                 return true;
3984         default:
3985                 BUG();
3986         }
3987 }
3988
3989 #define RETRY 1
3990 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3991                                        struct intel_crtc_config *pipe_config)
3992 {
3993         struct drm_device *dev = intel_crtc->base.dev;
3994         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3995         int lane, link_bw, fdi_dotclock;
3996         bool setup_ok, needs_recompute = false;
3997
3998 retry:
3999         /* FDI is a binary signal running at ~2.7GHz, encoding
4000          * each output octet as 10 bits. The actual frequency
4001          * is stored as a divider into a 100MHz clock, and the
4002          * mode pixel clock is stored in units of 1KHz.
4003          * Hence the bw of each lane in terms of the mode signal
4004          * is:
4005          */
4006         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4007
4008         fdi_dotclock = adjusted_mode->clock;
4009         fdi_dotclock /= pipe_config->pixel_multiplier;
4010
4011         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4012                                            pipe_config->pipe_bpp);
4013
4014         pipe_config->fdi_lanes = lane;
4015
4016         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4017                                link_bw, &pipe_config->fdi_m_n);
4018
4019         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4020                                             intel_crtc->pipe, pipe_config);
4021         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4022                 pipe_config->pipe_bpp -= 2*3;
4023                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4024                               pipe_config->pipe_bpp);
4025                 needs_recompute = true;
4026                 pipe_config->bw_constrained = true;
4027
4028                 goto retry;
4029         }
4030
4031         if (needs_recompute)
4032                 return RETRY;
4033
4034         return setup_ok ? 0 : -EINVAL;
4035 }
4036
4037 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4038                                    struct intel_crtc_config *pipe_config)
4039 {
4040         pipe_config->ips_enabled = i915_enable_ips &&
4041                                    hsw_crtc_supports_ips(crtc) &&
4042                                    pipe_config->pipe_bpp == 24;
4043 }
4044
4045 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4046                                      struct intel_crtc_config *pipe_config)
4047 {
4048         struct drm_device *dev = crtc->base.dev;
4049         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4050
4051         if (HAS_PCH_SPLIT(dev)) {
4052                 /* FDI link clock is fixed at 2.7G */
4053                 if (pipe_config->requested_mode.clock * 3
4054                     > IRONLAKE_FDI_FREQ * 4)
4055                         return -EINVAL;
4056         }
4057
4058         /* All interlaced capable intel hw wants timings in frames. Note though
4059          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4060          * timings, so we need to be careful not to clobber these.*/
4061         if (!pipe_config->timings_set)
4062                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4063
4064         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4065          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4066          */
4067         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4068                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4069                 return -EINVAL;
4070
4071         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4072                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4073         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4074                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4075                  * for lvds. */
4076                 pipe_config->pipe_bpp = 8*3;
4077         }
4078
4079         if (HAS_IPS(dev))
4080                 hsw_compute_ips_config(crtc, pipe_config);
4081
4082         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4083          * clock survives for now. */
4084         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4085                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4086
4087         if (pipe_config->has_pch_encoder)
4088                 return ironlake_fdi_compute_config(crtc, pipe_config);
4089
4090         return 0;
4091 }
4092
4093 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4094 {
4095         return 400000; /* FIXME */
4096 }
4097
4098 static int i945_get_display_clock_speed(struct drm_device *dev)
4099 {
4100         return 400000;
4101 }
4102
4103 static int i915_get_display_clock_speed(struct drm_device *dev)
4104 {
4105         return 333000;
4106 }
4107
4108 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4109 {
4110         return 200000;
4111 }
4112
4113 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4114 {
4115         u16 gcfgc = 0;
4116
4117         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4118
4119         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4120                 return 133000;
4121         else {
4122                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4123                 case GC_DISPLAY_CLOCK_333_MHZ:
4124                         return 333000;
4125                 default:
4126                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4127                         return 190000;
4128                 }
4129         }
4130 }
4131
4132 static int i865_get_display_clock_speed(struct drm_device *dev)
4133 {
4134         return 266000;
4135 }
4136
4137 static int i855_get_display_clock_speed(struct drm_device *dev)
4138 {
4139         u16 hpllcc = 0;
4140         /* Assume that the hardware is in the high speed state.  This
4141          * should be the default.
4142          */
4143         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4144         case GC_CLOCK_133_200:
4145         case GC_CLOCK_100_200:
4146                 return 200000;
4147         case GC_CLOCK_166_250:
4148                 return 250000;
4149         case GC_CLOCK_100_133:
4150                 return 133000;
4151         }
4152
4153         /* Shouldn't happen */
4154         return 0;
4155 }
4156
4157 static int i830_get_display_clock_speed(struct drm_device *dev)
4158 {
4159         return 133000;
4160 }
4161
4162 static void
4163 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4164 {
4165         while (*num > DATA_LINK_M_N_MASK ||
4166                *den > DATA_LINK_M_N_MASK) {
4167                 *num >>= 1;
4168                 *den >>= 1;
4169         }
4170 }
4171
4172 static void compute_m_n(unsigned int m, unsigned int n,
4173                         uint32_t *ret_m, uint32_t *ret_n)
4174 {
4175         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4176         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4177         intel_reduce_m_n_ratio(ret_m, ret_n);
4178 }
4179
4180 void
4181 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4182                        int pixel_clock, int link_clock,
4183                        struct intel_link_m_n *m_n)
4184 {
4185         m_n->tu = 64;
4186
4187         compute_m_n(bits_per_pixel * pixel_clock,
4188                     link_clock * nlanes * 8,
4189                     &m_n->gmch_m, &m_n->gmch_n);
4190
4191         compute_m_n(pixel_clock, link_clock,
4192                     &m_n->link_m, &m_n->link_n);
4193 }
4194
4195 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4196 {
4197         if (i915_panel_use_ssc >= 0)
4198                 return i915_panel_use_ssc != 0;
4199         return dev_priv->vbt.lvds_use_ssc
4200                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4201 }
4202
4203 static int vlv_get_refclk(struct drm_crtc *crtc)
4204 {
4205         struct drm_device *dev = crtc->dev;
4206         struct drm_i915_private *dev_priv = dev->dev_private;
4207         int refclk = 27000; /* for DP & HDMI */
4208
4209         return 100000; /* only one validated so far */
4210
4211         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4212                 refclk = 96000;
4213         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4214                 if (intel_panel_use_ssc(dev_priv))
4215                         refclk = 100000;
4216                 else
4217                         refclk = 96000;
4218         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4219                 refclk = 100000;
4220         }
4221
4222         return refclk;
4223 }
4224
4225 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4226 {
4227         struct drm_device *dev = crtc->dev;
4228         struct drm_i915_private *dev_priv = dev->dev_private;
4229         int refclk;
4230
4231         if (IS_VALLEYVIEW(dev)) {
4232                 refclk = vlv_get_refclk(crtc);
4233         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4234             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4235                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4236                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4237                               refclk / 1000);
4238         } else if (!IS_GEN2(dev)) {
4239                 refclk = 96000;
4240         } else {
4241                 refclk = 48000;
4242         }
4243
4244         return refclk;
4245 }
4246
4247 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4248 {
4249         return (1 << dpll->n) << 16 | dpll->m2;
4250 }
4251
4252 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4253 {
4254         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4255 }
4256
4257 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4258                                      intel_clock_t *reduced_clock)
4259 {
4260         struct drm_device *dev = crtc->base.dev;
4261         struct drm_i915_private *dev_priv = dev->dev_private;
4262         int pipe = crtc->pipe;
4263         u32 fp, fp2 = 0;
4264
4265         if (IS_PINEVIEW(dev)) {
4266                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4267                 if (reduced_clock)
4268                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4269         } else {
4270                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4271                 if (reduced_clock)
4272                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4273         }
4274
4275         I915_WRITE(FP0(pipe), fp);
4276
4277         crtc->lowfreq_avail = false;
4278         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4279             reduced_clock && i915_powersave) {
4280                 I915_WRITE(FP1(pipe), fp2);
4281                 crtc->lowfreq_avail = true;
4282         } else {
4283                 I915_WRITE(FP1(pipe), fp);
4284         }
4285 }
4286
4287 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4288 {
4289         u32 reg_val;
4290
4291         /*
4292          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4293          * and set it to a reasonable value instead.
4294          */
4295         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4296         reg_val &= 0xffffff00;
4297         reg_val |= 0x00000030;
4298         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4299
4300         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4301         reg_val &= 0x8cffffff;
4302         reg_val = 0x8c000000;
4303         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4304
4305         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4306         reg_val &= 0xffffff00;
4307         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4308
4309         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4310         reg_val &= 0x00ffffff;
4311         reg_val |= 0xb0000000;
4312         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4313 }
4314
4315 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4316                                          struct intel_link_m_n *m_n)
4317 {
4318         struct drm_device *dev = crtc->base.dev;
4319         struct drm_i915_private *dev_priv = dev->dev_private;
4320         int pipe = crtc->pipe;
4321
4322         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4323         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4324         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4325         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4326 }
4327
4328 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4329                                          struct intel_link_m_n *m_n)
4330 {
4331         struct drm_device *dev = crtc->base.dev;
4332         struct drm_i915_private *dev_priv = dev->dev_private;
4333         int pipe = crtc->pipe;
4334         enum transcoder transcoder = crtc->config.cpu_transcoder;
4335
4336         if (INTEL_INFO(dev)->gen >= 5) {
4337                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4338                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4339                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4340                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4341         } else {
4342                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4343                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4344                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4345                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4346         }
4347 }
4348
4349 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4350 {
4351         if (crtc->config.has_pch_encoder)
4352                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4353         else
4354                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4355 }
4356
4357 static void vlv_update_pll(struct intel_crtc *crtc)
4358 {
4359         struct drm_device *dev = crtc->base.dev;
4360         struct drm_i915_private *dev_priv = dev->dev_private;
4361         struct intel_encoder *encoder;
4362         int pipe = crtc->pipe;
4363         u32 dpll, mdiv;
4364         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4365         bool is_hdmi;
4366         u32 coreclk, reg_val, dpll_md;
4367
4368         mutex_lock(&dev_priv->dpio_lock);
4369
4370         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4371
4372         bestn = crtc->config.dpll.n;
4373         bestm1 = crtc->config.dpll.m1;
4374         bestm2 = crtc->config.dpll.m2;
4375         bestp1 = crtc->config.dpll.p1;
4376         bestp2 = crtc->config.dpll.p2;
4377
4378         /* See eDP HDMI DPIO driver vbios notes doc */
4379
4380         /* PLL B needs special handling */
4381         if (pipe)
4382                 vlv_pllb_recal_opamp(dev_priv);
4383
4384         /* Set up Tx target for periodic Rcomp update */
4385         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4386
4387         /* Disable target IRef on PLL */
4388         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4389         reg_val &= 0x00ffffff;
4390         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4391
4392         /* Disable fast lock */
4393         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4394
4395         /* Set idtafcrecal before PLL is enabled */
4396         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4397         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4398         mdiv |= ((bestn << DPIO_N_SHIFT));
4399         mdiv |= (1 << DPIO_K_SHIFT);
4400
4401         /*
4402          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4403          * but we don't support that).
4404          * Note: don't use the DAC post divider as it seems unstable.
4405          */
4406         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4407         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4408
4409         mdiv |= DPIO_ENABLE_CALIBRATION;
4410         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4411
4412         /* Set HBR and RBR LPF coefficients */
4413         if (crtc->config.port_clock == 162000 ||
4414             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4415             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4416                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4417                                  0x005f0021);
4418         else
4419                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4420                                  0x00d0000f);
4421
4422         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4423             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4424                 /* Use SSC source */
4425                 if (!pipe)
4426                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4427                                          0x0df40000);
4428                 else
4429                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4430                                          0x0df70000);
4431         } else { /* HDMI or VGA */
4432                 /* Use bend source */
4433                 if (!pipe)
4434                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4435                                          0x0df70000);
4436                 else
4437                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4438                                          0x0df40000);
4439         }
4440
4441         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4442         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4443         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4444             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4445                 coreclk |= 0x01000000;
4446         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4447
4448         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4449
4450         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4451                 if (encoder->pre_pll_enable)
4452                         encoder->pre_pll_enable(encoder);
4453
4454         /* Enable DPIO clock input */
4455         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4456                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4457         if (pipe)
4458                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4459
4460         dpll |= DPLL_VCO_ENABLE;
4461         I915_WRITE(DPLL(pipe), dpll);
4462         POSTING_READ(DPLL(pipe));
4463         udelay(150);
4464
4465         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4466                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4467
4468         dpll_md = (crtc->config.pixel_multiplier - 1)
4469                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4470         I915_WRITE(DPLL_MD(pipe), dpll_md);
4471         POSTING_READ(DPLL_MD(pipe));
4472
4473         if (crtc->config.has_dp_encoder)
4474                 intel_dp_set_m_n(crtc);
4475
4476         mutex_unlock(&dev_priv->dpio_lock);
4477 }
4478
4479 static void i9xx_update_pll(struct intel_crtc *crtc,
4480                             intel_clock_t *reduced_clock,
4481                             int num_connectors)
4482 {
4483         struct drm_device *dev = crtc->base.dev;
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485         struct intel_encoder *encoder;
4486         int pipe = crtc->pipe;
4487         u32 dpll;
4488         bool is_sdvo;
4489         struct dpll *clock = &crtc->config.dpll;
4490
4491         i9xx_update_pll_dividers(crtc, reduced_clock);
4492
4493         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4494                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4495
4496         dpll = DPLL_VGA_MODE_DIS;
4497
4498         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4499                 dpll |= DPLLB_MODE_LVDS;
4500         else
4501                 dpll |= DPLLB_MODE_DAC_SERIAL;
4502
4503         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4504                 dpll |= (crtc->config.pixel_multiplier - 1)
4505                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4506         }
4507
4508         if (is_sdvo)
4509                 dpll |= DPLL_DVO_HIGH_SPEED;
4510
4511         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4512                 dpll |= DPLL_DVO_HIGH_SPEED;
4513
4514         /* compute bitmask from p1 value */
4515         if (IS_PINEVIEW(dev))
4516                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4517         else {
4518                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4519                 if (IS_G4X(dev) && reduced_clock)
4520                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4521         }
4522         switch (clock->p2) {
4523         case 5:
4524                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4525                 break;
4526         case 7:
4527                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4528                 break;
4529         case 10:
4530                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4531                 break;
4532         case 14:
4533                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4534                 break;
4535         }
4536         if (INTEL_INFO(dev)->gen >= 4)
4537                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4538
4539         if (crtc->config.sdvo_tv_clock)
4540                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4541         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4542                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4543                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4544         else
4545                 dpll |= PLL_REF_INPUT_DREFCLK;
4546
4547         dpll |= DPLL_VCO_ENABLE;
4548         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4549         POSTING_READ(DPLL(pipe));
4550         udelay(150);
4551
4552         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4553                 if (encoder->pre_pll_enable)
4554                         encoder->pre_pll_enable(encoder);
4555
4556         if (crtc->config.has_dp_encoder)
4557                 intel_dp_set_m_n(crtc);
4558
4559         I915_WRITE(DPLL(pipe), dpll);
4560
4561         /* Wait for the clocks to stabilize. */
4562         POSTING_READ(DPLL(pipe));
4563         udelay(150);
4564
4565         if (INTEL_INFO(dev)->gen >= 4) {
4566                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4567                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4568                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4569         } else {
4570                 /* The pixel multiplier can only be updated once the
4571                  * DPLL is enabled and the clocks are stable.
4572                  *
4573                  * So write it again.
4574                  */
4575                 I915_WRITE(DPLL(pipe), dpll);
4576         }
4577 }
4578
4579 static void i8xx_update_pll(struct intel_crtc *crtc,
4580                             intel_clock_t *reduced_clock,
4581                             int num_connectors)
4582 {
4583         struct drm_device *dev = crtc->base.dev;
4584         struct drm_i915_private *dev_priv = dev->dev_private;
4585         struct intel_encoder *encoder;
4586         int pipe = crtc->pipe;
4587         u32 dpll;
4588         struct dpll *clock = &crtc->config.dpll;
4589
4590         i9xx_update_pll_dividers(crtc, reduced_clock);
4591
4592         dpll = DPLL_VGA_MODE_DIS;
4593
4594         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4595                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596         } else {
4597                 if (clock->p1 == 2)
4598                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4599                 else
4600                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4601                 if (clock->p2 == 4)
4602                         dpll |= PLL_P2_DIVIDE_BY_4;
4603         }
4604
4605         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4606                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4607                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4608         else
4609                 dpll |= PLL_REF_INPUT_DREFCLK;
4610
4611         dpll |= DPLL_VCO_ENABLE;
4612         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4613         POSTING_READ(DPLL(pipe));
4614         udelay(150);
4615
4616         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4617                 if (encoder->pre_pll_enable)
4618                         encoder->pre_pll_enable(encoder);
4619
4620         I915_WRITE(DPLL(pipe), dpll);
4621
4622         /* Wait for the clocks to stabilize. */
4623         POSTING_READ(DPLL(pipe));
4624         udelay(150);
4625
4626         /* The pixel multiplier can only be updated once the
4627          * DPLL is enabled and the clocks are stable.
4628          *
4629          * So write it again.
4630          */
4631         I915_WRITE(DPLL(pipe), dpll);
4632 }
4633
4634 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4635 {
4636         struct drm_device *dev = intel_crtc->base.dev;
4637         struct drm_i915_private *dev_priv = dev->dev_private;
4638         enum pipe pipe = intel_crtc->pipe;
4639         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4640         struct drm_display_mode *adjusted_mode =
4641                 &intel_crtc->config.adjusted_mode;
4642         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4643         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4644
4645         /* We need to be careful not to changed the adjusted mode, for otherwise
4646          * the hw state checker will get angry at the mismatch. */
4647         crtc_vtotal = adjusted_mode->crtc_vtotal;
4648         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4649
4650         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4651                 /* the chip adds 2 halflines automatically */
4652                 crtc_vtotal -= 1;
4653                 crtc_vblank_end -= 1;
4654                 vsyncshift = adjusted_mode->crtc_hsync_start
4655                              - adjusted_mode->crtc_htotal / 2;
4656         } else {
4657                 vsyncshift = 0;
4658         }
4659
4660         if (INTEL_INFO(dev)->gen > 3)
4661                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4662
4663         I915_WRITE(HTOTAL(cpu_transcoder),
4664                    (adjusted_mode->crtc_hdisplay - 1) |
4665                    ((adjusted_mode->crtc_htotal - 1) << 16));
4666         I915_WRITE(HBLANK(cpu_transcoder),
4667                    (adjusted_mode->crtc_hblank_start - 1) |
4668                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4669         I915_WRITE(HSYNC(cpu_transcoder),
4670                    (adjusted_mode->crtc_hsync_start - 1) |
4671                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4672
4673         I915_WRITE(VTOTAL(cpu_transcoder),
4674                    (adjusted_mode->crtc_vdisplay - 1) |
4675                    ((crtc_vtotal - 1) << 16));
4676         I915_WRITE(VBLANK(cpu_transcoder),
4677                    (adjusted_mode->crtc_vblank_start - 1) |
4678                    ((crtc_vblank_end - 1) << 16));
4679         I915_WRITE(VSYNC(cpu_transcoder),
4680                    (adjusted_mode->crtc_vsync_start - 1) |
4681                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4682
4683         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4684          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4685          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4686          * bits. */
4687         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4688             (pipe == PIPE_B || pipe == PIPE_C))
4689                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4690
4691         /* pipesrc controls the size that is scaled from, which should
4692          * always be the user's requested size.
4693          */
4694         I915_WRITE(PIPESRC(pipe),
4695                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4696 }
4697
4698 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4699                                    struct intel_crtc_config *pipe_config)
4700 {
4701         struct drm_device *dev = crtc->base.dev;
4702         struct drm_i915_private *dev_priv = dev->dev_private;
4703         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4704         uint32_t tmp;
4705
4706         tmp = I915_READ(HTOTAL(cpu_transcoder));
4707         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4708         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4709         tmp = I915_READ(HBLANK(cpu_transcoder));
4710         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4711         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4712         tmp = I915_READ(HSYNC(cpu_transcoder));
4713         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4714         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4715
4716         tmp = I915_READ(VTOTAL(cpu_transcoder));
4717         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4718         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4719         tmp = I915_READ(VBLANK(cpu_transcoder));
4720         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4721         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4722         tmp = I915_READ(VSYNC(cpu_transcoder));
4723         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4724         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4725
4726         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4727                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4728                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4729                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4730         }
4731
4732         tmp = I915_READ(PIPESRC(crtc->pipe));
4733         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4734         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4735 }
4736
4737 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4738 {
4739         struct drm_device *dev = intel_crtc->base.dev;
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741         uint32_t pipeconf;
4742
4743         pipeconf = 0;
4744
4745         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4746                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4747                  * core speed.
4748                  *
4749                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4750                  * pipe == 0 check?
4751                  */
4752                 if (intel_crtc->config.requested_mode.clock >
4753                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4754                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4755         }
4756
4757         /* only g4x and later have fancy bpc/dither controls */
4758         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4759                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4760                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4761                         pipeconf |= PIPECONF_DITHER_EN |
4762                                     PIPECONF_DITHER_TYPE_SP;
4763
4764                 switch (intel_crtc->config.pipe_bpp) {
4765                 case 18:
4766                         pipeconf |= PIPECONF_6BPC;
4767                         break;
4768                 case 24:
4769                         pipeconf |= PIPECONF_8BPC;
4770                         break;
4771                 case 30:
4772                         pipeconf |= PIPECONF_10BPC;
4773                         break;
4774                 default:
4775                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4776                         BUG();
4777                 }
4778         }
4779
4780         if (HAS_PIPE_CXSR(dev)) {
4781                 if (intel_crtc->lowfreq_avail) {
4782                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4783                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4784                 } else {
4785                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4786                 }
4787         }
4788
4789         if (!IS_GEN2(dev) &&
4790             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4791                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4792         else
4793                 pipeconf |= PIPECONF_PROGRESSIVE;
4794
4795         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4796                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4797
4798         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4799         POSTING_READ(PIPECONF(intel_crtc->pipe));
4800 }
4801
4802 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4803                               int x, int y,
4804                               struct drm_framebuffer *fb)
4805 {
4806         struct drm_device *dev = crtc->dev;
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4810         int pipe = intel_crtc->pipe;
4811         int plane = intel_crtc->plane;
4812         int refclk, num_connectors = 0;
4813         intel_clock_t clock, reduced_clock;
4814         u32 dspcntr;
4815         bool ok, has_reduced_clock = false;
4816         bool is_lvds = false;
4817         struct intel_encoder *encoder;
4818         const intel_limit_t *limit;
4819         int ret;
4820
4821         for_each_encoder_on_crtc(dev, crtc, encoder) {
4822                 switch (encoder->type) {
4823                 case INTEL_OUTPUT_LVDS:
4824                         is_lvds = true;
4825                         break;
4826                 }
4827
4828                 num_connectors++;
4829         }
4830
4831         refclk = i9xx_get_refclk(crtc, num_connectors);
4832
4833         /*
4834          * Returns a set of divisors for the desired target clock with the given
4835          * refclk, or FALSE.  The returned values represent the clock equation:
4836          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4837          */
4838         limit = intel_limit(crtc, refclk);
4839         ok = dev_priv->display.find_dpll(limit, crtc,
4840                                          intel_crtc->config.port_clock,
4841                                          refclk, NULL, &clock);
4842         if (!ok && !intel_crtc->config.clock_set) {
4843                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4844                 return -EINVAL;
4845         }
4846
4847         /* Ensure that the cursor is valid for the new mode before changing... */
4848         intel_crtc_update_cursor(crtc, true);
4849
4850         if (is_lvds && dev_priv->lvds_downclock_avail) {
4851                 /*
4852                  * Ensure we match the reduced clock's P to the target clock.
4853                  * If the clocks don't match, we can't switch the display clock
4854                  * by using the FP0/FP1. In such case we will disable the LVDS
4855                  * downclock feature.
4856                 */
4857                 has_reduced_clock =
4858                         dev_priv->display.find_dpll(limit, crtc,
4859                                                     dev_priv->lvds_downclock,
4860                                                     refclk, &clock,
4861                                                     &reduced_clock);
4862         }
4863         /* Compat-code for transition, will disappear. */
4864         if (!intel_crtc->config.clock_set) {
4865                 intel_crtc->config.dpll.n = clock.n;
4866                 intel_crtc->config.dpll.m1 = clock.m1;
4867                 intel_crtc->config.dpll.m2 = clock.m2;
4868                 intel_crtc->config.dpll.p1 = clock.p1;
4869                 intel_crtc->config.dpll.p2 = clock.p2;
4870         }
4871
4872         if (IS_GEN2(dev))
4873                 i8xx_update_pll(intel_crtc,
4874                                 has_reduced_clock ? &reduced_clock : NULL,
4875                                 num_connectors);
4876         else if (IS_VALLEYVIEW(dev))
4877                 vlv_update_pll(intel_crtc);
4878         else
4879                 i9xx_update_pll(intel_crtc,
4880                                 has_reduced_clock ? &reduced_clock : NULL,
4881                                 num_connectors);
4882
4883         /* Set up the display plane register */
4884         dspcntr = DISPPLANE_GAMMA_ENABLE;
4885
4886         if (!IS_VALLEYVIEW(dev)) {
4887                 if (pipe == 0)
4888                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4889                 else
4890                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4891         }
4892
4893         intel_set_pipe_timings(intel_crtc);
4894
4895         /* pipesrc and dspsize control the size that is scaled from,
4896          * which should always be the user's requested size.
4897          */
4898         I915_WRITE(DSPSIZE(plane),
4899                    ((mode->vdisplay - 1) << 16) |
4900                    (mode->hdisplay - 1));
4901         I915_WRITE(DSPPOS(plane), 0);
4902
4903         i9xx_set_pipeconf(intel_crtc);
4904
4905         I915_WRITE(DSPCNTR(plane), dspcntr);
4906         POSTING_READ(DSPCNTR(plane));
4907
4908         ret = intel_pipe_set_base(crtc, x, y, fb);
4909
4910         intel_update_watermarks(dev);
4911
4912         return ret;
4913 }
4914
4915 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4916                                  struct intel_crtc_config *pipe_config)
4917 {
4918         struct drm_device *dev = crtc->base.dev;
4919         struct drm_i915_private *dev_priv = dev->dev_private;
4920         uint32_t tmp;
4921
4922         tmp = I915_READ(PFIT_CONTROL);
4923
4924         if (INTEL_INFO(dev)->gen < 4) {
4925                 if (crtc->pipe != PIPE_B)
4926                         return;
4927
4928                 /* gen2/3 store dither state in pfit control, needs to match */
4929                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4930         } else {
4931                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4932                         return;
4933         }
4934
4935         if (!(tmp & PFIT_ENABLE))
4936                 return;
4937
4938         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4939         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4940         if (INTEL_INFO(dev)->gen < 5)
4941                 pipe_config->gmch_pfit.lvds_border_bits =
4942                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4943 }
4944
4945 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4946                                  struct intel_crtc_config *pipe_config)
4947 {
4948         struct drm_device *dev = crtc->base.dev;
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         uint32_t tmp;
4951
4952         pipe_config->cpu_transcoder = crtc->pipe;
4953         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4954
4955         tmp = I915_READ(PIPECONF(crtc->pipe));
4956         if (!(tmp & PIPECONF_ENABLE))
4957                 return false;
4958
4959         intel_get_pipe_timings(crtc, pipe_config);
4960
4961         i9xx_get_pfit_config(crtc, pipe_config);
4962
4963         if (INTEL_INFO(dev)->gen >= 4) {
4964                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4965                 pipe_config->pixel_multiplier =
4966                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4967                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4968         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4969                 tmp = I915_READ(DPLL(crtc->pipe));
4970                 pipe_config->pixel_multiplier =
4971                         ((tmp & SDVO_MULTIPLIER_MASK)
4972                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4973         } else {
4974                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4975                  * port and will be fixed up in the encoder->get_config
4976                  * function. */
4977                 pipe_config->pixel_multiplier = 1;
4978         }
4979
4980         return true;
4981 }
4982
4983 static void ironlake_init_pch_refclk(struct drm_device *dev)
4984 {
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986         struct drm_mode_config *mode_config = &dev->mode_config;
4987         struct intel_encoder *encoder;
4988         u32 val, final;
4989         bool has_lvds = false;
4990         bool has_cpu_edp = false;
4991         bool has_panel = false;
4992         bool has_ck505 = false;
4993         bool can_ssc = false;
4994
4995         /* We need to take the global config into account */
4996         list_for_each_entry(encoder, &mode_config->encoder_list,
4997                             base.head) {
4998                 switch (encoder->type) {
4999                 case INTEL_OUTPUT_LVDS:
5000                         has_panel = true;
5001                         has_lvds = true;
5002                         break;
5003                 case INTEL_OUTPUT_EDP:
5004                         has_panel = true;
5005                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5006                                 has_cpu_edp = true;
5007                         break;
5008                 }
5009         }
5010
5011         if (HAS_PCH_IBX(dev)) {
5012                 has_ck505 = dev_priv->vbt.display_clock_mode;
5013                 can_ssc = has_ck505;
5014         } else {
5015                 has_ck505 = false;
5016                 can_ssc = true;
5017         }
5018
5019         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5020                       has_panel, has_lvds, has_ck505);
5021
5022         /* Ironlake: try to setup display ref clock before DPLL
5023          * enabling. This is only under driver's control after
5024          * PCH B stepping, previous chipset stepping should be
5025          * ignoring this setting.
5026          */
5027         val = I915_READ(PCH_DREF_CONTROL);
5028
5029         /* As we must carefully and slowly disable/enable each source in turn,
5030          * compute the final state we want first and check if we need to
5031          * make any changes at all.
5032          */
5033         final = val;
5034         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5035         if (has_ck505)
5036                 final |= DREF_NONSPREAD_CK505_ENABLE;
5037         else
5038                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5039
5040         final &= ~DREF_SSC_SOURCE_MASK;
5041         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5042         final &= ~DREF_SSC1_ENABLE;
5043
5044         if (has_panel) {
5045                 final |= DREF_SSC_SOURCE_ENABLE;
5046
5047                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5048                         final |= DREF_SSC1_ENABLE;
5049
5050                 if (has_cpu_edp) {
5051                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5052                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5053                         else
5054                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5055                 } else
5056                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5057         } else {
5058                 final |= DREF_SSC_SOURCE_DISABLE;
5059                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5060         }
5061
5062         if (final == val)
5063                 return;
5064
5065         /* Always enable nonspread source */
5066         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5067
5068         if (has_ck505)
5069                 val |= DREF_NONSPREAD_CK505_ENABLE;
5070         else
5071                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5072
5073         if (has_panel) {
5074                 val &= ~DREF_SSC_SOURCE_MASK;
5075                 val |= DREF_SSC_SOURCE_ENABLE;
5076
5077                 /* SSC must be turned on before enabling the CPU output  */
5078                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5079                         DRM_DEBUG_KMS("Using SSC on panel\n");
5080                         val |= DREF_SSC1_ENABLE;
5081                 } else
5082                         val &= ~DREF_SSC1_ENABLE;
5083
5084                 /* Get SSC going before enabling the outputs */
5085                 I915_WRITE(PCH_DREF_CONTROL, val);
5086                 POSTING_READ(PCH_DREF_CONTROL);
5087                 udelay(200);
5088
5089                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5090
5091                 /* Enable CPU source on CPU attached eDP */
5092                 if (has_cpu_edp) {
5093                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5094                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5095                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5096                         }
5097                         else
5098                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5099                 } else
5100                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5101
5102                 I915_WRITE(PCH_DREF_CONTROL, val);
5103                 POSTING_READ(PCH_DREF_CONTROL);
5104                 udelay(200);
5105         } else {
5106                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5107
5108                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5109
5110                 /* Turn off CPU output */
5111                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5112
5113                 I915_WRITE(PCH_DREF_CONTROL, val);
5114                 POSTING_READ(PCH_DREF_CONTROL);
5115                 udelay(200);
5116
5117                 /* Turn off the SSC source */
5118                 val &= ~DREF_SSC_SOURCE_MASK;
5119                 val |= DREF_SSC_SOURCE_DISABLE;
5120
5121                 /* Turn off SSC1 */
5122                 val &= ~DREF_SSC1_ENABLE;
5123
5124                 I915_WRITE(PCH_DREF_CONTROL, val);
5125                 POSTING_READ(PCH_DREF_CONTROL);
5126                 udelay(200);
5127         }
5128
5129         BUG_ON(val != final);
5130 }
5131
5132 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5133 static void lpt_init_pch_refclk(struct drm_device *dev)
5134 {
5135         struct drm_i915_private *dev_priv = dev->dev_private;
5136         struct drm_mode_config *mode_config = &dev->mode_config;
5137         struct intel_encoder *encoder;
5138         bool has_vga = false;
5139         bool is_sdv = false;
5140         u32 tmp;
5141
5142         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5143                 switch (encoder->type) {
5144                 case INTEL_OUTPUT_ANALOG:
5145                         has_vga = true;
5146                         break;
5147                 }
5148         }
5149
5150         if (!has_vga)
5151                 return;
5152
5153         mutex_lock(&dev_priv->dpio_lock);
5154
5155         /* XXX: Rip out SDV support once Haswell ships for real. */
5156         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5157                 is_sdv = true;
5158
5159         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5160         tmp &= ~SBI_SSCCTL_DISABLE;
5161         tmp |= SBI_SSCCTL_PATHALT;
5162         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5163
5164         udelay(24);
5165
5166         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5167         tmp &= ~SBI_SSCCTL_PATHALT;
5168         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5169
5170         if (!is_sdv) {
5171                 tmp = I915_READ(SOUTH_CHICKEN2);
5172                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5173                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5174
5175                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5176                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5177                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5178
5179                 tmp = I915_READ(SOUTH_CHICKEN2);
5180                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5181                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5182
5183                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5184                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5185                                        100))
5186                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5187         }
5188
5189         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5190         tmp &= ~(0xFF << 24);
5191         tmp |= (0x12 << 24);
5192         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5193
5194         if (is_sdv) {
5195                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5196                 tmp |= 0x7FFF;
5197                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5198         }
5199
5200         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5201         tmp |= (1 << 11);
5202         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5203
5204         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5205         tmp |= (1 << 11);
5206         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5207
5208         if (is_sdv) {
5209                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5210                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5211                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5212
5213                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5214                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5215                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5216
5217                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5218                 tmp |= (0x3F << 8);
5219                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5220
5221                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5222                 tmp |= (0x3F << 8);
5223                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5224         }
5225
5226         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5227         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5228         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5229
5230         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5231         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5232         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5233
5234         if (!is_sdv) {
5235                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5236                 tmp &= ~(7 << 13);
5237                 tmp |= (5 << 13);
5238                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5239
5240                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5241                 tmp &= ~(7 << 13);
5242                 tmp |= (5 << 13);
5243                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5244         }
5245
5246         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5247         tmp &= ~0xFF;
5248         tmp |= 0x1C;
5249         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5252         tmp &= ~0xFF;
5253         tmp |= 0x1C;
5254         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5255
5256         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5257         tmp &= ~(0xFF << 16);
5258         tmp |= (0x1C << 16);
5259         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5260
5261         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5262         tmp &= ~(0xFF << 16);
5263         tmp |= (0x1C << 16);
5264         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5265
5266         if (!is_sdv) {
5267                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5268                 tmp |= (1 << 27);
5269                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5270
5271                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5272                 tmp |= (1 << 27);
5273                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5274
5275                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5276                 tmp &= ~(0xF << 28);
5277                 tmp |= (4 << 28);
5278                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5279
5280                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5281                 tmp &= ~(0xF << 28);
5282                 tmp |= (4 << 28);
5283                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5284         }
5285
5286         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5287         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5288         tmp |= SBI_DBUFF0_ENABLE;
5289         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5290
5291         mutex_unlock(&dev_priv->dpio_lock);
5292 }
5293
5294 /*
5295  * Initialize reference clocks when the driver loads
5296  */
5297 void intel_init_pch_refclk(struct drm_device *dev)
5298 {
5299         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5300                 ironlake_init_pch_refclk(dev);
5301         else if (HAS_PCH_LPT(dev))
5302                 lpt_init_pch_refclk(dev);
5303 }
5304
5305 static int ironlake_get_refclk(struct drm_crtc *crtc)
5306 {
5307         struct drm_device *dev = crtc->dev;
5308         struct drm_i915_private *dev_priv = dev->dev_private;
5309         struct intel_encoder *encoder;
5310         int num_connectors = 0;
5311         bool is_lvds = false;
5312
5313         for_each_encoder_on_crtc(dev, crtc, encoder) {
5314                 switch (encoder->type) {
5315                 case INTEL_OUTPUT_LVDS:
5316                         is_lvds = true;
5317                         break;
5318                 }
5319                 num_connectors++;
5320         }
5321
5322         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5323                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5324                               dev_priv->vbt.lvds_ssc_freq);
5325                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5326         }
5327
5328         return 120000;
5329 }
5330
5331 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5332 {
5333         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5335         int pipe = intel_crtc->pipe;
5336         uint32_t val;
5337
5338         val = 0;
5339
5340         switch (intel_crtc->config.pipe_bpp) {
5341         case 18:
5342                 val |= PIPECONF_6BPC;
5343                 break;
5344         case 24:
5345                 val |= PIPECONF_8BPC;
5346                 break;
5347         case 30:
5348                 val |= PIPECONF_10BPC;
5349                 break;
5350         case 36:
5351                 val |= PIPECONF_12BPC;
5352                 break;
5353         default:
5354                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5355                 BUG();
5356         }
5357
5358         if (intel_crtc->config.dither)
5359                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5360
5361         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5362                 val |= PIPECONF_INTERLACED_ILK;
5363         else
5364                 val |= PIPECONF_PROGRESSIVE;
5365
5366         if (intel_crtc->config.limited_color_range)
5367                 val |= PIPECONF_COLOR_RANGE_SELECT;
5368
5369         I915_WRITE(PIPECONF(pipe), val);
5370         POSTING_READ(PIPECONF(pipe));
5371 }
5372
5373 /*
5374  * Set up the pipe CSC unit.
5375  *
5376  * Currently only full range RGB to limited range RGB conversion
5377  * is supported, but eventually this should handle various
5378  * RGB<->YCbCr scenarios as well.
5379  */
5380 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5381 {
5382         struct drm_device *dev = crtc->dev;
5383         struct drm_i915_private *dev_priv = dev->dev_private;
5384         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5385         int pipe = intel_crtc->pipe;
5386         uint16_t coeff = 0x7800; /* 1.0 */
5387
5388         /*
5389          * TODO: Check what kind of values actually come out of the pipe
5390          * with these coeff/postoff values and adjust to get the best
5391          * accuracy. Perhaps we even need to take the bpc value into
5392          * consideration.
5393          */
5394
5395         if (intel_crtc->config.limited_color_range)
5396                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5397
5398         /*
5399          * GY/GU and RY/RU should be the other way around according
5400          * to BSpec, but reality doesn't agree. Just set them up in
5401          * a way that results in the correct picture.
5402          */
5403         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5404         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5405
5406         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5407         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5408
5409         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5410         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5411
5412         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5413         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5414         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5415
5416         if (INTEL_INFO(dev)->gen > 6) {
5417                 uint16_t postoff = 0;
5418
5419                 if (intel_crtc->config.limited_color_range)
5420                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5421
5422                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5423                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5424                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5425
5426                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5427         } else {
5428                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5429
5430                 if (intel_crtc->config.limited_color_range)
5431                         mode |= CSC_BLACK_SCREEN_OFFSET;
5432
5433                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5434         }
5435 }
5436
5437 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5438 {
5439         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5441         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5442         uint32_t val;
5443
5444         val = 0;
5445
5446         if (intel_crtc->config.dither)
5447                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5448
5449         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5450                 val |= PIPECONF_INTERLACED_ILK;
5451         else
5452                 val |= PIPECONF_PROGRESSIVE;
5453
5454         I915_WRITE(PIPECONF(cpu_transcoder), val);
5455         POSTING_READ(PIPECONF(cpu_transcoder));
5456
5457         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5458         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5459 }
5460
5461 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5462                                     intel_clock_t *clock,
5463                                     bool *has_reduced_clock,
5464                                     intel_clock_t *reduced_clock)
5465 {
5466         struct drm_device *dev = crtc->dev;
5467         struct drm_i915_private *dev_priv = dev->dev_private;
5468         struct intel_encoder *intel_encoder;
5469         int refclk;
5470         const intel_limit_t *limit;
5471         bool ret, is_lvds = false;
5472
5473         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5474                 switch (intel_encoder->type) {
5475                 case INTEL_OUTPUT_LVDS:
5476                         is_lvds = true;
5477                         break;
5478                 }
5479         }
5480
5481         refclk = ironlake_get_refclk(crtc);
5482
5483         /*
5484          * Returns a set of divisors for the desired target clock with the given
5485          * refclk, or FALSE.  The returned values represent the clock equation:
5486          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5487          */
5488         limit = intel_limit(crtc, refclk);
5489         ret = dev_priv->display.find_dpll(limit, crtc,
5490                                           to_intel_crtc(crtc)->config.port_clock,
5491                                           refclk, NULL, clock);
5492         if (!ret)
5493                 return false;
5494
5495         if (is_lvds && dev_priv->lvds_downclock_avail) {
5496                 /*
5497                  * Ensure we match the reduced clock's P to the target clock.
5498                  * If the clocks don't match, we can't switch the display clock
5499                  * by using the FP0/FP1. In such case we will disable the LVDS
5500                  * downclock feature.
5501                 */
5502                 *has_reduced_clock =
5503                         dev_priv->display.find_dpll(limit, crtc,
5504                                                     dev_priv->lvds_downclock,
5505                                                     refclk, clock,
5506                                                     reduced_clock);
5507         }
5508
5509         return true;
5510 }
5511
5512 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5513 {
5514         struct drm_i915_private *dev_priv = dev->dev_private;
5515         uint32_t temp;
5516
5517         temp = I915_READ(SOUTH_CHICKEN1);
5518         if (temp & FDI_BC_BIFURCATION_SELECT)
5519                 return;
5520
5521         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5522         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5523
5524         temp |= FDI_BC_BIFURCATION_SELECT;
5525         DRM_DEBUG_KMS("enabling fdi C rx\n");
5526         I915_WRITE(SOUTH_CHICKEN1, temp);
5527         POSTING_READ(SOUTH_CHICKEN1);
5528 }
5529
5530 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5531 {
5532         struct drm_device *dev = intel_crtc->base.dev;
5533         struct drm_i915_private *dev_priv = dev->dev_private;
5534
5535         switch (intel_crtc->pipe) {
5536         case PIPE_A:
5537                 break;
5538         case PIPE_B:
5539                 if (intel_crtc->config.fdi_lanes > 2)
5540                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5541                 else
5542                         cpt_enable_fdi_bc_bifurcation(dev);
5543
5544                 break;
5545         case PIPE_C:
5546                 cpt_enable_fdi_bc_bifurcation(dev);
5547
5548                 break;
5549         default:
5550                 BUG();
5551         }
5552 }
5553
5554 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5555 {
5556         /*
5557          * Account for spread spectrum to avoid
5558          * oversubscribing the link. Max center spread
5559          * is 2.5%; use 5% for safety's sake.
5560          */
5561         u32 bps = target_clock * bpp * 21 / 20;
5562         return bps / (link_bw * 8) + 1;
5563 }
5564
5565 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5566 {
5567         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5568 }
5569
5570 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5571                                       u32 *fp,
5572                                       intel_clock_t *reduced_clock, u32 *fp2)
5573 {
5574         struct drm_crtc *crtc = &intel_crtc->base;
5575         struct drm_device *dev = crtc->dev;
5576         struct drm_i915_private *dev_priv = dev->dev_private;
5577         struct intel_encoder *intel_encoder;
5578         uint32_t dpll;
5579         int factor, num_connectors = 0;
5580         bool is_lvds = false, is_sdvo = false;
5581
5582         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5583                 switch (intel_encoder->type) {
5584                 case INTEL_OUTPUT_LVDS:
5585                         is_lvds = true;
5586                         break;
5587                 case INTEL_OUTPUT_SDVO:
5588                 case INTEL_OUTPUT_HDMI:
5589                         is_sdvo = true;
5590                         break;
5591                 }
5592
5593                 num_connectors++;
5594         }
5595
5596         /* Enable autotuning of the PLL clock (if permissible) */
5597         factor = 21;
5598         if (is_lvds) {
5599                 if ((intel_panel_use_ssc(dev_priv) &&
5600                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5601                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5602                         factor = 25;
5603         } else if (intel_crtc->config.sdvo_tv_clock)
5604                 factor = 20;
5605
5606         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5607                 *fp |= FP_CB_TUNE;
5608
5609         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5610                 *fp2 |= FP_CB_TUNE;
5611
5612         dpll = 0;
5613
5614         if (is_lvds)
5615                 dpll |= DPLLB_MODE_LVDS;
5616         else
5617                 dpll |= DPLLB_MODE_DAC_SERIAL;
5618
5619         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5620                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5621
5622         if (is_sdvo)
5623                 dpll |= DPLL_DVO_HIGH_SPEED;
5624         if (intel_crtc->config.has_dp_encoder)
5625                 dpll |= DPLL_DVO_HIGH_SPEED;
5626
5627         /* compute bitmask from p1 value */
5628         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5629         /* also FPA1 */
5630         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5631
5632         switch (intel_crtc->config.dpll.p2) {
5633         case 5:
5634                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5635                 break;
5636         case 7:
5637                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5638                 break;
5639         case 10:
5640                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5641                 break;
5642         case 14:
5643                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5644                 break;
5645         }
5646
5647         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5648                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5649         else
5650                 dpll |= PLL_REF_INPUT_DREFCLK;
5651
5652         return dpll | DPLL_VCO_ENABLE;
5653 }
5654
5655 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5656                                   int x, int y,
5657                                   struct drm_framebuffer *fb)
5658 {
5659         struct drm_device *dev = crtc->dev;
5660         struct drm_i915_private *dev_priv = dev->dev_private;
5661         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5662         int pipe = intel_crtc->pipe;
5663         int plane = intel_crtc->plane;
5664         int num_connectors = 0;
5665         intel_clock_t clock, reduced_clock;
5666         u32 dpll = 0, fp = 0, fp2 = 0;
5667         bool ok, has_reduced_clock = false;
5668         bool is_lvds = false;
5669         struct intel_encoder *encoder;
5670         struct intel_shared_dpll *pll;
5671         int ret;
5672
5673         for_each_encoder_on_crtc(dev, crtc, encoder) {
5674                 switch (encoder->type) {
5675                 case INTEL_OUTPUT_LVDS:
5676                         is_lvds = true;
5677                         break;
5678                 }
5679
5680                 num_connectors++;
5681         }
5682
5683         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5684              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5685
5686         ok = ironlake_compute_clocks(crtc, &clock,
5687                                      &has_reduced_clock, &reduced_clock);
5688         if (!ok && !intel_crtc->config.clock_set) {
5689                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5690                 return -EINVAL;
5691         }
5692         /* Compat-code for transition, will disappear. */
5693         if (!intel_crtc->config.clock_set) {
5694                 intel_crtc->config.dpll.n = clock.n;
5695                 intel_crtc->config.dpll.m1 = clock.m1;
5696                 intel_crtc->config.dpll.m2 = clock.m2;
5697                 intel_crtc->config.dpll.p1 = clock.p1;
5698                 intel_crtc->config.dpll.p2 = clock.p2;
5699         }
5700
5701         /* Ensure that the cursor is valid for the new mode before changing... */
5702         intel_crtc_update_cursor(crtc, true);
5703
5704         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5705         if (intel_crtc->config.has_pch_encoder) {
5706                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5707                 if (has_reduced_clock)
5708                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5709
5710                 dpll = ironlake_compute_dpll(intel_crtc,
5711                                              &fp, &reduced_clock,
5712                                              has_reduced_clock ? &fp2 : NULL);
5713
5714                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5715                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5716                 if (has_reduced_clock)
5717                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5718                 else
5719                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5720
5721                 pll = intel_get_shared_dpll(intel_crtc);
5722                 if (pll == NULL) {
5723                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5724                                          pipe_name(pipe));
5725                         return -EINVAL;
5726                 }
5727         } else
5728                 intel_put_shared_dpll(intel_crtc);
5729
5730         if (intel_crtc->config.has_dp_encoder)
5731                 intel_dp_set_m_n(intel_crtc);
5732
5733         if (is_lvds && has_reduced_clock && i915_powersave)
5734                 intel_crtc->lowfreq_avail = true;
5735         else
5736                 intel_crtc->lowfreq_avail = false;
5737
5738         if (intel_crtc->config.has_pch_encoder) {
5739                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5740
5741         }
5742
5743         intel_set_pipe_timings(intel_crtc);
5744
5745         if (intel_crtc->config.has_pch_encoder) {
5746                 intel_cpu_transcoder_set_m_n(intel_crtc,
5747                                              &intel_crtc->config.fdi_m_n);
5748         }
5749
5750         if (IS_IVYBRIDGE(dev))
5751                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5752
5753         ironlake_set_pipeconf(crtc);
5754
5755         /* Set up the display plane register */
5756         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5757         POSTING_READ(DSPCNTR(plane));
5758
5759         ret = intel_pipe_set_base(crtc, x, y, fb);
5760
5761         intel_update_watermarks(dev);
5762
5763         return ret;
5764 }
5765
5766 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5767                                         struct intel_crtc_config *pipe_config)
5768 {
5769         struct drm_device *dev = crtc->base.dev;
5770         struct drm_i915_private *dev_priv = dev->dev_private;
5771         enum transcoder transcoder = pipe_config->cpu_transcoder;
5772
5773         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5774         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5775         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5776                                         & ~TU_SIZE_MASK;
5777         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5778         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5779                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5780 }
5781
5782 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5783                                      struct intel_crtc_config *pipe_config)
5784 {
5785         struct drm_device *dev = crtc->base.dev;
5786         struct drm_i915_private *dev_priv = dev->dev_private;
5787         uint32_t tmp;
5788
5789         tmp = I915_READ(PF_CTL(crtc->pipe));
5790
5791         if (tmp & PF_ENABLE) {
5792                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5793                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5794
5795                 /* We currently do not free assignements of panel fitters on
5796                  * ivb/hsw (since we don't use the higher upscaling modes which
5797                  * differentiates them) so just WARN about this case for now. */
5798                 if (IS_GEN7(dev)) {
5799                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5800                                 PF_PIPE_SEL_IVB(crtc->pipe));
5801                 }
5802         }
5803 }
5804
5805 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5806                                      struct intel_crtc_config *pipe_config)
5807 {
5808         struct drm_device *dev = crtc->base.dev;
5809         struct drm_i915_private *dev_priv = dev->dev_private;
5810         uint32_t tmp;
5811
5812         pipe_config->cpu_transcoder = crtc->pipe;
5813         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5814
5815         tmp = I915_READ(PIPECONF(crtc->pipe));
5816         if (!(tmp & PIPECONF_ENABLE))
5817                 return false;
5818
5819         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5820                 struct intel_shared_dpll *pll;
5821
5822                 pipe_config->has_pch_encoder = true;
5823
5824                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5825                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5826                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5827
5828                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5829
5830                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5831                  * since we don't have state tracking for pch clocks yet. */
5832                 pipe_config->pixel_multiplier = 1;
5833
5834                 if (HAS_PCH_IBX(dev_priv->dev)) {
5835                         pipe_config->shared_dpll = crtc->pipe;
5836                 } else {
5837                         tmp = I915_READ(PCH_DPLL_SEL);
5838                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5839                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5840                         else
5841                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5842                 }
5843
5844                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5845
5846                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5847                                            &pipe_config->dpll_hw_state));
5848         } else {
5849                 pipe_config->pixel_multiplier = 1;
5850         }
5851
5852         intel_get_pipe_timings(crtc, pipe_config);
5853
5854         ironlake_get_pfit_config(crtc, pipe_config);
5855
5856         return true;
5857 }
5858
5859 static void haswell_modeset_global_resources(struct drm_device *dev)
5860 {
5861         bool enable = false;
5862         struct intel_crtc *crtc;
5863
5864         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5865                 if (!crtc->base.enabled)
5866                         continue;
5867
5868                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5869                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5870                         enable = true;
5871         }
5872
5873         intel_set_power_well(dev, enable);
5874 }
5875
5876 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5877                                  int x, int y,
5878                                  struct drm_framebuffer *fb)
5879 {
5880         struct drm_device *dev = crtc->dev;
5881         struct drm_i915_private *dev_priv = dev->dev_private;
5882         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5883         int plane = intel_crtc->plane;
5884         int ret;
5885
5886         if (!intel_ddi_pll_mode_set(crtc))
5887                 return -EINVAL;
5888
5889         /* Ensure that the cursor is valid for the new mode before changing... */
5890         intel_crtc_update_cursor(crtc, true);
5891
5892         if (intel_crtc->config.has_dp_encoder)
5893                 intel_dp_set_m_n(intel_crtc);
5894
5895         intel_crtc->lowfreq_avail = false;
5896
5897         intel_set_pipe_timings(intel_crtc);
5898
5899         if (intel_crtc->config.has_pch_encoder) {
5900                 intel_cpu_transcoder_set_m_n(intel_crtc,
5901                                              &intel_crtc->config.fdi_m_n);
5902         }
5903
5904         haswell_set_pipeconf(crtc);
5905
5906         intel_set_pipe_csc(crtc);
5907
5908         /* Set up the display plane register */
5909         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5910         POSTING_READ(DSPCNTR(plane));
5911
5912         ret = intel_pipe_set_base(crtc, x, y, fb);
5913
5914         intel_update_watermarks(dev);
5915
5916         return ret;
5917 }
5918
5919 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5920                                     struct intel_crtc_config *pipe_config)
5921 {
5922         struct drm_device *dev = crtc->base.dev;
5923         struct drm_i915_private *dev_priv = dev->dev_private;
5924         enum intel_display_power_domain pfit_domain;
5925         uint32_t tmp;
5926
5927         pipe_config->cpu_transcoder = crtc->pipe;
5928         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5929
5930         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5931         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5932                 enum pipe trans_edp_pipe;
5933                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5934                 default:
5935                         WARN(1, "unknown pipe linked to edp transcoder\n");
5936                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5937                 case TRANS_DDI_EDP_INPUT_A_ON:
5938                         trans_edp_pipe = PIPE_A;
5939                         break;
5940                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5941                         trans_edp_pipe = PIPE_B;
5942                         break;
5943                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5944                         trans_edp_pipe = PIPE_C;
5945                         break;
5946                 }
5947
5948                 if (trans_edp_pipe == crtc->pipe)
5949                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5950         }
5951
5952         if (!intel_display_power_enabled(dev,
5953                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5954                 return false;
5955
5956         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5957         if (!(tmp & PIPECONF_ENABLE))
5958                 return false;
5959
5960         /*
5961          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5962          * DDI E. So just check whether this pipe is wired to DDI E and whether
5963          * the PCH transcoder is on.
5964          */
5965         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5966         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5967             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5968                 pipe_config->has_pch_encoder = true;
5969
5970                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5971                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5972                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5973
5974                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5975         }
5976
5977         intel_get_pipe_timings(crtc, pipe_config);
5978
5979         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5980         if (intel_display_power_enabled(dev, pfit_domain))
5981                 ironlake_get_pfit_config(crtc, pipe_config);
5982
5983         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5984                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
5985
5986         pipe_config->pixel_multiplier = 1;
5987
5988         return true;
5989 }
5990
5991 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5992                                int x, int y,
5993                                struct drm_framebuffer *fb)
5994 {
5995         struct drm_device *dev = crtc->dev;
5996         struct drm_i915_private *dev_priv = dev->dev_private;
5997         struct drm_encoder_helper_funcs *encoder_funcs;
5998         struct intel_encoder *encoder;
5999         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000         struct drm_display_mode *adjusted_mode =
6001                 &intel_crtc->config.adjusted_mode;
6002         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6003         int pipe = intel_crtc->pipe;
6004         int ret;
6005
6006         drm_vblank_pre_modeset(dev, pipe);
6007
6008         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6009
6010         drm_vblank_post_modeset(dev, pipe);
6011
6012         if (ret != 0)
6013                 return ret;
6014
6015         for_each_encoder_on_crtc(dev, crtc, encoder) {
6016                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6017                         encoder->base.base.id,
6018                         drm_get_encoder_name(&encoder->base),
6019                         mode->base.id, mode->name);
6020                 if (encoder->mode_set) {
6021                         encoder->mode_set(encoder);
6022                 } else {
6023                         encoder_funcs = encoder->base.helper_private;
6024                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6025                 }
6026         }
6027
6028         return 0;
6029 }
6030
6031 static bool intel_eld_uptodate(struct drm_connector *connector,
6032                                int reg_eldv, uint32_t bits_eldv,
6033                                int reg_elda, uint32_t bits_elda,
6034                                int reg_edid)
6035 {
6036         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6037         uint8_t *eld = connector->eld;
6038         uint32_t i;
6039
6040         i = I915_READ(reg_eldv);
6041         i &= bits_eldv;
6042
6043         if (!eld[0])
6044                 return !i;
6045
6046         if (!i)
6047                 return false;
6048
6049         i = I915_READ(reg_elda);
6050         i &= ~bits_elda;
6051         I915_WRITE(reg_elda, i);
6052
6053         for (i = 0; i < eld[2]; i++)
6054                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6055                         return false;
6056
6057         return true;
6058 }
6059
6060 static void g4x_write_eld(struct drm_connector *connector,
6061                           struct drm_crtc *crtc)
6062 {
6063         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6064         uint8_t *eld = connector->eld;
6065         uint32_t eldv;
6066         uint32_t len;
6067         uint32_t i;
6068
6069         i = I915_READ(G4X_AUD_VID_DID);
6070
6071         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6072                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6073         else
6074                 eldv = G4X_ELDV_DEVCTG;
6075
6076         if (intel_eld_uptodate(connector,
6077                                G4X_AUD_CNTL_ST, eldv,
6078                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6079                                G4X_HDMIW_HDMIEDID))
6080                 return;
6081
6082         i = I915_READ(G4X_AUD_CNTL_ST);
6083         i &= ~(eldv | G4X_ELD_ADDR);
6084         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6085         I915_WRITE(G4X_AUD_CNTL_ST, i);
6086
6087         if (!eld[0])
6088                 return;
6089
6090         len = min_t(uint8_t, eld[2], len);
6091         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6092         for (i = 0; i < len; i++)
6093                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6094
6095         i = I915_READ(G4X_AUD_CNTL_ST);
6096         i |= eldv;
6097         I915_WRITE(G4X_AUD_CNTL_ST, i);
6098 }
6099
6100 static void haswell_write_eld(struct drm_connector *connector,
6101                                      struct drm_crtc *crtc)
6102 {
6103         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6104         uint8_t *eld = connector->eld;
6105         struct drm_device *dev = crtc->dev;
6106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6107         uint32_t eldv;
6108         uint32_t i;
6109         int len;
6110         int pipe = to_intel_crtc(crtc)->pipe;
6111         int tmp;
6112
6113         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6114         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6115         int aud_config = HSW_AUD_CFG(pipe);
6116         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6117
6118
6119         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6120
6121         /* Audio output enable */
6122         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6123         tmp = I915_READ(aud_cntrl_st2);
6124         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6125         I915_WRITE(aud_cntrl_st2, tmp);
6126
6127         /* Wait for 1 vertical blank */
6128         intel_wait_for_vblank(dev, pipe);
6129
6130         /* Set ELD valid state */
6131         tmp = I915_READ(aud_cntrl_st2);
6132         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6133         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6134         I915_WRITE(aud_cntrl_st2, tmp);
6135         tmp = I915_READ(aud_cntrl_st2);
6136         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6137
6138         /* Enable HDMI mode */
6139         tmp = I915_READ(aud_config);
6140         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6141         /* clear N_programing_enable and N_value_index */
6142         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6143         I915_WRITE(aud_config, tmp);
6144
6145         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6146
6147         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6148         intel_crtc->eld_vld = true;
6149
6150         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6151                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6152                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6153                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6154         } else
6155                 I915_WRITE(aud_config, 0);
6156
6157         if (intel_eld_uptodate(connector,
6158                                aud_cntrl_st2, eldv,
6159                                aud_cntl_st, IBX_ELD_ADDRESS,
6160                                hdmiw_hdmiedid))
6161                 return;
6162
6163         i = I915_READ(aud_cntrl_st2);
6164         i &= ~eldv;
6165         I915_WRITE(aud_cntrl_st2, i);
6166
6167         if (!eld[0])
6168                 return;
6169
6170         i = I915_READ(aud_cntl_st);
6171         i &= ~IBX_ELD_ADDRESS;
6172         I915_WRITE(aud_cntl_st, i);
6173         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6174         DRM_DEBUG_DRIVER("port num:%d\n", i);
6175
6176         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6177         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6178         for (i = 0; i < len; i++)
6179                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6180
6181         i = I915_READ(aud_cntrl_st2);
6182         i |= eldv;
6183         I915_WRITE(aud_cntrl_st2, i);
6184
6185 }
6186
6187 static void ironlake_write_eld(struct drm_connector *connector,
6188                                      struct drm_crtc *crtc)
6189 {
6190         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6191         uint8_t *eld = connector->eld;
6192         uint32_t eldv;
6193         uint32_t i;
6194         int len;
6195         int hdmiw_hdmiedid;
6196         int aud_config;
6197         int aud_cntl_st;
6198         int aud_cntrl_st2;
6199         int pipe = to_intel_crtc(crtc)->pipe;
6200
6201         if (HAS_PCH_IBX(connector->dev)) {
6202                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6203                 aud_config = IBX_AUD_CFG(pipe);
6204                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6205                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6206         } else {
6207                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6208                 aud_config = CPT_AUD_CFG(pipe);
6209                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6210                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6211         }
6212
6213         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6214
6215         i = I915_READ(aud_cntl_st);
6216         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6217         if (!i) {
6218                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6219                 /* operate blindly on all ports */
6220                 eldv = IBX_ELD_VALIDB;
6221                 eldv |= IBX_ELD_VALIDB << 4;
6222                 eldv |= IBX_ELD_VALIDB << 8;
6223         } else {
6224                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6225                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6226         }
6227
6228         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6229                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6230                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6231                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6232         } else
6233                 I915_WRITE(aud_config, 0);
6234
6235         if (intel_eld_uptodate(connector,
6236                                aud_cntrl_st2, eldv,
6237                                aud_cntl_st, IBX_ELD_ADDRESS,
6238                                hdmiw_hdmiedid))
6239                 return;
6240
6241         i = I915_READ(aud_cntrl_st2);
6242         i &= ~eldv;
6243         I915_WRITE(aud_cntrl_st2, i);
6244
6245         if (!eld[0])
6246                 return;
6247
6248         i = I915_READ(aud_cntl_st);
6249         i &= ~IBX_ELD_ADDRESS;
6250         I915_WRITE(aud_cntl_st, i);
6251
6252         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6253         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6254         for (i = 0; i < len; i++)
6255                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6256
6257         i = I915_READ(aud_cntrl_st2);
6258         i |= eldv;
6259         I915_WRITE(aud_cntrl_st2, i);
6260 }
6261
6262 void intel_write_eld(struct drm_encoder *encoder,
6263                      struct drm_display_mode *mode)
6264 {
6265         struct drm_crtc *crtc = encoder->crtc;
6266         struct drm_connector *connector;
6267         struct drm_device *dev = encoder->dev;
6268         struct drm_i915_private *dev_priv = dev->dev_private;
6269
6270         connector = drm_select_eld(encoder, mode);
6271         if (!connector)
6272                 return;
6273
6274         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6275                          connector->base.id,
6276                          drm_get_connector_name(connector),
6277                          connector->encoder->base.id,
6278                          drm_get_encoder_name(connector->encoder));
6279
6280         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6281
6282         if (dev_priv->display.write_eld)
6283                 dev_priv->display.write_eld(connector, crtc);
6284 }
6285
6286 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6287 void intel_crtc_load_lut(struct drm_crtc *crtc)
6288 {
6289         struct drm_device *dev = crtc->dev;
6290         struct drm_i915_private *dev_priv = dev->dev_private;
6291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6292         enum pipe pipe = intel_crtc->pipe;
6293         int palreg = PALETTE(pipe);
6294         int i;
6295         bool reenable_ips = false;
6296
6297         /* The clocks have to be on to load the palette. */
6298         if (!crtc->enabled || !intel_crtc->active)
6299                 return;
6300
6301         if (!HAS_PCH_SPLIT(dev_priv->dev))
6302                 assert_pll_enabled(dev_priv, pipe);
6303
6304         /* use legacy palette for Ironlake */
6305         if (HAS_PCH_SPLIT(dev))
6306                 palreg = LGC_PALETTE(pipe);
6307
6308         /* Workaround : Do not read or write the pipe palette/gamma data while
6309          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6310          */
6311         if (intel_crtc->config.ips_enabled &&
6312             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6313              GAMMA_MODE_MODE_SPLIT)) {
6314                 hsw_disable_ips(intel_crtc);
6315                 reenable_ips = true;
6316         }
6317
6318         for (i = 0; i < 256; i++) {
6319                 I915_WRITE(palreg + 4 * i,
6320                            (intel_crtc->lut_r[i] << 16) |
6321                            (intel_crtc->lut_g[i] << 8) |
6322                            intel_crtc->lut_b[i]);
6323         }
6324
6325         if (reenable_ips)
6326                 hsw_enable_ips(intel_crtc);
6327 }
6328
6329 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6330 {
6331         struct drm_device *dev = crtc->dev;
6332         struct drm_i915_private *dev_priv = dev->dev_private;
6333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334         bool visible = base != 0;
6335         u32 cntl;
6336
6337         if (intel_crtc->cursor_visible == visible)
6338                 return;
6339
6340         cntl = I915_READ(_CURACNTR);
6341         if (visible) {
6342                 /* On these chipsets we can only modify the base whilst
6343                  * the cursor is disabled.
6344                  */
6345                 I915_WRITE(_CURABASE, base);
6346
6347                 cntl &= ~(CURSOR_FORMAT_MASK);
6348                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6349                 cntl |= CURSOR_ENABLE |
6350                         CURSOR_GAMMA_ENABLE |
6351                         CURSOR_FORMAT_ARGB;
6352         } else
6353                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6354         I915_WRITE(_CURACNTR, cntl);
6355
6356         intel_crtc->cursor_visible = visible;
6357 }
6358
6359 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6360 {
6361         struct drm_device *dev = crtc->dev;
6362         struct drm_i915_private *dev_priv = dev->dev_private;
6363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364         int pipe = intel_crtc->pipe;
6365         bool visible = base != 0;
6366
6367         if (intel_crtc->cursor_visible != visible) {
6368                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6369                 if (base) {
6370                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6371                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6372                         cntl |= pipe << 28; /* Connect to correct pipe */
6373                 } else {
6374                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6375                         cntl |= CURSOR_MODE_DISABLE;
6376                 }
6377                 I915_WRITE(CURCNTR(pipe), cntl);
6378
6379                 intel_crtc->cursor_visible = visible;
6380         }
6381         /* and commit changes on next vblank */
6382         I915_WRITE(CURBASE(pipe), base);
6383 }
6384
6385 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6386 {
6387         struct drm_device *dev = crtc->dev;
6388         struct drm_i915_private *dev_priv = dev->dev_private;
6389         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390         int pipe = intel_crtc->pipe;
6391         bool visible = base != 0;
6392
6393         if (intel_crtc->cursor_visible != visible) {
6394                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6395                 if (base) {
6396                         cntl &= ~CURSOR_MODE;
6397                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6398                 } else {
6399                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6400                         cntl |= CURSOR_MODE_DISABLE;
6401                 }
6402                 if (IS_HASWELL(dev))
6403                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6404                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6405
6406                 intel_crtc->cursor_visible = visible;
6407         }
6408         /* and commit changes on next vblank */
6409         I915_WRITE(CURBASE_IVB(pipe), base);
6410 }
6411
6412 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6413 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6414                                      bool on)
6415 {
6416         struct drm_device *dev = crtc->dev;
6417         struct drm_i915_private *dev_priv = dev->dev_private;
6418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419         int pipe = intel_crtc->pipe;
6420         int x = intel_crtc->cursor_x;
6421         int y = intel_crtc->cursor_y;
6422         u32 base, pos;
6423         bool visible;
6424
6425         pos = 0;
6426
6427         if (on && crtc->enabled && crtc->fb) {
6428                 base = intel_crtc->cursor_addr;
6429                 if (x > (int) crtc->fb->width)
6430                         base = 0;
6431
6432                 if (y > (int) crtc->fb->height)
6433                         base = 0;
6434         } else
6435                 base = 0;
6436
6437         if (x < 0) {
6438                 if (x + intel_crtc->cursor_width < 0)
6439                         base = 0;
6440
6441                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6442                 x = -x;
6443         }
6444         pos |= x << CURSOR_X_SHIFT;
6445
6446         if (y < 0) {
6447                 if (y + intel_crtc->cursor_height < 0)
6448                         base = 0;
6449
6450                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6451                 y = -y;
6452         }
6453         pos |= y << CURSOR_Y_SHIFT;
6454
6455         visible = base != 0;
6456         if (!visible && !intel_crtc->cursor_visible)
6457                 return;
6458
6459         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6460                 I915_WRITE(CURPOS_IVB(pipe), pos);
6461                 ivb_update_cursor(crtc, base);
6462         } else {
6463                 I915_WRITE(CURPOS(pipe), pos);
6464                 if (IS_845G(dev) || IS_I865G(dev))
6465                         i845_update_cursor(crtc, base);
6466                 else
6467                         i9xx_update_cursor(crtc, base);
6468         }
6469 }
6470
6471 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6472                                  struct drm_file *file,
6473                                  uint32_t handle,
6474                                  uint32_t width, uint32_t height)
6475 {
6476         struct drm_device *dev = crtc->dev;
6477         struct drm_i915_private *dev_priv = dev->dev_private;
6478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6479         struct drm_i915_gem_object *obj;
6480         uint32_t addr;
6481         int ret;
6482
6483         /* if we want to turn off the cursor ignore width and height */
6484         if (!handle) {
6485                 DRM_DEBUG_KMS("cursor off\n");
6486                 addr = 0;
6487                 obj = NULL;
6488                 mutex_lock(&dev->struct_mutex);
6489                 goto finish;
6490         }
6491
6492         /* Currently we only support 64x64 cursors */
6493         if (width != 64 || height != 64) {
6494                 DRM_ERROR("we currently only support 64x64 cursors\n");
6495                 return -EINVAL;
6496         }
6497
6498         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6499         if (&obj->base == NULL)
6500                 return -ENOENT;
6501
6502         if (obj->base.size < width * height * 4) {
6503                 DRM_ERROR("buffer is to small\n");
6504                 ret = -ENOMEM;
6505                 goto fail;
6506         }
6507
6508         /* we only need to pin inside GTT if cursor is non-phy */
6509         mutex_lock(&dev->struct_mutex);
6510         if (!dev_priv->info->cursor_needs_physical) {
6511                 unsigned alignment;
6512
6513                 if (obj->tiling_mode) {
6514                         DRM_ERROR("cursor cannot be tiled\n");
6515                         ret = -EINVAL;
6516                         goto fail_locked;
6517                 }
6518
6519                 /* Note that the w/a also requires 2 PTE of padding following
6520                  * the bo. We currently fill all unused PTE with the shadow
6521                  * page and so we should always have valid PTE following the
6522                  * cursor preventing the VT-d warning.
6523                  */
6524                 alignment = 0;
6525                 if (need_vtd_wa(dev))
6526                         alignment = 64*1024;
6527
6528                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6529                 if (ret) {
6530                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6531                         goto fail_locked;
6532                 }
6533
6534                 ret = i915_gem_object_put_fence(obj);
6535                 if (ret) {
6536                         DRM_ERROR("failed to release fence for cursor");
6537                         goto fail_unpin;
6538                 }
6539
6540                 addr = obj->gtt_offset;
6541         } else {
6542                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6543                 ret = i915_gem_attach_phys_object(dev, obj,
6544                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6545                                                   align);
6546                 if (ret) {
6547                         DRM_ERROR("failed to attach phys object\n");
6548                         goto fail_locked;
6549                 }
6550                 addr = obj->phys_obj->handle->busaddr;
6551         }
6552
6553         if (IS_GEN2(dev))
6554                 I915_WRITE(CURSIZE, (height << 12) | width);
6555
6556  finish:
6557         if (intel_crtc->cursor_bo) {
6558                 if (dev_priv->info->cursor_needs_physical) {
6559                         if (intel_crtc->cursor_bo != obj)
6560                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6561                 } else
6562                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6563                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6564         }
6565
6566         mutex_unlock(&dev->struct_mutex);
6567
6568         intel_crtc->cursor_addr = addr;
6569         intel_crtc->cursor_bo = obj;
6570         intel_crtc->cursor_width = width;
6571         intel_crtc->cursor_height = height;
6572
6573         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6574
6575         return 0;
6576 fail_unpin:
6577         i915_gem_object_unpin(obj);
6578 fail_locked:
6579         mutex_unlock(&dev->struct_mutex);
6580 fail:
6581         drm_gem_object_unreference_unlocked(&obj->base);
6582         return ret;
6583 }
6584
6585 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6586 {
6587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6588
6589         intel_crtc->cursor_x = x;
6590         intel_crtc->cursor_y = y;
6591
6592         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6593
6594         return 0;
6595 }
6596
6597 /** Sets the color ramps on behalf of RandR */
6598 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6599                                  u16 blue, int regno)
6600 {
6601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602
6603         intel_crtc->lut_r[regno] = red >> 8;
6604         intel_crtc->lut_g[regno] = green >> 8;
6605         intel_crtc->lut_b[regno] = blue >> 8;
6606 }
6607
6608 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6609                              u16 *blue, int regno)
6610 {
6611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612
6613         *red = intel_crtc->lut_r[regno] << 8;
6614         *green = intel_crtc->lut_g[regno] << 8;
6615         *blue = intel_crtc->lut_b[regno] << 8;
6616 }
6617
6618 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6619                                  u16 *blue, uint32_t start, uint32_t size)
6620 {
6621         int end = (start + size > 256) ? 256 : start + size, i;
6622         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6623
6624         for (i = start; i < end; i++) {
6625                 intel_crtc->lut_r[i] = red[i] >> 8;
6626                 intel_crtc->lut_g[i] = green[i] >> 8;
6627                 intel_crtc->lut_b[i] = blue[i] >> 8;
6628         }
6629
6630         intel_crtc_load_lut(crtc);
6631 }
6632
6633 /* VESA 640x480x72Hz mode to set on the pipe */
6634 static struct drm_display_mode load_detect_mode = {
6635         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6636                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6637 };
6638
6639 static struct drm_framebuffer *
6640 intel_framebuffer_create(struct drm_device *dev,
6641                          struct drm_mode_fb_cmd2 *mode_cmd,
6642                          struct drm_i915_gem_object *obj)
6643 {
6644         struct intel_framebuffer *intel_fb;
6645         int ret;
6646
6647         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6648         if (!intel_fb) {
6649                 drm_gem_object_unreference_unlocked(&obj->base);
6650                 return ERR_PTR(-ENOMEM);
6651         }
6652
6653         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6654         if (ret) {
6655                 drm_gem_object_unreference_unlocked(&obj->base);
6656                 kfree(intel_fb);
6657                 return ERR_PTR(ret);
6658         }
6659
6660         return &intel_fb->base;
6661 }
6662
6663 static u32
6664 intel_framebuffer_pitch_for_width(int width, int bpp)
6665 {
6666         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6667         return ALIGN(pitch, 64);
6668 }
6669
6670 static u32
6671 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6672 {
6673         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6674         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6675 }
6676
6677 static struct drm_framebuffer *
6678 intel_framebuffer_create_for_mode(struct drm_device *dev,
6679                                   struct drm_display_mode *mode,
6680                                   int depth, int bpp)
6681 {
6682         struct drm_i915_gem_object *obj;
6683         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6684
6685         obj = i915_gem_alloc_object(dev,
6686                                     intel_framebuffer_size_for_mode(mode, bpp));
6687         if (obj == NULL)
6688                 return ERR_PTR(-ENOMEM);
6689
6690         mode_cmd.width = mode->hdisplay;
6691         mode_cmd.height = mode->vdisplay;
6692         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6693                                                                 bpp);
6694         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6695
6696         return intel_framebuffer_create(dev, &mode_cmd, obj);
6697 }
6698
6699 static struct drm_framebuffer *
6700 mode_fits_in_fbdev(struct drm_device *dev,
6701                    struct drm_display_mode *mode)
6702 {
6703         struct drm_i915_private *dev_priv = dev->dev_private;
6704         struct drm_i915_gem_object *obj;
6705         struct drm_framebuffer *fb;
6706
6707         if (dev_priv->fbdev == NULL)
6708                 return NULL;
6709
6710         obj = dev_priv->fbdev->ifb.obj;
6711         if (obj == NULL)
6712                 return NULL;
6713
6714         fb = &dev_priv->fbdev->ifb.base;
6715         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6716                                                                fb->bits_per_pixel))
6717                 return NULL;
6718
6719         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6720                 return NULL;
6721
6722         return fb;
6723 }
6724
6725 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6726                                 struct drm_display_mode *mode,
6727                                 struct intel_load_detect_pipe *old)
6728 {
6729         struct intel_crtc *intel_crtc;
6730         struct intel_encoder *intel_encoder =
6731                 intel_attached_encoder(connector);
6732         struct drm_crtc *possible_crtc;
6733         struct drm_encoder *encoder = &intel_encoder->base;
6734         struct drm_crtc *crtc = NULL;
6735         struct drm_device *dev = encoder->dev;
6736         struct drm_framebuffer *fb;
6737         int i = -1;
6738
6739         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6740                       connector->base.id, drm_get_connector_name(connector),
6741                       encoder->base.id, drm_get_encoder_name(encoder));
6742
6743         /*
6744          * Algorithm gets a little messy:
6745          *
6746          *   - if the connector already has an assigned crtc, use it (but make
6747          *     sure it's on first)
6748          *
6749          *   - try to find the first unused crtc that can drive this connector,
6750          *     and use that if we find one
6751          */
6752
6753         /* See if we already have a CRTC for this connector */
6754         if (encoder->crtc) {
6755                 crtc = encoder->crtc;
6756
6757                 mutex_lock(&crtc->mutex);
6758
6759                 old->dpms_mode = connector->dpms;
6760                 old->load_detect_temp = false;
6761
6762                 /* Make sure the crtc and connector are running */
6763                 if (connector->dpms != DRM_MODE_DPMS_ON)
6764                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6765
6766                 return true;
6767         }
6768
6769         /* Find an unused one (if possible) */
6770         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6771                 i++;
6772                 if (!(encoder->possible_crtcs & (1 << i)))
6773                         continue;
6774                 if (!possible_crtc->enabled) {
6775                         crtc = possible_crtc;
6776                         break;
6777                 }
6778         }
6779
6780         /*
6781          * If we didn't find an unused CRTC, don't use any.
6782          */
6783         if (!crtc) {
6784                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6785                 return false;
6786         }
6787
6788         mutex_lock(&crtc->mutex);
6789         intel_encoder->new_crtc = to_intel_crtc(crtc);
6790         to_intel_connector(connector)->new_encoder = intel_encoder;
6791
6792         intel_crtc = to_intel_crtc(crtc);
6793         old->dpms_mode = connector->dpms;
6794         old->load_detect_temp = true;
6795         old->release_fb = NULL;
6796
6797         if (!mode)
6798                 mode = &load_detect_mode;
6799
6800         /* We need a framebuffer large enough to accommodate all accesses
6801          * that the plane may generate whilst we perform load detection.
6802          * We can not rely on the fbcon either being present (we get called
6803          * during its initialisation to detect all boot displays, or it may
6804          * not even exist) or that it is large enough to satisfy the
6805          * requested mode.
6806          */
6807         fb = mode_fits_in_fbdev(dev, mode);
6808         if (fb == NULL) {
6809                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6810                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6811                 old->release_fb = fb;
6812         } else
6813                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6814         if (IS_ERR(fb)) {
6815                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6816                 mutex_unlock(&crtc->mutex);
6817                 return false;
6818         }
6819
6820         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6821                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6822                 if (old->release_fb)
6823                         old->release_fb->funcs->destroy(old->release_fb);
6824                 mutex_unlock(&crtc->mutex);
6825                 return false;
6826         }
6827
6828         /* let the connector get through one full cycle before testing */
6829         intel_wait_for_vblank(dev, intel_crtc->pipe);
6830         return true;
6831 }
6832
6833 void intel_release_load_detect_pipe(struct drm_connector *connector,
6834                                     struct intel_load_detect_pipe *old)
6835 {
6836         struct intel_encoder *intel_encoder =
6837                 intel_attached_encoder(connector);
6838         struct drm_encoder *encoder = &intel_encoder->base;
6839         struct drm_crtc *crtc = encoder->crtc;
6840
6841         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6842                       connector->base.id, drm_get_connector_name(connector),
6843                       encoder->base.id, drm_get_encoder_name(encoder));
6844
6845         if (old->load_detect_temp) {
6846                 to_intel_connector(connector)->new_encoder = NULL;
6847                 intel_encoder->new_crtc = NULL;
6848                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6849
6850                 if (old->release_fb) {
6851                         drm_framebuffer_unregister_private(old->release_fb);
6852                         drm_framebuffer_unreference(old->release_fb);
6853                 }
6854
6855                 mutex_unlock(&crtc->mutex);
6856                 return;
6857         }
6858
6859         /* Switch crtc and encoder back off if necessary */
6860         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6861                 connector->funcs->dpms(connector, old->dpms_mode);
6862
6863         mutex_unlock(&crtc->mutex);
6864 }
6865
6866 /* Returns the clock of the currently programmed mode of the given pipe. */
6867 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6868 {
6869         struct drm_i915_private *dev_priv = dev->dev_private;
6870         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871         int pipe = intel_crtc->pipe;
6872         u32 dpll = I915_READ(DPLL(pipe));
6873         u32 fp;
6874         intel_clock_t clock;
6875
6876         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6877                 fp = I915_READ(FP0(pipe));
6878         else
6879                 fp = I915_READ(FP1(pipe));
6880
6881         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6882         if (IS_PINEVIEW(dev)) {
6883                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6884                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6885         } else {
6886                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6887                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6888         }
6889
6890         if (!IS_GEN2(dev)) {
6891                 if (IS_PINEVIEW(dev))
6892                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6893                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6894                 else
6895                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6896                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6897
6898                 switch (dpll & DPLL_MODE_MASK) {
6899                 case DPLLB_MODE_DAC_SERIAL:
6900                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6901                                 5 : 10;
6902                         break;
6903                 case DPLLB_MODE_LVDS:
6904                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6905                                 7 : 14;
6906                         break;
6907                 default:
6908                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6909                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6910                         return 0;
6911                 }
6912
6913                 if (IS_PINEVIEW(dev))
6914                         pineview_clock(96000, &clock);
6915                 else
6916                         i9xx_clock(96000, &clock);
6917         } else {
6918                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6919
6920                 if (is_lvds) {
6921                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6922                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6923                         clock.p2 = 14;
6924
6925                         if ((dpll & PLL_REF_INPUT_MASK) ==
6926                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6927                                 /* XXX: might not be 66MHz */
6928                                 i9xx_clock(66000, &clock);
6929                         } else
6930                                 i9xx_clock(48000, &clock);
6931                 } else {
6932                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6933                                 clock.p1 = 2;
6934                         else {
6935                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6936                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6937                         }
6938                         if (dpll & PLL_P2_DIVIDE_BY_4)
6939                                 clock.p2 = 4;
6940                         else
6941                                 clock.p2 = 2;
6942
6943                         i9xx_clock(48000, &clock);
6944                 }
6945         }
6946
6947         /* XXX: It would be nice to validate the clocks, but we can't reuse
6948          * i830PllIsValid() because it relies on the xf86_config connector
6949          * configuration being accurate, which it isn't necessarily.
6950          */
6951
6952         return clock.dot;
6953 }
6954
6955 /** Returns the currently programmed mode of the given pipe. */
6956 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6957                                              struct drm_crtc *crtc)
6958 {
6959         struct drm_i915_private *dev_priv = dev->dev_private;
6960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6961         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6962         struct drm_display_mode *mode;
6963         int htot = I915_READ(HTOTAL(cpu_transcoder));
6964         int hsync = I915_READ(HSYNC(cpu_transcoder));
6965         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6966         int vsync = I915_READ(VSYNC(cpu_transcoder));
6967
6968         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6969         if (!mode)
6970                 return NULL;
6971
6972         mode->clock = intel_crtc_clock_get(dev, crtc);
6973         mode->hdisplay = (htot & 0xffff) + 1;
6974         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6975         mode->hsync_start = (hsync & 0xffff) + 1;
6976         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6977         mode->vdisplay = (vtot & 0xffff) + 1;
6978         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6979         mode->vsync_start = (vsync & 0xffff) + 1;
6980         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6981
6982         drm_mode_set_name(mode);
6983
6984         return mode;
6985 }
6986
6987 static void intel_increase_pllclock(struct drm_crtc *crtc)
6988 {
6989         struct drm_device *dev = crtc->dev;
6990         drm_i915_private_t *dev_priv = dev->dev_private;
6991         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6992         int pipe = intel_crtc->pipe;
6993         int dpll_reg = DPLL(pipe);
6994         int dpll;
6995
6996         if (HAS_PCH_SPLIT(dev))
6997                 return;
6998
6999         if (!dev_priv->lvds_downclock_avail)
7000                 return;
7001
7002         dpll = I915_READ(dpll_reg);
7003         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7004                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7005
7006                 assert_panel_unlocked(dev_priv, pipe);
7007
7008                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7009                 I915_WRITE(dpll_reg, dpll);
7010                 intel_wait_for_vblank(dev, pipe);
7011
7012                 dpll = I915_READ(dpll_reg);
7013                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7014                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7015         }
7016 }
7017
7018 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7019 {
7020         struct drm_device *dev = crtc->dev;
7021         drm_i915_private_t *dev_priv = dev->dev_private;
7022         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023
7024         if (HAS_PCH_SPLIT(dev))
7025                 return;
7026
7027         if (!dev_priv->lvds_downclock_avail)
7028                 return;
7029
7030         /*
7031          * Since this is called by a timer, we should never get here in
7032          * the manual case.
7033          */
7034         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7035                 int pipe = intel_crtc->pipe;
7036                 int dpll_reg = DPLL(pipe);
7037                 int dpll;
7038
7039                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7040
7041                 assert_panel_unlocked(dev_priv, pipe);
7042
7043                 dpll = I915_READ(dpll_reg);
7044                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7045                 I915_WRITE(dpll_reg, dpll);
7046                 intel_wait_for_vblank(dev, pipe);
7047                 dpll = I915_READ(dpll_reg);
7048                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7049                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7050         }
7051
7052 }
7053
7054 void intel_mark_busy(struct drm_device *dev)
7055 {
7056         i915_update_gfx_val(dev->dev_private);
7057 }
7058
7059 void intel_mark_idle(struct drm_device *dev)
7060 {
7061         struct drm_crtc *crtc;
7062
7063         if (!i915_powersave)
7064                 return;
7065
7066         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7067                 if (!crtc->fb)
7068                         continue;
7069
7070                 intel_decrease_pllclock(crtc);
7071         }
7072 }
7073
7074 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7075                         struct intel_ring_buffer *ring)
7076 {
7077         struct drm_device *dev = obj->base.dev;
7078         struct drm_crtc *crtc;
7079
7080         if (!i915_powersave)
7081                 return;
7082
7083         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7084                 if (!crtc->fb)
7085                         continue;
7086
7087                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7088                         continue;
7089
7090                 intel_increase_pllclock(crtc);
7091                 if (ring && intel_fbc_enabled(dev))
7092                         ring->fbc_dirty = true;
7093         }
7094 }
7095
7096 static void intel_crtc_destroy(struct drm_crtc *crtc)
7097 {
7098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7099         struct drm_device *dev = crtc->dev;
7100         struct intel_unpin_work *work;
7101         unsigned long flags;
7102
7103         spin_lock_irqsave(&dev->event_lock, flags);
7104         work = intel_crtc->unpin_work;
7105         intel_crtc->unpin_work = NULL;
7106         spin_unlock_irqrestore(&dev->event_lock, flags);
7107
7108         if (work) {
7109                 cancel_work_sync(&work->work);
7110                 kfree(work);
7111         }
7112
7113         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7114
7115         drm_crtc_cleanup(crtc);
7116
7117         kfree(intel_crtc);
7118 }
7119
7120 static void intel_unpin_work_fn(struct work_struct *__work)
7121 {
7122         struct intel_unpin_work *work =
7123                 container_of(__work, struct intel_unpin_work, work);
7124         struct drm_device *dev = work->crtc->dev;
7125
7126         mutex_lock(&dev->struct_mutex);
7127         intel_unpin_fb_obj(work->old_fb_obj);
7128         drm_gem_object_unreference(&work->pending_flip_obj->base);
7129         drm_gem_object_unreference(&work->old_fb_obj->base);
7130
7131         intel_update_fbc(dev);
7132         mutex_unlock(&dev->struct_mutex);
7133
7134         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7135         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7136
7137         kfree(work);
7138 }
7139
7140 static void do_intel_finish_page_flip(struct drm_device *dev,
7141                                       struct drm_crtc *crtc)
7142 {
7143         drm_i915_private_t *dev_priv = dev->dev_private;
7144         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7145         struct intel_unpin_work *work;
7146         unsigned long flags;
7147
7148         /* Ignore early vblank irqs */
7149         if (intel_crtc == NULL)
7150                 return;
7151
7152         spin_lock_irqsave(&dev->event_lock, flags);
7153         work = intel_crtc->unpin_work;
7154
7155         /* Ensure we don't miss a work->pending update ... */
7156         smp_rmb();
7157
7158         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7159                 spin_unlock_irqrestore(&dev->event_lock, flags);
7160                 return;
7161         }
7162
7163         /* and that the unpin work is consistent wrt ->pending. */
7164         smp_rmb();
7165
7166         intel_crtc->unpin_work = NULL;
7167
7168         if (work->event)
7169                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7170
7171         drm_vblank_put(dev, intel_crtc->pipe);
7172
7173         spin_unlock_irqrestore(&dev->event_lock, flags);
7174
7175         wake_up_all(&dev_priv->pending_flip_queue);
7176
7177         queue_work(dev_priv->wq, &work->work);
7178
7179         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7180 }
7181
7182 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7183 {
7184         drm_i915_private_t *dev_priv = dev->dev_private;
7185         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7186
7187         do_intel_finish_page_flip(dev, crtc);
7188 }
7189
7190 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7191 {
7192         drm_i915_private_t *dev_priv = dev->dev_private;
7193         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7194
7195         do_intel_finish_page_flip(dev, crtc);
7196 }
7197
7198 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7199 {
7200         drm_i915_private_t *dev_priv = dev->dev_private;
7201         struct intel_crtc *intel_crtc =
7202                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7203         unsigned long flags;
7204
7205         /* NB: An MMIO update of the plane base pointer will also
7206          * generate a page-flip completion irq, i.e. every modeset
7207          * is also accompanied by a spurious intel_prepare_page_flip().
7208          */
7209         spin_lock_irqsave(&dev->event_lock, flags);
7210         if (intel_crtc->unpin_work)
7211                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7212         spin_unlock_irqrestore(&dev->event_lock, flags);
7213 }
7214
7215 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7216 {
7217         /* Ensure that the work item is consistent when activating it ... */
7218         smp_wmb();
7219         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7220         /* and that it is marked active as soon as the irq could fire. */
7221         smp_wmb();
7222 }
7223
7224 static int intel_gen2_queue_flip(struct drm_device *dev,
7225                                  struct drm_crtc *crtc,
7226                                  struct drm_framebuffer *fb,
7227                                  struct drm_i915_gem_object *obj)
7228 {
7229         struct drm_i915_private *dev_priv = dev->dev_private;
7230         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7231         u32 flip_mask;
7232         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7233         int ret;
7234
7235         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7236         if (ret)
7237                 goto err;
7238
7239         ret = intel_ring_begin(ring, 6);
7240         if (ret)
7241                 goto err_unpin;
7242
7243         /* Can't queue multiple flips, so wait for the previous
7244          * one to finish before executing the next.
7245          */
7246         if (intel_crtc->plane)
7247                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7248         else
7249                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7250         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7251         intel_ring_emit(ring, MI_NOOP);
7252         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7253                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7254         intel_ring_emit(ring, fb->pitches[0]);
7255         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7256         intel_ring_emit(ring, 0); /* aux display base address, unused */
7257
7258         intel_mark_page_flip_active(intel_crtc);
7259         intel_ring_advance(ring);
7260         return 0;
7261
7262 err_unpin:
7263         intel_unpin_fb_obj(obj);
7264 err:
7265         return ret;
7266 }
7267
7268 static int intel_gen3_queue_flip(struct drm_device *dev,
7269                                  struct drm_crtc *crtc,
7270                                  struct drm_framebuffer *fb,
7271                                  struct drm_i915_gem_object *obj)
7272 {
7273         struct drm_i915_private *dev_priv = dev->dev_private;
7274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7275         u32 flip_mask;
7276         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7277         int ret;
7278
7279         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7280         if (ret)
7281                 goto err;
7282
7283         ret = intel_ring_begin(ring, 6);
7284         if (ret)
7285                 goto err_unpin;
7286
7287         if (intel_crtc->plane)
7288                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7289         else
7290                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7291         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7292         intel_ring_emit(ring, MI_NOOP);
7293         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7294                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7295         intel_ring_emit(ring, fb->pitches[0]);
7296         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7297         intel_ring_emit(ring, MI_NOOP);
7298
7299         intel_mark_page_flip_active(intel_crtc);
7300         intel_ring_advance(ring);
7301         return 0;
7302
7303 err_unpin:
7304         intel_unpin_fb_obj(obj);
7305 err:
7306         return ret;
7307 }
7308
7309 static int intel_gen4_queue_flip(struct drm_device *dev,
7310                                  struct drm_crtc *crtc,
7311                                  struct drm_framebuffer *fb,
7312                                  struct drm_i915_gem_object *obj)
7313 {
7314         struct drm_i915_private *dev_priv = dev->dev_private;
7315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7316         uint32_t pf, pipesrc;
7317         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7318         int ret;
7319
7320         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7321         if (ret)
7322                 goto err;
7323
7324         ret = intel_ring_begin(ring, 4);
7325         if (ret)
7326                 goto err_unpin;
7327
7328         /* i965+ uses the linear or tiled offsets from the
7329          * Display Registers (which do not change across a page-flip)
7330          * so we need only reprogram the base address.
7331          */
7332         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7333                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7334         intel_ring_emit(ring, fb->pitches[0]);
7335         intel_ring_emit(ring,
7336                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7337                         obj->tiling_mode);
7338
7339         /* XXX Enabling the panel-fitter across page-flip is so far
7340          * untested on non-native modes, so ignore it for now.
7341          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7342          */
7343         pf = 0;
7344         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7345         intel_ring_emit(ring, pf | pipesrc);
7346
7347         intel_mark_page_flip_active(intel_crtc);
7348         intel_ring_advance(ring);
7349         return 0;
7350
7351 err_unpin:
7352         intel_unpin_fb_obj(obj);
7353 err:
7354         return ret;
7355 }
7356
7357 static int intel_gen6_queue_flip(struct drm_device *dev,
7358                                  struct drm_crtc *crtc,
7359                                  struct drm_framebuffer *fb,
7360                                  struct drm_i915_gem_object *obj)
7361 {
7362         struct drm_i915_private *dev_priv = dev->dev_private;
7363         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7364         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7365         uint32_t pf, pipesrc;
7366         int ret;
7367
7368         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7369         if (ret)
7370                 goto err;
7371
7372         ret = intel_ring_begin(ring, 4);
7373         if (ret)
7374                 goto err_unpin;
7375
7376         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7377                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7378         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7379         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7380
7381         /* Contrary to the suggestions in the documentation,
7382          * "Enable Panel Fitter" does not seem to be required when page
7383          * flipping with a non-native mode, and worse causes a normal
7384          * modeset to fail.
7385          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7386          */
7387         pf = 0;
7388         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7389         intel_ring_emit(ring, pf | pipesrc);
7390
7391         intel_mark_page_flip_active(intel_crtc);
7392         intel_ring_advance(ring);
7393         return 0;
7394
7395 err_unpin:
7396         intel_unpin_fb_obj(obj);
7397 err:
7398         return ret;
7399 }
7400
7401 /*
7402  * On gen7 we currently use the blit ring because (in early silicon at least)
7403  * the render ring doesn't give us interrpts for page flip completion, which
7404  * means clients will hang after the first flip is queued.  Fortunately the
7405  * blit ring generates interrupts properly, so use it instead.
7406  */
7407 static int intel_gen7_queue_flip(struct drm_device *dev,
7408                                  struct drm_crtc *crtc,
7409                                  struct drm_framebuffer *fb,
7410                                  struct drm_i915_gem_object *obj)
7411 {
7412         struct drm_i915_private *dev_priv = dev->dev_private;
7413         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7414         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7415         uint32_t plane_bit = 0;
7416         int ret;
7417
7418         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7419         if (ret)
7420                 goto err;
7421
7422         switch(intel_crtc->plane) {
7423         case PLANE_A:
7424                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7425                 break;
7426         case PLANE_B:
7427                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7428                 break;
7429         case PLANE_C:
7430                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7431                 break;
7432         default:
7433                 WARN_ONCE(1, "unknown plane in flip command\n");
7434                 ret = -ENODEV;
7435                 goto err_unpin;
7436         }
7437
7438         ret = intel_ring_begin(ring, 4);
7439         if (ret)
7440                 goto err_unpin;
7441
7442         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7443         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7444         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7445         intel_ring_emit(ring, (MI_NOOP));
7446
7447         intel_mark_page_flip_active(intel_crtc);
7448         intel_ring_advance(ring);
7449         return 0;
7450
7451 err_unpin:
7452         intel_unpin_fb_obj(obj);
7453 err:
7454         return ret;
7455 }
7456
7457 static int intel_default_queue_flip(struct drm_device *dev,
7458                                     struct drm_crtc *crtc,
7459                                     struct drm_framebuffer *fb,
7460                                     struct drm_i915_gem_object *obj)
7461 {
7462         return -ENODEV;
7463 }
7464
7465 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7466                                 struct drm_framebuffer *fb,
7467                                 struct drm_pending_vblank_event *event)
7468 {
7469         struct drm_device *dev = crtc->dev;
7470         struct drm_i915_private *dev_priv = dev->dev_private;
7471         struct drm_framebuffer *old_fb = crtc->fb;
7472         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7474         struct intel_unpin_work *work;
7475         unsigned long flags;
7476         int ret;
7477
7478         /* Can't change pixel format via MI display flips. */
7479         if (fb->pixel_format != crtc->fb->pixel_format)
7480                 return -EINVAL;
7481
7482         /*
7483          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7484          * Note that pitch changes could also affect these register.
7485          */
7486         if (INTEL_INFO(dev)->gen > 3 &&
7487             (fb->offsets[0] != crtc->fb->offsets[0] ||
7488              fb->pitches[0] != crtc->fb->pitches[0]))
7489                 return -EINVAL;
7490
7491         work = kzalloc(sizeof *work, GFP_KERNEL);
7492         if (work == NULL)
7493                 return -ENOMEM;
7494
7495         work->event = event;
7496         work->crtc = crtc;
7497         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7498         INIT_WORK(&work->work, intel_unpin_work_fn);
7499
7500         ret = drm_vblank_get(dev, intel_crtc->pipe);
7501         if (ret)
7502                 goto free_work;
7503
7504         /* We borrow the event spin lock for protecting unpin_work */
7505         spin_lock_irqsave(&dev->event_lock, flags);
7506         if (intel_crtc->unpin_work) {
7507                 spin_unlock_irqrestore(&dev->event_lock, flags);
7508                 kfree(work);
7509                 drm_vblank_put(dev, intel_crtc->pipe);
7510
7511                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7512                 return -EBUSY;
7513         }
7514         intel_crtc->unpin_work = work;
7515         spin_unlock_irqrestore(&dev->event_lock, flags);
7516
7517         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7518                 flush_workqueue(dev_priv->wq);
7519
7520         ret = i915_mutex_lock_interruptible(dev);
7521         if (ret)
7522                 goto cleanup;
7523
7524         /* Reference the objects for the scheduled work. */
7525         drm_gem_object_reference(&work->old_fb_obj->base);
7526         drm_gem_object_reference(&obj->base);
7527
7528         crtc->fb = fb;
7529
7530         work->pending_flip_obj = obj;
7531
7532         work->enable_stall_check = true;
7533
7534         atomic_inc(&intel_crtc->unpin_work_count);
7535         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7536
7537         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7538         if (ret)
7539                 goto cleanup_pending;
7540
7541         intel_disable_fbc(dev);
7542         intel_mark_fb_busy(obj, NULL);
7543         mutex_unlock(&dev->struct_mutex);
7544
7545         trace_i915_flip_request(intel_crtc->plane, obj);
7546
7547         return 0;
7548
7549 cleanup_pending:
7550         atomic_dec(&intel_crtc->unpin_work_count);
7551         crtc->fb = old_fb;
7552         drm_gem_object_unreference(&work->old_fb_obj->base);
7553         drm_gem_object_unreference(&obj->base);
7554         mutex_unlock(&dev->struct_mutex);
7555
7556 cleanup:
7557         spin_lock_irqsave(&dev->event_lock, flags);
7558         intel_crtc->unpin_work = NULL;
7559         spin_unlock_irqrestore(&dev->event_lock, flags);
7560
7561         drm_vblank_put(dev, intel_crtc->pipe);
7562 free_work:
7563         kfree(work);
7564
7565         return ret;
7566 }
7567
7568 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7569         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7570         .load_lut = intel_crtc_load_lut,
7571 };
7572
7573 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7574                                   struct drm_crtc *crtc)
7575 {
7576         struct drm_device *dev;
7577         struct drm_crtc *tmp;
7578         int crtc_mask = 1;
7579
7580         WARN(!crtc, "checking null crtc?\n");
7581
7582         dev = crtc->dev;
7583
7584         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7585                 if (tmp == crtc)
7586                         break;
7587                 crtc_mask <<= 1;
7588         }
7589
7590         if (encoder->possible_crtcs & crtc_mask)
7591                 return true;
7592         return false;
7593 }
7594
7595 /**
7596  * intel_modeset_update_staged_output_state
7597  *
7598  * Updates the staged output configuration state, e.g. after we've read out the
7599  * current hw state.
7600  */
7601 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7602 {
7603         struct intel_encoder *encoder;
7604         struct intel_connector *connector;
7605
7606         list_for_each_entry(connector, &dev->mode_config.connector_list,
7607                             base.head) {
7608                 connector->new_encoder =
7609                         to_intel_encoder(connector->base.encoder);
7610         }
7611
7612         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7613                             base.head) {
7614                 encoder->new_crtc =
7615                         to_intel_crtc(encoder->base.crtc);
7616         }
7617 }
7618
7619 /**
7620  * intel_modeset_commit_output_state
7621  *
7622  * This function copies the stage display pipe configuration to the real one.
7623  */
7624 static void intel_modeset_commit_output_state(struct drm_device *dev)
7625 {
7626         struct intel_encoder *encoder;
7627         struct intel_connector *connector;
7628
7629         list_for_each_entry(connector, &dev->mode_config.connector_list,
7630                             base.head) {
7631                 connector->base.encoder = &connector->new_encoder->base;
7632         }
7633
7634         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7635                             base.head) {
7636                 encoder->base.crtc = &encoder->new_crtc->base;
7637         }
7638 }
7639
7640 static void
7641 connected_sink_compute_bpp(struct intel_connector * connector,
7642                            struct intel_crtc_config *pipe_config)
7643 {
7644         int bpp = pipe_config->pipe_bpp;
7645
7646         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7647                 connector->base.base.id,
7648                 drm_get_connector_name(&connector->base));
7649
7650         /* Don't use an invalid EDID bpc value */
7651         if (connector->base.display_info.bpc &&
7652             connector->base.display_info.bpc * 3 < bpp) {
7653                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7654                               bpp, connector->base.display_info.bpc*3);
7655                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7656         }
7657
7658         /* Clamp bpp to 8 on screens without EDID 1.4 */
7659         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7660                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7661                               bpp);
7662                 pipe_config->pipe_bpp = 24;
7663         }
7664 }
7665
7666 static int
7667 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7668                           struct drm_framebuffer *fb,
7669                           struct intel_crtc_config *pipe_config)
7670 {
7671         struct drm_device *dev = crtc->base.dev;
7672         struct intel_connector *connector;
7673         int bpp;
7674
7675         switch (fb->pixel_format) {
7676         case DRM_FORMAT_C8:
7677                 bpp = 8*3; /* since we go through a colormap */
7678                 break;
7679         case DRM_FORMAT_XRGB1555:
7680         case DRM_FORMAT_ARGB1555:
7681                 /* checked in intel_framebuffer_init already */
7682                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7683                         return -EINVAL;
7684         case DRM_FORMAT_RGB565:
7685                 bpp = 6*3; /* min is 18bpp */
7686                 break;
7687         case DRM_FORMAT_XBGR8888:
7688         case DRM_FORMAT_ABGR8888:
7689                 /* checked in intel_framebuffer_init already */
7690                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7691                         return -EINVAL;
7692         case DRM_FORMAT_XRGB8888:
7693         case DRM_FORMAT_ARGB8888:
7694                 bpp = 8*3;
7695                 break;
7696         case DRM_FORMAT_XRGB2101010:
7697         case DRM_FORMAT_ARGB2101010:
7698         case DRM_FORMAT_XBGR2101010:
7699         case DRM_FORMAT_ABGR2101010:
7700                 /* checked in intel_framebuffer_init already */
7701                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7702                         return -EINVAL;
7703                 bpp = 10*3;
7704                 break;
7705         /* TODO: gen4+ supports 16 bpc floating point, too. */
7706         default:
7707                 DRM_DEBUG_KMS("unsupported depth\n");
7708                 return -EINVAL;
7709         }
7710
7711         pipe_config->pipe_bpp = bpp;
7712
7713         /* Clamp display bpp to EDID value */
7714         list_for_each_entry(connector, &dev->mode_config.connector_list,
7715                             base.head) {
7716                 if (!connector->new_encoder ||
7717                     connector->new_encoder->new_crtc != crtc)
7718                         continue;
7719
7720                 connected_sink_compute_bpp(connector, pipe_config);
7721         }
7722
7723         return bpp;
7724 }
7725
7726 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7727                                    struct intel_crtc_config *pipe_config,
7728                                    const char *context)
7729 {
7730         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7731                       context, pipe_name(crtc->pipe));
7732
7733         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7734         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7735                       pipe_config->pipe_bpp, pipe_config->dither);
7736         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7737                       pipe_config->has_pch_encoder,
7738                       pipe_config->fdi_lanes,
7739                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7740                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7741                       pipe_config->fdi_m_n.tu);
7742         DRM_DEBUG_KMS("requested mode:\n");
7743         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7744         DRM_DEBUG_KMS("adjusted mode:\n");
7745         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7746         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7747                       pipe_config->gmch_pfit.control,
7748                       pipe_config->gmch_pfit.pgm_ratios,
7749                       pipe_config->gmch_pfit.lvds_border_bits);
7750         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7751                       pipe_config->pch_pfit.pos,
7752                       pipe_config->pch_pfit.size);
7753         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7754 }
7755
7756 static bool check_encoder_cloning(struct drm_crtc *crtc)
7757 {
7758         int num_encoders = 0;
7759         bool uncloneable_encoders = false;
7760         struct intel_encoder *encoder;
7761
7762         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7763                             base.head) {
7764                 if (&encoder->new_crtc->base != crtc)
7765                         continue;
7766
7767                 num_encoders++;
7768                 if (!encoder->cloneable)
7769                         uncloneable_encoders = true;
7770         }
7771
7772         return !(num_encoders > 1 && uncloneable_encoders);
7773 }
7774
7775 static struct intel_crtc_config *
7776 intel_modeset_pipe_config(struct drm_crtc *crtc,
7777                           struct drm_framebuffer *fb,
7778                           struct drm_display_mode *mode)
7779 {
7780         struct drm_device *dev = crtc->dev;
7781         struct drm_encoder_helper_funcs *encoder_funcs;
7782         struct intel_encoder *encoder;
7783         struct intel_crtc_config *pipe_config;
7784         int plane_bpp, ret = -EINVAL;
7785         bool retry = true;
7786
7787         if (!check_encoder_cloning(crtc)) {
7788                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7789                 return ERR_PTR(-EINVAL);
7790         }
7791
7792         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7793         if (!pipe_config)
7794                 return ERR_PTR(-ENOMEM);
7795
7796         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7797         drm_mode_copy(&pipe_config->requested_mode, mode);
7798         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7799         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7800
7801         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7802          * plane pixel format and any sink constraints into account. Returns the
7803          * source plane bpp so that dithering can be selected on mismatches
7804          * after encoders and crtc also have had their say. */
7805         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7806                                               fb, pipe_config);
7807         if (plane_bpp < 0)
7808                 goto fail;
7809
7810 encoder_retry:
7811         /* Ensure the port clock defaults are reset when retrying. */
7812         pipe_config->port_clock = 0;
7813         pipe_config->pixel_multiplier = 1;
7814
7815         /* Pass our mode to the connectors and the CRTC to give them a chance to
7816          * adjust it according to limitations or connector properties, and also
7817          * a chance to reject the mode entirely.
7818          */
7819         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7820                             base.head) {
7821
7822                 if (&encoder->new_crtc->base != crtc)
7823                         continue;
7824
7825                 if (encoder->compute_config) {
7826                         if (!(encoder->compute_config(encoder, pipe_config))) {
7827                                 DRM_DEBUG_KMS("Encoder config failure\n");
7828                                 goto fail;
7829                         }
7830
7831                         continue;
7832                 }
7833
7834                 encoder_funcs = encoder->base.helper_private;
7835                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7836                                                 &pipe_config->requested_mode,
7837                                                 &pipe_config->adjusted_mode))) {
7838                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7839                         goto fail;
7840                 }
7841         }
7842
7843         /* Set default port clock if not overwritten by the encoder. Needs to be
7844          * done afterwards in case the encoder adjusts the mode. */
7845         if (!pipe_config->port_clock)
7846                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7847
7848         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7849         if (ret < 0) {
7850                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7851                 goto fail;
7852         }
7853
7854         if (ret == RETRY) {
7855                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7856                         ret = -EINVAL;
7857                         goto fail;
7858                 }
7859
7860                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7861                 retry = false;
7862                 goto encoder_retry;
7863         }
7864
7865         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7866         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7867                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7868
7869         return pipe_config;
7870 fail:
7871         kfree(pipe_config);
7872         return ERR_PTR(ret);
7873 }
7874
7875 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7876  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7877 static void
7878 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7879                              unsigned *prepare_pipes, unsigned *disable_pipes)
7880 {
7881         struct intel_crtc *intel_crtc;
7882         struct drm_device *dev = crtc->dev;
7883         struct intel_encoder *encoder;
7884         struct intel_connector *connector;
7885         struct drm_crtc *tmp_crtc;
7886
7887         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7888
7889         /* Check which crtcs have changed outputs connected to them, these need
7890          * to be part of the prepare_pipes mask. We don't (yet) support global
7891          * modeset across multiple crtcs, so modeset_pipes will only have one
7892          * bit set at most. */
7893         list_for_each_entry(connector, &dev->mode_config.connector_list,
7894                             base.head) {
7895                 if (connector->base.encoder == &connector->new_encoder->base)
7896                         continue;
7897
7898                 if (connector->base.encoder) {
7899                         tmp_crtc = connector->base.encoder->crtc;
7900
7901                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7902                 }
7903
7904                 if (connector->new_encoder)
7905                         *prepare_pipes |=
7906                                 1 << connector->new_encoder->new_crtc->pipe;
7907         }
7908
7909         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7910                             base.head) {
7911                 if (encoder->base.crtc == &encoder->new_crtc->base)
7912                         continue;
7913
7914                 if (encoder->base.crtc) {
7915                         tmp_crtc = encoder->base.crtc;
7916
7917                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7918                 }
7919
7920                 if (encoder->new_crtc)
7921                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7922         }
7923
7924         /* Check for any pipes that will be fully disabled ... */
7925         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7926                             base.head) {
7927                 bool used = false;
7928
7929                 /* Don't try to disable disabled crtcs. */
7930                 if (!intel_crtc->base.enabled)
7931                         continue;
7932
7933                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7934                                     base.head) {
7935                         if (encoder->new_crtc == intel_crtc)
7936                                 used = true;
7937                 }
7938
7939                 if (!used)
7940                         *disable_pipes |= 1 << intel_crtc->pipe;
7941         }
7942
7943
7944         /* set_mode is also used to update properties on life display pipes. */
7945         intel_crtc = to_intel_crtc(crtc);
7946         if (crtc->enabled)
7947                 *prepare_pipes |= 1 << intel_crtc->pipe;
7948
7949         /*
7950          * For simplicity do a full modeset on any pipe where the output routing
7951          * changed. We could be more clever, but that would require us to be
7952          * more careful with calling the relevant encoder->mode_set functions.
7953          */
7954         if (*prepare_pipes)
7955                 *modeset_pipes = *prepare_pipes;
7956
7957         /* ... and mask these out. */
7958         *modeset_pipes &= ~(*disable_pipes);
7959         *prepare_pipes &= ~(*disable_pipes);
7960
7961         /*
7962          * HACK: We don't (yet) fully support global modesets. intel_set_config
7963          * obies this rule, but the modeset restore mode of
7964          * intel_modeset_setup_hw_state does not.
7965          */
7966         *modeset_pipes &= 1 << intel_crtc->pipe;
7967         *prepare_pipes &= 1 << intel_crtc->pipe;
7968
7969         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7970                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7971 }
7972
7973 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7974 {
7975         struct drm_encoder *encoder;
7976         struct drm_device *dev = crtc->dev;
7977
7978         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7979                 if (encoder->crtc == crtc)
7980                         return true;
7981
7982         return false;
7983 }
7984
7985 static void
7986 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7987 {
7988         struct intel_encoder *intel_encoder;
7989         struct intel_crtc *intel_crtc;
7990         struct drm_connector *connector;
7991
7992         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7993                             base.head) {
7994                 if (!intel_encoder->base.crtc)
7995                         continue;
7996
7997                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7998
7999                 if (prepare_pipes & (1 << intel_crtc->pipe))
8000                         intel_encoder->connectors_active = false;
8001         }
8002
8003         intel_modeset_commit_output_state(dev);
8004
8005         /* Update computed state. */
8006         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8007                             base.head) {
8008                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8009         }
8010
8011         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8012                 if (!connector->encoder || !connector->encoder->crtc)
8013                         continue;
8014
8015                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8016
8017                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8018                         struct drm_property *dpms_property =
8019                                 dev->mode_config.dpms_property;
8020
8021                         connector->dpms = DRM_MODE_DPMS_ON;
8022                         drm_object_property_set_value(&connector->base,
8023                                                          dpms_property,
8024                                                          DRM_MODE_DPMS_ON);
8025
8026                         intel_encoder = to_intel_encoder(connector->encoder);
8027                         intel_encoder->connectors_active = true;
8028                 }
8029         }
8030
8031 }
8032
8033 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8034         list_for_each_entry((intel_crtc), \
8035                             &(dev)->mode_config.crtc_list, \
8036                             base.head) \
8037                 if (mask & (1 <<(intel_crtc)->pipe))
8038
8039 static bool
8040 intel_pipe_config_compare(struct drm_device *dev,
8041                           struct intel_crtc_config *current_config,
8042                           struct intel_crtc_config *pipe_config)
8043 {
8044 #define PIPE_CONF_CHECK_X(name) \
8045         if (current_config->name != pipe_config->name) { \
8046                 DRM_ERROR("mismatch in " #name " " \
8047                           "(expected 0x%08x, found 0x%08x)\n", \
8048                           current_config->name, \
8049                           pipe_config->name); \
8050                 return false; \
8051         }
8052
8053 #define PIPE_CONF_CHECK_I(name) \
8054         if (current_config->name != pipe_config->name) { \
8055                 DRM_ERROR("mismatch in " #name " " \
8056                           "(expected %i, found %i)\n", \
8057                           current_config->name, \
8058                           pipe_config->name); \
8059                 return false; \
8060         }
8061
8062 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8063         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8064                 DRM_ERROR("mismatch in " #name " " \
8065                           "(expected %i, found %i)\n", \
8066                           current_config->name & (mask), \
8067                           pipe_config->name & (mask)); \
8068                 return false; \
8069         }
8070
8071 #define PIPE_CONF_QUIRK(quirk)  \
8072         ((current_config->quirks | pipe_config->quirks) & (quirk))
8073
8074         PIPE_CONF_CHECK_I(cpu_transcoder);
8075
8076         PIPE_CONF_CHECK_I(has_pch_encoder);
8077         PIPE_CONF_CHECK_I(fdi_lanes);
8078         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8079         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8080         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8081         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8082         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8083
8084         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8085         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8086         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8087         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8088         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8089         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8090
8091         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8092         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8093         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8094         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8095         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8096         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8097
8098         if (!HAS_PCH_SPLIT(dev))
8099                 PIPE_CONF_CHECK_I(pixel_multiplier);
8100
8101         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8102                               DRM_MODE_FLAG_INTERLACE);
8103
8104         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8105                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8106                                       DRM_MODE_FLAG_PHSYNC);
8107                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8108                                       DRM_MODE_FLAG_NHSYNC);
8109                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8110                                       DRM_MODE_FLAG_PVSYNC);
8111                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8112                                       DRM_MODE_FLAG_NVSYNC);
8113         }
8114
8115         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8116         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8117
8118         PIPE_CONF_CHECK_I(gmch_pfit.control);
8119         /* pfit ratios are autocomputed by the hw on gen4+ */
8120         if (INTEL_INFO(dev)->gen < 4)
8121                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8122         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8123         PIPE_CONF_CHECK_I(pch_pfit.pos);
8124         PIPE_CONF_CHECK_I(pch_pfit.size);
8125
8126         PIPE_CONF_CHECK_I(ips_enabled);
8127
8128         PIPE_CONF_CHECK_I(shared_dpll);
8129         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8130         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8131         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8132
8133 #undef PIPE_CONF_CHECK_X
8134 #undef PIPE_CONF_CHECK_I
8135 #undef PIPE_CONF_CHECK_FLAGS
8136 #undef PIPE_CONF_QUIRK
8137
8138         return true;
8139 }
8140
8141 static void
8142 check_connector_state(struct drm_device *dev)
8143 {
8144         struct intel_connector *connector;
8145
8146         list_for_each_entry(connector, &dev->mode_config.connector_list,
8147                             base.head) {
8148                 /* This also checks the encoder/connector hw state with the
8149                  * ->get_hw_state callbacks. */
8150                 intel_connector_check_state(connector);
8151
8152                 WARN(&connector->new_encoder->base != connector->base.encoder,
8153                      "connector's staged encoder doesn't match current encoder\n");
8154         }
8155 }
8156
8157 static void
8158 check_encoder_state(struct drm_device *dev)
8159 {
8160         struct intel_encoder *encoder;
8161         struct intel_connector *connector;
8162
8163         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8164                             base.head) {
8165                 bool enabled = false;
8166                 bool active = false;
8167                 enum pipe pipe, tracked_pipe;
8168
8169                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8170                               encoder->base.base.id,
8171                               drm_get_encoder_name(&encoder->base));
8172
8173                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8174                      "encoder's stage crtc doesn't match current crtc\n");
8175                 WARN(encoder->connectors_active && !encoder->base.crtc,
8176                      "encoder's active_connectors set, but no crtc\n");
8177
8178                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8179                                     base.head) {
8180                         if (connector->base.encoder != &encoder->base)
8181                                 continue;
8182                         enabled = true;
8183                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8184                                 active = true;
8185                 }
8186                 WARN(!!encoder->base.crtc != enabled,
8187                      "encoder's enabled state mismatch "
8188                      "(expected %i, found %i)\n",
8189                      !!encoder->base.crtc, enabled);
8190                 WARN(active && !encoder->base.crtc,
8191                      "active encoder with no crtc\n");
8192
8193                 WARN(encoder->connectors_active != active,
8194                      "encoder's computed active state doesn't match tracked active state "
8195                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8196
8197                 active = encoder->get_hw_state(encoder, &pipe);
8198                 WARN(active != encoder->connectors_active,
8199                      "encoder's hw state doesn't match sw tracking "
8200                      "(expected %i, found %i)\n",
8201                      encoder->connectors_active, active);
8202
8203                 if (!encoder->base.crtc)
8204                         continue;
8205
8206                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8207                 WARN(active && pipe != tracked_pipe,
8208                      "active encoder's pipe doesn't match"
8209                      "(expected %i, found %i)\n",
8210                      tracked_pipe, pipe);
8211
8212         }
8213 }
8214
8215 static void
8216 check_crtc_state(struct drm_device *dev)
8217 {
8218         drm_i915_private_t *dev_priv = dev->dev_private;
8219         struct intel_crtc *crtc;
8220         struct intel_encoder *encoder;
8221         struct intel_crtc_config pipe_config;
8222
8223         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8224                             base.head) {
8225                 bool enabled = false;
8226                 bool active = false;
8227
8228                 memset(&pipe_config, 0, sizeof(pipe_config));
8229
8230                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8231                               crtc->base.base.id);
8232
8233                 WARN(crtc->active && !crtc->base.enabled,
8234                      "active crtc, but not enabled in sw tracking\n");
8235
8236                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8237                                     base.head) {
8238                         if (encoder->base.crtc != &crtc->base)
8239                                 continue;
8240                         enabled = true;
8241                         if (encoder->connectors_active)
8242                                 active = true;
8243                 }
8244
8245                 WARN(active != crtc->active,
8246                      "crtc's computed active state doesn't match tracked active state "
8247                      "(expected %i, found %i)\n", active, crtc->active);
8248                 WARN(enabled != crtc->base.enabled,
8249                      "crtc's computed enabled state doesn't match tracked enabled state "
8250                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8251
8252                 active = dev_priv->display.get_pipe_config(crtc,
8253                                                            &pipe_config);
8254
8255                 /* hw state is inconsistent with the pipe A quirk */
8256                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8257                         active = crtc->active;
8258
8259                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8260                                     base.head) {
8261                         if (encoder->base.crtc != &crtc->base)
8262                                 continue;
8263                         if (encoder->get_config)
8264                                 encoder->get_config(encoder, &pipe_config);
8265                 }
8266
8267                 WARN(crtc->active != active,
8268                      "crtc active state doesn't match with hw state "
8269                      "(expected %i, found %i)\n", crtc->active, active);
8270
8271                 if (active &&
8272                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8273                         WARN(1, "pipe state doesn't match!\n");
8274                         intel_dump_pipe_config(crtc, &pipe_config,
8275                                                "[hw state]");
8276                         intel_dump_pipe_config(crtc, &crtc->config,
8277                                                "[sw state]");
8278                 }
8279         }
8280 }
8281
8282 static void
8283 check_shared_dpll_state(struct drm_device *dev)
8284 {
8285         drm_i915_private_t *dev_priv = dev->dev_private;
8286         struct intel_crtc *crtc;
8287         struct intel_dpll_hw_state dpll_hw_state;
8288         int i;
8289
8290         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8291                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8292                 int enabled_crtcs = 0, active_crtcs = 0;
8293                 bool active;
8294
8295                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8296
8297                 DRM_DEBUG_KMS("%s\n", pll->name);
8298
8299                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8300
8301                 WARN(pll->active > pll->refcount,
8302                      "more active pll users than references: %i vs %i\n",
8303                      pll->active, pll->refcount);
8304                 WARN(pll->active && !pll->on,
8305                      "pll in active use but not on in sw tracking\n");
8306                 WARN(pll->on != active,
8307                      "pll on state mismatch (expected %i, found %i)\n",
8308                      pll->on, active);
8309
8310                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8311                                     base.head) {
8312                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8313                                 enabled_crtcs++;
8314                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8315                                 active_crtcs++;
8316                 }
8317                 WARN(pll->active != active_crtcs,
8318                      "pll active crtcs mismatch (expected %i, found %i)\n",
8319                      pll->active, active_crtcs);
8320                 WARN(pll->refcount != enabled_crtcs,
8321                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8322                      pll->refcount, enabled_crtcs);
8323
8324                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8325                                        sizeof(dpll_hw_state)),
8326                      "pll hw state mismatch\n");
8327         }
8328 }
8329
8330 void
8331 intel_modeset_check_state(struct drm_device *dev)
8332 {
8333         check_connector_state(dev);
8334         check_encoder_state(dev);
8335         check_crtc_state(dev);
8336         check_shared_dpll_state(dev);
8337 }
8338
8339 static int __intel_set_mode(struct drm_crtc *crtc,
8340                             struct drm_display_mode *mode,
8341                             int x, int y, struct drm_framebuffer *fb)
8342 {
8343         struct drm_device *dev = crtc->dev;
8344         drm_i915_private_t *dev_priv = dev->dev_private;
8345         struct drm_display_mode *saved_mode, *saved_hwmode;
8346         struct intel_crtc_config *pipe_config = NULL;
8347         struct intel_crtc *intel_crtc;
8348         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8349         int ret = 0;
8350
8351         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8352         if (!saved_mode)
8353                 return -ENOMEM;
8354         saved_hwmode = saved_mode + 1;
8355
8356         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8357                                      &prepare_pipes, &disable_pipes);
8358
8359         *saved_hwmode = crtc->hwmode;
8360         *saved_mode = crtc->mode;
8361
8362         /* Hack: Because we don't (yet) support global modeset on multiple
8363          * crtcs, we don't keep track of the new mode for more than one crtc.
8364          * Hence simply check whether any bit is set in modeset_pipes in all the
8365          * pieces of code that are not yet converted to deal with mutliple crtcs
8366          * changing their mode at the same time. */
8367         if (modeset_pipes) {
8368                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8369                 if (IS_ERR(pipe_config)) {
8370                         ret = PTR_ERR(pipe_config);
8371                         pipe_config = NULL;
8372
8373                         goto out;
8374                 }
8375                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8376                                        "[modeset]");
8377         }
8378
8379         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8380                 intel_crtc_disable(&intel_crtc->base);
8381
8382         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8383                 if (intel_crtc->base.enabled)
8384                         dev_priv->display.crtc_disable(&intel_crtc->base);
8385         }
8386
8387         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8388          * to set it here already despite that we pass it down the callchain.
8389          */
8390         if (modeset_pipes) {
8391                 crtc->mode = *mode;
8392                 /* mode_set/enable/disable functions rely on a correct pipe
8393                  * config. */
8394                 to_intel_crtc(crtc)->config = *pipe_config;
8395         }
8396
8397         /* Only after disabling all output pipelines that will be changed can we
8398          * update the the output configuration. */
8399         intel_modeset_update_state(dev, prepare_pipes);
8400
8401         if (dev_priv->display.modeset_global_resources)
8402                 dev_priv->display.modeset_global_resources(dev);
8403
8404         /* Set up the DPLL and any encoders state that needs to adjust or depend
8405          * on the DPLL.
8406          */
8407         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8408                 ret = intel_crtc_mode_set(&intel_crtc->base,
8409                                           x, y, fb);
8410                 if (ret)
8411                         goto done;
8412         }
8413
8414         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8415         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8416                 dev_priv->display.crtc_enable(&intel_crtc->base);
8417
8418         if (modeset_pipes) {
8419                 /* Store real post-adjustment hardware mode. */
8420                 crtc->hwmode = pipe_config->adjusted_mode;
8421
8422                 /* Calculate and store various constants which
8423                  * are later needed by vblank and swap-completion
8424                  * timestamping. They are derived from true hwmode.
8425                  */
8426                 drm_calc_timestamping_constants(crtc);
8427         }
8428
8429         /* FIXME: add subpixel order */
8430 done:
8431         if (ret && crtc->enabled) {
8432                 crtc->hwmode = *saved_hwmode;
8433                 crtc->mode = *saved_mode;
8434         }
8435
8436 out:
8437         kfree(pipe_config);
8438         kfree(saved_mode);
8439         return ret;
8440 }
8441
8442 int intel_set_mode(struct drm_crtc *crtc,
8443                      struct drm_display_mode *mode,
8444                      int x, int y, struct drm_framebuffer *fb)
8445 {
8446         int ret;
8447
8448         ret = __intel_set_mode(crtc, mode, x, y, fb);
8449
8450         if (ret == 0)
8451                 intel_modeset_check_state(crtc->dev);
8452
8453         return ret;
8454 }
8455
8456 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8457 {
8458         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8459 }
8460
8461 #undef for_each_intel_crtc_masked
8462
8463 static void intel_set_config_free(struct intel_set_config *config)
8464 {
8465         if (!config)
8466                 return;
8467
8468         kfree(config->save_connector_encoders);
8469         kfree(config->save_encoder_crtcs);
8470         kfree(config);
8471 }
8472
8473 static int intel_set_config_save_state(struct drm_device *dev,
8474                                        struct intel_set_config *config)
8475 {
8476         struct drm_encoder *encoder;
8477         struct drm_connector *connector;
8478         int count;
8479
8480         config->save_encoder_crtcs =
8481                 kcalloc(dev->mode_config.num_encoder,
8482                         sizeof(struct drm_crtc *), GFP_KERNEL);
8483         if (!config->save_encoder_crtcs)
8484                 return -ENOMEM;
8485
8486         config->save_connector_encoders =
8487                 kcalloc(dev->mode_config.num_connector,
8488                         sizeof(struct drm_encoder *), GFP_KERNEL);
8489         if (!config->save_connector_encoders)
8490                 return -ENOMEM;
8491
8492         /* Copy data. Note that driver private data is not affected.
8493          * Should anything bad happen only the expected state is
8494          * restored, not the drivers personal bookkeeping.
8495          */
8496         count = 0;
8497         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8498                 config->save_encoder_crtcs[count++] = encoder->crtc;
8499         }
8500
8501         count = 0;
8502         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8503                 config->save_connector_encoders[count++] = connector->encoder;
8504         }
8505
8506         return 0;
8507 }
8508
8509 static void intel_set_config_restore_state(struct drm_device *dev,
8510                                            struct intel_set_config *config)
8511 {
8512         struct intel_encoder *encoder;
8513         struct intel_connector *connector;
8514         int count;
8515
8516         count = 0;
8517         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8518                 encoder->new_crtc =
8519                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8520         }
8521
8522         count = 0;
8523         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8524                 connector->new_encoder =
8525                         to_intel_encoder(config->save_connector_encoders[count++]);
8526         }
8527 }
8528
8529 static bool
8530 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8531                       int num_connectors)
8532 {
8533         int i;
8534
8535         for (i = 0; i < num_connectors; i++)
8536                 if (connectors[i].encoder &&
8537                     connectors[i].encoder->crtc == crtc &&
8538                     connectors[i].dpms != DRM_MODE_DPMS_ON)
8539                         return true;
8540
8541         return false;
8542 }
8543
8544 static void
8545 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8546                                       struct intel_set_config *config)
8547 {
8548
8549         /* We should be able to check here if the fb has the same properties
8550          * and then just flip_or_move it */
8551         if (set->connectors != NULL &&
8552             is_crtc_connector_off(set->crtc, *set->connectors,
8553                                   set->num_connectors)) {
8554                         config->mode_changed = true;
8555         } else if (set->crtc->fb != set->fb) {
8556                 /* If we have no fb then treat it as a full mode set */
8557                 if (set->crtc->fb == NULL) {
8558                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8559                         config->mode_changed = true;
8560                 } else if (set->fb == NULL) {
8561                         config->mode_changed = true;
8562                 } else if (set->fb->pixel_format !=
8563                            set->crtc->fb->pixel_format) {
8564                         config->mode_changed = true;
8565                 } else {
8566                         config->fb_changed = true;
8567                 }
8568         }
8569
8570         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8571                 config->fb_changed = true;
8572
8573         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8574                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8575                 drm_mode_debug_printmodeline(&set->crtc->mode);
8576                 drm_mode_debug_printmodeline(set->mode);
8577                 config->mode_changed = true;
8578         }
8579 }
8580
8581 static int
8582 intel_modeset_stage_output_state(struct drm_device *dev,
8583                                  struct drm_mode_set *set,
8584                                  struct intel_set_config *config)
8585 {
8586         struct drm_crtc *new_crtc;
8587         struct intel_connector *connector;
8588         struct intel_encoder *encoder;
8589         int count, ro;
8590
8591         /* The upper layers ensure that we either disable a crtc or have a list
8592          * of connectors. For paranoia, double-check this. */
8593         WARN_ON(!set->fb && (set->num_connectors != 0));
8594         WARN_ON(set->fb && (set->num_connectors == 0));
8595
8596         count = 0;
8597         list_for_each_entry(connector, &dev->mode_config.connector_list,
8598                             base.head) {
8599                 /* Otherwise traverse passed in connector list and get encoders
8600                  * for them. */
8601                 for (ro = 0; ro < set->num_connectors; ro++) {
8602                         if (set->connectors[ro] == &connector->base) {
8603                                 connector->new_encoder = connector->encoder;
8604                                 break;
8605                         }
8606                 }
8607
8608                 /* If we disable the crtc, disable all its connectors. Also, if
8609                  * the connector is on the changing crtc but not on the new
8610                  * connector list, disable it. */
8611                 if ((!set->fb || ro == set->num_connectors) &&
8612                     connector->base.encoder &&
8613                     connector->base.encoder->crtc == set->crtc) {
8614                         connector->new_encoder = NULL;
8615
8616                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8617                                 connector->base.base.id,
8618                                 drm_get_connector_name(&connector->base));
8619                 }
8620
8621
8622                 if (&connector->new_encoder->base != connector->base.encoder) {
8623                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8624                         config->mode_changed = true;
8625                 }
8626         }
8627         /* connector->new_encoder is now updated for all connectors. */
8628
8629         /* Update crtc of enabled connectors. */
8630         count = 0;
8631         list_for_each_entry(connector, &dev->mode_config.connector_list,
8632                             base.head) {
8633                 if (!connector->new_encoder)
8634                         continue;
8635
8636                 new_crtc = connector->new_encoder->base.crtc;
8637
8638                 for (ro = 0; ro < set->num_connectors; ro++) {
8639                         if (set->connectors[ro] == &connector->base)
8640                                 new_crtc = set->crtc;
8641                 }
8642
8643                 /* Make sure the new CRTC will work with the encoder */
8644                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8645                                            new_crtc)) {
8646                         return -EINVAL;
8647                 }
8648                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8649
8650                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8651                         connector->base.base.id,
8652                         drm_get_connector_name(&connector->base),
8653                         new_crtc->base.id);
8654         }
8655
8656         /* Check for any encoders that needs to be disabled. */
8657         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8658                             base.head) {
8659                 list_for_each_entry(connector,
8660                                     &dev->mode_config.connector_list,
8661                                     base.head) {
8662                         if (connector->new_encoder == encoder) {
8663                                 WARN_ON(!connector->new_encoder->new_crtc);
8664
8665                                 goto next_encoder;
8666                         }
8667                 }
8668                 encoder->new_crtc = NULL;
8669 next_encoder:
8670                 /* Only now check for crtc changes so we don't miss encoders
8671                  * that will be disabled. */
8672                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8673                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8674                         config->mode_changed = true;
8675                 }
8676         }
8677         /* Now we've also updated encoder->new_crtc for all encoders. */
8678
8679         return 0;
8680 }
8681
8682 static int intel_crtc_set_config(struct drm_mode_set *set)
8683 {
8684         struct drm_device *dev;
8685         struct drm_mode_set save_set;
8686         struct intel_set_config *config;
8687         int ret;
8688
8689         BUG_ON(!set);
8690         BUG_ON(!set->crtc);
8691         BUG_ON(!set->crtc->helper_private);
8692
8693         /* Enforce sane interface api - has been abused by the fb helper. */
8694         BUG_ON(!set->mode && set->fb);
8695         BUG_ON(set->fb && set->num_connectors == 0);
8696
8697         if (set->fb) {
8698                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8699                                 set->crtc->base.id, set->fb->base.id,
8700                                 (int)set->num_connectors, set->x, set->y);
8701         } else {
8702                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8703         }
8704
8705         dev = set->crtc->dev;
8706
8707         ret = -ENOMEM;
8708         config = kzalloc(sizeof(*config), GFP_KERNEL);
8709         if (!config)
8710                 goto out_config;
8711
8712         ret = intel_set_config_save_state(dev, config);
8713         if (ret)
8714                 goto out_config;
8715
8716         save_set.crtc = set->crtc;
8717         save_set.mode = &set->crtc->mode;
8718         save_set.x = set->crtc->x;
8719         save_set.y = set->crtc->y;
8720         save_set.fb = set->crtc->fb;
8721
8722         /* Compute whether we need a full modeset, only an fb base update or no
8723          * change at all. In the future we might also check whether only the
8724          * mode changed, e.g. for LVDS where we only change the panel fitter in
8725          * such cases. */
8726         intel_set_config_compute_mode_changes(set, config);
8727
8728         ret = intel_modeset_stage_output_state(dev, set, config);
8729         if (ret)
8730                 goto fail;
8731
8732         if (config->mode_changed) {
8733                 ret = intel_set_mode(set->crtc, set->mode,
8734                                      set->x, set->y, set->fb);
8735         } else if (config->fb_changed) {
8736                 intel_crtc_wait_for_pending_flips(set->crtc);
8737
8738                 ret = intel_pipe_set_base(set->crtc,
8739                                           set->x, set->y, set->fb);
8740         }
8741
8742         if (ret) {
8743                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8744                               set->crtc->base.id, ret);
8745 fail:
8746                 intel_set_config_restore_state(dev, config);
8747
8748                 /* Try to restore the config */
8749                 if (config->mode_changed &&
8750                     intel_set_mode(save_set.crtc, save_set.mode,
8751                                    save_set.x, save_set.y, save_set.fb))
8752                         DRM_ERROR("failed to restore config after modeset failure\n");
8753         }
8754
8755 out_config:
8756         intel_set_config_free(config);
8757         return ret;
8758 }
8759
8760 static const struct drm_crtc_funcs intel_crtc_funcs = {
8761         .cursor_set = intel_crtc_cursor_set,
8762         .cursor_move = intel_crtc_cursor_move,
8763         .gamma_set = intel_crtc_gamma_set,
8764         .set_config = intel_crtc_set_config,
8765         .destroy = intel_crtc_destroy,
8766         .page_flip = intel_crtc_page_flip,
8767 };
8768
8769 static void intel_cpu_pll_init(struct drm_device *dev)
8770 {
8771         if (HAS_DDI(dev))
8772                 intel_ddi_pll_init(dev);
8773 }
8774
8775 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8776                                       struct intel_shared_dpll *pll,
8777                                       struct intel_dpll_hw_state *hw_state)
8778 {
8779         uint32_t val;
8780
8781         val = I915_READ(PCH_DPLL(pll->id));
8782         hw_state->dpll = val;
8783         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8784         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8785
8786         return val & DPLL_VCO_ENABLE;
8787 }
8788
8789 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8790                                   struct intel_shared_dpll *pll)
8791 {
8792         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8793         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8794 }
8795
8796 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8797                                 struct intel_shared_dpll *pll)
8798 {
8799         /* PCH refclock must be enabled first */
8800         assert_pch_refclk_enabled(dev_priv);
8801
8802         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8803
8804         /* Wait for the clocks to stabilize. */
8805         POSTING_READ(PCH_DPLL(pll->id));
8806         udelay(150);
8807
8808         /* The pixel multiplier can only be updated once the
8809          * DPLL is enabled and the clocks are stable.
8810          *
8811          * So write it again.
8812          */
8813         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8814         POSTING_READ(PCH_DPLL(pll->id));
8815         udelay(200);
8816 }
8817
8818 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8819                                  struct intel_shared_dpll *pll)
8820 {
8821         struct drm_device *dev = dev_priv->dev;
8822         struct intel_crtc *crtc;
8823
8824         /* Make sure no transcoder isn't still depending on us. */
8825         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8826                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8827                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8828         }
8829
8830         I915_WRITE(PCH_DPLL(pll->id), 0);
8831         POSTING_READ(PCH_DPLL(pll->id));
8832         udelay(200);
8833 }
8834
8835 static char *ibx_pch_dpll_names[] = {
8836         "PCH DPLL A",
8837         "PCH DPLL B",
8838 };
8839
8840 static void ibx_pch_dpll_init(struct drm_device *dev)
8841 {
8842         struct drm_i915_private *dev_priv = dev->dev_private;
8843         int i;
8844
8845         dev_priv->num_shared_dpll = 2;
8846
8847         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8848                 dev_priv->shared_dplls[i].id = i;
8849                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8850                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8851                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8852                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8853                 dev_priv->shared_dplls[i].get_hw_state =
8854                         ibx_pch_dpll_get_hw_state;
8855         }
8856 }
8857
8858 static void intel_shared_dpll_init(struct drm_device *dev)
8859 {
8860         struct drm_i915_private *dev_priv = dev->dev_private;
8861
8862         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8863                 ibx_pch_dpll_init(dev);
8864         else
8865                 dev_priv->num_shared_dpll = 0;
8866
8867         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8868         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8869                       dev_priv->num_shared_dpll);
8870 }
8871
8872 static void intel_crtc_init(struct drm_device *dev, int pipe)
8873 {
8874         drm_i915_private_t *dev_priv = dev->dev_private;
8875         struct intel_crtc *intel_crtc;
8876         int i;
8877
8878         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8879         if (intel_crtc == NULL)
8880                 return;
8881
8882         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8883
8884         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8885         for (i = 0; i < 256; i++) {
8886                 intel_crtc->lut_r[i] = i;
8887                 intel_crtc->lut_g[i] = i;
8888                 intel_crtc->lut_b[i] = i;
8889         }
8890
8891         /* Swap pipes & planes for FBC on pre-965 */
8892         intel_crtc->pipe = pipe;
8893         intel_crtc->plane = pipe;
8894         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8895                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8896                 intel_crtc->plane = !pipe;
8897         }
8898
8899         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8900                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8901         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8902         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8903
8904         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8905 }
8906
8907 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8908                                 struct drm_file *file)
8909 {
8910         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8911         struct drm_mode_object *drmmode_obj;
8912         struct intel_crtc *crtc;
8913
8914         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8915                 return -ENODEV;
8916
8917         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8918                         DRM_MODE_OBJECT_CRTC);
8919
8920         if (!drmmode_obj) {
8921                 DRM_ERROR("no such CRTC id\n");
8922                 return -EINVAL;
8923         }
8924
8925         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8926         pipe_from_crtc_id->pipe = crtc->pipe;
8927
8928         return 0;
8929 }
8930
8931 static int intel_encoder_clones(struct intel_encoder *encoder)
8932 {
8933         struct drm_device *dev = encoder->base.dev;
8934         struct intel_encoder *source_encoder;
8935         int index_mask = 0;
8936         int entry = 0;
8937
8938         list_for_each_entry(source_encoder,
8939                             &dev->mode_config.encoder_list, base.head) {
8940
8941                 if (encoder == source_encoder)
8942                         index_mask |= (1 << entry);
8943
8944                 /* Intel hw has only one MUX where enocoders could be cloned. */
8945                 if (encoder->cloneable && source_encoder->cloneable)
8946                         index_mask |= (1 << entry);
8947
8948                 entry++;
8949         }
8950
8951         return index_mask;
8952 }
8953
8954 static bool has_edp_a(struct drm_device *dev)
8955 {
8956         struct drm_i915_private *dev_priv = dev->dev_private;
8957
8958         if (!IS_MOBILE(dev))
8959                 return false;
8960
8961         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8962                 return false;
8963
8964         if (IS_GEN5(dev) &&
8965             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8966                 return false;
8967
8968         return true;
8969 }
8970
8971 static void intel_setup_outputs(struct drm_device *dev)
8972 {
8973         struct drm_i915_private *dev_priv = dev->dev_private;
8974         struct intel_encoder *encoder;
8975         bool dpd_is_edp = false;
8976
8977         intel_lvds_init(dev);
8978
8979         if (!IS_ULT(dev))
8980                 intel_crt_init(dev);
8981
8982         if (HAS_DDI(dev)) {
8983                 int found;
8984
8985                 /* Haswell uses DDI functions to detect digital outputs */
8986                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8987                 /* DDI A only supports eDP */
8988                 if (found)
8989                         intel_ddi_init(dev, PORT_A);
8990
8991                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8992                  * register */
8993                 found = I915_READ(SFUSE_STRAP);
8994
8995                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8996                         intel_ddi_init(dev, PORT_B);
8997                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8998                         intel_ddi_init(dev, PORT_C);
8999                 if (found & SFUSE_STRAP_DDID_DETECTED)
9000                         intel_ddi_init(dev, PORT_D);
9001         } else if (HAS_PCH_SPLIT(dev)) {
9002                 int found;
9003                 dpd_is_edp = intel_dpd_is_edp(dev);
9004
9005                 if (has_edp_a(dev))
9006                         intel_dp_init(dev, DP_A, PORT_A);
9007
9008                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9009                         /* PCH SDVOB multiplex with HDMIB */
9010                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9011                         if (!found)
9012                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9013                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9014                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9015                 }
9016
9017                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9018                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9019
9020                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9021                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9022
9023                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9024                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9025
9026                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9027                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9028         } else if (IS_VALLEYVIEW(dev)) {
9029                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9030                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9031                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9032
9033                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9034                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9035                                         PORT_B);
9036                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9037                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9038                 }
9039         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9040                 bool found = false;
9041
9042                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9043                         DRM_DEBUG_KMS("probing SDVOB\n");
9044                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9045                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9046                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9047                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9048                         }
9049
9050                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9051                                 intel_dp_init(dev, DP_B, PORT_B);
9052                 }
9053
9054                 /* Before G4X SDVOC doesn't have its own detect register */
9055
9056                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9057                         DRM_DEBUG_KMS("probing SDVOC\n");
9058                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9059                 }
9060
9061                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9062
9063                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9064                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9065                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9066                         }
9067                         if (SUPPORTS_INTEGRATED_DP(dev))
9068                                 intel_dp_init(dev, DP_C, PORT_C);
9069                 }
9070
9071                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9072                     (I915_READ(DP_D) & DP_DETECTED))
9073                         intel_dp_init(dev, DP_D, PORT_D);
9074         } else if (IS_GEN2(dev))
9075                 intel_dvo_init(dev);
9076
9077         if (SUPPORTS_TV(dev))
9078                 intel_tv_init(dev);
9079
9080         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9081                 encoder->base.possible_crtcs = encoder->crtc_mask;
9082                 encoder->base.possible_clones =
9083                         intel_encoder_clones(encoder);
9084         }
9085
9086         intel_init_pch_refclk(dev);
9087
9088         drm_helper_move_panel_connectors_to_head(dev);
9089 }
9090
9091 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9092 {
9093         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9094
9095         drm_framebuffer_cleanup(fb);
9096         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9097
9098         kfree(intel_fb);
9099 }
9100
9101 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9102                                                 struct drm_file *file,
9103                                                 unsigned int *handle)
9104 {
9105         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9106         struct drm_i915_gem_object *obj = intel_fb->obj;
9107
9108         return drm_gem_handle_create(file, &obj->base, handle);
9109 }
9110
9111 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9112         .destroy = intel_user_framebuffer_destroy,
9113         .create_handle = intel_user_framebuffer_create_handle,
9114 };
9115
9116 int intel_framebuffer_init(struct drm_device *dev,
9117                            struct intel_framebuffer *intel_fb,
9118                            struct drm_mode_fb_cmd2 *mode_cmd,
9119                            struct drm_i915_gem_object *obj)
9120 {
9121         int pitch_limit;
9122         int ret;
9123
9124         if (obj->tiling_mode == I915_TILING_Y) {
9125                 DRM_DEBUG("hardware does not support tiling Y\n");
9126                 return -EINVAL;
9127         }
9128
9129         if (mode_cmd->pitches[0] & 63) {
9130                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9131                           mode_cmd->pitches[0]);
9132                 return -EINVAL;
9133         }
9134
9135         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9136                 pitch_limit = 32*1024;
9137         } else if (INTEL_INFO(dev)->gen >= 4) {
9138                 if (obj->tiling_mode)
9139                         pitch_limit = 16*1024;
9140                 else
9141                         pitch_limit = 32*1024;
9142         } else if (INTEL_INFO(dev)->gen >= 3) {
9143                 if (obj->tiling_mode)
9144                         pitch_limit = 8*1024;
9145                 else
9146                         pitch_limit = 16*1024;
9147         } else
9148                 /* XXX DSPC is limited to 4k tiled */
9149                 pitch_limit = 8*1024;
9150
9151         if (mode_cmd->pitches[0] > pitch_limit) {
9152                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9153                           obj->tiling_mode ? "tiled" : "linear",
9154                           mode_cmd->pitches[0], pitch_limit);
9155                 return -EINVAL;
9156         }
9157
9158         if (obj->tiling_mode != I915_TILING_NONE &&
9159             mode_cmd->pitches[0] != obj->stride) {
9160                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9161                           mode_cmd->pitches[0], obj->stride);
9162                 return -EINVAL;
9163         }
9164
9165         /* Reject formats not supported by any plane early. */
9166         switch (mode_cmd->pixel_format) {
9167         case DRM_FORMAT_C8:
9168         case DRM_FORMAT_RGB565:
9169         case DRM_FORMAT_XRGB8888:
9170         case DRM_FORMAT_ARGB8888:
9171                 break;
9172         case DRM_FORMAT_XRGB1555:
9173         case DRM_FORMAT_ARGB1555:
9174                 if (INTEL_INFO(dev)->gen > 3) {
9175                         DRM_DEBUG("unsupported pixel format: %s\n",
9176                                   drm_get_format_name(mode_cmd->pixel_format));
9177                         return -EINVAL;
9178                 }
9179                 break;
9180         case DRM_FORMAT_XBGR8888:
9181         case DRM_FORMAT_ABGR8888:
9182         case DRM_FORMAT_XRGB2101010:
9183         case DRM_FORMAT_ARGB2101010:
9184         case DRM_FORMAT_XBGR2101010:
9185         case DRM_FORMAT_ABGR2101010:
9186                 if (INTEL_INFO(dev)->gen < 4) {
9187                         DRM_DEBUG("unsupported pixel format: %s\n",
9188                                   drm_get_format_name(mode_cmd->pixel_format));
9189                         return -EINVAL;
9190                 }
9191                 break;
9192         case DRM_FORMAT_YUYV:
9193         case DRM_FORMAT_UYVY:
9194         case DRM_FORMAT_YVYU:
9195         case DRM_FORMAT_VYUY:
9196                 if (INTEL_INFO(dev)->gen < 5) {
9197                         DRM_DEBUG("unsupported pixel format: %s\n",
9198                                   drm_get_format_name(mode_cmd->pixel_format));
9199                         return -EINVAL;
9200                 }
9201                 break;
9202         default:
9203                 DRM_DEBUG("unsupported pixel format: %s\n",
9204                           drm_get_format_name(mode_cmd->pixel_format));
9205                 return -EINVAL;
9206         }
9207
9208         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9209         if (mode_cmd->offsets[0] != 0)
9210                 return -EINVAL;
9211
9212         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9213         intel_fb->obj = obj;
9214
9215         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9216         if (ret) {
9217                 DRM_ERROR("framebuffer init failed %d\n", ret);
9218                 return ret;
9219         }
9220
9221         return 0;
9222 }
9223
9224 static struct drm_framebuffer *
9225 intel_user_framebuffer_create(struct drm_device *dev,
9226                               struct drm_file *filp,
9227                               struct drm_mode_fb_cmd2 *mode_cmd)
9228 {
9229         struct drm_i915_gem_object *obj;
9230
9231         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9232                                                 mode_cmd->handles[0]));
9233         if (&obj->base == NULL)
9234                 return ERR_PTR(-ENOENT);
9235
9236         return intel_framebuffer_create(dev, mode_cmd, obj);
9237 }
9238
9239 static const struct drm_mode_config_funcs intel_mode_funcs = {
9240         .fb_create = intel_user_framebuffer_create,
9241         .output_poll_changed = intel_fb_output_poll_changed,
9242 };
9243
9244 /* Set up chip specific display functions */
9245 static void intel_init_display(struct drm_device *dev)
9246 {
9247         struct drm_i915_private *dev_priv = dev->dev_private;
9248
9249         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9250                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9251         else if (IS_VALLEYVIEW(dev))
9252                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9253         else if (IS_PINEVIEW(dev))
9254                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9255         else
9256                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9257
9258         if (HAS_DDI(dev)) {
9259                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9260                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9261                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9262                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9263                 dev_priv->display.off = haswell_crtc_off;
9264                 dev_priv->display.update_plane = ironlake_update_plane;
9265         } else if (HAS_PCH_SPLIT(dev)) {
9266                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9267                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9268                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9269                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9270                 dev_priv->display.off = ironlake_crtc_off;
9271                 dev_priv->display.update_plane = ironlake_update_plane;
9272         } else if (IS_VALLEYVIEW(dev)) {
9273                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9274                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9275                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9276                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9277                 dev_priv->display.off = i9xx_crtc_off;
9278                 dev_priv->display.update_plane = i9xx_update_plane;
9279         } else {
9280                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9281                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9282                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9283                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9284                 dev_priv->display.off = i9xx_crtc_off;
9285                 dev_priv->display.update_plane = i9xx_update_plane;
9286         }
9287
9288         /* Returns the core display clock speed */
9289         if (IS_VALLEYVIEW(dev))
9290                 dev_priv->display.get_display_clock_speed =
9291                         valleyview_get_display_clock_speed;
9292         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9293                 dev_priv->display.get_display_clock_speed =
9294                         i945_get_display_clock_speed;
9295         else if (IS_I915G(dev))
9296                 dev_priv->display.get_display_clock_speed =
9297                         i915_get_display_clock_speed;
9298         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9299                 dev_priv->display.get_display_clock_speed =
9300                         i9xx_misc_get_display_clock_speed;
9301         else if (IS_I915GM(dev))
9302                 dev_priv->display.get_display_clock_speed =
9303                         i915gm_get_display_clock_speed;
9304         else if (IS_I865G(dev))
9305                 dev_priv->display.get_display_clock_speed =
9306                         i865_get_display_clock_speed;
9307         else if (IS_I85X(dev))
9308                 dev_priv->display.get_display_clock_speed =
9309                         i855_get_display_clock_speed;
9310         else /* 852, 830 */
9311                 dev_priv->display.get_display_clock_speed =
9312                         i830_get_display_clock_speed;
9313
9314         if (HAS_PCH_SPLIT(dev)) {
9315                 if (IS_GEN5(dev)) {
9316                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9317                         dev_priv->display.write_eld = ironlake_write_eld;
9318                 } else if (IS_GEN6(dev)) {
9319                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9320                         dev_priv->display.write_eld = ironlake_write_eld;
9321                 } else if (IS_IVYBRIDGE(dev)) {
9322                         /* FIXME: detect B0+ stepping and use auto training */
9323                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9324                         dev_priv->display.write_eld = ironlake_write_eld;
9325                         dev_priv->display.modeset_global_resources =
9326                                 ivb_modeset_global_resources;
9327                 } else if (IS_HASWELL(dev)) {
9328                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9329                         dev_priv->display.write_eld = haswell_write_eld;
9330                         dev_priv->display.modeset_global_resources =
9331                                 haswell_modeset_global_resources;
9332                 }
9333         } else if (IS_G4X(dev)) {
9334                 dev_priv->display.write_eld = g4x_write_eld;
9335         }
9336
9337         /* Default just returns -ENODEV to indicate unsupported */
9338         dev_priv->display.queue_flip = intel_default_queue_flip;
9339
9340         switch (INTEL_INFO(dev)->gen) {
9341         case 2:
9342                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9343                 break;
9344
9345         case 3:
9346                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9347                 break;
9348
9349         case 4:
9350         case 5:
9351                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9352                 break;
9353
9354         case 6:
9355                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9356                 break;
9357         case 7:
9358                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9359                 break;
9360         }
9361 }
9362
9363 /*
9364  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9365  * resume, or other times.  This quirk makes sure that's the case for
9366  * affected systems.
9367  */
9368 static void quirk_pipea_force(struct drm_device *dev)
9369 {
9370         struct drm_i915_private *dev_priv = dev->dev_private;
9371
9372         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9373         DRM_INFO("applying pipe a force quirk\n");
9374 }
9375
9376 /*
9377  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9378  */
9379 static void quirk_ssc_force_disable(struct drm_device *dev)
9380 {
9381         struct drm_i915_private *dev_priv = dev->dev_private;
9382         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9383         DRM_INFO("applying lvds SSC disable quirk\n");
9384 }
9385
9386 /*
9387  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9388  * brightness value
9389  */
9390 static void quirk_invert_brightness(struct drm_device *dev)
9391 {
9392         struct drm_i915_private *dev_priv = dev->dev_private;
9393         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9394         DRM_INFO("applying inverted panel brightness quirk\n");
9395 }
9396
9397 struct intel_quirk {
9398         int device;
9399         int subsystem_vendor;
9400         int subsystem_device;
9401         void (*hook)(struct drm_device *dev);
9402 };
9403
9404 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9405 struct intel_dmi_quirk {
9406         void (*hook)(struct drm_device *dev);
9407         const struct dmi_system_id (*dmi_id_list)[];
9408 };
9409
9410 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9411 {
9412         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9413         return 1;
9414 }
9415
9416 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9417         {
9418                 .dmi_id_list = &(const struct dmi_system_id[]) {
9419                         {
9420                                 .callback = intel_dmi_reverse_brightness,
9421                                 .ident = "NCR Corporation",
9422                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9423                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9424                                 },
9425                         },
9426                         { }  /* terminating entry */
9427                 },
9428                 .hook = quirk_invert_brightness,
9429         },
9430 };
9431
9432 static struct intel_quirk intel_quirks[] = {
9433         /* HP Mini needs pipe A force quirk (LP: #322104) */
9434         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9435
9436         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9437         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9438
9439         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9440         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9441
9442         /* 830/845 need to leave pipe A & dpll A up */
9443         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9444         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9445
9446         /* Lenovo U160 cannot use SSC on LVDS */
9447         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9448
9449         /* Sony Vaio Y cannot use SSC on LVDS */
9450         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9451
9452         /* Acer Aspire 5734Z must invert backlight brightness */
9453         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9454
9455         /* Acer/eMachines G725 */
9456         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9457
9458         /* Acer/eMachines e725 */
9459         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9460
9461         /* Acer/Packard Bell NCL20 */
9462         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9463
9464         /* Acer Aspire 4736Z */
9465         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9466 };
9467
9468 static void intel_init_quirks(struct drm_device *dev)
9469 {
9470         struct pci_dev *d = dev->pdev;
9471         int i;
9472
9473         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9474                 struct intel_quirk *q = &intel_quirks[i];
9475
9476                 if (d->device == q->device &&
9477                     (d->subsystem_vendor == q->subsystem_vendor ||
9478                      q->subsystem_vendor == PCI_ANY_ID) &&
9479                     (d->subsystem_device == q->subsystem_device ||
9480                      q->subsystem_device == PCI_ANY_ID))
9481                         q->hook(dev);
9482         }
9483         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9484                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9485                         intel_dmi_quirks[i].hook(dev);
9486         }
9487 }
9488
9489 /* Disable the VGA plane that we never use */
9490 static void i915_disable_vga(struct drm_device *dev)
9491 {
9492         struct drm_i915_private *dev_priv = dev->dev_private;
9493         u8 sr1;
9494         u32 vga_reg = i915_vgacntrl_reg(dev);
9495
9496         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9497         outb(SR01, VGA_SR_INDEX);
9498         sr1 = inb(VGA_SR_DATA);
9499         outb(sr1 | 1<<5, VGA_SR_DATA);
9500         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9501         udelay(300);
9502
9503         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9504         POSTING_READ(vga_reg);
9505 }
9506
9507 void intel_modeset_init_hw(struct drm_device *dev)
9508 {
9509         intel_init_power_well(dev);
9510
9511         intel_prepare_ddi(dev);
9512
9513         intel_init_clock_gating(dev);
9514
9515         mutex_lock(&dev->struct_mutex);
9516         intel_enable_gt_powersave(dev);
9517         mutex_unlock(&dev->struct_mutex);
9518 }
9519
9520 void intel_modeset_suspend_hw(struct drm_device *dev)
9521 {
9522         intel_suspend_hw(dev);
9523 }
9524
9525 void intel_modeset_init(struct drm_device *dev)
9526 {
9527         struct drm_i915_private *dev_priv = dev->dev_private;
9528         int i, j, ret;
9529
9530         drm_mode_config_init(dev);
9531
9532         dev->mode_config.min_width = 0;
9533         dev->mode_config.min_height = 0;
9534
9535         dev->mode_config.preferred_depth = 24;
9536         dev->mode_config.prefer_shadow = 1;
9537
9538         dev->mode_config.funcs = &intel_mode_funcs;
9539
9540         intel_init_quirks(dev);
9541
9542         intel_init_pm(dev);
9543
9544         if (INTEL_INFO(dev)->num_pipes == 0)
9545                 return;
9546
9547         intel_init_display(dev);
9548
9549         if (IS_GEN2(dev)) {
9550                 dev->mode_config.max_width = 2048;
9551                 dev->mode_config.max_height = 2048;
9552         } else if (IS_GEN3(dev)) {
9553                 dev->mode_config.max_width = 4096;
9554                 dev->mode_config.max_height = 4096;
9555         } else {
9556                 dev->mode_config.max_width = 8192;
9557                 dev->mode_config.max_height = 8192;
9558         }
9559         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9560
9561         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9562                       INTEL_INFO(dev)->num_pipes,
9563                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9564
9565         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9566                 intel_crtc_init(dev, i);
9567                 for (j = 0; j < dev_priv->num_plane; j++) {
9568                         ret = intel_plane_init(dev, i, j);
9569                         if (ret)
9570                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9571                                               pipe_name(i), sprite_name(i, j), ret);
9572                 }
9573         }
9574
9575         intel_cpu_pll_init(dev);
9576         intel_shared_dpll_init(dev);
9577
9578         /* Just disable it once at startup */
9579         i915_disable_vga(dev);
9580         intel_setup_outputs(dev);
9581
9582         /* Just in case the BIOS is doing something questionable. */
9583         intel_disable_fbc(dev);
9584 }
9585
9586 static void
9587 intel_connector_break_all_links(struct intel_connector *connector)
9588 {
9589         connector->base.dpms = DRM_MODE_DPMS_OFF;
9590         connector->base.encoder = NULL;
9591         connector->encoder->connectors_active = false;
9592         connector->encoder->base.crtc = NULL;
9593 }
9594
9595 static void intel_enable_pipe_a(struct drm_device *dev)
9596 {
9597         struct intel_connector *connector;
9598         struct drm_connector *crt = NULL;
9599         struct intel_load_detect_pipe load_detect_temp;
9600
9601         /* We can't just switch on the pipe A, we need to set things up with a
9602          * proper mode and output configuration. As a gross hack, enable pipe A
9603          * by enabling the load detect pipe once. */
9604         list_for_each_entry(connector,
9605                             &dev->mode_config.connector_list,
9606                             base.head) {
9607                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9608                         crt = &connector->base;
9609                         break;
9610                 }
9611         }
9612
9613         if (!crt)
9614                 return;
9615
9616         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9617                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9618
9619
9620 }
9621
9622 static bool
9623 intel_check_plane_mapping(struct intel_crtc *crtc)
9624 {
9625         struct drm_device *dev = crtc->base.dev;
9626         struct drm_i915_private *dev_priv = dev->dev_private;
9627         u32 reg, val;
9628
9629         if (INTEL_INFO(dev)->num_pipes == 1)
9630                 return true;
9631
9632         reg = DSPCNTR(!crtc->plane);
9633         val = I915_READ(reg);
9634
9635         if ((val & DISPLAY_PLANE_ENABLE) &&
9636             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9637                 return false;
9638
9639         return true;
9640 }
9641
9642 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9643 {
9644         struct drm_device *dev = crtc->base.dev;
9645         struct drm_i915_private *dev_priv = dev->dev_private;
9646         u32 reg;
9647
9648         /* Clear any frame start delays used for debugging left by the BIOS */
9649         reg = PIPECONF(crtc->config.cpu_transcoder);
9650         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9651
9652         /* We need to sanitize the plane -> pipe mapping first because this will
9653          * disable the crtc (and hence change the state) if it is wrong. Note
9654          * that gen4+ has a fixed plane -> pipe mapping.  */
9655         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9656                 struct intel_connector *connector;
9657                 bool plane;
9658
9659                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9660                               crtc->base.base.id);
9661
9662                 /* Pipe has the wrong plane attached and the plane is active.
9663                  * Temporarily change the plane mapping and disable everything
9664                  * ...  */
9665                 plane = crtc->plane;
9666                 crtc->plane = !plane;
9667                 dev_priv->display.crtc_disable(&crtc->base);
9668                 crtc->plane = plane;
9669
9670                 /* ... and break all links. */
9671                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9672                                     base.head) {
9673                         if (connector->encoder->base.crtc != &crtc->base)
9674                                 continue;
9675
9676                         intel_connector_break_all_links(connector);
9677                 }
9678
9679                 WARN_ON(crtc->active);
9680                 crtc->base.enabled = false;
9681         }
9682
9683         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9684             crtc->pipe == PIPE_A && !crtc->active) {
9685                 /* BIOS forgot to enable pipe A, this mostly happens after
9686                  * resume. Force-enable the pipe to fix this, the update_dpms
9687                  * call below we restore the pipe to the right state, but leave
9688                  * the required bits on. */
9689                 intel_enable_pipe_a(dev);
9690         }
9691
9692         /* Adjust the state of the output pipe according to whether we
9693          * have active connectors/encoders. */
9694         intel_crtc_update_dpms(&crtc->base);
9695
9696         if (crtc->active != crtc->base.enabled) {
9697                 struct intel_encoder *encoder;
9698
9699                 /* This can happen either due to bugs in the get_hw_state
9700                  * functions or because the pipe is force-enabled due to the
9701                  * pipe A quirk. */
9702                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9703                               crtc->base.base.id,
9704                               crtc->base.enabled ? "enabled" : "disabled",
9705                               crtc->active ? "enabled" : "disabled");
9706
9707                 crtc->base.enabled = crtc->active;
9708
9709                 /* Because we only establish the connector -> encoder ->
9710                  * crtc links if something is active, this means the
9711                  * crtc is now deactivated. Break the links. connector
9712                  * -> encoder links are only establish when things are
9713                  *  actually up, hence no need to break them. */
9714                 WARN_ON(crtc->active);
9715
9716                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9717                         WARN_ON(encoder->connectors_active);
9718                         encoder->base.crtc = NULL;
9719                 }
9720         }
9721 }
9722
9723 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9724 {
9725         struct intel_connector *connector;
9726         struct drm_device *dev = encoder->base.dev;
9727
9728         /* We need to check both for a crtc link (meaning that the
9729          * encoder is active and trying to read from a pipe) and the
9730          * pipe itself being active. */
9731         bool has_active_crtc = encoder->base.crtc &&
9732                 to_intel_crtc(encoder->base.crtc)->active;
9733
9734         if (encoder->connectors_active && !has_active_crtc) {
9735                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9736                               encoder->base.base.id,
9737                               drm_get_encoder_name(&encoder->base));
9738
9739                 /* Connector is active, but has no active pipe. This is
9740                  * fallout from our resume register restoring. Disable
9741                  * the encoder manually again. */
9742                 if (encoder->base.crtc) {
9743                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9744                                       encoder->base.base.id,
9745                                       drm_get_encoder_name(&encoder->base));
9746                         encoder->disable(encoder);
9747                 }
9748
9749                 /* Inconsistent output/port/pipe state happens presumably due to
9750                  * a bug in one of the get_hw_state functions. Or someplace else
9751                  * in our code, like the register restore mess on resume. Clamp
9752                  * things to off as a safer default. */
9753                 list_for_each_entry(connector,
9754                                     &dev->mode_config.connector_list,
9755                                     base.head) {
9756                         if (connector->encoder != encoder)
9757                                 continue;
9758
9759                         intel_connector_break_all_links(connector);
9760                 }
9761         }
9762         /* Enabled encoders without active connectors will be fixed in
9763          * the crtc fixup. */
9764 }
9765
9766 void i915_redisable_vga(struct drm_device *dev)
9767 {
9768         struct drm_i915_private *dev_priv = dev->dev_private;
9769         u32 vga_reg = i915_vgacntrl_reg(dev);
9770
9771         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9772                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9773                 i915_disable_vga(dev);
9774         }
9775 }
9776
9777 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9778 {
9779         struct drm_i915_private *dev_priv = dev->dev_private;
9780         enum pipe pipe;
9781         struct intel_crtc *crtc;
9782         struct intel_encoder *encoder;
9783         struct intel_connector *connector;
9784         int i;
9785
9786         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9787                             base.head) {
9788                 memset(&crtc->config, 0, sizeof(crtc->config));
9789
9790                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9791                                                                  &crtc->config);
9792
9793                 crtc->base.enabled = crtc->active;
9794
9795                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9796                               crtc->base.base.id,
9797                               crtc->active ? "enabled" : "disabled");
9798         }
9799
9800         /* FIXME: Smash this into the new shared dpll infrastructure. */
9801         if (HAS_DDI(dev))
9802                 intel_ddi_setup_hw_pll_state(dev);
9803
9804         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9805                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9806
9807                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9808                 pll->active = 0;
9809                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9810                                     base.head) {
9811                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9812                                 pll->active++;
9813                 }
9814                 pll->refcount = pll->active;
9815
9816                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9817                               pll->name, pll->refcount);
9818         }
9819
9820         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9821                             base.head) {
9822                 pipe = 0;
9823
9824                 if (encoder->get_hw_state(encoder, &pipe)) {
9825                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9826                         encoder->base.crtc = &crtc->base;
9827                         if (encoder->get_config)
9828                                 encoder->get_config(encoder, &crtc->config);
9829                 } else {
9830                         encoder->base.crtc = NULL;
9831                 }
9832
9833                 encoder->connectors_active = false;
9834                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9835                               encoder->base.base.id,
9836                               drm_get_encoder_name(&encoder->base),
9837                               encoder->base.crtc ? "enabled" : "disabled",
9838                               pipe);
9839         }
9840
9841         list_for_each_entry(connector, &dev->mode_config.connector_list,
9842                             base.head) {
9843                 if (connector->get_hw_state(connector)) {
9844                         connector->base.dpms = DRM_MODE_DPMS_ON;
9845                         connector->encoder->connectors_active = true;
9846                         connector->base.encoder = &connector->encoder->base;
9847                 } else {
9848                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9849                         connector->base.encoder = NULL;
9850                 }
9851                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9852                               connector->base.base.id,
9853                               drm_get_connector_name(&connector->base),
9854                               connector->base.encoder ? "enabled" : "disabled");
9855         }
9856 }
9857
9858 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9859  * and i915 state tracking structures. */
9860 void intel_modeset_setup_hw_state(struct drm_device *dev,
9861                                   bool force_restore)
9862 {
9863         struct drm_i915_private *dev_priv = dev->dev_private;
9864         enum pipe pipe;
9865         struct drm_plane *plane;
9866         struct intel_crtc *crtc;
9867         struct intel_encoder *encoder;
9868
9869         intel_modeset_readout_hw_state(dev);
9870
9871         /* HW state is read out, now we need to sanitize this mess. */
9872         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9873                             base.head) {
9874                 intel_sanitize_encoder(encoder);
9875         }
9876
9877         for_each_pipe(pipe) {
9878                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9879                 intel_sanitize_crtc(crtc);
9880                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9881         }
9882
9883         if (force_restore) {
9884                 /*
9885                  * We need to use raw interfaces for restoring state to avoid
9886                  * checking (bogus) intermediate states.
9887                  */
9888                 for_each_pipe(pipe) {
9889                         struct drm_crtc *crtc =
9890                                 dev_priv->pipe_to_crtc_mapping[pipe];
9891
9892                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9893                                          crtc->fb);
9894                 }
9895                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9896                         intel_plane_restore(plane);
9897
9898                 i915_redisable_vga(dev);
9899         } else {
9900                 intel_modeset_update_staged_output_state(dev);
9901         }
9902
9903         intel_modeset_check_state(dev);
9904
9905         drm_mode_config_reset(dev);
9906 }
9907
9908 void intel_modeset_gem_init(struct drm_device *dev)
9909 {
9910         intel_modeset_init_hw(dev);
9911
9912         intel_setup_overlay(dev);
9913
9914         intel_modeset_setup_hw_state(dev, false);
9915 }
9916
9917 void intel_modeset_cleanup(struct drm_device *dev)
9918 {
9919         struct drm_i915_private *dev_priv = dev->dev_private;
9920         struct drm_crtc *crtc;
9921         struct intel_crtc *intel_crtc;
9922
9923         /*
9924          * Interrupts and polling as the first thing to avoid creating havoc.
9925          * Too much stuff here (turning of rps, connectors, ...) would
9926          * experience fancy races otherwise.
9927          */
9928         drm_irq_uninstall(dev);
9929         cancel_work_sync(&dev_priv->hotplug_work);
9930         /*
9931          * Due to the hpd irq storm handling the hotplug work can re-arm the
9932          * poll handlers. Hence disable polling after hpd handling is shut down.
9933          */
9934         drm_kms_helper_poll_fini(dev);
9935
9936         mutex_lock(&dev->struct_mutex);
9937
9938         intel_unregister_dsm_handler();
9939
9940         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9941                 /* Skip inactive CRTCs */
9942                 if (!crtc->fb)
9943                         continue;
9944
9945                 intel_crtc = to_intel_crtc(crtc);
9946                 intel_increase_pllclock(crtc);
9947         }
9948
9949         intel_disable_fbc(dev);
9950
9951         intel_disable_gt_powersave(dev);
9952
9953         ironlake_teardown_rc6(dev);
9954
9955         mutex_unlock(&dev->struct_mutex);
9956
9957         /* flush any delayed tasks or pending work */
9958         flush_scheduled_work();
9959
9960         /* destroy backlight, if any, before the connectors */
9961         intel_panel_destroy_backlight(dev);
9962
9963         drm_mode_config_cleanup(dev);
9964
9965         intel_cleanup_overlay(dev);
9966 }
9967
9968 /*
9969  * Return which encoder is currently attached for connector.
9970  */
9971 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9972 {
9973         return &intel_attached_encoder(connector)->base;
9974 }
9975
9976 void intel_connector_attach_encoder(struct intel_connector *connector,
9977                                     struct intel_encoder *encoder)
9978 {
9979         connector->encoder = encoder;
9980         drm_mode_connector_attach_encoder(&connector->base,
9981                                           &encoder->base);
9982 }
9983
9984 /*
9985  * set vga decode state - true == enable VGA decode
9986  */
9987 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9988 {
9989         struct drm_i915_private *dev_priv = dev->dev_private;
9990         u16 gmch_ctrl;
9991
9992         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9993         if (state)
9994                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9995         else
9996                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9997         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9998         return 0;
9999 }
10000
10001 #ifdef CONFIG_DEBUG_FS
10002 #include <linux/seq_file.h>
10003
10004 struct intel_display_error_state {
10005
10006         u32 power_well_driver;
10007
10008         struct intel_cursor_error_state {
10009                 u32 control;
10010                 u32 position;
10011                 u32 base;
10012                 u32 size;
10013         } cursor[I915_MAX_PIPES];
10014
10015         struct intel_pipe_error_state {
10016                 enum transcoder cpu_transcoder;
10017                 u32 conf;
10018                 u32 source;
10019
10020                 u32 htotal;
10021                 u32 hblank;
10022                 u32 hsync;
10023                 u32 vtotal;
10024                 u32 vblank;
10025                 u32 vsync;
10026         } pipe[I915_MAX_PIPES];
10027
10028         struct intel_plane_error_state {
10029                 u32 control;
10030                 u32 stride;
10031                 u32 size;
10032                 u32 pos;
10033                 u32 addr;
10034                 u32 surface;
10035                 u32 tile_offset;
10036         } plane[I915_MAX_PIPES];
10037 };
10038
10039 struct intel_display_error_state *
10040 intel_display_capture_error_state(struct drm_device *dev)
10041 {
10042         drm_i915_private_t *dev_priv = dev->dev_private;
10043         struct intel_display_error_state *error;
10044         enum transcoder cpu_transcoder;
10045         int i;
10046
10047         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10048         if (error == NULL)
10049                 return NULL;
10050
10051         if (HAS_POWER_WELL(dev))
10052                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10053
10054         for_each_pipe(i) {
10055                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10056                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10057
10058                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10059                         error->cursor[i].control = I915_READ(CURCNTR(i));
10060                         error->cursor[i].position = I915_READ(CURPOS(i));
10061                         error->cursor[i].base = I915_READ(CURBASE(i));
10062                 } else {
10063                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10064                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10065                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10066                 }
10067
10068                 error->plane[i].control = I915_READ(DSPCNTR(i));
10069                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10070                 if (INTEL_INFO(dev)->gen <= 3) {
10071                         error->plane[i].size = I915_READ(DSPSIZE(i));
10072                         error->plane[i].pos = I915_READ(DSPPOS(i));
10073                 }
10074                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10075                         error->plane[i].addr = I915_READ(DSPADDR(i));
10076                 if (INTEL_INFO(dev)->gen >= 4) {
10077                         error->plane[i].surface = I915_READ(DSPSURF(i));
10078                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10079                 }
10080
10081                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10082                 error->pipe[i].source = I915_READ(PIPESRC(i));
10083                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10084                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10085                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10086                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10087                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10088                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10089         }
10090
10091         /* In the code above we read the registers without checking if the power
10092          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10093          * prevent the next I915_WRITE from detecting it and printing an error
10094          * message. */
10095         if (HAS_POWER_WELL(dev))
10096                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10097
10098         return error;
10099 }
10100
10101 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10102
10103 void
10104 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10105                                 struct drm_device *dev,
10106                                 struct intel_display_error_state *error)
10107 {
10108         int i;
10109
10110         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10111         if (HAS_POWER_WELL(dev))
10112                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10113                            error->power_well_driver);
10114         for_each_pipe(i) {
10115                 err_printf(m, "Pipe [%d]:\n", i);
10116                 err_printf(m, "  CPU transcoder: %c\n",
10117                            transcoder_name(error->pipe[i].cpu_transcoder));
10118                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10119                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10120                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10121                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10122                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10123                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10124                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10125                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10126
10127                 err_printf(m, "Plane [%d]:\n", i);
10128                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10129                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10130                 if (INTEL_INFO(dev)->gen <= 3) {
10131                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10132                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10133                 }
10134                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10135                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10136                 if (INTEL_INFO(dev)->gen >= 4) {
10137                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10138                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10139                 }
10140
10141                 err_printf(m, "Cursor [%d]:\n", i);
10142                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10143                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10144                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10145         }
10146 }
10147 #endif