Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 void assert_pll(struct drm_i915_private *dev_priv,
 896                 enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909
 910 struct intel_shared_dpll *
 911 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 912 {
 913         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 914
 915         if (crtc->config.shared_dpll < 0)
 916                 return NULL;
 917
 918         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 919 }
 920
 921 /* For ILK+ */
 922 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 923                         struct intel_shared_dpll *pll,
 924                         bool state)
 925 {
 926         bool cur_state;
 927         struct intel_dpll_hw_state hw_state;
 928
 929         if (HAS_PCH_LPT(dev_priv->dev)) {
 930                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 931                 return;
 932         }
 933
 934         if (WARN (!pll,
 935                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 936                 return;
 937
 938         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 939         WARN(cur_state != state,
 940              "%s assertion failure (expected %s, current %s)\n",
 941              pll->name, state_string(state), state_string(cur_state));
 942 }
 943
 944 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 945                           enum pipe pipe, bool state)
 946 {
 947         int reg;
 948         u32 val;
 949         bool cur_state;
 950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 951                                                                       pipe);
 952
 953         if (HAS_DDI(dev_priv->dev)) {
 954                 /* DDI does not have a specific FDI_TX register */
 955                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 956                 val = I915_READ(reg);
 957                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 958         } else {
 959                 reg = FDI_TX_CTL(pipe);
 960                 val = I915_READ(reg);
 961                 cur_state = !!(val & FDI_TX_ENABLE);
 962         }
 963         WARN(cur_state != state,
 964              "FDI TX state assertion failure (expected %s, current %s)\n",
 965              state_string(state), state_string(cur_state));
 966 }
 967 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 968 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 969
 970 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 971                           enum pipe pipe, bool state)
 972 {
 973         int reg;
 974         u32 val;
 975         bool cur_state;
 976
 977         reg = FDI_RX_CTL(pipe);
 978         val = I915_READ(reg);
 979         cur_state = !!(val & FDI_RX_ENABLE);
 980         WARN(cur_state != state,
 981              "FDI RX state assertion failure (expected %s, current %s)\n",
 982              state_string(state), state_string(cur_state));
 983 }
 984 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 985 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 986
 987 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 988                                       enum pipe pipe)
 989 {
 990         int reg;
 991         u32 val;
 992
 993         /* ILK FDI PLL is always enabled */
 994         if (dev_priv->info->gen == 5)
 995                 return;
 996
 997         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
 998         if (HAS_DDI(dev_priv->dev))
 999                 return;
1000
1001         reg = FDI_TX_CTL(pipe);
1002         val = I915_READ(reg);
1003         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1004 }
1005
1006 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1007                        enum pipe pipe, bool state)
1008 {
1009         int reg;
1010         u32 val;
1011         bool cur_state;
1012
1013         reg = FDI_RX_CTL(pipe);
1014         val = I915_READ(reg);
1015         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1016         WARN(cur_state != state,
1017              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1018              state_string(state), state_string(cur_state));
1019 }
1020
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022                                   enum pipe pipe)
1023 {
1024         int pp_reg, lvds_reg;
1025         u32 val;
1026         enum pipe panel_pipe = PIPE_A;
1027         bool locked = true;
1028
1029         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030                 pp_reg = PCH_PP_CONTROL;
1031                 lvds_reg = PCH_LVDS;
1032         } else {
1033                 pp_reg = PP_CONTROL;
1034                 lvds_reg = LVDS;
1035         }
1036
1037         val = I915_READ(pp_reg);
1038         if (!(val & PANEL_POWER_ON) ||
1039             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040                 locked = false;
1041
1042         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043                 panel_pipe = PIPE_B;
1044
1045         WARN(panel_pipe == pipe && locked,
1046              "panel assertion failure, pipe %c regs locked\n",
1047              pipe_name(pipe));
1048 }
1049
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051                  enum pipe pipe, bool state)
1052 {
1053         int reg;
1054         u32 val;
1055         bool cur_state;
1056         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057                                                                       pipe);
1058
1059         /* if we need the pipe A quirk it must be always on */
1060         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061                 state = true;
1062
1063         if (!intel_display_power_enabled(dev_priv->dev,
1064                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1065                 cur_state = false;
1066         } else {
1067                 reg = PIPECONF(cpu_transcoder);
1068                 val = I915_READ(reg);
1069                 cur_state = !!(val & PIPECONF_ENABLE);
1070         }
1071
1072         WARN(cur_state != state,
1073              "pipe %c assertion failure (expected %s, current %s)\n",
1074              pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078                          enum plane plane, bool state)
1079 {
1080         int reg;
1081         u32 val;
1082         bool cur_state;
1083
1084         reg = DSPCNTR(plane);
1085         val = I915_READ(reg);
1086         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087         WARN(cur_state != state,
1088              "plane %c assertion failure (expected %s, current %s)\n",
1089              plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096                                    enum pipe pipe)
1097 {
1098         struct drm_device *dev = dev_priv->dev;
1099         int reg, i;
1100         u32 val;
1101         int cur_pipe;
1102
1103         /* Primary planes are fixed to pipes on gen4+ */
1104         if (INTEL_INFO(dev)->gen >= 4) {
1105                 reg = DSPCNTR(pipe);
1106                 val = I915_READ(reg);
1107                 WARN((val & DISPLAY_PLANE_ENABLE),
1108                      "plane %c assertion failure, should be disabled but not\n",
1109                      plane_name(pipe));
1110                 return;
1111         }
1112
1113         /* Need to check both planes against the pipe */
1114         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1115                 reg = DSPCNTR(i);
1116                 val = I915_READ(reg);
1117                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118                         DISPPLANE_SEL_PIPE_SHIFT;
1119                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121                      plane_name(i), pipe_name(pipe));
1122         }
1123 }
1124
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126                                     enum pipe pipe)
1127 {
1128         struct drm_device *dev = dev_priv->dev;
1129         int reg, i;
1130         u32 val;
1131
1132         if (IS_VALLEYVIEW(dev)) {
1133                 for (i = 0; i < dev_priv->num_plane; i++) {
1134                         reg = SPCNTR(pipe, i);
1135                         val = I915_READ(reg);
1136                         WARN((val & SP_ENABLE),
1137                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138                              sprite_name(pipe, i), pipe_name(pipe));
1139                 }
1140         } else if (INTEL_INFO(dev)->gen >= 7) {
1141                 reg = SPRCTL(pipe);
1142                 val = I915_READ(reg);
1143                 WARN((val & SPRITE_ENABLE),
1144                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145                      plane_name(pipe), pipe_name(pipe));
1146         } else if (INTEL_INFO(dev)->gen >= 5) {
1147                 reg = DVSCNTR(pipe);
1148                 val = I915_READ(reg);
1149                 WARN((val & DVS_ENABLE),
1150                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151                      plane_name(pipe), pipe_name(pipe));
1152         }
1153 }
1154
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156 {
1157         u32 val;
1158         bool enabled;
1159
1160         if (HAS_PCH_LPT(dev_priv->dev)) {
1161                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162                 return;
1163         }
1164
1165         val = I915_READ(PCH_DREF_CONTROL);
1166         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167                             DREF_SUPERSPREAD_SOURCE_MASK));
1168         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172                                            enum pipe pipe)
1173 {
1174         int reg;
1175         u32 val;
1176         bool enabled;
1177
1178         reg = PCH_TRANSCONF(pipe);
1179         val = I915_READ(reg);
1180         enabled = !!(val & TRANS_ENABLE);
1181         WARN(enabled,
1182              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183              pipe_name(pipe));
1184 }
1185
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187                             enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189         if ((val & DP_PORT_EN) == 0)
1190                 return false;
1191
1192         if (HAS_PCH_CPT(dev_priv->dev)) {
1193                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196                         return false;
1197         } else {
1198                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199                         return false;
1200         }
1201         return true;
1202 }
1203
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205                               enum pipe pipe, u32 val)
1206 {
1207         if ((val & SDVO_ENABLE) == 0)
1208                 return false;
1209
1210         if (HAS_PCH_CPT(dev_priv->dev)) {
1211                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212                         return false;
1213         } else {
1214                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215                         return false;
1216         }
1217         return true;
1218 }
1219
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221                               enum pipe pipe, u32 val)
1222 {
1223         if ((val & LVDS_PORT_EN) == 0)
1224                 return false;
1225
1226         if (HAS_PCH_CPT(dev_priv->dev)) {
1227                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228                         return false;
1229         } else {
1230                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231                         return false;
1232         }
1233         return true;
1234 }
1235
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237                               enum pipe pipe, u32 val)
1238 {
1239         if ((val & ADPA_DAC_ENABLE) == 0)
1240                 return false;
1241         if (HAS_PCH_CPT(dev_priv->dev)) {
1242                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243                         return false;
1244         } else {
1245                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246                         return false;
1247         }
1248         return true;
1249 }
1250
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252                                    enum pipe pipe, int reg, u32 port_sel)
1253 {
1254         u32 val = I915_READ(reg);
1255         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257              reg, pipe_name(pipe));
1258
1259         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260              && (val & DP_PIPEB_SELECT),
1261              "IBX PCH dp port still using transcoder B\n");
1262 }
1263
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265                                      enum pipe pipe, int reg)
1266 {
1267         u32 val = I915_READ(reg);
1268         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270              reg, pipe_name(pipe));
1271
1272         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273              && (val & SDVO_PIPE_B_SELECT),
1274              "IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278                                       enum pipe pipe)
1279 {
1280         int reg;
1281         u32 val;
1282
1283         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287         reg = PCH_ADPA;
1288         val = I915_READ(reg);
1289         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290              "PCH VGA enabled on transcoder %c, should be disabled\n",
1291              pipe_name(pipe));
1292
1293         reg = PCH_LVDS;
1294         val = I915_READ(reg);
1295         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1297              pipe_name(pipe));
1298
1299         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1305 {
1306         int reg;
1307         u32 val;
1308
1309         assert_pipe_disabled(dev_priv, pipe);
1310
1311         /* No really, not for ILK+ */
1312         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1313
1314         /* PLL is protected by panel, make sure we can write it */
1315         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1316                 assert_panel_unlocked(dev_priv, pipe);
1317
1318         reg = DPLL(pipe);
1319         val = I915_READ(reg);
1320         val |= DPLL_VCO_ENABLE;
1321
1322         /* We do this three times for luck */
1323         I915_WRITE(reg, val);
1324         POSTING_READ(reg);
1325         udelay(150); /* wait for warmup */
1326         I915_WRITE(reg, val);
1327         POSTING_READ(reg);
1328         udelay(150); /* wait for warmup */
1329         I915_WRITE(reg, val);
1330         POSTING_READ(reg);
1331         udelay(150); /* wait for warmup */
1332 }
1333
1334 static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1335 {
1336         int reg;
1337         u32 val;
1338
1339         assert_pipe_disabled(dev_priv, pipe);
1340
1341         /* No really, not for ILK+ */
1342         BUG_ON(dev_priv->info->gen >= 5);
1343
1344         /* PLL is protected by panel, make sure we can write it */
1345         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1346                 assert_panel_unlocked(dev_priv, pipe);
1347
1348         reg = DPLL(pipe);
1349         val = I915_READ(reg);
1350         val |= DPLL_VCO_ENABLE;
1351
1352         /* We do this three times for luck */
1353         I915_WRITE(reg, val);
1354         POSTING_READ(reg);
1355         udelay(150); /* wait for warmup */
1356         I915_WRITE(reg, val);
1357         POSTING_READ(reg);
1358         udelay(150); /* wait for warmup */
1359         I915_WRITE(reg, val);
1360         POSTING_READ(reg);
1361         udelay(150); /* wait for warmup */
1362 }
1363
1364 /**
1365  * intel_disable_pll - disable a PLL
1366  * @dev_priv: i915 private structure
1367  * @pipe: pipe PLL to disable
1368  *
1369  * Disable the PLL for @pipe, making sure the pipe is off first.
1370  *
1371  * Note!  This is for pre-ILK only.
1372  */
1373 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1374 {
1375         int reg;
1376         u32 val;
1377
1378         /* Don't disable pipe A or pipe A PLLs if needed */
1379         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1380                 return;
1381
1382         /* Make sure the pipe isn't still relying on us */
1383         assert_pipe_disabled(dev_priv, pipe);
1384
1385         reg = DPLL(pipe);
1386         val = I915_READ(reg);
1387         val &= ~DPLL_VCO_ENABLE;
1388         I915_WRITE(reg, val);
1389         POSTING_READ(reg);
1390 }
1391
1392 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1393 {
1394         u32 port_mask;
1395
1396         if (!port)
1397                 port_mask = DPLL_PORTB_READY_MASK;
1398         else
1399                 port_mask = DPLL_PORTC_READY_MASK;
1400
1401         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1402                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1403                      'B' + port, I915_READ(DPLL(0)));
1404 }
1405
1406 /**
1407  * ironlake_enable_shared_dpll - enable PCH PLL
1408  * @dev_priv: i915 private structure
1409  * @pipe: pipe PLL to enable
1410  *
1411  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1412  * drives the transcoder clock.
1413  */
1414 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1415 {
1416         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1417         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1418
1419         /* PCH PLLs only available on ILK, SNB and IVB */
1420         BUG_ON(dev_priv->info->gen < 5);
1421         if (WARN_ON(pll == NULL))
1422                 return;
1423
1424         if (WARN_ON(pll->refcount == 0))
1425                 return;
1426
1427         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1428                       pll->name, pll->active, pll->on,
1429                       crtc->base.base.id);
1430
1431         if (pll->active++) {
1432                 WARN_ON(!pll->on);
1433                 assert_shared_dpll_enabled(dev_priv, pll);
1434                 return;
1435         }
1436         WARN_ON(pll->on);
1437
1438         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1439         pll->enable(dev_priv, pll);
1440         pll->on = true;
1441 }
1442
1443 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1444 {
1445         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1446         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1447
1448         /* PCH only available on ILK+ */
1449         BUG_ON(dev_priv->info->gen < 5);
1450         if (WARN_ON(pll == NULL))
1451                return;
1452
1453         if (WARN_ON(pll->refcount == 0))
1454                 return;
1455
1456         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1457                       pll->name, pll->active, pll->on,
1458                       crtc->base.base.id);
1459
1460         if (WARN_ON(pll->active == 0)) {
1461                 assert_shared_dpll_disabled(dev_priv, pll);
1462                 return;
1463         }
1464
1465         assert_shared_dpll_enabled(dev_priv, pll);
1466         WARN_ON(!pll->on);
1467         if (--pll->active)
1468                 return;
1469
1470         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1471         pll->disable(dev_priv, pll);
1472         pll->on = false;
1473 }
1474
1475 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1476                                            enum pipe pipe)
1477 {
1478         struct drm_device *dev = dev_priv->dev;
1479         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1481         uint32_t reg, val, pipeconf_val;
1482
1483         /* PCH only available on ILK+ */
1484         BUG_ON(dev_priv->info->gen < 5);
1485
1486         /* Make sure PCH DPLL is enabled */
1487         assert_shared_dpll_enabled(dev_priv,
1488                                    intel_crtc_to_shared_dpll(intel_crtc));
1489
1490         /* FDI must be feeding us bits for PCH ports */
1491         assert_fdi_tx_enabled(dev_priv, pipe);
1492         assert_fdi_rx_enabled(dev_priv, pipe);
1493
1494         if (HAS_PCH_CPT(dev)) {
1495                 /* Workaround: Set the timing override bit before enabling the
1496                  * pch transcoder. */
1497                 reg = TRANS_CHICKEN2(pipe);
1498                 val = I915_READ(reg);
1499                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1500                 I915_WRITE(reg, val);
1501         }
1502
1503         reg = PCH_TRANSCONF(pipe);
1504         val = I915_READ(reg);
1505         pipeconf_val = I915_READ(PIPECONF(pipe));
1506
1507         if (HAS_PCH_IBX(dev_priv->dev)) {
1508                 /*
1509                  * make the BPC in transcoder be consistent with
1510                  * that in pipeconf reg.
1511                  */
1512                 val &= ~PIPECONF_BPC_MASK;
1513                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1514         }
1515
1516         val &= ~TRANS_INTERLACE_MASK;
1517         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1518                 if (HAS_PCH_IBX(dev_priv->dev) &&
1519                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1520                         val |= TRANS_LEGACY_INTERLACED_ILK;
1521                 else
1522                         val |= TRANS_INTERLACED;
1523         else
1524                 val |= TRANS_PROGRESSIVE;
1525
1526         I915_WRITE(reg, val | TRANS_ENABLE);
1527         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1528                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1529 }
1530
1531 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1532                                       enum transcoder cpu_transcoder)
1533 {
1534         u32 val, pipeconf_val;
1535
1536         /* PCH only available on ILK+ */
1537         BUG_ON(dev_priv->info->gen < 5);
1538
1539         /* FDI must be feeding us bits for PCH ports */
1540         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1541         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1542
1543         /* Workaround: set timing override bit. */
1544         val = I915_READ(_TRANSA_CHICKEN2);
1545         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1546         I915_WRITE(_TRANSA_CHICKEN2, val);
1547
1548         val = TRANS_ENABLE;
1549         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1550
1551         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1552             PIPECONF_INTERLACED_ILK)
1553                 val |= TRANS_INTERLACED;
1554         else
1555                 val |= TRANS_PROGRESSIVE;
1556
1557         I915_WRITE(LPT_TRANSCONF, val);
1558         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1559                 DRM_ERROR("Failed to enable PCH transcoder\n");
1560 }
1561
1562 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1563                                             enum pipe pipe)
1564 {
1565         struct drm_device *dev = dev_priv->dev;
1566         uint32_t reg, val;
1567
1568         /* FDI relies on the transcoder */
1569         assert_fdi_tx_disabled(dev_priv, pipe);
1570         assert_fdi_rx_disabled(dev_priv, pipe);
1571
1572         /* Ports must be off as well */
1573         assert_pch_ports_disabled(dev_priv, pipe);
1574
1575         reg = PCH_TRANSCONF(pipe);
1576         val = I915_READ(reg);
1577         val &= ~TRANS_ENABLE;
1578         I915_WRITE(reg, val);
1579         /* wait for PCH transcoder off, transcoder state */
1580         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1581                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1582
1583         if (!HAS_PCH_IBX(dev)) {
1584                 /* Workaround: Clear the timing override chicken bit again. */
1585                 reg = TRANS_CHICKEN2(pipe);
1586                 val = I915_READ(reg);
1587                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1588                 I915_WRITE(reg, val);
1589         }
1590 }
1591
1592 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1593 {
1594         u32 val;
1595
1596         val = I915_READ(LPT_TRANSCONF);
1597         val &= ~TRANS_ENABLE;
1598         I915_WRITE(LPT_TRANSCONF, val);
1599         /* wait for PCH transcoder off, transcoder state */
1600         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1601                 DRM_ERROR("Failed to disable PCH transcoder\n");
1602
1603         /* Workaround: clear timing override bit. */
1604         val = I915_READ(_TRANSA_CHICKEN2);
1605         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1606         I915_WRITE(_TRANSA_CHICKEN2, val);
1607 }
1608
1609 /**
1610  * intel_enable_pipe - enable a pipe, asserting requirements
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe to enable
1613  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1614  *
1615  * Enable @pipe, making sure that various hardware specific requirements
1616  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1617  *
1618  * @pipe should be %PIPE_A or %PIPE_B.
1619  *
1620  * Will wait until the pipe is actually running (i.e. first vblank) before
1621  * returning.
1622  */
1623 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1624                               bool pch_port)
1625 {
1626         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1627                                                                       pipe);
1628         enum pipe pch_transcoder;
1629         int reg;
1630         u32 val;
1631
1632         assert_planes_disabled(dev_priv, pipe);
1633         assert_sprites_disabled(dev_priv, pipe);
1634
1635         if (HAS_PCH_LPT(dev_priv->dev))
1636                 pch_transcoder = TRANSCODER_A;
1637         else
1638                 pch_transcoder = pipe;
1639
1640         /*
1641          * A pipe without a PLL won't actually be able to drive bits from
1642          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1643          * need the check.
1644          */
1645         if (!HAS_PCH_SPLIT(dev_priv->dev))
1646                 assert_pll_enabled(dev_priv, pipe);
1647         else {
1648                 if (pch_port) {
1649                         /* if driving the PCH, we need FDI enabled */
1650                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1651                         assert_fdi_tx_pll_enabled(dev_priv,
1652                                                   (enum pipe) cpu_transcoder);
1653                 }
1654                 /* FIXME: assert CPU port conditions for SNB+ */
1655         }
1656
1657         reg = PIPECONF(cpu_transcoder);
1658         val = I915_READ(reg);
1659         if (val & PIPECONF_ENABLE)
1660                 return;
1661
1662         I915_WRITE(reg, val | PIPECONF_ENABLE);
1663         intel_wait_for_vblank(dev_priv->dev, pipe);
1664 }
1665
1666 /**
1667  * intel_disable_pipe - disable a pipe, asserting requirements
1668  * @dev_priv: i915 private structure
1669  * @pipe: pipe to disable
1670  *
1671  * Disable @pipe, making sure that various hardware specific requirements
1672  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1673  *
1674  * @pipe should be %PIPE_A or %PIPE_B.
1675  *
1676  * Will wait until the pipe has shut down before returning.
1677  */
1678 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1679                                enum pipe pipe)
1680 {
1681         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1682                                                                       pipe);
1683         int reg;
1684         u32 val;
1685
1686         /*
1687          * Make sure planes won't keep trying to pump pixels to us,
1688          * or we might hang the display.
1689          */
1690         assert_planes_disabled(dev_priv, pipe);
1691         assert_sprites_disabled(dev_priv, pipe);
1692
1693         /* Don't disable pipe A or pipe A PLLs if needed */
1694         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1695                 return;
1696
1697         reg = PIPECONF(cpu_transcoder);
1698         val = I915_READ(reg);
1699         if ((val & PIPECONF_ENABLE) == 0)
1700                 return;
1701
1702         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1703         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1704 }
1705
1706 /*
1707  * Plane regs are double buffered, going from enabled->disabled needs a
1708  * trigger in order to latch.  The display address reg provides this.
1709  */
1710 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1711                                       enum plane plane)
1712 {
1713         if (dev_priv->info->gen >= 4)
1714                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1715         else
1716                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1717 }
1718
1719 /**
1720  * intel_enable_plane - enable a display plane on a given pipe
1721  * @dev_priv: i915 private structure
1722  * @plane: plane to enable
1723  * @pipe: pipe being fed
1724  *
1725  * Enable @plane on @pipe, making sure that @pipe is running first.
1726  */
1727 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1728                                enum plane plane, enum pipe pipe)
1729 {
1730         int reg;
1731         u32 val;
1732
1733         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1734         assert_pipe_enabled(dev_priv, pipe);
1735
1736         reg = DSPCNTR(plane);
1737         val = I915_READ(reg);
1738         if (val & DISPLAY_PLANE_ENABLE)
1739                 return;
1740
1741         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1742         intel_flush_display_plane(dev_priv, plane);
1743         intel_wait_for_vblank(dev_priv->dev, pipe);
1744 }
1745
1746 /**
1747  * intel_disable_plane - disable a display plane
1748  * @dev_priv: i915 private structure
1749  * @plane: plane to disable
1750  * @pipe: pipe consuming the data
1751  *
1752  * Disable @plane; should be an independent operation.
1753  */
1754 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1755                                 enum plane plane, enum pipe pipe)
1756 {
1757         int reg;
1758         u32 val;
1759
1760         reg = DSPCNTR(plane);
1761         val = I915_READ(reg);
1762         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1763                 return;
1764
1765         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1766         intel_flush_display_plane(dev_priv, plane);
1767         intel_wait_for_vblank(dev_priv->dev, pipe);
1768 }
1769
1770 static bool need_vtd_wa(struct drm_device *dev)
1771 {
1772 #ifdef CONFIG_INTEL_IOMMU
1773         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1774                 return true;
1775 #endif
1776         return false;
1777 }
1778
1779 int
1780 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1781                            struct drm_i915_gem_object *obj,
1782                            struct intel_ring_buffer *pipelined)
1783 {
1784         struct drm_i915_private *dev_priv = dev->dev_private;
1785         u32 alignment;
1786         int ret;
1787
1788         switch (obj->tiling_mode) {
1789         case I915_TILING_NONE:
1790                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1791                         alignment = 128 * 1024;
1792                 else if (INTEL_INFO(dev)->gen >= 4)
1793                         alignment = 4 * 1024;
1794                 else
1795                         alignment = 64 * 1024;
1796                 break;
1797         case I915_TILING_X:
1798                 /* pin() will align the object as required by fence */
1799                 alignment = 0;
1800                 break;
1801         case I915_TILING_Y:
1802                 /* Despite that we check this in framebuffer_init userspace can
1803                  * screw us over and change the tiling after the fact. Only
1804                  * pinned buffers can't change their tiling. */
1805                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1806                 return -EINVAL;
1807         default:
1808                 BUG();
1809         }
1810
1811         /* Note that the w/a also requires 64 PTE of padding following the
1812          * bo. We currently fill all unused PTE with the shadow page and so
1813          * we should always have valid PTE following the scanout preventing
1814          * the VT-d warning.
1815          */
1816         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1817                 alignment = 256 * 1024;
1818
1819         dev_priv->mm.interruptible = false;
1820         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1821         if (ret)
1822                 goto err_interruptible;
1823
1824         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1825          * fence, whereas 965+ only requires a fence if using
1826          * framebuffer compression.  For simplicity, we always install
1827          * a fence as the cost is not that onerous.
1828          */
1829         ret = i915_gem_object_get_fence(obj);
1830         if (ret)
1831                 goto err_unpin;
1832
1833         i915_gem_object_pin_fence(obj);
1834
1835         dev_priv->mm.interruptible = true;
1836         return 0;
1837
1838 err_unpin:
1839         i915_gem_object_unpin(obj);
1840 err_interruptible:
1841         dev_priv->mm.interruptible = true;
1842         return ret;
1843 }
1844
1845 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1846 {
1847         i915_gem_object_unpin_fence(obj);
1848         i915_gem_object_unpin(obj);
1849 }
1850
1851 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1852  * is assumed to be a power-of-two. */
1853 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1854                                              unsigned int tiling_mode,
1855                                              unsigned int cpp,
1856                                              unsigned int pitch)
1857 {
1858         if (tiling_mode != I915_TILING_NONE) {
1859                 unsigned int tile_rows, tiles;
1860
1861                 tile_rows = *y / 8;
1862                 *y %= 8;
1863
1864                 tiles = *x / (512/cpp);
1865                 *x %= 512/cpp;
1866
1867                 return tile_rows * pitch * 8 + tiles * 4096;
1868         } else {
1869                 unsigned int offset;
1870
1871                 offset = *y * pitch + *x * cpp;
1872                 *y = 0;
1873                 *x = (offset & 4095) / cpp;
1874                 return offset & -4096;
1875         }
1876 }
1877
1878 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1879                              int x, int y)
1880 {
1881         struct drm_device *dev = crtc->dev;
1882         struct drm_i915_private *dev_priv = dev->dev_private;
1883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1884         struct intel_framebuffer *intel_fb;
1885         struct drm_i915_gem_object *obj;
1886         int plane = intel_crtc->plane;
1887         unsigned long linear_offset;
1888         u32 dspcntr;
1889         u32 reg;
1890
1891         switch (plane) {
1892         case 0:
1893         case 1:
1894                 break;
1895         default:
1896                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1897                 return -EINVAL;
1898         }
1899
1900         intel_fb = to_intel_framebuffer(fb);
1901         obj = intel_fb->obj;
1902
1903         reg = DSPCNTR(plane);
1904         dspcntr = I915_READ(reg);
1905         /* Mask out pixel format bits in case we change it */
1906         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1907         switch (fb->pixel_format) {
1908         case DRM_FORMAT_C8:
1909                 dspcntr |= DISPPLANE_8BPP;
1910                 break;
1911         case DRM_FORMAT_XRGB1555:
1912         case DRM_FORMAT_ARGB1555:
1913                 dspcntr |= DISPPLANE_BGRX555;
1914                 break;
1915         case DRM_FORMAT_RGB565:
1916                 dspcntr |= DISPPLANE_BGRX565;
1917                 break;
1918         case DRM_FORMAT_XRGB8888:
1919         case DRM_FORMAT_ARGB8888:
1920                 dspcntr |= DISPPLANE_BGRX888;
1921                 break;
1922         case DRM_FORMAT_XBGR8888:
1923         case DRM_FORMAT_ABGR8888:
1924                 dspcntr |= DISPPLANE_RGBX888;
1925                 break;
1926         case DRM_FORMAT_XRGB2101010:
1927         case DRM_FORMAT_ARGB2101010:
1928                 dspcntr |= DISPPLANE_BGRX101010;
1929                 break;
1930         case DRM_FORMAT_XBGR2101010:
1931         case DRM_FORMAT_ABGR2101010:
1932                 dspcntr |= DISPPLANE_RGBX101010;
1933                 break;
1934         default:
1935                 BUG();
1936         }
1937
1938         if (INTEL_INFO(dev)->gen >= 4) {
1939                 if (obj->tiling_mode != I915_TILING_NONE)
1940                         dspcntr |= DISPPLANE_TILED;
1941                 else
1942                         dspcntr &= ~DISPPLANE_TILED;
1943         }
1944
1945         if (IS_G4X(dev))
1946                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1947
1948         I915_WRITE(reg, dspcntr);
1949
1950         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1951
1952         if (INTEL_INFO(dev)->gen >= 4) {
1953                 intel_crtc->dspaddr_offset =
1954                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1955                                                        fb->bits_per_pixel / 8,
1956                                                        fb->pitches[0]);
1957                 linear_offset -= intel_crtc->dspaddr_offset;
1958         } else {
1959                 intel_crtc->dspaddr_offset = linear_offset;
1960         }
1961
1962         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1963                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1964         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1965         if (INTEL_INFO(dev)->gen >= 4) {
1966                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1967                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1968                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1969                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1970         } else
1971                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1972         POSTING_READ(reg);
1973
1974         return 0;
1975 }
1976
1977 static int ironlake_update_plane(struct drm_crtc *crtc,
1978                                  struct drm_framebuffer *fb, int x, int y)
1979 {
1980         struct drm_device *dev = crtc->dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         struct intel_framebuffer *intel_fb;
1984         struct drm_i915_gem_object *obj;
1985         int plane = intel_crtc->plane;
1986         unsigned long linear_offset;
1987         u32 dspcntr;
1988         u32 reg;
1989
1990         switch (plane) {
1991         case 0:
1992         case 1:
1993         case 2:
1994                 break;
1995         default:
1996                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1997                 return -EINVAL;
1998         }
1999
2000         intel_fb = to_intel_framebuffer(fb);
2001         obj = intel_fb->obj;
2002
2003         reg = DSPCNTR(plane);
2004         dspcntr = I915_READ(reg);
2005         /* Mask out pixel format bits in case we change it */
2006         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2007         switch (fb->pixel_format) {
2008         case DRM_FORMAT_C8:
2009                 dspcntr |= DISPPLANE_8BPP;
2010                 break;
2011         case DRM_FORMAT_RGB565:
2012                 dspcntr |= DISPPLANE_BGRX565;
2013                 break;
2014         case DRM_FORMAT_XRGB8888:
2015         case DRM_FORMAT_ARGB8888:
2016                 dspcntr |= DISPPLANE_BGRX888;
2017                 break;
2018         case DRM_FORMAT_XBGR8888:
2019         case DRM_FORMAT_ABGR8888:
2020                 dspcntr |= DISPPLANE_RGBX888;
2021                 break;
2022         case DRM_FORMAT_XRGB2101010:
2023         case DRM_FORMAT_ARGB2101010:
2024                 dspcntr |= DISPPLANE_BGRX101010;
2025                 break;
2026         case DRM_FORMAT_XBGR2101010:
2027         case DRM_FORMAT_ABGR2101010:
2028                 dspcntr |= DISPPLANE_RGBX101010;
2029                 break;
2030         default:
2031                 BUG();
2032         }
2033
2034         if (obj->tiling_mode != I915_TILING_NONE)
2035                 dspcntr |= DISPPLANE_TILED;
2036         else
2037                 dspcntr &= ~DISPPLANE_TILED;
2038
2039         /* must disable */
2040         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2041
2042         I915_WRITE(reg, dspcntr);
2043
2044         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2045         intel_crtc->dspaddr_offset =
2046                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2047                                                fb->bits_per_pixel / 8,
2048                                                fb->pitches[0]);
2049         linear_offset -= intel_crtc->dspaddr_offset;
2050
2051         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2052                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2053         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2054         I915_MODIFY_DISPBASE(DSPSURF(plane),
2055                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2056         if (IS_HASWELL(dev)) {
2057                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2058         } else {
2059                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2060                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2061         }
2062         POSTING_READ(reg);
2063
2064         return 0;
2065 }
2066
2067 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2068 static int
2069 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2070                            int x, int y, enum mode_set_atomic state)
2071 {
2072         struct drm_device *dev = crtc->dev;
2073         struct drm_i915_private *dev_priv = dev->dev_private;
2074
2075         if (dev_priv->display.disable_fbc)
2076                 dev_priv->display.disable_fbc(dev);
2077         intel_increase_pllclock(crtc);
2078
2079         return dev_priv->display.update_plane(crtc, fb, x, y);
2080 }
2081
2082 void intel_display_handle_reset(struct drm_device *dev)
2083 {
2084         struct drm_i915_private *dev_priv = dev->dev_private;
2085         struct drm_crtc *crtc;
2086
2087         /*
2088          * Flips in the rings have been nuked by the reset,
2089          * so complete all pending flips so that user space
2090          * will get its events and not get stuck.
2091          *
2092          * Also update the base address of all primary
2093          * planes to the the last fb to make sure we're
2094          * showing the correct fb after a reset.
2095          *
2096          * Need to make two loops over the crtcs so that we
2097          * don't try to grab a crtc mutex before the
2098          * pending_flip_queue really got woken up.
2099          */
2100
2101         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2102                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103                 enum plane plane = intel_crtc->plane;
2104
2105                 intel_prepare_page_flip(dev, plane);
2106                 intel_finish_page_flip_plane(dev, plane);
2107         }
2108
2109         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2110                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112                 mutex_lock(&crtc->mutex);
2113                 if (intel_crtc->active)
2114                         dev_priv->display.update_plane(crtc, crtc->fb,
2115                                                        crtc->x, crtc->y);
2116                 mutex_unlock(&crtc->mutex);
2117         }
2118 }
2119
2120 static int
2121 intel_finish_fb(struct drm_framebuffer *old_fb)
2122 {
2123         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2124         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2125         bool was_interruptible = dev_priv->mm.interruptible;
2126         int ret;
2127
2128         /* Big Hammer, we also need to ensure that any pending
2129          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2130          * current scanout is retired before unpinning the old
2131          * framebuffer.
2132          *
2133          * This should only fail upon a hung GPU, in which case we
2134          * can safely continue.
2135          */
2136         dev_priv->mm.interruptible = false;
2137         ret = i915_gem_object_finish_gpu(obj);
2138         dev_priv->mm.interruptible = was_interruptible;
2139
2140         return ret;
2141 }
2142
2143 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2144 {
2145         struct drm_device *dev = crtc->dev;
2146         struct drm_i915_master_private *master_priv;
2147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2148
2149         if (!dev->primary->master)
2150                 return;
2151
2152         master_priv = dev->primary->master->driver_priv;
2153         if (!master_priv->sarea_priv)
2154                 return;
2155
2156         switch (intel_crtc->pipe) {
2157         case 0:
2158                 master_priv->sarea_priv->pipeA_x = x;
2159                 master_priv->sarea_priv->pipeA_y = y;
2160                 break;
2161         case 1:
2162                 master_priv->sarea_priv->pipeB_x = x;
2163                 master_priv->sarea_priv->pipeB_y = y;
2164                 break;
2165         default:
2166                 break;
2167         }
2168 }
2169
2170 static int
2171 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2172                     struct drm_framebuffer *fb)
2173 {
2174         struct drm_device *dev = crtc->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2177         struct drm_framebuffer *old_fb;
2178         int ret;
2179
2180         /* no fb bound */
2181         if (!fb) {
2182                 DRM_ERROR("No FB bound\n");
2183                 return 0;
2184         }
2185
2186         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2187                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2188                           plane_name(intel_crtc->plane),
2189                           INTEL_INFO(dev)->num_pipes);
2190                 return -EINVAL;
2191         }
2192
2193         mutex_lock(&dev->struct_mutex);
2194         ret = intel_pin_and_fence_fb_obj(dev,
2195                                          to_intel_framebuffer(fb)->obj,
2196                                          NULL);
2197         if (ret != 0) {
2198                 mutex_unlock(&dev->struct_mutex);
2199                 DRM_ERROR("pin & fence failed\n");
2200                 return ret;
2201         }
2202
2203         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2204         if (ret) {
2205                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2206                 mutex_unlock(&dev->struct_mutex);
2207                 DRM_ERROR("failed to update base address\n");
2208                 return ret;
2209         }
2210
2211         old_fb = crtc->fb;
2212         crtc->fb = fb;
2213         crtc->x = x;
2214         crtc->y = y;
2215
2216         if (old_fb) {
2217                 if (intel_crtc->active && old_fb != fb)
2218                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2219                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2220         }
2221
2222         intel_update_fbc(dev);
2223         mutex_unlock(&dev->struct_mutex);
2224
2225         intel_crtc_update_sarea_pos(crtc, x, y);
2226
2227         return 0;
2228 }
2229
2230 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2231 {
2232         struct drm_device *dev = crtc->dev;
2233         struct drm_i915_private *dev_priv = dev->dev_private;
2234         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2235         int pipe = intel_crtc->pipe;
2236         u32 reg, temp;
2237
2238         /* enable normal train */
2239         reg = FDI_TX_CTL(pipe);
2240         temp = I915_READ(reg);
2241         if (IS_IVYBRIDGE(dev)) {
2242                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2243                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2244         } else {
2245                 temp &= ~FDI_LINK_TRAIN_NONE;
2246                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2247         }
2248         I915_WRITE(reg, temp);
2249
2250         reg = FDI_RX_CTL(pipe);
2251         temp = I915_READ(reg);
2252         if (HAS_PCH_CPT(dev)) {
2253                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2254                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2255         } else {
2256                 temp &= ~FDI_LINK_TRAIN_NONE;
2257                 temp |= FDI_LINK_TRAIN_NONE;
2258         }
2259         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2260
2261         /* wait one idle pattern time */
2262         POSTING_READ(reg);
2263         udelay(1000);
2264
2265         /* IVB wants error correction enabled */
2266         if (IS_IVYBRIDGE(dev))
2267                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2268                            FDI_FE_ERRC_ENABLE);
2269 }
2270
2271 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2272 {
2273         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2274 }
2275
2276 static void ivb_modeset_global_resources(struct drm_device *dev)
2277 {
2278         struct drm_i915_private *dev_priv = dev->dev_private;
2279         struct intel_crtc *pipe_B_crtc =
2280                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2281         struct intel_crtc *pipe_C_crtc =
2282                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2283         uint32_t temp;
2284
2285         /*
2286          * When everything is off disable fdi C so that we could enable fdi B
2287          * with all lanes. Note that we don't care about enabled pipes without
2288          * an enabled pch encoder.
2289          */
2290         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2291             !pipe_has_enabled_pch(pipe_C_crtc)) {
2292                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2293                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2294
2295                 temp = I915_READ(SOUTH_CHICKEN1);
2296                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2297                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2298                 I915_WRITE(SOUTH_CHICKEN1, temp);
2299         }
2300 }
2301
2302 /* The FDI link training functions for ILK/Ibexpeak. */
2303 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2304 {
2305         struct drm_device *dev = crtc->dev;
2306         struct drm_i915_private *dev_priv = dev->dev_private;
2307         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2308         int pipe = intel_crtc->pipe;
2309         int plane = intel_crtc->plane;
2310         u32 reg, temp, tries;
2311
2312         /* FDI needs bits from pipe & plane first */
2313         assert_pipe_enabled(dev_priv, pipe);
2314         assert_plane_enabled(dev_priv, plane);
2315
2316         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2317            for train result */
2318         reg = FDI_RX_IMR(pipe);
2319         temp = I915_READ(reg);
2320         temp &= ~FDI_RX_SYMBOL_LOCK;
2321         temp &= ~FDI_RX_BIT_LOCK;
2322         I915_WRITE(reg, temp);
2323         I915_READ(reg);
2324         udelay(150);
2325
2326         /* enable CPU FDI TX and PCH FDI RX */
2327         reg = FDI_TX_CTL(pipe);
2328         temp = I915_READ(reg);
2329         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2330         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2331         temp &= ~FDI_LINK_TRAIN_NONE;
2332         temp |= FDI_LINK_TRAIN_PATTERN_1;
2333         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2334
2335         reg = FDI_RX_CTL(pipe);
2336         temp = I915_READ(reg);
2337         temp &= ~FDI_LINK_TRAIN_NONE;
2338         temp |= FDI_LINK_TRAIN_PATTERN_1;
2339         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2340
2341         POSTING_READ(reg);
2342         udelay(150);
2343
2344         /* Ironlake workaround, enable clock pointer after FDI enable*/
2345         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2346         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2347                    FDI_RX_PHASE_SYNC_POINTER_EN);
2348
2349         reg = FDI_RX_IIR(pipe);
2350         for (tries = 0; tries < 5; tries++) {
2351                 temp = I915_READ(reg);
2352                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2353
2354                 if ((temp & FDI_RX_BIT_LOCK)) {
2355                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2356                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2357                         break;
2358                 }
2359         }
2360         if (tries == 5)
2361                 DRM_ERROR("FDI train 1 fail!\n");
2362
2363         /* Train 2 */
2364         reg = FDI_TX_CTL(pipe);
2365         temp = I915_READ(reg);
2366         temp &= ~FDI_LINK_TRAIN_NONE;
2367         temp |= FDI_LINK_TRAIN_PATTERN_2;
2368         I915_WRITE(reg, temp);
2369
2370         reg = FDI_RX_CTL(pipe);
2371         temp = I915_READ(reg);
2372         temp &= ~FDI_LINK_TRAIN_NONE;
2373         temp |= FDI_LINK_TRAIN_PATTERN_2;
2374         I915_WRITE(reg, temp);
2375
2376         POSTING_READ(reg);
2377         udelay(150);
2378
2379         reg = FDI_RX_IIR(pipe);
2380         for (tries = 0; tries < 5; tries++) {
2381                 temp = I915_READ(reg);
2382                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2383
2384                 if (temp & FDI_RX_SYMBOL_LOCK) {
2385                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2386                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2387                         break;
2388                 }
2389         }
2390         if (tries == 5)
2391                 DRM_ERROR("FDI train 2 fail!\n");
2392
2393         DRM_DEBUG_KMS("FDI train done\n");
2394
2395 }
2396
2397 static const int snb_b_fdi_train_param[] = {
2398         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2399         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2400         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2401         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2402 };
2403
2404 /* The FDI link training functions for SNB/Cougarpoint. */
2405 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2406 {
2407         struct drm_device *dev = crtc->dev;
2408         struct drm_i915_private *dev_priv = dev->dev_private;
2409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410         int pipe = intel_crtc->pipe;
2411         u32 reg, temp, i, retry;
2412
2413         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2414            for train result */
2415         reg = FDI_RX_IMR(pipe);
2416         temp = I915_READ(reg);
2417         temp &= ~FDI_RX_SYMBOL_LOCK;
2418         temp &= ~FDI_RX_BIT_LOCK;
2419         I915_WRITE(reg, temp);
2420
2421         POSTING_READ(reg);
2422         udelay(150);
2423
2424         /* enable CPU FDI TX and PCH FDI RX */
2425         reg = FDI_TX_CTL(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2428         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2429         temp &= ~FDI_LINK_TRAIN_NONE;
2430         temp |= FDI_LINK_TRAIN_PATTERN_1;
2431         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2432         /* SNB-B */
2433         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         I915_WRITE(FDI_RX_MISC(pipe),
2437                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2438
2439         reg = FDI_RX_CTL(pipe);
2440         temp = I915_READ(reg);
2441         if (HAS_PCH_CPT(dev)) {
2442                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2443                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2444         } else {
2445                 temp &= ~FDI_LINK_TRAIN_NONE;
2446                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447         }
2448         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2449
2450         POSTING_READ(reg);
2451         udelay(150);
2452
2453         for (i = 0; i < 4; i++) {
2454                 reg = FDI_TX_CTL(pipe);
2455                 temp = I915_READ(reg);
2456                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2457                 temp |= snb_b_fdi_train_param[i];
2458                 I915_WRITE(reg, temp);
2459
2460                 POSTING_READ(reg);
2461                 udelay(500);
2462
2463                 for (retry = 0; retry < 5; retry++) {
2464                         reg = FDI_RX_IIR(pipe);
2465                         temp = I915_READ(reg);
2466                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2467                         if (temp & FDI_RX_BIT_LOCK) {
2468                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2469                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2470                                 break;
2471                         }
2472                         udelay(50);
2473                 }
2474                 if (retry < 5)
2475                         break;
2476         }
2477         if (i == 4)
2478                 DRM_ERROR("FDI train 1 fail!\n");
2479
2480         /* Train 2 */
2481         reg = FDI_TX_CTL(pipe);
2482         temp = I915_READ(reg);
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_2;
2485         if (IS_GEN6(dev)) {
2486                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487                 /* SNB-B */
2488                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2489         }
2490         I915_WRITE(reg, temp);
2491
2492         reg = FDI_RX_CTL(pipe);
2493         temp = I915_READ(reg);
2494         if (HAS_PCH_CPT(dev)) {
2495                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2496                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2497         } else {
2498                 temp &= ~FDI_LINK_TRAIN_NONE;
2499                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2500         }
2501         I915_WRITE(reg, temp);
2502
2503         POSTING_READ(reg);
2504         udelay(150);
2505
2506         for (i = 0; i < 4; i++) {
2507                 reg = FDI_TX_CTL(pipe);
2508                 temp = I915_READ(reg);
2509                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2510                 temp |= snb_b_fdi_train_param[i];
2511                 I915_WRITE(reg, temp);
2512
2513                 POSTING_READ(reg);
2514                 udelay(500);
2515
2516                 for (retry = 0; retry < 5; retry++) {
2517                         reg = FDI_RX_IIR(pipe);
2518                         temp = I915_READ(reg);
2519                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2520                         if (temp & FDI_RX_SYMBOL_LOCK) {
2521                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2522                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2523                                 break;
2524                         }
2525                         udelay(50);
2526                 }
2527                 if (retry < 5)
2528                         break;
2529         }
2530         if (i == 4)
2531                 DRM_ERROR("FDI train 2 fail!\n");
2532
2533         DRM_DEBUG_KMS("FDI train done.\n");
2534 }
2535
2536 /* Manual link training for Ivy Bridge A0 parts */
2537 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2538 {
2539         struct drm_device *dev = crtc->dev;
2540         struct drm_i915_private *dev_priv = dev->dev_private;
2541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2542         int pipe = intel_crtc->pipe;
2543         u32 reg, temp, i;
2544
2545         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2546            for train result */
2547         reg = FDI_RX_IMR(pipe);
2548         temp = I915_READ(reg);
2549         temp &= ~FDI_RX_SYMBOL_LOCK;
2550         temp &= ~FDI_RX_BIT_LOCK;
2551         I915_WRITE(reg, temp);
2552
2553         POSTING_READ(reg);
2554         udelay(150);
2555
2556         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2557                       I915_READ(FDI_RX_IIR(pipe)));
2558
2559         /* enable CPU FDI TX and PCH FDI RX */
2560         reg = FDI_TX_CTL(pipe);
2561         temp = I915_READ(reg);
2562         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2563         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2564         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2565         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2566         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2568         temp |= FDI_COMPOSITE_SYNC;
2569         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2570
2571         I915_WRITE(FDI_RX_MISC(pipe),
2572                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2573
2574         reg = FDI_RX_CTL(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~FDI_LINK_TRAIN_AUTO;
2577         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2578         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2579         temp |= FDI_COMPOSITE_SYNC;
2580         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2581
2582         POSTING_READ(reg);
2583         udelay(150);
2584
2585         for (i = 0; i < 4; i++) {
2586                 reg = FDI_TX_CTL(pipe);
2587                 temp = I915_READ(reg);
2588                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589                 temp |= snb_b_fdi_train_param[i];
2590                 I915_WRITE(reg, temp);
2591
2592                 POSTING_READ(reg);
2593                 udelay(500);
2594
2595                 reg = FDI_RX_IIR(pipe);
2596                 temp = I915_READ(reg);
2597                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2598
2599                 if (temp & FDI_RX_BIT_LOCK ||
2600                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2601                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2602                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2603                         break;
2604                 }
2605         }
2606         if (i == 4)
2607                 DRM_ERROR("FDI train 1 fail!\n");
2608
2609         /* Train 2 */
2610         reg = FDI_TX_CTL(pipe);
2611         temp = I915_READ(reg);
2612         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2613         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2614         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2616         I915_WRITE(reg, temp);
2617
2618         reg = FDI_RX_CTL(pipe);
2619         temp = I915_READ(reg);
2620         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2621         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2622         I915_WRITE(reg, temp);
2623
2624         POSTING_READ(reg);
2625         udelay(150);
2626
2627         for (i = 0; i < 4; i++) {
2628                 reg = FDI_TX_CTL(pipe);
2629                 temp = I915_READ(reg);
2630                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631                 temp |= snb_b_fdi_train_param[i];
2632                 I915_WRITE(reg, temp);
2633
2634                 POSTING_READ(reg);
2635                 udelay(500);
2636
2637                 reg = FDI_RX_IIR(pipe);
2638                 temp = I915_READ(reg);
2639                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2640
2641                 if (temp & FDI_RX_SYMBOL_LOCK) {
2642                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2643                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2644                         break;
2645                 }
2646         }
2647         if (i == 4)
2648                 DRM_ERROR("FDI train 2 fail!\n");
2649
2650         DRM_DEBUG_KMS("FDI train done.\n");
2651 }
2652
2653 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2654 {
2655         struct drm_device *dev = intel_crtc->base.dev;
2656         struct drm_i915_private *dev_priv = dev->dev_private;
2657         int pipe = intel_crtc->pipe;
2658         u32 reg, temp;
2659
2660
2661         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2662         reg = FDI_RX_CTL(pipe);
2663         temp = I915_READ(reg);
2664         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2665         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2666         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2667         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2668
2669         POSTING_READ(reg);
2670         udelay(200);
2671
2672         /* Switch from Rawclk to PCDclk */
2673         temp = I915_READ(reg);
2674         I915_WRITE(reg, temp | FDI_PCDCLK);
2675
2676         POSTING_READ(reg);
2677         udelay(200);
2678
2679         /* Enable CPU FDI TX PLL, always on for Ironlake */
2680         reg = FDI_TX_CTL(pipe);
2681         temp = I915_READ(reg);
2682         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2683                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2684
2685                 POSTING_READ(reg);
2686                 udelay(100);
2687         }
2688 }
2689
2690 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2691 {
2692         struct drm_device *dev = intel_crtc->base.dev;
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         int pipe = intel_crtc->pipe;
2695         u32 reg, temp;
2696
2697         /* Switch from PCDclk to Rawclk */
2698         reg = FDI_RX_CTL(pipe);
2699         temp = I915_READ(reg);
2700         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2701
2702         /* Disable CPU FDI TX PLL */
2703         reg = FDI_TX_CTL(pipe);
2704         temp = I915_READ(reg);
2705         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2706
2707         POSTING_READ(reg);
2708         udelay(100);
2709
2710         reg = FDI_RX_CTL(pipe);
2711         temp = I915_READ(reg);
2712         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2713
2714         /* Wait for the clocks to turn off. */
2715         POSTING_READ(reg);
2716         udelay(100);
2717 }
2718
2719 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2720 {
2721         struct drm_device *dev = crtc->dev;
2722         struct drm_i915_private *dev_priv = dev->dev_private;
2723         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2724         int pipe = intel_crtc->pipe;
2725         u32 reg, temp;
2726
2727         /* disable CPU FDI tx and PCH FDI rx */
2728         reg = FDI_TX_CTL(pipe);
2729         temp = I915_READ(reg);
2730         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2731         POSTING_READ(reg);
2732
2733         reg = FDI_RX_CTL(pipe);
2734         temp = I915_READ(reg);
2735         temp &= ~(0x7 << 16);
2736         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2737         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2738
2739         POSTING_READ(reg);
2740         udelay(100);
2741
2742         /* Ironlake workaround, disable clock pointer after downing FDI */
2743         if (HAS_PCH_IBX(dev)) {
2744                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2745         }
2746
2747         /* still set train pattern 1 */
2748         reg = FDI_TX_CTL(pipe);
2749         temp = I915_READ(reg);
2750         temp &= ~FDI_LINK_TRAIN_NONE;
2751         temp |= FDI_LINK_TRAIN_PATTERN_1;
2752         I915_WRITE(reg, temp);
2753
2754         reg = FDI_RX_CTL(pipe);
2755         temp = I915_READ(reg);
2756         if (HAS_PCH_CPT(dev)) {
2757                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2758                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2759         } else {
2760                 temp &= ~FDI_LINK_TRAIN_NONE;
2761                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2762         }
2763         /* BPC in FDI rx is consistent with that in PIPECONF */
2764         temp &= ~(0x07 << 16);
2765         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2766         I915_WRITE(reg, temp);
2767
2768         POSTING_READ(reg);
2769         udelay(100);
2770 }
2771
2772 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2773 {
2774         struct drm_device *dev = crtc->dev;
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777         unsigned long flags;
2778         bool pending;
2779
2780         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2781             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2782                 return false;
2783
2784         spin_lock_irqsave(&dev->event_lock, flags);
2785         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2786         spin_unlock_irqrestore(&dev->event_lock, flags);
2787
2788         return pending;
2789 }
2790
2791 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2792 {
2793         struct drm_device *dev = crtc->dev;
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795
2796         if (crtc->fb == NULL)
2797                 return;
2798
2799         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2800
2801         wait_event(dev_priv->pending_flip_queue,
2802                    !intel_crtc_has_pending_flip(crtc));
2803
2804         mutex_lock(&dev->struct_mutex);
2805         intel_finish_fb(crtc->fb);
2806         mutex_unlock(&dev->struct_mutex);
2807 }
2808
2809 /* Program iCLKIP clock to the desired frequency */
2810 static void lpt_program_iclkip(struct drm_crtc *crtc)
2811 {
2812         struct drm_device *dev = crtc->dev;
2813         struct drm_i915_private *dev_priv = dev->dev_private;
2814         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2815         u32 temp;
2816
2817         mutex_lock(&dev_priv->dpio_lock);
2818
2819         /* It is necessary to ungate the pixclk gate prior to programming
2820          * the divisors, and gate it back when it is done.
2821          */
2822         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2823
2824         /* Disable SSCCTL */
2825         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2826                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2827                                 SBI_SSCCTL_DISABLE,
2828                         SBI_ICLK);
2829
2830         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2831         if (crtc->mode.clock == 20000) {
2832                 auxdiv = 1;
2833                 divsel = 0x41;
2834                 phaseinc = 0x20;
2835         } else {
2836                 /* The iCLK virtual clock root frequency is in MHz,
2837                  * but the crtc->mode.clock in in KHz. To get the divisors,
2838                  * it is necessary to divide one by another, so we
2839                  * convert the virtual clock precision to KHz here for higher
2840                  * precision.
2841                  */
2842                 u32 iclk_virtual_root_freq = 172800 * 1000;
2843                 u32 iclk_pi_range = 64;
2844                 u32 desired_divisor, msb_divisor_value, pi_value;
2845
2846                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2847                 msb_divisor_value = desired_divisor / iclk_pi_range;
2848                 pi_value = desired_divisor % iclk_pi_range;
2849
2850                 auxdiv = 0;
2851                 divsel = msb_divisor_value - 2;
2852                 phaseinc = pi_value;
2853         }
2854
2855         /* This should not happen with any sane values */
2856         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2857                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2858         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2859                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2860
2861         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2862                         crtc->mode.clock,
2863                         auxdiv,
2864                         divsel,
2865                         phasedir,
2866                         phaseinc);
2867
2868         /* Program SSCDIVINTPHASE6 */
2869         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2870         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2871         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2872         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2873         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2874         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2875         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2876         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2877
2878         /* Program SSCAUXDIV */
2879         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2880         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2881         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2882         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2883
2884         /* Enable modulator and associated divider */
2885         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2886         temp &= ~SBI_SSCCTL_DISABLE;
2887         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2888
2889         /* Wait for initialization time */
2890         udelay(24);
2891
2892         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2893
2894         mutex_unlock(&dev_priv->dpio_lock);
2895 }
2896
2897 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2898                                                 enum pipe pch_transcoder)
2899 {
2900         struct drm_device *dev = crtc->base.dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2903
2904         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2905                    I915_READ(HTOTAL(cpu_transcoder)));
2906         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2907                    I915_READ(HBLANK(cpu_transcoder)));
2908         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2909                    I915_READ(HSYNC(cpu_transcoder)));
2910
2911         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2912                    I915_READ(VTOTAL(cpu_transcoder)));
2913         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2914                    I915_READ(VBLANK(cpu_transcoder)));
2915         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2916                    I915_READ(VSYNC(cpu_transcoder)));
2917         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2918                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2919 }
2920
2921 /*
2922  * Enable PCH resources required for PCH ports:
2923  *   - PCH PLLs
2924  *   - FDI training & RX/TX
2925  *   - update transcoder timings
2926  *   - DP transcoding bits
2927  *   - transcoder
2928  */
2929 static void ironlake_pch_enable(struct drm_crtc *crtc)
2930 {
2931         struct drm_device *dev = crtc->dev;
2932         struct drm_i915_private *dev_priv = dev->dev_private;
2933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2934         int pipe = intel_crtc->pipe;
2935         u32 reg, temp;
2936
2937         assert_pch_transcoder_disabled(dev_priv, pipe);
2938
2939         /* Write the TU size bits before fdi link training, so that error
2940          * detection works. */
2941         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2942                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2943
2944         /* For PCH output, training FDI link */
2945         dev_priv->display.fdi_link_train(crtc);
2946
2947         /* XXX: pch pll's can be enabled any time before we enable the PCH
2948          * transcoder, and we actually should do this to not upset any PCH
2949          * transcoder that already use the clock when we share it.
2950          *
2951          * Note that enable_shared_dpll tries to do the right thing, but
2952          * get_shared_dpll unconditionally resets the pll - we need that to have
2953          * the right LVDS enable sequence. */
2954         ironlake_enable_shared_dpll(intel_crtc);
2955
2956         if (HAS_PCH_CPT(dev)) {
2957                 u32 sel;
2958
2959                 temp = I915_READ(PCH_DPLL_SEL);
2960                 temp |= TRANS_DPLL_ENABLE(pipe);
2961                 sel = TRANS_DPLLB_SEL(pipe);
2962                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2963                         temp |= sel;
2964                 else
2965                         temp &= ~sel;
2966                 I915_WRITE(PCH_DPLL_SEL, temp);
2967         }
2968
2969         /* set transcoder timing, panel must allow it */
2970         assert_panel_unlocked(dev_priv, pipe);
2971         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2972
2973         intel_fdi_normal_train(crtc);
2974
2975         /* For PCH DP, enable TRANS_DP_CTL */
2976         if (HAS_PCH_CPT(dev) &&
2977             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2978              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2979                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2980                 reg = TRANS_DP_CTL(pipe);
2981                 temp = I915_READ(reg);
2982                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2983                           TRANS_DP_SYNC_MASK |
2984                           TRANS_DP_BPC_MASK);
2985                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2986                          TRANS_DP_ENH_FRAMING);
2987                 temp |= bpc << 9; /* same format but at 11:9 */
2988
2989                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2990                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2991                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2992                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2993
2994                 switch (intel_trans_dp_port_sel(crtc)) {
2995                 case PCH_DP_B:
2996                         temp |= TRANS_DP_PORT_SEL_B;
2997                         break;
2998                 case PCH_DP_C:
2999                         temp |= TRANS_DP_PORT_SEL_C;
3000                         break;
3001                 case PCH_DP_D:
3002                         temp |= TRANS_DP_PORT_SEL_D;
3003                         break;
3004                 default:
3005                         BUG();
3006                 }
3007
3008                 I915_WRITE(reg, temp);
3009         }
3010
3011         ironlake_enable_pch_transcoder(dev_priv, pipe);
3012 }
3013
3014 static void lpt_pch_enable(struct drm_crtc *crtc)
3015 {
3016         struct drm_device *dev = crtc->dev;
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3020
3021         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3022
3023         lpt_program_iclkip(crtc);
3024
3025         /* Set transcoder timing. */
3026         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3027
3028         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3029 }
3030
3031 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3032 {
3033         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3034
3035         if (pll == NULL)
3036                 return;
3037
3038         if (pll->refcount == 0) {
3039                 WARN(1, "bad %s refcount\n", pll->name);
3040                 return;
3041         }
3042
3043         if (--pll->refcount == 0) {
3044                 WARN_ON(pll->on);
3045                 WARN_ON(pll->active);
3046         }
3047
3048         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3049 }
3050
3051 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3052 {
3053         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3054         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3055         enum intel_dpll_id i;
3056
3057         if (pll) {
3058                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3059                               crtc->base.base.id, pll->name);
3060                 intel_put_shared_dpll(crtc);
3061         }
3062
3063         if (HAS_PCH_IBX(dev_priv->dev)) {
3064                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3065                 i = crtc->pipe;
3066                 pll = &dev_priv->shared_dplls[i];
3067
3068                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3069                               crtc->base.base.id, pll->name);
3070
3071                 goto found;
3072         }
3073
3074         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3075                 pll = &dev_priv->shared_dplls[i];
3076
3077                 /* Only want to check enabled timings first */
3078                 if (pll->refcount == 0)
3079                         continue;
3080
3081                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3082                            sizeof(pll->hw_state)) == 0) {
3083                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3084                                       crtc->base.base.id,
3085                                       pll->name, pll->refcount, pll->active);
3086
3087                         goto found;
3088                 }
3089         }
3090
3091         /* Ok no matching timings, maybe there's a free one? */
3092         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3093                 pll = &dev_priv->shared_dplls[i];
3094                 if (pll->refcount == 0) {
3095                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3096                                       crtc->base.base.id, pll->name);
3097                         goto found;
3098                 }
3099         }
3100
3101         return NULL;
3102
3103 found:
3104         crtc->config.shared_dpll = i;
3105         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3106                          pipe_name(crtc->pipe));
3107
3108         if (pll->active == 0) {
3109                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3110                        sizeof(pll->hw_state));
3111
3112                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3113                 WARN_ON(pll->on);
3114                 assert_shared_dpll_disabled(dev_priv, pll);
3115
3116                 pll->mode_set(dev_priv, pll);
3117         }
3118         pll->refcount++;
3119
3120         return pll;
3121 }
3122
3123 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3124 {
3125         struct drm_i915_private *dev_priv = dev->dev_private;
3126         int dslreg = PIPEDSL(pipe);
3127         u32 temp;
3128
3129         temp = I915_READ(dslreg);
3130         udelay(500);
3131         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3132                 if (wait_for(I915_READ(dslreg) != temp, 5))
3133                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3134         }
3135 }
3136
3137 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3138 {
3139         struct drm_device *dev = crtc->base.dev;
3140         struct drm_i915_private *dev_priv = dev->dev_private;
3141         int pipe = crtc->pipe;
3142
3143         if (crtc->config.pch_pfit.size) {
3144                 /* Force use of hard-coded filter coefficients
3145                  * as some pre-programmed values are broken,
3146                  * e.g. x201.
3147                  */
3148                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3149                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3150                                                  PF_PIPE_SEL_IVB(pipe));
3151                 else
3152                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3153                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3154                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3155         }
3156 }
3157
3158 static void intel_enable_planes(struct drm_crtc *crtc)
3159 {
3160         struct drm_device *dev = crtc->dev;
3161         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162         struct intel_plane *intel_plane;
3163
3164         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165                 if (intel_plane->pipe == pipe)
3166                         intel_plane_restore(&intel_plane->base);
3167 }
3168
3169 static void intel_disable_planes(struct drm_crtc *crtc)
3170 {
3171         struct drm_device *dev = crtc->dev;
3172         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3173         struct intel_plane *intel_plane;
3174
3175         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3176                 if (intel_plane->pipe == pipe)
3177                         intel_plane_disable(&intel_plane->base);
3178 }
3179
3180 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3181 {
3182         struct drm_device *dev = crtc->dev;
3183         struct drm_i915_private *dev_priv = dev->dev_private;
3184         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3185         struct intel_encoder *encoder;
3186         int pipe = intel_crtc->pipe;
3187         int plane = intel_crtc->plane;
3188
3189         WARN_ON(!crtc->enabled);
3190
3191         if (intel_crtc->active)
3192                 return;
3193
3194         intel_crtc->active = true;
3195
3196         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3197         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3198
3199         intel_update_watermarks(dev);
3200
3201         for_each_encoder_on_crtc(dev, crtc, encoder) {
3202                 if (encoder->pre_pll_enable)
3203                         encoder->pre_pll_enable(encoder);
3204                 if (encoder->pre_enable)
3205                         encoder->pre_enable(encoder);
3206         }
3207
3208         if (intel_crtc->config.has_pch_encoder) {
3209                 /* Note: FDI PLL enabling _must_ be done before we enable the
3210                  * cpu pipes, hence this is separate from all the other fdi/pch
3211                  * enabling. */
3212                 ironlake_fdi_pll_enable(intel_crtc);
3213         } else {
3214                 assert_fdi_tx_disabled(dev_priv, pipe);
3215                 assert_fdi_rx_disabled(dev_priv, pipe);
3216         }
3217
3218         ironlake_pfit_enable(intel_crtc);
3219
3220         /*
3221          * On ILK+ LUT must be loaded before the pipe is running but with
3222          * clocks enabled
3223          */
3224         intel_crtc_load_lut(crtc);
3225
3226         intel_enable_pipe(dev_priv, pipe,
3227                           intel_crtc->config.has_pch_encoder);
3228         intel_enable_plane(dev_priv, plane, pipe);
3229         intel_enable_planes(crtc);
3230         intel_crtc_update_cursor(crtc, true);
3231
3232         if (intel_crtc->config.has_pch_encoder)
3233                 ironlake_pch_enable(crtc);
3234
3235         mutex_lock(&dev->struct_mutex);
3236         intel_update_fbc(dev);
3237         mutex_unlock(&dev->struct_mutex);
3238
3239         for_each_encoder_on_crtc(dev, crtc, encoder)
3240                 encoder->enable(encoder);
3241
3242         if (HAS_PCH_CPT(dev))
3243                 cpt_verify_modeset(dev, intel_crtc->pipe);
3244
3245         /*
3246          * There seems to be a race in PCH platform hw (at least on some
3247          * outputs) where an enabled pipe still completes any pageflip right
3248          * away (as if the pipe is off) instead of waiting for vblank. As soon
3249          * as the first vblank happend, everything works as expected. Hence just
3250          * wait for one vblank before returning to avoid strange things
3251          * happening.
3252          */
3253         intel_wait_for_vblank(dev, intel_crtc->pipe);
3254 }
3255
3256 /* IPS only exists on ULT machines and is tied to pipe A. */
3257 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3258 {
3259         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3260 }
3261
3262 static void hsw_enable_ips(struct intel_crtc *crtc)
3263 {
3264         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3265
3266         if (!crtc->config.ips_enabled)
3267                 return;
3268
3269         /* We can only enable IPS after we enable a plane and wait for a vblank.
3270          * We guarantee that the plane is enabled by calling intel_enable_ips
3271          * only after intel_enable_plane. And intel_enable_plane already waits
3272          * for a vblank, so all we need to do here is to enable the IPS bit. */
3273         assert_plane_enabled(dev_priv, crtc->plane);
3274         I915_WRITE(IPS_CTL, IPS_ENABLE);
3275 }
3276
3277 static void hsw_disable_ips(struct intel_crtc *crtc)
3278 {
3279         struct drm_device *dev = crtc->base.dev;
3280         struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282         if (!crtc->config.ips_enabled)
3283                 return;
3284
3285         assert_plane_enabled(dev_priv, crtc->plane);
3286         I915_WRITE(IPS_CTL, 0);
3287
3288         /* We need to wait for a vblank before we can disable the plane. */
3289         intel_wait_for_vblank(dev, crtc->pipe);
3290 }
3291
3292 static void haswell_crtc_enable(struct drm_crtc *crtc)
3293 {
3294         struct drm_device *dev = crtc->dev;
3295         struct drm_i915_private *dev_priv = dev->dev_private;
3296         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3297         struct intel_encoder *encoder;
3298         int pipe = intel_crtc->pipe;
3299         int plane = intel_crtc->plane;
3300
3301         WARN_ON(!crtc->enabled);
3302
3303         if (intel_crtc->active)
3304                 return;
3305
3306         intel_crtc->active = true;
3307
3308         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3309         if (intel_crtc->config.has_pch_encoder)
3310                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3311
3312         intel_update_watermarks(dev);
3313
3314         if (intel_crtc->config.has_pch_encoder)
3315                 dev_priv->display.fdi_link_train(crtc);
3316
3317         for_each_encoder_on_crtc(dev, crtc, encoder)
3318                 if (encoder->pre_enable)
3319                         encoder->pre_enable(encoder);
3320
3321         intel_ddi_enable_pipe_clock(intel_crtc);
3322
3323         ironlake_pfit_enable(intel_crtc);
3324
3325         /*
3326          * On ILK+ LUT must be loaded before the pipe is running but with
3327          * clocks enabled
3328          */
3329         intel_crtc_load_lut(crtc);
3330
3331         intel_ddi_set_pipe_settings(crtc);
3332         intel_ddi_enable_transcoder_func(crtc);
3333
3334         intel_enable_pipe(dev_priv, pipe,
3335                           intel_crtc->config.has_pch_encoder);
3336         intel_enable_plane(dev_priv, plane, pipe);
3337         intel_enable_planes(crtc);
3338         intel_crtc_update_cursor(crtc, true);
3339
3340         hsw_enable_ips(intel_crtc);
3341
3342         if (intel_crtc->config.has_pch_encoder)
3343                 lpt_pch_enable(crtc);
3344
3345         mutex_lock(&dev->struct_mutex);
3346         intel_update_fbc(dev);
3347         mutex_unlock(&dev->struct_mutex);
3348
3349         for_each_encoder_on_crtc(dev, crtc, encoder)
3350                 encoder->enable(encoder);
3351
3352         /*
3353          * There seems to be a race in PCH platform hw (at least on some
3354          * outputs) where an enabled pipe still completes any pageflip right
3355          * away (as if the pipe is off) instead of waiting for vblank. As soon
3356          * as the first vblank happend, everything works as expected. Hence just
3357          * wait for one vblank before returning to avoid strange things
3358          * happening.
3359          */
3360         intel_wait_for_vblank(dev, intel_crtc->pipe);
3361 }
3362
3363 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3364 {
3365         struct drm_device *dev = crtc->base.dev;
3366         struct drm_i915_private *dev_priv = dev->dev_private;
3367         int pipe = crtc->pipe;
3368
3369         /* To avoid upsetting the power well on haswell only disable the pfit if
3370          * it's in use. The hw state code will make sure we get this right. */
3371         if (crtc->config.pch_pfit.size) {
3372                 I915_WRITE(PF_CTL(pipe), 0);
3373                 I915_WRITE(PF_WIN_POS(pipe), 0);
3374                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3375         }
3376 }
3377
3378 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383         struct intel_encoder *encoder;
3384         int pipe = intel_crtc->pipe;
3385         int plane = intel_crtc->plane;
3386         u32 reg, temp;
3387
3388
3389         if (!intel_crtc->active)
3390                 return;
3391
3392         for_each_encoder_on_crtc(dev, crtc, encoder)
3393                 encoder->disable(encoder);
3394
3395         intel_crtc_wait_for_pending_flips(crtc);
3396         drm_vblank_off(dev, pipe);
3397
3398         if (dev_priv->cfb_plane == plane)
3399                 intel_disable_fbc(dev);
3400
3401         intel_crtc_update_cursor(crtc, false);
3402         intel_disable_planes(crtc);
3403         intel_disable_plane(dev_priv, plane, pipe);
3404
3405         if (intel_crtc->config.has_pch_encoder)
3406                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3407
3408         intel_disable_pipe(dev_priv, pipe);
3409
3410         ironlake_pfit_disable(intel_crtc);
3411
3412         for_each_encoder_on_crtc(dev, crtc, encoder)
3413                 if (encoder->post_disable)
3414                         encoder->post_disable(encoder);
3415
3416         if (intel_crtc->config.has_pch_encoder) {
3417                 ironlake_fdi_disable(crtc);
3418
3419                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3420                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3421
3422                 if (HAS_PCH_CPT(dev)) {
3423                         /* disable TRANS_DP_CTL */
3424                         reg = TRANS_DP_CTL(pipe);
3425                         temp = I915_READ(reg);
3426                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3427                                   TRANS_DP_PORT_SEL_MASK);
3428                         temp |= TRANS_DP_PORT_SEL_NONE;
3429                         I915_WRITE(reg, temp);
3430
3431                         /* disable DPLL_SEL */
3432                         temp = I915_READ(PCH_DPLL_SEL);
3433                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3434                         I915_WRITE(PCH_DPLL_SEL, temp);
3435                 }
3436
3437                 /* disable PCH DPLL */
3438                 intel_disable_shared_dpll(intel_crtc);
3439
3440                 ironlake_fdi_pll_disable(intel_crtc);
3441         }
3442
3443         intel_crtc->active = false;
3444         intel_update_watermarks(dev);
3445
3446         mutex_lock(&dev->struct_mutex);
3447         intel_update_fbc(dev);
3448         mutex_unlock(&dev->struct_mutex);
3449 }
3450
3451 static void haswell_crtc_disable(struct drm_crtc *crtc)
3452 {
3453         struct drm_device *dev = crtc->dev;
3454         struct drm_i915_private *dev_priv = dev->dev_private;
3455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3456         struct intel_encoder *encoder;
3457         int pipe = intel_crtc->pipe;
3458         int plane = intel_crtc->plane;
3459         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3460
3461         if (!intel_crtc->active)
3462                 return;
3463
3464         for_each_encoder_on_crtc(dev, crtc, encoder)
3465                 encoder->disable(encoder);
3466
3467         intel_crtc_wait_for_pending_flips(crtc);
3468         drm_vblank_off(dev, pipe);
3469
3470         /* FBC must be disabled before disabling the plane on HSW. */
3471         if (dev_priv->cfb_plane == plane)
3472                 intel_disable_fbc(dev);
3473
3474         hsw_disable_ips(intel_crtc);
3475
3476         intel_crtc_update_cursor(crtc, false);
3477         intel_disable_planes(crtc);
3478         intel_disable_plane(dev_priv, plane, pipe);
3479
3480         if (intel_crtc->config.has_pch_encoder)
3481                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3482         intel_disable_pipe(dev_priv, pipe);
3483
3484         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3485
3486         ironlake_pfit_disable(intel_crtc);
3487
3488         intel_ddi_disable_pipe_clock(intel_crtc);
3489
3490         for_each_encoder_on_crtc(dev, crtc, encoder)
3491                 if (encoder->post_disable)
3492                         encoder->post_disable(encoder);
3493
3494         if (intel_crtc->config.has_pch_encoder) {
3495                 lpt_disable_pch_transcoder(dev_priv);
3496                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3497                 intel_ddi_fdi_disable(crtc);
3498         }
3499
3500         intel_crtc->active = false;
3501         intel_update_watermarks(dev);
3502
3503         mutex_lock(&dev->struct_mutex);
3504         intel_update_fbc(dev);
3505         mutex_unlock(&dev->struct_mutex);
3506 }
3507
3508 static void ironlake_crtc_off(struct drm_crtc *crtc)
3509 {
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         intel_put_shared_dpll(intel_crtc);
3512 }
3513
3514 static void haswell_crtc_off(struct drm_crtc *crtc)
3515 {
3516         intel_ddi_put_crtc_pll(crtc);
3517 }
3518
3519 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3520 {
3521         if (!enable && intel_crtc->overlay) {
3522                 struct drm_device *dev = intel_crtc->base.dev;
3523                 struct drm_i915_private *dev_priv = dev->dev_private;
3524
3525                 mutex_lock(&dev->struct_mutex);
3526                 dev_priv->mm.interruptible = false;
3527                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3528                 dev_priv->mm.interruptible = true;
3529                 mutex_unlock(&dev->struct_mutex);
3530         }
3531
3532         /* Let userspace switch the overlay on again. In most cases userspace
3533          * has to recompute where to put it anyway.
3534          */
3535 }
3536
3537 /**
3538  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3539  * cursor plane briefly if not already running after enabling the display
3540  * plane.
3541  * This workaround avoids occasional blank screens when self refresh is
3542  * enabled.
3543  */
3544 static void
3545 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3546 {
3547         u32 cntl = I915_READ(CURCNTR(pipe));
3548
3549         if ((cntl & CURSOR_MODE) == 0) {
3550                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3551
3552                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3553                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3554                 intel_wait_for_vblank(dev_priv->dev, pipe);
3555                 I915_WRITE(CURCNTR(pipe), cntl);
3556                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3557                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3558         }
3559 }
3560
3561 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3562 {
3563         struct drm_device *dev = crtc->base.dev;
3564         struct drm_i915_private *dev_priv = dev->dev_private;
3565         struct intel_crtc_config *pipe_config = &crtc->config;
3566
3567         if (!crtc->config.gmch_pfit.control)
3568                 return;
3569
3570         /*
3571          * The panel fitter should only be adjusted whilst the pipe is disabled,
3572          * according to register description and PRM.
3573          */
3574         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3575         assert_pipe_disabled(dev_priv, crtc->pipe);
3576
3577         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3578         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3579
3580         /* Border color in case we don't scale up to the full screen. Black by
3581          * default, change to something else for debugging. */
3582         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3583 }
3584
3585 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3586 {
3587         struct drm_device *dev = crtc->dev;
3588         struct drm_i915_private *dev_priv = dev->dev_private;
3589         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3590         struct intel_encoder *encoder;
3591         int pipe = intel_crtc->pipe;
3592         int plane = intel_crtc->plane;
3593
3594         WARN_ON(!crtc->enabled);
3595
3596         if (intel_crtc->active)
3597                 return;
3598
3599         intel_crtc->active = true;
3600         intel_update_watermarks(dev);
3601
3602         mutex_lock(&dev_priv->dpio_lock);
3603
3604         for_each_encoder_on_crtc(dev, crtc, encoder)
3605                 if (encoder->pre_pll_enable)
3606                         encoder->pre_pll_enable(encoder);
3607
3608         vlv_enable_pll(dev_priv, pipe);
3609
3610         for_each_encoder_on_crtc(dev, crtc, encoder)
3611                 if (encoder->pre_enable)
3612                         encoder->pre_enable(encoder);
3613
3614         /* VLV wants encoder enabling _before_ the pipe is up. */
3615         for_each_encoder_on_crtc(dev, crtc, encoder)
3616                 encoder->enable(encoder);
3617
3618         i9xx_pfit_enable(intel_crtc);
3619
3620         intel_crtc_load_lut(crtc);
3621
3622         intel_enable_pipe(dev_priv, pipe, false);
3623         intel_enable_plane(dev_priv, plane, pipe);
3624         intel_enable_planes(crtc);
3625         intel_crtc_update_cursor(crtc, true);
3626
3627         intel_update_fbc(dev);
3628
3629         mutex_unlock(&dev_priv->dpio_lock);
3630 }
3631
3632 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3633 {
3634         struct drm_device *dev = crtc->dev;
3635         struct drm_i915_private *dev_priv = dev->dev_private;
3636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3637         struct intel_encoder *encoder;
3638         int pipe = intel_crtc->pipe;
3639         int plane = intel_crtc->plane;
3640
3641         WARN_ON(!crtc->enabled);
3642
3643         if (intel_crtc->active)
3644                 return;
3645
3646         intel_crtc->active = true;
3647         intel_update_watermarks(dev);
3648
3649         i9xx_enable_pll(dev_priv, pipe);
3650
3651         for_each_encoder_on_crtc(dev, crtc, encoder)
3652                 if (encoder->pre_enable)
3653                         encoder->pre_enable(encoder);
3654
3655         i9xx_pfit_enable(intel_crtc);
3656
3657         intel_crtc_load_lut(crtc);
3658
3659         intel_enable_pipe(dev_priv, pipe, false);
3660         intel_enable_plane(dev_priv, plane, pipe);
3661         intel_enable_planes(crtc);
3662         /* The fixup needs to happen before cursor is enabled */
3663         if (IS_G4X(dev))
3664                 g4x_fixup_plane(dev_priv, pipe);
3665         intel_crtc_update_cursor(crtc, true);
3666
3667         /* Give the overlay scaler a chance to enable if it's on this pipe */
3668         intel_crtc_dpms_overlay(intel_crtc, true);
3669
3670         intel_update_fbc(dev);
3671
3672         for_each_encoder_on_crtc(dev, crtc, encoder)
3673                 encoder->enable(encoder);
3674 }
3675
3676 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3677 {
3678         struct drm_device *dev = crtc->base.dev;
3679         struct drm_i915_private *dev_priv = dev->dev_private;
3680
3681         if (!crtc->config.gmch_pfit.control)
3682                 return;
3683
3684         assert_pipe_disabled(dev_priv, crtc->pipe);
3685
3686         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3687                          I915_READ(PFIT_CONTROL));
3688         I915_WRITE(PFIT_CONTROL, 0);
3689 }
3690
3691 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3692 {
3693         struct drm_device *dev = crtc->dev;
3694         struct drm_i915_private *dev_priv = dev->dev_private;
3695         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3696         struct intel_encoder *encoder;
3697         int pipe = intel_crtc->pipe;
3698         int plane = intel_crtc->plane;
3699
3700         if (!intel_crtc->active)
3701                 return;
3702
3703         for_each_encoder_on_crtc(dev, crtc, encoder)
3704                 encoder->disable(encoder);
3705
3706         /* Give the overlay scaler a chance to disable if it's on this pipe */
3707         intel_crtc_wait_for_pending_flips(crtc);
3708         drm_vblank_off(dev, pipe);
3709
3710         if (dev_priv->cfb_plane == plane)
3711                 intel_disable_fbc(dev);
3712
3713         intel_crtc_dpms_overlay(intel_crtc, false);
3714         intel_crtc_update_cursor(crtc, false);
3715         intel_disable_planes(crtc);
3716         intel_disable_plane(dev_priv, plane, pipe);
3717
3718         intel_disable_pipe(dev_priv, pipe);
3719
3720         i9xx_pfit_disable(intel_crtc);
3721
3722         for_each_encoder_on_crtc(dev, crtc, encoder)
3723                 if (encoder->post_disable)
3724                         encoder->post_disable(encoder);
3725
3726         intel_disable_pll(dev_priv, pipe);
3727
3728         intel_crtc->active = false;
3729         intel_update_fbc(dev);
3730         intel_update_watermarks(dev);
3731 }
3732
3733 static void i9xx_crtc_off(struct drm_crtc *crtc)
3734 {
3735 }
3736
3737 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3738                                     bool enabled)
3739 {
3740         struct drm_device *dev = crtc->dev;
3741         struct drm_i915_master_private *master_priv;
3742         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743         int pipe = intel_crtc->pipe;
3744
3745         if (!dev->primary->master)
3746                 return;
3747
3748         master_priv = dev->primary->master->driver_priv;
3749         if (!master_priv->sarea_priv)
3750                 return;
3751
3752         switch (pipe) {
3753         case 0:
3754                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3755                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3756                 break;
3757         case 1:
3758                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3759                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3760                 break;
3761         default:
3762                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3763                 break;
3764         }
3765 }
3766
3767 /**
3768  * Sets the power management mode of the pipe and plane.
3769  */
3770 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3771 {
3772         struct drm_device *dev = crtc->dev;
3773         struct drm_i915_private *dev_priv = dev->dev_private;
3774         struct intel_encoder *intel_encoder;
3775         bool enable = false;
3776
3777         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3778                 enable |= intel_encoder->connectors_active;
3779
3780         if (enable)
3781                 dev_priv->display.crtc_enable(crtc);
3782         else
3783                 dev_priv->display.crtc_disable(crtc);
3784
3785         intel_crtc_update_sarea(crtc, enable);
3786 }
3787
3788 static void intel_crtc_disable(struct drm_crtc *crtc)
3789 {
3790         struct drm_device *dev = crtc->dev;
3791         struct drm_connector *connector;
3792         struct drm_i915_private *dev_priv = dev->dev_private;
3793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3794
3795         /* crtc should still be enabled when we disable it. */
3796         WARN_ON(!crtc->enabled);
3797
3798         dev_priv->display.crtc_disable(crtc);
3799         intel_crtc->eld_vld = false;
3800         intel_crtc_update_sarea(crtc, false);
3801         dev_priv->display.off(crtc);
3802
3803         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3804         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3805
3806         if (crtc->fb) {
3807                 mutex_lock(&dev->struct_mutex);
3808                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3809                 mutex_unlock(&dev->struct_mutex);
3810                 crtc->fb = NULL;
3811         }
3812
3813         /* Update computed state. */
3814         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3815                 if (!connector->encoder || !connector->encoder->crtc)
3816                         continue;
3817
3818                 if (connector->encoder->crtc != crtc)
3819                         continue;
3820
3821                 connector->dpms = DRM_MODE_DPMS_OFF;
3822                 to_intel_encoder(connector->encoder)->connectors_active = false;
3823         }
3824 }
3825
3826 void intel_modeset_disable(struct drm_device *dev)
3827 {
3828         struct drm_crtc *crtc;
3829
3830         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3831                 if (crtc->enabled)
3832                         intel_crtc_disable(crtc);
3833         }
3834 }
3835
3836 void intel_encoder_destroy(struct drm_encoder *encoder)
3837 {
3838         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3839
3840         drm_encoder_cleanup(encoder);
3841         kfree(intel_encoder);
3842 }
3843
3844 /* Simple dpms helper for encodres with just one connector, no cloning and only
3845  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3846  * state of the entire output pipe. */
3847 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3848 {
3849         if (mode == DRM_MODE_DPMS_ON) {
3850                 encoder->connectors_active = true;
3851
3852                 intel_crtc_update_dpms(encoder->base.crtc);
3853         } else {
3854                 encoder->connectors_active = false;
3855
3856                 intel_crtc_update_dpms(encoder->base.crtc);
3857         }
3858 }
3859
3860 /* Cross check the actual hw state with our own modeset state tracking (and it's
3861  * internal consistency). */
3862 static void intel_connector_check_state(struct intel_connector *connector)
3863 {
3864         if (connector->get_hw_state(connector)) {
3865                 struct intel_encoder *encoder = connector->encoder;
3866                 struct drm_crtc *crtc;
3867                 bool encoder_enabled;
3868                 enum pipe pipe;
3869
3870                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3871                               connector->base.base.id,
3872                               drm_get_connector_name(&connector->base));
3873
3874                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3875                      "wrong connector dpms state\n");
3876                 WARN(connector->base.encoder != &encoder->base,
3877                      "active connector not linked to encoder\n");
3878                 WARN(!encoder->connectors_active,
3879                      "encoder->connectors_active not set\n");
3880
3881                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3882                 WARN(!encoder_enabled, "encoder not enabled\n");
3883                 if (WARN_ON(!encoder->base.crtc))
3884                         return;
3885
3886                 crtc = encoder->base.crtc;
3887
3888                 WARN(!crtc->enabled, "crtc not enabled\n");
3889                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3890                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3891                      "encoder active on the wrong pipe\n");
3892         }
3893 }
3894
3895 /* Even simpler default implementation, if there's really no special case to
3896  * consider. */
3897 void intel_connector_dpms(struct drm_connector *connector, int mode)
3898 {
3899         struct intel_encoder *encoder = intel_attached_encoder(connector);
3900
3901         /* All the simple cases only support two dpms states. */
3902         if (mode != DRM_MODE_DPMS_ON)
3903                 mode = DRM_MODE_DPMS_OFF;
3904
3905         if (mode == connector->dpms)
3906                 return;
3907
3908         connector->dpms = mode;
3909
3910         /* Only need to change hw state when actually enabled */
3911         if (encoder->base.crtc)
3912                 intel_encoder_dpms(encoder, mode);
3913         else
3914                 WARN_ON(encoder->connectors_active != false);
3915
3916         intel_modeset_check_state(connector->dev);
3917 }
3918
3919 /* Simple connector->get_hw_state implementation for encoders that support only
3920  * one connector and no cloning and hence the encoder state determines the state
3921  * of the connector. */
3922 bool intel_connector_get_hw_state(struct intel_connector *connector)
3923 {
3924         enum pipe pipe = 0;
3925         struct intel_encoder *encoder = connector->encoder;
3926
3927         return encoder->get_hw_state(encoder, &pipe);
3928 }
3929
3930 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3931                                      struct intel_crtc_config *pipe_config)
3932 {
3933         struct drm_i915_private *dev_priv = dev->dev_private;
3934         struct intel_crtc *pipe_B_crtc =
3935                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3936
3937         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3938                       pipe_name(pipe), pipe_config->fdi_lanes);
3939         if (pipe_config->fdi_lanes > 4) {
3940                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3941                               pipe_name(pipe), pipe_config->fdi_lanes);
3942                 return false;
3943         }
3944
3945         if (IS_HASWELL(dev)) {
3946                 if (pipe_config->fdi_lanes > 2) {
3947                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3948                                       pipe_config->fdi_lanes);
3949                         return false;
3950                 } else {
3951                         return true;
3952                 }
3953         }
3954
3955         if (INTEL_INFO(dev)->num_pipes == 2)
3956                 return true;
3957
3958         /* Ivybridge 3 pipe is really complicated */
3959         switch (pipe) {
3960         case PIPE_A:
3961                 return true;
3962         case PIPE_B:
3963                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3964                     pipe_config->fdi_lanes > 2) {
3965                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3966                                       pipe_name(pipe), pipe_config->fdi_lanes);
3967                         return false;
3968                 }
3969                 return true;
3970         case PIPE_C:
3971                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3972                     pipe_B_crtc->config.fdi_lanes <= 2) {
3973                         if (pipe_config->fdi_lanes > 2) {
3974                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3975                                               pipe_name(pipe), pipe_config->fdi_lanes);
3976                                 return false;
3977                         }
3978                 } else {
3979                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3980                         return false;
3981                 }
3982                 return true;
3983         default:
3984                 BUG();
3985         }
3986 }
3987
3988 #define RETRY 1
3989 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3990                                        struct intel_crtc_config *pipe_config)
3991 {
3992         struct drm_device *dev = intel_crtc->base.dev;
3993         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3994         int lane, link_bw, fdi_dotclock;
3995         bool setup_ok, needs_recompute = false;
3996
3997 retry:
3998         /* FDI is a binary signal running at ~2.7GHz, encoding
3999          * each output octet as 10 bits. The actual frequency
4000          * is stored as a divider into a 100MHz clock, and the
4001          * mode pixel clock is stored in units of 1KHz.
4002          * Hence the bw of each lane in terms of the mode signal
4003          * is:
4004          */
4005         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4006
4007         fdi_dotclock = adjusted_mode->clock;
4008         fdi_dotclock /= pipe_config->pixel_multiplier;
4009
4010         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4011                                            pipe_config->pipe_bpp);
4012
4013         pipe_config->fdi_lanes = lane;
4014
4015         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4016                                link_bw, &pipe_config->fdi_m_n);
4017
4018         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4019                                             intel_crtc->pipe, pipe_config);
4020         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4021                 pipe_config->pipe_bpp -= 2*3;
4022                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4023                               pipe_config->pipe_bpp);
4024                 needs_recompute = true;
4025                 pipe_config->bw_constrained = true;
4026
4027                 goto retry;
4028         }
4029
4030         if (needs_recompute)
4031                 return RETRY;
4032
4033         return setup_ok ? 0 : -EINVAL;
4034 }
4035
4036 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4037                                    struct intel_crtc_config *pipe_config)
4038 {
4039         pipe_config->ips_enabled = i915_enable_ips &&
4040                                    hsw_crtc_supports_ips(crtc) &&
4041                                    pipe_config->pipe_bpp == 24;
4042 }
4043
4044 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4045                                      struct intel_crtc_config *pipe_config)
4046 {
4047         struct drm_device *dev = crtc->base.dev;
4048         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4049
4050         if (HAS_PCH_SPLIT(dev)) {
4051                 /* FDI link clock is fixed at 2.7G */
4052                 if (pipe_config->requested_mode.clock * 3
4053                     > IRONLAKE_FDI_FREQ * 4)
4054                         return -EINVAL;
4055         }
4056
4057         /* All interlaced capable intel hw wants timings in frames. Note though
4058          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4059          * timings, so we need to be careful not to clobber these.*/
4060         if (!pipe_config->timings_set)
4061                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4062
4063         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4064          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4065          */
4066         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4067                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4068                 return -EINVAL;
4069
4070         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4071                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4072         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4073                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4074                  * for lvds. */
4075                 pipe_config->pipe_bpp = 8*3;
4076         }
4077
4078         if (HAS_IPS(dev))
4079                 hsw_compute_ips_config(crtc, pipe_config);
4080
4081         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4082          * clock survives for now. */
4083         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4084                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4085
4086         if (pipe_config->has_pch_encoder)
4087                 return ironlake_fdi_compute_config(crtc, pipe_config);
4088
4089         return 0;
4090 }
4091
4092 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4093 {
4094         return 400000; /* FIXME */
4095 }
4096
4097 static int i945_get_display_clock_speed(struct drm_device *dev)
4098 {
4099         return 400000;
4100 }
4101
4102 static int i915_get_display_clock_speed(struct drm_device *dev)
4103 {
4104         return 333000;
4105 }
4106
4107 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4108 {
4109         return 200000;
4110 }
4111
4112 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4113 {
4114         u16 gcfgc = 0;
4115
4116         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4117
4118         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4119                 return 133000;
4120         else {
4121                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4122                 case GC_DISPLAY_CLOCK_333_MHZ:
4123                         return 333000;
4124                 default:
4125                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4126                         return 190000;
4127                 }
4128         }
4129 }
4130
4131 static int i865_get_display_clock_speed(struct drm_device *dev)
4132 {
4133         return 266000;
4134 }
4135
4136 static int i855_get_display_clock_speed(struct drm_device *dev)
4137 {
4138         u16 hpllcc = 0;
4139         /* Assume that the hardware is in the high speed state.  This
4140          * should be the default.
4141          */
4142         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4143         case GC_CLOCK_133_200:
4144         case GC_CLOCK_100_200:
4145                 return 200000;
4146         case GC_CLOCK_166_250:
4147                 return 250000;
4148         case GC_CLOCK_100_133:
4149                 return 133000;
4150         }
4151
4152         /* Shouldn't happen */
4153         return 0;
4154 }
4155
4156 static int i830_get_display_clock_speed(struct drm_device *dev)
4157 {
4158         return 133000;
4159 }
4160
4161 static void
4162 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4163 {
4164         while (*num > DATA_LINK_M_N_MASK ||
4165                *den > DATA_LINK_M_N_MASK) {
4166                 *num >>= 1;
4167                 *den >>= 1;
4168         }
4169 }
4170
4171 static void compute_m_n(unsigned int m, unsigned int n,
4172                         uint32_t *ret_m, uint32_t *ret_n)
4173 {
4174         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4175         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4176         intel_reduce_m_n_ratio(ret_m, ret_n);
4177 }
4178
4179 void
4180 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4181                        int pixel_clock, int link_clock,
4182                        struct intel_link_m_n *m_n)
4183 {
4184         m_n->tu = 64;
4185
4186         compute_m_n(bits_per_pixel * pixel_clock,
4187                     link_clock * nlanes * 8,
4188                     &m_n->gmch_m, &m_n->gmch_n);
4189
4190         compute_m_n(pixel_clock, link_clock,
4191                     &m_n->link_m, &m_n->link_n);
4192 }
4193
4194 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4195 {
4196         if (i915_panel_use_ssc >= 0)
4197                 return i915_panel_use_ssc != 0;
4198         return dev_priv->vbt.lvds_use_ssc
4199                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4200 }
4201
4202 static int vlv_get_refclk(struct drm_crtc *crtc)
4203 {
4204         struct drm_device *dev = crtc->dev;
4205         struct drm_i915_private *dev_priv = dev->dev_private;
4206         int refclk = 27000; /* for DP & HDMI */
4207
4208         return 100000; /* only one validated so far */
4209
4210         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4211                 refclk = 96000;
4212         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4213                 if (intel_panel_use_ssc(dev_priv))
4214                         refclk = 100000;
4215                 else
4216                         refclk = 96000;
4217         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4218                 refclk = 100000;
4219         }
4220
4221         return refclk;
4222 }
4223
4224 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4225 {
4226         struct drm_device *dev = crtc->dev;
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         int refclk;
4229
4230         if (IS_VALLEYVIEW(dev)) {
4231                 refclk = vlv_get_refclk(crtc);
4232         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4233             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4234                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4235                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4236                               refclk / 1000);
4237         } else if (!IS_GEN2(dev)) {
4238                 refclk = 96000;
4239         } else {
4240                 refclk = 48000;
4241         }
4242
4243         return refclk;
4244 }
4245
4246 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4247 {
4248         return (1 << dpll->n) << 16 | dpll->m2;
4249 }
4250
4251 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4252 {
4253         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4254 }
4255
4256 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4257                                      intel_clock_t *reduced_clock)
4258 {
4259         struct drm_device *dev = crtc->base.dev;
4260         struct drm_i915_private *dev_priv = dev->dev_private;
4261         int pipe = crtc->pipe;
4262         u32 fp, fp2 = 0;
4263
4264         if (IS_PINEVIEW(dev)) {
4265                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4266                 if (reduced_clock)
4267                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4268         } else {
4269                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4270                 if (reduced_clock)
4271                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4272         }
4273
4274         I915_WRITE(FP0(pipe), fp);
4275         crtc->config.dpll_hw_state.fp0 = fp;
4276
4277         crtc->lowfreq_avail = false;
4278         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4279             reduced_clock && i915_powersave) {
4280                 I915_WRITE(FP1(pipe), fp2);
4281                 crtc->config.dpll_hw_state.fp1 = fp2;
4282                 crtc->lowfreq_avail = true;
4283         } else {
4284                 I915_WRITE(FP1(pipe), fp);
4285                 crtc->config.dpll_hw_state.fp1 = fp;
4286         }
4287 }
4288
4289 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4290 {
4291         u32 reg_val;
4292
4293         /*
4294          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4295          * and set it to a reasonable value instead.
4296          */
4297         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4298         reg_val &= 0xffffff00;
4299         reg_val |= 0x00000030;
4300         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4301
4302         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4303         reg_val &= 0x8cffffff;
4304         reg_val = 0x8c000000;
4305         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4306
4307         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4308         reg_val &= 0xffffff00;
4309         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4310
4311         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4312         reg_val &= 0x00ffffff;
4313         reg_val |= 0xb0000000;
4314         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4315 }
4316
4317 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4318                                          struct intel_link_m_n *m_n)
4319 {
4320         struct drm_device *dev = crtc->base.dev;
4321         struct drm_i915_private *dev_priv = dev->dev_private;
4322         int pipe = crtc->pipe;
4323
4324         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4325         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4326         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4327         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4328 }
4329
4330 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4331                                          struct intel_link_m_n *m_n)
4332 {
4333         struct drm_device *dev = crtc->base.dev;
4334         struct drm_i915_private *dev_priv = dev->dev_private;
4335         int pipe = crtc->pipe;
4336         enum transcoder transcoder = crtc->config.cpu_transcoder;
4337
4338         if (INTEL_INFO(dev)->gen >= 5) {
4339                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4340                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4341                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4342                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4343         } else {
4344                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4345                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4346                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4347                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4348         }
4349 }
4350
4351 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4352 {
4353         if (crtc->config.has_pch_encoder)
4354                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4355         else
4356                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4357 }
4358
4359 static void vlv_update_pll(struct intel_crtc *crtc)
4360 {
4361         struct drm_device *dev = crtc->base.dev;
4362         struct drm_i915_private *dev_priv = dev->dev_private;
4363         struct intel_encoder *encoder;
4364         int pipe = crtc->pipe;
4365         u32 dpll, mdiv;
4366         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4367         bool is_hdmi;
4368         u32 coreclk, reg_val, dpll_md;
4369
4370         mutex_lock(&dev_priv->dpio_lock);
4371
4372         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4373
4374         bestn = crtc->config.dpll.n;
4375         bestm1 = crtc->config.dpll.m1;
4376         bestm2 = crtc->config.dpll.m2;
4377         bestp1 = crtc->config.dpll.p1;
4378         bestp2 = crtc->config.dpll.p2;
4379
4380         /* See eDP HDMI DPIO driver vbios notes doc */
4381
4382         /* PLL B needs special handling */
4383         if (pipe)
4384                 vlv_pllb_recal_opamp(dev_priv);
4385
4386         /* Set up Tx target for periodic Rcomp update */
4387         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4388
4389         /* Disable target IRef on PLL */
4390         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4391         reg_val &= 0x00ffffff;
4392         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4393
4394         /* Disable fast lock */
4395         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4396
4397         /* Set idtafcrecal before PLL is enabled */
4398         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4399         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4400         mdiv |= ((bestn << DPIO_N_SHIFT));
4401         mdiv |= (1 << DPIO_K_SHIFT);
4402
4403         /*
4404          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4405          * but we don't support that).
4406          * Note: don't use the DAC post divider as it seems unstable.
4407          */
4408         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4409         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4410
4411         mdiv |= DPIO_ENABLE_CALIBRATION;
4412         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4413
4414         /* Set HBR and RBR LPF coefficients */
4415         if (crtc->config.port_clock == 162000 ||
4416             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4417             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4418                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4419                                  0x005f0021);
4420         else
4421                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4422                                  0x00d0000f);
4423
4424         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4425             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4426                 /* Use SSC source */
4427                 if (!pipe)
4428                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4429                                          0x0df40000);
4430                 else
4431                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4432                                          0x0df70000);
4433         } else { /* HDMI or VGA */
4434                 /* Use bend source */
4435                 if (!pipe)
4436                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4437                                          0x0df70000);
4438                 else
4439                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4440                                          0x0df40000);
4441         }
4442
4443         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4444         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4445         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4446             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4447                 coreclk |= 0x01000000;
4448         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4449
4450         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4451
4452         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4453                 if (encoder->pre_pll_enable)
4454                         encoder->pre_pll_enable(encoder);
4455
4456         /* Enable DPIO clock input */
4457         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4458                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4459         if (pipe)
4460                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4461
4462         dpll |= DPLL_VCO_ENABLE;
4463         crtc->config.dpll_hw_state.dpll = dpll;
4464
4465         I915_WRITE(DPLL(pipe), dpll);
4466         POSTING_READ(DPLL(pipe));
4467         udelay(150);
4468
4469         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4470                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4471
4472         dpll_md = (crtc->config.pixel_multiplier - 1)
4473                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4474         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4475
4476         I915_WRITE(DPLL_MD(pipe), dpll_md);
4477         POSTING_READ(DPLL_MD(pipe));
4478
4479         if (crtc->config.has_dp_encoder)
4480                 intel_dp_set_m_n(crtc);
4481
4482         mutex_unlock(&dev_priv->dpio_lock);
4483 }
4484
4485 static void i9xx_update_pll(struct intel_crtc *crtc,
4486                             intel_clock_t *reduced_clock,
4487                             int num_connectors)
4488 {
4489         struct drm_device *dev = crtc->base.dev;
4490         struct drm_i915_private *dev_priv = dev->dev_private;
4491         struct intel_encoder *encoder;
4492         int pipe = crtc->pipe;
4493         u32 dpll;
4494         bool is_sdvo;
4495         struct dpll *clock = &crtc->config.dpll;
4496
4497         i9xx_update_pll_dividers(crtc, reduced_clock);
4498
4499         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4500                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4501
4502         dpll = DPLL_VGA_MODE_DIS;
4503
4504         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4505                 dpll |= DPLLB_MODE_LVDS;
4506         else
4507                 dpll |= DPLLB_MODE_DAC_SERIAL;
4508
4509         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4510                 dpll |= (crtc->config.pixel_multiplier - 1)
4511                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4512         }
4513
4514         if (is_sdvo)
4515                 dpll |= DPLL_DVO_HIGH_SPEED;
4516
4517         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4518                 dpll |= DPLL_DVO_HIGH_SPEED;
4519
4520         /* compute bitmask from p1 value */
4521         if (IS_PINEVIEW(dev))
4522                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4523         else {
4524                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4525                 if (IS_G4X(dev) && reduced_clock)
4526                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4527         }
4528         switch (clock->p2) {
4529         case 5:
4530                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4531                 break;
4532         case 7:
4533                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4534                 break;
4535         case 10:
4536                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4537                 break;
4538         case 14:
4539                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4540                 break;
4541         }
4542         if (INTEL_INFO(dev)->gen >= 4)
4543                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4544
4545         if (crtc->config.sdvo_tv_clock)
4546                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4547         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4548                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4549                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4550         else
4551                 dpll |= PLL_REF_INPUT_DREFCLK;
4552
4553         dpll |= DPLL_VCO_ENABLE;
4554         crtc->config.dpll_hw_state.dpll = dpll;
4555
4556         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4557         POSTING_READ(DPLL(pipe));
4558         udelay(150);
4559
4560         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4561                 if (encoder->pre_pll_enable)
4562                         encoder->pre_pll_enable(encoder);
4563
4564         if (crtc->config.has_dp_encoder)
4565                 intel_dp_set_m_n(crtc);
4566
4567         I915_WRITE(DPLL(pipe), dpll);
4568
4569         /* Wait for the clocks to stabilize. */
4570         POSTING_READ(DPLL(pipe));
4571         udelay(150);
4572
4573         if (INTEL_INFO(dev)->gen >= 4) {
4574                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4575                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4576                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4577
4578                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4579         } else {
4580                 /* The pixel multiplier can only be updated once the
4581                  * DPLL is enabled and the clocks are stable.
4582                  *
4583                  * So write it again.
4584                  */
4585                 I915_WRITE(DPLL(pipe), dpll);
4586         }
4587 }
4588
4589 static void i8xx_update_pll(struct intel_crtc *crtc,
4590                             intel_clock_t *reduced_clock,
4591                             int num_connectors)
4592 {
4593         struct drm_device *dev = crtc->base.dev;
4594         struct drm_i915_private *dev_priv = dev->dev_private;
4595         struct intel_encoder *encoder;
4596         int pipe = crtc->pipe;
4597         u32 dpll;
4598         struct dpll *clock = &crtc->config.dpll;
4599
4600         i9xx_update_pll_dividers(crtc, reduced_clock);
4601
4602         dpll = DPLL_VGA_MODE_DIS;
4603
4604         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4605                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4606         } else {
4607                 if (clock->p1 == 2)
4608                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4609                 else
4610                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4611                 if (clock->p2 == 4)
4612                         dpll |= PLL_P2_DIVIDE_BY_4;
4613         }
4614
4615         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4616                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4617                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4618         else
4619                 dpll |= PLL_REF_INPUT_DREFCLK;
4620
4621         dpll |= DPLL_VCO_ENABLE;
4622         crtc->config.dpll_hw_state.dpll = dpll;
4623
4624         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4625         POSTING_READ(DPLL(pipe));
4626         udelay(150);
4627
4628         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4629                 if (encoder->pre_pll_enable)
4630                         encoder->pre_pll_enable(encoder);
4631
4632         I915_WRITE(DPLL(pipe), dpll);
4633
4634         /* Wait for the clocks to stabilize. */
4635         POSTING_READ(DPLL(pipe));
4636         udelay(150);
4637
4638         /* The pixel multiplier can only be updated once the
4639          * DPLL is enabled and the clocks are stable.
4640          *
4641          * So write it again.
4642          */
4643         I915_WRITE(DPLL(pipe), dpll);
4644 }
4645
4646 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4647 {
4648         struct drm_device *dev = intel_crtc->base.dev;
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650         enum pipe pipe = intel_crtc->pipe;
4651         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4652         struct drm_display_mode *adjusted_mode =
4653                 &intel_crtc->config.adjusted_mode;
4654         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4655         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4656
4657         /* We need to be careful not to changed the adjusted mode, for otherwise
4658          * the hw state checker will get angry at the mismatch. */
4659         crtc_vtotal = adjusted_mode->crtc_vtotal;
4660         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4661
4662         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4663                 /* the chip adds 2 halflines automatically */
4664                 crtc_vtotal -= 1;
4665                 crtc_vblank_end -= 1;
4666                 vsyncshift = adjusted_mode->crtc_hsync_start
4667                              - adjusted_mode->crtc_htotal / 2;
4668         } else {
4669                 vsyncshift = 0;
4670         }
4671
4672         if (INTEL_INFO(dev)->gen > 3)
4673                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4674
4675         I915_WRITE(HTOTAL(cpu_transcoder),
4676                    (adjusted_mode->crtc_hdisplay - 1) |
4677                    ((adjusted_mode->crtc_htotal - 1) << 16));
4678         I915_WRITE(HBLANK(cpu_transcoder),
4679                    (adjusted_mode->crtc_hblank_start - 1) |
4680                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4681         I915_WRITE(HSYNC(cpu_transcoder),
4682                    (adjusted_mode->crtc_hsync_start - 1) |
4683                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4684
4685         I915_WRITE(VTOTAL(cpu_transcoder),
4686                    (adjusted_mode->crtc_vdisplay - 1) |
4687                    ((crtc_vtotal - 1) << 16));
4688         I915_WRITE(VBLANK(cpu_transcoder),
4689                    (adjusted_mode->crtc_vblank_start - 1) |
4690                    ((crtc_vblank_end - 1) << 16));
4691         I915_WRITE(VSYNC(cpu_transcoder),
4692                    (adjusted_mode->crtc_vsync_start - 1) |
4693                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4694
4695         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4696          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4697          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4698          * bits. */
4699         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4700             (pipe == PIPE_B || pipe == PIPE_C))
4701                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4702
4703         /* pipesrc controls the size that is scaled from, which should
4704          * always be the user's requested size.
4705          */
4706         I915_WRITE(PIPESRC(pipe),
4707                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4708 }
4709
4710 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4711                                    struct intel_crtc_config *pipe_config)
4712 {
4713         struct drm_device *dev = crtc->base.dev;
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4716         uint32_t tmp;
4717
4718         tmp = I915_READ(HTOTAL(cpu_transcoder));
4719         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4720         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4721         tmp = I915_READ(HBLANK(cpu_transcoder));
4722         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4723         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4724         tmp = I915_READ(HSYNC(cpu_transcoder));
4725         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4726         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4727
4728         tmp = I915_READ(VTOTAL(cpu_transcoder));
4729         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4730         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4731         tmp = I915_READ(VBLANK(cpu_transcoder));
4732         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4733         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4734         tmp = I915_READ(VSYNC(cpu_transcoder));
4735         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4736         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4737
4738         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4739                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4740                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4741                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4742         }
4743
4744         tmp = I915_READ(PIPESRC(crtc->pipe));
4745         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4746         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4747 }
4748
4749 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4750 {
4751         struct drm_device *dev = intel_crtc->base.dev;
4752         struct drm_i915_private *dev_priv = dev->dev_private;
4753         uint32_t pipeconf;
4754
4755         pipeconf = 0;
4756
4757         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4758                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4759                  * core speed.
4760                  *
4761                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4762                  * pipe == 0 check?
4763                  */
4764                 if (intel_crtc->config.requested_mode.clock >
4765                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4766                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4767         }
4768
4769         /* only g4x and later have fancy bpc/dither controls */
4770         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4771                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4772                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4773                         pipeconf |= PIPECONF_DITHER_EN |
4774                                     PIPECONF_DITHER_TYPE_SP;
4775
4776                 switch (intel_crtc->config.pipe_bpp) {
4777                 case 18:
4778                         pipeconf |= PIPECONF_6BPC;
4779                         break;
4780                 case 24:
4781                         pipeconf |= PIPECONF_8BPC;
4782                         break;
4783                 case 30:
4784                         pipeconf |= PIPECONF_10BPC;
4785                         break;
4786                 default:
4787                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4788                         BUG();
4789                 }
4790         }
4791
4792         if (HAS_PIPE_CXSR(dev)) {
4793                 if (intel_crtc->lowfreq_avail) {
4794                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4795                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4796                 } else {
4797                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4798                 }
4799         }
4800
4801         if (!IS_GEN2(dev) &&
4802             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4803                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4804         else
4805                 pipeconf |= PIPECONF_PROGRESSIVE;
4806
4807         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4808                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4809
4810         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4811         POSTING_READ(PIPECONF(intel_crtc->pipe));
4812 }
4813
4814 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4815                               int x, int y,
4816                               struct drm_framebuffer *fb)
4817 {
4818         struct drm_device *dev = crtc->dev;
4819         struct drm_i915_private *dev_priv = dev->dev_private;
4820         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4821         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4822         int pipe = intel_crtc->pipe;
4823         int plane = intel_crtc->plane;
4824         int refclk, num_connectors = 0;
4825         intel_clock_t clock, reduced_clock;
4826         u32 dspcntr;
4827         bool ok, has_reduced_clock = false;
4828         bool is_lvds = false;
4829         struct intel_encoder *encoder;
4830         const intel_limit_t *limit;
4831         int ret;
4832
4833         for_each_encoder_on_crtc(dev, crtc, encoder) {
4834                 switch (encoder->type) {
4835                 case INTEL_OUTPUT_LVDS:
4836                         is_lvds = true;
4837                         break;
4838                 }
4839
4840                 num_connectors++;
4841         }
4842
4843         refclk = i9xx_get_refclk(crtc, num_connectors);
4844
4845         /*
4846          * Returns a set of divisors for the desired target clock with the given
4847          * refclk, or FALSE.  The returned values represent the clock equation:
4848          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4849          */
4850         limit = intel_limit(crtc, refclk);
4851         ok = dev_priv->display.find_dpll(limit, crtc,
4852                                          intel_crtc->config.port_clock,
4853                                          refclk, NULL, &clock);
4854         if (!ok && !intel_crtc->config.clock_set) {
4855                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4856                 return -EINVAL;
4857         }
4858
4859         /* Ensure that the cursor is valid for the new mode before changing... */
4860         intel_crtc_update_cursor(crtc, true);
4861
4862         if (is_lvds && dev_priv->lvds_downclock_avail) {
4863                 /*
4864                  * Ensure we match the reduced clock's P to the target clock.
4865                  * If the clocks don't match, we can't switch the display clock
4866                  * by using the FP0/FP1. In such case we will disable the LVDS
4867                  * downclock feature.
4868                 */
4869                 has_reduced_clock =
4870                         dev_priv->display.find_dpll(limit, crtc,
4871                                                     dev_priv->lvds_downclock,
4872                                                     refclk, &clock,
4873                                                     &reduced_clock);
4874         }
4875         /* Compat-code for transition, will disappear. */
4876         if (!intel_crtc->config.clock_set) {
4877                 intel_crtc->config.dpll.n = clock.n;
4878                 intel_crtc->config.dpll.m1 = clock.m1;
4879                 intel_crtc->config.dpll.m2 = clock.m2;
4880                 intel_crtc->config.dpll.p1 = clock.p1;
4881                 intel_crtc->config.dpll.p2 = clock.p2;
4882         }
4883
4884         if (IS_GEN2(dev))
4885                 i8xx_update_pll(intel_crtc,
4886                                 has_reduced_clock ? &reduced_clock : NULL,
4887                                 num_connectors);
4888         else if (IS_VALLEYVIEW(dev))
4889                 vlv_update_pll(intel_crtc);
4890         else
4891                 i9xx_update_pll(intel_crtc,
4892                                 has_reduced_clock ? &reduced_clock : NULL,
4893                                 num_connectors);
4894
4895         /* Set up the display plane register */
4896         dspcntr = DISPPLANE_GAMMA_ENABLE;
4897
4898         if (!IS_VALLEYVIEW(dev)) {
4899                 if (pipe == 0)
4900                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4901                 else
4902                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4903         }
4904
4905         intel_set_pipe_timings(intel_crtc);
4906
4907         /* pipesrc and dspsize control the size that is scaled from,
4908          * which should always be the user's requested size.
4909          */
4910         I915_WRITE(DSPSIZE(plane),
4911                    ((mode->vdisplay - 1) << 16) |
4912                    (mode->hdisplay - 1));
4913         I915_WRITE(DSPPOS(plane), 0);
4914
4915         i9xx_set_pipeconf(intel_crtc);
4916
4917         I915_WRITE(DSPCNTR(plane), dspcntr);
4918         POSTING_READ(DSPCNTR(plane));
4919
4920         ret = intel_pipe_set_base(crtc, x, y, fb);
4921
4922         intel_update_watermarks(dev);
4923
4924         return ret;
4925 }
4926
4927 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4928                                  struct intel_crtc_config *pipe_config)
4929 {
4930         struct drm_device *dev = crtc->base.dev;
4931         struct drm_i915_private *dev_priv = dev->dev_private;
4932         uint32_t tmp;
4933
4934         tmp = I915_READ(PFIT_CONTROL);
4935
4936         if (INTEL_INFO(dev)->gen < 4) {
4937                 if (crtc->pipe != PIPE_B)
4938                         return;
4939
4940                 /* gen2/3 store dither state in pfit control, needs to match */
4941                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4942         } else {
4943                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4944                         return;
4945         }
4946
4947         if (!(tmp & PFIT_ENABLE))
4948                 return;
4949
4950         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4951         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4952         if (INTEL_INFO(dev)->gen < 5)
4953                 pipe_config->gmch_pfit.lvds_border_bits =
4954                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4955 }
4956
4957 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4958                                  struct intel_crtc_config *pipe_config)
4959 {
4960         struct drm_device *dev = crtc->base.dev;
4961         struct drm_i915_private *dev_priv = dev->dev_private;
4962         uint32_t tmp;
4963
4964         pipe_config->cpu_transcoder = crtc->pipe;
4965         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4966
4967         tmp = I915_READ(PIPECONF(crtc->pipe));
4968         if (!(tmp & PIPECONF_ENABLE))
4969                 return false;
4970
4971         intel_get_pipe_timings(crtc, pipe_config);
4972
4973         i9xx_get_pfit_config(crtc, pipe_config);
4974
4975         if (INTEL_INFO(dev)->gen >= 4) {
4976                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4977                 pipe_config->pixel_multiplier =
4978                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4979                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4980                 pipe_config->dpll_hw_state.dpll_md = tmp;
4981         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4982                 tmp = I915_READ(DPLL(crtc->pipe));
4983                 pipe_config->pixel_multiplier =
4984                         ((tmp & SDVO_MULTIPLIER_MASK)
4985                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4986         } else {
4987                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4988                  * port and will be fixed up in the encoder->get_config
4989                  * function. */
4990                 pipe_config->pixel_multiplier = 1;
4991         }
4992         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4993         if (!IS_VALLEYVIEW(dev)) {
4994                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
4995                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
4996         }
4997
4998         return true;
4999 }
5000
5001 static void ironlake_init_pch_refclk(struct drm_device *dev)
5002 {
5003         struct drm_i915_private *dev_priv = dev->dev_private;
5004         struct drm_mode_config *mode_config = &dev->mode_config;
5005         struct intel_encoder *encoder;
5006         u32 val, final;
5007         bool has_lvds = false;
5008         bool has_cpu_edp = false;
5009         bool has_panel = false;
5010         bool has_ck505 = false;
5011         bool can_ssc = false;
5012
5013         /* We need to take the global config into account */
5014         list_for_each_entry(encoder, &mode_config->encoder_list,
5015                             base.head) {
5016                 switch (encoder->type) {
5017                 case INTEL_OUTPUT_LVDS:
5018                         has_panel = true;
5019                         has_lvds = true;
5020                         break;
5021                 case INTEL_OUTPUT_EDP:
5022                         has_panel = true;
5023                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5024                                 has_cpu_edp = true;
5025                         break;
5026                 }
5027         }
5028
5029         if (HAS_PCH_IBX(dev)) {
5030                 has_ck505 = dev_priv->vbt.display_clock_mode;
5031                 can_ssc = has_ck505;
5032         } else {
5033                 has_ck505 = false;
5034                 can_ssc = true;
5035         }
5036
5037         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5038                       has_panel, has_lvds, has_ck505);
5039
5040         /* Ironlake: try to setup display ref clock before DPLL
5041          * enabling. This is only under driver's control after
5042          * PCH B stepping, previous chipset stepping should be
5043          * ignoring this setting.
5044          */
5045         val = I915_READ(PCH_DREF_CONTROL);
5046
5047         /* As we must carefully and slowly disable/enable each source in turn,
5048          * compute the final state we want first and check if we need to
5049          * make any changes at all.
5050          */
5051         final = val;
5052         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5053         if (has_ck505)
5054                 final |= DREF_NONSPREAD_CK505_ENABLE;
5055         else
5056                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5057
5058         final &= ~DREF_SSC_SOURCE_MASK;
5059         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5060         final &= ~DREF_SSC1_ENABLE;
5061
5062         if (has_panel) {
5063                 final |= DREF_SSC_SOURCE_ENABLE;
5064
5065                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5066                         final |= DREF_SSC1_ENABLE;
5067
5068                 if (has_cpu_edp) {
5069                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5070                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5071                         else
5072                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5073                 } else
5074                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5075         } else {
5076                 final |= DREF_SSC_SOURCE_DISABLE;
5077                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5078         }
5079
5080         if (final == val)
5081                 return;
5082
5083         /* Always enable nonspread source */
5084         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5085
5086         if (has_ck505)
5087                 val |= DREF_NONSPREAD_CK505_ENABLE;
5088         else
5089                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5090
5091         if (has_panel) {
5092                 val &= ~DREF_SSC_SOURCE_MASK;
5093                 val |= DREF_SSC_SOURCE_ENABLE;
5094
5095                 /* SSC must be turned on before enabling the CPU output  */
5096                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5097                         DRM_DEBUG_KMS("Using SSC on panel\n");
5098                         val |= DREF_SSC1_ENABLE;
5099                 } else
5100                         val &= ~DREF_SSC1_ENABLE;
5101
5102                 /* Get SSC going before enabling the outputs */
5103                 I915_WRITE(PCH_DREF_CONTROL, val);
5104                 POSTING_READ(PCH_DREF_CONTROL);
5105                 udelay(200);
5106
5107                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5108
5109                 /* Enable CPU source on CPU attached eDP */
5110                 if (has_cpu_edp) {
5111                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5112                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5113                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5114                         }
5115                         else
5116                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5117                 } else
5118                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5119
5120                 I915_WRITE(PCH_DREF_CONTROL, val);
5121                 POSTING_READ(PCH_DREF_CONTROL);
5122                 udelay(200);
5123         } else {
5124                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5125
5126                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5127
5128                 /* Turn off CPU output */
5129                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5130
5131                 I915_WRITE(PCH_DREF_CONTROL, val);
5132                 POSTING_READ(PCH_DREF_CONTROL);
5133                 udelay(200);
5134
5135                 /* Turn off the SSC source */
5136                 val &= ~DREF_SSC_SOURCE_MASK;
5137                 val |= DREF_SSC_SOURCE_DISABLE;
5138
5139                 /* Turn off SSC1 */
5140                 val &= ~DREF_SSC1_ENABLE;
5141
5142                 I915_WRITE(PCH_DREF_CONTROL, val);
5143                 POSTING_READ(PCH_DREF_CONTROL);
5144                 udelay(200);
5145         }
5146
5147         BUG_ON(val != final);
5148 }
5149
5150 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5151 static void lpt_init_pch_refclk(struct drm_device *dev)
5152 {
5153         struct drm_i915_private *dev_priv = dev->dev_private;
5154         struct drm_mode_config *mode_config = &dev->mode_config;
5155         struct intel_encoder *encoder;
5156         bool has_vga = false;
5157         bool is_sdv = false;
5158         u32 tmp;
5159
5160         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5161                 switch (encoder->type) {
5162                 case INTEL_OUTPUT_ANALOG:
5163                         has_vga = true;
5164                         break;
5165                 }
5166         }
5167
5168         if (!has_vga)
5169                 return;
5170
5171         mutex_lock(&dev_priv->dpio_lock);
5172
5173         /* XXX: Rip out SDV support once Haswell ships for real. */
5174         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5175                 is_sdv = true;
5176
5177         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5178         tmp &= ~SBI_SSCCTL_DISABLE;
5179         tmp |= SBI_SSCCTL_PATHALT;
5180         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5181
5182         udelay(24);
5183
5184         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5185         tmp &= ~SBI_SSCCTL_PATHALT;
5186         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5187
5188         if (!is_sdv) {
5189                 tmp = I915_READ(SOUTH_CHICKEN2);
5190                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5191                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5192
5193                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5194                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5195                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5196
5197                 tmp = I915_READ(SOUTH_CHICKEN2);
5198                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5199                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5200
5201                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5202                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5203                                        100))
5204                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5205         }
5206
5207         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5208         tmp &= ~(0xFF << 24);
5209         tmp |= (0x12 << 24);
5210         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5211
5212         if (is_sdv) {
5213                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5214                 tmp |= 0x7FFF;
5215                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5216         }
5217
5218         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5219         tmp |= (1 << 11);
5220         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5221
5222         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5223         tmp |= (1 << 11);
5224         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5225
5226         if (is_sdv) {
5227                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5228                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5229                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5230
5231                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5232                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5233                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5234
5235                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5236                 tmp |= (0x3F << 8);
5237                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5238
5239                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5240                 tmp |= (0x3F << 8);
5241                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5242         }
5243
5244         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5245         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5246         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5247
5248         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5249         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5250         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5251
5252         if (!is_sdv) {
5253                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5254                 tmp &= ~(7 << 13);
5255                 tmp |= (5 << 13);
5256                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5257
5258                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5259                 tmp &= ~(7 << 13);
5260                 tmp |= (5 << 13);
5261                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5262         }
5263
5264         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5265         tmp &= ~0xFF;
5266         tmp |= 0x1C;
5267         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5268
5269         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5270         tmp &= ~0xFF;
5271         tmp |= 0x1C;
5272         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5273
5274         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5275         tmp &= ~(0xFF << 16);
5276         tmp |= (0x1C << 16);
5277         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5278
5279         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5280         tmp &= ~(0xFF << 16);
5281         tmp |= (0x1C << 16);
5282         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5283
5284         if (!is_sdv) {
5285                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5286                 tmp |= (1 << 27);
5287                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5288
5289                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5290                 tmp |= (1 << 27);
5291                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5292
5293                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5294                 tmp &= ~(0xF << 28);
5295                 tmp |= (4 << 28);
5296                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5297
5298                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5299                 tmp &= ~(0xF << 28);
5300                 tmp |= (4 << 28);
5301                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5302         }
5303
5304         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5305         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5306         tmp |= SBI_DBUFF0_ENABLE;
5307         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5308
5309         mutex_unlock(&dev_priv->dpio_lock);
5310 }
5311
5312 /*
5313  * Initialize reference clocks when the driver loads
5314  */
5315 void intel_init_pch_refclk(struct drm_device *dev)
5316 {
5317         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5318                 ironlake_init_pch_refclk(dev);
5319         else if (HAS_PCH_LPT(dev))
5320                 lpt_init_pch_refclk(dev);
5321 }
5322
5323 static int ironlake_get_refclk(struct drm_crtc *crtc)
5324 {
5325         struct drm_device *dev = crtc->dev;
5326         struct drm_i915_private *dev_priv = dev->dev_private;
5327         struct intel_encoder *encoder;
5328         int num_connectors = 0;
5329         bool is_lvds = false;
5330
5331         for_each_encoder_on_crtc(dev, crtc, encoder) {
5332                 switch (encoder->type) {
5333                 case INTEL_OUTPUT_LVDS:
5334                         is_lvds = true;
5335                         break;
5336                 }
5337                 num_connectors++;
5338         }
5339
5340         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5341                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5342                               dev_priv->vbt.lvds_ssc_freq);
5343                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5344         }
5345
5346         return 120000;
5347 }
5348
5349 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5350 {
5351         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5352         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5353         int pipe = intel_crtc->pipe;
5354         uint32_t val;
5355
5356         val = 0;
5357
5358         switch (intel_crtc->config.pipe_bpp) {
5359         case 18:
5360                 val |= PIPECONF_6BPC;
5361                 break;
5362         case 24:
5363                 val |= PIPECONF_8BPC;
5364                 break;
5365         case 30:
5366                 val |= PIPECONF_10BPC;
5367                 break;
5368         case 36:
5369                 val |= PIPECONF_12BPC;
5370                 break;
5371         default:
5372                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5373                 BUG();
5374         }
5375
5376         if (intel_crtc->config.dither)
5377                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5378
5379         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5380                 val |= PIPECONF_INTERLACED_ILK;
5381         else
5382                 val |= PIPECONF_PROGRESSIVE;
5383
5384         if (intel_crtc->config.limited_color_range)
5385                 val |= PIPECONF_COLOR_RANGE_SELECT;
5386
5387         I915_WRITE(PIPECONF(pipe), val);
5388         POSTING_READ(PIPECONF(pipe));
5389 }
5390
5391 /*
5392  * Set up the pipe CSC unit.
5393  *
5394  * Currently only full range RGB to limited range RGB conversion
5395  * is supported, but eventually this should handle various
5396  * RGB<->YCbCr scenarios as well.
5397  */
5398 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5399 {
5400         struct drm_device *dev = crtc->dev;
5401         struct drm_i915_private *dev_priv = dev->dev_private;
5402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5403         int pipe = intel_crtc->pipe;
5404         uint16_t coeff = 0x7800; /* 1.0 */
5405
5406         /*
5407          * TODO: Check what kind of values actually come out of the pipe
5408          * with these coeff/postoff values and adjust to get the best
5409          * accuracy. Perhaps we even need to take the bpc value into
5410          * consideration.
5411          */
5412
5413         if (intel_crtc->config.limited_color_range)
5414                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5415
5416         /*
5417          * GY/GU and RY/RU should be the other way around according
5418          * to BSpec, but reality doesn't agree. Just set them up in
5419          * a way that results in the correct picture.
5420          */
5421         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5422         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5423
5424         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5425         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5426
5427         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5428         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5429
5430         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5431         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5432         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5433
5434         if (INTEL_INFO(dev)->gen > 6) {
5435                 uint16_t postoff = 0;
5436
5437                 if (intel_crtc->config.limited_color_range)
5438                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5439
5440                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5441                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5442                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5443
5444                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5445         } else {
5446                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5447
5448                 if (intel_crtc->config.limited_color_range)
5449                         mode |= CSC_BLACK_SCREEN_OFFSET;
5450
5451                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5452         }
5453 }
5454
5455 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5456 {
5457         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5459         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5460         uint32_t val;
5461
5462         val = 0;
5463
5464         if (intel_crtc->config.dither)
5465                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5466
5467         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5468                 val |= PIPECONF_INTERLACED_ILK;
5469         else
5470                 val |= PIPECONF_PROGRESSIVE;
5471
5472         I915_WRITE(PIPECONF(cpu_transcoder), val);
5473         POSTING_READ(PIPECONF(cpu_transcoder));
5474
5475         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5476         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5477 }
5478
5479 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5480                                     intel_clock_t *clock,
5481                                     bool *has_reduced_clock,
5482                                     intel_clock_t *reduced_clock)
5483 {
5484         struct drm_device *dev = crtc->dev;
5485         struct drm_i915_private *dev_priv = dev->dev_private;
5486         struct intel_encoder *intel_encoder;
5487         int refclk;
5488         const intel_limit_t *limit;
5489         bool ret, is_lvds = false;
5490
5491         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5492                 switch (intel_encoder->type) {
5493                 case INTEL_OUTPUT_LVDS:
5494                         is_lvds = true;
5495                         break;
5496                 }
5497         }
5498
5499         refclk = ironlake_get_refclk(crtc);
5500
5501         /*
5502          * Returns a set of divisors for the desired target clock with the given
5503          * refclk, or FALSE.  The returned values represent the clock equation:
5504          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5505          */
5506         limit = intel_limit(crtc, refclk);
5507         ret = dev_priv->display.find_dpll(limit, crtc,
5508                                           to_intel_crtc(crtc)->config.port_clock,
5509                                           refclk, NULL, clock);
5510         if (!ret)
5511                 return false;
5512
5513         if (is_lvds && dev_priv->lvds_downclock_avail) {
5514                 /*
5515                  * Ensure we match the reduced clock's P to the target clock.
5516                  * If the clocks don't match, we can't switch the display clock
5517                  * by using the FP0/FP1. In such case we will disable the LVDS
5518                  * downclock feature.
5519                 */
5520                 *has_reduced_clock =
5521                         dev_priv->display.find_dpll(limit, crtc,
5522                                                     dev_priv->lvds_downclock,
5523                                                     refclk, clock,
5524                                                     reduced_clock);
5525         }
5526
5527         return true;
5528 }
5529
5530 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5531 {
5532         struct drm_i915_private *dev_priv = dev->dev_private;
5533         uint32_t temp;
5534
5535         temp = I915_READ(SOUTH_CHICKEN1);
5536         if (temp & FDI_BC_BIFURCATION_SELECT)
5537                 return;
5538
5539         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5540         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5541
5542         temp |= FDI_BC_BIFURCATION_SELECT;
5543         DRM_DEBUG_KMS("enabling fdi C rx\n");
5544         I915_WRITE(SOUTH_CHICKEN1, temp);
5545         POSTING_READ(SOUTH_CHICKEN1);
5546 }
5547
5548 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5549 {
5550         struct drm_device *dev = intel_crtc->base.dev;
5551         struct drm_i915_private *dev_priv = dev->dev_private;
5552
5553         switch (intel_crtc->pipe) {
5554         case PIPE_A:
5555                 break;
5556         case PIPE_B:
5557                 if (intel_crtc->config.fdi_lanes > 2)
5558                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5559                 else
5560                         cpt_enable_fdi_bc_bifurcation(dev);
5561
5562                 break;
5563         case PIPE_C:
5564                 cpt_enable_fdi_bc_bifurcation(dev);
5565
5566                 break;
5567         default:
5568                 BUG();
5569         }
5570 }
5571
5572 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5573 {
5574         /*
5575          * Account for spread spectrum to avoid
5576          * oversubscribing the link. Max center spread
5577          * is 2.5%; use 5% for safety's sake.
5578          */
5579         u32 bps = target_clock * bpp * 21 / 20;
5580         return bps / (link_bw * 8) + 1;
5581 }
5582
5583 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5584 {
5585         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5586 }
5587
5588 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5589                                       u32 *fp,
5590                                       intel_clock_t *reduced_clock, u32 *fp2)
5591 {
5592         struct drm_crtc *crtc = &intel_crtc->base;
5593         struct drm_device *dev = crtc->dev;
5594         struct drm_i915_private *dev_priv = dev->dev_private;
5595         struct intel_encoder *intel_encoder;
5596         uint32_t dpll;
5597         int factor, num_connectors = 0;
5598         bool is_lvds = false, is_sdvo = false;
5599
5600         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5601                 switch (intel_encoder->type) {
5602                 case INTEL_OUTPUT_LVDS:
5603                         is_lvds = true;
5604                         break;
5605                 case INTEL_OUTPUT_SDVO:
5606                 case INTEL_OUTPUT_HDMI:
5607                         is_sdvo = true;
5608                         break;
5609                 }
5610
5611                 num_connectors++;
5612         }
5613
5614         /* Enable autotuning of the PLL clock (if permissible) */
5615         factor = 21;
5616         if (is_lvds) {
5617                 if ((intel_panel_use_ssc(dev_priv) &&
5618                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5619                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5620                         factor = 25;
5621         } else if (intel_crtc->config.sdvo_tv_clock)
5622                 factor = 20;
5623
5624         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5625                 *fp |= FP_CB_TUNE;
5626
5627         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5628                 *fp2 |= FP_CB_TUNE;
5629
5630         dpll = 0;
5631
5632         if (is_lvds)
5633                 dpll |= DPLLB_MODE_LVDS;
5634         else
5635                 dpll |= DPLLB_MODE_DAC_SERIAL;
5636
5637         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5638                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5639
5640         if (is_sdvo)
5641                 dpll |= DPLL_DVO_HIGH_SPEED;
5642         if (intel_crtc->config.has_dp_encoder)
5643                 dpll |= DPLL_DVO_HIGH_SPEED;
5644
5645         /* compute bitmask from p1 value */
5646         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5647         /* also FPA1 */
5648         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5649
5650         switch (intel_crtc->config.dpll.p2) {
5651         case 5:
5652                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5653                 break;
5654         case 7:
5655                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5656                 break;
5657         case 10:
5658                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5659                 break;
5660         case 14:
5661                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5662                 break;
5663         }
5664
5665         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5666                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5667         else
5668                 dpll |= PLL_REF_INPUT_DREFCLK;
5669
5670         return dpll | DPLL_VCO_ENABLE;
5671 }
5672
5673 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5674                                   int x, int y,
5675                                   struct drm_framebuffer *fb)
5676 {
5677         struct drm_device *dev = crtc->dev;
5678         struct drm_i915_private *dev_priv = dev->dev_private;
5679         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5680         int pipe = intel_crtc->pipe;
5681         int plane = intel_crtc->plane;
5682         int num_connectors = 0;
5683         intel_clock_t clock, reduced_clock;
5684         u32 dpll = 0, fp = 0, fp2 = 0;
5685         bool ok, has_reduced_clock = false;
5686         bool is_lvds = false;
5687         struct intel_encoder *encoder;
5688         struct intel_shared_dpll *pll;
5689         int ret;
5690
5691         for_each_encoder_on_crtc(dev, crtc, encoder) {
5692                 switch (encoder->type) {
5693                 case INTEL_OUTPUT_LVDS:
5694                         is_lvds = true;
5695                         break;
5696                 }
5697
5698                 num_connectors++;
5699         }
5700
5701         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5702              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5703
5704         ok = ironlake_compute_clocks(crtc, &clock,
5705                                      &has_reduced_clock, &reduced_clock);
5706         if (!ok && !intel_crtc->config.clock_set) {
5707                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5708                 return -EINVAL;
5709         }
5710         /* Compat-code for transition, will disappear. */
5711         if (!intel_crtc->config.clock_set) {
5712                 intel_crtc->config.dpll.n = clock.n;
5713                 intel_crtc->config.dpll.m1 = clock.m1;
5714                 intel_crtc->config.dpll.m2 = clock.m2;
5715                 intel_crtc->config.dpll.p1 = clock.p1;
5716                 intel_crtc->config.dpll.p2 = clock.p2;
5717         }
5718
5719         /* Ensure that the cursor is valid for the new mode before changing... */
5720         intel_crtc_update_cursor(crtc, true);
5721
5722         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5723         if (intel_crtc->config.has_pch_encoder) {
5724                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5725                 if (has_reduced_clock)
5726                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5727
5728                 dpll = ironlake_compute_dpll(intel_crtc,
5729                                              &fp, &reduced_clock,
5730                                              has_reduced_clock ? &fp2 : NULL);
5731
5732                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5733                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5734                 if (has_reduced_clock)
5735                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5736                 else
5737                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5738
5739                 pll = intel_get_shared_dpll(intel_crtc);
5740                 if (pll == NULL) {
5741                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5742                                          pipe_name(pipe));
5743                         return -EINVAL;
5744                 }
5745         } else
5746                 intel_put_shared_dpll(intel_crtc);
5747
5748         if (intel_crtc->config.has_dp_encoder)
5749                 intel_dp_set_m_n(intel_crtc);
5750
5751         if (is_lvds && has_reduced_clock && i915_powersave)
5752                 intel_crtc->lowfreq_avail = true;
5753         else
5754                 intel_crtc->lowfreq_avail = false;
5755
5756         if (intel_crtc->config.has_pch_encoder) {
5757                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5758
5759         }
5760
5761         intel_set_pipe_timings(intel_crtc);
5762
5763         if (intel_crtc->config.has_pch_encoder) {
5764                 intel_cpu_transcoder_set_m_n(intel_crtc,
5765                                              &intel_crtc->config.fdi_m_n);
5766         }
5767
5768         if (IS_IVYBRIDGE(dev))
5769                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5770
5771         ironlake_set_pipeconf(crtc);
5772
5773         /* Set up the display plane register */
5774         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5775         POSTING_READ(DSPCNTR(plane));
5776
5777         ret = intel_pipe_set_base(crtc, x, y, fb);
5778
5779         intel_update_watermarks(dev);
5780
5781         return ret;
5782 }
5783
5784 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5785                                         struct intel_crtc_config *pipe_config)
5786 {
5787         struct drm_device *dev = crtc->base.dev;
5788         struct drm_i915_private *dev_priv = dev->dev_private;
5789         enum transcoder transcoder = pipe_config->cpu_transcoder;
5790
5791         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5792         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5793         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5794                                         & ~TU_SIZE_MASK;
5795         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5796         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5797                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5798 }
5799
5800 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5801                                      struct intel_crtc_config *pipe_config)
5802 {
5803         struct drm_device *dev = crtc->base.dev;
5804         struct drm_i915_private *dev_priv = dev->dev_private;
5805         uint32_t tmp;
5806
5807         tmp = I915_READ(PF_CTL(crtc->pipe));
5808
5809         if (tmp & PF_ENABLE) {
5810                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5811                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5812
5813                 /* We currently do not free assignements of panel fitters on
5814                  * ivb/hsw (since we don't use the higher upscaling modes which
5815                  * differentiates them) so just WARN about this case for now. */
5816                 if (IS_GEN7(dev)) {
5817                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5818                                 PF_PIPE_SEL_IVB(crtc->pipe));
5819                 }
5820         }
5821 }
5822
5823 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5824                                      struct intel_crtc_config *pipe_config)
5825 {
5826         struct drm_device *dev = crtc->base.dev;
5827         struct drm_i915_private *dev_priv = dev->dev_private;
5828         uint32_t tmp;
5829
5830         pipe_config->cpu_transcoder = crtc->pipe;
5831         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5832
5833         tmp = I915_READ(PIPECONF(crtc->pipe));
5834         if (!(tmp & PIPECONF_ENABLE))
5835                 return false;
5836
5837         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5838                 struct intel_shared_dpll *pll;
5839
5840                 pipe_config->has_pch_encoder = true;
5841
5842                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5843                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5844                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5845
5846                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5847
5848                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5849                  * since we don't have state tracking for pch clocks yet. */
5850                 pipe_config->pixel_multiplier = 1;
5851
5852                 if (HAS_PCH_IBX(dev_priv->dev)) {
5853                         pipe_config->shared_dpll = crtc->pipe;
5854                 } else {
5855                         tmp = I915_READ(PCH_DPLL_SEL);
5856                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5857                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5858                         else
5859                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5860                 }
5861
5862                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5863
5864                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5865                                            &pipe_config->dpll_hw_state));
5866         } else {
5867                 pipe_config->pixel_multiplier = 1;
5868         }
5869
5870         intel_get_pipe_timings(crtc, pipe_config);
5871
5872         ironlake_get_pfit_config(crtc, pipe_config);
5873
5874         return true;
5875 }
5876
5877 static void haswell_modeset_global_resources(struct drm_device *dev)
5878 {
5879         bool enable = false;
5880         struct intel_crtc *crtc;
5881
5882         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5883                 if (!crtc->base.enabled)
5884                         continue;
5885
5886                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5887                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5888                         enable = true;
5889         }
5890
5891         intel_set_power_well(dev, enable);
5892 }
5893
5894 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5895                                  int x, int y,
5896                                  struct drm_framebuffer *fb)
5897 {
5898         struct drm_device *dev = crtc->dev;
5899         struct drm_i915_private *dev_priv = dev->dev_private;
5900         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5901         int plane = intel_crtc->plane;
5902         int ret;
5903
5904         if (!intel_ddi_pll_mode_set(crtc))
5905                 return -EINVAL;
5906
5907         /* Ensure that the cursor is valid for the new mode before changing... */
5908         intel_crtc_update_cursor(crtc, true);
5909
5910         if (intel_crtc->config.has_dp_encoder)
5911                 intel_dp_set_m_n(intel_crtc);
5912
5913         intel_crtc->lowfreq_avail = false;
5914
5915         intel_set_pipe_timings(intel_crtc);
5916
5917         if (intel_crtc->config.has_pch_encoder) {
5918                 intel_cpu_transcoder_set_m_n(intel_crtc,
5919                                              &intel_crtc->config.fdi_m_n);
5920         }
5921
5922         haswell_set_pipeconf(crtc);
5923
5924         intel_set_pipe_csc(crtc);
5925
5926         /* Set up the display plane register */
5927         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5928         POSTING_READ(DSPCNTR(plane));
5929
5930         ret = intel_pipe_set_base(crtc, x, y, fb);
5931
5932         intel_update_watermarks(dev);
5933
5934         return ret;
5935 }
5936
5937 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5938                                     struct intel_crtc_config *pipe_config)
5939 {
5940         struct drm_device *dev = crtc->base.dev;
5941         struct drm_i915_private *dev_priv = dev->dev_private;
5942         enum intel_display_power_domain pfit_domain;
5943         uint32_t tmp;
5944
5945         pipe_config->cpu_transcoder = crtc->pipe;
5946         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5947
5948         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5949         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5950                 enum pipe trans_edp_pipe;
5951                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5952                 default:
5953                         WARN(1, "unknown pipe linked to edp transcoder\n");
5954                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5955                 case TRANS_DDI_EDP_INPUT_A_ON:
5956                         trans_edp_pipe = PIPE_A;
5957                         break;
5958                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5959                         trans_edp_pipe = PIPE_B;
5960                         break;
5961                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5962                         trans_edp_pipe = PIPE_C;
5963                         break;
5964                 }
5965
5966                 if (trans_edp_pipe == crtc->pipe)
5967                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5968         }
5969
5970         if (!intel_display_power_enabled(dev,
5971                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5972                 return false;
5973
5974         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5975         if (!(tmp & PIPECONF_ENABLE))
5976                 return false;
5977
5978         /*
5979          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5980          * DDI E. So just check whether this pipe is wired to DDI E and whether
5981          * the PCH transcoder is on.
5982          */
5983         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5984         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5985             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5986                 pipe_config->has_pch_encoder = true;
5987
5988                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5989                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5990                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5991
5992                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5993         }
5994
5995         intel_get_pipe_timings(crtc, pipe_config);
5996
5997         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5998         if (intel_display_power_enabled(dev, pfit_domain))
5999                 ironlake_get_pfit_config(crtc, pipe_config);
6000
6001         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6002                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6003
6004         pipe_config->pixel_multiplier = 1;
6005
6006         return true;
6007 }
6008
6009 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6010                                int x, int y,
6011                                struct drm_framebuffer *fb)
6012 {
6013         struct drm_device *dev = crtc->dev;
6014         struct drm_i915_private *dev_priv = dev->dev_private;
6015         struct drm_encoder_helper_funcs *encoder_funcs;
6016         struct intel_encoder *encoder;
6017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6018         struct drm_display_mode *adjusted_mode =
6019                 &intel_crtc->config.adjusted_mode;
6020         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6021         int pipe = intel_crtc->pipe;
6022         int ret;
6023
6024         drm_vblank_pre_modeset(dev, pipe);
6025
6026         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6027
6028         drm_vblank_post_modeset(dev, pipe);
6029
6030         if (ret != 0)
6031                 return ret;
6032
6033         for_each_encoder_on_crtc(dev, crtc, encoder) {
6034                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6035                         encoder->base.base.id,
6036                         drm_get_encoder_name(&encoder->base),
6037                         mode->base.id, mode->name);
6038                 if (encoder->mode_set) {
6039                         encoder->mode_set(encoder);
6040                 } else {
6041                         encoder_funcs = encoder->base.helper_private;
6042                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6043                 }
6044         }
6045
6046         return 0;
6047 }
6048
6049 static bool intel_eld_uptodate(struct drm_connector *connector,
6050                                int reg_eldv, uint32_t bits_eldv,
6051                                int reg_elda, uint32_t bits_elda,
6052                                int reg_edid)
6053 {
6054         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6055         uint8_t *eld = connector->eld;
6056         uint32_t i;
6057
6058         i = I915_READ(reg_eldv);
6059         i &= bits_eldv;
6060
6061         if (!eld[0])
6062                 return !i;
6063
6064         if (!i)
6065                 return false;
6066
6067         i = I915_READ(reg_elda);
6068         i &= ~bits_elda;
6069         I915_WRITE(reg_elda, i);
6070
6071         for (i = 0; i < eld[2]; i++)
6072                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6073                         return false;
6074
6075         return true;
6076 }
6077
6078 static void g4x_write_eld(struct drm_connector *connector,
6079                           struct drm_crtc *crtc)
6080 {
6081         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6082         uint8_t *eld = connector->eld;
6083         uint32_t eldv;
6084         uint32_t len;
6085         uint32_t i;
6086
6087         i = I915_READ(G4X_AUD_VID_DID);
6088
6089         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6090                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6091         else
6092                 eldv = G4X_ELDV_DEVCTG;
6093
6094         if (intel_eld_uptodate(connector,
6095                                G4X_AUD_CNTL_ST, eldv,
6096                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6097                                G4X_HDMIW_HDMIEDID))
6098                 return;
6099
6100         i = I915_READ(G4X_AUD_CNTL_ST);
6101         i &= ~(eldv | G4X_ELD_ADDR);
6102         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6103         I915_WRITE(G4X_AUD_CNTL_ST, i);
6104
6105         if (!eld[0])
6106                 return;
6107
6108         len = min_t(uint8_t, eld[2], len);
6109         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6110         for (i = 0; i < len; i++)
6111                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6112
6113         i = I915_READ(G4X_AUD_CNTL_ST);
6114         i |= eldv;
6115         I915_WRITE(G4X_AUD_CNTL_ST, i);
6116 }
6117
6118 static void haswell_write_eld(struct drm_connector *connector,
6119                                      struct drm_crtc *crtc)
6120 {
6121         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6122         uint8_t *eld = connector->eld;
6123         struct drm_device *dev = crtc->dev;
6124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125         uint32_t eldv;
6126         uint32_t i;
6127         int len;
6128         int pipe = to_intel_crtc(crtc)->pipe;
6129         int tmp;
6130
6131         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6132         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6133         int aud_config = HSW_AUD_CFG(pipe);
6134         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6135
6136
6137         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6138
6139         /* Audio output enable */
6140         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6141         tmp = I915_READ(aud_cntrl_st2);
6142         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6143         I915_WRITE(aud_cntrl_st2, tmp);
6144
6145         /* Wait for 1 vertical blank */
6146         intel_wait_for_vblank(dev, pipe);
6147
6148         /* Set ELD valid state */
6149         tmp = I915_READ(aud_cntrl_st2);
6150         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6151         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6152         I915_WRITE(aud_cntrl_st2, tmp);
6153         tmp = I915_READ(aud_cntrl_st2);
6154         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6155
6156         /* Enable HDMI mode */
6157         tmp = I915_READ(aud_config);
6158         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6159         /* clear N_programing_enable and N_value_index */
6160         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6161         I915_WRITE(aud_config, tmp);
6162
6163         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6164
6165         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6166         intel_crtc->eld_vld = true;
6167
6168         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6169                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6170                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6171                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6172         } else
6173                 I915_WRITE(aud_config, 0);
6174
6175         if (intel_eld_uptodate(connector,
6176                                aud_cntrl_st2, eldv,
6177                                aud_cntl_st, IBX_ELD_ADDRESS,
6178                                hdmiw_hdmiedid))
6179                 return;
6180
6181         i = I915_READ(aud_cntrl_st2);
6182         i &= ~eldv;
6183         I915_WRITE(aud_cntrl_st2, i);
6184
6185         if (!eld[0])
6186                 return;
6187
6188         i = I915_READ(aud_cntl_st);
6189         i &= ~IBX_ELD_ADDRESS;
6190         I915_WRITE(aud_cntl_st, i);
6191         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6192         DRM_DEBUG_DRIVER("port num:%d\n", i);
6193
6194         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6195         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6196         for (i = 0; i < len; i++)
6197                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6198
6199         i = I915_READ(aud_cntrl_st2);
6200         i |= eldv;
6201         I915_WRITE(aud_cntrl_st2, i);
6202
6203 }
6204
6205 static void ironlake_write_eld(struct drm_connector *connector,
6206                                      struct drm_crtc *crtc)
6207 {
6208         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6209         uint8_t *eld = connector->eld;
6210         uint32_t eldv;
6211         uint32_t i;
6212         int len;
6213         int hdmiw_hdmiedid;
6214         int aud_config;
6215         int aud_cntl_st;
6216         int aud_cntrl_st2;
6217         int pipe = to_intel_crtc(crtc)->pipe;
6218
6219         if (HAS_PCH_IBX(connector->dev)) {
6220                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6221                 aud_config = IBX_AUD_CFG(pipe);
6222                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6223                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6224         } else {
6225                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6226                 aud_config = CPT_AUD_CFG(pipe);
6227                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6228                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6229         }
6230
6231         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6232
6233         i = I915_READ(aud_cntl_st);
6234         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6235         if (!i) {
6236                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6237                 /* operate blindly on all ports */
6238                 eldv = IBX_ELD_VALIDB;
6239                 eldv |= IBX_ELD_VALIDB << 4;
6240                 eldv |= IBX_ELD_VALIDB << 8;
6241         } else {
6242                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6243                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6244         }
6245
6246         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6247                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6248                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6249                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6250         } else
6251                 I915_WRITE(aud_config, 0);
6252
6253         if (intel_eld_uptodate(connector,
6254                                aud_cntrl_st2, eldv,
6255                                aud_cntl_st, IBX_ELD_ADDRESS,
6256                                hdmiw_hdmiedid))
6257                 return;
6258
6259         i = I915_READ(aud_cntrl_st2);
6260         i &= ~eldv;
6261         I915_WRITE(aud_cntrl_st2, i);
6262
6263         if (!eld[0])
6264                 return;
6265
6266         i = I915_READ(aud_cntl_st);
6267         i &= ~IBX_ELD_ADDRESS;
6268         I915_WRITE(aud_cntl_st, i);
6269
6270         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6271         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6272         for (i = 0; i < len; i++)
6273                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6274
6275         i = I915_READ(aud_cntrl_st2);
6276         i |= eldv;
6277         I915_WRITE(aud_cntrl_st2, i);
6278 }
6279
6280 void intel_write_eld(struct drm_encoder *encoder,
6281                      struct drm_display_mode *mode)
6282 {
6283         struct drm_crtc *crtc = encoder->crtc;
6284         struct drm_connector *connector;
6285         struct drm_device *dev = encoder->dev;
6286         struct drm_i915_private *dev_priv = dev->dev_private;
6287
6288         connector = drm_select_eld(encoder, mode);
6289         if (!connector)
6290                 return;
6291
6292         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6293                          connector->base.id,
6294                          drm_get_connector_name(connector),
6295                          connector->encoder->base.id,
6296                          drm_get_encoder_name(connector->encoder));
6297
6298         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6299
6300         if (dev_priv->display.write_eld)
6301                 dev_priv->display.write_eld(connector, crtc);
6302 }
6303
6304 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6305 void intel_crtc_load_lut(struct drm_crtc *crtc)
6306 {
6307         struct drm_device *dev = crtc->dev;
6308         struct drm_i915_private *dev_priv = dev->dev_private;
6309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6310         enum pipe pipe = intel_crtc->pipe;
6311         int palreg = PALETTE(pipe);
6312         int i;
6313         bool reenable_ips = false;
6314
6315         /* The clocks have to be on to load the palette. */
6316         if (!crtc->enabled || !intel_crtc->active)
6317                 return;
6318
6319         if (!HAS_PCH_SPLIT(dev_priv->dev))
6320                 assert_pll_enabled(dev_priv, pipe);
6321
6322         /* use legacy palette for Ironlake */
6323         if (HAS_PCH_SPLIT(dev))
6324                 palreg = LGC_PALETTE(pipe);
6325
6326         /* Workaround : Do not read or write the pipe palette/gamma data while
6327          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6328          */
6329         if (intel_crtc->config.ips_enabled &&
6330             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6331              GAMMA_MODE_MODE_SPLIT)) {
6332                 hsw_disable_ips(intel_crtc);
6333                 reenable_ips = true;
6334         }
6335
6336         for (i = 0; i < 256; i++) {
6337                 I915_WRITE(palreg + 4 * i,
6338                            (intel_crtc->lut_r[i] << 16) |
6339                            (intel_crtc->lut_g[i] << 8) |
6340                            intel_crtc->lut_b[i]);
6341         }
6342
6343         if (reenable_ips)
6344                 hsw_enable_ips(intel_crtc);
6345 }
6346
6347 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6348 {
6349         struct drm_device *dev = crtc->dev;
6350         struct drm_i915_private *dev_priv = dev->dev_private;
6351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6352         bool visible = base != 0;
6353         u32 cntl;
6354
6355         if (intel_crtc->cursor_visible == visible)
6356                 return;
6357
6358         cntl = I915_READ(_CURACNTR);
6359         if (visible) {
6360                 /* On these chipsets we can only modify the base whilst
6361                  * the cursor is disabled.
6362                  */
6363                 I915_WRITE(_CURABASE, base);
6364
6365                 cntl &= ~(CURSOR_FORMAT_MASK);
6366                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6367                 cntl |= CURSOR_ENABLE |
6368                         CURSOR_GAMMA_ENABLE |
6369                         CURSOR_FORMAT_ARGB;
6370         } else
6371                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6372         I915_WRITE(_CURACNTR, cntl);
6373
6374         intel_crtc->cursor_visible = visible;
6375 }
6376
6377 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6378 {
6379         struct drm_device *dev = crtc->dev;
6380         struct drm_i915_private *dev_priv = dev->dev_private;
6381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382         int pipe = intel_crtc->pipe;
6383         bool visible = base != 0;
6384
6385         if (intel_crtc->cursor_visible != visible) {
6386                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6387                 if (base) {
6388                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6389                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6390                         cntl |= pipe << 28; /* Connect to correct pipe */
6391                 } else {
6392                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6393                         cntl |= CURSOR_MODE_DISABLE;
6394                 }
6395                 I915_WRITE(CURCNTR(pipe), cntl);
6396
6397                 intel_crtc->cursor_visible = visible;
6398         }
6399         /* and commit changes on next vblank */
6400         I915_WRITE(CURBASE(pipe), base);
6401 }
6402
6403 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6404 {
6405         struct drm_device *dev = crtc->dev;
6406         struct drm_i915_private *dev_priv = dev->dev_private;
6407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6408         int pipe = intel_crtc->pipe;
6409         bool visible = base != 0;
6410
6411         if (intel_crtc->cursor_visible != visible) {
6412                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6413                 if (base) {
6414                         cntl &= ~CURSOR_MODE;
6415                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6416                 } else {
6417                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6418                         cntl |= CURSOR_MODE_DISABLE;
6419                 }
6420                 if (IS_HASWELL(dev))
6421                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6422                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6423
6424                 intel_crtc->cursor_visible = visible;
6425         }
6426         /* and commit changes on next vblank */
6427         I915_WRITE(CURBASE_IVB(pipe), base);
6428 }
6429
6430 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6431 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6432                                      bool on)
6433 {
6434         struct drm_device *dev = crtc->dev;
6435         struct drm_i915_private *dev_priv = dev->dev_private;
6436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6437         int pipe = intel_crtc->pipe;
6438         int x = intel_crtc->cursor_x;
6439         int y = intel_crtc->cursor_y;
6440         u32 base, pos;
6441         bool visible;
6442
6443         pos = 0;
6444
6445         if (on && crtc->enabled && crtc->fb) {
6446                 base = intel_crtc->cursor_addr;
6447                 if (x > (int) crtc->fb->width)
6448                         base = 0;
6449
6450                 if (y > (int) crtc->fb->height)
6451                         base = 0;
6452         } else
6453                 base = 0;
6454
6455         if (x < 0) {
6456                 if (x + intel_crtc->cursor_width < 0)
6457                         base = 0;
6458
6459                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6460                 x = -x;
6461         }
6462         pos |= x << CURSOR_X_SHIFT;
6463
6464         if (y < 0) {
6465                 if (y + intel_crtc->cursor_height < 0)
6466                         base = 0;
6467
6468                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6469                 y = -y;
6470         }
6471         pos |= y << CURSOR_Y_SHIFT;
6472
6473         visible = base != 0;
6474         if (!visible && !intel_crtc->cursor_visible)
6475                 return;
6476
6477         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6478                 I915_WRITE(CURPOS_IVB(pipe), pos);
6479                 ivb_update_cursor(crtc, base);
6480         } else {
6481                 I915_WRITE(CURPOS(pipe), pos);
6482                 if (IS_845G(dev) || IS_I865G(dev))
6483                         i845_update_cursor(crtc, base);
6484                 else
6485                         i9xx_update_cursor(crtc, base);
6486         }
6487 }
6488
6489 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6490                                  struct drm_file *file,
6491                                  uint32_t handle,
6492                                  uint32_t width, uint32_t height)
6493 {
6494         struct drm_device *dev = crtc->dev;
6495         struct drm_i915_private *dev_priv = dev->dev_private;
6496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497         struct drm_i915_gem_object *obj;
6498         uint32_t addr;
6499         int ret;
6500
6501         /* if we want to turn off the cursor ignore width and height */
6502         if (!handle) {
6503                 DRM_DEBUG_KMS("cursor off\n");
6504                 addr = 0;
6505                 obj = NULL;
6506                 mutex_lock(&dev->struct_mutex);
6507                 goto finish;
6508         }
6509
6510         /* Currently we only support 64x64 cursors */
6511         if (width != 64 || height != 64) {
6512                 DRM_ERROR("we currently only support 64x64 cursors\n");
6513                 return -EINVAL;
6514         }
6515
6516         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6517         if (&obj->base == NULL)
6518                 return -ENOENT;
6519
6520         if (obj->base.size < width * height * 4) {
6521                 DRM_ERROR("buffer is to small\n");
6522                 ret = -ENOMEM;
6523                 goto fail;
6524         }
6525
6526         /* we only need to pin inside GTT if cursor is non-phy */
6527         mutex_lock(&dev->struct_mutex);
6528         if (!dev_priv->info->cursor_needs_physical) {
6529                 unsigned alignment;
6530
6531                 if (obj->tiling_mode) {
6532                         DRM_ERROR("cursor cannot be tiled\n");
6533                         ret = -EINVAL;
6534                         goto fail_locked;
6535                 }
6536
6537                 /* Note that the w/a also requires 2 PTE of padding following
6538                  * the bo. We currently fill all unused PTE with the shadow
6539                  * page and so we should always have valid PTE following the
6540                  * cursor preventing the VT-d warning.
6541                  */
6542                 alignment = 0;
6543                 if (need_vtd_wa(dev))
6544                         alignment = 64*1024;
6545
6546                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6547                 if (ret) {
6548                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6549                         goto fail_locked;
6550                 }
6551
6552                 ret = i915_gem_object_put_fence(obj);
6553                 if (ret) {
6554                         DRM_ERROR("failed to release fence for cursor");
6555                         goto fail_unpin;
6556                 }
6557
6558                 addr = obj->gtt_offset;
6559         } else {
6560                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6561                 ret = i915_gem_attach_phys_object(dev, obj,
6562                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6563                                                   align);
6564                 if (ret) {
6565                         DRM_ERROR("failed to attach phys object\n");
6566                         goto fail_locked;
6567                 }
6568                 addr = obj->phys_obj->handle->busaddr;
6569         }
6570
6571         if (IS_GEN2(dev))
6572                 I915_WRITE(CURSIZE, (height << 12) | width);
6573
6574  finish:
6575         if (intel_crtc->cursor_bo) {
6576                 if (dev_priv->info->cursor_needs_physical) {
6577                         if (intel_crtc->cursor_bo != obj)
6578                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6579                 } else
6580                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6581                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6582         }
6583
6584         mutex_unlock(&dev->struct_mutex);
6585
6586         intel_crtc->cursor_addr = addr;
6587         intel_crtc->cursor_bo = obj;
6588         intel_crtc->cursor_width = width;
6589         intel_crtc->cursor_height = height;
6590
6591         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6592
6593         return 0;
6594 fail_unpin:
6595         i915_gem_object_unpin(obj);
6596 fail_locked:
6597         mutex_unlock(&dev->struct_mutex);
6598 fail:
6599         drm_gem_object_unreference_unlocked(&obj->base);
6600         return ret;
6601 }
6602
6603 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6604 {
6605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6606
6607         intel_crtc->cursor_x = x;
6608         intel_crtc->cursor_y = y;
6609
6610         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6611
6612         return 0;
6613 }
6614
6615 /** Sets the color ramps on behalf of RandR */
6616 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6617                                  u16 blue, int regno)
6618 {
6619         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6620
6621         intel_crtc->lut_r[regno] = red >> 8;
6622         intel_crtc->lut_g[regno] = green >> 8;
6623         intel_crtc->lut_b[regno] = blue >> 8;
6624 }
6625
6626 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6627                              u16 *blue, int regno)
6628 {
6629         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6630
6631         *red = intel_crtc->lut_r[regno] << 8;
6632         *green = intel_crtc->lut_g[regno] << 8;
6633         *blue = intel_crtc->lut_b[regno] << 8;
6634 }
6635
6636 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6637                                  u16 *blue, uint32_t start, uint32_t size)
6638 {
6639         int end = (start + size > 256) ? 256 : start + size, i;
6640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6641
6642         for (i = start; i < end; i++) {
6643                 intel_crtc->lut_r[i] = red[i] >> 8;
6644                 intel_crtc->lut_g[i] = green[i] >> 8;
6645                 intel_crtc->lut_b[i] = blue[i] >> 8;
6646         }
6647
6648         intel_crtc_load_lut(crtc);
6649 }
6650
6651 /* VESA 640x480x72Hz mode to set on the pipe */
6652 static struct drm_display_mode load_detect_mode = {
6653         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6654                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6655 };
6656
6657 static struct drm_framebuffer *
6658 intel_framebuffer_create(struct drm_device *dev,
6659                          struct drm_mode_fb_cmd2 *mode_cmd,
6660                          struct drm_i915_gem_object *obj)
6661 {
6662         struct intel_framebuffer *intel_fb;
6663         int ret;
6664
6665         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6666         if (!intel_fb) {
6667                 drm_gem_object_unreference_unlocked(&obj->base);
6668                 return ERR_PTR(-ENOMEM);
6669         }
6670
6671         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6672         if (ret) {
6673                 drm_gem_object_unreference_unlocked(&obj->base);
6674                 kfree(intel_fb);
6675                 return ERR_PTR(ret);
6676         }
6677
6678         return &intel_fb->base;
6679 }
6680
6681 static u32
6682 intel_framebuffer_pitch_for_width(int width, int bpp)
6683 {
6684         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6685         return ALIGN(pitch, 64);
6686 }
6687
6688 static u32
6689 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6690 {
6691         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6692         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6693 }
6694
6695 static struct drm_framebuffer *
6696 intel_framebuffer_create_for_mode(struct drm_device *dev,
6697                                   struct drm_display_mode *mode,
6698                                   int depth, int bpp)
6699 {
6700         struct drm_i915_gem_object *obj;
6701         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6702
6703         obj = i915_gem_alloc_object(dev,
6704                                     intel_framebuffer_size_for_mode(mode, bpp));
6705         if (obj == NULL)
6706                 return ERR_PTR(-ENOMEM);
6707
6708         mode_cmd.width = mode->hdisplay;
6709         mode_cmd.height = mode->vdisplay;
6710         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6711                                                                 bpp);
6712         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6713
6714         return intel_framebuffer_create(dev, &mode_cmd, obj);
6715 }
6716
6717 static struct drm_framebuffer *
6718 mode_fits_in_fbdev(struct drm_device *dev,
6719                    struct drm_display_mode *mode)
6720 {
6721         struct drm_i915_private *dev_priv = dev->dev_private;
6722         struct drm_i915_gem_object *obj;
6723         struct drm_framebuffer *fb;
6724
6725         if (dev_priv->fbdev == NULL)
6726                 return NULL;
6727
6728         obj = dev_priv->fbdev->ifb.obj;
6729         if (obj == NULL)
6730                 return NULL;
6731
6732         fb = &dev_priv->fbdev->ifb.base;
6733         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6734                                                                fb->bits_per_pixel))
6735                 return NULL;
6736
6737         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6738                 return NULL;
6739
6740         return fb;
6741 }
6742
6743 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6744                                 struct drm_display_mode *mode,
6745                                 struct intel_load_detect_pipe *old)
6746 {
6747         struct intel_crtc *intel_crtc;
6748         struct intel_encoder *intel_encoder =
6749                 intel_attached_encoder(connector);
6750         struct drm_crtc *possible_crtc;
6751         struct drm_encoder *encoder = &intel_encoder->base;
6752         struct drm_crtc *crtc = NULL;
6753         struct drm_device *dev = encoder->dev;
6754         struct drm_framebuffer *fb;
6755         int i = -1;
6756
6757         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6758                       connector->base.id, drm_get_connector_name(connector),
6759                       encoder->base.id, drm_get_encoder_name(encoder));
6760
6761         /*
6762          * Algorithm gets a little messy:
6763          *
6764          *   - if the connector already has an assigned crtc, use it (but make
6765          *     sure it's on first)
6766          *
6767          *   - try to find the first unused crtc that can drive this connector,
6768          *     and use that if we find one
6769          */
6770
6771         /* See if we already have a CRTC for this connector */
6772         if (encoder->crtc) {
6773                 crtc = encoder->crtc;
6774
6775                 mutex_lock(&crtc->mutex);
6776
6777                 old->dpms_mode = connector->dpms;
6778                 old->load_detect_temp = false;
6779
6780                 /* Make sure the crtc and connector are running */
6781                 if (connector->dpms != DRM_MODE_DPMS_ON)
6782                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6783
6784                 return true;
6785         }
6786
6787         /* Find an unused one (if possible) */
6788         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6789                 i++;
6790                 if (!(encoder->possible_crtcs & (1 << i)))
6791                         continue;
6792                 if (!possible_crtc->enabled) {
6793                         crtc = possible_crtc;
6794                         break;
6795                 }
6796         }
6797
6798         /*
6799          * If we didn't find an unused CRTC, don't use any.
6800          */
6801         if (!crtc) {
6802                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6803                 return false;
6804         }
6805
6806         mutex_lock(&crtc->mutex);
6807         intel_encoder->new_crtc = to_intel_crtc(crtc);
6808         to_intel_connector(connector)->new_encoder = intel_encoder;
6809
6810         intel_crtc = to_intel_crtc(crtc);
6811         old->dpms_mode = connector->dpms;
6812         old->load_detect_temp = true;
6813         old->release_fb = NULL;
6814
6815         if (!mode)
6816                 mode = &load_detect_mode;
6817
6818         /* We need a framebuffer large enough to accommodate all accesses
6819          * that the plane may generate whilst we perform load detection.
6820          * We can not rely on the fbcon either being present (we get called
6821          * during its initialisation to detect all boot displays, or it may
6822          * not even exist) or that it is large enough to satisfy the
6823          * requested mode.
6824          */
6825         fb = mode_fits_in_fbdev(dev, mode);
6826         if (fb == NULL) {
6827                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6828                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6829                 old->release_fb = fb;
6830         } else
6831                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6832         if (IS_ERR(fb)) {
6833                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6834                 mutex_unlock(&crtc->mutex);
6835                 return false;
6836         }
6837
6838         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6839                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6840                 if (old->release_fb)
6841                         old->release_fb->funcs->destroy(old->release_fb);
6842                 mutex_unlock(&crtc->mutex);
6843                 return false;
6844         }
6845
6846         /* let the connector get through one full cycle before testing */
6847         intel_wait_for_vblank(dev, intel_crtc->pipe);
6848         return true;
6849 }
6850
6851 void intel_release_load_detect_pipe(struct drm_connector *connector,
6852                                     struct intel_load_detect_pipe *old)
6853 {
6854         struct intel_encoder *intel_encoder =
6855                 intel_attached_encoder(connector);
6856         struct drm_encoder *encoder = &intel_encoder->base;
6857         struct drm_crtc *crtc = encoder->crtc;
6858
6859         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6860                       connector->base.id, drm_get_connector_name(connector),
6861                       encoder->base.id, drm_get_encoder_name(encoder));
6862
6863         if (old->load_detect_temp) {
6864                 to_intel_connector(connector)->new_encoder = NULL;
6865                 intel_encoder->new_crtc = NULL;
6866                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6867
6868                 if (old->release_fb) {
6869                         drm_framebuffer_unregister_private(old->release_fb);
6870                         drm_framebuffer_unreference(old->release_fb);
6871                 }
6872
6873                 mutex_unlock(&crtc->mutex);
6874                 return;
6875         }
6876
6877         /* Switch crtc and encoder back off if necessary */
6878         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6879                 connector->funcs->dpms(connector, old->dpms_mode);
6880
6881         mutex_unlock(&crtc->mutex);
6882 }
6883
6884 /* Returns the clock of the currently programmed mode of the given pipe. */
6885 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6886 {
6887         struct drm_i915_private *dev_priv = dev->dev_private;
6888         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6889         int pipe = intel_crtc->pipe;
6890         u32 dpll = I915_READ(DPLL(pipe));
6891         u32 fp;
6892         intel_clock_t clock;
6893
6894         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6895                 fp = I915_READ(FP0(pipe));
6896         else
6897                 fp = I915_READ(FP1(pipe));
6898
6899         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6900         if (IS_PINEVIEW(dev)) {
6901                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6902                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6903         } else {
6904                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6905                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6906         }
6907
6908         if (!IS_GEN2(dev)) {
6909                 if (IS_PINEVIEW(dev))
6910                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6911                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6912                 else
6913                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6914                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6915
6916                 switch (dpll & DPLL_MODE_MASK) {
6917                 case DPLLB_MODE_DAC_SERIAL:
6918                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6919                                 5 : 10;
6920                         break;
6921                 case DPLLB_MODE_LVDS:
6922                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6923                                 7 : 14;
6924                         break;
6925                 default:
6926                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6927                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6928                         return 0;
6929                 }
6930
6931                 if (IS_PINEVIEW(dev))
6932                         pineview_clock(96000, &clock);
6933                 else
6934                         i9xx_clock(96000, &clock);
6935         } else {
6936                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6937
6938                 if (is_lvds) {
6939                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6940                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6941                         clock.p2 = 14;
6942
6943                         if ((dpll & PLL_REF_INPUT_MASK) ==
6944                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6945                                 /* XXX: might not be 66MHz */
6946                                 i9xx_clock(66000, &clock);
6947                         } else
6948                                 i9xx_clock(48000, &clock);
6949                 } else {
6950                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6951                                 clock.p1 = 2;
6952                         else {
6953                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6954                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6955                         }
6956                         if (dpll & PLL_P2_DIVIDE_BY_4)
6957                                 clock.p2 = 4;
6958                         else
6959                                 clock.p2 = 2;
6960
6961                         i9xx_clock(48000, &clock);
6962                 }
6963         }
6964
6965         /* XXX: It would be nice to validate the clocks, but we can't reuse
6966          * i830PllIsValid() because it relies on the xf86_config connector
6967          * configuration being accurate, which it isn't necessarily.
6968          */
6969
6970         return clock.dot;
6971 }
6972
6973 /** Returns the currently programmed mode of the given pipe. */
6974 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6975                                              struct drm_crtc *crtc)
6976 {
6977         struct drm_i915_private *dev_priv = dev->dev_private;
6978         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6979         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6980         struct drm_display_mode *mode;
6981         int htot = I915_READ(HTOTAL(cpu_transcoder));
6982         int hsync = I915_READ(HSYNC(cpu_transcoder));
6983         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6984         int vsync = I915_READ(VSYNC(cpu_transcoder));
6985
6986         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6987         if (!mode)
6988                 return NULL;
6989
6990         mode->clock = intel_crtc_clock_get(dev, crtc);
6991         mode->hdisplay = (htot & 0xffff) + 1;
6992         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6993         mode->hsync_start = (hsync & 0xffff) + 1;
6994         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6995         mode->vdisplay = (vtot & 0xffff) + 1;
6996         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6997         mode->vsync_start = (vsync & 0xffff) + 1;
6998         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6999
7000         drm_mode_set_name(mode);
7001
7002         return mode;
7003 }
7004
7005 static void intel_increase_pllclock(struct drm_crtc *crtc)
7006 {
7007         struct drm_device *dev = crtc->dev;
7008         drm_i915_private_t *dev_priv = dev->dev_private;
7009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7010         int pipe = intel_crtc->pipe;
7011         int dpll_reg = DPLL(pipe);
7012         int dpll;
7013
7014         if (HAS_PCH_SPLIT(dev))
7015                 return;
7016
7017         if (!dev_priv->lvds_downclock_avail)
7018                 return;
7019
7020         dpll = I915_READ(dpll_reg);
7021         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7022                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7023
7024                 assert_panel_unlocked(dev_priv, pipe);
7025
7026                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7027                 I915_WRITE(dpll_reg, dpll);
7028                 intel_wait_for_vblank(dev, pipe);
7029
7030                 dpll = I915_READ(dpll_reg);
7031                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7032                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7033         }
7034 }
7035
7036 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7037 {
7038         struct drm_device *dev = crtc->dev;
7039         drm_i915_private_t *dev_priv = dev->dev_private;
7040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7041
7042         if (HAS_PCH_SPLIT(dev))
7043                 return;
7044
7045         if (!dev_priv->lvds_downclock_avail)
7046                 return;
7047
7048         /*
7049          * Since this is called by a timer, we should never get here in
7050          * the manual case.
7051          */
7052         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7053                 int pipe = intel_crtc->pipe;
7054                 int dpll_reg = DPLL(pipe);
7055                 int dpll;
7056
7057                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7058
7059                 assert_panel_unlocked(dev_priv, pipe);
7060
7061                 dpll = I915_READ(dpll_reg);
7062                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7063                 I915_WRITE(dpll_reg, dpll);
7064                 intel_wait_for_vblank(dev, pipe);
7065                 dpll = I915_READ(dpll_reg);
7066                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7067                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7068         }
7069
7070 }
7071
7072 void intel_mark_busy(struct drm_device *dev)
7073 {
7074         i915_update_gfx_val(dev->dev_private);
7075 }
7076
7077 void intel_mark_idle(struct drm_device *dev)
7078 {
7079         struct drm_crtc *crtc;
7080
7081         if (!i915_powersave)
7082                 return;
7083
7084         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7085                 if (!crtc->fb)
7086                         continue;
7087
7088                 intel_decrease_pllclock(crtc);
7089         }
7090 }
7091
7092 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7093                         struct intel_ring_buffer *ring)
7094 {
7095         struct drm_device *dev = obj->base.dev;
7096         struct drm_crtc *crtc;
7097
7098         if (!i915_powersave)
7099                 return;
7100
7101         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7102                 if (!crtc->fb)
7103                         continue;
7104
7105                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7106                         continue;
7107
7108                 intel_increase_pllclock(crtc);
7109                 if (ring && intel_fbc_enabled(dev))
7110                         ring->fbc_dirty = true;
7111         }
7112 }
7113
7114 static void intel_crtc_destroy(struct drm_crtc *crtc)
7115 {
7116         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7117         struct drm_device *dev = crtc->dev;
7118         struct intel_unpin_work *work;
7119         unsigned long flags;
7120
7121         spin_lock_irqsave(&dev->event_lock, flags);
7122         work = intel_crtc->unpin_work;
7123         intel_crtc->unpin_work = NULL;
7124         spin_unlock_irqrestore(&dev->event_lock, flags);
7125
7126         if (work) {
7127                 cancel_work_sync(&work->work);
7128                 kfree(work);
7129         }
7130
7131         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7132
7133         drm_crtc_cleanup(crtc);
7134
7135         kfree(intel_crtc);
7136 }
7137
7138 static void intel_unpin_work_fn(struct work_struct *__work)
7139 {
7140         struct intel_unpin_work *work =
7141                 container_of(__work, struct intel_unpin_work, work);
7142         struct drm_device *dev = work->crtc->dev;
7143
7144         mutex_lock(&dev->struct_mutex);
7145         intel_unpin_fb_obj(work->old_fb_obj);
7146         drm_gem_object_unreference(&work->pending_flip_obj->base);
7147         drm_gem_object_unreference(&work->old_fb_obj->base);
7148
7149         intel_update_fbc(dev);
7150         mutex_unlock(&dev->struct_mutex);
7151
7152         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7153         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7154
7155         kfree(work);
7156 }
7157
7158 static void do_intel_finish_page_flip(struct drm_device *dev,
7159                                       struct drm_crtc *crtc)
7160 {
7161         drm_i915_private_t *dev_priv = dev->dev_private;
7162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7163         struct intel_unpin_work *work;
7164         unsigned long flags;
7165
7166         /* Ignore early vblank irqs */
7167         if (intel_crtc == NULL)
7168                 return;
7169
7170         spin_lock_irqsave(&dev->event_lock, flags);
7171         work = intel_crtc->unpin_work;
7172
7173         /* Ensure we don't miss a work->pending update ... */
7174         smp_rmb();
7175
7176         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7177                 spin_unlock_irqrestore(&dev->event_lock, flags);
7178                 return;
7179         }
7180
7181         /* and that the unpin work is consistent wrt ->pending. */
7182         smp_rmb();
7183
7184         intel_crtc->unpin_work = NULL;
7185
7186         if (work->event)
7187                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7188
7189         drm_vblank_put(dev, intel_crtc->pipe);
7190
7191         spin_unlock_irqrestore(&dev->event_lock, flags);
7192
7193         wake_up_all(&dev_priv->pending_flip_queue);
7194
7195         queue_work(dev_priv->wq, &work->work);
7196
7197         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7198 }
7199
7200 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7201 {
7202         drm_i915_private_t *dev_priv = dev->dev_private;
7203         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7204
7205         do_intel_finish_page_flip(dev, crtc);
7206 }
7207
7208 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7209 {
7210         drm_i915_private_t *dev_priv = dev->dev_private;
7211         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7212
7213         do_intel_finish_page_flip(dev, crtc);
7214 }
7215
7216 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7217 {
7218         drm_i915_private_t *dev_priv = dev->dev_private;
7219         struct intel_crtc *intel_crtc =
7220                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7221         unsigned long flags;
7222
7223         /* NB: An MMIO update of the plane base pointer will also
7224          * generate a page-flip completion irq, i.e. every modeset
7225          * is also accompanied by a spurious intel_prepare_page_flip().
7226          */
7227         spin_lock_irqsave(&dev->event_lock, flags);
7228         if (intel_crtc->unpin_work)
7229                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7230         spin_unlock_irqrestore(&dev->event_lock, flags);
7231 }
7232
7233 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7234 {
7235         /* Ensure that the work item is consistent when activating it ... */
7236         smp_wmb();
7237         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7238         /* and that it is marked active as soon as the irq could fire. */
7239         smp_wmb();
7240 }
7241
7242 static int intel_gen2_queue_flip(struct drm_device *dev,
7243                                  struct drm_crtc *crtc,
7244                                  struct drm_framebuffer *fb,
7245                                  struct drm_i915_gem_object *obj)
7246 {
7247         struct drm_i915_private *dev_priv = dev->dev_private;
7248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7249         u32 flip_mask;
7250         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7251         int ret;
7252
7253         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7254         if (ret)
7255                 goto err;
7256
7257         ret = intel_ring_begin(ring, 6);
7258         if (ret)
7259                 goto err_unpin;
7260
7261         /* Can't queue multiple flips, so wait for the previous
7262          * one to finish before executing the next.
7263          */
7264         if (intel_crtc->plane)
7265                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7266         else
7267                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7268         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7269         intel_ring_emit(ring, MI_NOOP);
7270         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7271                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7272         intel_ring_emit(ring, fb->pitches[0]);
7273         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7274         intel_ring_emit(ring, 0); /* aux display base address, unused */
7275
7276         intel_mark_page_flip_active(intel_crtc);
7277         intel_ring_advance(ring);
7278         return 0;
7279
7280 err_unpin:
7281         intel_unpin_fb_obj(obj);
7282 err:
7283         return ret;
7284 }
7285
7286 static int intel_gen3_queue_flip(struct drm_device *dev,
7287                                  struct drm_crtc *crtc,
7288                                  struct drm_framebuffer *fb,
7289                                  struct drm_i915_gem_object *obj)
7290 {
7291         struct drm_i915_private *dev_priv = dev->dev_private;
7292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7293         u32 flip_mask;
7294         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7295         int ret;
7296
7297         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7298         if (ret)
7299                 goto err;
7300
7301         ret = intel_ring_begin(ring, 6);
7302         if (ret)
7303                 goto err_unpin;
7304
7305         if (intel_crtc->plane)
7306                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7307         else
7308                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7309         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7310         intel_ring_emit(ring, MI_NOOP);
7311         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7312                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7313         intel_ring_emit(ring, fb->pitches[0]);
7314         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7315         intel_ring_emit(ring, MI_NOOP);
7316
7317         intel_mark_page_flip_active(intel_crtc);
7318         intel_ring_advance(ring);
7319         return 0;
7320
7321 err_unpin:
7322         intel_unpin_fb_obj(obj);
7323 err:
7324         return ret;
7325 }
7326
7327 static int intel_gen4_queue_flip(struct drm_device *dev,
7328                                  struct drm_crtc *crtc,
7329                                  struct drm_framebuffer *fb,
7330                                  struct drm_i915_gem_object *obj)
7331 {
7332         struct drm_i915_private *dev_priv = dev->dev_private;
7333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7334         uint32_t pf, pipesrc;
7335         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7336         int ret;
7337
7338         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7339         if (ret)
7340                 goto err;
7341
7342         ret = intel_ring_begin(ring, 4);
7343         if (ret)
7344                 goto err_unpin;
7345
7346         /* i965+ uses the linear or tiled offsets from the
7347          * Display Registers (which do not change across a page-flip)
7348          * so we need only reprogram the base address.
7349          */
7350         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7351                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7352         intel_ring_emit(ring, fb->pitches[0]);
7353         intel_ring_emit(ring,
7354                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7355                         obj->tiling_mode);
7356
7357         /* XXX Enabling the panel-fitter across page-flip is so far
7358          * untested on non-native modes, so ignore it for now.
7359          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7360          */
7361         pf = 0;
7362         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7363         intel_ring_emit(ring, pf | pipesrc);
7364
7365         intel_mark_page_flip_active(intel_crtc);
7366         intel_ring_advance(ring);
7367         return 0;
7368
7369 err_unpin:
7370         intel_unpin_fb_obj(obj);
7371 err:
7372         return ret;
7373 }
7374
7375 static int intel_gen6_queue_flip(struct drm_device *dev,
7376                                  struct drm_crtc *crtc,
7377                                  struct drm_framebuffer *fb,
7378                                  struct drm_i915_gem_object *obj)
7379 {
7380         struct drm_i915_private *dev_priv = dev->dev_private;
7381         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7382         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7383         uint32_t pf, pipesrc;
7384         int ret;
7385
7386         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7387         if (ret)
7388                 goto err;
7389
7390         ret = intel_ring_begin(ring, 4);
7391         if (ret)
7392                 goto err_unpin;
7393
7394         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7395                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7396         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7397         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7398
7399         /* Contrary to the suggestions in the documentation,
7400          * "Enable Panel Fitter" does not seem to be required when page
7401          * flipping with a non-native mode, and worse causes a normal
7402          * modeset to fail.
7403          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7404          */
7405         pf = 0;
7406         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7407         intel_ring_emit(ring, pf | pipesrc);
7408
7409         intel_mark_page_flip_active(intel_crtc);
7410         intel_ring_advance(ring);
7411         return 0;
7412
7413 err_unpin:
7414         intel_unpin_fb_obj(obj);
7415 err:
7416         return ret;
7417 }
7418
7419 /*
7420  * On gen7 we currently use the blit ring because (in early silicon at least)
7421  * the render ring doesn't give us interrpts for page flip completion, which
7422  * means clients will hang after the first flip is queued.  Fortunately the
7423  * blit ring generates interrupts properly, so use it instead.
7424  */
7425 static int intel_gen7_queue_flip(struct drm_device *dev,
7426                                  struct drm_crtc *crtc,
7427                                  struct drm_framebuffer *fb,
7428                                  struct drm_i915_gem_object *obj)
7429 {
7430         struct drm_i915_private *dev_priv = dev->dev_private;
7431         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7432         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7433         uint32_t plane_bit = 0;
7434         int ret;
7435
7436         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7437         if (ret)
7438                 goto err;
7439
7440         switch(intel_crtc->plane) {
7441         case PLANE_A:
7442                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7443                 break;
7444         case PLANE_B:
7445                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7446                 break;
7447         case PLANE_C:
7448                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7449                 break;
7450         default:
7451                 WARN_ONCE(1, "unknown plane in flip command\n");
7452                 ret = -ENODEV;
7453                 goto err_unpin;
7454         }
7455
7456         ret = intel_ring_begin(ring, 4);
7457         if (ret)
7458                 goto err_unpin;
7459
7460         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7461         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7462         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7463         intel_ring_emit(ring, (MI_NOOP));
7464
7465         intel_mark_page_flip_active(intel_crtc);
7466         intel_ring_advance(ring);
7467         return 0;
7468
7469 err_unpin:
7470         intel_unpin_fb_obj(obj);
7471 err:
7472         return ret;
7473 }
7474
7475 static int intel_default_queue_flip(struct drm_device *dev,
7476                                     struct drm_crtc *crtc,
7477                                     struct drm_framebuffer *fb,
7478                                     struct drm_i915_gem_object *obj)
7479 {
7480         return -ENODEV;
7481 }
7482
7483 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7484                                 struct drm_framebuffer *fb,
7485                                 struct drm_pending_vblank_event *event)
7486 {
7487         struct drm_device *dev = crtc->dev;
7488         struct drm_i915_private *dev_priv = dev->dev_private;
7489         struct drm_framebuffer *old_fb = crtc->fb;
7490         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7491         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7492         struct intel_unpin_work *work;
7493         unsigned long flags;
7494         int ret;
7495
7496         /* Can't change pixel format via MI display flips. */
7497         if (fb->pixel_format != crtc->fb->pixel_format)
7498                 return -EINVAL;
7499
7500         /*
7501          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7502          * Note that pitch changes could also affect these register.
7503          */
7504         if (INTEL_INFO(dev)->gen > 3 &&
7505             (fb->offsets[0] != crtc->fb->offsets[0] ||
7506              fb->pitches[0] != crtc->fb->pitches[0]))
7507                 return -EINVAL;
7508
7509         work = kzalloc(sizeof *work, GFP_KERNEL);
7510         if (work == NULL)
7511                 return -ENOMEM;
7512
7513         work->event = event;
7514         work->crtc = crtc;
7515         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7516         INIT_WORK(&work->work, intel_unpin_work_fn);
7517
7518         ret = drm_vblank_get(dev, intel_crtc->pipe);
7519         if (ret)
7520                 goto free_work;
7521
7522         /* We borrow the event spin lock for protecting unpin_work */
7523         spin_lock_irqsave(&dev->event_lock, flags);
7524         if (intel_crtc->unpin_work) {
7525                 spin_unlock_irqrestore(&dev->event_lock, flags);
7526                 kfree(work);
7527                 drm_vblank_put(dev, intel_crtc->pipe);
7528
7529                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7530                 return -EBUSY;
7531         }
7532         intel_crtc->unpin_work = work;
7533         spin_unlock_irqrestore(&dev->event_lock, flags);
7534
7535         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7536                 flush_workqueue(dev_priv->wq);
7537
7538         ret = i915_mutex_lock_interruptible(dev);
7539         if (ret)
7540                 goto cleanup;
7541
7542         /* Reference the objects for the scheduled work. */
7543         drm_gem_object_reference(&work->old_fb_obj->base);
7544         drm_gem_object_reference(&obj->base);
7545
7546         crtc->fb = fb;
7547
7548         work->pending_flip_obj = obj;
7549
7550         work->enable_stall_check = true;
7551
7552         atomic_inc(&intel_crtc->unpin_work_count);
7553         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7554
7555         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7556         if (ret)
7557                 goto cleanup_pending;
7558
7559         intel_disable_fbc(dev);
7560         intel_mark_fb_busy(obj, NULL);
7561         mutex_unlock(&dev->struct_mutex);
7562
7563         trace_i915_flip_request(intel_crtc->plane, obj);
7564
7565         return 0;
7566
7567 cleanup_pending:
7568         atomic_dec(&intel_crtc->unpin_work_count);
7569         crtc->fb = old_fb;
7570         drm_gem_object_unreference(&work->old_fb_obj->base);
7571         drm_gem_object_unreference(&obj->base);
7572         mutex_unlock(&dev->struct_mutex);
7573
7574 cleanup:
7575         spin_lock_irqsave(&dev->event_lock, flags);
7576         intel_crtc->unpin_work = NULL;
7577         spin_unlock_irqrestore(&dev->event_lock, flags);
7578
7579         drm_vblank_put(dev, intel_crtc->pipe);
7580 free_work:
7581         kfree(work);
7582
7583         return ret;
7584 }
7585
7586 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7587         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7588         .load_lut = intel_crtc_load_lut,
7589 };
7590
7591 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7592                                   struct drm_crtc *crtc)
7593 {
7594         struct drm_device *dev;
7595         struct drm_crtc *tmp;
7596         int crtc_mask = 1;
7597
7598         WARN(!crtc, "checking null crtc?\n");
7599
7600         dev = crtc->dev;
7601
7602         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7603                 if (tmp == crtc)
7604                         break;
7605                 crtc_mask <<= 1;
7606         }
7607
7608         if (encoder->possible_crtcs & crtc_mask)
7609                 return true;
7610         return false;
7611 }
7612
7613 /**
7614  * intel_modeset_update_staged_output_state
7615  *
7616  * Updates the staged output configuration state, e.g. after we've read out the
7617  * current hw state.
7618  */
7619 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7620 {
7621         struct intel_encoder *encoder;
7622         struct intel_connector *connector;
7623
7624         list_for_each_entry(connector, &dev->mode_config.connector_list,
7625                             base.head) {
7626                 connector->new_encoder =
7627                         to_intel_encoder(connector->base.encoder);
7628         }
7629
7630         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7631                             base.head) {
7632                 encoder->new_crtc =
7633                         to_intel_crtc(encoder->base.crtc);
7634         }
7635 }
7636
7637 /**
7638  * intel_modeset_commit_output_state
7639  *
7640  * This function copies the stage display pipe configuration to the real one.
7641  */
7642 static void intel_modeset_commit_output_state(struct drm_device *dev)
7643 {
7644         struct intel_encoder *encoder;
7645         struct intel_connector *connector;
7646
7647         list_for_each_entry(connector, &dev->mode_config.connector_list,
7648                             base.head) {
7649                 connector->base.encoder = &connector->new_encoder->base;
7650         }
7651
7652         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7653                             base.head) {
7654                 encoder->base.crtc = &encoder->new_crtc->base;
7655         }
7656 }
7657
7658 static void
7659 connected_sink_compute_bpp(struct intel_connector * connector,
7660                            struct intel_crtc_config *pipe_config)
7661 {
7662         int bpp = pipe_config->pipe_bpp;
7663
7664         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7665                 connector->base.base.id,
7666                 drm_get_connector_name(&connector->base));
7667
7668         /* Don't use an invalid EDID bpc value */
7669         if (connector->base.display_info.bpc &&
7670             connector->base.display_info.bpc * 3 < bpp) {
7671                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7672                               bpp, connector->base.display_info.bpc*3);
7673                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7674         }
7675
7676         /* Clamp bpp to 8 on screens without EDID 1.4 */
7677         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7678                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7679                               bpp);
7680                 pipe_config->pipe_bpp = 24;
7681         }
7682 }
7683
7684 static int
7685 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7686                           struct drm_framebuffer *fb,
7687                           struct intel_crtc_config *pipe_config)
7688 {
7689         struct drm_device *dev = crtc->base.dev;
7690         struct intel_connector *connector;
7691         int bpp;
7692
7693         switch (fb->pixel_format) {
7694         case DRM_FORMAT_C8:
7695                 bpp = 8*3; /* since we go through a colormap */
7696                 break;
7697         case DRM_FORMAT_XRGB1555:
7698         case DRM_FORMAT_ARGB1555:
7699                 /* checked in intel_framebuffer_init already */
7700                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7701                         return -EINVAL;
7702         case DRM_FORMAT_RGB565:
7703                 bpp = 6*3; /* min is 18bpp */
7704                 break;
7705         case DRM_FORMAT_XBGR8888:
7706         case DRM_FORMAT_ABGR8888:
7707                 /* checked in intel_framebuffer_init already */
7708                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7709                         return -EINVAL;
7710         case DRM_FORMAT_XRGB8888:
7711         case DRM_FORMAT_ARGB8888:
7712                 bpp = 8*3;
7713                 break;
7714         case DRM_FORMAT_XRGB2101010:
7715         case DRM_FORMAT_ARGB2101010:
7716         case DRM_FORMAT_XBGR2101010:
7717         case DRM_FORMAT_ABGR2101010:
7718                 /* checked in intel_framebuffer_init already */
7719                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7720                         return -EINVAL;
7721                 bpp = 10*3;
7722                 break;
7723         /* TODO: gen4+ supports 16 bpc floating point, too. */
7724         default:
7725                 DRM_DEBUG_KMS("unsupported depth\n");
7726                 return -EINVAL;
7727         }
7728
7729         pipe_config->pipe_bpp = bpp;
7730
7731         /* Clamp display bpp to EDID value */
7732         list_for_each_entry(connector, &dev->mode_config.connector_list,
7733                             base.head) {
7734                 if (!connector->new_encoder ||
7735                     connector->new_encoder->new_crtc != crtc)
7736                         continue;
7737
7738                 connected_sink_compute_bpp(connector, pipe_config);
7739         }
7740
7741         return bpp;
7742 }
7743
7744 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7745                                    struct intel_crtc_config *pipe_config,
7746                                    const char *context)
7747 {
7748         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7749                       context, pipe_name(crtc->pipe));
7750
7751         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7752         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7753                       pipe_config->pipe_bpp, pipe_config->dither);
7754         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7755                       pipe_config->has_pch_encoder,
7756                       pipe_config->fdi_lanes,
7757                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7758                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7759                       pipe_config->fdi_m_n.tu);
7760         DRM_DEBUG_KMS("requested mode:\n");
7761         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7762         DRM_DEBUG_KMS("adjusted mode:\n");
7763         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7764         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7765                       pipe_config->gmch_pfit.control,
7766                       pipe_config->gmch_pfit.pgm_ratios,
7767                       pipe_config->gmch_pfit.lvds_border_bits);
7768         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7769                       pipe_config->pch_pfit.pos,
7770                       pipe_config->pch_pfit.size);
7771         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7772 }
7773
7774 static bool check_encoder_cloning(struct drm_crtc *crtc)
7775 {
7776         int num_encoders = 0;
7777         bool uncloneable_encoders = false;
7778         struct intel_encoder *encoder;
7779
7780         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7781                             base.head) {
7782                 if (&encoder->new_crtc->base != crtc)
7783                         continue;
7784
7785                 num_encoders++;
7786                 if (!encoder->cloneable)
7787                         uncloneable_encoders = true;
7788         }
7789
7790         return !(num_encoders > 1 && uncloneable_encoders);
7791 }
7792
7793 static struct intel_crtc_config *
7794 intel_modeset_pipe_config(struct drm_crtc *crtc,
7795                           struct drm_framebuffer *fb,
7796                           struct drm_display_mode *mode)
7797 {
7798         struct drm_device *dev = crtc->dev;
7799         struct drm_encoder_helper_funcs *encoder_funcs;
7800         struct intel_encoder *encoder;
7801         struct intel_crtc_config *pipe_config;
7802         int plane_bpp, ret = -EINVAL;
7803         bool retry = true;
7804
7805         if (!check_encoder_cloning(crtc)) {
7806                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7807                 return ERR_PTR(-EINVAL);
7808         }
7809
7810         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7811         if (!pipe_config)
7812                 return ERR_PTR(-ENOMEM);
7813
7814         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7815         drm_mode_copy(&pipe_config->requested_mode, mode);
7816         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7817         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7818
7819         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7820          * plane pixel format and any sink constraints into account. Returns the
7821          * source plane bpp so that dithering can be selected on mismatches
7822          * after encoders and crtc also have had their say. */
7823         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7824                                               fb, pipe_config);
7825         if (plane_bpp < 0)
7826                 goto fail;
7827
7828 encoder_retry:
7829         /* Ensure the port clock defaults are reset when retrying. */
7830         pipe_config->port_clock = 0;
7831         pipe_config->pixel_multiplier = 1;
7832
7833         /* Pass our mode to the connectors and the CRTC to give them a chance to
7834          * adjust it according to limitations or connector properties, and also
7835          * a chance to reject the mode entirely.
7836          */
7837         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7838                             base.head) {
7839
7840                 if (&encoder->new_crtc->base != crtc)
7841                         continue;
7842
7843                 if (encoder->compute_config) {
7844                         if (!(encoder->compute_config(encoder, pipe_config))) {
7845                                 DRM_DEBUG_KMS("Encoder config failure\n");
7846                                 goto fail;
7847                         }
7848
7849                         continue;
7850                 }
7851
7852                 encoder_funcs = encoder->base.helper_private;
7853                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7854                                                 &pipe_config->requested_mode,
7855                                                 &pipe_config->adjusted_mode))) {
7856                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7857                         goto fail;
7858                 }
7859         }
7860
7861         /* Set default port clock if not overwritten by the encoder. Needs to be
7862          * done afterwards in case the encoder adjusts the mode. */
7863         if (!pipe_config->port_clock)
7864                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7865
7866         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7867         if (ret < 0) {
7868                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7869                 goto fail;
7870         }
7871
7872         if (ret == RETRY) {
7873                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7874                         ret = -EINVAL;
7875                         goto fail;
7876                 }
7877
7878                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7879                 retry = false;
7880                 goto encoder_retry;
7881         }
7882
7883         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7884         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7885                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7886
7887         return pipe_config;
7888 fail:
7889         kfree(pipe_config);
7890         return ERR_PTR(ret);
7891 }
7892
7893 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7894  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7895 static void
7896 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7897                              unsigned *prepare_pipes, unsigned *disable_pipes)
7898 {
7899         struct intel_crtc *intel_crtc;
7900         struct drm_device *dev = crtc->dev;
7901         struct intel_encoder *encoder;
7902         struct intel_connector *connector;
7903         struct drm_crtc *tmp_crtc;
7904
7905         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7906
7907         /* Check which crtcs have changed outputs connected to them, these need
7908          * to be part of the prepare_pipes mask. We don't (yet) support global
7909          * modeset across multiple crtcs, so modeset_pipes will only have one
7910          * bit set at most. */
7911         list_for_each_entry(connector, &dev->mode_config.connector_list,
7912                             base.head) {
7913                 if (connector->base.encoder == &connector->new_encoder->base)
7914                         continue;
7915
7916                 if (connector->base.encoder) {
7917                         tmp_crtc = connector->base.encoder->crtc;
7918
7919                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7920                 }
7921
7922                 if (connector->new_encoder)
7923                         *prepare_pipes |=
7924                                 1 << connector->new_encoder->new_crtc->pipe;
7925         }
7926
7927         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7928                             base.head) {
7929                 if (encoder->base.crtc == &encoder->new_crtc->base)
7930                         continue;
7931
7932                 if (encoder->base.crtc) {
7933                         tmp_crtc = encoder->base.crtc;
7934
7935                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7936                 }
7937
7938                 if (encoder->new_crtc)
7939                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7940         }
7941
7942         /* Check for any pipes that will be fully disabled ... */
7943         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7944                             base.head) {
7945                 bool used = false;
7946
7947                 /* Don't try to disable disabled crtcs. */
7948                 if (!intel_crtc->base.enabled)
7949                         continue;
7950
7951                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7952                                     base.head) {
7953                         if (encoder->new_crtc == intel_crtc)
7954                                 used = true;
7955                 }
7956
7957                 if (!used)
7958                         *disable_pipes |= 1 << intel_crtc->pipe;
7959         }
7960
7961
7962         /* set_mode is also used to update properties on life display pipes. */
7963         intel_crtc = to_intel_crtc(crtc);
7964         if (crtc->enabled)
7965                 *prepare_pipes |= 1 << intel_crtc->pipe;
7966
7967         /*
7968          * For simplicity do a full modeset on any pipe where the output routing
7969          * changed. We could be more clever, but that would require us to be
7970          * more careful with calling the relevant encoder->mode_set functions.
7971          */
7972         if (*prepare_pipes)
7973                 *modeset_pipes = *prepare_pipes;
7974
7975         /* ... and mask these out. */
7976         *modeset_pipes &= ~(*disable_pipes);
7977         *prepare_pipes &= ~(*disable_pipes);
7978
7979         /*
7980          * HACK: We don't (yet) fully support global modesets. intel_set_config
7981          * obies this rule, but the modeset restore mode of
7982          * intel_modeset_setup_hw_state does not.
7983          */
7984         *modeset_pipes &= 1 << intel_crtc->pipe;
7985         *prepare_pipes &= 1 << intel_crtc->pipe;
7986
7987         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7988                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7989 }
7990
7991 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7992 {
7993         struct drm_encoder *encoder;
7994         struct drm_device *dev = crtc->dev;
7995
7996         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7997                 if (encoder->crtc == crtc)
7998                         return true;
7999
8000         return false;
8001 }
8002
8003 static void
8004 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8005 {
8006         struct intel_encoder *intel_encoder;
8007         struct intel_crtc *intel_crtc;
8008         struct drm_connector *connector;
8009
8010         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8011                             base.head) {
8012                 if (!intel_encoder->base.crtc)
8013                         continue;
8014
8015                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8016
8017                 if (prepare_pipes & (1 << intel_crtc->pipe))
8018                         intel_encoder->connectors_active = false;
8019         }
8020
8021         intel_modeset_commit_output_state(dev);
8022
8023         /* Update computed state. */
8024         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8025                             base.head) {
8026                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8027         }
8028
8029         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8030                 if (!connector->encoder || !connector->encoder->crtc)
8031                         continue;
8032
8033                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8034
8035                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8036                         struct drm_property *dpms_property =
8037                                 dev->mode_config.dpms_property;
8038
8039                         connector->dpms = DRM_MODE_DPMS_ON;
8040                         drm_object_property_set_value(&connector->base,
8041                                                          dpms_property,
8042                                                          DRM_MODE_DPMS_ON);
8043
8044                         intel_encoder = to_intel_encoder(connector->encoder);
8045                         intel_encoder->connectors_active = true;
8046                 }
8047         }
8048
8049 }
8050
8051 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8052         list_for_each_entry((intel_crtc), \
8053                             &(dev)->mode_config.crtc_list, \
8054                             base.head) \
8055                 if (mask & (1 <<(intel_crtc)->pipe))
8056
8057 static bool
8058 intel_pipe_config_compare(struct drm_device *dev,
8059                           struct intel_crtc_config *current_config,
8060                           struct intel_crtc_config *pipe_config)
8061 {
8062 #define PIPE_CONF_CHECK_X(name) \
8063         if (current_config->name != pipe_config->name) { \
8064                 DRM_ERROR("mismatch in " #name " " \
8065                           "(expected 0x%08x, found 0x%08x)\n", \
8066                           current_config->name, \
8067                           pipe_config->name); \
8068                 return false; \
8069         }
8070
8071 #define PIPE_CONF_CHECK_I(name) \
8072         if (current_config->name != pipe_config->name) { \
8073                 DRM_ERROR("mismatch in " #name " " \
8074                           "(expected %i, found %i)\n", \
8075                           current_config->name, \
8076                           pipe_config->name); \
8077                 return false; \
8078         }
8079
8080 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8081         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8082                 DRM_ERROR("mismatch in " #name " " \
8083                           "(expected %i, found %i)\n", \
8084                           current_config->name & (mask), \
8085                           pipe_config->name & (mask)); \
8086                 return false; \
8087         }
8088
8089 #define PIPE_CONF_QUIRK(quirk)  \
8090         ((current_config->quirks | pipe_config->quirks) & (quirk))
8091
8092         PIPE_CONF_CHECK_I(cpu_transcoder);
8093
8094         PIPE_CONF_CHECK_I(has_pch_encoder);
8095         PIPE_CONF_CHECK_I(fdi_lanes);
8096         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8097         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8098         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8099         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8100         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8101
8102         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8103         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8104         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8105         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8106         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8107         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8108
8109         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8110         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8111         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8112         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8113         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8114         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8115
8116         if (!HAS_PCH_SPLIT(dev))
8117                 PIPE_CONF_CHECK_I(pixel_multiplier);
8118
8119         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8120                               DRM_MODE_FLAG_INTERLACE);
8121
8122         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8123                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8124                                       DRM_MODE_FLAG_PHSYNC);
8125                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8126                                       DRM_MODE_FLAG_NHSYNC);
8127                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8128                                       DRM_MODE_FLAG_PVSYNC);
8129                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8130                                       DRM_MODE_FLAG_NVSYNC);
8131         }
8132
8133         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8134         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8135
8136         PIPE_CONF_CHECK_I(gmch_pfit.control);
8137         /* pfit ratios are autocomputed by the hw on gen4+ */
8138         if (INTEL_INFO(dev)->gen < 4)
8139                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8140         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8141         PIPE_CONF_CHECK_I(pch_pfit.pos);
8142         PIPE_CONF_CHECK_I(pch_pfit.size);
8143
8144         PIPE_CONF_CHECK_I(ips_enabled);
8145
8146         PIPE_CONF_CHECK_I(shared_dpll);
8147         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8148         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8149         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8150         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8151
8152 #undef PIPE_CONF_CHECK_X
8153 #undef PIPE_CONF_CHECK_I
8154 #undef PIPE_CONF_CHECK_FLAGS
8155 #undef PIPE_CONF_QUIRK
8156
8157         return true;
8158 }
8159
8160 static void
8161 check_connector_state(struct drm_device *dev)
8162 {
8163         struct intel_connector *connector;
8164
8165         list_for_each_entry(connector, &dev->mode_config.connector_list,
8166                             base.head) {
8167                 /* This also checks the encoder/connector hw state with the
8168                  * ->get_hw_state callbacks. */
8169                 intel_connector_check_state(connector);
8170
8171                 WARN(&connector->new_encoder->base != connector->base.encoder,
8172                      "connector's staged encoder doesn't match current encoder\n");
8173         }
8174 }
8175
8176 static void
8177 check_encoder_state(struct drm_device *dev)
8178 {
8179         struct intel_encoder *encoder;
8180         struct intel_connector *connector;
8181
8182         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8183                             base.head) {
8184                 bool enabled = false;
8185                 bool active = false;
8186                 enum pipe pipe, tracked_pipe;
8187
8188                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8189                               encoder->base.base.id,
8190                               drm_get_encoder_name(&encoder->base));
8191
8192                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8193                      "encoder's stage crtc doesn't match current crtc\n");
8194                 WARN(encoder->connectors_active && !encoder->base.crtc,
8195                      "encoder's active_connectors set, but no crtc\n");
8196
8197                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8198                                     base.head) {
8199                         if (connector->base.encoder != &encoder->base)
8200                                 continue;
8201                         enabled = true;
8202                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8203                                 active = true;
8204                 }
8205                 WARN(!!encoder->base.crtc != enabled,
8206                      "encoder's enabled state mismatch "
8207                      "(expected %i, found %i)\n",
8208                      !!encoder->base.crtc, enabled);
8209                 WARN(active && !encoder->base.crtc,
8210                      "active encoder with no crtc\n");
8211
8212                 WARN(encoder->connectors_active != active,
8213                      "encoder's computed active state doesn't match tracked active state "
8214                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8215
8216                 active = encoder->get_hw_state(encoder, &pipe);
8217                 WARN(active != encoder->connectors_active,
8218                      "encoder's hw state doesn't match sw tracking "
8219                      "(expected %i, found %i)\n",
8220                      encoder->connectors_active, active);
8221
8222                 if (!encoder->base.crtc)
8223                         continue;
8224
8225                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8226                 WARN(active && pipe != tracked_pipe,
8227                      "active encoder's pipe doesn't match"
8228                      "(expected %i, found %i)\n",
8229                      tracked_pipe, pipe);
8230
8231         }
8232 }
8233
8234 static void
8235 check_crtc_state(struct drm_device *dev)
8236 {
8237         drm_i915_private_t *dev_priv = dev->dev_private;
8238         struct intel_crtc *crtc;
8239         struct intel_encoder *encoder;
8240         struct intel_crtc_config pipe_config;
8241
8242         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8243                             base.head) {
8244                 bool enabled = false;
8245                 bool active = false;
8246
8247                 memset(&pipe_config, 0, sizeof(pipe_config));
8248
8249                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8250                               crtc->base.base.id);
8251
8252                 WARN(crtc->active && !crtc->base.enabled,
8253                      "active crtc, but not enabled in sw tracking\n");
8254
8255                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8256                                     base.head) {
8257                         if (encoder->base.crtc != &crtc->base)
8258                                 continue;
8259                         enabled = true;
8260                         if (encoder->connectors_active)
8261                                 active = true;
8262                 }
8263
8264                 WARN(active != crtc->active,
8265                      "crtc's computed active state doesn't match tracked active state "
8266                      "(expected %i, found %i)\n", active, crtc->active);
8267                 WARN(enabled != crtc->base.enabled,
8268                      "crtc's computed enabled state doesn't match tracked enabled state "
8269                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8270
8271                 active = dev_priv->display.get_pipe_config(crtc,
8272                                                            &pipe_config);
8273
8274                 /* hw state is inconsistent with the pipe A quirk */
8275                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8276                         active = crtc->active;
8277
8278                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8279                                     base.head) {
8280                         if (encoder->base.crtc != &crtc->base)
8281                                 continue;
8282                         if (encoder->get_config)
8283                                 encoder->get_config(encoder, &pipe_config);
8284                 }
8285
8286                 WARN(crtc->active != active,
8287                      "crtc active state doesn't match with hw state "
8288                      "(expected %i, found %i)\n", crtc->active, active);
8289
8290                 if (active &&
8291                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8292                         WARN(1, "pipe state doesn't match!\n");
8293                         intel_dump_pipe_config(crtc, &pipe_config,
8294                                                "[hw state]");
8295                         intel_dump_pipe_config(crtc, &crtc->config,
8296                                                "[sw state]");
8297                 }
8298         }
8299 }
8300
8301 static void
8302 check_shared_dpll_state(struct drm_device *dev)
8303 {
8304         drm_i915_private_t *dev_priv = dev->dev_private;
8305         struct intel_crtc *crtc;
8306         struct intel_dpll_hw_state dpll_hw_state;
8307         int i;
8308
8309         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8310                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8311                 int enabled_crtcs = 0, active_crtcs = 0;
8312                 bool active;
8313
8314                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8315
8316                 DRM_DEBUG_KMS("%s\n", pll->name);
8317
8318                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8319
8320                 WARN(pll->active > pll->refcount,
8321                      "more active pll users than references: %i vs %i\n",
8322                      pll->active, pll->refcount);
8323                 WARN(pll->active && !pll->on,
8324                      "pll in active use but not on in sw tracking\n");
8325                 WARN(pll->on != active,
8326                      "pll on state mismatch (expected %i, found %i)\n",
8327                      pll->on, active);
8328
8329                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8330                                     base.head) {
8331                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8332                                 enabled_crtcs++;
8333                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8334                                 active_crtcs++;
8335                 }
8336                 WARN(pll->active != active_crtcs,
8337                      "pll active crtcs mismatch (expected %i, found %i)\n",
8338                      pll->active, active_crtcs);
8339                 WARN(pll->refcount != enabled_crtcs,
8340                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8341                      pll->refcount, enabled_crtcs);
8342
8343                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8344                                        sizeof(dpll_hw_state)),
8345                      "pll hw state mismatch\n");
8346         }
8347 }
8348
8349 void
8350 intel_modeset_check_state(struct drm_device *dev)
8351 {
8352         check_connector_state(dev);
8353         check_encoder_state(dev);
8354         check_crtc_state(dev);
8355         check_shared_dpll_state(dev);
8356 }
8357
8358 static int __intel_set_mode(struct drm_crtc *crtc,
8359                             struct drm_display_mode *mode,
8360                             int x, int y, struct drm_framebuffer *fb)
8361 {
8362         struct drm_device *dev = crtc->dev;
8363         drm_i915_private_t *dev_priv = dev->dev_private;
8364         struct drm_display_mode *saved_mode, *saved_hwmode;
8365         struct intel_crtc_config *pipe_config = NULL;
8366         struct intel_crtc *intel_crtc;
8367         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8368         int ret = 0;
8369
8370         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8371         if (!saved_mode)
8372                 return -ENOMEM;
8373         saved_hwmode = saved_mode + 1;
8374
8375         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8376                                      &prepare_pipes, &disable_pipes);
8377
8378         *saved_hwmode = crtc->hwmode;
8379         *saved_mode = crtc->mode;
8380
8381         /* Hack: Because we don't (yet) support global modeset on multiple
8382          * crtcs, we don't keep track of the new mode for more than one crtc.
8383          * Hence simply check whether any bit is set in modeset_pipes in all the
8384          * pieces of code that are not yet converted to deal with mutliple crtcs
8385          * changing their mode at the same time. */
8386         if (modeset_pipes) {
8387                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8388                 if (IS_ERR(pipe_config)) {
8389                         ret = PTR_ERR(pipe_config);
8390                         pipe_config = NULL;
8391
8392                         goto out;
8393                 }
8394                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8395                                        "[modeset]");
8396         }
8397
8398         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8399                 intel_crtc_disable(&intel_crtc->base);
8400
8401         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8402                 if (intel_crtc->base.enabled)
8403                         dev_priv->display.crtc_disable(&intel_crtc->base);
8404         }
8405
8406         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8407          * to set it here already despite that we pass it down the callchain.
8408          */
8409         if (modeset_pipes) {
8410                 crtc->mode = *mode;
8411                 /* mode_set/enable/disable functions rely on a correct pipe
8412                  * config. */
8413                 to_intel_crtc(crtc)->config = *pipe_config;
8414         }
8415
8416         /* Only after disabling all output pipelines that will be changed can we
8417          * update the the output configuration. */
8418         intel_modeset_update_state(dev, prepare_pipes);
8419
8420         if (dev_priv->display.modeset_global_resources)
8421                 dev_priv->display.modeset_global_resources(dev);
8422
8423         /* Set up the DPLL and any encoders state that needs to adjust or depend
8424          * on the DPLL.
8425          */
8426         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8427                 ret = intel_crtc_mode_set(&intel_crtc->base,
8428                                           x, y, fb);
8429                 if (ret)
8430                         goto done;
8431         }
8432
8433         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8434         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8435                 dev_priv->display.crtc_enable(&intel_crtc->base);
8436
8437         if (modeset_pipes) {
8438                 /* Store real post-adjustment hardware mode. */
8439                 crtc->hwmode = pipe_config->adjusted_mode;
8440
8441                 /* Calculate and store various constants which
8442                  * are later needed by vblank and swap-completion
8443                  * timestamping. They are derived from true hwmode.
8444                  */
8445                 drm_calc_timestamping_constants(crtc);
8446         }
8447
8448         /* FIXME: add subpixel order */
8449 done:
8450         if (ret && crtc->enabled) {
8451                 crtc->hwmode = *saved_hwmode;
8452                 crtc->mode = *saved_mode;
8453         }
8454
8455 out:
8456         kfree(pipe_config);
8457         kfree(saved_mode);
8458         return ret;
8459 }
8460
8461 int intel_set_mode(struct drm_crtc *crtc,
8462                      struct drm_display_mode *mode,
8463                      int x, int y, struct drm_framebuffer *fb)
8464 {
8465         int ret;
8466
8467         ret = __intel_set_mode(crtc, mode, x, y, fb);
8468
8469         if (ret == 0)
8470                 intel_modeset_check_state(crtc->dev);
8471
8472         return ret;
8473 }
8474
8475 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8476 {
8477         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8478 }
8479
8480 #undef for_each_intel_crtc_masked
8481
8482 static void intel_set_config_free(struct intel_set_config *config)
8483 {
8484         if (!config)
8485                 return;
8486
8487         kfree(config->save_connector_encoders);
8488         kfree(config->save_encoder_crtcs);
8489         kfree(config);
8490 }
8491
8492 static int intel_set_config_save_state(struct drm_device *dev,
8493                                        struct intel_set_config *config)
8494 {
8495         struct drm_encoder *encoder;
8496         struct drm_connector *connector;
8497         int count;
8498
8499         config->save_encoder_crtcs =
8500                 kcalloc(dev->mode_config.num_encoder,
8501                         sizeof(struct drm_crtc *), GFP_KERNEL);
8502         if (!config->save_encoder_crtcs)
8503                 return -ENOMEM;
8504
8505         config->save_connector_encoders =
8506                 kcalloc(dev->mode_config.num_connector,
8507                         sizeof(struct drm_encoder *), GFP_KERNEL);
8508         if (!config->save_connector_encoders)
8509                 return -ENOMEM;
8510
8511         /* Copy data. Note that driver private data is not affected.
8512          * Should anything bad happen only the expected state is
8513          * restored, not the drivers personal bookkeeping.
8514          */
8515         count = 0;
8516         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8517                 config->save_encoder_crtcs[count++] = encoder->crtc;
8518         }
8519
8520         count = 0;
8521         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8522                 config->save_connector_encoders[count++] = connector->encoder;
8523         }
8524
8525         return 0;
8526 }
8527
8528 static void intel_set_config_restore_state(struct drm_device *dev,
8529                                            struct intel_set_config *config)
8530 {
8531         struct intel_encoder *encoder;
8532         struct intel_connector *connector;
8533         int count;
8534
8535         count = 0;
8536         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8537                 encoder->new_crtc =
8538                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8539         }
8540
8541         count = 0;
8542         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8543                 connector->new_encoder =
8544                         to_intel_encoder(config->save_connector_encoders[count++]);
8545         }
8546 }
8547
8548 static bool
8549 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8550                       int num_connectors)
8551 {
8552         int i;
8553
8554         for (i = 0; i < num_connectors; i++)
8555                 if (connectors[i].encoder &&
8556                     connectors[i].encoder->crtc == crtc &&
8557                     connectors[i].dpms != DRM_MODE_DPMS_ON)
8558                         return true;
8559
8560         return false;
8561 }
8562
8563 static void
8564 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8565                                       struct intel_set_config *config)
8566 {
8567
8568         /* We should be able to check here if the fb has the same properties
8569          * and then just flip_or_move it */
8570         if (set->connectors != NULL &&
8571             is_crtc_connector_off(set->crtc, *set->connectors,
8572                                   set->num_connectors)) {
8573                         config->mode_changed = true;
8574         } else if (set->crtc->fb != set->fb) {
8575                 /* If we have no fb then treat it as a full mode set */
8576                 if (set->crtc->fb == NULL) {
8577                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8578                         config->mode_changed = true;
8579                 } else if (set->fb == NULL) {
8580                         config->mode_changed = true;
8581                 } else if (set->fb->pixel_format !=
8582                            set->crtc->fb->pixel_format) {
8583                         config->mode_changed = true;
8584                 } else {
8585                         config->fb_changed = true;
8586                 }
8587         }
8588
8589         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8590                 config->fb_changed = true;
8591
8592         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8593                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8594                 drm_mode_debug_printmodeline(&set->crtc->mode);
8595                 drm_mode_debug_printmodeline(set->mode);
8596                 config->mode_changed = true;
8597         }
8598 }
8599
8600 static int
8601 intel_modeset_stage_output_state(struct drm_device *dev,
8602                                  struct drm_mode_set *set,
8603                                  struct intel_set_config *config)
8604 {
8605         struct drm_crtc *new_crtc;
8606         struct intel_connector *connector;
8607         struct intel_encoder *encoder;
8608         int count, ro;
8609
8610         /* The upper layers ensure that we either disable a crtc or have a list
8611          * of connectors. For paranoia, double-check this. */
8612         WARN_ON(!set->fb && (set->num_connectors != 0));
8613         WARN_ON(set->fb && (set->num_connectors == 0));
8614
8615         count = 0;
8616         list_for_each_entry(connector, &dev->mode_config.connector_list,
8617                             base.head) {
8618                 /* Otherwise traverse passed in connector list and get encoders
8619                  * for them. */
8620                 for (ro = 0; ro < set->num_connectors; ro++) {
8621                         if (set->connectors[ro] == &connector->base) {
8622                                 connector->new_encoder = connector->encoder;
8623                                 break;
8624                         }
8625                 }
8626
8627                 /* If we disable the crtc, disable all its connectors. Also, if
8628                  * the connector is on the changing crtc but not on the new
8629                  * connector list, disable it. */
8630                 if ((!set->fb || ro == set->num_connectors) &&
8631                     connector->base.encoder &&
8632                     connector->base.encoder->crtc == set->crtc) {
8633                         connector->new_encoder = NULL;
8634
8635                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8636                                 connector->base.base.id,
8637                                 drm_get_connector_name(&connector->base));
8638                 }
8639
8640
8641                 if (&connector->new_encoder->base != connector->base.encoder) {
8642                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8643                         config->mode_changed = true;
8644                 }
8645         }
8646         /* connector->new_encoder is now updated for all connectors. */
8647
8648         /* Update crtc of enabled connectors. */
8649         count = 0;
8650         list_for_each_entry(connector, &dev->mode_config.connector_list,
8651                             base.head) {
8652                 if (!connector->new_encoder)
8653                         continue;
8654
8655                 new_crtc = connector->new_encoder->base.crtc;
8656
8657                 for (ro = 0; ro < set->num_connectors; ro++) {
8658                         if (set->connectors[ro] == &connector->base)
8659                                 new_crtc = set->crtc;
8660                 }
8661
8662                 /* Make sure the new CRTC will work with the encoder */
8663                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8664                                            new_crtc)) {
8665                         return -EINVAL;
8666                 }
8667                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8668
8669                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8670                         connector->base.base.id,
8671                         drm_get_connector_name(&connector->base),
8672                         new_crtc->base.id);
8673         }
8674
8675         /* Check for any encoders that needs to be disabled. */
8676         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8677                             base.head) {
8678                 list_for_each_entry(connector,
8679                                     &dev->mode_config.connector_list,
8680                                     base.head) {
8681                         if (connector->new_encoder == encoder) {
8682                                 WARN_ON(!connector->new_encoder->new_crtc);
8683
8684                                 goto next_encoder;
8685                         }
8686                 }
8687                 encoder->new_crtc = NULL;
8688 next_encoder:
8689                 /* Only now check for crtc changes so we don't miss encoders
8690                  * that will be disabled. */
8691                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8692                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8693                         config->mode_changed = true;
8694                 }
8695         }
8696         /* Now we've also updated encoder->new_crtc for all encoders. */
8697
8698         return 0;
8699 }
8700
8701 static int intel_crtc_set_config(struct drm_mode_set *set)
8702 {
8703         struct drm_device *dev;
8704         struct drm_mode_set save_set;
8705         struct intel_set_config *config;
8706         int ret;
8707
8708         BUG_ON(!set);
8709         BUG_ON(!set->crtc);
8710         BUG_ON(!set->crtc->helper_private);
8711
8712         /* Enforce sane interface api - has been abused by the fb helper. */
8713         BUG_ON(!set->mode && set->fb);
8714         BUG_ON(set->fb && set->num_connectors == 0);
8715
8716         if (set->fb) {
8717                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8718                                 set->crtc->base.id, set->fb->base.id,
8719                                 (int)set->num_connectors, set->x, set->y);
8720         } else {
8721                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8722         }
8723
8724         dev = set->crtc->dev;
8725
8726         ret = -ENOMEM;
8727         config = kzalloc(sizeof(*config), GFP_KERNEL);
8728         if (!config)
8729                 goto out_config;
8730
8731         ret = intel_set_config_save_state(dev, config);
8732         if (ret)
8733                 goto out_config;
8734
8735         save_set.crtc = set->crtc;
8736         save_set.mode = &set->crtc->mode;
8737         save_set.x = set->crtc->x;
8738         save_set.y = set->crtc->y;
8739         save_set.fb = set->crtc->fb;
8740
8741         /* Compute whether we need a full modeset, only an fb base update or no
8742          * change at all. In the future we might also check whether only the
8743          * mode changed, e.g. for LVDS where we only change the panel fitter in
8744          * such cases. */
8745         intel_set_config_compute_mode_changes(set, config);
8746
8747         ret = intel_modeset_stage_output_state(dev, set, config);
8748         if (ret)
8749                 goto fail;
8750
8751         if (config->mode_changed) {
8752                 ret = intel_set_mode(set->crtc, set->mode,
8753                                      set->x, set->y, set->fb);
8754         } else if (config->fb_changed) {
8755                 intel_crtc_wait_for_pending_flips(set->crtc);
8756
8757                 ret = intel_pipe_set_base(set->crtc,
8758                                           set->x, set->y, set->fb);
8759         }
8760
8761         if (ret) {
8762                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8763                               set->crtc->base.id, ret);
8764 fail:
8765                 intel_set_config_restore_state(dev, config);
8766
8767                 /* Try to restore the config */
8768                 if (config->mode_changed &&
8769                     intel_set_mode(save_set.crtc, save_set.mode,
8770                                    save_set.x, save_set.y, save_set.fb))
8771                         DRM_ERROR("failed to restore config after modeset failure\n");
8772         }
8773
8774 out_config:
8775         intel_set_config_free(config);
8776         return ret;
8777 }
8778
8779 static const struct drm_crtc_funcs intel_crtc_funcs = {
8780         .cursor_set = intel_crtc_cursor_set,
8781         .cursor_move = intel_crtc_cursor_move,
8782         .gamma_set = intel_crtc_gamma_set,
8783         .set_config = intel_crtc_set_config,
8784         .destroy = intel_crtc_destroy,
8785         .page_flip = intel_crtc_page_flip,
8786 };
8787
8788 static void intel_cpu_pll_init(struct drm_device *dev)
8789 {
8790         if (HAS_DDI(dev))
8791                 intel_ddi_pll_init(dev);
8792 }
8793
8794 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8795                                       struct intel_shared_dpll *pll,
8796                                       struct intel_dpll_hw_state *hw_state)
8797 {
8798         uint32_t val;
8799
8800         val = I915_READ(PCH_DPLL(pll->id));
8801         hw_state->dpll = val;
8802         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8803         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8804
8805         return val & DPLL_VCO_ENABLE;
8806 }
8807
8808 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8809                                   struct intel_shared_dpll *pll)
8810 {
8811         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8812         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8813 }
8814
8815 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8816                                 struct intel_shared_dpll *pll)
8817 {
8818         /* PCH refclock must be enabled first */
8819         assert_pch_refclk_enabled(dev_priv);
8820
8821         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8822
8823         /* Wait for the clocks to stabilize. */
8824         POSTING_READ(PCH_DPLL(pll->id));
8825         udelay(150);
8826
8827         /* The pixel multiplier can only be updated once the
8828          * DPLL is enabled and the clocks are stable.
8829          *
8830          * So write it again.
8831          */
8832         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8833         POSTING_READ(PCH_DPLL(pll->id));
8834         udelay(200);
8835 }
8836
8837 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8838                                  struct intel_shared_dpll *pll)
8839 {
8840         struct drm_device *dev = dev_priv->dev;
8841         struct intel_crtc *crtc;
8842
8843         /* Make sure no transcoder isn't still depending on us. */
8844         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8845                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8846                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8847         }
8848
8849         I915_WRITE(PCH_DPLL(pll->id), 0);
8850         POSTING_READ(PCH_DPLL(pll->id));
8851         udelay(200);
8852 }
8853
8854 static char *ibx_pch_dpll_names[] = {
8855         "PCH DPLL A",
8856         "PCH DPLL B",
8857 };
8858
8859 static void ibx_pch_dpll_init(struct drm_device *dev)
8860 {
8861         struct drm_i915_private *dev_priv = dev->dev_private;
8862         int i;
8863
8864         dev_priv->num_shared_dpll = 2;
8865
8866         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8867                 dev_priv->shared_dplls[i].id = i;
8868                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8869                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8870                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8871                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8872                 dev_priv->shared_dplls[i].get_hw_state =
8873                         ibx_pch_dpll_get_hw_state;
8874         }
8875 }
8876
8877 static void intel_shared_dpll_init(struct drm_device *dev)
8878 {
8879         struct drm_i915_private *dev_priv = dev->dev_private;
8880
8881         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8882                 ibx_pch_dpll_init(dev);
8883         else
8884                 dev_priv->num_shared_dpll = 0;
8885
8886         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8887         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8888                       dev_priv->num_shared_dpll);
8889 }
8890
8891 static void intel_crtc_init(struct drm_device *dev, int pipe)
8892 {
8893         drm_i915_private_t *dev_priv = dev->dev_private;
8894         struct intel_crtc *intel_crtc;
8895         int i;
8896
8897         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8898         if (intel_crtc == NULL)
8899                 return;
8900
8901         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8902
8903         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8904         for (i = 0; i < 256; i++) {
8905                 intel_crtc->lut_r[i] = i;
8906                 intel_crtc->lut_g[i] = i;
8907                 intel_crtc->lut_b[i] = i;
8908         }
8909
8910         /* Swap pipes & planes for FBC on pre-965 */
8911         intel_crtc->pipe = pipe;
8912         intel_crtc->plane = pipe;
8913         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8914                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8915                 intel_crtc->plane = !pipe;
8916         }
8917
8918         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8919                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8920         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8921         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8922
8923         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8924 }
8925
8926 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8927                                 struct drm_file *file)
8928 {
8929         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8930         struct drm_mode_object *drmmode_obj;
8931         struct intel_crtc *crtc;
8932
8933         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8934                 return -ENODEV;
8935
8936         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8937                         DRM_MODE_OBJECT_CRTC);
8938
8939         if (!drmmode_obj) {
8940                 DRM_ERROR("no such CRTC id\n");
8941                 return -EINVAL;
8942         }
8943
8944         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8945         pipe_from_crtc_id->pipe = crtc->pipe;
8946
8947         return 0;
8948 }
8949
8950 static int intel_encoder_clones(struct intel_encoder *encoder)
8951 {
8952         struct drm_device *dev = encoder->base.dev;
8953         struct intel_encoder *source_encoder;
8954         int index_mask = 0;
8955         int entry = 0;
8956
8957         list_for_each_entry(source_encoder,
8958                             &dev->mode_config.encoder_list, base.head) {
8959
8960                 if (encoder == source_encoder)
8961                         index_mask |= (1 << entry);
8962
8963                 /* Intel hw has only one MUX where enocoders could be cloned. */
8964                 if (encoder->cloneable && source_encoder->cloneable)
8965                         index_mask |= (1 << entry);
8966
8967                 entry++;
8968         }
8969
8970         return index_mask;
8971 }
8972
8973 static bool has_edp_a(struct drm_device *dev)
8974 {
8975         struct drm_i915_private *dev_priv = dev->dev_private;
8976
8977         if (!IS_MOBILE(dev))
8978                 return false;
8979
8980         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8981                 return false;
8982
8983         if (IS_GEN5(dev) &&
8984             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8985                 return false;
8986
8987         return true;
8988 }
8989
8990 static void intel_setup_outputs(struct drm_device *dev)
8991 {
8992         struct drm_i915_private *dev_priv = dev->dev_private;
8993         struct intel_encoder *encoder;
8994         bool dpd_is_edp = false;
8995
8996         intel_lvds_init(dev);
8997
8998         if (!IS_ULT(dev))
8999                 intel_crt_init(dev);
9000
9001         if (HAS_DDI(dev)) {
9002                 int found;
9003
9004                 /* Haswell uses DDI functions to detect digital outputs */
9005                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9006                 /* DDI A only supports eDP */
9007                 if (found)
9008                         intel_ddi_init(dev, PORT_A);
9009
9010                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9011                  * register */
9012                 found = I915_READ(SFUSE_STRAP);
9013
9014                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9015                         intel_ddi_init(dev, PORT_B);
9016                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9017                         intel_ddi_init(dev, PORT_C);
9018                 if (found & SFUSE_STRAP_DDID_DETECTED)
9019                         intel_ddi_init(dev, PORT_D);
9020         } else if (HAS_PCH_SPLIT(dev)) {
9021                 int found;
9022                 dpd_is_edp = intel_dpd_is_edp(dev);
9023
9024                 if (has_edp_a(dev))
9025                         intel_dp_init(dev, DP_A, PORT_A);
9026
9027                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9028                         /* PCH SDVOB multiplex with HDMIB */
9029                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9030                         if (!found)
9031                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9032                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9033                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9034                 }
9035
9036                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9037                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9038
9039                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9040                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9041
9042                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9043                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9044
9045                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9046                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9047         } else if (IS_VALLEYVIEW(dev)) {
9048                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9049                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9050                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9051
9052                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9053                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9054                                         PORT_B);
9055                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9056                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9057                 }
9058         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9059                 bool found = false;
9060
9061                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9062                         DRM_DEBUG_KMS("probing SDVOB\n");
9063                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9064                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9065                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9066                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9067                         }
9068
9069                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9070                                 intel_dp_init(dev, DP_B, PORT_B);
9071                 }
9072
9073                 /* Before G4X SDVOC doesn't have its own detect register */
9074
9075                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9076                         DRM_DEBUG_KMS("probing SDVOC\n");
9077                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9078                 }
9079
9080                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9081
9082                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9083                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9084                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9085                         }
9086                         if (SUPPORTS_INTEGRATED_DP(dev))
9087                                 intel_dp_init(dev, DP_C, PORT_C);
9088                 }
9089
9090                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9091                     (I915_READ(DP_D) & DP_DETECTED))
9092                         intel_dp_init(dev, DP_D, PORT_D);
9093         } else if (IS_GEN2(dev))
9094                 intel_dvo_init(dev);
9095
9096         if (SUPPORTS_TV(dev))
9097                 intel_tv_init(dev);
9098
9099         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9100                 encoder->base.possible_crtcs = encoder->crtc_mask;
9101                 encoder->base.possible_clones =
9102                         intel_encoder_clones(encoder);
9103         }
9104
9105         intel_init_pch_refclk(dev);
9106
9107         drm_helper_move_panel_connectors_to_head(dev);
9108 }
9109
9110 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9111 {
9112         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9113
9114         drm_framebuffer_cleanup(fb);
9115         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9116
9117         kfree(intel_fb);
9118 }
9119
9120 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9121                                                 struct drm_file *file,
9122                                                 unsigned int *handle)
9123 {
9124         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9125         struct drm_i915_gem_object *obj = intel_fb->obj;
9126
9127         return drm_gem_handle_create(file, &obj->base, handle);
9128 }
9129
9130 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9131         .destroy = intel_user_framebuffer_destroy,
9132         .create_handle = intel_user_framebuffer_create_handle,
9133 };
9134
9135 int intel_framebuffer_init(struct drm_device *dev,
9136                            struct intel_framebuffer *intel_fb,
9137                            struct drm_mode_fb_cmd2 *mode_cmd,
9138                            struct drm_i915_gem_object *obj)
9139 {
9140         int pitch_limit;
9141         int ret;
9142
9143         if (obj->tiling_mode == I915_TILING_Y) {
9144                 DRM_DEBUG("hardware does not support tiling Y\n");
9145                 return -EINVAL;
9146         }
9147
9148         if (mode_cmd->pitches[0] & 63) {
9149                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9150                           mode_cmd->pitches[0]);
9151                 return -EINVAL;
9152         }
9153
9154         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9155                 pitch_limit = 32*1024;
9156         } else if (INTEL_INFO(dev)->gen >= 4) {
9157                 if (obj->tiling_mode)
9158                         pitch_limit = 16*1024;
9159                 else
9160                         pitch_limit = 32*1024;
9161         } else if (INTEL_INFO(dev)->gen >= 3) {
9162                 if (obj->tiling_mode)
9163                         pitch_limit = 8*1024;
9164                 else
9165                         pitch_limit = 16*1024;
9166         } else
9167                 /* XXX DSPC is limited to 4k tiled */
9168                 pitch_limit = 8*1024;
9169
9170         if (mode_cmd->pitches[0] > pitch_limit) {
9171                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9172                           obj->tiling_mode ? "tiled" : "linear",
9173                           mode_cmd->pitches[0], pitch_limit);
9174                 return -EINVAL;
9175         }
9176
9177         if (obj->tiling_mode != I915_TILING_NONE &&
9178             mode_cmd->pitches[0] != obj->stride) {
9179                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9180                           mode_cmd->pitches[0], obj->stride);
9181                 return -EINVAL;
9182         }
9183
9184         /* Reject formats not supported by any plane early. */
9185         switch (mode_cmd->pixel_format) {
9186         case DRM_FORMAT_C8:
9187         case DRM_FORMAT_RGB565:
9188         case DRM_FORMAT_XRGB8888:
9189         case DRM_FORMAT_ARGB8888:
9190                 break;
9191         case DRM_FORMAT_XRGB1555:
9192         case DRM_FORMAT_ARGB1555:
9193                 if (INTEL_INFO(dev)->gen > 3) {
9194                         DRM_DEBUG("unsupported pixel format: %s\n",
9195                                   drm_get_format_name(mode_cmd->pixel_format));
9196                         return -EINVAL;
9197                 }
9198                 break;
9199         case DRM_FORMAT_XBGR8888:
9200         case DRM_FORMAT_ABGR8888:
9201         case DRM_FORMAT_XRGB2101010:
9202         case DRM_FORMAT_ARGB2101010:
9203         case DRM_FORMAT_XBGR2101010:
9204         case DRM_FORMAT_ABGR2101010:
9205                 if (INTEL_INFO(dev)->gen < 4) {
9206                         DRM_DEBUG("unsupported pixel format: %s\n",
9207                                   drm_get_format_name(mode_cmd->pixel_format));
9208                         return -EINVAL;
9209                 }
9210                 break;
9211         case DRM_FORMAT_YUYV:
9212         case DRM_FORMAT_UYVY:
9213         case DRM_FORMAT_YVYU:
9214         case DRM_FORMAT_VYUY:
9215                 if (INTEL_INFO(dev)->gen < 5) {
9216                         DRM_DEBUG("unsupported pixel format: %s\n",
9217                                   drm_get_format_name(mode_cmd->pixel_format));
9218                         return -EINVAL;
9219                 }
9220                 break;
9221         default:
9222                 DRM_DEBUG("unsupported pixel format: %s\n",
9223                           drm_get_format_name(mode_cmd->pixel_format));
9224                 return -EINVAL;
9225         }
9226
9227         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9228         if (mode_cmd->offsets[0] != 0)
9229                 return -EINVAL;
9230
9231         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9232         intel_fb->obj = obj;
9233
9234         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9235         if (ret) {
9236                 DRM_ERROR("framebuffer init failed %d\n", ret);
9237                 return ret;
9238         }
9239
9240         return 0;
9241 }
9242
9243 static struct drm_framebuffer *
9244 intel_user_framebuffer_create(struct drm_device *dev,
9245                               struct drm_file *filp,
9246                               struct drm_mode_fb_cmd2 *mode_cmd)
9247 {
9248         struct drm_i915_gem_object *obj;
9249
9250         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9251                                                 mode_cmd->handles[0]));
9252         if (&obj->base == NULL)
9253                 return ERR_PTR(-ENOENT);
9254
9255         return intel_framebuffer_create(dev, mode_cmd, obj);
9256 }
9257
9258 static const struct drm_mode_config_funcs intel_mode_funcs = {
9259         .fb_create = intel_user_framebuffer_create,
9260         .output_poll_changed = intel_fb_output_poll_changed,
9261 };
9262
9263 /* Set up chip specific display functions */
9264 static void intel_init_display(struct drm_device *dev)
9265 {
9266         struct drm_i915_private *dev_priv = dev->dev_private;
9267
9268         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9269                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9270         else if (IS_VALLEYVIEW(dev))
9271                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9272         else if (IS_PINEVIEW(dev))
9273                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9274         else
9275                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9276
9277         if (HAS_DDI(dev)) {
9278                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9279                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9280                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9281                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9282                 dev_priv->display.off = haswell_crtc_off;
9283                 dev_priv->display.update_plane = ironlake_update_plane;
9284         } else if (HAS_PCH_SPLIT(dev)) {
9285                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9286                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9287                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9288                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9289                 dev_priv->display.off = ironlake_crtc_off;
9290                 dev_priv->display.update_plane = ironlake_update_plane;
9291         } else if (IS_VALLEYVIEW(dev)) {
9292                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9293                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9294                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9295                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9296                 dev_priv->display.off = i9xx_crtc_off;
9297                 dev_priv->display.update_plane = i9xx_update_plane;
9298         } else {
9299                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9300                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9301                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9302                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9303                 dev_priv->display.off = i9xx_crtc_off;
9304                 dev_priv->display.update_plane = i9xx_update_plane;
9305         }
9306
9307         /* Returns the core display clock speed */
9308         if (IS_VALLEYVIEW(dev))
9309                 dev_priv->display.get_display_clock_speed =
9310                         valleyview_get_display_clock_speed;
9311         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9312                 dev_priv->display.get_display_clock_speed =
9313                         i945_get_display_clock_speed;
9314         else if (IS_I915G(dev))
9315                 dev_priv->display.get_display_clock_speed =
9316                         i915_get_display_clock_speed;
9317         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9318                 dev_priv->display.get_display_clock_speed =
9319                         i9xx_misc_get_display_clock_speed;
9320         else if (IS_I915GM(dev))
9321                 dev_priv->display.get_display_clock_speed =
9322                         i915gm_get_display_clock_speed;
9323         else if (IS_I865G(dev))
9324                 dev_priv->display.get_display_clock_speed =
9325                         i865_get_display_clock_speed;
9326         else if (IS_I85X(dev))
9327                 dev_priv->display.get_display_clock_speed =
9328                         i855_get_display_clock_speed;
9329         else /* 852, 830 */
9330                 dev_priv->display.get_display_clock_speed =
9331                         i830_get_display_clock_speed;
9332
9333         if (HAS_PCH_SPLIT(dev)) {
9334                 if (IS_GEN5(dev)) {
9335                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9336                         dev_priv->display.write_eld = ironlake_write_eld;
9337                 } else if (IS_GEN6(dev)) {
9338                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9339                         dev_priv->display.write_eld = ironlake_write_eld;
9340                 } else if (IS_IVYBRIDGE(dev)) {
9341                         /* FIXME: detect B0+ stepping and use auto training */
9342                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9343                         dev_priv->display.write_eld = ironlake_write_eld;
9344                         dev_priv->display.modeset_global_resources =
9345                                 ivb_modeset_global_resources;
9346                 } else if (IS_HASWELL(dev)) {
9347                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9348                         dev_priv->display.write_eld = haswell_write_eld;
9349                         dev_priv->display.modeset_global_resources =
9350                                 haswell_modeset_global_resources;
9351                 }
9352         } else if (IS_G4X(dev)) {
9353                 dev_priv->display.write_eld = g4x_write_eld;
9354         }
9355
9356         /* Default just returns -ENODEV to indicate unsupported */
9357         dev_priv->display.queue_flip = intel_default_queue_flip;
9358
9359         switch (INTEL_INFO(dev)->gen) {
9360         case 2:
9361                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9362                 break;
9363
9364         case 3:
9365                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9366                 break;
9367
9368         case 4:
9369         case 5:
9370                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9371                 break;
9372
9373         case 6:
9374                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9375                 break;
9376         case 7:
9377                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9378                 break;
9379         }
9380 }
9381
9382 /*
9383  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9384  * resume, or other times.  This quirk makes sure that's the case for
9385  * affected systems.
9386  */
9387 static void quirk_pipea_force(struct drm_device *dev)
9388 {
9389         struct drm_i915_private *dev_priv = dev->dev_private;
9390
9391         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9392         DRM_INFO("applying pipe a force quirk\n");
9393 }
9394
9395 /*
9396  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9397  */
9398 static void quirk_ssc_force_disable(struct drm_device *dev)
9399 {
9400         struct drm_i915_private *dev_priv = dev->dev_private;
9401         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9402         DRM_INFO("applying lvds SSC disable quirk\n");
9403 }
9404
9405 /*
9406  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9407  * brightness value
9408  */
9409 static void quirk_invert_brightness(struct drm_device *dev)
9410 {
9411         struct drm_i915_private *dev_priv = dev->dev_private;
9412         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9413         DRM_INFO("applying inverted panel brightness quirk\n");
9414 }
9415
9416 struct intel_quirk {
9417         int device;
9418         int subsystem_vendor;
9419         int subsystem_device;
9420         void (*hook)(struct drm_device *dev);
9421 };
9422
9423 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9424 struct intel_dmi_quirk {
9425         void (*hook)(struct drm_device *dev);
9426         const struct dmi_system_id (*dmi_id_list)[];
9427 };
9428
9429 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9430 {
9431         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9432         return 1;
9433 }
9434
9435 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9436         {
9437                 .dmi_id_list = &(const struct dmi_system_id[]) {
9438                         {
9439                                 .callback = intel_dmi_reverse_brightness,
9440                                 .ident = "NCR Corporation",
9441                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9442                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9443                                 },
9444                         },
9445                         { }  /* terminating entry */
9446                 },
9447                 .hook = quirk_invert_brightness,
9448         },
9449 };
9450
9451 static struct intel_quirk intel_quirks[] = {
9452         /* HP Mini needs pipe A force quirk (LP: #322104) */
9453         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9454
9455         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9456         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9457
9458         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9459         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9460
9461         /* 830/845 need to leave pipe A & dpll A up */
9462         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9463         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9464
9465         /* Lenovo U160 cannot use SSC on LVDS */
9466         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9467
9468         /* Sony Vaio Y cannot use SSC on LVDS */
9469         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9470
9471         /* Acer Aspire 5734Z must invert backlight brightness */
9472         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9473
9474         /* Acer/eMachines G725 */
9475         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9476
9477         /* Acer/eMachines e725 */
9478         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9479
9480         /* Acer/Packard Bell NCL20 */
9481         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9482
9483         /* Acer Aspire 4736Z */
9484         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9485 };
9486
9487 static void intel_init_quirks(struct drm_device *dev)
9488 {
9489         struct pci_dev *d = dev->pdev;
9490         int i;
9491
9492         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9493                 struct intel_quirk *q = &intel_quirks[i];
9494
9495                 if (d->device == q->device &&
9496                     (d->subsystem_vendor == q->subsystem_vendor ||
9497                      q->subsystem_vendor == PCI_ANY_ID) &&
9498                     (d->subsystem_device == q->subsystem_device ||
9499                      q->subsystem_device == PCI_ANY_ID))
9500                         q->hook(dev);
9501         }
9502         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9503                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9504                         intel_dmi_quirks[i].hook(dev);
9505         }
9506 }
9507
9508 /* Disable the VGA plane that we never use */
9509 static void i915_disable_vga(struct drm_device *dev)
9510 {
9511         struct drm_i915_private *dev_priv = dev->dev_private;
9512         u8 sr1;
9513         u32 vga_reg = i915_vgacntrl_reg(dev);
9514
9515         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9516         outb(SR01, VGA_SR_INDEX);
9517         sr1 = inb(VGA_SR_DATA);
9518         outb(sr1 | 1<<5, VGA_SR_DATA);
9519         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9520         udelay(300);
9521
9522         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9523         POSTING_READ(vga_reg);
9524 }
9525
9526 void intel_modeset_init_hw(struct drm_device *dev)
9527 {
9528         intel_init_power_well(dev);
9529
9530         intel_prepare_ddi(dev);
9531
9532         intel_init_clock_gating(dev);
9533
9534         mutex_lock(&dev->struct_mutex);
9535         intel_enable_gt_powersave(dev);
9536         mutex_unlock(&dev->struct_mutex);
9537 }
9538
9539 void intel_modeset_suspend_hw(struct drm_device *dev)
9540 {
9541         intel_suspend_hw(dev);
9542 }
9543
9544 void intel_modeset_init(struct drm_device *dev)
9545 {
9546         struct drm_i915_private *dev_priv = dev->dev_private;
9547         int i, j, ret;
9548
9549         drm_mode_config_init(dev);
9550
9551         dev->mode_config.min_width = 0;
9552         dev->mode_config.min_height = 0;
9553
9554         dev->mode_config.preferred_depth = 24;
9555         dev->mode_config.prefer_shadow = 1;
9556
9557         dev->mode_config.funcs = &intel_mode_funcs;
9558
9559         intel_init_quirks(dev);
9560
9561         intel_init_pm(dev);
9562
9563         if (INTEL_INFO(dev)->num_pipes == 0)
9564                 return;
9565
9566         intel_init_display(dev);
9567
9568         if (IS_GEN2(dev)) {
9569                 dev->mode_config.max_width = 2048;
9570                 dev->mode_config.max_height = 2048;
9571         } else if (IS_GEN3(dev)) {
9572                 dev->mode_config.max_width = 4096;
9573                 dev->mode_config.max_height = 4096;
9574         } else {
9575                 dev->mode_config.max_width = 8192;
9576                 dev->mode_config.max_height = 8192;
9577         }
9578         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9579
9580         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9581                       INTEL_INFO(dev)->num_pipes,
9582                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9583
9584         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9585                 intel_crtc_init(dev, i);
9586                 for (j = 0; j < dev_priv->num_plane; j++) {
9587                         ret = intel_plane_init(dev, i, j);
9588                         if (ret)
9589                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9590                                               pipe_name(i), sprite_name(i, j), ret);
9591                 }
9592         }
9593
9594         intel_cpu_pll_init(dev);
9595         intel_shared_dpll_init(dev);
9596
9597         /* Just disable it once at startup */
9598         i915_disable_vga(dev);
9599         intel_setup_outputs(dev);
9600
9601         /* Just in case the BIOS is doing something questionable. */
9602         intel_disable_fbc(dev);
9603 }
9604
9605 static void
9606 intel_connector_break_all_links(struct intel_connector *connector)
9607 {
9608         connector->base.dpms = DRM_MODE_DPMS_OFF;
9609         connector->base.encoder = NULL;
9610         connector->encoder->connectors_active = false;
9611         connector->encoder->base.crtc = NULL;
9612 }
9613
9614 static void intel_enable_pipe_a(struct drm_device *dev)
9615 {
9616         struct intel_connector *connector;
9617         struct drm_connector *crt = NULL;
9618         struct intel_load_detect_pipe load_detect_temp;
9619
9620         /* We can't just switch on the pipe A, we need to set things up with a
9621          * proper mode and output configuration. As a gross hack, enable pipe A
9622          * by enabling the load detect pipe once. */
9623         list_for_each_entry(connector,
9624                             &dev->mode_config.connector_list,
9625                             base.head) {
9626                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9627                         crt = &connector->base;
9628                         break;
9629                 }
9630         }
9631
9632         if (!crt)
9633                 return;
9634
9635         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9636                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9637
9638
9639 }
9640
9641 static bool
9642 intel_check_plane_mapping(struct intel_crtc *crtc)
9643 {
9644         struct drm_device *dev = crtc->base.dev;
9645         struct drm_i915_private *dev_priv = dev->dev_private;
9646         u32 reg, val;
9647
9648         if (INTEL_INFO(dev)->num_pipes == 1)
9649                 return true;
9650
9651         reg = DSPCNTR(!crtc->plane);
9652         val = I915_READ(reg);
9653
9654         if ((val & DISPLAY_PLANE_ENABLE) &&
9655             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9656                 return false;
9657
9658         return true;
9659 }
9660
9661 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9662 {
9663         struct drm_device *dev = crtc->base.dev;
9664         struct drm_i915_private *dev_priv = dev->dev_private;
9665         u32 reg;
9666
9667         /* Clear any frame start delays used for debugging left by the BIOS */
9668         reg = PIPECONF(crtc->config.cpu_transcoder);
9669         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9670
9671         /* We need to sanitize the plane -> pipe mapping first because this will
9672          * disable the crtc (and hence change the state) if it is wrong. Note
9673          * that gen4+ has a fixed plane -> pipe mapping.  */
9674         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9675                 struct intel_connector *connector;
9676                 bool plane;
9677
9678                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9679                               crtc->base.base.id);
9680
9681                 /* Pipe has the wrong plane attached and the plane is active.
9682                  * Temporarily change the plane mapping and disable everything
9683                  * ...  */
9684                 plane = crtc->plane;
9685                 crtc->plane = !plane;
9686                 dev_priv->display.crtc_disable(&crtc->base);
9687                 crtc->plane = plane;
9688
9689                 /* ... and break all links. */
9690                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9691                                     base.head) {
9692                         if (connector->encoder->base.crtc != &crtc->base)
9693                                 continue;
9694
9695                         intel_connector_break_all_links(connector);
9696                 }
9697
9698                 WARN_ON(crtc->active);
9699                 crtc->base.enabled = false;
9700         }
9701
9702         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9703             crtc->pipe == PIPE_A && !crtc->active) {
9704                 /* BIOS forgot to enable pipe A, this mostly happens after
9705                  * resume. Force-enable the pipe to fix this, the update_dpms
9706                  * call below we restore the pipe to the right state, but leave
9707                  * the required bits on. */
9708                 intel_enable_pipe_a(dev);
9709         }
9710
9711         /* Adjust the state of the output pipe according to whether we
9712          * have active connectors/encoders. */
9713         intel_crtc_update_dpms(&crtc->base);
9714
9715         if (crtc->active != crtc->base.enabled) {
9716                 struct intel_encoder *encoder;
9717
9718                 /* This can happen either due to bugs in the get_hw_state
9719                  * functions or because the pipe is force-enabled due to the
9720                  * pipe A quirk. */
9721                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9722                               crtc->base.base.id,
9723                               crtc->base.enabled ? "enabled" : "disabled",
9724                               crtc->active ? "enabled" : "disabled");
9725
9726                 crtc->base.enabled = crtc->active;
9727
9728                 /* Because we only establish the connector -> encoder ->
9729                  * crtc links if something is active, this means the
9730                  * crtc is now deactivated. Break the links. connector
9731                  * -> encoder links are only establish when things are
9732                  *  actually up, hence no need to break them. */
9733                 WARN_ON(crtc->active);
9734
9735                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9736                         WARN_ON(encoder->connectors_active);
9737                         encoder->base.crtc = NULL;
9738                 }
9739         }
9740 }
9741
9742 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9743 {
9744         struct intel_connector *connector;
9745         struct drm_device *dev = encoder->base.dev;
9746
9747         /* We need to check both for a crtc link (meaning that the
9748          * encoder is active and trying to read from a pipe) and the
9749          * pipe itself being active. */
9750         bool has_active_crtc = encoder->base.crtc &&
9751                 to_intel_crtc(encoder->base.crtc)->active;
9752
9753         if (encoder->connectors_active && !has_active_crtc) {
9754                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9755                               encoder->base.base.id,
9756                               drm_get_encoder_name(&encoder->base));
9757
9758                 /* Connector is active, but has no active pipe. This is
9759                  * fallout from our resume register restoring. Disable
9760                  * the encoder manually again. */
9761                 if (encoder->base.crtc) {
9762                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9763                                       encoder->base.base.id,
9764                                       drm_get_encoder_name(&encoder->base));
9765                         encoder->disable(encoder);
9766                 }
9767
9768                 /* Inconsistent output/port/pipe state happens presumably due to
9769                  * a bug in one of the get_hw_state functions. Or someplace else
9770                  * in our code, like the register restore mess on resume. Clamp
9771                  * things to off as a safer default. */
9772                 list_for_each_entry(connector,
9773                                     &dev->mode_config.connector_list,
9774                                     base.head) {
9775                         if (connector->encoder != encoder)
9776                                 continue;
9777
9778                         intel_connector_break_all_links(connector);
9779                 }
9780         }
9781         /* Enabled encoders without active connectors will be fixed in
9782          * the crtc fixup. */
9783 }
9784
9785 void i915_redisable_vga(struct drm_device *dev)
9786 {
9787         struct drm_i915_private *dev_priv = dev->dev_private;
9788         u32 vga_reg = i915_vgacntrl_reg(dev);
9789
9790         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9791                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9792                 i915_disable_vga(dev);
9793         }
9794 }
9795
9796 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9797 {
9798         struct drm_i915_private *dev_priv = dev->dev_private;
9799         enum pipe pipe;
9800         struct intel_crtc *crtc;
9801         struct intel_encoder *encoder;
9802         struct intel_connector *connector;
9803         int i;
9804
9805         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9806                             base.head) {
9807                 memset(&crtc->config, 0, sizeof(crtc->config));
9808
9809                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9810                                                                  &crtc->config);
9811
9812                 crtc->base.enabled = crtc->active;
9813
9814                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9815                               crtc->base.base.id,
9816                               crtc->active ? "enabled" : "disabled");
9817         }
9818
9819         /* FIXME: Smash this into the new shared dpll infrastructure. */
9820         if (HAS_DDI(dev))
9821                 intel_ddi_setup_hw_pll_state(dev);
9822
9823         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9824                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9825
9826                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9827                 pll->active = 0;
9828                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9829                                     base.head) {
9830                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9831                                 pll->active++;
9832                 }
9833                 pll->refcount = pll->active;
9834
9835                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9836                               pll->name, pll->refcount);
9837         }
9838
9839         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9840                             base.head) {
9841                 pipe = 0;
9842
9843                 if (encoder->get_hw_state(encoder, &pipe)) {
9844                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9845                         encoder->base.crtc = &crtc->base;
9846                         if (encoder->get_config)
9847                                 encoder->get_config(encoder, &crtc->config);
9848                 } else {
9849                         encoder->base.crtc = NULL;
9850                 }
9851
9852                 encoder->connectors_active = false;
9853                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9854                               encoder->base.base.id,
9855                               drm_get_encoder_name(&encoder->base),
9856                               encoder->base.crtc ? "enabled" : "disabled",
9857                               pipe);
9858         }
9859
9860         list_for_each_entry(connector, &dev->mode_config.connector_list,
9861                             base.head) {
9862                 if (connector->get_hw_state(connector)) {
9863                         connector->base.dpms = DRM_MODE_DPMS_ON;
9864                         connector->encoder->connectors_active = true;
9865                         connector->base.encoder = &connector->encoder->base;
9866                 } else {
9867                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9868                         connector->base.encoder = NULL;
9869                 }
9870                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9871                               connector->base.base.id,
9872                               drm_get_connector_name(&connector->base),
9873                               connector->base.encoder ? "enabled" : "disabled");
9874         }
9875 }
9876
9877 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9878  * and i915 state tracking structures. */
9879 void intel_modeset_setup_hw_state(struct drm_device *dev,
9880                                   bool force_restore)
9881 {
9882         struct drm_i915_private *dev_priv = dev->dev_private;
9883         enum pipe pipe;
9884         struct drm_plane *plane;
9885         struct intel_crtc *crtc;
9886         struct intel_encoder *encoder;
9887
9888         intel_modeset_readout_hw_state(dev);
9889
9890         /* HW state is read out, now we need to sanitize this mess. */
9891         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9892                             base.head) {
9893                 intel_sanitize_encoder(encoder);
9894         }
9895
9896         for_each_pipe(pipe) {
9897                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9898                 intel_sanitize_crtc(crtc);
9899                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9900         }
9901
9902         if (force_restore) {
9903                 /*
9904                  * We need to use raw interfaces for restoring state to avoid
9905                  * checking (bogus) intermediate states.
9906                  */
9907                 for_each_pipe(pipe) {
9908                         struct drm_crtc *crtc =
9909                                 dev_priv->pipe_to_crtc_mapping[pipe];
9910
9911                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9912                                          crtc->fb);
9913                 }
9914                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9915                         intel_plane_restore(plane);
9916
9917                 i915_redisable_vga(dev);
9918         } else {
9919                 intel_modeset_update_staged_output_state(dev);
9920         }
9921
9922         intel_modeset_check_state(dev);
9923
9924         drm_mode_config_reset(dev);
9925 }
9926
9927 void intel_modeset_gem_init(struct drm_device *dev)
9928 {
9929         intel_modeset_init_hw(dev);
9930
9931         intel_setup_overlay(dev);
9932
9933         intel_modeset_setup_hw_state(dev, false);
9934 }
9935
9936 void intel_modeset_cleanup(struct drm_device *dev)
9937 {
9938         struct drm_i915_private *dev_priv = dev->dev_private;
9939         struct drm_crtc *crtc;
9940         struct intel_crtc *intel_crtc;
9941
9942         /*
9943          * Interrupts and polling as the first thing to avoid creating havoc.
9944          * Too much stuff here (turning of rps, connectors, ...) would
9945          * experience fancy races otherwise.
9946          */
9947         drm_irq_uninstall(dev);
9948         cancel_work_sync(&dev_priv->hotplug_work);
9949         /*
9950          * Due to the hpd irq storm handling the hotplug work can re-arm the
9951          * poll handlers. Hence disable polling after hpd handling is shut down.
9952          */
9953         drm_kms_helper_poll_fini(dev);
9954
9955         mutex_lock(&dev->struct_mutex);
9956
9957         intel_unregister_dsm_handler();
9958
9959         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9960                 /* Skip inactive CRTCs */
9961                 if (!crtc->fb)
9962                         continue;
9963
9964                 intel_crtc = to_intel_crtc(crtc);
9965                 intel_increase_pllclock(crtc);
9966         }
9967
9968         intel_disable_fbc(dev);
9969
9970         intel_disable_gt_powersave(dev);
9971
9972         ironlake_teardown_rc6(dev);
9973
9974         mutex_unlock(&dev->struct_mutex);
9975
9976         /* flush any delayed tasks or pending work */
9977         flush_scheduled_work();
9978
9979         /* destroy backlight, if any, before the connectors */
9980         intel_panel_destroy_backlight(dev);
9981
9982         drm_mode_config_cleanup(dev);
9983
9984         intel_cleanup_overlay(dev);
9985 }
9986
9987 /*
9988  * Return which encoder is currently attached for connector.
9989  */
9990 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9991 {
9992         return &intel_attached_encoder(connector)->base;
9993 }
9994
9995 void intel_connector_attach_encoder(struct intel_connector *connector,
9996                                     struct intel_encoder *encoder)
9997 {
9998         connector->encoder = encoder;
9999         drm_mode_connector_attach_encoder(&connector->base,
10000                                           &encoder->base);
10001 }
10002
10003 /*
10004  * set vga decode state - true == enable VGA decode
10005  */
10006 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10007 {
10008         struct drm_i915_private *dev_priv = dev->dev_private;
10009         u16 gmch_ctrl;
10010
10011         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10012         if (state)
10013                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10014         else
10015                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10016         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10017         return 0;
10018 }
10019
10020 #ifdef CONFIG_DEBUG_FS
10021 #include <linux/seq_file.h>
10022
10023 struct intel_display_error_state {
10024
10025         u32 power_well_driver;
10026
10027         struct intel_cursor_error_state {
10028                 u32 control;
10029                 u32 position;
10030                 u32 base;
10031                 u32 size;
10032         } cursor[I915_MAX_PIPES];
10033
10034         struct intel_pipe_error_state {
10035                 enum transcoder cpu_transcoder;
10036                 u32 conf;
10037                 u32 source;
10038
10039                 u32 htotal;
10040                 u32 hblank;
10041                 u32 hsync;
10042                 u32 vtotal;
10043                 u32 vblank;
10044                 u32 vsync;
10045         } pipe[I915_MAX_PIPES];
10046
10047         struct intel_plane_error_state {
10048                 u32 control;
10049                 u32 stride;
10050                 u32 size;
10051                 u32 pos;
10052                 u32 addr;
10053                 u32 surface;
10054                 u32 tile_offset;
10055         } plane[I915_MAX_PIPES];
10056 };
10057
10058 struct intel_display_error_state *
10059 intel_display_capture_error_state(struct drm_device *dev)
10060 {
10061         drm_i915_private_t *dev_priv = dev->dev_private;
10062         struct intel_display_error_state *error;
10063         enum transcoder cpu_transcoder;
10064         int i;
10065
10066         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10067         if (error == NULL)
10068                 return NULL;
10069
10070         if (HAS_POWER_WELL(dev))
10071                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10072
10073         for_each_pipe(i) {
10074                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10075                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10076
10077                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10078                         error->cursor[i].control = I915_READ(CURCNTR(i));
10079                         error->cursor[i].position = I915_READ(CURPOS(i));
10080                         error->cursor[i].base = I915_READ(CURBASE(i));
10081                 } else {
10082                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10083                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10084                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10085                 }
10086
10087                 error->plane[i].control = I915_READ(DSPCNTR(i));
10088                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10089                 if (INTEL_INFO(dev)->gen <= 3) {
10090                         error->plane[i].size = I915_READ(DSPSIZE(i));
10091                         error->plane[i].pos = I915_READ(DSPPOS(i));
10092                 }
10093                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10094                         error->plane[i].addr = I915_READ(DSPADDR(i));
10095                 if (INTEL_INFO(dev)->gen >= 4) {
10096                         error->plane[i].surface = I915_READ(DSPSURF(i));
10097                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10098                 }
10099
10100                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10101                 error->pipe[i].source = I915_READ(PIPESRC(i));
10102                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10103                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10104                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10105                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10106                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10107                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10108         }
10109
10110         /* In the code above we read the registers without checking if the power
10111          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10112          * prevent the next I915_WRITE from detecting it and printing an error
10113          * message. */
10114         if (HAS_POWER_WELL(dev))
10115                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10116
10117         return error;
10118 }
10119
10120 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10121
10122 void
10123 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10124                                 struct drm_device *dev,
10125                                 struct intel_display_error_state *error)
10126 {
10127         int i;
10128
10129         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10130         if (HAS_POWER_WELL(dev))
10131                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10132                            error->power_well_driver);
10133         for_each_pipe(i) {
10134                 err_printf(m, "Pipe [%d]:\n", i);
10135                 err_printf(m, "  CPU transcoder: %c\n",
10136                            transcoder_name(error->pipe[i].cpu_transcoder));
10137                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10138                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10139                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10140                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10141                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10142                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10143                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10144                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10145
10146                 err_printf(m, "Plane [%d]:\n", i);
10147                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10148                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10149                 if (INTEL_INFO(dev)->gen <= 3) {
10150                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10151                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10152                 }
10153                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10154                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10155                 if (INTEL_INFO(dev)->gen >= 4) {
10156                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10157                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10158                 }
10159
10160                 err_printf(m, "Cursor [%d]:\n", i);
10161                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10162                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10163                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10164         }
10165 }
10166 #endif