Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 typedef struct {
  54         int     min, max;
  55 } intel_range_t;
  56
  57 typedef struct {
  58         int     dot_limit;
  59         int     p2_slow, p2_fast;
  60 } intel_p2_t;
  61
  62 typedef struct intel_limit intel_limit_t;
  63 struct intel_limit {
  64         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  65         intel_p2_t          p2;
  66 };
  67
  68 /* FDI */
  69 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv_dac = {
 313         .dot = { .min = 25000, .max = 270000 },
 314         .vco = { .min = 4000000, .max = 6000000 },
 315         .n = { .min = 1, .max = 7 },
 316         .m = { .min = 22, .max = 450 }, /* guess */
 317         .m1 = { .min = 2, .max = 3 },
 318         .m2 = { .min = 11, .max = 156 },
 319         .p = { .min = 10, .max = 30 },
 320         .p1 = { .min = 1, .max = 3 },
 321         .p2 = { .dot_limit = 270000,
 322                 .p2_slow = 2, .p2_fast = 20 },
 323 };
 324
 325 static const intel_limit_t intel_limits_vlv_hdmi = {
 326         .dot = { .min = 25000, .max = 270000 },
 327         .vco = { .min = 4000000, .max = 6000000 },
 328         .n = { .min = 1, .max = 7 },
 329         .m = { .min = 60, .max = 300 }, /* guess */
 330         .m1 = { .min = 2, .max = 3 },
 331         .m2 = { .min = 11, .max = 156 },
 332         .p = { .min = 10, .max = 30 },
 333         .p1 = { .min = 2, .max = 3 },
 334         .p2 = { .dot_limit = 270000,
 335                 .p2_slow = 2, .p2_fast = 20 },
 336 };
 337
 338 static const intel_limit_t intel_limits_vlv_dp = {
 339         .dot = { .min = 25000, .max = 270000 },
 340         .vco = { .min = 4000000, .max = 6000000 },
 341         .n = { .min = 1, .max = 7 },
 342         .m = { .min = 22, .max = 450 },
 343         .m1 = { .min = 2, .max = 3 },
 344         .m2 = { .min = 11, .max = 156 },
 345         .p = { .min = 10, .max = 30 },
 346         .p1 = { .min = 1, .max = 3 },
 347         .p2 = { .dot_limit = 270000,
 348                 .p2_slow = 2, .p2_fast = 20 },
 349 };
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 412                         limit = &intel_limits_vlv_dac;
 413                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 414                         limit = &intel_limits_vlv_hdmi;
 415                 else
 416                         limit = &intel_limits_vlv_dp;
 417         } else if (!IS_GEN2(dev)) {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i9xx_lvds;
 420                 else
 421                         limit = &intel_limits_i9xx_sdvo;
 422         } else {
 423                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 424                         limit = &intel_limits_i8xx_lvds;
 425                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 426                         limit = &intel_limits_i8xx_dvo;
 427                 else
 428                         limit = &intel_limits_i8xx_dac;
 429         }
 430         return limit;
 431 }
 432
 433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 434 static void pineview_clock(int refclk, intel_clock_t *clock)
 435 {
 436         clock->m = clock->m2 + 2;
 437         clock->p = clock->p1 * clock->p2;
 438         clock->vco = refclk * clock->m / clock->n;
 439         clock->dot = clock->vco / clock->p;
 440 }
 441
 442 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 443 {
 444         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 445 }
 446
 447 static void i9xx_clock(int refclk, intel_clock_t *clock)
 448 {
 449         clock->m = i9xx_dpll_compute_m(clock);
 450         clock->p = clock->p1 * clock->p2;
 451         clock->vco = refclk * clock->m / (clock->n + 2);
 452         clock->dot = clock->vco / clock->p;
 453 }
 454
 455 /**
 456  * Returns whether any output on the specified pipe is of the specified type
 457  */
 458 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 459 {
 460         struct drm_device *dev = crtc->dev;
 461         struct intel_encoder *encoder;
 462
 463         for_each_encoder_on_crtc(dev, crtc, encoder)
 464                 if (encoder->type == type)
 465                         return true;
 466
 467         return false;
 468 }
 469
 470 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 471 /**
 472  * Returns whether the given set of divisors are valid for a given refclk with
 473  * the given connectors.
 474  */
 475
 476 static bool intel_PLL_is_valid(struct drm_device *dev,
 477                                const intel_limit_t *limit,
 478                                const intel_clock_t *clock)
 479 {
 480         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 481                 INTELPllInvalid("p1 out of range\n");
 482         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 483                 INTELPllInvalid("p out of range\n");
 484         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 485                 INTELPllInvalid("m2 out of range\n");
 486         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 487                 INTELPllInvalid("m1 out of range\n");
 488         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 489                 INTELPllInvalid("m1 <= m2\n");
 490         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 491                 INTELPllInvalid("m out of range\n");
 492         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 493                 INTELPllInvalid("n out of range\n");
 494         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 495                 INTELPllInvalid("vco out of range\n");
 496         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 497          * connector, etc., rather than just a single range.
 498          */
 499         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 500                 INTELPllInvalid("dot out of range\n");
 501
 502         return true;
 503 }
 504
 505 static bool
 506 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 507                     int target, int refclk, intel_clock_t *match_clock,
 508                     intel_clock_t *best_clock)
 509 {
 510         struct drm_device *dev = crtc->dev;
 511         intel_clock_t clock;
 512         int err = target;
 513
 514         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 515                 /*
 516                  * For LVDS just rely on its current settings for dual-channel.
 517                  * We haven't figured out how to reliably set up different
 518                  * single/dual channel state, if we even can.
 519                  */
 520                 if (intel_is_dual_link_lvds(dev))
 521                         clock.p2 = limit->p2.p2_fast;
 522                 else
 523                         clock.p2 = limit->p2.p2_slow;
 524         } else {
 525                 if (target < limit->p2.dot_limit)
 526                         clock.p2 = limit->p2.p2_slow;
 527                 else
 528                         clock.p2 = limit->p2.p2_fast;
 529         }
 530
 531         memset(best_clock, 0, sizeof(*best_clock));
 532
 533         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 534              clock.m1++) {
 535                 for (clock.m2 = limit->m2.min;
 536                      clock.m2 <= limit->m2.max; clock.m2++) {
 537                         if (clock.m2 >= clock.m1)
 538                                 break;
 539                         for (clock.n = limit->n.min;
 540                              clock.n <= limit->n.max; clock.n++) {
 541                                 for (clock.p1 = limit->p1.min;
 542                                         clock.p1 <= limit->p1.max; clock.p1++) {
 543                                         int this_err;
 544
 545                                         i9xx_clock(refclk, &clock);
 546                                         if (!intel_PLL_is_valid(dev, limit,
 547                                                                 &clock))
 548                                                 continue;
 549                                         if (match_clock &&
 550                                             clock.p != match_clock->p)
 551                                                 continue;
 552
 553                                         this_err = abs(clock.dot - target);
 554                                         if (this_err < err) {
 555                                                 *best_clock = clock;
 556                                                 err = this_err;
 557                                         }
 558                                 }
 559                         }
 560                 }
 561         }
 562
 563         return (err != target);
 564 }
 565
 566 static bool
 567 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 568                    int target, int refclk, intel_clock_t *match_clock,
 569                    intel_clock_t *best_clock)
 570 {
 571         struct drm_device *dev = crtc->dev;
 572         intel_clock_t clock;
 573         int err = target;
 574
 575         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 576                 /*
 577                  * For LVDS just rely on its current settings for dual-channel.
 578                  * We haven't figured out how to reliably set up different
 579                  * single/dual channel state, if we even can.
 580                  */
 581                 if (intel_is_dual_link_lvds(dev))
 582                         clock.p2 = limit->p2.p2_fast;
 583                 else
 584                         clock.p2 = limit->p2.p2_slow;
 585         } else {
 586                 if (target < limit->p2.dot_limit)
 587                         clock.p2 = limit->p2.p2_slow;
 588                 else
 589                         clock.p2 = limit->p2.p2_fast;
 590         }
 591
 592         memset(best_clock, 0, sizeof(*best_clock));
 593
 594         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 595              clock.m1++) {
 596                 for (clock.m2 = limit->m2.min;
 597                      clock.m2 <= limit->m2.max; clock.m2++) {
 598                         for (clock.n = limit->n.min;
 599                              clock.n <= limit->n.max; clock.n++) {
 600                                 for (clock.p1 = limit->p1.min;
 601                                         clock.p1 <= limit->p1.max; clock.p1++) {
 602                                         int this_err;
 603
 604                                         pineview_clock(refclk, &clock);
 605                                         if (!intel_PLL_is_valid(dev, limit,
 606                                                                 &clock))
 607                                                 continue;
 608                                         if (match_clock &&
 609                                             clock.p != match_clock->p)
 610                                                 continue;
 611
 612                                         this_err = abs(clock.dot - target);
 613                                         if (this_err < err) {
 614                                                 *best_clock = clock;
 615                                                 err = this_err;
 616                                         }
 617                                 }
 618                         }
 619                 }
 620         }
 621
 622         return (err != target);
 623 }
 624
 625 static bool
 626 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 627                    int target, int refclk, intel_clock_t *match_clock,
 628                    intel_clock_t *best_clock)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         intel_clock_t clock;
 632         int max_n;
 633         bool found;
 634         /* approximately equals target * 0.00585 */
 635         int err_most = (target >> 8) + (target >> 9);
 636         found = false;
 637
 638         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 639                 if (intel_is_dual_link_lvds(dev))
 640                         clock.p2 = limit->p2.p2_fast;
 641                 else
 642                         clock.p2 = limit->p2.p2_slow;
 643         } else {
 644                 if (target < limit->p2.dot_limit)
 645                         clock.p2 = limit->p2.p2_slow;
 646                 else
 647                         clock.p2 = limit->p2.p2_fast;
 648         }
 649
 650         memset(best_clock, 0, sizeof(*best_clock));
 651         max_n = limit->n.max;
 652         /* based on hardware requirement, prefer smaller n to precision */
 653         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 654                 /* based on hardware requirement, prefere larger m1,m2 */
 655                 for (clock.m1 = limit->m1.max;
 656                      clock.m1 >= limit->m1.min; clock.m1--) {
 657                         for (clock.m2 = limit->m2.max;
 658                              clock.m2 >= limit->m2.min; clock.m2--) {
 659                                 for (clock.p1 = limit->p1.max;
 660                                      clock.p1 >= limit->p1.min; clock.p1--) {
 661                                         int this_err;
 662
 663                                         i9xx_clock(refclk, &clock);
 664                                         if (!intel_PLL_is_valid(dev, limit,
 665                                                                 &clock))
 666                                                 continue;
 667
 668                                         this_err = abs(clock.dot - target);
 669                                         if (this_err < err_most) {
 670                                                 *best_clock = clock;
 671                                                 err_most = this_err;
 672                                                 max_n = clock.n;
 673                                                 found = true;
 674                                         }
 675                                 }
 676                         }
 677                 }
 678         }
 679         return found;
 680 }
 681
 682 static bool
 683 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 684                    int target, int refclk, intel_clock_t *match_clock,
 685                    intel_clock_t *best_clock)
 686 {
 687         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 688         u32 m, n, fastclk;
 689         u32 updrate, minupdate, fracbits, p;
 690         unsigned long bestppm, ppm, absppm;
 691         int dotclk, flag;
 692
 693         flag = 0;
 694         dotclk = target * 1000;
 695         bestppm = 1000000;
 696         ppm = absppm = 0;
 697         fastclk = dotclk / (2*100);
 698         updrate = 0;
 699         minupdate = 19200;
 700         fracbits = 1;
 701         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 702         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 703
 704         /* based on hardware requirement, prefer smaller n to precision */
 705         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 706                 updrate = refclk / n;
 707                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 708                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 709                                 if (p2 > 10)
 710                                         p2 = p2 - 1;
 711                                 p = p1 * p2;
 712                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 713                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 714                                         m2 = (((2*(fastclk * p * n / m1 )) +
 715                                                refclk) / (2*refclk));
 716                                         m = m1 * m2;
 717                                         vco = updrate * m;
 718                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 719                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 720                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 721                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 722                                                         bestppm = 0;
 723                                                         flag = 1;
 724                                                 }
 725                                                 if (absppm < bestppm - 10) {
 726                                                         bestppm = absppm;
 727                                                         flag = 1;
 728                                                 }
 729                                                 if (flag) {
 730                                                         bestn = n;
 731                                                         bestm1 = m1;
 732                                                         bestm2 = m2;
 733                                                         bestp1 = p1;
 734                                                         bestp2 = p2;
 735                                                         flag = 0;
 736                                                 }
 737                                         }
 738                                 }
 739                         }
 740                 }
 741         }
 742         best_clock->n = bestn;
 743         best_clock->m1 = bestm1;
 744         best_clock->m2 = bestm2;
 745         best_clock->p1 = bestp1;
 746         best_clock->p2 = bestp2;
 747
 748         return true;
 749 }
 750
 751 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 752                                              enum pipe pipe)
 753 {
 754         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 756
 757         return intel_crtc->config.cpu_transcoder;
 758 }
 759
 760 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         u32 frame, frame_reg = PIPEFRAME(pipe);
 764
 765         frame = I915_READ(frame_reg);
 766
 767         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 768                 DRM_DEBUG_KMS("vblank wait timed out\n");
 769 }
 770
 771 /**
 772  * intel_wait_for_vblank - wait for vblank on a given pipe
 773  * @dev: drm device
 774  * @pipe: pipe to wait for
 775  *
 776  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 777  * mode setting code.
 778  */
 779 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int pipestat_reg = PIPESTAT(pipe);
 783
 784         if (INTEL_INFO(dev)->gen >= 5) {
 785                 ironlake_wait_for_vblank(dev, pipe);
 786                 return;
 787         }
 788
 789         /* Clear existing vblank status. Note this will clear any other
 790          * sticky status fields as well.
 791          *
 792          * This races with i915_driver_irq_handler() with the result
 793          * that either function could miss a vblank event.  Here it is not
 794          * fatal, as we will either wait upon the next vblank interrupt or
 795          * timeout.  Generally speaking intel_wait_for_vblank() is only
 796          * called during modeset at which time the GPU should be idle and
 797          * should *not* be performing page flips and thus not waiting on
 798          * vblanks...
 799          * Currently, the result of us stealing a vblank from the irq
 800          * handler is that a single frame will be skipped during swapbuffers.
 801          */
 802         I915_WRITE(pipestat_reg,
 803                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 804
 805         /* Wait for vblank interrupt bit to set */
 806         if (wait_for(I915_READ(pipestat_reg) &
 807                      PIPE_VBLANK_INTERRUPT_STATUS,
 808                      50))
 809                 DRM_DEBUG_KMS("vblank wait timed out\n");
 810 }
 811
 812 /*
 813  * intel_wait_for_pipe_off - wait for pipe to turn off
 814  * @dev: drm device
 815  * @pipe: pipe to wait for
 816  *
 817  * After disabling a pipe, we can't wait for vblank in the usual way,
 818  * spinning on the vblank interrupt status bit, since we won't actually
 819  * see an interrupt when the pipe is disabled.
 820  *
 821  * On Gen4 and above:
 822  *   wait for the pipe register state bit to turn off
 823  *
 824  * Otherwise:
 825  *   wait for the display line value to settle (it usually
 826  *   ends up stopping at the start of the next frame).
 827  *
 828  */
 829 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 830 {
 831         struct drm_i915_private *dev_priv = dev->dev_private;
 832         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 833                                                                       pipe);
 834
 835         if (INTEL_INFO(dev)->gen >= 4) {
 836                 int reg = PIPECONF(cpu_transcoder);
 837
 838                 /* Wait for the Pipe State to go off */
 839                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 840                              100))
 841                         WARN(1, "pipe_off wait timed out\n");
 842         } else {
 843                 u32 last_line, line_mask;
 844                 int reg = PIPEDSL(pipe);
 845                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 846
 847                 if (IS_GEN2(dev))
 848                         line_mask = DSL_LINEMASK_GEN2;
 849                 else
 850                         line_mask = DSL_LINEMASK_GEN3;
 851
 852                 /* Wait for the display line to settle */
 853                 do {
 854                         last_line = I915_READ(reg) & line_mask;
 855                         mdelay(5);
 856                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 857                          time_after(timeout, jiffies));
 858                 if (time_after(jiffies, timeout))
 859                         WARN(1, "pipe_off wait timed out\n");
 860         }
 861 }
 862
 863 /*
 864  * ibx_digital_port_connected - is the specified port connected?
 865  * @dev_priv: i915 private structure
 866  * @port: the port to test
 867  *
 868  * Returns true if @port is connected, false otherwise.
 869  */
 870 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 871                                 struct intel_digital_port *port)
 872 {
 873         u32 bit;
 874
 875         if (HAS_PCH_IBX(dev_priv->dev)) {
 876                 switch(port->port) {
 877                 case PORT_B:
 878                         bit = SDE_PORTB_HOTPLUG;
 879                         break;
 880                 case PORT_C:
 881                         bit = SDE_PORTC_HOTPLUG;
 882                         break;
 883                 case PORT_D:
 884                         bit = SDE_PORTD_HOTPLUG;
 885                         break;
 886                 default:
 887                         return true;
 888                 }
 889         } else {
 890                 switch(port->port) {
 891                 case PORT_B:
 892                         bit = SDE_PORTB_HOTPLUG_CPT;
 893                         break;
 894                 case PORT_C:
 895                         bit = SDE_PORTC_HOTPLUG_CPT;
 896                         break;
 897                 case PORT_D:
 898                         bit = SDE_PORTD_HOTPLUG_CPT;
 899                         break;
 900                 default:
 901                         return true;
 902                 }
 903         }
 904
 905         return I915_READ(SDEISR) & bit;
 906 }
 907
 908 static const char *state_string(bool enabled)
 909 {
 910         return enabled ? "on" : "off";
 911 }
 912
 913 /* Only for pre-ILK configs */
 914 void assert_pll(struct drm_i915_private *dev_priv,
 915                 enum pipe pipe, bool state)
 916 {
 917         int reg;
 918         u32 val;
 919         bool cur_state;
 920
 921         reg = DPLL(pipe);
 922         val = I915_READ(reg);
 923         cur_state = !!(val & DPLL_VCO_ENABLE);
 924         WARN(cur_state != state,
 925              "PLL state assertion failure (expected %s, current %s)\n",
 926              state_string(state), state_string(cur_state));
 927 }
 928
 929 struct intel_shared_dpll *
 930 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 931 {
 932         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 933
 934         if (crtc->config.shared_dpll < 0)
 935                 return NULL;
 936
 937         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 938 }
 939
 940 /* For ILK+ */
 941 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 942                         struct intel_shared_dpll *pll,
 943                         bool state)
 944 {
 945         bool cur_state;
 946         struct intel_dpll_hw_state hw_state;
 947
 948         if (HAS_PCH_LPT(dev_priv->dev)) {
 949                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 950                 return;
 951         }
 952
 953         if (WARN (!pll,
 954                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 955                 return;
 956
 957         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 958         WARN(cur_state != state,
 959              "%s assertion failure (expected %s, current %s)\n",
 960              pll->name, state_string(state), state_string(cur_state));
 961 }
 962
 963 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 964                           enum pipe pipe, bool state)
 965 {
 966         int reg;
 967         u32 val;
 968         bool cur_state;
 969         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 970                                                                       pipe);
 971
 972         if (HAS_DDI(dev_priv->dev)) {
 973                 /* DDI does not have a specific FDI_TX register */
 974                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 975                 val = I915_READ(reg);
 976                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 977         } else {
 978                 reg = FDI_TX_CTL(pipe);
 979                 val = I915_READ(reg);
 980                 cur_state = !!(val & FDI_TX_ENABLE);
 981         }
 982         WARN(cur_state != state,
 983              "FDI TX state assertion failure (expected %s, current %s)\n",
 984              state_string(state), state_string(cur_state));
 985 }
 986 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 987 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 988
 989 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 990                           enum pipe pipe, bool state)
 991 {
 992         int reg;
 993         u32 val;
 994         bool cur_state;
 995
 996         reg = FDI_RX_CTL(pipe);
 997         val = I915_READ(reg);
 998         cur_state = !!(val & FDI_RX_ENABLE);
 999         WARN(cur_state != state,
1000              "FDI RX state assertion failure (expected %s, current %s)\n",
1001              state_string(state), state_string(cur_state));
1002 }
1003 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1004 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1005
1006 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1007                                       enum pipe pipe)
1008 {
1009         int reg;
1010         u32 val;
1011
1012         /* ILK FDI PLL is always enabled */
1013         if (dev_priv->info->gen == 5)
1014                 return;
1015
1016         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1017         if (HAS_DDI(dev_priv->dev))
1018                 return;
1019
1020         reg = FDI_TX_CTL(pipe);
1021         val = I915_READ(reg);
1022         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1023 }
1024
1025 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1026                        enum pipe pipe, bool state)
1027 {
1028         int reg;
1029         u32 val;
1030         bool cur_state;
1031
1032         reg = FDI_RX_CTL(pipe);
1033         val = I915_READ(reg);
1034         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1035         WARN(cur_state != state,
1036              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1037              state_string(state), state_string(cur_state));
1038 }
1039
1040 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1041                                   enum pipe pipe)
1042 {
1043         int pp_reg, lvds_reg;
1044         u32 val;
1045         enum pipe panel_pipe = PIPE_A;
1046         bool locked = true;
1047
1048         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1049                 pp_reg = PCH_PP_CONTROL;
1050                 lvds_reg = PCH_LVDS;
1051         } else {
1052                 pp_reg = PP_CONTROL;
1053                 lvds_reg = LVDS;
1054         }
1055
1056         val = I915_READ(pp_reg);
1057         if (!(val & PANEL_POWER_ON) ||
1058             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1059                 locked = false;
1060
1061         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1062                 panel_pipe = PIPE_B;
1063
1064         WARN(panel_pipe == pipe && locked,
1065              "panel assertion failure, pipe %c regs locked\n",
1066              pipe_name(pipe));
1067 }
1068
1069 void assert_pipe(struct drm_i915_private *dev_priv,
1070                  enum pipe pipe, bool state)
1071 {
1072         int reg;
1073         u32 val;
1074         bool cur_state;
1075         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1076                                                                       pipe);
1077
1078         /* if we need the pipe A quirk it must be always on */
1079         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1080                 state = true;
1081
1082         if (!intel_display_power_enabled(dev_priv->dev,
1083                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1084                 cur_state = false;
1085         } else {
1086                 reg = PIPECONF(cpu_transcoder);
1087                 val = I915_READ(reg);
1088                 cur_state = !!(val & PIPECONF_ENABLE);
1089         }
1090
1091         WARN(cur_state != state,
1092              "pipe %c assertion failure (expected %s, current %s)\n",
1093              pipe_name(pipe), state_string(state), state_string(cur_state));
1094 }
1095
1096 static void assert_plane(struct drm_i915_private *dev_priv,
1097                          enum plane plane, bool state)
1098 {
1099         int reg;
1100         u32 val;
1101         bool cur_state;
1102
1103         reg = DSPCNTR(plane);
1104         val = I915_READ(reg);
1105         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1106         WARN(cur_state != state,
1107              "plane %c assertion failure (expected %s, current %s)\n",
1108              plane_name(plane), state_string(state), state_string(cur_state));
1109 }
1110
1111 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1112 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1113
1114 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1115                                    enum pipe pipe)
1116 {
1117         struct drm_device *dev = dev_priv->dev;
1118         int reg, i;
1119         u32 val;
1120         int cur_pipe;
1121
1122         /* Primary planes are fixed to pipes on gen4+ */
1123         if (INTEL_INFO(dev)->gen >= 4) {
1124                 reg = DSPCNTR(pipe);
1125                 val = I915_READ(reg);
1126                 WARN((val & DISPLAY_PLANE_ENABLE),
1127                      "plane %c assertion failure, should be disabled but not\n",
1128                      plane_name(pipe));
1129                 return;
1130         }
1131
1132         /* Need to check both planes against the pipe */
1133         for_each_pipe(i) {
1134                 reg = DSPCNTR(i);
1135                 val = I915_READ(reg);
1136                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1137                         DISPPLANE_SEL_PIPE_SHIFT;
1138                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1139                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1140                      plane_name(i), pipe_name(pipe));
1141         }
1142 }
1143
1144 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1145                                     enum pipe pipe)
1146 {
1147         struct drm_device *dev = dev_priv->dev;
1148         int reg, i;
1149         u32 val;
1150
1151         if (IS_VALLEYVIEW(dev)) {
1152                 for (i = 0; i < dev_priv->num_plane; i++) {
1153                         reg = SPCNTR(pipe, i);
1154                         val = I915_READ(reg);
1155                         WARN((val & SP_ENABLE),
1156                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1157                              sprite_name(pipe, i), pipe_name(pipe));
1158                 }
1159         } else if (INTEL_INFO(dev)->gen >= 7) {
1160                 reg = SPRCTL(pipe);
1161                 val = I915_READ(reg);
1162                 WARN((val & SPRITE_ENABLE),
1163                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1164                      plane_name(pipe), pipe_name(pipe));
1165         } else if (INTEL_INFO(dev)->gen >= 5) {
1166                 reg = DVSCNTR(pipe);
1167                 val = I915_READ(reg);
1168                 WARN((val & DVS_ENABLE),
1169                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1170                      plane_name(pipe), pipe_name(pipe));
1171         }
1172 }
1173
1174 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1175 {
1176         u32 val;
1177         bool enabled;
1178
1179         if (HAS_PCH_LPT(dev_priv->dev)) {
1180                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1181                 return;
1182         }
1183
1184         val = I915_READ(PCH_DREF_CONTROL);
1185         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1186                             DREF_SUPERSPREAD_SOURCE_MASK));
1187         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1188 }
1189
1190 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1191                                            enum pipe pipe)
1192 {
1193         int reg;
1194         u32 val;
1195         bool enabled;
1196
1197         reg = PCH_TRANSCONF(pipe);
1198         val = I915_READ(reg);
1199         enabled = !!(val & TRANS_ENABLE);
1200         WARN(enabled,
1201              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1202              pipe_name(pipe));
1203 }
1204
1205 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1206                             enum pipe pipe, u32 port_sel, u32 val)
1207 {
1208         if ((val & DP_PORT_EN) == 0)
1209                 return false;
1210
1211         if (HAS_PCH_CPT(dev_priv->dev)) {
1212                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1213                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1214                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1215                         return false;
1216         } else {
1217                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1218                         return false;
1219         }
1220         return true;
1221 }
1222
1223 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1224                               enum pipe pipe, u32 val)
1225 {
1226         if ((val & SDVO_ENABLE) == 0)
1227                 return false;
1228
1229         if (HAS_PCH_CPT(dev_priv->dev)) {
1230                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1231                         return false;
1232         } else {
1233                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1234                         return false;
1235         }
1236         return true;
1237 }
1238
1239 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1240                               enum pipe pipe, u32 val)
1241 {
1242         if ((val & LVDS_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1247                         return false;
1248         } else {
1249                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1250                         return false;
1251         }
1252         return true;
1253 }
1254
1255 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1256                               enum pipe pipe, u32 val)
1257 {
1258         if ((val & ADPA_DAC_ENABLE) == 0)
1259                 return false;
1260         if (HAS_PCH_CPT(dev_priv->dev)) {
1261                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1262                         return false;
1263         } else {
1264                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1265                         return false;
1266         }
1267         return true;
1268 }
1269
1270 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1271                                    enum pipe pipe, int reg, u32 port_sel)
1272 {
1273         u32 val = I915_READ(reg);
1274         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1275              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1276              reg, pipe_name(pipe));
1277
1278         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1279              && (val & DP_PIPEB_SELECT),
1280              "IBX PCH dp port still using transcoder B\n");
1281 }
1282
1283 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1284                                      enum pipe pipe, int reg)
1285 {
1286         u32 val = I915_READ(reg);
1287         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1288              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1289              reg, pipe_name(pipe));
1290
1291         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1292              && (val & SDVO_PIPE_B_SELECT),
1293              "IBX PCH hdmi port still using transcoder B\n");
1294 }
1295
1296 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1297                                       enum pipe pipe)
1298 {
1299         int reg;
1300         u32 val;
1301
1302         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1303         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1304         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1305
1306         reg = PCH_ADPA;
1307         val = I915_READ(reg);
1308         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1309              "PCH VGA enabled on transcoder %c, should be disabled\n",
1310              pipe_name(pipe));
1311
1312         reg = PCH_LVDS;
1313         val = I915_READ(reg);
1314         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1315              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1316              pipe_name(pipe));
1317
1318         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1319         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1320         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1321 }
1322
1323 static void vlv_enable_pll(struct intel_crtc *crtc)
1324 {
1325         struct drm_device *dev = crtc->base.dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         int reg = DPLL(crtc->pipe);
1328         u32 dpll = crtc->config.dpll_hw_state.dpll;
1329
1330         assert_pipe_disabled(dev_priv, crtc->pipe);
1331
1332         /* No really, not for ILK+ */
1333         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1334
1335         /* PLL is protected by panel, make sure we can write it */
1336         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1337                 assert_panel_unlocked(dev_priv, crtc->pipe);
1338
1339         I915_WRITE(reg, dpll);
1340         POSTING_READ(reg);
1341         udelay(150);
1342
1343         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1344                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1345
1346         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1347         POSTING_READ(DPLL_MD(crtc->pipe));
1348
1349         /* We do this three times for luck */
1350         I915_WRITE(reg, dpll);
1351         POSTING_READ(reg);
1352         udelay(150); /* wait for warmup */
1353         I915_WRITE(reg, dpll);
1354         POSTING_READ(reg);
1355         udelay(150); /* wait for warmup */
1356         I915_WRITE(reg, dpll);
1357         POSTING_READ(reg);
1358         udelay(150); /* wait for warmup */
1359 }
1360
1361 static void i9xx_enable_pll(struct intel_crtc *crtc)
1362 {
1363         struct drm_device *dev = crtc->base.dev;
1364         struct drm_i915_private *dev_priv = dev->dev_private;
1365         int reg = DPLL(crtc->pipe);
1366         u32 dpll = crtc->config.dpll_hw_state.dpll;
1367
1368         assert_pipe_disabled(dev_priv, crtc->pipe);
1369
1370         /* No really, not for ILK+ */
1371         BUG_ON(dev_priv->info->gen >= 5);
1372
1373         /* PLL is protected by panel, make sure we can write it */
1374         if (IS_MOBILE(dev) && !IS_I830(dev))
1375                 assert_panel_unlocked(dev_priv, crtc->pipe);
1376
1377         I915_WRITE(reg, dpll);
1378
1379         /* Wait for the clocks to stabilize. */
1380         POSTING_READ(reg);
1381         udelay(150);
1382
1383         if (INTEL_INFO(dev)->gen >= 4) {
1384                 I915_WRITE(DPLL_MD(crtc->pipe),
1385                            crtc->config.dpll_hw_state.dpll_md);
1386         } else {
1387                 /* The pixel multiplier can only be updated once the
1388                  * DPLL is enabled and the clocks are stable.
1389                  *
1390                  * So write it again.
1391                  */
1392                 I915_WRITE(reg, dpll);
1393         }
1394
1395         /* We do this three times for luck */
1396         I915_WRITE(reg, dpll);
1397         POSTING_READ(reg);
1398         udelay(150); /* wait for warmup */
1399         I915_WRITE(reg, dpll);
1400         POSTING_READ(reg);
1401         udelay(150); /* wait for warmup */
1402         I915_WRITE(reg, dpll);
1403         POSTING_READ(reg);
1404         udelay(150); /* wait for warmup */
1405 }
1406
1407 /**
1408  * i9xx_disable_pll - disable a PLL
1409  * @dev_priv: i915 private structure
1410  * @pipe: pipe PLL to disable
1411  *
1412  * Disable the PLL for @pipe, making sure the pipe is off first.
1413  *
1414  * Note!  This is for pre-ILK only.
1415  */
1416 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1417 {
1418         /* Don't disable pipe A or pipe A PLLs if needed */
1419         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1420                 return;
1421
1422         /* Make sure the pipe isn't still relying on us */
1423         assert_pipe_disabled(dev_priv, pipe);
1424
1425         I915_WRITE(DPLL(pipe), 0);
1426         POSTING_READ(DPLL(pipe));
1427 }
1428
1429 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1430 {
1431         u32 port_mask;
1432
1433         if (!port)
1434                 port_mask = DPLL_PORTB_READY_MASK;
1435         else
1436                 port_mask = DPLL_PORTC_READY_MASK;
1437
1438         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1439                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1440                      'B' + port, I915_READ(DPLL(0)));
1441 }
1442
1443 /**
1444  * ironlake_enable_shared_dpll - enable PCH PLL
1445  * @dev_priv: i915 private structure
1446  * @pipe: pipe PLL to enable
1447  *
1448  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1449  * drives the transcoder clock.
1450  */
1451 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1452 {
1453         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1454         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1455
1456         /* PCH PLLs only available on ILK, SNB and IVB */
1457         BUG_ON(dev_priv->info->gen < 5);
1458         if (WARN_ON(pll == NULL))
1459                 return;
1460
1461         if (WARN_ON(pll->refcount == 0))
1462                 return;
1463
1464         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1465                       pll->name, pll->active, pll->on,
1466                       crtc->base.base.id);
1467
1468         if (pll->active++) {
1469                 WARN_ON(!pll->on);
1470                 assert_shared_dpll_enabled(dev_priv, pll);
1471                 return;
1472         }
1473         WARN_ON(pll->on);
1474
1475         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1476         pll->enable(dev_priv, pll);
1477         pll->on = true;
1478 }
1479
1480 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1481 {
1482         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1483         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1484
1485         /* PCH only available on ILK+ */
1486         BUG_ON(dev_priv->info->gen < 5);
1487         if (WARN_ON(pll == NULL))
1488                return;
1489
1490         if (WARN_ON(pll->refcount == 0))
1491                 return;
1492
1493         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1494                       pll->name, pll->active, pll->on,
1495                       crtc->base.base.id);
1496
1497         if (WARN_ON(pll->active == 0)) {
1498                 assert_shared_dpll_disabled(dev_priv, pll);
1499                 return;
1500         }
1501
1502         assert_shared_dpll_enabled(dev_priv, pll);
1503         WARN_ON(!pll->on);
1504         if (--pll->active)
1505                 return;
1506
1507         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1508         pll->disable(dev_priv, pll);
1509         pll->on = false;
1510 }
1511
1512 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1513                                            enum pipe pipe)
1514 {
1515         struct drm_device *dev = dev_priv->dev;
1516         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1518         uint32_t reg, val, pipeconf_val;
1519
1520         /* PCH only available on ILK+ */
1521         BUG_ON(dev_priv->info->gen < 5);
1522
1523         /* Make sure PCH DPLL is enabled */
1524         assert_shared_dpll_enabled(dev_priv,
1525                                    intel_crtc_to_shared_dpll(intel_crtc));
1526
1527         /* FDI must be feeding us bits for PCH ports */
1528         assert_fdi_tx_enabled(dev_priv, pipe);
1529         assert_fdi_rx_enabled(dev_priv, pipe);
1530
1531         if (HAS_PCH_CPT(dev)) {
1532                 /* Workaround: Set the timing override bit before enabling the
1533                  * pch transcoder. */
1534                 reg = TRANS_CHICKEN2(pipe);
1535                 val = I915_READ(reg);
1536                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1537                 I915_WRITE(reg, val);
1538         }
1539
1540         reg = PCH_TRANSCONF(pipe);
1541         val = I915_READ(reg);
1542         pipeconf_val = I915_READ(PIPECONF(pipe));
1543
1544         if (HAS_PCH_IBX(dev_priv->dev)) {
1545                 /*
1546                  * make the BPC in transcoder be consistent with
1547                  * that in pipeconf reg.
1548                  */
1549                 val &= ~PIPECONF_BPC_MASK;
1550                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1551         }
1552
1553         val &= ~TRANS_INTERLACE_MASK;
1554         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1555                 if (HAS_PCH_IBX(dev_priv->dev) &&
1556                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1557                         val |= TRANS_LEGACY_INTERLACED_ILK;
1558                 else
1559                         val |= TRANS_INTERLACED;
1560         else
1561                 val |= TRANS_PROGRESSIVE;
1562
1563         I915_WRITE(reg, val | TRANS_ENABLE);
1564         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1565                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1566 }
1567
1568 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1569                                       enum transcoder cpu_transcoder)
1570 {
1571         u32 val, pipeconf_val;
1572
1573         /* PCH only available on ILK+ */
1574         BUG_ON(dev_priv->info->gen < 5);
1575
1576         /* FDI must be feeding us bits for PCH ports */
1577         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1578         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1579
1580         /* Workaround: set timing override bit. */
1581         val = I915_READ(_TRANSA_CHICKEN2);
1582         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1583         I915_WRITE(_TRANSA_CHICKEN2, val);
1584
1585         val = TRANS_ENABLE;
1586         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1587
1588         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1589             PIPECONF_INTERLACED_ILK)
1590                 val |= TRANS_INTERLACED;
1591         else
1592                 val |= TRANS_PROGRESSIVE;
1593
1594         I915_WRITE(LPT_TRANSCONF, val);
1595         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1596                 DRM_ERROR("Failed to enable PCH transcoder\n");
1597 }
1598
1599 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1600                                             enum pipe pipe)
1601 {
1602         struct drm_device *dev = dev_priv->dev;
1603         uint32_t reg, val;
1604
1605         /* FDI relies on the transcoder */
1606         assert_fdi_tx_disabled(dev_priv, pipe);
1607         assert_fdi_rx_disabled(dev_priv, pipe);
1608
1609         /* Ports must be off as well */
1610         assert_pch_ports_disabled(dev_priv, pipe);
1611
1612         reg = PCH_TRANSCONF(pipe);
1613         val = I915_READ(reg);
1614         val &= ~TRANS_ENABLE;
1615         I915_WRITE(reg, val);
1616         /* wait for PCH transcoder off, transcoder state */
1617         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1618                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1619
1620         if (!HAS_PCH_IBX(dev)) {
1621                 /* Workaround: Clear the timing override chicken bit again. */
1622                 reg = TRANS_CHICKEN2(pipe);
1623                 val = I915_READ(reg);
1624                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1625                 I915_WRITE(reg, val);
1626         }
1627 }
1628
1629 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1630 {
1631         u32 val;
1632
1633         val = I915_READ(LPT_TRANSCONF);
1634         val &= ~TRANS_ENABLE;
1635         I915_WRITE(LPT_TRANSCONF, val);
1636         /* wait for PCH transcoder off, transcoder state */
1637         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1638                 DRM_ERROR("Failed to disable PCH transcoder\n");
1639
1640         /* Workaround: clear timing override bit. */
1641         val = I915_READ(_TRANSA_CHICKEN2);
1642         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1643         I915_WRITE(_TRANSA_CHICKEN2, val);
1644 }
1645
1646 /**
1647  * intel_enable_pipe - enable a pipe, asserting requirements
1648  * @dev_priv: i915 private structure
1649  * @pipe: pipe to enable
1650  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1651  *
1652  * Enable @pipe, making sure that various hardware specific requirements
1653  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1654  *
1655  * @pipe should be %PIPE_A or %PIPE_B.
1656  *
1657  * Will wait until the pipe is actually running (i.e. first vblank) before
1658  * returning.
1659  */
1660 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1661                               bool pch_port)
1662 {
1663         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1664                                                                       pipe);
1665         enum pipe pch_transcoder;
1666         int reg;
1667         u32 val;
1668
1669         assert_planes_disabled(dev_priv, pipe);
1670         assert_sprites_disabled(dev_priv, pipe);
1671
1672         if (HAS_PCH_LPT(dev_priv->dev))
1673                 pch_transcoder = TRANSCODER_A;
1674         else
1675                 pch_transcoder = pipe;
1676
1677         /*
1678          * A pipe without a PLL won't actually be able to drive bits from
1679          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1680          * need the check.
1681          */
1682         if (!HAS_PCH_SPLIT(dev_priv->dev))
1683                 assert_pll_enabled(dev_priv, pipe);
1684         else {
1685                 if (pch_port) {
1686                         /* if driving the PCH, we need FDI enabled */
1687                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1688                         assert_fdi_tx_pll_enabled(dev_priv,
1689                                                   (enum pipe) cpu_transcoder);
1690                 }
1691                 /* FIXME: assert CPU port conditions for SNB+ */
1692         }
1693
1694         reg = PIPECONF(cpu_transcoder);
1695         val = I915_READ(reg);
1696         if (val & PIPECONF_ENABLE)
1697                 return;
1698
1699         I915_WRITE(reg, val | PIPECONF_ENABLE);
1700         intel_wait_for_vblank(dev_priv->dev, pipe);
1701 }
1702
1703 /**
1704  * intel_disable_pipe - disable a pipe, asserting requirements
1705  * @dev_priv: i915 private structure
1706  * @pipe: pipe to disable
1707  *
1708  * Disable @pipe, making sure that various hardware specific requirements
1709  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1710  *
1711  * @pipe should be %PIPE_A or %PIPE_B.
1712  *
1713  * Will wait until the pipe has shut down before returning.
1714  */
1715 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1716                                enum pipe pipe)
1717 {
1718         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1719                                                                       pipe);
1720         int reg;
1721         u32 val;
1722
1723         /*
1724          * Make sure planes won't keep trying to pump pixels to us,
1725          * or we might hang the display.
1726          */
1727         assert_planes_disabled(dev_priv, pipe);
1728         assert_sprites_disabled(dev_priv, pipe);
1729
1730         /* Don't disable pipe A or pipe A PLLs if needed */
1731         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1732                 return;
1733
1734         reg = PIPECONF(cpu_transcoder);
1735         val = I915_READ(reg);
1736         if ((val & PIPECONF_ENABLE) == 0)
1737                 return;
1738
1739         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1740         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1741 }
1742
1743 /*
1744  * Plane regs are double buffered, going from enabled->disabled needs a
1745  * trigger in order to latch.  The display address reg provides this.
1746  */
1747 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1748                                       enum plane plane)
1749 {
1750         if (dev_priv->info->gen >= 4)
1751                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1752         else
1753                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1754 }
1755
1756 /**
1757  * intel_enable_plane - enable a display plane on a given pipe
1758  * @dev_priv: i915 private structure
1759  * @plane: plane to enable
1760  * @pipe: pipe being fed
1761  *
1762  * Enable @plane on @pipe, making sure that @pipe is running first.
1763  */
1764 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1765                                enum plane plane, enum pipe pipe)
1766 {
1767         int reg;
1768         u32 val;
1769
1770         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1771         assert_pipe_enabled(dev_priv, pipe);
1772
1773         reg = DSPCNTR(plane);
1774         val = I915_READ(reg);
1775         if (val & DISPLAY_PLANE_ENABLE)
1776                 return;
1777
1778         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1779         intel_flush_display_plane(dev_priv, plane);
1780         intel_wait_for_vblank(dev_priv->dev, pipe);
1781 }
1782
1783 /**
1784  * intel_disable_plane - disable a display plane
1785  * @dev_priv: i915 private structure
1786  * @plane: plane to disable
1787  * @pipe: pipe consuming the data
1788  *
1789  * Disable @plane; should be an independent operation.
1790  */
1791 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1792                                 enum plane plane, enum pipe pipe)
1793 {
1794         int reg;
1795         u32 val;
1796
1797         reg = DSPCNTR(plane);
1798         val = I915_READ(reg);
1799         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1800                 return;
1801
1802         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1803         intel_flush_display_plane(dev_priv, plane);
1804         intel_wait_for_vblank(dev_priv->dev, pipe);
1805 }
1806
1807 static bool need_vtd_wa(struct drm_device *dev)
1808 {
1809 #ifdef CONFIG_INTEL_IOMMU
1810         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1811                 return true;
1812 #endif
1813         return false;
1814 }
1815
1816 int
1817 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1818                            struct drm_i915_gem_object *obj,
1819                            struct intel_ring_buffer *pipelined)
1820 {
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822         u32 alignment;
1823         int ret;
1824
1825         switch (obj->tiling_mode) {
1826         case I915_TILING_NONE:
1827                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1828                         alignment = 128 * 1024;
1829                 else if (INTEL_INFO(dev)->gen >= 4)
1830                         alignment = 4 * 1024;
1831                 else
1832                         alignment = 64 * 1024;
1833                 break;
1834         case I915_TILING_X:
1835                 /* pin() will align the object as required by fence */
1836                 alignment = 0;
1837                 break;
1838         case I915_TILING_Y:
1839                 /* Despite that we check this in framebuffer_init userspace can
1840                  * screw us over and change the tiling after the fact. Only
1841                  * pinned buffers can't change their tiling. */
1842                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1843                 return -EINVAL;
1844         default:
1845                 BUG();
1846         }
1847
1848         /* Note that the w/a also requires 64 PTE of padding following the
1849          * bo. We currently fill all unused PTE with the shadow page and so
1850          * we should always have valid PTE following the scanout preventing
1851          * the VT-d warning.
1852          */
1853         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1854                 alignment = 256 * 1024;
1855
1856         dev_priv->mm.interruptible = false;
1857         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1858         if (ret)
1859                 goto err_interruptible;
1860
1861         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1862          * fence, whereas 965+ only requires a fence if using
1863          * framebuffer compression.  For simplicity, we always install
1864          * a fence as the cost is not that onerous.
1865          */
1866         ret = i915_gem_object_get_fence(obj);
1867         if (ret)
1868                 goto err_unpin;
1869
1870         i915_gem_object_pin_fence(obj);
1871
1872         dev_priv->mm.interruptible = true;
1873         return 0;
1874
1875 err_unpin:
1876         i915_gem_object_unpin(obj);
1877 err_interruptible:
1878         dev_priv->mm.interruptible = true;
1879         return ret;
1880 }
1881
1882 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1883 {
1884         i915_gem_object_unpin_fence(obj);
1885         i915_gem_object_unpin(obj);
1886 }
1887
1888 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1889  * is assumed to be a power-of-two. */
1890 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1891                                              unsigned int tiling_mode,
1892                                              unsigned int cpp,
1893                                              unsigned int pitch)
1894 {
1895         if (tiling_mode != I915_TILING_NONE) {
1896                 unsigned int tile_rows, tiles;
1897
1898                 tile_rows = *y / 8;
1899                 *y %= 8;
1900
1901                 tiles = *x / (512/cpp);
1902                 *x %= 512/cpp;
1903
1904                 return tile_rows * pitch * 8 + tiles * 4096;
1905         } else {
1906                 unsigned int offset;
1907
1908                 offset = *y * pitch + *x * cpp;
1909                 *y = 0;
1910                 *x = (offset & 4095) / cpp;
1911                 return offset & -4096;
1912         }
1913 }
1914
1915 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1916                              int x, int y)
1917 {
1918         struct drm_device *dev = crtc->dev;
1919         struct drm_i915_private *dev_priv = dev->dev_private;
1920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1921         struct intel_framebuffer *intel_fb;
1922         struct drm_i915_gem_object *obj;
1923         int plane = intel_crtc->plane;
1924         unsigned long linear_offset;
1925         u32 dspcntr;
1926         u32 reg;
1927
1928         switch (plane) {
1929         case 0:
1930         case 1:
1931                 break;
1932         default:
1933                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1934                 return -EINVAL;
1935         }
1936
1937         intel_fb = to_intel_framebuffer(fb);
1938         obj = intel_fb->obj;
1939
1940         reg = DSPCNTR(plane);
1941         dspcntr = I915_READ(reg);
1942         /* Mask out pixel format bits in case we change it */
1943         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1944         switch (fb->pixel_format) {
1945         case DRM_FORMAT_C8:
1946                 dspcntr |= DISPPLANE_8BPP;
1947                 break;
1948         case DRM_FORMAT_XRGB1555:
1949         case DRM_FORMAT_ARGB1555:
1950                 dspcntr |= DISPPLANE_BGRX555;
1951                 break;
1952         case DRM_FORMAT_RGB565:
1953                 dspcntr |= DISPPLANE_BGRX565;
1954                 break;
1955         case DRM_FORMAT_XRGB8888:
1956         case DRM_FORMAT_ARGB8888:
1957                 dspcntr |= DISPPLANE_BGRX888;
1958                 break;
1959         case DRM_FORMAT_XBGR8888:
1960         case DRM_FORMAT_ABGR8888:
1961                 dspcntr |= DISPPLANE_RGBX888;
1962                 break;
1963         case DRM_FORMAT_XRGB2101010:
1964         case DRM_FORMAT_ARGB2101010:
1965                 dspcntr |= DISPPLANE_BGRX101010;
1966                 break;
1967         case DRM_FORMAT_XBGR2101010:
1968         case DRM_FORMAT_ABGR2101010:
1969                 dspcntr |= DISPPLANE_RGBX101010;
1970                 break;
1971         default:
1972                 BUG();
1973         }
1974
1975         if (INTEL_INFO(dev)->gen >= 4) {
1976                 if (obj->tiling_mode != I915_TILING_NONE)
1977                         dspcntr |= DISPPLANE_TILED;
1978                 else
1979                         dspcntr &= ~DISPPLANE_TILED;
1980         }
1981
1982         if (IS_G4X(dev))
1983                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1984
1985         I915_WRITE(reg, dspcntr);
1986
1987         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1988
1989         if (INTEL_INFO(dev)->gen >= 4) {
1990                 intel_crtc->dspaddr_offset =
1991                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1992                                                        fb->bits_per_pixel / 8,
1993                                                        fb->pitches[0]);
1994                 linear_offset -= intel_crtc->dspaddr_offset;
1995         } else {
1996                 intel_crtc->dspaddr_offset = linear_offset;
1997         }
1998
1999         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2000                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2001                       fb->pitches[0]);
2002         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2003         if (INTEL_INFO(dev)->gen >= 4) {
2004                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2005                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2006                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2007                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2008         } else
2009                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2010         POSTING_READ(reg);
2011
2012         return 0;
2013 }
2014
2015 static int ironlake_update_plane(struct drm_crtc *crtc,
2016                                  struct drm_framebuffer *fb, int x, int y)
2017 {
2018         struct drm_device *dev = crtc->dev;
2019         struct drm_i915_private *dev_priv = dev->dev_private;
2020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2021         struct intel_framebuffer *intel_fb;
2022         struct drm_i915_gem_object *obj;
2023         int plane = intel_crtc->plane;
2024         unsigned long linear_offset;
2025         u32 dspcntr;
2026         u32 reg;
2027
2028         switch (plane) {
2029         case 0:
2030         case 1:
2031         case 2:
2032                 break;
2033         default:
2034                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2035                 return -EINVAL;
2036         }
2037
2038         intel_fb = to_intel_framebuffer(fb);
2039         obj = intel_fb->obj;
2040
2041         reg = DSPCNTR(plane);
2042         dspcntr = I915_READ(reg);
2043         /* Mask out pixel format bits in case we change it */
2044         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2045         switch (fb->pixel_format) {
2046         case DRM_FORMAT_C8:
2047                 dspcntr |= DISPPLANE_8BPP;
2048                 break;
2049         case DRM_FORMAT_RGB565:
2050                 dspcntr |= DISPPLANE_BGRX565;
2051                 break;
2052         case DRM_FORMAT_XRGB8888:
2053         case DRM_FORMAT_ARGB8888:
2054                 dspcntr |= DISPPLANE_BGRX888;
2055                 break;
2056         case DRM_FORMAT_XBGR8888:
2057         case DRM_FORMAT_ABGR8888:
2058                 dspcntr |= DISPPLANE_RGBX888;
2059                 break;
2060         case DRM_FORMAT_XRGB2101010:
2061         case DRM_FORMAT_ARGB2101010:
2062                 dspcntr |= DISPPLANE_BGRX101010;
2063                 break;
2064         case DRM_FORMAT_XBGR2101010:
2065         case DRM_FORMAT_ABGR2101010:
2066                 dspcntr |= DISPPLANE_RGBX101010;
2067                 break;
2068         default:
2069                 BUG();
2070         }
2071
2072         if (obj->tiling_mode != I915_TILING_NONE)
2073                 dspcntr |= DISPPLANE_TILED;
2074         else
2075                 dspcntr &= ~DISPPLANE_TILED;
2076
2077         /* must disable */
2078         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2079
2080         I915_WRITE(reg, dspcntr);
2081
2082         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2083         intel_crtc->dspaddr_offset =
2084                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2085                                                fb->bits_per_pixel / 8,
2086                                                fb->pitches[0]);
2087         linear_offset -= intel_crtc->dspaddr_offset;
2088
2089         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2090                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2091                       fb->pitches[0]);
2092         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2093         I915_MODIFY_DISPBASE(DSPSURF(plane),
2094                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2095         if (IS_HASWELL(dev)) {
2096                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2097         } else {
2098                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2099                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2100         }
2101         POSTING_READ(reg);
2102
2103         return 0;
2104 }
2105
2106 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2107 static int
2108 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2109                            int x, int y, enum mode_set_atomic state)
2110 {
2111         struct drm_device *dev = crtc->dev;
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113
2114         if (dev_priv->display.disable_fbc)
2115                 dev_priv->display.disable_fbc(dev);
2116         intel_increase_pllclock(crtc);
2117
2118         return dev_priv->display.update_plane(crtc, fb, x, y);
2119 }
2120
2121 void intel_display_handle_reset(struct drm_device *dev)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         struct drm_crtc *crtc;
2125
2126         /*
2127          * Flips in the rings have been nuked by the reset,
2128          * so complete all pending flips so that user space
2129          * will get its events and not get stuck.
2130          *
2131          * Also update the base address of all primary
2132          * planes to the the last fb to make sure we're
2133          * showing the correct fb after a reset.
2134          *
2135          * Need to make two loops over the crtcs so that we
2136          * don't try to grab a crtc mutex before the
2137          * pending_flip_queue really got woken up.
2138          */
2139
2140         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2141                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2142                 enum plane plane = intel_crtc->plane;
2143
2144                 intel_prepare_page_flip(dev, plane);
2145                 intel_finish_page_flip_plane(dev, plane);
2146         }
2147
2148         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2149                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2150
2151                 mutex_lock(&crtc->mutex);
2152                 if (intel_crtc->active)
2153                         dev_priv->display.update_plane(crtc, crtc->fb,
2154                                                        crtc->x, crtc->y);
2155                 mutex_unlock(&crtc->mutex);
2156         }
2157 }
2158
2159 static int
2160 intel_finish_fb(struct drm_framebuffer *old_fb)
2161 {
2162         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2163         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2164         bool was_interruptible = dev_priv->mm.interruptible;
2165         int ret;
2166
2167         /* Big Hammer, we also need to ensure that any pending
2168          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2169          * current scanout is retired before unpinning the old
2170          * framebuffer.
2171          *
2172          * This should only fail upon a hung GPU, in which case we
2173          * can safely continue.
2174          */
2175         dev_priv->mm.interruptible = false;
2176         ret = i915_gem_object_finish_gpu(obj);
2177         dev_priv->mm.interruptible = was_interruptible;
2178
2179         return ret;
2180 }
2181
2182 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2183 {
2184         struct drm_device *dev = crtc->dev;
2185         struct drm_i915_master_private *master_priv;
2186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2187
2188         if (!dev->primary->master)
2189                 return;
2190
2191         master_priv = dev->primary->master->driver_priv;
2192         if (!master_priv->sarea_priv)
2193                 return;
2194
2195         switch (intel_crtc->pipe) {
2196         case 0:
2197                 master_priv->sarea_priv->pipeA_x = x;
2198                 master_priv->sarea_priv->pipeA_y = y;
2199                 break;
2200         case 1:
2201                 master_priv->sarea_priv->pipeB_x = x;
2202                 master_priv->sarea_priv->pipeB_y = y;
2203                 break;
2204         default:
2205                 break;
2206         }
2207 }
2208
2209 static int
2210 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2211                     struct drm_framebuffer *fb)
2212 {
2213         struct drm_device *dev = crtc->dev;
2214         struct drm_i915_private *dev_priv = dev->dev_private;
2215         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2216         struct drm_framebuffer *old_fb;
2217         int ret;
2218
2219         /* no fb bound */
2220         if (!fb) {
2221                 DRM_ERROR("No FB bound\n");
2222                 return 0;
2223         }
2224
2225         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2226                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2227                           plane_name(intel_crtc->plane),
2228                           INTEL_INFO(dev)->num_pipes);
2229                 return -EINVAL;
2230         }
2231
2232         mutex_lock(&dev->struct_mutex);
2233         ret = intel_pin_and_fence_fb_obj(dev,
2234                                          to_intel_framebuffer(fb)->obj,
2235                                          NULL);
2236         if (ret != 0) {
2237                 mutex_unlock(&dev->struct_mutex);
2238                 DRM_ERROR("pin & fence failed\n");
2239                 return ret;
2240         }
2241
2242         /* Update pipe size and adjust fitter if needed */
2243         if (i915_fastboot) {
2244                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2245                            ((crtc->mode.hdisplay - 1) << 16) |
2246                            (crtc->mode.vdisplay - 1));
2247                 if (!intel_crtc->config.pch_pfit.size &&
2248                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2249                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2250                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2251                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2252                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2253                 }
2254         }
2255
2256         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2257         if (ret) {
2258                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2259                 mutex_unlock(&dev->struct_mutex);
2260                 DRM_ERROR("failed to update base address\n");
2261                 return ret;
2262         }
2263
2264         old_fb = crtc->fb;
2265         crtc->fb = fb;
2266         crtc->x = x;
2267         crtc->y = y;
2268
2269         if (old_fb) {
2270                 if (intel_crtc->active && old_fb != fb)
2271                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2272                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2273         }
2274
2275         intel_update_fbc(dev);
2276         intel_edp_psr_update(dev);
2277         mutex_unlock(&dev->struct_mutex);
2278
2279         intel_crtc_update_sarea_pos(crtc, x, y);
2280
2281         return 0;
2282 }
2283
2284 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2285 {
2286         struct drm_device *dev = crtc->dev;
2287         struct drm_i915_private *dev_priv = dev->dev_private;
2288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2289         int pipe = intel_crtc->pipe;
2290         u32 reg, temp;
2291
2292         /* enable normal train */
2293         reg = FDI_TX_CTL(pipe);
2294         temp = I915_READ(reg);
2295         if (IS_IVYBRIDGE(dev)) {
2296                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2297                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2298         } else {
2299                 temp &= ~FDI_LINK_TRAIN_NONE;
2300                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2301         }
2302         I915_WRITE(reg, temp);
2303
2304         reg = FDI_RX_CTL(pipe);
2305         temp = I915_READ(reg);
2306         if (HAS_PCH_CPT(dev)) {
2307                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2308                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2309         } else {
2310                 temp &= ~FDI_LINK_TRAIN_NONE;
2311                 temp |= FDI_LINK_TRAIN_NONE;
2312         }
2313         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2314
2315         /* wait one idle pattern time */
2316         POSTING_READ(reg);
2317         udelay(1000);
2318
2319         /* IVB wants error correction enabled */
2320         if (IS_IVYBRIDGE(dev))
2321                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2322                            FDI_FE_ERRC_ENABLE);
2323 }
2324
2325 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2326 {
2327         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2328 }
2329
2330 static void ivb_modeset_global_resources(struct drm_device *dev)
2331 {
2332         struct drm_i915_private *dev_priv = dev->dev_private;
2333         struct intel_crtc *pipe_B_crtc =
2334                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2335         struct intel_crtc *pipe_C_crtc =
2336                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2337         uint32_t temp;
2338
2339         /*
2340          * When everything is off disable fdi C so that we could enable fdi B
2341          * with all lanes. Note that we don't care about enabled pipes without
2342          * an enabled pch encoder.
2343          */
2344         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2345             !pipe_has_enabled_pch(pipe_C_crtc)) {
2346                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2347                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2348
2349                 temp = I915_READ(SOUTH_CHICKEN1);
2350                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2351                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2352                 I915_WRITE(SOUTH_CHICKEN1, temp);
2353         }
2354 }
2355
2356 /* The FDI link training functions for ILK/Ibexpeak. */
2357 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2358 {
2359         struct drm_device *dev = crtc->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362         int pipe = intel_crtc->pipe;
2363         int plane = intel_crtc->plane;
2364         u32 reg, temp, tries;
2365
2366         /* FDI needs bits from pipe & plane first */
2367         assert_pipe_enabled(dev_priv, pipe);
2368         assert_plane_enabled(dev_priv, plane);
2369
2370         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2371            for train result */
2372         reg = FDI_RX_IMR(pipe);
2373         temp = I915_READ(reg);
2374         temp &= ~FDI_RX_SYMBOL_LOCK;
2375         temp &= ~FDI_RX_BIT_LOCK;
2376         I915_WRITE(reg, temp);
2377         I915_READ(reg);
2378         udelay(150);
2379
2380         /* enable CPU FDI TX and PCH FDI RX */
2381         reg = FDI_TX_CTL(pipe);
2382         temp = I915_READ(reg);
2383         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2384         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2385         temp &= ~FDI_LINK_TRAIN_NONE;
2386         temp |= FDI_LINK_TRAIN_PATTERN_1;
2387         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2388
2389         reg = FDI_RX_CTL(pipe);
2390         temp = I915_READ(reg);
2391         temp &= ~FDI_LINK_TRAIN_NONE;
2392         temp |= FDI_LINK_TRAIN_PATTERN_1;
2393         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2394
2395         POSTING_READ(reg);
2396         udelay(150);
2397
2398         /* Ironlake workaround, enable clock pointer after FDI enable*/
2399         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2400         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2401                    FDI_RX_PHASE_SYNC_POINTER_EN);
2402
2403         reg = FDI_RX_IIR(pipe);
2404         for (tries = 0; tries < 5; tries++) {
2405                 temp = I915_READ(reg);
2406                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2407
2408                 if ((temp & FDI_RX_BIT_LOCK)) {
2409                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2410                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2411                         break;
2412                 }
2413         }
2414         if (tries == 5)
2415                 DRM_ERROR("FDI train 1 fail!\n");
2416
2417         /* Train 2 */
2418         reg = FDI_TX_CTL(pipe);
2419         temp = I915_READ(reg);
2420         temp &= ~FDI_LINK_TRAIN_NONE;
2421         temp |= FDI_LINK_TRAIN_PATTERN_2;
2422         I915_WRITE(reg, temp);
2423
2424         reg = FDI_RX_CTL(pipe);
2425         temp = I915_READ(reg);
2426         temp &= ~FDI_LINK_TRAIN_NONE;
2427         temp |= FDI_LINK_TRAIN_PATTERN_2;
2428         I915_WRITE(reg, temp);
2429
2430         POSTING_READ(reg);
2431         udelay(150);
2432
2433         reg = FDI_RX_IIR(pipe);
2434         for (tries = 0; tries < 5; tries++) {
2435                 temp = I915_READ(reg);
2436                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438                 if (temp & FDI_RX_SYMBOL_LOCK) {
2439                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2440                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2441                         break;
2442                 }
2443         }
2444         if (tries == 5)
2445                 DRM_ERROR("FDI train 2 fail!\n");
2446
2447         DRM_DEBUG_KMS("FDI train done\n");
2448
2449 }
2450
2451 static const int snb_b_fdi_train_param[] = {
2452         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2453         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2454         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2455         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2456 };
2457
2458 /* The FDI link training functions for SNB/Cougarpoint. */
2459 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2460 {
2461         struct drm_device *dev = crtc->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2464         int pipe = intel_crtc->pipe;
2465         u32 reg, temp, i, retry;
2466
2467         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2468            for train result */
2469         reg = FDI_RX_IMR(pipe);
2470         temp = I915_READ(reg);
2471         temp &= ~FDI_RX_SYMBOL_LOCK;
2472         temp &= ~FDI_RX_BIT_LOCK;
2473         I915_WRITE(reg, temp);
2474
2475         POSTING_READ(reg);
2476         udelay(150);
2477
2478         /* enable CPU FDI TX and PCH FDI RX */
2479         reg = FDI_TX_CTL(pipe);
2480         temp = I915_READ(reg);
2481         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2482         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2483         temp &= ~FDI_LINK_TRAIN_NONE;
2484         temp |= FDI_LINK_TRAIN_PATTERN_1;
2485         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486         /* SNB-B */
2487         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2488         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2489
2490         I915_WRITE(FDI_RX_MISC(pipe),
2491                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2492
2493         reg = FDI_RX_CTL(pipe);
2494         temp = I915_READ(reg);
2495         if (HAS_PCH_CPT(dev)) {
2496                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2498         } else {
2499                 temp &= ~FDI_LINK_TRAIN_NONE;
2500                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2501         }
2502         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2503
2504         POSTING_READ(reg);
2505         udelay(150);
2506
2507         for (i = 0; i < 4; i++) {
2508                 reg = FDI_TX_CTL(pipe);
2509                 temp = I915_READ(reg);
2510                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511                 temp |= snb_b_fdi_train_param[i];
2512                 I915_WRITE(reg, temp);
2513
2514                 POSTING_READ(reg);
2515                 udelay(500);
2516
2517                 for (retry = 0; retry < 5; retry++) {
2518                         reg = FDI_RX_IIR(pipe);
2519                         temp = I915_READ(reg);
2520                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521                         if (temp & FDI_RX_BIT_LOCK) {
2522                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2523                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2524                                 break;
2525                         }
2526                         udelay(50);
2527                 }
2528                 if (retry < 5)
2529                         break;
2530         }
2531         if (i == 4)
2532                 DRM_ERROR("FDI train 1 fail!\n");
2533
2534         /* Train 2 */
2535         reg = FDI_TX_CTL(pipe);
2536         temp = I915_READ(reg);
2537         temp &= ~FDI_LINK_TRAIN_NONE;
2538         temp |= FDI_LINK_TRAIN_PATTERN_2;
2539         if (IS_GEN6(dev)) {
2540                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541                 /* SNB-B */
2542                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2543         }
2544         I915_WRITE(reg, temp);
2545
2546         reg = FDI_RX_CTL(pipe);
2547         temp = I915_READ(reg);
2548         if (HAS_PCH_CPT(dev)) {
2549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2551         } else {
2552                 temp &= ~FDI_LINK_TRAIN_NONE;
2553                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2554         }
2555         I915_WRITE(reg, temp);
2556
2557         POSTING_READ(reg);
2558         udelay(150);
2559
2560         for (i = 0; i < 4; i++) {
2561                 reg = FDI_TX_CTL(pipe);
2562                 temp = I915_READ(reg);
2563                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2564                 temp |= snb_b_fdi_train_param[i];
2565                 I915_WRITE(reg, temp);
2566
2567                 POSTING_READ(reg);
2568                 udelay(500);
2569
2570                 for (retry = 0; retry < 5; retry++) {
2571                         reg = FDI_RX_IIR(pipe);
2572                         temp = I915_READ(reg);
2573                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2574                         if (temp & FDI_RX_SYMBOL_LOCK) {
2575                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2576                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2577                                 break;
2578                         }
2579                         udelay(50);
2580                 }
2581                 if (retry < 5)
2582                         break;
2583         }
2584         if (i == 4)
2585                 DRM_ERROR("FDI train 2 fail!\n");
2586
2587         DRM_DEBUG_KMS("FDI train done.\n");
2588 }
2589
2590 /* Manual link training for Ivy Bridge A0 parts */
2591 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2592 {
2593         struct drm_device *dev = crtc->dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2596         int pipe = intel_crtc->pipe;
2597         u32 reg, temp, i;
2598
2599         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2600            for train result */
2601         reg = FDI_RX_IMR(pipe);
2602         temp = I915_READ(reg);
2603         temp &= ~FDI_RX_SYMBOL_LOCK;
2604         temp &= ~FDI_RX_BIT_LOCK;
2605         I915_WRITE(reg, temp);
2606
2607         POSTING_READ(reg);
2608         udelay(150);
2609
2610         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2611                       I915_READ(FDI_RX_IIR(pipe)));
2612
2613         /* enable CPU FDI TX and PCH FDI RX */
2614         reg = FDI_TX_CTL(pipe);
2615         temp = I915_READ(reg);
2616         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2617         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2618         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2619         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2620         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2622         temp |= FDI_COMPOSITE_SYNC;
2623         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2624
2625         I915_WRITE(FDI_RX_MISC(pipe),
2626                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
2628         reg = FDI_RX_CTL(pipe);
2629         temp = I915_READ(reg);
2630         temp &= ~FDI_LINK_TRAIN_AUTO;
2631         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633         temp |= FDI_COMPOSITE_SYNC;
2634         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636         POSTING_READ(reg);
2637         udelay(150);
2638
2639         for (i = 0; i < 4; i++) {
2640                 reg = FDI_TX_CTL(pipe);
2641                 temp = I915_READ(reg);
2642                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643                 temp |= snb_b_fdi_train_param[i];
2644                 I915_WRITE(reg, temp);
2645
2646                 POSTING_READ(reg);
2647                 udelay(500);
2648
2649                 reg = FDI_RX_IIR(pipe);
2650                 temp = I915_READ(reg);
2651                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2652
2653                 if (temp & FDI_RX_BIT_LOCK ||
2654                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2655                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2656                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2657                         break;
2658                 }
2659         }
2660         if (i == 4)
2661                 DRM_ERROR("FDI train 1 fail!\n");
2662
2663         /* Train 2 */
2664         reg = FDI_TX_CTL(pipe);
2665         temp = I915_READ(reg);
2666         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2667         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2668         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2669         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2670         I915_WRITE(reg, temp);
2671
2672         reg = FDI_RX_CTL(pipe);
2673         temp = I915_READ(reg);
2674         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2675         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2676         I915_WRITE(reg, temp);
2677
2678         POSTING_READ(reg);
2679         udelay(150);
2680
2681         for (i = 0; i < 4; i++) {
2682                 reg = FDI_TX_CTL(pipe);
2683                 temp = I915_READ(reg);
2684                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2685                 temp |= snb_b_fdi_train_param[i];
2686                 I915_WRITE(reg, temp);
2687
2688                 POSTING_READ(reg);
2689                 udelay(500);
2690
2691                 reg = FDI_RX_IIR(pipe);
2692                 temp = I915_READ(reg);
2693                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694
2695                 if (temp & FDI_RX_SYMBOL_LOCK) {
2696                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2697                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2698                         break;
2699                 }
2700         }
2701         if (i == 4)
2702                 DRM_ERROR("FDI train 2 fail!\n");
2703
2704         DRM_DEBUG_KMS("FDI train done.\n");
2705 }
2706
2707 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2708 {
2709         struct drm_device *dev = intel_crtc->base.dev;
2710         struct drm_i915_private *dev_priv = dev->dev_private;
2711         int pipe = intel_crtc->pipe;
2712         u32 reg, temp;
2713
2714
2715         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2716         reg = FDI_RX_CTL(pipe);
2717         temp = I915_READ(reg);
2718         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2719         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2720         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2721         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2722
2723         POSTING_READ(reg);
2724         udelay(200);
2725
2726         /* Switch from Rawclk to PCDclk */
2727         temp = I915_READ(reg);
2728         I915_WRITE(reg, temp | FDI_PCDCLK);
2729
2730         POSTING_READ(reg);
2731         udelay(200);
2732
2733         /* Enable CPU FDI TX PLL, always on for Ironlake */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2737                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2738
2739                 POSTING_READ(reg);
2740                 udelay(100);
2741         }
2742 }
2743
2744 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2745 {
2746         struct drm_device *dev = intel_crtc->base.dev;
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748         int pipe = intel_crtc->pipe;
2749         u32 reg, temp;
2750
2751         /* Switch from PCDclk to Rawclk */
2752         reg = FDI_RX_CTL(pipe);
2753         temp = I915_READ(reg);
2754         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2755
2756         /* Disable CPU FDI TX PLL */
2757         reg = FDI_TX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2760
2761         POSTING_READ(reg);
2762         udelay(100);
2763
2764         reg = FDI_RX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2767
2768         /* Wait for the clocks to turn off. */
2769         POSTING_READ(reg);
2770         udelay(100);
2771 }
2772
2773 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2774 {
2775         struct drm_device *dev = crtc->dev;
2776         struct drm_i915_private *dev_priv = dev->dev_private;
2777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778         int pipe = intel_crtc->pipe;
2779         u32 reg, temp;
2780
2781         /* disable CPU FDI tx and PCH FDI rx */
2782         reg = FDI_TX_CTL(pipe);
2783         temp = I915_READ(reg);
2784         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2785         POSTING_READ(reg);
2786
2787         reg = FDI_RX_CTL(pipe);
2788         temp = I915_READ(reg);
2789         temp &= ~(0x7 << 16);
2790         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2791         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         /* Ironlake workaround, disable clock pointer after downing FDI */
2797         if (HAS_PCH_IBX(dev)) {
2798                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2799         }
2800
2801         /* still set train pattern 1 */
2802         reg = FDI_TX_CTL(pipe);
2803         temp = I915_READ(reg);
2804         temp &= ~FDI_LINK_TRAIN_NONE;
2805         temp |= FDI_LINK_TRAIN_PATTERN_1;
2806         I915_WRITE(reg, temp);
2807
2808         reg = FDI_RX_CTL(pipe);
2809         temp = I915_READ(reg);
2810         if (HAS_PCH_CPT(dev)) {
2811                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2813         } else {
2814                 temp &= ~FDI_LINK_TRAIN_NONE;
2815                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816         }
2817         /* BPC in FDI rx is consistent with that in PIPECONF */
2818         temp &= ~(0x07 << 16);
2819         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2820         I915_WRITE(reg, temp);
2821
2822         POSTING_READ(reg);
2823         udelay(100);
2824 }
2825
2826 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2831         unsigned long flags;
2832         bool pending;
2833
2834         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2835             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2836                 return false;
2837
2838         spin_lock_irqsave(&dev->event_lock, flags);
2839         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2840         spin_unlock_irqrestore(&dev->event_lock, flags);
2841
2842         return pending;
2843 }
2844
2845 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849
2850         if (crtc->fb == NULL)
2851                 return;
2852
2853         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2854
2855         wait_event(dev_priv->pending_flip_queue,
2856                    !intel_crtc_has_pending_flip(crtc));
2857
2858         mutex_lock(&dev->struct_mutex);
2859         intel_finish_fb(crtc->fb);
2860         mutex_unlock(&dev->struct_mutex);
2861 }
2862
2863 /* Program iCLKIP clock to the desired frequency */
2864 static void lpt_program_iclkip(struct drm_crtc *crtc)
2865 {
2866         struct drm_device *dev = crtc->dev;
2867         struct drm_i915_private *dev_priv = dev->dev_private;
2868         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2869         u32 temp;
2870
2871         mutex_lock(&dev_priv->dpio_lock);
2872
2873         /* It is necessary to ungate the pixclk gate prior to programming
2874          * the divisors, and gate it back when it is done.
2875          */
2876         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2877
2878         /* Disable SSCCTL */
2879         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2880                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2881                                 SBI_SSCCTL_DISABLE,
2882                         SBI_ICLK);
2883
2884         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2885         if (crtc->mode.clock == 20000) {
2886                 auxdiv = 1;
2887                 divsel = 0x41;
2888                 phaseinc = 0x20;
2889         } else {
2890                 /* The iCLK virtual clock root frequency is in MHz,
2891                  * but the crtc->mode.clock in in KHz. To get the divisors,
2892                  * it is necessary to divide one by another, so we
2893                  * convert the virtual clock precision to KHz here for higher
2894                  * precision.
2895                  */
2896                 u32 iclk_virtual_root_freq = 172800 * 1000;
2897                 u32 iclk_pi_range = 64;
2898                 u32 desired_divisor, msb_divisor_value, pi_value;
2899
2900                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2901                 msb_divisor_value = desired_divisor / iclk_pi_range;
2902                 pi_value = desired_divisor % iclk_pi_range;
2903
2904                 auxdiv = 0;
2905                 divsel = msb_divisor_value - 2;
2906                 phaseinc = pi_value;
2907         }
2908
2909         /* This should not happen with any sane values */
2910         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2911                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2912         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2913                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2914
2915         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2916                         crtc->mode.clock,
2917                         auxdiv,
2918                         divsel,
2919                         phasedir,
2920                         phaseinc);
2921
2922         /* Program SSCDIVINTPHASE6 */
2923         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2924         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2925         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2926         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2927         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2928         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2929         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2930         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2931
2932         /* Program SSCAUXDIV */
2933         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2934         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2935         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2936         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2937
2938         /* Enable modulator and associated divider */
2939         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2940         temp &= ~SBI_SSCCTL_DISABLE;
2941         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2942
2943         /* Wait for initialization time */
2944         udelay(24);
2945
2946         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2947
2948         mutex_unlock(&dev_priv->dpio_lock);
2949 }
2950
2951 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2952                                                 enum pipe pch_transcoder)
2953 {
2954         struct drm_device *dev = crtc->base.dev;
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2957
2958         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2959                    I915_READ(HTOTAL(cpu_transcoder)));
2960         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2961                    I915_READ(HBLANK(cpu_transcoder)));
2962         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2963                    I915_READ(HSYNC(cpu_transcoder)));
2964
2965         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2966                    I915_READ(VTOTAL(cpu_transcoder)));
2967         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2968                    I915_READ(VBLANK(cpu_transcoder)));
2969         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2970                    I915_READ(VSYNC(cpu_transcoder)));
2971         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2972                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2973 }
2974
2975 /*
2976  * Enable PCH resources required for PCH ports:
2977  *   - PCH PLLs
2978  *   - FDI training & RX/TX
2979  *   - update transcoder timings
2980  *   - DP transcoding bits
2981  *   - transcoder
2982  */
2983 static void ironlake_pch_enable(struct drm_crtc *crtc)
2984 {
2985         struct drm_device *dev = crtc->dev;
2986         struct drm_i915_private *dev_priv = dev->dev_private;
2987         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2988         int pipe = intel_crtc->pipe;
2989         u32 reg, temp;
2990
2991         assert_pch_transcoder_disabled(dev_priv, pipe);
2992
2993         /* Write the TU size bits before fdi link training, so that error
2994          * detection works. */
2995         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2996                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2997
2998         /* For PCH output, training FDI link */
2999         dev_priv->display.fdi_link_train(crtc);
3000
3001         /* We need to program the right clock selection before writing the pixel
3002          * mutliplier into the DPLL. */
3003         if (HAS_PCH_CPT(dev)) {
3004                 u32 sel;
3005
3006                 temp = I915_READ(PCH_DPLL_SEL);
3007                 temp |= TRANS_DPLL_ENABLE(pipe);
3008                 sel = TRANS_DPLLB_SEL(pipe);
3009                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3010                         temp |= sel;
3011                 else
3012                         temp &= ~sel;
3013                 I915_WRITE(PCH_DPLL_SEL, temp);
3014         }
3015
3016         /* XXX: pch pll's can be enabled any time before we enable the PCH
3017          * transcoder, and we actually should do this to not upset any PCH
3018          * transcoder that already use the clock when we share it.
3019          *
3020          * Note that enable_shared_dpll tries to do the right thing, but
3021          * get_shared_dpll unconditionally resets the pll - we need that to have
3022          * the right LVDS enable sequence. */
3023         ironlake_enable_shared_dpll(intel_crtc);
3024
3025         /* set transcoder timing, panel must allow it */
3026         assert_panel_unlocked(dev_priv, pipe);
3027         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3028
3029         intel_fdi_normal_train(crtc);
3030
3031         /* For PCH DP, enable TRANS_DP_CTL */
3032         if (HAS_PCH_CPT(dev) &&
3033             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3034              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3035                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3036                 reg = TRANS_DP_CTL(pipe);
3037                 temp = I915_READ(reg);
3038                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3039                           TRANS_DP_SYNC_MASK |
3040                           TRANS_DP_BPC_MASK);
3041                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3042                          TRANS_DP_ENH_FRAMING);
3043                 temp |= bpc << 9; /* same format but at 11:9 */
3044
3045                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3046                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3047                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3048                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3049
3050                 switch (intel_trans_dp_port_sel(crtc)) {
3051                 case PCH_DP_B:
3052                         temp |= TRANS_DP_PORT_SEL_B;
3053                         break;
3054                 case PCH_DP_C:
3055                         temp |= TRANS_DP_PORT_SEL_C;
3056                         break;
3057                 case PCH_DP_D:
3058                         temp |= TRANS_DP_PORT_SEL_D;
3059                         break;
3060                 default:
3061                         BUG();
3062                 }
3063
3064                 I915_WRITE(reg, temp);
3065         }
3066
3067         ironlake_enable_pch_transcoder(dev_priv, pipe);
3068 }
3069
3070 static void lpt_pch_enable(struct drm_crtc *crtc)
3071 {
3072         struct drm_device *dev = crtc->dev;
3073         struct drm_i915_private *dev_priv = dev->dev_private;
3074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3076
3077         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3078
3079         lpt_program_iclkip(crtc);
3080
3081         /* Set transcoder timing. */
3082         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3083
3084         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3085 }
3086
3087 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3088 {
3089         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090
3091         if (pll == NULL)
3092                 return;
3093
3094         if (pll->refcount == 0) {
3095                 WARN(1, "bad %s refcount\n", pll->name);
3096                 return;
3097         }
3098
3099         if (--pll->refcount == 0) {
3100                 WARN_ON(pll->on);
3101                 WARN_ON(pll->active);
3102         }
3103
3104         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3105 }
3106
3107 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3108 {
3109         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3110         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3111         enum intel_dpll_id i;
3112
3113         if (pll) {
3114                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3115                               crtc->base.base.id, pll->name);
3116                 intel_put_shared_dpll(crtc);
3117         }
3118
3119         if (HAS_PCH_IBX(dev_priv->dev)) {
3120                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3121                 i = (enum intel_dpll_id) crtc->pipe;
3122                 pll = &dev_priv->shared_dplls[i];
3123
3124                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3125                               crtc->base.base.id, pll->name);
3126
3127                 goto found;
3128         }
3129
3130         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3131                 pll = &dev_priv->shared_dplls[i];
3132
3133                 /* Only want to check enabled timings first */
3134                 if (pll->refcount == 0)
3135                         continue;
3136
3137                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3138                            sizeof(pll->hw_state)) == 0) {
3139                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3140                                       crtc->base.base.id,
3141                                       pll->name, pll->refcount, pll->active);
3142
3143                         goto found;
3144                 }
3145         }
3146
3147         /* Ok no matching timings, maybe there's a free one? */
3148         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3149                 pll = &dev_priv->shared_dplls[i];
3150                 if (pll->refcount == 0) {
3151                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3152                                       crtc->base.base.id, pll->name);
3153                         goto found;
3154                 }
3155         }
3156
3157         return NULL;
3158
3159 found:
3160         crtc->config.shared_dpll = i;
3161         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3162                          pipe_name(crtc->pipe));
3163
3164         if (pll->active == 0) {
3165                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3166                        sizeof(pll->hw_state));
3167
3168                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3169                 WARN_ON(pll->on);
3170                 assert_shared_dpll_disabled(dev_priv, pll);
3171
3172                 pll->mode_set(dev_priv, pll);
3173         }
3174         pll->refcount++;
3175
3176         return pll;
3177 }
3178
3179 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3180 {
3181         struct drm_i915_private *dev_priv = dev->dev_private;
3182         int dslreg = PIPEDSL(pipe);
3183         u32 temp;
3184
3185         temp = I915_READ(dslreg);
3186         udelay(500);
3187         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3188                 if (wait_for(I915_READ(dslreg) != temp, 5))
3189                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3190         }
3191 }
3192
3193 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->base.dev;
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         int pipe = crtc->pipe;
3198
3199         if (crtc->config.pch_pfit.size) {
3200                 /* Force use of hard-coded filter coefficients
3201                  * as some pre-programmed values are broken,
3202                  * e.g. x201.
3203                  */
3204                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3205                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3206                                                  PF_PIPE_SEL_IVB(pipe));
3207                 else
3208                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3209                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3210                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3211         }
3212 }
3213
3214 static void intel_enable_planes(struct drm_crtc *crtc)
3215 {
3216         struct drm_device *dev = crtc->dev;
3217         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3218         struct intel_plane *intel_plane;
3219
3220         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3221                 if (intel_plane->pipe == pipe)
3222                         intel_plane_restore(&intel_plane->base);
3223 }
3224
3225 static void intel_disable_planes(struct drm_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3229         struct intel_plane *intel_plane;
3230
3231         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3232                 if (intel_plane->pipe == pipe)
3233                         intel_plane_disable(&intel_plane->base);
3234 }
3235
3236 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3237 {
3238         struct drm_device *dev = crtc->dev;
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3241         struct intel_encoder *encoder;
3242         int pipe = intel_crtc->pipe;
3243         int plane = intel_crtc->plane;
3244
3245         WARN_ON(!crtc->enabled);
3246
3247         if (intel_crtc->active)
3248                 return;
3249
3250         intel_crtc->active = true;
3251
3252         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3253         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3254
3255         intel_update_watermarks(dev);
3256
3257         for_each_encoder_on_crtc(dev, crtc, encoder)
3258                 if (encoder->pre_enable)
3259                         encoder->pre_enable(encoder);
3260
3261         if (intel_crtc->config.has_pch_encoder) {
3262                 /* Note: FDI PLL enabling _must_ be done before we enable the
3263                  * cpu pipes, hence this is separate from all the other fdi/pch
3264                  * enabling. */
3265                 ironlake_fdi_pll_enable(intel_crtc);
3266         } else {
3267                 assert_fdi_tx_disabled(dev_priv, pipe);
3268                 assert_fdi_rx_disabled(dev_priv, pipe);
3269         }
3270
3271         ironlake_pfit_enable(intel_crtc);
3272
3273         /*
3274          * On ILK+ LUT must be loaded before the pipe is running but with
3275          * clocks enabled
3276          */
3277         intel_crtc_load_lut(crtc);
3278
3279         intel_enable_pipe(dev_priv, pipe,
3280                           intel_crtc->config.has_pch_encoder);
3281         intel_enable_plane(dev_priv, plane, pipe);
3282         intel_enable_planes(crtc);
3283         intel_crtc_update_cursor(crtc, true);
3284
3285         if (intel_crtc->config.has_pch_encoder)
3286                 ironlake_pch_enable(crtc);
3287
3288         mutex_lock(&dev->struct_mutex);
3289         intel_update_fbc(dev);
3290         mutex_unlock(&dev->struct_mutex);
3291
3292         for_each_encoder_on_crtc(dev, crtc, encoder)
3293                 encoder->enable(encoder);
3294
3295         if (HAS_PCH_CPT(dev))
3296                 cpt_verify_modeset(dev, intel_crtc->pipe);
3297
3298         /*
3299          * There seems to be a race in PCH platform hw (at least on some
3300          * outputs) where an enabled pipe still completes any pageflip right
3301          * away (as if the pipe is off) instead of waiting for vblank. As soon
3302          * as the first vblank happend, everything works as expected. Hence just
3303          * wait for one vblank before returning to avoid strange things
3304          * happening.
3305          */
3306         intel_wait_for_vblank(dev, intel_crtc->pipe);
3307 }
3308
3309 /* IPS only exists on ULT machines and is tied to pipe A. */
3310 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3311 {
3312         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3313 }
3314
3315 static void hsw_enable_ips(struct intel_crtc *crtc)
3316 {
3317         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3318
3319         if (!crtc->config.ips_enabled)
3320                 return;
3321
3322         /* We can only enable IPS after we enable a plane and wait for a vblank.
3323          * We guarantee that the plane is enabled by calling intel_enable_ips
3324          * only after intel_enable_plane. And intel_enable_plane already waits
3325          * for a vblank, so all we need to do here is to enable the IPS bit. */
3326         assert_plane_enabled(dev_priv, crtc->plane);
3327         I915_WRITE(IPS_CTL, IPS_ENABLE);
3328 }
3329
3330 static void hsw_disable_ips(struct intel_crtc *crtc)
3331 {
3332         struct drm_device *dev = crtc->base.dev;
3333         struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335         if (!crtc->config.ips_enabled)
3336                 return;
3337
3338         assert_plane_enabled(dev_priv, crtc->plane);
3339         I915_WRITE(IPS_CTL, 0);
3340
3341         /* We need to wait for a vblank before we can disable the plane. */
3342         intel_wait_for_vblank(dev, crtc->pipe);
3343 }
3344
3345 static void haswell_crtc_enable(struct drm_crtc *crtc)
3346 {
3347         struct drm_device *dev = crtc->dev;
3348         struct drm_i915_private *dev_priv = dev->dev_private;
3349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350         struct intel_encoder *encoder;
3351         int pipe = intel_crtc->pipe;
3352         int plane = intel_crtc->plane;
3353
3354         WARN_ON(!crtc->enabled);
3355
3356         if (intel_crtc->active)
3357                 return;
3358
3359         intel_crtc->active = true;
3360
3361         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3362         if (intel_crtc->config.has_pch_encoder)
3363                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3364
3365         intel_update_watermarks(dev);
3366
3367         if (intel_crtc->config.has_pch_encoder)
3368                 dev_priv->display.fdi_link_train(crtc);
3369
3370         for_each_encoder_on_crtc(dev, crtc, encoder)
3371                 if (encoder->pre_enable)
3372                         encoder->pre_enable(encoder);
3373
3374         intel_ddi_enable_pipe_clock(intel_crtc);
3375
3376         ironlake_pfit_enable(intel_crtc);
3377
3378         /*
3379          * On ILK+ LUT must be loaded before the pipe is running but with
3380          * clocks enabled
3381          */
3382         intel_crtc_load_lut(crtc);
3383
3384         intel_ddi_set_pipe_settings(crtc);
3385         intel_ddi_enable_transcoder_func(crtc);
3386
3387         intel_enable_pipe(dev_priv, pipe,
3388                           intel_crtc->config.has_pch_encoder);
3389         intel_enable_plane(dev_priv, plane, pipe);
3390         intel_enable_planes(crtc);
3391         intel_crtc_update_cursor(crtc, true);
3392
3393         hsw_enable_ips(intel_crtc);
3394
3395         if (intel_crtc->config.has_pch_encoder)
3396                 lpt_pch_enable(crtc);
3397
3398         mutex_lock(&dev->struct_mutex);
3399         intel_update_fbc(dev);
3400         mutex_unlock(&dev->struct_mutex);
3401
3402         for_each_encoder_on_crtc(dev, crtc, encoder)
3403                 encoder->enable(encoder);
3404
3405         /*
3406          * There seems to be a race in PCH platform hw (at least on some
3407          * outputs) where an enabled pipe still completes any pageflip right
3408          * away (as if the pipe is off) instead of waiting for vblank. As soon
3409          * as the first vblank happend, everything works as expected. Hence just
3410          * wait for one vblank before returning to avoid strange things
3411          * happening.
3412          */
3413         intel_wait_for_vblank(dev, intel_crtc->pipe);
3414 }
3415
3416 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3417 {
3418         struct drm_device *dev = crtc->base.dev;
3419         struct drm_i915_private *dev_priv = dev->dev_private;
3420         int pipe = crtc->pipe;
3421
3422         /* To avoid upsetting the power well on haswell only disable the pfit if
3423          * it's in use. The hw state code will make sure we get this right. */
3424         if (crtc->config.pch_pfit.size) {
3425                 I915_WRITE(PF_CTL(pipe), 0);
3426                 I915_WRITE(PF_WIN_POS(pipe), 0);
3427                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3428         }
3429 }
3430
3431 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3432 {
3433         struct drm_device *dev = crtc->dev;
3434         struct drm_i915_private *dev_priv = dev->dev_private;
3435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436         struct intel_encoder *encoder;
3437         int pipe = intel_crtc->pipe;
3438         int plane = intel_crtc->plane;
3439         u32 reg, temp;
3440
3441
3442         if (!intel_crtc->active)
3443                 return;
3444
3445         for_each_encoder_on_crtc(dev, crtc, encoder)
3446                 encoder->disable(encoder);
3447
3448         intel_crtc_wait_for_pending_flips(crtc);
3449         drm_vblank_off(dev, pipe);
3450
3451         if (dev_priv->fbc.plane == plane)
3452                 intel_disable_fbc(dev);
3453
3454         intel_crtc_update_cursor(crtc, false);
3455         intel_disable_planes(crtc);
3456         intel_disable_plane(dev_priv, plane, pipe);
3457
3458         if (intel_crtc->config.has_pch_encoder)
3459                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3460
3461         intel_disable_pipe(dev_priv, pipe);
3462
3463         ironlake_pfit_disable(intel_crtc);
3464
3465         for_each_encoder_on_crtc(dev, crtc, encoder)
3466                 if (encoder->post_disable)
3467                         encoder->post_disable(encoder);
3468
3469         if (intel_crtc->config.has_pch_encoder) {
3470                 ironlake_fdi_disable(crtc);
3471
3472                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3473                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3474
3475                 if (HAS_PCH_CPT(dev)) {
3476                         /* disable TRANS_DP_CTL */
3477                         reg = TRANS_DP_CTL(pipe);
3478                         temp = I915_READ(reg);
3479                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3480                                   TRANS_DP_PORT_SEL_MASK);
3481                         temp |= TRANS_DP_PORT_SEL_NONE;
3482                         I915_WRITE(reg, temp);
3483
3484                         /* disable DPLL_SEL */
3485                         temp = I915_READ(PCH_DPLL_SEL);
3486                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3487                         I915_WRITE(PCH_DPLL_SEL, temp);
3488                 }
3489
3490                 /* disable PCH DPLL */
3491                 intel_disable_shared_dpll(intel_crtc);
3492
3493                 ironlake_fdi_pll_disable(intel_crtc);
3494         }
3495
3496         intel_crtc->active = false;
3497         intel_update_watermarks(dev);
3498
3499         mutex_lock(&dev->struct_mutex);
3500         intel_update_fbc(dev);
3501         mutex_unlock(&dev->struct_mutex);
3502 }
3503
3504 static void haswell_crtc_disable(struct drm_crtc *crtc)
3505 {
3506         struct drm_device *dev = crtc->dev;
3507         struct drm_i915_private *dev_priv = dev->dev_private;
3508         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3509         struct intel_encoder *encoder;
3510         int pipe = intel_crtc->pipe;
3511         int plane = intel_crtc->plane;
3512         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3513
3514         if (!intel_crtc->active)
3515                 return;
3516
3517         for_each_encoder_on_crtc(dev, crtc, encoder)
3518                 encoder->disable(encoder);
3519
3520         intel_crtc_wait_for_pending_flips(crtc);
3521         drm_vblank_off(dev, pipe);
3522
3523         /* FBC must be disabled before disabling the plane on HSW. */
3524         if (dev_priv->fbc.plane == plane)
3525                 intel_disable_fbc(dev);
3526
3527         hsw_disable_ips(intel_crtc);
3528
3529         intel_crtc_update_cursor(crtc, false);
3530         intel_disable_planes(crtc);
3531         intel_disable_plane(dev_priv, plane, pipe);
3532
3533         if (intel_crtc->config.has_pch_encoder)
3534                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3535         intel_disable_pipe(dev_priv, pipe);
3536
3537         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3538
3539         ironlake_pfit_disable(intel_crtc);
3540
3541         intel_ddi_disable_pipe_clock(intel_crtc);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 lpt_disable_pch_transcoder(dev_priv);
3549                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_shared_dpll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         intel_ddi_put_crtc_pll(crtc);
3570 }
3571
3572 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3573 {
3574         if (!enable && intel_crtc->overlay) {
3575                 struct drm_device *dev = intel_crtc->base.dev;
3576                 struct drm_i915_private *dev_priv = dev->dev_private;
3577
3578                 mutex_lock(&dev->struct_mutex);
3579                 dev_priv->mm.interruptible = false;
3580                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3581                 dev_priv->mm.interruptible = true;
3582                 mutex_unlock(&dev->struct_mutex);
3583         }
3584
3585         /* Let userspace switch the overlay on again. In most cases userspace
3586          * has to recompute where to put it anyway.
3587          */
3588 }
3589
3590 /**
3591  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3592  * cursor plane briefly if not already running after enabling the display
3593  * plane.
3594  * This workaround avoids occasional blank screens when self refresh is
3595  * enabled.
3596  */
3597 static void
3598 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3599 {
3600         u32 cntl = I915_READ(CURCNTR(pipe));
3601
3602         if ((cntl & CURSOR_MODE) == 0) {
3603                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3604
3605                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3606                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3607                 intel_wait_for_vblank(dev_priv->dev, pipe);
3608                 I915_WRITE(CURCNTR(pipe), cntl);
3609                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3610                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3611         }
3612 }
3613
3614 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3615 {
3616         struct drm_device *dev = crtc->base.dev;
3617         struct drm_i915_private *dev_priv = dev->dev_private;
3618         struct intel_crtc_config *pipe_config = &crtc->config;
3619
3620         if (!crtc->config.gmch_pfit.control)
3621                 return;
3622
3623         /*
3624          * The panel fitter should only be adjusted whilst the pipe is disabled,
3625          * according to register description and PRM.
3626          */
3627         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3628         assert_pipe_disabled(dev_priv, crtc->pipe);
3629
3630         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3631         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3632
3633         /* Border color in case we don't scale up to the full screen. Black by
3634          * default, change to something else for debugging. */
3635         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3636 }
3637
3638 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3639 {
3640         struct drm_device *dev = crtc->dev;
3641         struct drm_i915_private *dev_priv = dev->dev_private;
3642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643         struct intel_encoder *encoder;
3644         int pipe = intel_crtc->pipe;
3645         int plane = intel_crtc->plane;
3646
3647         WARN_ON(!crtc->enabled);
3648
3649         if (intel_crtc->active)
3650                 return;
3651
3652         intel_crtc->active = true;
3653         intel_update_watermarks(dev);
3654
3655         for_each_encoder_on_crtc(dev, crtc, encoder)
3656                 if (encoder->pre_pll_enable)
3657                         encoder->pre_pll_enable(encoder);
3658
3659         vlv_enable_pll(intel_crtc);
3660
3661         for_each_encoder_on_crtc(dev, crtc, encoder)
3662                 if (encoder->pre_enable)
3663                         encoder->pre_enable(encoder);
3664
3665         i9xx_pfit_enable(intel_crtc);
3666
3667         intel_crtc_load_lut(crtc);
3668
3669         intel_enable_pipe(dev_priv, pipe, false);
3670         intel_enable_plane(dev_priv, plane, pipe);
3671         intel_enable_planes(crtc);
3672         intel_crtc_update_cursor(crtc, true);
3673
3674         intel_update_fbc(dev);
3675
3676         for_each_encoder_on_crtc(dev, crtc, encoder)
3677                 encoder->enable(encoder);
3678 }
3679
3680 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3681 {
3682         struct drm_device *dev = crtc->dev;
3683         struct drm_i915_private *dev_priv = dev->dev_private;
3684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3685         struct intel_encoder *encoder;
3686         int pipe = intel_crtc->pipe;
3687         int plane = intel_crtc->plane;
3688
3689         WARN_ON(!crtc->enabled);
3690
3691         if (intel_crtc->active)
3692                 return;
3693
3694         intel_crtc->active = true;
3695         intel_update_watermarks(dev);
3696
3697         for_each_encoder_on_crtc(dev, crtc, encoder)
3698                 if (encoder->pre_enable)
3699                         encoder->pre_enable(encoder);
3700
3701         i9xx_enable_pll(intel_crtc);
3702
3703         i9xx_pfit_enable(intel_crtc);
3704
3705         intel_crtc_load_lut(crtc);
3706
3707         intel_enable_pipe(dev_priv, pipe, false);
3708         intel_enable_plane(dev_priv, plane, pipe);
3709         intel_enable_planes(crtc);
3710         /* The fixup needs to happen before cursor is enabled */
3711         if (IS_G4X(dev))
3712                 g4x_fixup_plane(dev_priv, pipe);
3713         intel_crtc_update_cursor(crtc, true);
3714
3715         /* Give the overlay scaler a chance to enable if it's on this pipe */
3716         intel_crtc_dpms_overlay(intel_crtc, true);
3717
3718         intel_update_fbc(dev);
3719
3720         for_each_encoder_on_crtc(dev, crtc, encoder)
3721                 encoder->enable(encoder);
3722 }
3723
3724 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3725 {
3726         struct drm_device *dev = crtc->base.dev;
3727         struct drm_i915_private *dev_priv = dev->dev_private;
3728
3729         if (!crtc->config.gmch_pfit.control)
3730                 return;
3731
3732         assert_pipe_disabled(dev_priv, crtc->pipe);
3733
3734         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3735                          I915_READ(PFIT_CONTROL));
3736         I915_WRITE(PFIT_CONTROL, 0);
3737 }
3738
3739 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3740 {
3741         struct drm_device *dev = crtc->dev;
3742         struct drm_i915_private *dev_priv = dev->dev_private;
3743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744         struct intel_encoder *encoder;
3745         int pipe = intel_crtc->pipe;
3746         int plane = intel_crtc->plane;
3747
3748         if (!intel_crtc->active)
3749                 return;
3750
3751         for_each_encoder_on_crtc(dev, crtc, encoder)
3752                 encoder->disable(encoder);
3753
3754         /* Give the overlay scaler a chance to disable if it's on this pipe */
3755         intel_crtc_wait_for_pending_flips(crtc);
3756         drm_vblank_off(dev, pipe);
3757
3758         if (dev_priv->fbc.plane == plane)
3759                 intel_disable_fbc(dev);
3760
3761         intel_crtc_dpms_overlay(intel_crtc, false);
3762         intel_crtc_update_cursor(crtc, false);
3763         intel_disable_planes(crtc);
3764         intel_disable_plane(dev_priv, plane, pipe);
3765
3766         intel_disable_pipe(dev_priv, pipe);
3767
3768         i9xx_pfit_disable(intel_crtc);
3769
3770         for_each_encoder_on_crtc(dev, crtc, encoder)
3771                 if (encoder->post_disable)
3772                         encoder->post_disable(encoder);
3773
3774         i9xx_disable_pll(dev_priv, pipe);
3775
3776         intel_crtc->active = false;
3777         intel_update_fbc(dev);
3778         intel_update_watermarks(dev);
3779 }
3780
3781 static void i9xx_crtc_off(struct drm_crtc *crtc)
3782 {
3783 }
3784
3785 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3786                                     bool enabled)
3787 {
3788         struct drm_device *dev = crtc->dev;
3789         struct drm_i915_master_private *master_priv;
3790         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3791         int pipe = intel_crtc->pipe;
3792
3793         if (!dev->primary->master)
3794                 return;
3795
3796         master_priv = dev->primary->master->driver_priv;
3797         if (!master_priv->sarea_priv)
3798                 return;
3799
3800         switch (pipe) {
3801         case 0:
3802                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3803                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3804                 break;
3805         case 1:
3806                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3807                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3808                 break;
3809         default:
3810                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3811                 break;
3812         }
3813 }
3814
3815 /**
3816  * Sets the power management mode of the pipe and plane.
3817  */
3818 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3819 {
3820         struct drm_device *dev = crtc->dev;
3821         struct drm_i915_private *dev_priv = dev->dev_private;
3822         struct intel_encoder *intel_encoder;
3823         bool enable = false;
3824
3825         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3826                 enable |= intel_encoder->connectors_active;
3827
3828         if (enable)
3829                 dev_priv->display.crtc_enable(crtc);
3830         else
3831                 dev_priv->display.crtc_disable(crtc);
3832
3833         intel_crtc_update_sarea(crtc, enable);
3834 }
3835
3836 static void intel_crtc_disable(struct drm_crtc *crtc)
3837 {
3838         struct drm_device *dev = crtc->dev;
3839         struct drm_connector *connector;
3840         struct drm_i915_private *dev_priv = dev->dev_private;
3841         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3842
3843         /* crtc should still be enabled when we disable it. */
3844         WARN_ON(!crtc->enabled);
3845
3846         dev_priv->display.crtc_disable(crtc);
3847         intel_crtc->eld_vld = false;
3848         intel_crtc_update_sarea(crtc, false);
3849         dev_priv->display.off(crtc);
3850
3851         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3852         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3853
3854         if (crtc->fb) {
3855                 mutex_lock(&dev->struct_mutex);
3856                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3857                 mutex_unlock(&dev->struct_mutex);
3858                 crtc->fb = NULL;
3859         }
3860
3861         /* Update computed state. */
3862         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3863                 if (!connector->encoder || !connector->encoder->crtc)
3864                         continue;
3865
3866                 if (connector->encoder->crtc != crtc)
3867                         continue;
3868
3869                 connector->dpms = DRM_MODE_DPMS_OFF;
3870                 to_intel_encoder(connector->encoder)->connectors_active = false;
3871         }
3872 }
3873
3874 void intel_modeset_disable(struct drm_device *dev)
3875 {
3876         struct drm_crtc *crtc;
3877
3878         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3879                 if (crtc->enabled)
3880                         intel_crtc_disable(crtc);
3881         }
3882 }
3883
3884 void intel_encoder_destroy(struct drm_encoder *encoder)
3885 {
3886         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3887
3888         drm_encoder_cleanup(encoder);
3889         kfree(intel_encoder);
3890 }
3891
3892 /* Simple dpms helper for encodres with just one connector, no cloning and only
3893  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3894  * state of the entire output pipe. */
3895 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3896 {
3897         if (mode == DRM_MODE_DPMS_ON) {
3898                 encoder->connectors_active = true;
3899
3900                 intel_crtc_update_dpms(encoder->base.crtc);
3901         } else {
3902                 encoder->connectors_active = false;
3903
3904                 intel_crtc_update_dpms(encoder->base.crtc);
3905         }
3906 }
3907
3908 /* Cross check the actual hw state with our own modeset state tracking (and it's
3909  * internal consistency). */
3910 static void intel_connector_check_state(struct intel_connector *connector)
3911 {
3912         if (connector->get_hw_state(connector)) {
3913                 struct intel_encoder *encoder = connector->encoder;
3914                 struct drm_crtc *crtc;
3915                 bool encoder_enabled;
3916                 enum pipe pipe;
3917
3918                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3919                               connector->base.base.id,
3920                               drm_get_connector_name(&connector->base));
3921
3922                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3923                      "wrong connector dpms state\n");
3924                 WARN(connector->base.encoder != &encoder->base,
3925                      "active connector not linked to encoder\n");
3926                 WARN(!encoder->connectors_active,
3927                      "encoder->connectors_active not set\n");
3928
3929                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3930                 WARN(!encoder_enabled, "encoder not enabled\n");
3931                 if (WARN_ON(!encoder->base.crtc))
3932                         return;
3933
3934                 crtc = encoder->base.crtc;
3935
3936                 WARN(!crtc->enabled, "crtc not enabled\n");
3937                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3938                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3939                      "encoder active on the wrong pipe\n");
3940         }
3941 }
3942
3943 /* Even simpler default implementation, if there's really no special case to
3944  * consider. */
3945 void intel_connector_dpms(struct drm_connector *connector, int mode)
3946 {
3947         struct intel_encoder *encoder = intel_attached_encoder(connector);
3948
3949         /* All the simple cases only support two dpms states. */
3950         if (mode != DRM_MODE_DPMS_ON)
3951                 mode = DRM_MODE_DPMS_OFF;
3952
3953         if (mode == connector->dpms)
3954                 return;
3955
3956         connector->dpms = mode;
3957
3958         /* Only need to change hw state when actually enabled */
3959         if (encoder->base.crtc)
3960                 intel_encoder_dpms(encoder, mode);
3961         else
3962                 WARN_ON(encoder->connectors_active != false);
3963
3964         intel_modeset_check_state(connector->dev);
3965 }
3966
3967 /* Simple connector->get_hw_state implementation for encoders that support only
3968  * one connector and no cloning and hence the encoder state determines the state
3969  * of the connector. */
3970 bool intel_connector_get_hw_state(struct intel_connector *connector)
3971 {
3972         enum pipe pipe = 0;
3973         struct intel_encoder *encoder = connector->encoder;
3974
3975         return encoder->get_hw_state(encoder, &pipe);
3976 }
3977
3978 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3979                                      struct intel_crtc_config *pipe_config)
3980 {
3981         struct drm_i915_private *dev_priv = dev->dev_private;
3982         struct intel_crtc *pipe_B_crtc =
3983                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3984
3985         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3986                       pipe_name(pipe), pipe_config->fdi_lanes);
3987         if (pipe_config->fdi_lanes > 4) {
3988                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3989                               pipe_name(pipe), pipe_config->fdi_lanes);
3990                 return false;
3991         }
3992
3993         if (IS_HASWELL(dev)) {
3994                 if (pipe_config->fdi_lanes > 2) {
3995                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3996                                       pipe_config->fdi_lanes);
3997                         return false;
3998                 } else {
3999                         return true;
4000                 }
4001         }
4002
4003         if (INTEL_INFO(dev)->num_pipes == 2)
4004                 return true;
4005
4006         /* Ivybridge 3 pipe is really complicated */
4007         switch (pipe) {
4008         case PIPE_A:
4009                 return true;
4010         case PIPE_B:
4011                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4012                     pipe_config->fdi_lanes > 2) {
4013                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4014                                       pipe_name(pipe), pipe_config->fdi_lanes);
4015                         return false;
4016                 }
4017                 return true;
4018         case PIPE_C:
4019                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4020                     pipe_B_crtc->config.fdi_lanes <= 2) {
4021                         if (pipe_config->fdi_lanes > 2) {
4022                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4023                                               pipe_name(pipe), pipe_config->fdi_lanes);
4024                                 return false;
4025                         }
4026                 } else {
4027                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4028                         return false;
4029                 }
4030                 return true;
4031         default:
4032                 BUG();
4033         }
4034 }
4035
4036 #define RETRY 1
4037 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4038                                        struct intel_crtc_config *pipe_config)
4039 {
4040         struct drm_device *dev = intel_crtc->base.dev;
4041         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4042         int lane, link_bw, fdi_dotclock;
4043         bool setup_ok, needs_recompute = false;
4044
4045 retry:
4046         /* FDI is a binary signal running at ~2.7GHz, encoding
4047          * each output octet as 10 bits. The actual frequency
4048          * is stored as a divider into a 100MHz clock, and the
4049          * mode pixel clock is stored in units of 1KHz.
4050          * Hence the bw of each lane in terms of the mode signal
4051          * is:
4052          */
4053         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4054
4055         fdi_dotclock = adjusted_mode->clock;
4056         fdi_dotclock /= pipe_config->pixel_multiplier;
4057
4058         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4059                                            pipe_config->pipe_bpp);
4060
4061         pipe_config->fdi_lanes = lane;
4062
4063         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4064                                link_bw, &pipe_config->fdi_m_n);
4065
4066         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4067                                             intel_crtc->pipe, pipe_config);
4068         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4069                 pipe_config->pipe_bpp -= 2*3;
4070                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4071                               pipe_config->pipe_bpp);
4072                 needs_recompute = true;
4073                 pipe_config->bw_constrained = true;
4074
4075                 goto retry;
4076         }
4077
4078         if (needs_recompute)
4079                 return RETRY;
4080
4081         return setup_ok ? 0 : -EINVAL;
4082 }
4083
4084 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4085                                    struct intel_crtc_config *pipe_config)
4086 {
4087         pipe_config->ips_enabled = i915_enable_ips &&
4088                                    hsw_crtc_supports_ips(crtc) &&
4089                                    pipe_config->pipe_bpp <= 24;
4090 }
4091
4092 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4093                                      struct intel_crtc_config *pipe_config)
4094 {
4095         struct drm_device *dev = crtc->base.dev;
4096         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4097
4098         if (HAS_PCH_SPLIT(dev)) {
4099                 /* FDI link clock is fixed at 2.7G */
4100                 if (pipe_config->requested_mode.clock * 3
4101                     > IRONLAKE_FDI_FREQ * 4)
4102                         return -EINVAL;
4103         }
4104
4105         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4106          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4107          */
4108         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4109                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4110                 return -EINVAL;
4111
4112         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4113                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4114         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4115                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4116                  * for lvds. */
4117                 pipe_config->pipe_bpp = 8*3;
4118         }
4119
4120         if (HAS_IPS(dev))
4121                 hsw_compute_ips_config(crtc, pipe_config);
4122
4123         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4124          * clock survives for now. */
4125         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4126                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4127
4128         if (pipe_config->has_pch_encoder)
4129                 return ironlake_fdi_compute_config(crtc, pipe_config);
4130
4131         return 0;
4132 }
4133
4134 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4135 {
4136         return 400000; /* FIXME */
4137 }
4138
4139 static int i945_get_display_clock_speed(struct drm_device *dev)
4140 {
4141         return 400000;
4142 }
4143
4144 static int i915_get_display_clock_speed(struct drm_device *dev)
4145 {
4146         return 333000;
4147 }
4148
4149 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4150 {
4151         return 200000;
4152 }
4153
4154 static int pnv_get_display_clock_speed(struct drm_device *dev)
4155 {
4156         u16 gcfgc = 0;
4157
4158         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4159
4160         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4161         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4162                 return 267000;
4163         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4164                 return 333000;
4165         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4166                 return 444000;
4167         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4168                 return 200000;
4169         default:
4170                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4171         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4172                 return 133000;
4173         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4174                 return 167000;
4175         }
4176 }
4177
4178 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4179 {
4180         u16 gcfgc = 0;
4181
4182         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4183
4184         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4185                 return 133000;
4186         else {
4187                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4188                 case GC_DISPLAY_CLOCK_333_MHZ:
4189                         return 333000;
4190                 default:
4191                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4192                         return 190000;
4193                 }
4194         }
4195 }
4196
4197 static int i865_get_display_clock_speed(struct drm_device *dev)
4198 {
4199         return 266000;
4200 }
4201
4202 static int i855_get_display_clock_speed(struct drm_device *dev)
4203 {
4204         u16 hpllcc = 0;
4205         /* Assume that the hardware is in the high speed state.  This
4206          * should be the default.
4207          */
4208         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4209         case GC_CLOCK_133_200:
4210         case GC_CLOCK_100_200:
4211                 return 200000;
4212         case GC_CLOCK_166_250:
4213                 return 250000;
4214         case GC_CLOCK_100_133:
4215                 return 133000;
4216         }
4217
4218         /* Shouldn't happen */
4219         return 0;
4220 }
4221
4222 static int i830_get_display_clock_speed(struct drm_device *dev)
4223 {
4224         return 133000;
4225 }
4226
4227 static void
4228 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4229 {
4230         while (*num > DATA_LINK_M_N_MASK ||
4231                *den > DATA_LINK_M_N_MASK) {
4232                 *num >>= 1;
4233                 *den >>= 1;
4234         }
4235 }
4236
4237 static void compute_m_n(unsigned int m, unsigned int n,
4238                         uint32_t *ret_m, uint32_t *ret_n)
4239 {
4240         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4241         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4242         intel_reduce_m_n_ratio(ret_m, ret_n);
4243 }
4244
4245 void
4246 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4247                        int pixel_clock, int link_clock,
4248                        struct intel_link_m_n *m_n)
4249 {
4250         m_n->tu = 64;
4251
4252         compute_m_n(bits_per_pixel * pixel_clock,
4253                     link_clock * nlanes * 8,
4254                     &m_n->gmch_m, &m_n->gmch_n);
4255
4256         compute_m_n(pixel_clock, link_clock,
4257                     &m_n->link_m, &m_n->link_n);
4258 }
4259
4260 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4261 {
4262         if (i915_panel_use_ssc >= 0)
4263                 return i915_panel_use_ssc != 0;
4264         return dev_priv->vbt.lvds_use_ssc
4265                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4266 }
4267
4268 static int vlv_get_refclk(struct drm_crtc *crtc)
4269 {
4270         struct drm_device *dev = crtc->dev;
4271         struct drm_i915_private *dev_priv = dev->dev_private;
4272         int refclk = 27000; /* for DP & HDMI */
4273
4274         return 100000; /* only one validated so far */
4275
4276         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4277                 refclk = 96000;
4278         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4279                 if (intel_panel_use_ssc(dev_priv))
4280                         refclk = 100000;
4281                 else
4282                         refclk = 96000;
4283         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4284                 refclk = 100000;
4285         }
4286
4287         return refclk;
4288 }
4289
4290 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4291 {
4292         struct drm_device *dev = crtc->dev;
4293         struct drm_i915_private *dev_priv = dev->dev_private;
4294         int refclk;
4295
4296         if (IS_VALLEYVIEW(dev)) {
4297                 refclk = vlv_get_refclk(crtc);
4298         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4299             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4300                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4301                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4302                               refclk / 1000);
4303         } else if (!IS_GEN2(dev)) {
4304                 refclk = 96000;
4305         } else {
4306                 refclk = 48000;
4307         }
4308
4309         return refclk;
4310 }
4311
4312 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4313 {
4314         return (1 << dpll->n) << 16 | dpll->m2;
4315 }
4316
4317 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4318 {
4319         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4320 }
4321
4322 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4323                                      intel_clock_t *reduced_clock)
4324 {
4325         struct drm_device *dev = crtc->base.dev;
4326         struct drm_i915_private *dev_priv = dev->dev_private;
4327         int pipe = crtc->pipe;
4328         u32 fp, fp2 = 0;
4329
4330         if (IS_PINEVIEW(dev)) {
4331                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4332                 if (reduced_clock)
4333                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4334         } else {
4335                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4336                 if (reduced_clock)
4337                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4338         }
4339
4340         I915_WRITE(FP0(pipe), fp);
4341         crtc->config.dpll_hw_state.fp0 = fp;
4342
4343         crtc->lowfreq_avail = false;
4344         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4345             reduced_clock && i915_powersave) {
4346                 I915_WRITE(FP1(pipe), fp2);
4347                 crtc->config.dpll_hw_state.fp1 = fp2;
4348                 crtc->lowfreq_avail = true;
4349         } else {
4350                 I915_WRITE(FP1(pipe), fp);
4351                 crtc->config.dpll_hw_state.fp1 = fp;
4352         }
4353 }
4354
4355 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4356 {
4357         u32 reg_val;
4358
4359         /*
4360          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4361          * and set it to a reasonable value instead.
4362          */
4363         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4364         reg_val &= 0xffffff00;
4365         reg_val |= 0x00000030;
4366         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4367
4368         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4369         reg_val &= 0x8cffffff;
4370         reg_val = 0x8c000000;
4371         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4372
4373         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4374         reg_val &= 0xffffff00;
4375         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4376
4377         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4378         reg_val &= 0x00ffffff;
4379         reg_val |= 0xb0000000;
4380         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4381 }
4382
4383 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4384                                          struct intel_link_m_n *m_n)
4385 {
4386         struct drm_device *dev = crtc->base.dev;
4387         struct drm_i915_private *dev_priv = dev->dev_private;
4388         int pipe = crtc->pipe;
4389
4390         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4391         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4392         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4393         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4394 }
4395
4396 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4397                                          struct intel_link_m_n *m_n)
4398 {
4399         struct drm_device *dev = crtc->base.dev;
4400         struct drm_i915_private *dev_priv = dev->dev_private;
4401         int pipe = crtc->pipe;
4402         enum transcoder transcoder = crtc->config.cpu_transcoder;
4403
4404         if (INTEL_INFO(dev)->gen >= 5) {
4405                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4406                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4407                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4408                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4409         } else {
4410                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4411                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4412                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4413                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4414         }
4415 }
4416
4417 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4418 {
4419         if (crtc->config.has_pch_encoder)
4420                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4421         else
4422                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4423 }
4424
4425 static void vlv_update_pll(struct intel_crtc *crtc)
4426 {
4427         struct drm_device *dev = crtc->base.dev;
4428         struct drm_i915_private *dev_priv = dev->dev_private;
4429         int pipe = crtc->pipe;
4430         u32 dpll, mdiv;
4431         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4432         bool is_hdmi;
4433         u32 coreclk, reg_val, dpll_md;
4434
4435         mutex_lock(&dev_priv->dpio_lock);
4436
4437         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4438
4439         bestn = crtc->config.dpll.n;
4440         bestm1 = crtc->config.dpll.m1;
4441         bestm2 = crtc->config.dpll.m2;
4442         bestp1 = crtc->config.dpll.p1;
4443         bestp2 = crtc->config.dpll.p2;
4444
4445         /* See eDP HDMI DPIO driver vbios notes doc */
4446
4447         /* PLL B needs special handling */
4448         if (pipe)
4449                 vlv_pllb_recal_opamp(dev_priv);
4450
4451         /* Set up Tx target for periodic Rcomp update */
4452         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4453
4454         /* Disable target IRef on PLL */
4455         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4456         reg_val &= 0x00ffffff;
4457         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4458
4459         /* Disable fast lock */
4460         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4461
4462         /* Set idtafcrecal before PLL is enabled */
4463         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4464         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4465         mdiv |= ((bestn << DPIO_N_SHIFT));
4466         mdiv |= (1 << DPIO_K_SHIFT);
4467
4468         /*
4469          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4470          * but we don't support that).
4471          * Note: don't use the DAC post divider as it seems unstable.
4472          */
4473         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4474         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4475
4476         mdiv |= DPIO_ENABLE_CALIBRATION;
4477         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4478
4479         /* Set HBR and RBR LPF coefficients */
4480         if (crtc->config.port_clock == 162000 ||
4481             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4482             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4483                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4484                                  0x009f0003);
4485         else
4486                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4487                                  0x00d0000f);
4488
4489         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4490             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4491                 /* Use SSC source */
4492                 if (!pipe)
4493                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4494                                          0x0df40000);
4495                 else
4496                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4497                                          0x0df70000);
4498         } else { /* HDMI or VGA */
4499                 /* Use bend source */
4500                 if (!pipe)
4501                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4502                                          0x0df70000);
4503                 else
4504                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4505                                          0x0df40000);
4506         }
4507
4508         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4509         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4510         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4511             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4512                 coreclk |= 0x01000000;
4513         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4514
4515         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4516
4517         /* Enable DPIO clock input */
4518         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4519                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4520         if (pipe)
4521                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4522
4523         dpll |= DPLL_VCO_ENABLE;
4524         crtc->config.dpll_hw_state.dpll = dpll;
4525
4526         dpll_md = (crtc->config.pixel_multiplier - 1)
4527                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4528         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4529
4530         if (crtc->config.has_dp_encoder)
4531                 intel_dp_set_m_n(crtc);
4532
4533         mutex_unlock(&dev_priv->dpio_lock);
4534 }
4535
4536 static void i9xx_update_pll(struct intel_crtc *crtc,
4537                             intel_clock_t *reduced_clock,
4538                             int num_connectors)
4539 {
4540         struct drm_device *dev = crtc->base.dev;
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         u32 dpll;
4543         bool is_sdvo;
4544         struct dpll *clock = &crtc->config.dpll;
4545
4546         i9xx_update_pll_dividers(crtc, reduced_clock);
4547
4548         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4549                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4550
4551         dpll = DPLL_VGA_MODE_DIS;
4552
4553         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4554                 dpll |= DPLLB_MODE_LVDS;
4555         else
4556                 dpll |= DPLLB_MODE_DAC_SERIAL;
4557
4558         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4559                 dpll |= (crtc->config.pixel_multiplier - 1)
4560                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4561         }
4562
4563         if (is_sdvo)
4564                 dpll |= DPLL_SDVO_HIGH_SPEED;
4565
4566         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4567                 dpll |= DPLL_SDVO_HIGH_SPEED;
4568
4569         /* compute bitmask from p1 value */
4570         if (IS_PINEVIEW(dev))
4571                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4572         else {
4573                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4574                 if (IS_G4X(dev) && reduced_clock)
4575                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4576         }
4577         switch (clock->p2) {
4578         case 5:
4579                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4580                 break;
4581         case 7:
4582                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4583                 break;
4584         case 10:
4585                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4586                 break;
4587         case 14:
4588                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4589                 break;
4590         }
4591         if (INTEL_INFO(dev)->gen >= 4)
4592                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4593
4594         if (crtc->config.sdvo_tv_clock)
4595                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4596         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4597                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4598                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4599         else
4600                 dpll |= PLL_REF_INPUT_DREFCLK;
4601
4602         dpll |= DPLL_VCO_ENABLE;
4603         crtc->config.dpll_hw_state.dpll = dpll;
4604
4605         if (INTEL_INFO(dev)->gen >= 4) {
4606                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4607                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4608                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4609         }
4610
4611         if (crtc->config.has_dp_encoder)
4612                 intel_dp_set_m_n(crtc);
4613 }
4614
4615 static void i8xx_update_pll(struct intel_crtc *crtc,
4616                             intel_clock_t *reduced_clock,
4617                             int num_connectors)
4618 {
4619         struct drm_device *dev = crtc->base.dev;
4620         struct drm_i915_private *dev_priv = dev->dev_private;
4621         u32 dpll;
4622         struct dpll *clock = &crtc->config.dpll;
4623
4624         i9xx_update_pll_dividers(crtc, reduced_clock);
4625
4626         dpll = DPLL_VGA_MODE_DIS;
4627
4628         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4629                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4630         } else {
4631                 if (clock->p1 == 2)
4632                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4633                 else
4634                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4635                 if (clock->p2 == 4)
4636                         dpll |= PLL_P2_DIVIDE_BY_4;
4637         }
4638
4639         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4640                 dpll |= DPLL_DVO_2X_MODE;
4641
4642         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4643                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4644                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4645         else
4646                 dpll |= PLL_REF_INPUT_DREFCLK;
4647
4648         dpll |= DPLL_VCO_ENABLE;
4649         crtc->config.dpll_hw_state.dpll = dpll;
4650 }
4651
4652 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4653 {
4654         struct drm_device *dev = intel_crtc->base.dev;
4655         struct drm_i915_private *dev_priv = dev->dev_private;
4656         enum pipe pipe = intel_crtc->pipe;
4657         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4658         struct drm_display_mode *adjusted_mode =
4659                 &intel_crtc->config.adjusted_mode;
4660         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4661         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4662
4663         /* We need to be careful not to changed the adjusted mode, for otherwise
4664          * the hw state checker will get angry at the mismatch. */
4665         crtc_vtotal = adjusted_mode->crtc_vtotal;
4666         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4667
4668         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4669                 /* the chip adds 2 halflines automatically */
4670                 crtc_vtotal -= 1;
4671                 crtc_vblank_end -= 1;
4672                 vsyncshift = adjusted_mode->crtc_hsync_start
4673                              - adjusted_mode->crtc_htotal / 2;
4674         } else {
4675                 vsyncshift = 0;
4676         }
4677
4678         if (INTEL_INFO(dev)->gen > 3)
4679                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4680
4681         I915_WRITE(HTOTAL(cpu_transcoder),
4682                    (adjusted_mode->crtc_hdisplay - 1) |
4683                    ((adjusted_mode->crtc_htotal - 1) << 16));
4684         I915_WRITE(HBLANK(cpu_transcoder),
4685                    (adjusted_mode->crtc_hblank_start - 1) |
4686                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4687         I915_WRITE(HSYNC(cpu_transcoder),
4688                    (adjusted_mode->crtc_hsync_start - 1) |
4689                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4690
4691         I915_WRITE(VTOTAL(cpu_transcoder),
4692                    (adjusted_mode->crtc_vdisplay - 1) |
4693                    ((crtc_vtotal - 1) << 16));
4694         I915_WRITE(VBLANK(cpu_transcoder),
4695                    (adjusted_mode->crtc_vblank_start - 1) |
4696                    ((crtc_vblank_end - 1) << 16));
4697         I915_WRITE(VSYNC(cpu_transcoder),
4698                    (adjusted_mode->crtc_vsync_start - 1) |
4699                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4700
4701         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4702          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4703          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4704          * bits. */
4705         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4706             (pipe == PIPE_B || pipe == PIPE_C))
4707                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4708
4709         /* pipesrc controls the size that is scaled from, which should
4710          * always be the user's requested size.
4711          */
4712         I915_WRITE(PIPESRC(pipe),
4713                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4714 }
4715
4716 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4717                                    struct intel_crtc_config *pipe_config)
4718 {
4719         struct drm_device *dev = crtc->base.dev;
4720         struct drm_i915_private *dev_priv = dev->dev_private;
4721         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4722         uint32_t tmp;
4723
4724         tmp = I915_READ(HTOTAL(cpu_transcoder));
4725         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4726         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4727         tmp = I915_READ(HBLANK(cpu_transcoder));
4728         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4729         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4730         tmp = I915_READ(HSYNC(cpu_transcoder));
4731         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4732         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4733
4734         tmp = I915_READ(VTOTAL(cpu_transcoder));
4735         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4736         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4737         tmp = I915_READ(VBLANK(cpu_transcoder));
4738         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4739         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4740         tmp = I915_READ(VSYNC(cpu_transcoder));
4741         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4742         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4743
4744         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4745                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4746                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4747                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4748         }
4749
4750         tmp = I915_READ(PIPESRC(crtc->pipe));
4751         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4752         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4753 }
4754
4755 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4756                                              struct intel_crtc_config *pipe_config)
4757 {
4758         struct drm_crtc *crtc = &intel_crtc->base;
4759
4760         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4761         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4762         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4763         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4764
4765         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4766         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4767         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4768         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4769
4770         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4771
4772         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4773         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4774 }
4775
4776 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4777 {
4778         struct drm_device *dev = intel_crtc->base.dev;
4779         struct drm_i915_private *dev_priv = dev->dev_private;
4780         uint32_t pipeconf;
4781
4782         pipeconf = 0;
4783
4784         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4785                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4786                  * core speed.
4787                  *
4788                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4789                  * pipe == 0 check?
4790                  */
4791                 if (intel_crtc->config.requested_mode.clock >
4792                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4793                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4794         }
4795
4796         /* only g4x and later have fancy bpc/dither controls */
4797         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4798                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4799                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4800                         pipeconf |= PIPECONF_DITHER_EN |
4801                                     PIPECONF_DITHER_TYPE_SP;
4802
4803                 switch (intel_crtc->config.pipe_bpp) {
4804                 case 18:
4805                         pipeconf |= PIPECONF_6BPC;
4806                         break;
4807                 case 24:
4808                         pipeconf |= PIPECONF_8BPC;
4809                         break;
4810                 case 30:
4811                         pipeconf |= PIPECONF_10BPC;
4812                         break;
4813                 default:
4814                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4815                         BUG();
4816                 }
4817         }
4818
4819         if (HAS_PIPE_CXSR(dev)) {
4820                 if (intel_crtc->lowfreq_avail) {
4821                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4822                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4823                 } else {
4824                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4825                 }
4826         }
4827
4828         if (!IS_GEN2(dev) &&
4829             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4830                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4831         else
4832                 pipeconf |= PIPECONF_PROGRESSIVE;
4833
4834         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4835                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4836
4837         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4838         POSTING_READ(PIPECONF(intel_crtc->pipe));
4839 }
4840
4841 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4842                               int x, int y,
4843                               struct drm_framebuffer *fb)
4844 {
4845         struct drm_device *dev = crtc->dev;
4846         struct drm_i915_private *dev_priv = dev->dev_private;
4847         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4848         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4849         int pipe = intel_crtc->pipe;
4850         int plane = intel_crtc->plane;
4851         int refclk, num_connectors = 0;
4852         intel_clock_t clock, reduced_clock;
4853         u32 dspcntr;
4854         bool ok, has_reduced_clock = false;
4855         bool is_lvds = false;
4856         struct intel_encoder *encoder;
4857         const intel_limit_t *limit;
4858         int ret;
4859
4860         for_each_encoder_on_crtc(dev, crtc, encoder) {
4861                 switch (encoder->type) {
4862                 case INTEL_OUTPUT_LVDS:
4863                         is_lvds = true;
4864                         break;
4865                 }
4866
4867                 num_connectors++;
4868         }
4869
4870         refclk = i9xx_get_refclk(crtc, num_connectors);
4871
4872         /*
4873          * Returns a set of divisors for the desired target clock with the given
4874          * refclk, or FALSE.  The returned values represent the clock equation:
4875          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4876          */
4877         limit = intel_limit(crtc, refclk);
4878         ok = dev_priv->display.find_dpll(limit, crtc,
4879                                          intel_crtc->config.port_clock,
4880                                          refclk, NULL, &clock);
4881         if (!ok && !intel_crtc->config.clock_set) {
4882                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4883                 return -EINVAL;
4884         }
4885
4886         /* Ensure that the cursor is valid for the new mode before changing... */
4887         intel_crtc_update_cursor(crtc, true);
4888
4889         if (is_lvds && dev_priv->lvds_downclock_avail) {
4890                 /*
4891                  * Ensure we match the reduced clock's P to the target clock.
4892                  * If the clocks don't match, we can't switch the display clock
4893                  * by using the FP0/FP1. In such case we will disable the LVDS
4894                  * downclock feature.
4895                 */
4896                 has_reduced_clock =
4897                         dev_priv->display.find_dpll(limit, crtc,
4898                                                     dev_priv->lvds_downclock,
4899                                                     refclk, &clock,
4900                                                     &reduced_clock);
4901         }
4902         /* Compat-code for transition, will disappear. */
4903         if (!intel_crtc->config.clock_set) {
4904                 intel_crtc->config.dpll.n = clock.n;
4905                 intel_crtc->config.dpll.m1 = clock.m1;
4906                 intel_crtc->config.dpll.m2 = clock.m2;
4907                 intel_crtc->config.dpll.p1 = clock.p1;
4908                 intel_crtc->config.dpll.p2 = clock.p2;
4909         }
4910
4911         if (IS_GEN2(dev))
4912                 i8xx_update_pll(intel_crtc,
4913                                 has_reduced_clock ? &reduced_clock : NULL,
4914                                 num_connectors);
4915         else if (IS_VALLEYVIEW(dev))
4916                 vlv_update_pll(intel_crtc);
4917         else
4918                 i9xx_update_pll(intel_crtc,
4919                                 has_reduced_clock ? &reduced_clock : NULL,
4920                                 num_connectors);
4921
4922         /* Set up the display plane register */
4923         dspcntr = DISPPLANE_GAMMA_ENABLE;
4924
4925         if (!IS_VALLEYVIEW(dev)) {
4926                 if (pipe == 0)
4927                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4928                 else
4929                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4930         }
4931
4932         intel_set_pipe_timings(intel_crtc);
4933
4934         /* pipesrc and dspsize control the size that is scaled from,
4935          * which should always be the user's requested size.
4936          */
4937         I915_WRITE(DSPSIZE(plane),
4938                    ((mode->vdisplay - 1) << 16) |
4939                    (mode->hdisplay - 1));
4940         I915_WRITE(DSPPOS(plane), 0);
4941
4942         i9xx_set_pipeconf(intel_crtc);
4943
4944         I915_WRITE(DSPCNTR(plane), dspcntr);
4945         POSTING_READ(DSPCNTR(plane));
4946
4947         ret = intel_pipe_set_base(crtc, x, y, fb);
4948
4949         intel_update_watermarks(dev);
4950
4951         return ret;
4952 }
4953
4954 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4955                                  struct intel_crtc_config *pipe_config)
4956 {
4957         struct drm_device *dev = crtc->base.dev;
4958         struct drm_i915_private *dev_priv = dev->dev_private;
4959         uint32_t tmp;
4960
4961         tmp = I915_READ(PFIT_CONTROL);
4962         if (!(tmp & PFIT_ENABLE))
4963                 return;
4964
4965         /* Check whether the pfit is attached to our pipe. */
4966         if (INTEL_INFO(dev)->gen < 4) {
4967                 if (crtc->pipe != PIPE_B)
4968                         return;
4969         } else {
4970                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4971                         return;
4972         }
4973
4974         pipe_config->gmch_pfit.control = tmp;
4975         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4976         if (INTEL_INFO(dev)->gen < 5)
4977                 pipe_config->gmch_pfit.lvds_border_bits =
4978                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4979 }
4980
4981 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4982                                  struct intel_crtc_config *pipe_config)
4983 {
4984         struct drm_device *dev = crtc->base.dev;
4985         struct drm_i915_private *dev_priv = dev->dev_private;
4986         uint32_t tmp;
4987
4988         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
4989         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4990
4991         tmp = I915_READ(PIPECONF(crtc->pipe));
4992         if (!(tmp & PIPECONF_ENABLE))
4993                 return false;
4994
4995         intel_get_pipe_timings(crtc, pipe_config);
4996
4997         i9xx_get_pfit_config(crtc, pipe_config);
4998
4999         if (INTEL_INFO(dev)->gen >= 4) {
5000                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5001                 pipe_config->pixel_multiplier =
5002                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5003                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5004                 pipe_config->dpll_hw_state.dpll_md = tmp;
5005         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5006                 tmp = I915_READ(DPLL(crtc->pipe));
5007                 pipe_config->pixel_multiplier =
5008                         ((tmp & SDVO_MULTIPLIER_MASK)
5009                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5010         } else {
5011                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5012                  * port and will be fixed up in the encoder->get_config
5013                  * function. */
5014                 pipe_config->pixel_multiplier = 1;
5015         }
5016         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5017         if (!IS_VALLEYVIEW(dev)) {
5018                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5019                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5020         } else {
5021                 /* Mask out read-only status bits. */
5022                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5023                                                      DPLL_PORTC_READY_MASK |
5024                                                      DPLL_PORTB_READY_MASK);
5025         }
5026
5027         return true;
5028 }
5029
5030 static void ironlake_init_pch_refclk(struct drm_device *dev)
5031 {
5032         struct drm_i915_private *dev_priv = dev->dev_private;
5033         struct drm_mode_config *mode_config = &dev->mode_config;
5034         struct intel_encoder *encoder;
5035         u32 val, final;
5036         bool has_lvds = false;
5037         bool has_cpu_edp = false;
5038         bool has_panel = false;
5039         bool has_ck505 = false;
5040         bool can_ssc = false;
5041
5042         /* We need to take the global config into account */
5043         list_for_each_entry(encoder, &mode_config->encoder_list,
5044                             base.head) {
5045                 switch (encoder->type) {
5046                 case INTEL_OUTPUT_LVDS:
5047                         has_panel = true;
5048                         has_lvds = true;
5049                         break;
5050                 case INTEL_OUTPUT_EDP:
5051                         has_panel = true;
5052                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5053                                 has_cpu_edp = true;
5054                         break;
5055                 }
5056         }
5057
5058         if (HAS_PCH_IBX(dev)) {
5059                 has_ck505 = dev_priv->vbt.display_clock_mode;
5060                 can_ssc = has_ck505;
5061         } else {
5062                 has_ck505 = false;
5063                 can_ssc = true;
5064         }
5065
5066         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5067                       has_panel, has_lvds, has_ck505);
5068
5069         /* Ironlake: try to setup display ref clock before DPLL
5070          * enabling. This is only under driver's control after
5071          * PCH B stepping, previous chipset stepping should be
5072          * ignoring this setting.
5073          */
5074         val = I915_READ(PCH_DREF_CONTROL);
5075
5076         /* As we must carefully and slowly disable/enable each source in turn,
5077          * compute the final state we want first and check if we need to
5078          * make any changes at all.
5079          */
5080         final = val;
5081         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5082         if (has_ck505)
5083                 final |= DREF_NONSPREAD_CK505_ENABLE;
5084         else
5085                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5086
5087         final &= ~DREF_SSC_SOURCE_MASK;
5088         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5089         final &= ~DREF_SSC1_ENABLE;
5090
5091         if (has_panel) {
5092                 final |= DREF_SSC_SOURCE_ENABLE;
5093
5094                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5095                         final |= DREF_SSC1_ENABLE;
5096
5097                 if (has_cpu_edp) {
5098                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5099                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5100                         else
5101                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5102                 } else
5103                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5104         } else {
5105                 final |= DREF_SSC_SOURCE_DISABLE;
5106                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5107         }
5108
5109         if (final == val)
5110                 return;
5111
5112         /* Always enable nonspread source */
5113         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5114
5115         if (has_ck505)
5116                 val |= DREF_NONSPREAD_CK505_ENABLE;
5117         else
5118                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5119
5120         if (has_panel) {
5121                 val &= ~DREF_SSC_SOURCE_MASK;
5122                 val |= DREF_SSC_SOURCE_ENABLE;
5123
5124                 /* SSC must be turned on before enabling the CPU output  */
5125                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5126                         DRM_DEBUG_KMS("Using SSC on panel\n");
5127                         val |= DREF_SSC1_ENABLE;
5128                 } else
5129                         val &= ~DREF_SSC1_ENABLE;
5130
5131                 /* Get SSC going before enabling the outputs */
5132                 I915_WRITE(PCH_DREF_CONTROL, val);
5133                 POSTING_READ(PCH_DREF_CONTROL);
5134                 udelay(200);
5135
5136                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5137
5138                 /* Enable CPU source on CPU attached eDP */
5139                 if (has_cpu_edp) {
5140                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5141                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5142                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5143                         }
5144                         else
5145                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5146                 } else
5147                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5148
5149                 I915_WRITE(PCH_DREF_CONTROL, val);
5150                 POSTING_READ(PCH_DREF_CONTROL);
5151                 udelay(200);
5152         } else {
5153                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5154
5155                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5156
5157                 /* Turn off CPU output */
5158                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5159
5160                 I915_WRITE(PCH_DREF_CONTROL, val);
5161                 POSTING_READ(PCH_DREF_CONTROL);
5162                 udelay(200);
5163
5164                 /* Turn off the SSC source */
5165                 val &= ~DREF_SSC_SOURCE_MASK;
5166                 val |= DREF_SSC_SOURCE_DISABLE;
5167
5168                 /* Turn off SSC1 */
5169                 val &= ~DREF_SSC1_ENABLE;
5170
5171                 I915_WRITE(PCH_DREF_CONTROL, val);
5172                 POSTING_READ(PCH_DREF_CONTROL);
5173                 udelay(200);
5174         }
5175
5176         BUG_ON(val != final);
5177 }
5178
5179 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5180 {
5181         uint32_t tmp;
5182
5183         tmp = I915_READ(SOUTH_CHICKEN2);
5184         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5185         I915_WRITE(SOUTH_CHICKEN2, tmp);
5186
5187         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5188                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5189                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5190
5191         tmp = I915_READ(SOUTH_CHICKEN2);
5192         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5193         I915_WRITE(SOUTH_CHICKEN2, tmp);
5194
5195         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5196                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5197                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5198 }
5199
5200 /* WaMPhyProgramming:hsw */
5201 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5202 {
5203         uint32_t tmp;
5204
5205         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5206         tmp &= ~(0xFF << 24);
5207         tmp |= (0x12 << 24);
5208         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5209
5210         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5211         tmp |= (1 << 11);
5212         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5213
5214         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5215         tmp |= (1 << 11);
5216         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5217
5218         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5219         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5220         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5221
5222         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5223         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5224         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5225
5226         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5227         tmp &= ~(7 << 13);
5228         tmp |= (5 << 13);
5229         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5230
5231         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5232         tmp &= ~(7 << 13);
5233         tmp |= (5 << 13);
5234         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5235
5236         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5237         tmp &= ~0xFF;
5238         tmp |= 0x1C;
5239         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5240
5241         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5242         tmp &= ~0xFF;
5243         tmp |= 0x1C;
5244         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5245
5246         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5247         tmp &= ~(0xFF << 16);
5248         tmp |= (0x1C << 16);
5249         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5252         tmp &= ~(0xFF << 16);
5253         tmp |= (0x1C << 16);
5254         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5255
5256         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5257         tmp |= (1 << 27);
5258         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5259
5260         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5261         tmp |= (1 << 27);
5262         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5263
5264         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5265         tmp &= ~(0xF << 28);
5266         tmp |= (4 << 28);
5267         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5268
5269         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5270         tmp &= ~(0xF << 28);
5271         tmp |= (4 << 28);
5272         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5273 }
5274
5275 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5276  * Programming" based on the parameters passed:
5277  * - Sequence to enable CLKOUT_DP
5278  * - Sequence to enable CLKOUT_DP without spread
5279  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5280  */
5281 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5282                                  bool with_fdi)
5283 {
5284         struct drm_i915_private *dev_priv = dev->dev_private;
5285         uint32_t reg, tmp;
5286
5287         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5288                 with_spread = true;
5289         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5290                  with_fdi, "LP PCH doesn't have FDI\n"))
5291                 with_fdi = false;
5292
5293         mutex_lock(&dev_priv->dpio_lock);
5294
5295         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5296         tmp &= ~SBI_SSCCTL_DISABLE;
5297         tmp |= SBI_SSCCTL_PATHALT;
5298         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5299
5300         udelay(24);
5301
5302         if (with_spread) {
5303                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5304                 tmp &= ~SBI_SSCCTL_PATHALT;
5305                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5306
5307                 if (with_fdi) {
5308                         lpt_reset_fdi_mphy(dev_priv);
5309                         lpt_program_fdi_mphy(dev_priv);
5310                 }
5311         }
5312
5313         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5314                SBI_GEN0 : SBI_DBUFF0;
5315         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5316         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5317         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5318
5319         mutex_unlock(&dev_priv->dpio_lock);
5320 }
5321
5322 /* Sequence to disable CLKOUT_DP */
5323 static void lpt_disable_clkout_dp(struct drm_device *dev)
5324 {
5325         struct drm_i915_private *dev_priv = dev->dev_private;
5326         uint32_t reg, tmp;
5327
5328         mutex_lock(&dev_priv->dpio_lock);
5329
5330         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5331                SBI_GEN0 : SBI_DBUFF0;
5332         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5333         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5334         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5335
5336         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5337         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5338                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5339                         tmp |= SBI_SSCCTL_PATHALT;
5340                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5341                         udelay(32);
5342                 }
5343                 tmp |= SBI_SSCCTL_DISABLE;
5344                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5345         }
5346
5347         mutex_unlock(&dev_priv->dpio_lock);
5348 }
5349
5350 static void lpt_init_pch_refclk(struct drm_device *dev)
5351 {
5352         struct drm_mode_config *mode_config = &dev->mode_config;
5353         struct intel_encoder *encoder;
5354         bool has_vga = false;
5355
5356         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5357                 switch (encoder->type) {
5358                 case INTEL_OUTPUT_ANALOG:
5359                         has_vga = true;
5360                         break;
5361                 }
5362         }
5363
5364         if (has_vga)
5365                 lpt_enable_clkout_dp(dev, true, true);
5366         else
5367                 lpt_disable_clkout_dp(dev);
5368 }
5369
5370 /*
5371  * Initialize reference clocks when the driver loads
5372  */
5373 void intel_init_pch_refclk(struct drm_device *dev)
5374 {
5375         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5376                 ironlake_init_pch_refclk(dev);
5377         else if (HAS_PCH_LPT(dev))
5378                 lpt_init_pch_refclk(dev);
5379 }
5380
5381 static int ironlake_get_refclk(struct drm_crtc *crtc)
5382 {
5383         struct drm_device *dev = crtc->dev;
5384         struct drm_i915_private *dev_priv = dev->dev_private;
5385         struct intel_encoder *encoder;
5386         int num_connectors = 0;
5387         bool is_lvds = false;
5388
5389         for_each_encoder_on_crtc(dev, crtc, encoder) {
5390                 switch (encoder->type) {
5391                 case INTEL_OUTPUT_LVDS:
5392                         is_lvds = true;
5393                         break;
5394                 }
5395                 num_connectors++;
5396         }
5397
5398         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5399                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5400                               dev_priv->vbt.lvds_ssc_freq);
5401                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5402         }
5403
5404         return 120000;
5405 }
5406
5407 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5408 {
5409         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5411         int pipe = intel_crtc->pipe;
5412         uint32_t val;
5413
5414         val = 0;
5415
5416         switch (intel_crtc->config.pipe_bpp) {
5417         case 18:
5418                 val |= PIPECONF_6BPC;
5419                 break;
5420         case 24:
5421                 val |= PIPECONF_8BPC;
5422                 break;
5423         case 30:
5424                 val |= PIPECONF_10BPC;
5425                 break;
5426         case 36:
5427                 val |= PIPECONF_12BPC;
5428                 break;
5429         default:
5430                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5431                 BUG();
5432         }
5433
5434         if (intel_crtc->config.dither)
5435                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5436
5437         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5438                 val |= PIPECONF_INTERLACED_ILK;
5439         else
5440                 val |= PIPECONF_PROGRESSIVE;
5441
5442         if (intel_crtc->config.limited_color_range)
5443                 val |= PIPECONF_COLOR_RANGE_SELECT;
5444
5445         I915_WRITE(PIPECONF(pipe), val);
5446         POSTING_READ(PIPECONF(pipe));
5447 }
5448
5449 /*
5450  * Set up the pipe CSC unit.
5451  *
5452  * Currently only full range RGB to limited range RGB conversion
5453  * is supported, but eventually this should handle various
5454  * RGB<->YCbCr scenarios as well.
5455  */
5456 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5457 {
5458         struct drm_device *dev = crtc->dev;
5459         struct drm_i915_private *dev_priv = dev->dev_private;
5460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5461         int pipe = intel_crtc->pipe;
5462         uint16_t coeff = 0x7800; /* 1.0 */
5463
5464         /*
5465          * TODO: Check what kind of values actually come out of the pipe
5466          * with these coeff/postoff values and adjust to get the best
5467          * accuracy. Perhaps we even need to take the bpc value into
5468          * consideration.
5469          */
5470
5471         if (intel_crtc->config.limited_color_range)
5472                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5473
5474         /*
5475          * GY/GU and RY/RU should be the other way around according
5476          * to BSpec, but reality doesn't agree. Just set them up in
5477          * a way that results in the correct picture.
5478          */
5479         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5480         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5481
5482         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5483         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5484
5485         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5486         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5487
5488         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5489         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5490         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5491
5492         if (INTEL_INFO(dev)->gen > 6) {
5493                 uint16_t postoff = 0;
5494
5495                 if (intel_crtc->config.limited_color_range)
5496                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5497
5498                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5499                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5500                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5501
5502                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5503         } else {
5504                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5505
5506                 if (intel_crtc->config.limited_color_range)
5507                         mode |= CSC_BLACK_SCREEN_OFFSET;
5508
5509                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5510         }
5511 }
5512
5513 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5514 {
5515         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5517         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5518         uint32_t val;
5519
5520         val = 0;
5521
5522         if (intel_crtc->config.dither)
5523                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5524
5525         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5526                 val |= PIPECONF_INTERLACED_ILK;
5527         else
5528                 val |= PIPECONF_PROGRESSIVE;
5529
5530         I915_WRITE(PIPECONF(cpu_transcoder), val);
5531         POSTING_READ(PIPECONF(cpu_transcoder));
5532
5533         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5534         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5535 }
5536
5537 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5538                                     intel_clock_t *clock,
5539                                     bool *has_reduced_clock,
5540                                     intel_clock_t *reduced_clock)
5541 {
5542         struct drm_device *dev = crtc->dev;
5543         struct drm_i915_private *dev_priv = dev->dev_private;
5544         struct intel_encoder *intel_encoder;
5545         int refclk;
5546         const intel_limit_t *limit;
5547         bool ret, is_lvds = false;
5548
5549         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5550                 switch (intel_encoder->type) {
5551                 case INTEL_OUTPUT_LVDS:
5552                         is_lvds = true;
5553                         break;
5554                 }
5555         }
5556
5557         refclk = ironlake_get_refclk(crtc);
5558
5559         /*
5560          * Returns a set of divisors for the desired target clock with the given
5561          * refclk, or FALSE.  The returned values represent the clock equation:
5562          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5563          */
5564         limit = intel_limit(crtc, refclk);
5565         ret = dev_priv->display.find_dpll(limit, crtc,
5566                                           to_intel_crtc(crtc)->config.port_clock,
5567                                           refclk, NULL, clock);
5568         if (!ret)
5569                 return false;
5570
5571         if (is_lvds && dev_priv->lvds_downclock_avail) {
5572                 /*
5573                  * Ensure we match the reduced clock's P to the target clock.
5574                  * If the clocks don't match, we can't switch the display clock
5575                  * by using the FP0/FP1. In such case we will disable the LVDS
5576                  * downclock feature.
5577                 */
5578                 *has_reduced_clock =
5579                         dev_priv->display.find_dpll(limit, crtc,
5580                                                     dev_priv->lvds_downclock,
5581                                                     refclk, clock,
5582                                                     reduced_clock);
5583         }
5584
5585         return true;
5586 }
5587
5588 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5589 {
5590         struct drm_i915_private *dev_priv = dev->dev_private;
5591         uint32_t temp;
5592
5593         temp = I915_READ(SOUTH_CHICKEN1);
5594         if (temp & FDI_BC_BIFURCATION_SELECT)
5595                 return;
5596
5597         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5598         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5599
5600         temp |= FDI_BC_BIFURCATION_SELECT;
5601         DRM_DEBUG_KMS("enabling fdi C rx\n");
5602         I915_WRITE(SOUTH_CHICKEN1, temp);
5603         POSTING_READ(SOUTH_CHICKEN1);
5604 }
5605
5606 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5607 {
5608         struct drm_device *dev = intel_crtc->base.dev;
5609         struct drm_i915_private *dev_priv = dev->dev_private;
5610
5611         switch (intel_crtc->pipe) {
5612         case PIPE_A:
5613                 break;
5614         case PIPE_B:
5615                 if (intel_crtc->config.fdi_lanes > 2)
5616                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5617                 else
5618                         cpt_enable_fdi_bc_bifurcation(dev);
5619
5620                 break;
5621         case PIPE_C:
5622                 cpt_enable_fdi_bc_bifurcation(dev);
5623
5624                 break;
5625         default:
5626                 BUG();
5627         }
5628 }
5629
5630 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5631 {
5632         /*
5633          * Account for spread spectrum to avoid
5634          * oversubscribing the link. Max center spread
5635          * is 2.5%; use 5% for safety's sake.
5636          */
5637         u32 bps = target_clock * bpp * 21 / 20;
5638         return bps / (link_bw * 8) + 1;
5639 }
5640
5641 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5642 {
5643         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5644 }
5645
5646 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5647                                       u32 *fp,
5648                                       intel_clock_t *reduced_clock, u32 *fp2)
5649 {
5650         struct drm_crtc *crtc = &intel_crtc->base;
5651         struct drm_device *dev = crtc->dev;
5652         struct drm_i915_private *dev_priv = dev->dev_private;
5653         struct intel_encoder *intel_encoder;
5654         uint32_t dpll;
5655         int factor, num_connectors = 0;
5656         bool is_lvds = false, is_sdvo = false;
5657
5658         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5659                 switch (intel_encoder->type) {
5660                 case INTEL_OUTPUT_LVDS:
5661                         is_lvds = true;
5662                         break;
5663                 case INTEL_OUTPUT_SDVO:
5664                 case INTEL_OUTPUT_HDMI:
5665                         is_sdvo = true;
5666                         break;
5667                 }
5668
5669                 num_connectors++;
5670         }
5671
5672         /* Enable autotuning of the PLL clock (if permissible) */
5673         factor = 21;
5674         if (is_lvds) {
5675                 if ((intel_panel_use_ssc(dev_priv) &&
5676                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5677                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5678                         factor = 25;
5679         } else if (intel_crtc->config.sdvo_tv_clock)
5680                 factor = 20;
5681
5682         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5683                 *fp |= FP_CB_TUNE;
5684
5685         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5686                 *fp2 |= FP_CB_TUNE;
5687
5688         dpll = 0;
5689
5690         if (is_lvds)
5691                 dpll |= DPLLB_MODE_LVDS;
5692         else
5693                 dpll |= DPLLB_MODE_DAC_SERIAL;
5694
5695         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5696                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5697
5698         if (is_sdvo)
5699                 dpll |= DPLL_SDVO_HIGH_SPEED;
5700         if (intel_crtc->config.has_dp_encoder)
5701                 dpll |= DPLL_SDVO_HIGH_SPEED;
5702
5703         /* compute bitmask from p1 value */
5704         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5705         /* also FPA1 */
5706         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5707
5708         switch (intel_crtc->config.dpll.p2) {
5709         case 5:
5710                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5711                 break;
5712         case 7:
5713                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5714                 break;
5715         case 10:
5716                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5717                 break;
5718         case 14:
5719                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5720                 break;
5721         }
5722
5723         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5724                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5725         else
5726                 dpll |= PLL_REF_INPUT_DREFCLK;
5727
5728         return dpll | DPLL_VCO_ENABLE;
5729 }
5730
5731 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5732                                   int x, int y,
5733                                   struct drm_framebuffer *fb)
5734 {
5735         struct drm_device *dev = crtc->dev;
5736         struct drm_i915_private *dev_priv = dev->dev_private;
5737         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5738         int pipe = intel_crtc->pipe;
5739         int plane = intel_crtc->plane;
5740         int num_connectors = 0;
5741         intel_clock_t clock, reduced_clock;
5742         u32 dpll = 0, fp = 0, fp2 = 0;
5743         bool ok, has_reduced_clock = false;
5744         bool is_lvds = false;
5745         struct intel_encoder *encoder;
5746         struct intel_shared_dpll *pll;
5747         int ret;
5748
5749         for_each_encoder_on_crtc(dev, crtc, encoder) {
5750                 switch (encoder->type) {
5751                 case INTEL_OUTPUT_LVDS:
5752                         is_lvds = true;
5753                         break;
5754                 }
5755
5756                 num_connectors++;
5757         }
5758
5759         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5760              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5761
5762         ok = ironlake_compute_clocks(crtc, &clock,
5763                                      &has_reduced_clock, &reduced_clock);
5764         if (!ok && !intel_crtc->config.clock_set) {
5765                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5766                 return -EINVAL;
5767         }
5768         /* Compat-code for transition, will disappear. */
5769         if (!intel_crtc->config.clock_set) {
5770                 intel_crtc->config.dpll.n = clock.n;
5771                 intel_crtc->config.dpll.m1 = clock.m1;
5772                 intel_crtc->config.dpll.m2 = clock.m2;
5773                 intel_crtc->config.dpll.p1 = clock.p1;
5774                 intel_crtc->config.dpll.p2 = clock.p2;
5775         }
5776
5777         /* Ensure that the cursor is valid for the new mode before changing... */
5778         intel_crtc_update_cursor(crtc, true);
5779
5780         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5781         if (intel_crtc->config.has_pch_encoder) {
5782                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5783                 if (has_reduced_clock)
5784                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5785
5786                 dpll = ironlake_compute_dpll(intel_crtc,
5787                                              &fp, &reduced_clock,
5788                                              has_reduced_clock ? &fp2 : NULL);
5789
5790                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5791                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5792                 if (has_reduced_clock)
5793                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5794                 else
5795                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5796
5797                 pll = intel_get_shared_dpll(intel_crtc);
5798                 if (pll == NULL) {
5799                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5800                                          pipe_name(pipe));
5801                         return -EINVAL;
5802                 }
5803         } else
5804                 intel_put_shared_dpll(intel_crtc);
5805
5806         if (intel_crtc->config.has_dp_encoder)
5807                 intel_dp_set_m_n(intel_crtc);
5808
5809         if (is_lvds && has_reduced_clock && i915_powersave)
5810                 intel_crtc->lowfreq_avail = true;
5811         else
5812                 intel_crtc->lowfreq_avail = false;
5813
5814         if (intel_crtc->config.has_pch_encoder) {
5815                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5816
5817         }
5818
5819         intel_set_pipe_timings(intel_crtc);
5820
5821         if (intel_crtc->config.has_pch_encoder) {
5822                 intel_cpu_transcoder_set_m_n(intel_crtc,
5823                                              &intel_crtc->config.fdi_m_n);
5824         }
5825
5826         if (IS_IVYBRIDGE(dev))
5827                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5828
5829         ironlake_set_pipeconf(crtc);
5830
5831         /* Set up the display plane register */
5832         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5833         POSTING_READ(DSPCNTR(plane));
5834
5835         ret = intel_pipe_set_base(crtc, x, y, fb);
5836
5837         intel_update_watermarks(dev);
5838
5839         return ret;
5840 }
5841
5842 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5843                                         struct intel_crtc_config *pipe_config)
5844 {
5845         struct drm_device *dev = crtc->base.dev;
5846         struct drm_i915_private *dev_priv = dev->dev_private;
5847         enum transcoder transcoder = pipe_config->cpu_transcoder;
5848
5849         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5850         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5851         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5852                                         & ~TU_SIZE_MASK;
5853         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5854         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5855                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5856 }
5857
5858 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5859                                      struct intel_crtc_config *pipe_config)
5860 {
5861         struct drm_device *dev = crtc->base.dev;
5862         struct drm_i915_private *dev_priv = dev->dev_private;
5863         uint32_t tmp;
5864
5865         tmp = I915_READ(PF_CTL(crtc->pipe));
5866
5867         if (tmp & PF_ENABLE) {
5868                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5869                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5870
5871                 /* We currently do not free assignements of panel fitters on
5872                  * ivb/hsw (since we don't use the higher upscaling modes which
5873                  * differentiates them) so just WARN about this case for now. */
5874                 if (IS_GEN7(dev)) {
5875                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5876                                 PF_PIPE_SEL_IVB(crtc->pipe));
5877                 }
5878         }
5879 }
5880
5881 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5882                                      struct intel_crtc_config *pipe_config)
5883 {
5884         struct drm_device *dev = crtc->base.dev;
5885         struct drm_i915_private *dev_priv = dev->dev_private;
5886         uint32_t tmp;
5887
5888         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5889         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5890
5891         tmp = I915_READ(PIPECONF(crtc->pipe));
5892         if (!(tmp & PIPECONF_ENABLE))
5893                 return false;
5894
5895         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5896                 struct intel_shared_dpll *pll;
5897
5898                 pipe_config->has_pch_encoder = true;
5899
5900                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5901                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5902                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5903
5904                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5905
5906                 if (HAS_PCH_IBX(dev_priv->dev)) {
5907                         pipe_config->shared_dpll =
5908                                 (enum intel_dpll_id) crtc->pipe;
5909                 } else {
5910                         tmp = I915_READ(PCH_DPLL_SEL);
5911                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5912                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5913                         else
5914                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5915                 }
5916
5917                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5918
5919                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5920                                            &pipe_config->dpll_hw_state));
5921
5922                 tmp = pipe_config->dpll_hw_state.dpll;
5923                 pipe_config->pixel_multiplier =
5924                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5925                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5926         } else {
5927                 pipe_config->pixel_multiplier = 1;
5928         }
5929
5930         intel_get_pipe_timings(crtc, pipe_config);
5931
5932         ironlake_get_pfit_config(crtc, pipe_config);
5933
5934         return true;
5935 }
5936
5937 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5938 {
5939         struct drm_device *dev = dev_priv->dev;
5940         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5941         struct intel_crtc *crtc;
5942         unsigned long irqflags;
5943         uint32_t val, pch_hpd_mask;
5944
5945         pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
5946         if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
5947                 pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
5948
5949         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5950                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5951                      pipe_name(crtc->pipe));
5952
5953         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5954         WARN(plls->spll_refcount, "SPLL enabled\n");
5955         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5956         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5957         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5958         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5959              "CPU PWM1 enabled\n");
5960         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5961              "CPU PWM2 enabled\n");
5962         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5963              "PCH PWM1 enabled\n");
5964         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5965              "Utility pin enabled\n");
5966         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5967
5968         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5969         val = I915_READ(DEIMR);
5970         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5971              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5972         val = I915_READ(SDEIMR);
5973         WARN((val & ~pch_hpd_mask) != val,
5974              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5975         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5976 }
5977
5978 /*
5979  * This function implements pieces of two sequences from BSpec:
5980  * - Sequence for display software to disable LCPLL
5981  * - Sequence for display software to allow package C8+
5982  * The steps implemented here are just the steps that actually touch the LCPLL
5983  * register. Callers should take care of disabling all the display engine
5984  * functions, doing the mode unset, fixing interrupts, etc.
5985  */
5986 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5987                        bool switch_to_fclk, bool allow_power_down)
5988 {
5989         uint32_t val;
5990
5991         assert_can_disable_lcpll(dev_priv);
5992
5993         val = I915_READ(LCPLL_CTL);
5994
5995         if (switch_to_fclk) {
5996                 val |= LCPLL_CD_SOURCE_FCLK;
5997                 I915_WRITE(LCPLL_CTL, val);
5998
5999                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6000                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6001                         DRM_ERROR("Switching to FCLK failed\n");
6002
6003                 val = I915_READ(LCPLL_CTL);
6004         }
6005
6006         val |= LCPLL_PLL_DISABLE;
6007         I915_WRITE(LCPLL_CTL, val);
6008         POSTING_READ(LCPLL_CTL);
6009
6010         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6011                 DRM_ERROR("LCPLL still locked\n");
6012
6013         val = I915_READ(D_COMP);
6014         val |= D_COMP_COMP_DISABLE;
6015         I915_WRITE(D_COMP, val);
6016         POSTING_READ(D_COMP);
6017         ndelay(100);
6018
6019         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6020                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6021
6022         if (allow_power_down) {
6023                 val = I915_READ(LCPLL_CTL);
6024                 val |= LCPLL_POWER_DOWN_ALLOW;
6025                 I915_WRITE(LCPLL_CTL, val);
6026                 POSTING_READ(LCPLL_CTL);
6027         }
6028 }
6029
6030 /*
6031  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6032  * source.
6033  */
6034 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6035 {
6036         uint32_t val;
6037
6038         val = I915_READ(LCPLL_CTL);
6039
6040         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6041                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6042                 return;
6043
6044         if (val & LCPLL_POWER_DOWN_ALLOW) {
6045                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6046                 I915_WRITE(LCPLL_CTL, val);
6047         }
6048
6049         val = I915_READ(D_COMP);
6050         val |= D_COMP_COMP_FORCE;
6051         val &= ~D_COMP_COMP_DISABLE;
6052         I915_WRITE(D_COMP, val);
6053         I915_READ(D_COMP);
6054
6055         val = I915_READ(LCPLL_CTL);
6056         val &= ~LCPLL_PLL_DISABLE;
6057         I915_WRITE(LCPLL_CTL, val);
6058
6059         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6060                 DRM_ERROR("LCPLL not locked yet\n");
6061
6062         if (val & LCPLL_CD_SOURCE_FCLK) {
6063                 val = I915_READ(LCPLL_CTL);
6064                 val &= ~LCPLL_CD_SOURCE_FCLK;
6065                 I915_WRITE(LCPLL_CTL, val);
6066
6067                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6068                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6069                         DRM_ERROR("Switching back to LCPLL failed\n");
6070         }
6071 }
6072
6073 static void haswell_modeset_global_resources(struct drm_device *dev)
6074 {
6075         bool enable = false;
6076         struct intel_crtc *crtc;
6077
6078         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6079                 if (!crtc->base.enabled)
6080                         continue;
6081
6082                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6083                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6084                         enable = true;
6085         }
6086
6087         intel_set_power_well(dev, enable);
6088 }
6089
6090 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6091                                  int x, int y,
6092                                  struct drm_framebuffer *fb)
6093 {
6094         struct drm_device *dev = crtc->dev;
6095         struct drm_i915_private *dev_priv = dev->dev_private;
6096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6097         int plane = intel_crtc->plane;
6098         int ret;
6099
6100         if (!intel_ddi_pll_mode_set(crtc))
6101                 return -EINVAL;
6102
6103         /* Ensure that the cursor is valid for the new mode before changing... */
6104         intel_crtc_update_cursor(crtc, true);
6105
6106         if (intel_crtc->config.has_dp_encoder)
6107                 intel_dp_set_m_n(intel_crtc);
6108
6109         intel_crtc->lowfreq_avail = false;
6110
6111         intel_set_pipe_timings(intel_crtc);
6112
6113         if (intel_crtc->config.has_pch_encoder) {
6114                 intel_cpu_transcoder_set_m_n(intel_crtc,
6115                                              &intel_crtc->config.fdi_m_n);
6116         }
6117
6118         haswell_set_pipeconf(crtc);
6119
6120         intel_set_pipe_csc(crtc);
6121
6122         /* Set up the display plane register */
6123         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6124         POSTING_READ(DSPCNTR(plane));
6125
6126         ret = intel_pipe_set_base(crtc, x, y, fb);
6127
6128         intel_update_watermarks(dev);
6129
6130         return ret;
6131 }
6132
6133 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6134                                     struct intel_crtc_config *pipe_config)
6135 {
6136         struct drm_device *dev = crtc->base.dev;
6137         struct drm_i915_private *dev_priv = dev->dev_private;
6138         enum intel_display_power_domain pfit_domain;
6139         uint32_t tmp;
6140
6141         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6142         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6143
6144         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6145         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6146                 enum pipe trans_edp_pipe;
6147                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6148                 default:
6149                         WARN(1, "unknown pipe linked to edp transcoder\n");
6150                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6151                 case TRANS_DDI_EDP_INPUT_A_ON:
6152                         trans_edp_pipe = PIPE_A;
6153                         break;
6154                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6155                         trans_edp_pipe = PIPE_B;
6156                         break;
6157                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6158                         trans_edp_pipe = PIPE_C;
6159                         break;
6160                 }
6161
6162                 if (trans_edp_pipe == crtc->pipe)
6163                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6164         }
6165
6166         if (!intel_display_power_enabled(dev,
6167                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6168                 return false;
6169
6170         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6171         if (!(tmp & PIPECONF_ENABLE))
6172                 return false;
6173
6174         /*
6175          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6176          * DDI E. So just check whether this pipe is wired to DDI E and whether
6177          * the PCH transcoder is on.
6178          */
6179         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6180         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6181             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6182                 pipe_config->has_pch_encoder = true;
6183
6184                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6185                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6186                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6187
6188                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6189         }
6190
6191         intel_get_pipe_timings(crtc, pipe_config);
6192
6193         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6194         if (intel_display_power_enabled(dev, pfit_domain))
6195                 ironlake_get_pfit_config(crtc, pipe_config);
6196
6197         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6198                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6199
6200         pipe_config->pixel_multiplier = 1;
6201
6202         return true;
6203 }
6204
6205 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6206                                int x, int y,
6207                                struct drm_framebuffer *fb)
6208 {
6209         struct drm_device *dev = crtc->dev;
6210         struct drm_i915_private *dev_priv = dev->dev_private;
6211         struct intel_encoder *encoder;
6212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6213         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6214         int pipe = intel_crtc->pipe;
6215         int ret;
6216
6217         drm_vblank_pre_modeset(dev, pipe);
6218
6219         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6220
6221         drm_vblank_post_modeset(dev, pipe);
6222
6223         if (ret != 0)
6224                 return ret;
6225
6226         for_each_encoder_on_crtc(dev, crtc, encoder) {
6227                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6228                         encoder->base.base.id,
6229                         drm_get_encoder_name(&encoder->base),
6230                         mode->base.id, mode->name);
6231                 encoder->mode_set(encoder);
6232         }
6233
6234         return 0;
6235 }
6236
6237 static bool intel_eld_uptodate(struct drm_connector *connector,
6238                                int reg_eldv, uint32_t bits_eldv,
6239                                int reg_elda, uint32_t bits_elda,
6240                                int reg_edid)
6241 {
6242         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6243         uint8_t *eld = connector->eld;
6244         uint32_t i;
6245
6246         i = I915_READ(reg_eldv);
6247         i &= bits_eldv;
6248
6249         if (!eld[0])
6250                 return !i;
6251
6252         if (!i)
6253                 return false;
6254
6255         i = I915_READ(reg_elda);
6256         i &= ~bits_elda;
6257         I915_WRITE(reg_elda, i);
6258
6259         for (i = 0; i < eld[2]; i++)
6260                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6261                         return false;
6262
6263         return true;
6264 }
6265
6266 static void g4x_write_eld(struct drm_connector *connector,
6267                           struct drm_crtc *crtc)
6268 {
6269         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6270         uint8_t *eld = connector->eld;
6271         uint32_t eldv;
6272         uint32_t len;
6273         uint32_t i;
6274
6275         i = I915_READ(G4X_AUD_VID_DID);
6276
6277         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6278                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6279         else
6280                 eldv = G4X_ELDV_DEVCTG;
6281
6282         if (intel_eld_uptodate(connector,
6283                                G4X_AUD_CNTL_ST, eldv,
6284                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6285                                G4X_HDMIW_HDMIEDID))
6286                 return;
6287
6288         i = I915_READ(G4X_AUD_CNTL_ST);
6289         i &= ~(eldv | G4X_ELD_ADDR);
6290         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6291         I915_WRITE(G4X_AUD_CNTL_ST, i);
6292
6293         if (!eld[0])
6294                 return;
6295
6296         len = min_t(uint8_t, eld[2], len);
6297         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6298         for (i = 0; i < len; i++)
6299                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6300
6301         i = I915_READ(G4X_AUD_CNTL_ST);
6302         i |= eldv;
6303         I915_WRITE(G4X_AUD_CNTL_ST, i);
6304 }
6305
6306 static void haswell_write_eld(struct drm_connector *connector,
6307                                      struct drm_crtc *crtc)
6308 {
6309         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6310         uint8_t *eld = connector->eld;
6311         struct drm_device *dev = crtc->dev;
6312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6313         uint32_t eldv;
6314         uint32_t i;
6315         int len;
6316         int pipe = to_intel_crtc(crtc)->pipe;
6317         int tmp;
6318
6319         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6320         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6321         int aud_config = HSW_AUD_CFG(pipe);
6322         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6323
6324
6325         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6326
6327         /* Audio output enable */
6328         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6329         tmp = I915_READ(aud_cntrl_st2);
6330         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6331         I915_WRITE(aud_cntrl_st2, tmp);
6332
6333         /* Wait for 1 vertical blank */
6334         intel_wait_for_vblank(dev, pipe);
6335
6336         /* Set ELD valid state */
6337         tmp = I915_READ(aud_cntrl_st2);
6338         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6339         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6340         I915_WRITE(aud_cntrl_st2, tmp);
6341         tmp = I915_READ(aud_cntrl_st2);
6342         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6343
6344         /* Enable HDMI mode */
6345         tmp = I915_READ(aud_config);
6346         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6347         /* clear N_programing_enable and N_value_index */
6348         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6349         I915_WRITE(aud_config, tmp);
6350
6351         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6352
6353         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6354         intel_crtc->eld_vld = true;
6355
6356         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6357                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6358                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6359                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6360         } else
6361                 I915_WRITE(aud_config, 0);
6362
6363         if (intel_eld_uptodate(connector,
6364                                aud_cntrl_st2, eldv,
6365                                aud_cntl_st, IBX_ELD_ADDRESS,
6366                                hdmiw_hdmiedid))
6367                 return;
6368
6369         i = I915_READ(aud_cntrl_st2);
6370         i &= ~eldv;
6371         I915_WRITE(aud_cntrl_st2, i);
6372
6373         if (!eld[0])
6374                 return;
6375
6376         i = I915_READ(aud_cntl_st);
6377         i &= ~IBX_ELD_ADDRESS;
6378         I915_WRITE(aud_cntl_st, i);
6379         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6380         DRM_DEBUG_DRIVER("port num:%d\n", i);
6381
6382         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6383         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6384         for (i = 0; i < len; i++)
6385                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6386
6387         i = I915_READ(aud_cntrl_st2);
6388         i |= eldv;
6389         I915_WRITE(aud_cntrl_st2, i);
6390
6391 }
6392
6393 static void ironlake_write_eld(struct drm_connector *connector,
6394                                      struct drm_crtc *crtc)
6395 {
6396         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6397         uint8_t *eld = connector->eld;
6398         uint32_t eldv;
6399         uint32_t i;
6400         int len;
6401         int hdmiw_hdmiedid;
6402         int aud_config;
6403         int aud_cntl_st;
6404         int aud_cntrl_st2;
6405         int pipe = to_intel_crtc(crtc)->pipe;
6406
6407         if (HAS_PCH_IBX(connector->dev)) {
6408                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6409                 aud_config = IBX_AUD_CFG(pipe);
6410                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6411                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6412         } else {
6413                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6414                 aud_config = CPT_AUD_CFG(pipe);
6415                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6416                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6417         }
6418
6419         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6420
6421         i = I915_READ(aud_cntl_st);
6422         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6423         if (!i) {
6424                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6425                 /* operate blindly on all ports */
6426                 eldv = IBX_ELD_VALIDB;
6427                 eldv |= IBX_ELD_VALIDB << 4;
6428                 eldv |= IBX_ELD_VALIDB << 8;
6429         } else {
6430                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6431                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6432         }
6433
6434         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6435                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6436                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6437                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6438         } else
6439                 I915_WRITE(aud_config, 0);
6440
6441         if (intel_eld_uptodate(connector,
6442                                aud_cntrl_st2, eldv,
6443                                aud_cntl_st, IBX_ELD_ADDRESS,
6444                                hdmiw_hdmiedid))
6445                 return;
6446
6447         i = I915_READ(aud_cntrl_st2);
6448         i &= ~eldv;
6449         I915_WRITE(aud_cntrl_st2, i);
6450
6451         if (!eld[0])
6452                 return;
6453
6454         i = I915_READ(aud_cntl_st);
6455         i &= ~IBX_ELD_ADDRESS;
6456         I915_WRITE(aud_cntl_st, i);
6457
6458         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6459         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6460         for (i = 0; i < len; i++)
6461                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6462
6463         i = I915_READ(aud_cntrl_st2);
6464         i |= eldv;
6465         I915_WRITE(aud_cntrl_st2, i);
6466 }
6467
6468 void intel_write_eld(struct drm_encoder *encoder,
6469                      struct drm_display_mode *mode)
6470 {
6471         struct drm_crtc *crtc = encoder->crtc;
6472         struct drm_connector *connector;
6473         struct drm_device *dev = encoder->dev;
6474         struct drm_i915_private *dev_priv = dev->dev_private;
6475
6476         connector = drm_select_eld(encoder, mode);
6477         if (!connector)
6478                 return;
6479
6480         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6481                          connector->base.id,
6482                          drm_get_connector_name(connector),
6483                          connector->encoder->base.id,
6484                          drm_get_encoder_name(connector->encoder));
6485
6486         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6487
6488         if (dev_priv->display.write_eld)
6489                 dev_priv->display.write_eld(connector, crtc);
6490 }
6491
6492 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6493 void intel_crtc_load_lut(struct drm_crtc *crtc)
6494 {
6495         struct drm_device *dev = crtc->dev;
6496         struct drm_i915_private *dev_priv = dev->dev_private;
6497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6498         enum pipe pipe = intel_crtc->pipe;
6499         int palreg = PALETTE(pipe);
6500         int i;
6501         bool reenable_ips = false;
6502
6503         /* The clocks have to be on to load the palette. */
6504         if (!crtc->enabled || !intel_crtc->active)
6505                 return;
6506
6507         if (!HAS_PCH_SPLIT(dev_priv->dev))
6508                 assert_pll_enabled(dev_priv, pipe);
6509
6510         /* use legacy palette for Ironlake */
6511         if (HAS_PCH_SPLIT(dev))
6512                 palreg = LGC_PALETTE(pipe);
6513
6514         /* Workaround : Do not read or write the pipe palette/gamma data while
6515          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6516          */
6517         if (intel_crtc->config.ips_enabled &&
6518             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6519              GAMMA_MODE_MODE_SPLIT)) {
6520                 hsw_disable_ips(intel_crtc);
6521                 reenable_ips = true;
6522         }
6523
6524         for (i = 0; i < 256; i++) {
6525                 I915_WRITE(palreg + 4 * i,
6526                            (intel_crtc->lut_r[i] << 16) |
6527                            (intel_crtc->lut_g[i] << 8) |
6528                            intel_crtc->lut_b[i]);
6529         }
6530
6531         if (reenable_ips)
6532                 hsw_enable_ips(intel_crtc);
6533 }
6534
6535 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6536 {
6537         struct drm_device *dev = crtc->dev;
6538         struct drm_i915_private *dev_priv = dev->dev_private;
6539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6540         bool visible = base != 0;
6541         u32 cntl;
6542
6543         if (intel_crtc->cursor_visible == visible)
6544                 return;
6545
6546         cntl = I915_READ(_CURACNTR);
6547         if (visible) {
6548                 /* On these chipsets we can only modify the base whilst
6549                  * the cursor is disabled.
6550                  */
6551                 I915_WRITE(_CURABASE, base);
6552
6553                 cntl &= ~(CURSOR_FORMAT_MASK);
6554                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6555                 cntl |= CURSOR_ENABLE |
6556                         CURSOR_GAMMA_ENABLE |
6557                         CURSOR_FORMAT_ARGB;
6558         } else
6559                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6560         I915_WRITE(_CURACNTR, cntl);
6561
6562         intel_crtc->cursor_visible = visible;
6563 }
6564
6565 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6566 {
6567         struct drm_device *dev = crtc->dev;
6568         struct drm_i915_private *dev_priv = dev->dev_private;
6569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6570         int pipe = intel_crtc->pipe;
6571         bool visible = base != 0;
6572
6573         if (intel_crtc->cursor_visible != visible) {
6574                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6575                 if (base) {
6576                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6577                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6578                         cntl |= pipe << 28; /* Connect to correct pipe */
6579                 } else {
6580                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6581                         cntl |= CURSOR_MODE_DISABLE;
6582                 }
6583                 I915_WRITE(CURCNTR(pipe), cntl);
6584
6585                 intel_crtc->cursor_visible = visible;
6586         }
6587         /* and commit changes on next vblank */
6588         I915_WRITE(CURBASE(pipe), base);
6589 }
6590
6591 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6592 {
6593         struct drm_device *dev = crtc->dev;
6594         struct drm_i915_private *dev_priv = dev->dev_private;
6595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6596         int pipe = intel_crtc->pipe;
6597         bool visible = base != 0;
6598
6599         if (intel_crtc->cursor_visible != visible) {
6600                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6601                 if (base) {
6602                         cntl &= ~CURSOR_MODE;
6603                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6604                 } else {
6605                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6606                         cntl |= CURSOR_MODE_DISABLE;
6607                 }
6608                 if (IS_HASWELL(dev))
6609                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6610                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6611
6612                 intel_crtc->cursor_visible = visible;
6613         }
6614         /* and commit changes on next vblank */
6615         I915_WRITE(CURBASE_IVB(pipe), base);
6616 }
6617
6618 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6619 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6620                                      bool on)
6621 {
6622         struct drm_device *dev = crtc->dev;
6623         struct drm_i915_private *dev_priv = dev->dev_private;
6624         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6625         int pipe = intel_crtc->pipe;
6626         int x = intel_crtc->cursor_x;
6627         int y = intel_crtc->cursor_y;
6628         u32 base, pos;
6629         bool visible;
6630
6631         pos = 0;
6632
6633         if (on && crtc->enabled && crtc->fb) {
6634                 base = intel_crtc->cursor_addr;
6635                 if (x > (int) crtc->fb->width)
6636                         base = 0;
6637
6638                 if (y > (int) crtc->fb->height)
6639                         base = 0;
6640         } else
6641                 base = 0;
6642
6643         if (x < 0) {
6644                 if (x + intel_crtc->cursor_width < 0)
6645                         base = 0;
6646
6647                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6648                 x = -x;
6649         }
6650         pos |= x << CURSOR_X_SHIFT;
6651
6652         if (y < 0) {
6653                 if (y + intel_crtc->cursor_height < 0)
6654                         base = 0;
6655
6656                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6657                 y = -y;
6658         }
6659         pos |= y << CURSOR_Y_SHIFT;
6660
6661         visible = base != 0;
6662         if (!visible && !intel_crtc->cursor_visible)
6663                 return;
6664
6665         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6666                 I915_WRITE(CURPOS_IVB(pipe), pos);
6667                 ivb_update_cursor(crtc, base);
6668         } else {
6669                 I915_WRITE(CURPOS(pipe), pos);
6670                 if (IS_845G(dev) || IS_I865G(dev))
6671                         i845_update_cursor(crtc, base);
6672                 else
6673                         i9xx_update_cursor(crtc, base);
6674         }
6675 }
6676
6677 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6678                                  struct drm_file *file,
6679                                  uint32_t handle,
6680                                  uint32_t width, uint32_t height)
6681 {
6682         struct drm_device *dev = crtc->dev;
6683         struct drm_i915_private *dev_priv = dev->dev_private;
6684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6685         struct drm_i915_gem_object *obj;
6686         uint32_t addr;
6687         int ret;
6688
6689         /* if we want to turn off the cursor ignore width and height */
6690         if (!handle) {
6691                 DRM_DEBUG_KMS("cursor off\n");
6692                 addr = 0;
6693                 obj = NULL;
6694                 mutex_lock(&dev->struct_mutex);
6695                 goto finish;
6696         }
6697
6698         /* Currently we only support 64x64 cursors */
6699         if (width != 64 || height != 64) {
6700                 DRM_ERROR("we currently only support 64x64 cursors\n");
6701                 return -EINVAL;
6702         }
6703
6704         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6705         if (&obj->base == NULL)
6706                 return -ENOENT;
6707
6708         if (obj->base.size < width * height * 4) {
6709                 DRM_ERROR("buffer is to small\n");
6710                 ret = -ENOMEM;
6711                 goto fail;
6712         }
6713
6714         /* we only need to pin inside GTT if cursor is non-phy */
6715         mutex_lock(&dev->struct_mutex);
6716         if (!dev_priv->info->cursor_needs_physical) {
6717                 unsigned alignment;
6718
6719                 if (obj->tiling_mode) {
6720                         DRM_ERROR("cursor cannot be tiled\n");
6721                         ret = -EINVAL;
6722                         goto fail_locked;
6723                 }
6724
6725                 /* Note that the w/a also requires 2 PTE of padding following
6726                  * the bo. We currently fill all unused PTE with the shadow
6727                  * page and so we should always have valid PTE following the
6728                  * cursor preventing the VT-d warning.
6729                  */
6730                 alignment = 0;
6731                 if (need_vtd_wa(dev))
6732                         alignment = 64*1024;
6733
6734                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6735                 if (ret) {
6736                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6737                         goto fail_locked;
6738                 }
6739
6740                 ret = i915_gem_object_put_fence(obj);
6741                 if (ret) {
6742                         DRM_ERROR("failed to release fence for cursor");
6743                         goto fail_unpin;
6744                 }
6745
6746                 addr = i915_gem_obj_ggtt_offset(obj);
6747         } else {
6748                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6749                 ret = i915_gem_attach_phys_object(dev, obj,
6750                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6751                                                   align);
6752                 if (ret) {
6753                         DRM_ERROR("failed to attach phys object\n");
6754                         goto fail_locked;
6755                 }
6756                 addr = obj->phys_obj->handle->busaddr;
6757         }
6758
6759         if (IS_GEN2(dev))
6760                 I915_WRITE(CURSIZE, (height << 12) | width);
6761
6762  finish:
6763         if (intel_crtc->cursor_bo) {
6764                 if (dev_priv->info->cursor_needs_physical) {
6765                         if (intel_crtc->cursor_bo != obj)
6766                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6767                 } else
6768                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6769                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6770         }
6771
6772         mutex_unlock(&dev->struct_mutex);
6773
6774         intel_crtc->cursor_addr = addr;
6775         intel_crtc->cursor_bo = obj;
6776         intel_crtc->cursor_width = width;
6777         intel_crtc->cursor_height = height;
6778
6779         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6780
6781         return 0;
6782 fail_unpin:
6783         i915_gem_object_unpin(obj);
6784 fail_locked:
6785         mutex_unlock(&dev->struct_mutex);
6786 fail:
6787         drm_gem_object_unreference_unlocked(&obj->base);
6788         return ret;
6789 }
6790
6791 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6792 {
6793         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6794
6795         intel_crtc->cursor_x = x;
6796         intel_crtc->cursor_y = y;
6797
6798         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6799
6800         return 0;
6801 }
6802
6803 /** Sets the color ramps on behalf of RandR */
6804 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6805                                  u16 blue, int regno)
6806 {
6807         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6808
6809         intel_crtc->lut_r[regno] = red >> 8;
6810         intel_crtc->lut_g[regno] = green >> 8;
6811         intel_crtc->lut_b[regno] = blue >> 8;
6812 }
6813
6814 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6815                              u16 *blue, int regno)
6816 {
6817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6818
6819         *red = intel_crtc->lut_r[regno] << 8;
6820         *green = intel_crtc->lut_g[regno] << 8;
6821         *blue = intel_crtc->lut_b[regno] << 8;
6822 }
6823
6824 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6825                                  u16 *blue, uint32_t start, uint32_t size)
6826 {
6827         int end = (start + size > 256) ? 256 : start + size, i;
6828         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6829
6830         for (i = start; i < end; i++) {
6831                 intel_crtc->lut_r[i] = red[i] >> 8;
6832                 intel_crtc->lut_g[i] = green[i] >> 8;
6833                 intel_crtc->lut_b[i] = blue[i] >> 8;
6834         }
6835
6836         intel_crtc_load_lut(crtc);
6837 }
6838
6839 /* VESA 640x480x72Hz mode to set on the pipe */
6840 static struct drm_display_mode load_detect_mode = {
6841         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6842                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6843 };
6844
6845 static struct drm_framebuffer *
6846 intel_framebuffer_create(struct drm_device *dev,
6847                          struct drm_mode_fb_cmd2 *mode_cmd,
6848                          struct drm_i915_gem_object *obj)
6849 {
6850         struct intel_framebuffer *intel_fb;
6851         int ret;
6852
6853         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6854         if (!intel_fb) {
6855                 drm_gem_object_unreference_unlocked(&obj->base);
6856                 return ERR_PTR(-ENOMEM);
6857         }
6858
6859         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6860         if (ret) {
6861                 drm_gem_object_unreference_unlocked(&obj->base);
6862                 kfree(intel_fb);
6863                 return ERR_PTR(ret);
6864         }
6865
6866         return &intel_fb->base;
6867 }
6868
6869 static u32
6870 intel_framebuffer_pitch_for_width(int width, int bpp)
6871 {
6872         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6873         return ALIGN(pitch, 64);
6874 }
6875
6876 static u32
6877 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6878 {
6879         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6880         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6881 }
6882
6883 static struct drm_framebuffer *
6884 intel_framebuffer_create_for_mode(struct drm_device *dev,
6885                                   struct drm_display_mode *mode,
6886                                   int depth, int bpp)
6887 {
6888         struct drm_i915_gem_object *obj;
6889         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6890
6891         obj = i915_gem_alloc_object(dev,
6892                                     intel_framebuffer_size_for_mode(mode, bpp));
6893         if (obj == NULL)
6894                 return ERR_PTR(-ENOMEM);
6895
6896         mode_cmd.width = mode->hdisplay;
6897         mode_cmd.height = mode->vdisplay;
6898         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6899                                                                 bpp);
6900         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6901
6902         return intel_framebuffer_create(dev, &mode_cmd, obj);
6903 }
6904
6905 static struct drm_framebuffer *
6906 mode_fits_in_fbdev(struct drm_device *dev,
6907                    struct drm_display_mode *mode)
6908 {
6909         struct drm_i915_private *dev_priv = dev->dev_private;
6910         struct drm_i915_gem_object *obj;
6911         struct drm_framebuffer *fb;
6912
6913         if (dev_priv->fbdev == NULL)
6914                 return NULL;
6915
6916         obj = dev_priv->fbdev->ifb.obj;
6917         if (obj == NULL)
6918                 return NULL;
6919
6920         fb = &dev_priv->fbdev->ifb.base;
6921         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6922                                                                fb->bits_per_pixel))
6923                 return NULL;
6924
6925         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6926                 return NULL;
6927
6928         return fb;
6929 }
6930
6931 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6932                                 struct drm_display_mode *mode,
6933                                 struct intel_load_detect_pipe *old)
6934 {
6935         struct intel_crtc *intel_crtc;
6936         struct intel_encoder *intel_encoder =
6937                 intel_attached_encoder(connector);
6938         struct drm_crtc *possible_crtc;
6939         struct drm_encoder *encoder = &intel_encoder->base;
6940         struct drm_crtc *crtc = NULL;
6941         struct drm_device *dev = encoder->dev;
6942         struct drm_framebuffer *fb;
6943         int i = -1;
6944
6945         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6946                       connector->base.id, drm_get_connector_name(connector),
6947                       encoder->base.id, drm_get_encoder_name(encoder));
6948
6949         /*
6950          * Algorithm gets a little messy:
6951          *
6952          *   - if the connector already has an assigned crtc, use it (but make
6953          *     sure it's on first)
6954          *
6955          *   - try to find the first unused crtc that can drive this connector,
6956          *     and use that if we find one
6957          */
6958
6959         /* See if we already have a CRTC for this connector */
6960         if (encoder->crtc) {
6961                 crtc = encoder->crtc;
6962
6963                 mutex_lock(&crtc->mutex);
6964
6965                 old->dpms_mode = connector->dpms;
6966                 old->load_detect_temp = false;
6967
6968                 /* Make sure the crtc and connector are running */
6969                 if (connector->dpms != DRM_MODE_DPMS_ON)
6970                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6971
6972                 return true;
6973         }
6974
6975         /* Find an unused one (if possible) */
6976         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6977                 i++;
6978                 if (!(encoder->possible_crtcs & (1 << i)))
6979                         continue;
6980                 if (!possible_crtc->enabled) {
6981                         crtc = possible_crtc;
6982                         break;
6983                 }
6984         }
6985
6986         /*
6987          * If we didn't find an unused CRTC, don't use any.
6988          */
6989         if (!crtc) {
6990                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6991                 return false;
6992         }
6993
6994         mutex_lock(&crtc->mutex);
6995         intel_encoder->new_crtc = to_intel_crtc(crtc);
6996         to_intel_connector(connector)->new_encoder = intel_encoder;
6997
6998         intel_crtc = to_intel_crtc(crtc);
6999         old->dpms_mode = connector->dpms;
7000         old->load_detect_temp = true;
7001         old->release_fb = NULL;
7002
7003         if (!mode)
7004                 mode = &load_detect_mode;
7005
7006         /* We need a framebuffer large enough to accommodate all accesses
7007          * that the plane may generate whilst we perform load detection.
7008          * We can not rely on the fbcon either being present (we get called
7009          * during its initialisation to detect all boot displays, or it may
7010          * not even exist) or that it is large enough to satisfy the
7011          * requested mode.
7012          */
7013         fb = mode_fits_in_fbdev(dev, mode);
7014         if (fb == NULL) {
7015                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7016                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7017                 old->release_fb = fb;
7018         } else
7019                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7020         if (IS_ERR(fb)) {
7021                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7022                 mutex_unlock(&crtc->mutex);
7023                 return false;
7024         }
7025
7026         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7027                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7028                 if (old->release_fb)
7029                         old->release_fb->funcs->destroy(old->release_fb);
7030                 mutex_unlock(&crtc->mutex);
7031                 return false;
7032         }
7033
7034         /* let the connector get through one full cycle before testing */
7035         intel_wait_for_vblank(dev, intel_crtc->pipe);
7036         return true;
7037 }
7038
7039 void intel_release_load_detect_pipe(struct drm_connector *connector,
7040                                     struct intel_load_detect_pipe *old)
7041 {
7042         struct intel_encoder *intel_encoder =
7043                 intel_attached_encoder(connector);
7044         struct drm_encoder *encoder = &intel_encoder->base;
7045         struct drm_crtc *crtc = encoder->crtc;
7046
7047         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7048                       connector->base.id, drm_get_connector_name(connector),
7049                       encoder->base.id, drm_get_encoder_name(encoder));
7050
7051         if (old->load_detect_temp) {
7052                 to_intel_connector(connector)->new_encoder = NULL;
7053                 intel_encoder->new_crtc = NULL;
7054                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7055
7056                 if (old->release_fb) {
7057                         drm_framebuffer_unregister_private(old->release_fb);
7058                         drm_framebuffer_unreference(old->release_fb);
7059                 }
7060
7061                 mutex_unlock(&crtc->mutex);
7062                 return;
7063         }
7064
7065         /* Switch crtc and encoder back off if necessary */
7066         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7067                 connector->funcs->dpms(connector, old->dpms_mode);
7068
7069         mutex_unlock(&crtc->mutex);
7070 }
7071
7072 /* Returns the clock of the currently programmed mode of the given pipe. */
7073 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7074                                 struct intel_crtc_config *pipe_config)
7075 {
7076         struct drm_device *dev = crtc->base.dev;
7077         struct drm_i915_private *dev_priv = dev->dev_private;
7078         int pipe = pipe_config->cpu_transcoder;
7079         u32 dpll = I915_READ(DPLL(pipe));
7080         u32 fp;
7081         intel_clock_t clock;
7082
7083         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7084                 fp = I915_READ(FP0(pipe));
7085         else
7086                 fp = I915_READ(FP1(pipe));
7087
7088         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7089         if (IS_PINEVIEW(dev)) {
7090                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7091                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7092         } else {
7093                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7094                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7095         }
7096
7097         if (!IS_GEN2(dev)) {
7098                 if (IS_PINEVIEW(dev))
7099                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7100                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7101                 else
7102                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7103                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7104
7105                 switch (dpll & DPLL_MODE_MASK) {
7106                 case DPLLB_MODE_DAC_SERIAL:
7107                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7108                                 5 : 10;
7109                         break;
7110                 case DPLLB_MODE_LVDS:
7111                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7112                                 7 : 14;
7113                         break;
7114                 default:
7115                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7116                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7117                         pipe_config->adjusted_mode.clock = 0;
7118                         return;
7119                 }
7120
7121                 if (IS_PINEVIEW(dev))
7122                         pineview_clock(96000, &clock);
7123                 else
7124                         i9xx_clock(96000, &clock);
7125         } else {
7126                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7127
7128                 if (is_lvds) {
7129                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7130                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7131                         clock.p2 = 14;
7132
7133                         if ((dpll & PLL_REF_INPUT_MASK) ==
7134                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7135                                 /* XXX: might not be 66MHz */
7136                                 i9xx_clock(66000, &clock);
7137                         } else
7138                                 i9xx_clock(48000, &clock);
7139                 } else {
7140                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7141                                 clock.p1 = 2;
7142                         else {
7143                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7144                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7145                         }
7146                         if (dpll & PLL_P2_DIVIDE_BY_4)
7147                                 clock.p2 = 4;
7148                         else
7149                                 clock.p2 = 2;
7150
7151                         i9xx_clock(48000, &clock);
7152                 }
7153         }
7154
7155         pipe_config->adjusted_mode.clock = clock.dot *
7156                 pipe_config->pixel_multiplier;
7157 }
7158
7159 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7160                                     struct intel_crtc_config *pipe_config)
7161 {
7162         struct drm_device *dev = crtc->base.dev;
7163         struct drm_i915_private *dev_priv = dev->dev_private;
7164         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7165         int link_freq, repeat;
7166         u64 clock;
7167         u32 link_m, link_n;
7168
7169         repeat = pipe_config->pixel_multiplier;
7170
7171         /*
7172          * The calculation for the data clock is:
7173          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7174          * But we want to avoid losing precison if possible, so:
7175          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7176          *
7177          * and the link clock is simpler:
7178          * link_clock = (m * link_clock * repeat) / n
7179          */
7180
7181         /*
7182          * We need to get the FDI or DP link clock here to derive
7183          * the M/N dividers.
7184          *
7185          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7186          * For DP, it's either 1.62GHz or 2.7GHz.
7187          * We do our calculations in 10*MHz since we don't need much precison.
7188          */
7189         if (pipe_config->has_pch_encoder)
7190                 link_freq = intel_fdi_link_freq(dev) * 10000;
7191         else
7192                 link_freq = pipe_config->port_clock;
7193
7194         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7195         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7196
7197         if (!link_m || !link_n)
7198                 return;
7199
7200         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7201         do_div(clock, link_n);
7202
7203         pipe_config->adjusted_mode.clock = clock;
7204 }
7205
7206 /** Returns the currently programmed mode of the given pipe. */
7207 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7208                                              struct drm_crtc *crtc)
7209 {
7210         struct drm_i915_private *dev_priv = dev->dev_private;
7211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7212         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7213         struct drm_display_mode *mode;
7214         struct intel_crtc_config pipe_config;
7215         int htot = I915_READ(HTOTAL(cpu_transcoder));
7216         int hsync = I915_READ(HSYNC(cpu_transcoder));
7217         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7218         int vsync = I915_READ(VSYNC(cpu_transcoder));
7219
7220         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7221         if (!mode)
7222                 return NULL;
7223
7224         /*
7225          * Construct a pipe_config sufficient for getting the clock info
7226          * back out of crtc_clock_get.
7227          *
7228          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7229          * to use a real value here instead.
7230          */
7231         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7232         pipe_config.pixel_multiplier = 1;
7233         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7234
7235         mode->clock = pipe_config.adjusted_mode.clock;
7236         mode->hdisplay = (htot & 0xffff) + 1;
7237         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7238         mode->hsync_start = (hsync & 0xffff) + 1;
7239         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7240         mode->vdisplay = (vtot & 0xffff) + 1;
7241         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7242         mode->vsync_start = (vsync & 0xffff) + 1;
7243         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7244
7245         drm_mode_set_name(mode);
7246
7247         return mode;
7248 }
7249
7250 static void intel_increase_pllclock(struct drm_crtc *crtc)
7251 {
7252         struct drm_device *dev = crtc->dev;
7253         drm_i915_private_t *dev_priv = dev->dev_private;
7254         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7255         int pipe = intel_crtc->pipe;
7256         int dpll_reg = DPLL(pipe);
7257         int dpll;
7258
7259         if (HAS_PCH_SPLIT(dev))
7260                 return;
7261
7262         if (!dev_priv->lvds_downclock_avail)
7263                 return;
7264
7265         dpll = I915_READ(dpll_reg);
7266         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7267                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7268
7269                 assert_panel_unlocked(dev_priv, pipe);
7270
7271                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7272                 I915_WRITE(dpll_reg, dpll);
7273                 intel_wait_for_vblank(dev, pipe);
7274
7275                 dpll = I915_READ(dpll_reg);
7276                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7277                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7278         }
7279 }
7280
7281 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7282 {
7283         struct drm_device *dev = crtc->dev;
7284         drm_i915_private_t *dev_priv = dev->dev_private;
7285         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7286
7287         if (HAS_PCH_SPLIT(dev))
7288                 return;
7289
7290         if (!dev_priv->lvds_downclock_avail)
7291                 return;
7292
7293         /*
7294          * Since this is called by a timer, we should never get here in
7295          * the manual case.
7296          */
7297         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7298                 int pipe = intel_crtc->pipe;
7299                 int dpll_reg = DPLL(pipe);
7300                 int dpll;
7301
7302                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7303
7304                 assert_panel_unlocked(dev_priv, pipe);
7305
7306                 dpll = I915_READ(dpll_reg);
7307                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7308                 I915_WRITE(dpll_reg, dpll);
7309                 intel_wait_for_vblank(dev, pipe);
7310                 dpll = I915_READ(dpll_reg);
7311                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7312                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7313         }
7314
7315 }
7316
7317 void intel_mark_busy(struct drm_device *dev)
7318 {
7319         i915_update_gfx_val(dev->dev_private);
7320 }
7321
7322 void intel_mark_idle(struct drm_device *dev)
7323 {
7324         struct drm_crtc *crtc;
7325
7326         if (!i915_powersave)
7327                 return;
7328
7329         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7330                 if (!crtc->fb)
7331                         continue;
7332
7333                 intel_decrease_pllclock(crtc);
7334         }
7335 }
7336
7337 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7338                         struct intel_ring_buffer *ring)
7339 {
7340         struct drm_device *dev = obj->base.dev;
7341         struct drm_crtc *crtc;
7342
7343         if (!i915_powersave)
7344                 return;
7345
7346         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7347                 if (!crtc->fb)
7348                         continue;
7349
7350                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7351                         continue;
7352
7353                 intel_increase_pllclock(crtc);
7354                 if (ring && intel_fbc_enabled(dev))
7355                         ring->fbc_dirty = true;
7356         }
7357 }
7358
7359 static void intel_crtc_destroy(struct drm_crtc *crtc)
7360 {
7361         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7362         struct drm_device *dev = crtc->dev;
7363         struct intel_unpin_work *work;
7364         unsigned long flags;
7365
7366         spin_lock_irqsave(&dev->event_lock, flags);
7367         work = intel_crtc->unpin_work;
7368         intel_crtc->unpin_work = NULL;
7369         spin_unlock_irqrestore(&dev->event_lock, flags);
7370
7371         if (work) {
7372                 cancel_work_sync(&work->work);
7373                 kfree(work);
7374         }
7375
7376         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7377
7378         drm_crtc_cleanup(crtc);
7379
7380         kfree(intel_crtc);
7381 }
7382
7383 static void intel_unpin_work_fn(struct work_struct *__work)
7384 {
7385         struct intel_unpin_work *work =
7386                 container_of(__work, struct intel_unpin_work, work);
7387         struct drm_device *dev = work->crtc->dev;
7388
7389         mutex_lock(&dev->struct_mutex);
7390         intel_unpin_fb_obj(work->old_fb_obj);
7391         drm_gem_object_unreference(&work->pending_flip_obj->base);
7392         drm_gem_object_unreference(&work->old_fb_obj->base);
7393
7394         intel_update_fbc(dev);
7395         mutex_unlock(&dev->struct_mutex);
7396
7397         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7398         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7399
7400         kfree(work);
7401 }
7402
7403 static void do_intel_finish_page_flip(struct drm_device *dev,
7404                                       struct drm_crtc *crtc)
7405 {
7406         drm_i915_private_t *dev_priv = dev->dev_private;
7407         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7408         struct intel_unpin_work *work;
7409         unsigned long flags;
7410
7411         /* Ignore early vblank irqs */
7412         if (intel_crtc == NULL)
7413                 return;
7414
7415         spin_lock_irqsave(&dev->event_lock, flags);
7416         work = intel_crtc->unpin_work;
7417
7418         /* Ensure we don't miss a work->pending update ... */
7419         smp_rmb();
7420
7421         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7422                 spin_unlock_irqrestore(&dev->event_lock, flags);
7423                 return;
7424         }
7425
7426         /* and that the unpin work is consistent wrt ->pending. */
7427         smp_rmb();
7428
7429         intel_crtc->unpin_work = NULL;
7430
7431         if (work->event)
7432                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7433
7434         drm_vblank_put(dev, intel_crtc->pipe);
7435
7436         spin_unlock_irqrestore(&dev->event_lock, flags);
7437
7438         wake_up_all(&dev_priv->pending_flip_queue);
7439
7440         queue_work(dev_priv->wq, &work->work);
7441
7442         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7443 }
7444
7445 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7446 {
7447         drm_i915_private_t *dev_priv = dev->dev_private;
7448         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7449
7450         do_intel_finish_page_flip(dev, crtc);
7451 }
7452
7453 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7454 {
7455         drm_i915_private_t *dev_priv = dev->dev_private;
7456         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7457
7458         do_intel_finish_page_flip(dev, crtc);
7459 }
7460
7461 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7462 {
7463         drm_i915_private_t *dev_priv = dev->dev_private;
7464         struct intel_crtc *intel_crtc =
7465                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7466         unsigned long flags;
7467
7468         /* NB: An MMIO update of the plane base pointer will also
7469          * generate a page-flip completion irq, i.e. every modeset
7470          * is also accompanied by a spurious intel_prepare_page_flip().
7471          */
7472         spin_lock_irqsave(&dev->event_lock, flags);
7473         if (intel_crtc->unpin_work)
7474                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7475         spin_unlock_irqrestore(&dev->event_lock, flags);
7476 }
7477
7478 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7479 {
7480         /* Ensure that the work item is consistent when activating it ... */
7481         smp_wmb();
7482         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7483         /* and that it is marked active as soon as the irq could fire. */
7484         smp_wmb();
7485 }
7486
7487 static int intel_gen2_queue_flip(struct drm_device *dev,
7488                                  struct drm_crtc *crtc,
7489                                  struct drm_framebuffer *fb,
7490                                  struct drm_i915_gem_object *obj)
7491 {
7492         struct drm_i915_private *dev_priv = dev->dev_private;
7493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7494         u32 flip_mask;
7495         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7496         int ret;
7497
7498         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7499         if (ret)
7500                 goto err;
7501
7502         ret = intel_ring_begin(ring, 6);
7503         if (ret)
7504                 goto err_unpin;
7505
7506         /* Can't queue multiple flips, so wait for the previous
7507          * one to finish before executing the next.
7508          */
7509         if (intel_crtc->plane)
7510                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7511         else
7512                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7513         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7514         intel_ring_emit(ring, MI_NOOP);
7515         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7516                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7517         intel_ring_emit(ring, fb->pitches[0]);
7518         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7519         intel_ring_emit(ring, 0); /* aux display base address, unused */
7520
7521         intel_mark_page_flip_active(intel_crtc);
7522         intel_ring_advance(ring);
7523         return 0;
7524
7525 err_unpin:
7526         intel_unpin_fb_obj(obj);
7527 err:
7528         return ret;
7529 }
7530
7531 static int intel_gen3_queue_flip(struct drm_device *dev,
7532                                  struct drm_crtc *crtc,
7533                                  struct drm_framebuffer *fb,
7534                                  struct drm_i915_gem_object *obj)
7535 {
7536         struct drm_i915_private *dev_priv = dev->dev_private;
7537         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7538         u32 flip_mask;
7539         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7540         int ret;
7541
7542         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7543         if (ret)
7544                 goto err;
7545
7546         ret = intel_ring_begin(ring, 6);
7547         if (ret)
7548                 goto err_unpin;
7549
7550         if (intel_crtc->plane)
7551                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7552         else
7553                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7554         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7555         intel_ring_emit(ring, MI_NOOP);
7556         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7557                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7558         intel_ring_emit(ring, fb->pitches[0]);
7559         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7560         intel_ring_emit(ring, MI_NOOP);
7561
7562         intel_mark_page_flip_active(intel_crtc);
7563         intel_ring_advance(ring);
7564         return 0;
7565
7566 err_unpin:
7567         intel_unpin_fb_obj(obj);
7568 err:
7569         return ret;
7570 }
7571
7572 static int intel_gen4_queue_flip(struct drm_device *dev,
7573                                  struct drm_crtc *crtc,
7574                                  struct drm_framebuffer *fb,
7575                                  struct drm_i915_gem_object *obj)
7576 {
7577         struct drm_i915_private *dev_priv = dev->dev_private;
7578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7579         uint32_t pf, pipesrc;
7580         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7581         int ret;
7582
7583         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7584         if (ret)
7585                 goto err;
7586
7587         ret = intel_ring_begin(ring, 4);
7588         if (ret)
7589                 goto err_unpin;
7590
7591         /* i965+ uses the linear or tiled offsets from the
7592          * Display Registers (which do not change across a page-flip)
7593          * so we need only reprogram the base address.
7594          */
7595         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7596                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7597         intel_ring_emit(ring, fb->pitches[0]);
7598         intel_ring_emit(ring,
7599                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7600                         obj->tiling_mode);
7601
7602         /* XXX Enabling the panel-fitter across page-flip is so far
7603          * untested on non-native modes, so ignore it for now.
7604          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7605          */
7606         pf = 0;
7607         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7608         intel_ring_emit(ring, pf | pipesrc);
7609
7610         intel_mark_page_flip_active(intel_crtc);
7611         intel_ring_advance(ring);
7612         return 0;
7613
7614 err_unpin:
7615         intel_unpin_fb_obj(obj);
7616 err:
7617         return ret;
7618 }
7619
7620 static int intel_gen6_queue_flip(struct drm_device *dev,
7621                                  struct drm_crtc *crtc,
7622                                  struct drm_framebuffer *fb,
7623                                  struct drm_i915_gem_object *obj)
7624 {
7625         struct drm_i915_private *dev_priv = dev->dev_private;
7626         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7627         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7628         uint32_t pf, pipesrc;
7629         int ret;
7630
7631         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7632         if (ret)
7633                 goto err;
7634
7635         ret = intel_ring_begin(ring, 4);
7636         if (ret)
7637                 goto err_unpin;
7638
7639         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7640                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7641         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7642         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7643
7644         /* Contrary to the suggestions in the documentation,
7645          * "Enable Panel Fitter" does not seem to be required when page
7646          * flipping with a non-native mode, and worse causes a normal
7647          * modeset to fail.
7648          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7649          */
7650         pf = 0;
7651         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7652         intel_ring_emit(ring, pf | pipesrc);
7653
7654         intel_mark_page_flip_active(intel_crtc);
7655         intel_ring_advance(ring);
7656         return 0;
7657
7658 err_unpin:
7659         intel_unpin_fb_obj(obj);
7660 err:
7661         return ret;
7662 }
7663
7664 /*
7665  * On gen7 we currently use the blit ring because (in early silicon at least)
7666  * the render ring doesn't give us interrpts for page flip completion, which
7667  * means clients will hang after the first flip is queued.  Fortunately the
7668  * blit ring generates interrupts properly, so use it instead.
7669  */
7670 static int intel_gen7_queue_flip(struct drm_device *dev,
7671                                  struct drm_crtc *crtc,
7672                                  struct drm_framebuffer *fb,
7673                                  struct drm_i915_gem_object *obj)
7674 {
7675         struct drm_i915_private *dev_priv = dev->dev_private;
7676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7677         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7678         uint32_t plane_bit = 0;
7679         int ret;
7680
7681         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7682         if (ret)
7683                 goto err;
7684
7685         switch(intel_crtc->plane) {
7686         case PLANE_A:
7687                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7688                 break;
7689         case PLANE_B:
7690                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7691                 break;
7692         case PLANE_C:
7693                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7694                 break;
7695         default:
7696                 WARN_ONCE(1, "unknown plane in flip command\n");
7697                 ret = -ENODEV;
7698                 goto err_unpin;
7699         }
7700
7701         ret = intel_ring_begin(ring, 4);
7702         if (ret)
7703                 goto err_unpin;
7704
7705         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7706         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7707         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7708         intel_ring_emit(ring, (MI_NOOP));
7709
7710         intel_mark_page_flip_active(intel_crtc);
7711         intel_ring_advance(ring);
7712         return 0;
7713
7714 err_unpin:
7715         intel_unpin_fb_obj(obj);
7716 err:
7717         return ret;
7718 }
7719
7720 static int intel_default_queue_flip(struct drm_device *dev,
7721                                     struct drm_crtc *crtc,
7722                                     struct drm_framebuffer *fb,
7723                                     struct drm_i915_gem_object *obj)
7724 {
7725         return -ENODEV;
7726 }
7727
7728 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7729                                 struct drm_framebuffer *fb,
7730                                 struct drm_pending_vblank_event *event)
7731 {
7732         struct drm_device *dev = crtc->dev;
7733         struct drm_i915_private *dev_priv = dev->dev_private;
7734         struct drm_framebuffer *old_fb = crtc->fb;
7735         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7737         struct intel_unpin_work *work;
7738         unsigned long flags;
7739         int ret;
7740
7741         /* Can't change pixel format via MI display flips. */
7742         if (fb->pixel_format != crtc->fb->pixel_format)
7743                 return -EINVAL;
7744
7745         /*
7746          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7747          * Note that pitch changes could also affect these register.
7748          */
7749         if (INTEL_INFO(dev)->gen > 3 &&
7750             (fb->offsets[0] != crtc->fb->offsets[0] ||
7751              fb->pitches[0] != crtc->fb->pitches[0]))
7752                 return -EINVAL;
7753
7754         work = kzalloc(sizeof *work, GFP_KERNEL);
7755         if (work == NULL)
7756                 return -ENOMEM;
7757
7758         work->event = event;
7759         work->crtc = crtc;
7760         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7761         INIT_WORK(&work->work, intel_unpin_work_fn);
7762
7763         ret = drm_vblank_get(dev, intel_crtc->pipe);
7764         if (ret)
7765                 goto free_work;
7766
7767         /* We borrow the event spin lock for protecting unpin_work */
7768         spin_lock_irqsave(&dev->event_lock, flags);
7769         if (intel_crtc->unpin_work) {
7770                 spin_unlock_irqrestore(&dev->event_lock, flags);
7771                 kfree(work);
7772                 drm_vblank_put(dev, intel_crtc->pipe);
7773
7774                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7775                 return -EBUSY;
7776         }
7777         intel_crtc->unpin_work = work;
7778         spin_unlock_irqrestore(&dev->event_lock, flags);
7779
7780         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7781                 flush_workqueue(dev_priv->wq);
7782
7783         ret = i915_mutex_lock_interruptible(dev);
7784         if (ret)
7785                 goto cleanup;
7786
7787         /* Reference the objects for the scheduled work. */
7788         drm_gem_object_reference(&work->old_fb_obj->base);
7789         drm_gem_object_reference(&obj->base);
7790
7791         crtc->fb = fb;
7792
7793         work->pending_flip_obj = obj;
7794
7795         work->enable_stall_check = true;
7796
7797         atomic_inc(&intel_crtc->unpin_work_count);
7798         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7799
7800         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7801         if (ret)
7802                 goto cleanup_pending;
7803
7804         intel_disable_fbc(dev);
7805         intel_mark_fb_busy(obj, NULL);
7806         mutex_unlock(&dev->struct_mutex);
7807
7808         trace_i915_flip_request(intel_crtc->plane, obj);
7809
7810         return 0;
7811
7812 cleanup_pending:
7813         atomic_dec(&intel_crtc->unpin_work_count);
7814         crtc->fb = old_fb;
7815         drm_gem_object_unreference(&work->old_fb_obj->base);
7816         drm_gem_object_unreference(&obj->base);
7817         mutex_unlock(&dev->struct_mutex);
7818
7819 cleanup:
7820         spin_lock_irqsave(&dev->event_lock, flags);
7821         intel_crtc->unpin_work = NULL;
7822         spin_unlock_irqrestore(&dev->event_lock, flags);
7823
7824         drm_vblank_put(dev, intel_crtc->pipe);
7825 free_work:
7826         kfree(work);
7827
7828         return ret;
7829 }
7830
7831 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7832         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7833         .load_lut = intel_crtc_load_lut,
7834 };
7835
7836 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7837                                   struct drm_crtc *crtc)
7838 {
7839         struct drm_device *dev;
7840         struct drm_crtc *tmp;
7841         int crtc_mask = 1;
7842
7843         WARN(!crtc, "checking null crtc?\n");
7844
7845         dev = crtc->dev;
7846
7847         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7848                 if (tmp == crtc)
7849                         break;
7850                 crtc_mask <<= 1;
7851         }
7852
7853         if (encoder->possible_crtcs & crtc_mask)
7854                 return true;
7855         return false;
7856 }
7857
7858 /**
7859  * intel_modeset_update_staged_output_state
7860  *
7861  * Updates the staged output configuration state, e.g. after we've read out the
7862  * current hw state.
7863  */
7864 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7865 {
7866         struct intel_encoder *encoder;
7867         struct intel_connector *connector;
7868
7869         list_for_each_entry(connector, &dev->mode_config.connector_list,
7870                             base.head) {
7871                 connector->new_encoder =
7872                         to_intel_encoder(connector->base.encoder);
7873         }
7874
7875         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7876                             base.head) {
7877                 encoder->new_crtc =
7878                         to_intel_crtc(encoder->base.crtc);
7879         }
7880 }
7881
7882 /**
7883  * intel_modeset_commit_output_state
7884  *
7885  * This function copies the stage display pipe configuration to the real one.
7886  */
7887 static void intel_modeset_commit_output_state(struct drm_device *dev)
7888 {
7889         struct intel_encoder *encoder;
7890         struct intel_connector *connector;
7891
7892         list_for_each_entry(connector, &dev->mode_config.connector_list,
7893                             base.head) {
7894                 connector->base.encoder = &connector->new_encoder->base;
7895         }
7896
7897         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7898                             base.head) {
7899                 encoder->base.crtc = &encoder->new_crtc->base;
7900         }
7901 }
7902
7903 static void
7904 connected_sink_compute_bpp(struct intel_connector * connector,
7905                            struct intel_crtc_config *pipe_config)
7906 {
7907         int bpp = pipe_config->pipe_bpp;
7908
7909         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7910                 connector->base.base.id,
7911                 drm_get_connector_name(&connector->base));
7912
7913         /* Don't use an invalid EDID bpc value */
7914         if (connector->base.display_info.bpc &&
7915             connector->base.display_info.bpc * 3 < bpp) {
7916                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7917                               bpp, connector->base.display_info.bpc*3);
7918                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7919         }
7920
7921         /* Clamp bpp to 8 on screens without EDID 1.4 */
7922         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7923                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7924                               bpp);
7925                 pipe_config->pipe_bpp = 24;
7926         }
7927 }
7928
7929 static int
7930 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7931                           struct drm_framebuffer *fb,
7932                           struct intel_crtc_config *pipe_config)
7933 {
7934         struct drm_device *dev = crtc->base.dev;
7935         struct intel_connector *connector;
7936         int bpp;
7937
7938         switch (fb->pixel_format) {
7939         case DRM_FORMAT_C8:
7940                 bpp = 8*3; /* since we go through a colormap */
7941                 break;
7942         case DRM_FORMAT_XRGB1555:
7943         case DRM_FORMAT_ARGB1555:
7944                 /* checked in intel_framebuffer_init already */
7945                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7946                         return -EINVAL;
7947         case DRM_FORMAT_RGB565:
7948                 bpp = 6*3; /* min is 18bpp */
7949                 break;
7950         case DRM_FORMAT_XBGR8888:
7951         case DRM_FORMAT_ABGR8888:
7952                 /* checked in intel_framebuffer_init already */
7953                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7954                         return -EINVAL;
7955         case DRM_FORMAT_XRGB8888:
7956         case DRM_FORMAT_ARGB8888:
7957                 bpp = 8*3;
7958                 break;
7959         case DRM_FORMAT_XRGB2101010:
7960         case DRM_FORMAT_ARGB2101010:
7961         case DRM_FORMAT_XBGR2101010:
7962         case DRM_FORMAT_ABGR2101010:
7963                 /* checked in intel_framebuffer_init already */
7964                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7965                         return -EINVAL;
7966                 bpp = 10*3;
7967                 break;
7968         /* TODO: gen4+ supports 16 bpc floating point, too. */
7969         default:
7970                 DRM_DEBUG_KMS("unsupported depth\n");
7971                 return -EINVAL;
7972         }
7973
7974         pipe_config->pipe_bpp = bpp;
7975
7976         /* Clamp display bpp to EDID value */
7977         list_for_each_entry(connector, &dev->mode_config.connector_list,
7978                             base.head) {
7979                 if (!connector->new_encoder ||
7980                     connector->new_encoder->new_crtc != crtc)
7981                         continue;
7982
7983                 connected_sink_compute_bpp(connector, pipe_config);
7984         }
7985
7986         return bpp;
7987 }
7988
7989 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7990                                    struct intel_crtc_config *pipe_config,
7991                                    const char *context)
7992 {
7993         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7994                       context, pipe_name(crtc->pipe));
7995
7996         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7997         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7998                       pipe_config->pipe_bpp, pipe_config->dither);
7999         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8000                       pipe_config->has_pch_encoder,
8001                       pipe_config->fdi_lanes,
8002                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8003                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8004                       pipe_config->fdi_m_n.tu);
8005         DRM_DEBUG_KMS("requested mode:\n");
8006         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8007         DRM_DEBUG_KMS("adjusted mode:\n");
8008         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8009         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8010                       pipe_config->gmch_pfit.control,
8011                       pipe_config->gmch_pfit.pgm_ratios,
8012                       pipe_config->gmch_pfit.lvds_border_bits);
8013         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8014                       pipe_config->pch_pfit.pos,
8015                       pipe_config->pch_pfit.size);
8016         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8017 }
8018
8019 static bool check_encoder_cloning(struct drm_crtc *crtc)
8020 {
8021         int num_encoders = 0;
8022         bool uncloneable_encoders = false;
8023         struct intel_encoder *encoder;
8024
8025         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8026                             base.head) {
8027                 if (&encoder->new_crtc->base != crtc)
8028                         continue;
8029
8030                 num_encoders++;
8031                 if (!encoder->cloneable)
8032                         uncloneable_encoders = true;
8033         }
8034
8035         return !(num_encoders > 1 && uncloneable_encoders);
8036 }
8037
8038 static struct intel_crtc_config *
8039 intel_modeset_pipe_config(struct drm_crtc *crtc,
8040                           struct drm_framebuffer *fb,
8041                           struct drm_display_mode *mode)
8042 {
8043         struct drm_device *dev = crtc->dev;
8044         struct intel_encoder *encoder;
8045         struct intel_crtc_config *pipe_config;
8046         int plane_bpp, ret = -EINVAL;
8047         bool retry = true;
8048
8049         if (!check_encoder_cloning(crtc)) {
8050                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8051                 return ERR_PTR(-EINVAL);
8052         }
8053
8054         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8055         if (!pipe_config)
8056                 return ERR_PTR(-ENOMEM);
8057
8058         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8059         drm_mode_copy(&pipe_config->requested_mode, mode);
8060         pipe_config->cpu_transcoder =
8061                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8062         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8063
8064         /*
8065          * Sanitize sync polarity flags based on requested ones. If neither
8066          * positive or negative polarity is requested, treat this as meaning
8067          * negative polarity.
8068          */
8069         if (!(pipe_config->adjusted_mode.flags &
8070               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8071                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8072
8073         if (!(pipe_config->adjusted_mode.flags &
8074               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8075                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8076
8077         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8078          * plane pixel format and any sink constraints into account. Returns the
8079          * source plane bpp so that dithering can be selected on mismatches
8080          * after encoders and crtc also have had their say. */
8081         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8082                                               fb, pipe_config);
8083         if (plane_bpp < 0)
8084                 goto fail;
8085
8086 encoder_retry:
8087         /* Ensure the port clock defaults are reset when retrying. */
8088         pipe_config->port_clock = 0;
8089         pipe_config->pixel_multiplier = 1;
8090
8091         /* Fill in default crtc timings, allow encoders to overwrite them. */
8092         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8093
8094         /* Pass our mode to the connectors and the CRTC to give them a chance to
8095          * adjust it according to limitations or connector properties, and also
8096          * a chance to reject the mode entirely.
8097          */
8098         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8099                             base.head) {
8100
8101                 if (&encoder->new_crtc->base != crtc)
8102                         continue;
8103
8104                 if (!(encoder->compute_config(encoder, pipe_config))) {
8105                         DRM_DEBUG_KMS("Encoder config failure\n");
8106                         goto fail;
8107                 }
8108         }
8109
8110         /* Set default port clock if not overwritten by the encoder. Needs to be
8111          * done afterwards in case the encoder adjusts the mode. */
8112         if (!pipe_config->port_clock)
8113                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8114
8115         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8116         if (ret < 0) {
8117                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8118                 goto fail;
8119         }
8120
8121         if (ret == RETRY) {
8122                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8123                         ret = -EINVAL;
8124                         goto fail;
8125                 }
8126
8127                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8128                 retry = false;
8129                 goto encoder_retry;
8130         }
8131
8132         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8133         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8134                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8135
8136         return pipe_config;
8137 fail:
8138         kfree(pipe_config);
8139         return ERR_PTR(ret);
8140 }
8141
8142 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8143  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8144 static void
8145 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8146                              unsigned *prepare_pipes, unsigned *disable_pipes)
8147 {
8148         struct intel_crtc *intel_crtc;
8149         struct drm_device *dev = crtc->dev;
8150         struct intel_encoder *encoder;
8151         struct intel_connector *connector;
8152         struct drm_crtc *tmp_crtc;
8153
8154         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8155
8156         /* Check which crtcs have changed outputs connected to them, these need
8157          * to be part of the prepare_pipes mask. We don't (yet) support global
8158          * modeset across multiple crtcs, so modeset_pipes will only have one
8159          * bit set at most. */
8160         list_for_each_entry(connector, &dev->mode_config.connector_list,
8161                             base.head) {
8162                 if (connector->base.encoder == &connector->new_encoder->base)
8163                         continue;
8164
8165                 if (connector->base.encoder) {
8166                         tmp_crtc = connector->base.encoder->crtc;
8167
8168                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8169                 }
8170
8171                 if (connector->new_encoder)
8172                         *prepare_pipes |=
8173                                 1 << connector->new_encoder->new_crtc->pipe;
8174         }
8175
8176         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8177                             base.head) {
8178                 if (encoder->base.crtc == &encoder->new_crtc->base)
8179                         continue;
8180
8181                 if (encoder->base.crtc) {
8182                         tmp_crtc = encoder->base.crtc;
8183
8184                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8185                 }
8186
8187                 if (encoder->new_crtc)
8188                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8189         }
8190
8191         /* Check for any pipes that will be fully disabled ... */
8192         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8193                             base.head) {
8194                 bool used = false;
8195
8196                 /* Don't try to disable disabled crtcs. */
8197                 if (!intel_crtc->base.enabled)
8198                         continue;
8199
8200                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8201                                     base.head) {
8202                         if (encoder->new_crtc == intel_crtc)
8203                                 used = true;
8204                 }
8205
8206                 if (!used)
8207                         *disable_pipes |= 1 << intel_crtc->pipe;
8208         }
8209
8210
8211         /* set_mode is also used to update properties on life display pipes. */
8212         intel_crtc = to_intel_crtc(crtc);
8213         if (crtc->enabled)
8214                 *prepare_pipes |= 1 << intel_crtc->pipe;
8215
8216         /*
8217          * For simplicity do a full modeset on any pipe where the output routing
8218          * changed. We could be more clever, but that would require us to be
8219          * more careful with calling the relevant encoder->mode_set functions.
8220          */
8221         if (*prepare_pipes)
8222                 *modeset_pipes = *prepare_pipes;
8223
8224         /* ... and mask these out. */
8225         *modeset_pipes &= ~(*disable_pipes);
8226         *prepare_pipes &= ~(*disable_pipes);
8227
8228         /*
8229          * HACK: We don't (yet) fully support global modesets. intel_set_config
8230          * obies this rule, but the modeset restore mode of
8231          * intel_modeset_setup_hw_state does not.
8232          */
8233         *modeset_pipes &= 1 << intel_crtc->pipe;
8234         *prepare_pipes &= 1 << intel_crtc->pipe;
8235
8236         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8237                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8238 }
8239
8240 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8241 {
8242         struct drm_encoder *encoder;
8243         struct drm_device *dev = crtc->dev;
8244
8245         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8246                 if (encoder->crtc == crtc)
8247                         return true;
8248
8249         return false;
8250 }
8251
8252 static void
8253 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8254 {
8255         struct intel_encoder *intel_encoder;
8256         struct intel_crtc *intel_crtc;
8257         struct drm_connector *connector;
8258
8259         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8260                             base.head) {
8261                 if (!intel_encoder->base.crtc)
8262                         continue;
8263
8264                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8265
8266                 if (prepare_pipes & (1 << intel_crtc->pipe))
8267                         intel_encoder->connectors_active = false;
8268         }
8269
8270         intel_modeset_commit_output_state(dev);
8271
8272         /* Update computed state. */
8273         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8274                             base.head) {
8275                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8276         }
8277
8278         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8279                 if (!connector->encoder || !connector->encoder->crtc)
8280                         continue;
8281
8282                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8283
8284                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8285                         struct drm_property *dpms_property =
8286                                 dev->mode_config.dpms_property;
8287
8288                         connector->dpms = DRM_MODE_DPMS_ON;
8289                         drm_object_property_set_value(&connector->base,
8290                                                          dpms_property,
8291                                                          DRM_MODE_DPMS_ON);
8292
8293                         intel_encoder = to_intel_encoder(connector->encoder);
8294                         intel_encoder->connectors_active = true;
8295                 }
8296         }
8297
8298 }
8299
8300 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8301                                     struct intel_crtc_config *new)
8302 {
8303         int clock1, clock2, diff;
8304
8305         clock1 = cur->adjusted_mode.clock;
8306         clock2 = new->adjusted_mode.clock;
8307
8308         if (clock1 == clock2)
8309                 return true;
8310
8311         if (!clock1 || !clock2)
8312                 return false;
8313
8314         diff = abs(clock1 - clock2);
8315
8316         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8317                 return true;
8318
8319         return false;
8320 }
8321
8322 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8323         list_for_each_entry((intel_crtc), \
8324                             &(dev)->mode_config.crtc_list, \
8325                             base.head) \
8326                 if (mask & (1 <<(intel_crtc)->pipe))
8327
8328 static bool
8329 intel_pipe_config_compare(struct drm_device *dev,
8330                           struct intel_crtc_config *current_config,
8331                           struct intel_crtc_config *pipe_config)
8332 {
8333 #define PIPE_CONF_CHECK_X(name) \
8334         if (current_config->name != pipe_config->name) { \
8335                 DRM_ERROR("mismatch in " #name " " \
8336                           "(expected 0x%08x, found 0x%08x)\n", \
8337                           current_config->name, \
8338                           pipe_config->name); \
8339                 return false; \
8340         }
8341
8342 #define PIPE_CONF_CHECK_I(name) \
8343         if (current_config->name != pipe_config->name) { \
8344                 DRM_ERROR("mismatch in " #name " " \
8345                           "(expected %i, found %i)\n", \
8346                           current_config->name, \
8347                           pipe_config->name); \
8348                 return false; \
8349         }
8350
8351 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8352         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8353                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8354                           "(expected %i, found %i)\n", \
8355                           current_config->name & (mask), \
8356                           pipe_config->name & (mask)); \
8357                 return false; \
8358         }
8359
8360 #define PIPE_CONF_QUIRK(quirk)  \
8361         ((current_config->quirks | pipe_config->quirks) & (quirk))
8362
8363         PIPE_CONF_CHECK_I(cpu_transcoder);
8364
8365         PIPE_CONF_CHECK_I(has_pch_encoder);
8366         PIPE_CONF_CHECK_I(fdi_lanes);
8367         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8368         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8369         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8370         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8371         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8372
8373         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8374         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8375         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8376         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8377         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8378         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8379
8380         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8381         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8382         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8383         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8384         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8385         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8386
8387         PIPE_CONF_CHECK_I(pixel_multiplier);
8388
8389         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8390                               DRM_MODE_FLAG_INTERLACE);
8391
8392         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8393                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8394                                       DRM_MODE_FLAG_PHSYNC);
8395                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8396                                       DRM_MODE_FLAG_NHSYNC);
8397                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8398                                       DRM_MODE_FLAG_PVSYNC);
8399                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8400                                       DRM_MODE_FLAG_NVSYNC);
8401         }
8402
8403         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8404         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8405
8406         PIPE_CONF_CHECK_I(gmch_pfit.control);
8407         /* pfit ratios are autocomputed by the hw on gen4+ */
8408         if (INTEL_INFO(dev)->gen < 4)
8409                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8410         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8411         PIPE_CONF_CHECK_I(pch_pfit.pos);
8412         PIPE_CONF_CHECK_I(pch_pfit.size);
8413
8414         PIPE_CONF_CHECK_I(ips_enabled);
8415
8416         PIPE_CONF_CHECK_I(shared_dpll);
8417         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8418         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8419         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8420         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8421
8422 #undef PIPE_CONF_CHECK_X
8423 #undef PIPE_CONF_CHECK_I
8424 #undef PIPE_CONF_CHECK_FLAGS
8425 #undef PIPE_CONF_QUIRK
8426
8427         if (!IS_HASWELL(dev)) {
8428                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8429                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8430                                   current_config->adjusted_mode.clock,
8431                                   pipe_config->adjusted_mode.clock);
8432                         return false;
8433                 }
8434         }
8435
8436         return true;
8437 }
8438
8439 static void
8440 check_connector_state(struct drm_device *dev)
8441 {
8442         struct intel_connector *connector;
8443
8444         list_for_each_entry(connector, &dev->mode_config.connector_list,
8445                             base.head) {
8446                 /* This also checks the encoder/connector hw state with the
8447                  * ->get_hw_state callbacks. */
8448                 intel_connector_check_state(connector);
8449
8450                 WARN(&connector->new_encoder->base != connector->base.encoder,
8451                      "connector's staged encoder doesn't match current encoder\n");
8452         }
8453 }
8454
8455 static void
8456 check_encoder_state(struct drm_device *dev)
8457 {
8458         struct intel_encoder *encoder;
8459         struct intel_connector *connector;
8460
8461         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8462                             base.head) {
8463                 bool enabled = false;
8464                 bool active = false;
8465                 enum pipe pipe, tracked_pipe;
8466
8467                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8468                               encoder->base.base.id,
8469                               drm_get_encoder_name(&encoder->base));
8470
8471                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8472                      "encoder's stage crtc doesn't match current crtc\n");
8473                 WARN(encoder->connectors_active && !encoder->base.crtc,
8474                      "encoder's active_connectors set, but no crtc\n");
8475
8476                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8477                                     base.head) {
8478                         if (connector->base.encoder != &encoder->base)
8479                                 continue;
8480                         enabled = true;
8481                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8482                                 active = true;
8483                 }
8484                 WARN(!!encoder->base.crtc != enabled,
8485                      "encoder's enabled state mismatch "
8486                      "(expected %i, found %i)\n",
8487                      !!encoder->base.crtc, enabled);
8488                 WARN(active && !encoder->base.crtc,
8489                      "active encoder with no crtc\n");
8490
8491                 WARN(encoder->connectors_active != active,
8492                      "encoder's computed active state doesn't match tracked active state "
8493                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8494
8495                 active = encoder->get_hw_state(encoder, &pipe);
8496                 WARN(active != encoder->connectors_active,
8497                      "encoder's hw state doesn't match sw tracking "
8498                      "(expected %i, found %i)\n",
8499                      encoder->connectors_active, active);
8500
8501                 if (!encoder->base.crtc)
8502                         continue;
8503
8504                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8505                 WARN(active && pipe != tracked_pipe,
8506                      "active encoder's pipe doesn't match"
8507                      "(expected %i, found %i)\n",
8508                      tracked_pipe, pipe);
8509
8510         }
8511 }
8512
8513 static void
8514 check_crtc_state(struct drm_device *dev)
8515 {
8516         drm_i915_private_t *dev_priv = dev->dev_private;
8517         struct intel_crtc *crtc;
8518         struct intel_encoder *encoder;
8519         struct intel_crtc_config pipe_config;
8520
8521         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8522                             base.head) {
8523                 bool enabled = false;
8524                 bool active = false;
8525
8526                 memset(&pipe_config, 0, sizeof(pipe_config));
8527
8528                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8529                               crtc->base.base.id);
8530
8531                 WARN(crtc->active && !crtc->base.enabled,
8532                      "active crtc, but not enabled in sw tracking\n");
8533
8534                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8535                                     base.head) {
8536                         if (encoder->base.crtc != &crtc->base)
8537                                 continue;
8538                         enabled = true;
8539                         if (encoder->connectors_active)
8540                                 active = true;
8541                 }
8542
8543                 WARN(active != crtc->active,
8544                      "crtc's computed active state doesn't match tracked active state "
8545                      "(expected %i, found %i)\n", active, crtc->active);
8546                 WARN(enabled != crtc->base.enabled,
8547                      "crtc's computed enabled state doesn't match tracked enabled state "
8548                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8549
8550                 active = dev_priv->display.get_pipe_config(crtc,
8551                                                            &pipe_config);
8552
8553                 /* hw state is inconsistent with the pipe A quirk */
8554                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8555                         active = crtc->active;
8556
8557                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8558                                     base.head) {
8559                         if (encoder->base.crtc != &crtc->base)
8560                                 continue;
8561                         if (encoder->get_config)
8562                                 encoder->get_config(encoder, &pipe_config);
8563                 }
8564
8565                 if (dev_priv->display.get_clock)
8566                         dev_priv->display.get_clock(crtc, &pipe_config);
8567
8568                 WARN(crtc->active != active,
8569                      "crtc active state doesn't match with hw state "
8570                      "(expected %i, found %i)\n", crtc->active, active);
8571
8572                 if (active &&
8573                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8574                         WARN(1, "pipe state doesn't match!\n");
8575                         intel_dump_pipe_config(crtc, &pipe_config,
8576                                                "[hw state]");
8577                         intel_dump_pipe_config(crtc, &crtc->config,
8578                                                "[sw state]");
8579                 }
8580         }
8581 }
8582
8583 static void
8584 check_shared_dpll_state(struct drm_device *dev)
8585 {
8586         drm_i915_private_t *dev_priv = dev->dev_private;
8587         struct intel_crtc *crtc;
8588         struct intel_dpll_hw_state dpll_hw_state;
8589         int i;
8590
8591         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8592                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8593                 int enabled_crtcs = 0, active_crtcs = 0;
8594                 bool active;
8595
8596                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8597
8598                 DRM_DEBUG_KMS("%s\n", pll->name);
8599
8600                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8601
8602                 WARN(pll->active > pll->refcount,
8603                      "more active pll users than references: %i vs %i\n",
8604                      pll->active, pll->refcount);
8605                 WARN(pll->active && !pll->on,
8606                      "pll in active use but not on in sw tracking\n");
8607                 WARN(pll->on && !pll->active,
8608                      "pll in on but not on in use in sw tracking\n");
8609                 WARN(pll->on != active,
8610                      "pll on state mismatch (expected %i, found %i)\n",
8611                      pll->on, active);
8612
8613                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8614                                     base.head) {
8615                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8616                                 enabled_crtcs++;
8617                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8618                                 active_crtcs++;
8619                 }
8620                 WARN(pll->active != active_crtcs,
8621                      "pll active crtcs mismatch (expected %i, found %i)\n",
8622                      pll->active, active_crtcs);
8623                 WARN(pll->refcount != enabled_crtcs,
8624                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8625                      pll->refcount, enabled_crtcs);
8626
8627                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8628                                        sizeof(dpll_hw_state)),
8629                      "pll hw state mismatch\n");
8630         }
8631 }
8632
8633 void
8634 intel_modeset_check_state(struct drm_device *dev)
8635 {
8636         check_connector_state(dev);
8637         check_encoder_state(dev);
8638         check_crtc_state(dev);
8639         check_shared_dpll_state(dev);
8640 }
8641
8642 static int __intel_set_mode(struct drm_crtc *crtc,
8643                             struct drm_display_mode *mode,
8644                             int x, int y, struct drm_framebuffer *fb)
8645 {
8646         struct drm_device *dev = crtc->dev;
8647         drm_i915_private_t *dev_priv = dev->dev_private;
8648         struct drm_display_mode *saved_mode, *saved_hwmode;
8649         struct intel_crtc_config *pipe_config = NULL;
8650         struct intel_crtc *intel_crtc;
8651         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8652         int ret = 0;
8653
8654         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8655         if (!saved_mode)
8656                 return -ENOMEM;
8657         saved_hwmode = saved_mode + 1;
8658
8659         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8660                                      &prepare_pipes, &disable_pipes);
8661
8662         *saved_hwmode = crtc->hwmode;
8663         *saved_mode = crtc->mode;
8664
8665         /* Hack: Because we don't (yet) support global modeset on multiple
8666          * crtcs, we don't keep track of the new mode for more than one crtc.
8667          * Hence simply check whether any bit is set in modeset_pipes in all the
8668          * pieces of code that are not yet converted to deal with mutliple crtcs
8669          * changing their mode at the same time. */
8670         if (modeset_pipes) {
8671                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8672                 if (IS_ERR(pipe_config)) {
8673                         ret = PTR_ERR(pipe_config);
8674                         pipe_config = NULL;
8675
8676                         goto out;
8677                 }
8678                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8679                                        "[modeset]");
8680         }
8681
8682         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8683                 intel_crtc_disable(&intel_crtc->base);
8684
8685         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8686                 if (intel_crtc->base.enabled)
8687                         dev_priv->display.crtc_disable(&intel_crtc->base);
8688         }
8689
8690         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8691          * to set it here already despite that we pass it down the callchain.
8692          */
8693         if (modeset_pipes) {
8694                 crtc->mode = *mode;
8695                 /* mode_set/enable/disable functions rely on a correct pipe
8696                  * config. */
8697                 to_intel_crtc(crtc)->config = *pipe_config;
8698         }
8699
8700         /* Only after disabling all output pipelines that will be changed can we
8701          * update the the output configuration. */
8702         intel_modeset_update_state(dev, prepare_pipes);
8703
8704         if (dev_priv->display.modeset_global_resources)
8705                 dev_priv->display.modeset_global_resources(dev);
8706
8707         /* Set up the DPLL and any encoders state that needs to adjust or depend
8708          * on the DPLL.
8709          */
8710         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8711                 ret = intel_crtc_mode_set(&intel_crtc->base,
8712                                           x, y, fb);
8713                 if (ret)
8714                         goto done;
8715         }
8716
8717         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8718         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8719                 dev_priv->display.crtc_enable(&intel_crtc->base);
8720
8721         if (modeset_pipes) {
8722                 /* Store real post-adjustment hardware mode. */
8723                 crtc->hwmode = pipe_config->adjusted_mode;
8724
8725                 /* Calculate and store various constants which
8726                  * are later needed by vblank and swap-completion
8727                  * timestamping. They are derived from true hwmode.
8728                  */
8729                 drm_calc_timestamping_constants(crtc);
8730         }
8731
8732         /* FIXME: add subpixel order */
8733 done:
8734         if (ret && crtc->enabled) {
8735                 crtc->hwmode = *saved_hwmode;
8736                 crtc->mode = *saved_mode;
8737         }
8738
8739 out:
8740         kfree(pipe_config);
8741         kfree(saved_mode);
8742         return ret;
8743 }
8744
8745 int intel_set_mode(struct drm_crtc *crtc,
8746                      struct drm_display_mode *mode,
8747                      int x, int y, struct drm_framebuffer *fb)
8748 {
8749         int ret;
8750
8751         ret = __intel_set_mode(crtc, mode, x, y, fb);
8752
8753         if (ret == 0)
8754                 intel_modeset_check_state(crtc->dev);
8755
8756         return ret;
8757 }
8758
8759 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8760 {
8761         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8762 }
8763
8764 #undef for_each_intel_crtc_masked
8765
8766 static void intel_set_config_free(struct intel_set_config *config)
8767 {
8768         if (!config)
8769                 return;
8770
8771         kfree(config->save_connector_encoders);
8772         kfree(config->save_encoder_crtcs);
8773         kfree(config);
8774 }
8775
8776 static int intel_set_config_save_state(struct drm_device *dev,
8777                                        struct intel_set_config *config)
8778 {
8779         struct drm_encoder *encoder;
8780         struct drm_connector *connector;
8781         int count;
8782
8783         config->save_encoder_crtcs =
8784                 kcalloc(dev->mode_config.num_encoder,
8785                         sizeof(struct drm_crtc *), GFP_KERNEL);
8786         if (!config->save_encoder_crtcs)
8787                 return -ENOMEM;
8788
8789         config->save_connector_encoders =
8790                 kcalloc(dev->mode_config.num_connector,
8791                         sizeof(struct drm_encoder *), GFP_KERNEL);
8792         if (!config->save_connector_encoders)
8793                 return -ENOMEM;
8794
8795         /* Copy data. Note that driver private data is not affected.
8796          * Should anything bad happen only the expected state is
8797          * restored, not the drivers personal bookkeeping.
8798          */
8799         count = 0;
8800         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8801                 config->save_encoder_crtcs[count++] = encoder->crtc;
8802         }
8803
8804         count = 0;
8805         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8806                 config->save_connector_encoders[count++] = connector->encoder;
8807         }
8808
8809         return 0;
8810 }
8811
8812 static void intel_set_config_restore_state(struct drm_device *dev,
8813                                            struct intel_set_config *config)
8814 {
8815         struct intel_encoder *encoder;
8816         struct intel_connector *connector;
8817         int count;
8818
8819         count = 0;
8820         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8821                 encoder->new_crtc =
8822                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8823         }
8824
8825         count = 0;
8826         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8827                 connector->new_encoder =
8828                         to_intel_encoder(config->save_connector_encoders[count++]);
8829         }
8830 }
8831
8832 static bool
8833 is_crtc_connector_off(struct drm_mode_set *set)
8834 {
8835         int i;
8836
8837         if (set->num_connectors == 0)
8838                 return false;
8839
8840         if (WARN_ON(set->connectors == NULL))
8841                 return false;
8842
8843         for (i = 0; i < set->num_connectors; i++)
8844                 if (set->connectors[i]->encoder &&
8845                     set->connectors[i]->encoder->crtc == set->crtc &&
8846                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8847                         return true;
8848
8849         return false;
8850 }
8851
8852 static void
8853 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8854                                       struct intel_set_config *config)
8855 {
8856
8857         /* We should be able to check here if the fb has the same properties
8858          * and then just flip_or_move it */
8859         if (is_crtc_connector_off(set)) {
8860                 config->mode_changed = true;
8861         } else if (set->crtc->fb != set->fb) {
8862                 /* If we have no fb then treat it as a full mode set */
8863                 if (set->crtc->fb == NULL) {
8864                         struct intel_crtc *intel_crtc =
8865                                 to_intel_crtc(set->crtc);
8866
8867                         if (intel_crtc->active && i915_fastboot) {
8868                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8869                                 config->fb_changed = true;
8870                         } else {
8871                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8872                                 config->mode_changed = true;
8873                         }
8874                 } else if (set->fb == NULL) {
8875                         config->mode_changed = true;
8876                 } else if (set->fb->pixel_format !=
8877                            set->crtc->fb->pixel_format) {
8878                         config->mode_changed = true;
8879                 } else {
8880                         config->fb_changed = true;
8881                 }
8882         }
8883
8884         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8885                 config->fb_changed = true;
8886
8887         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8888                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8889                 drm_mode_debug_printmodeline(&set->crtc->mode);
8890                 drm_mode_debug_printmodeline(set->mode);
8891                 config->mode_changed = true;
8892         }
8893 }
8894
8895 static int
8896 intel_modeset_stage_output_state(struct drm_device *dev,
8897                                  struct drm_mode_set *set,
8898                                  struct intel_set_config *config)
8899 {
8900         struct drm_crtc *new_crtc;
8901         struct intel_connector *connector;
8902         struct intel_encoder *encoder;
8903         int count, ro;
8904
8905         /* The upper layers ensure that we either disable a crtc or have a list
8906          * of connectors. For paranoia, double-check this. */
8907         WARN_ON(!set->fb && (set->num_connectors != 0));
8908         WARN_ON(set->fb && (set->num_connectors == 0));
8909
8910         count = 0;
8911         list_for_each_entry(connector, &dev->mode_config.connector_list,
8912                             base.head) {
8913                 /* Otherwise traverse passed in connector list and get encoders
8914                  * for them. */
8915                 for (ro = 0; ro < set->num_connectors; ro++) {
8916                         if (set->connectors[ro] == &connector->base) {
8917                                 connector->new_encoder = connector->encoder;
8918                                 break;
8919                         }
8920                 }
8921
8922                 /* If we disable the crtc, disable all its connectors. Also, if
8923                  * the connector is on the changing crtc but not on the new
8924                  * connector list, disable it. */
8925                 if ((!set->fb || ro == set->num_connectors) &&
8926                     connector->base.encoder &&
8927                     connector->base.encoder->crtc == set->crtc) {
8928                         connector->new_encoder = NULL;
8929
8930                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8931                                 connector->base.base.id,
8932                                 drm_get_connector_name(&connector->base));
8933                 }
8934
8935
8936                 if (&connector->new_encoder->base != connector->base.encoder) {
8937                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8938                         config->mode_changed = true;
8939                 }
8940         }
8941         /* connector->new_encoder is now updated for all connectors. */
8942
8943         /* Update crtc of enabled connectors. */
8944         count = 0;
8945         list_for_each_entry(connector, &dev->mode_config.connector_list,
8946                             base.head) {
8947                 if (!connector->new_encoder)
8948                         continue;
8949
8950                 new_crtc = connector->new_encoder->base.crtc;
8951
8952                 for (ro = 0; ro < set->num_connectors; ro++) {
8953                         if (set->connectors[ro] == &connector->base)
8954                                 new_crtc = set->crtc;
8955                 }
8956
8957                 /* Make sure the new CRTC will work with the encoder */
8958                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8959                                            new_crtc)) {
8960                         return -EINVAL;
8961                 }
8962                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8963
8964                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8965                         connector->base.base.id,
8966                         drm_get_connector_name(&connector->base),
8967                         new_crtc->base.id);
8968         }
8969
8970         /* Check for any encoders that needs to be disabled. */
8971         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8972                             base.head) {
8973                 list_for_each_entry(connector,
8974                                     &dev->mode_config.connector_list,
8975                                     base.head) {
8976                         if (connector->new_encoder == encoder) {
8977                                 WARN_ON(!connector->new_encoder->new_crtc);
8978
8979                                 goto next_encoder;
8980                         }
8981                 }
8982                 encoder->new_crtc = NULL;
8983 next_encoder:
8984                 /* Only now check for crtc changes so we don't miss encoders
8985                  * that will be disabled. */
8986                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8987                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8988                         config->mode_changed = true;
8989                 }
8990         }
8991         /* Now we've also updated encoder->new_crtc for all encoders. */
8992
8993         return 0;
8994 }
8995
8996 static int intel_crtc_set_config(struct drm_mode_set *set)
8997 {
8998         struct drm_device *dev;
8999         struct drm_mode_set save_set;
9000         struct intel_set_config *config;
9001         int ret;
9002
9003         BUG_ON(!set);
9004         BUG_ON(!set->crtc);
9005         BUG_ON(!set->crtc->helper_private);
9006
9007         /* Enforce sane interface api - has been abused by the fb helper. */
9008         BUG_ON(!set->mode && set->fb);
9009         BUG_ON(set->fb && set->num_connectors == 0);
9010
9011         if (set->fb) {
9012                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9013                                 set->crtc->base.id, set->fb->base.id,
9014                                 (int)set->num_connectors, set->x, set->y);
9015         } else {
9016                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9017         }
9018
9019         dev = set->crtc->dev;
9020
9021         ret = -ENOMEM;
9022         config = kzalloc(sizeof(*config), GFP_KERNEL);
9023         if (!config)
9024                 goto out_config;
9025
9026         ret = intel_set_config_save_state(dev, config);
9027         if (ret)
9028                 goto out_config;
9029
9030         save_set.crtc = set->crtc;
9031         save_set.mode = &set->crtc->mode;
9032         save_set.x = set->crtc->x;
9033         save_set.y = set->crtc->y;
9034         save_set.fb = set->crtc->fb;
9035
9036         /* Compute whether we need a full modeset, only an fb base update or no
9037          * change at all. In the future we might also check whether only the
9038          * mode changed, e.g. for LVDS where we only change the panel fitter in
9039          * such cases. */
9040         intel_set_config_compute_mode_changes(set, config);
9041
9042         ret = intel_modeset_stage_output_state(dev, set, config);
9043         if (ret)
9044                 goto fail;
9045
9046         if (config->mode_changed) {
9047                 ret = intel_set_mode(set->crtc, set->mode,
9048                                      set->x, set->y, set->fb);
9049         } else if (config->fb_changed) {
9050                 intel_crtc_wait_for_pending_flips(set->crtc);
9051
9052                 ret = intel_pipe_set_base(set->crtc,
9053                                           set->x, set->y, set->fb);
9054         }
9055
9056         if (ret) {
9057                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9058                               set->crtc->base.id, ret);
9059 fail:
9060                 intel_set_config_restore_state(dev, config);
9061
9062                 /* Try to restore the config */
9063                 if (config->mode_changed &&
9064                     intel_set_mode(save_set.crtc, save_set.mode,
9065                                    save_set.x, save_set.y, save_set.fb))
9066                         DRM_ERROR("failed to restore config after modeset failure\n");
9067         }
9068
9069 out_config:
9070         intel_set_config_free(config);
9071         return ret;
9072 }
9073
9074 static const struct drm_crtc_funcs intel_crtc_funcs = {
9075         .cursor_set = intel_crtc_cursor_set,
9076         .cursor_move = intel_crtc_cursor_move,
9077         .gamma_set = intel_crtc_gamma_set,
9078         .set_config = intel_crtc_set_config,
9079         .destroy = intel_crtc_destroy,
9080         .page_flip = intel_crtc_page_flip,
9081 };
9082
9083 static void intel_cpu_pll_init(struct drm_device *dev)
9084 {
9085         if (HAS_DDI(dev))
9086                 intel_ddi_pll_init(dev);
9087 }
9088
9089 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9090                                       struct intel_shared_dpll *pll,
9091                                       struct intel_dpll_hw_state *hw_state)
9092 {
9093         uint32_t val;
9094
9095         val = I915_READ(PCH_DPLL(pll->id));
9096         hw_state->dpll = val;
9097         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9098         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9099
9100         return val & DPLL_VCO_ENABLE;
9101 }
9102
9103 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9104                                   struct intel_shared_dpll *pll)
9105 {
9106         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9107         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9108 }
9109
9110 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9111                                 struct intel_shared_dpll *pll)
9112 {
9113         /* PCH refclock must be enabled first */
9114         assert_pch_refclk_enabled(dev_priv);
9115
9116         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9117
9118         /* Wait for the clocks to stabilize. */
9119         POSTING_READ(PCH_DPLL(pll->id));
9120         udelay(150);
9121
9122         /* The pixel multiplier can only be updated once the
9123          * DPLL is enabled and the clocks are stable.
9124          *
9125          * So write it again.
9126          */
9127         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9128         POSTING_READ(PCH_DPLL(pll->id));
9129         udelay(200);
9130 }
9131
9132 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9133                                  struct intel_shared_dpll *pll)
9134 {
9135         struct drm_device *dev = dev_priv->dev;
9136         struct intel_crtc *crtc;
9137
9138         /* Make sure no transcoder isn't still depending on us. */
9139         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9140                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9141                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9142         }
9143
9144         I915_WRITE(PCH_DPLL(pll->id), 0);
9145         POSTING_READ(PCH_DPLL(pll->id));
9146         udelay(200);
9147 }
9148
9149 static char *ibx_pch_dpll_names[] = {
9150         "PCH DPLL A",
9151         "PCH DPLL B",
9152 };
9153
9154 static void ibx_pch_dpll_init(struct drm_device *dev)
9155 {
9156         struct drm_i915_private *dev_priv = dev->dev_private;
9157         int i;
9158
9159         dev_priv->num_shared_dpll = 2;
9160
9161         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9162                 dev_priv->shared_dplls[i].id = i;
9163                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9164                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9165                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9166                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9167                 dev_priv->shared_dplls[i].get_hw_state =
9168                         ibx_pch_dpll_get_hw_state;
9169         }
9170 }
9171
9172 static void intel_shared_dpll_init(struct drm_device *dev)
9173 {
9174         struct drm_i915_private *dev_priv = dev->dev_private;
9175
9176         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9177                 ibx_pch_dpll_init(dev);
9178         else
9179                 dev_priv->num_shared_dpll = 0;
9180
9181         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9182         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9183                       dev_priv->num_shared_dpll);
9184 }
9185
9186 static void intel_crtc_init(struct drm_device *dev, int pipe)
9187 {
9188         drm_i915_private_t *dev_priv = dev->dev_private;
9189         struct intel_crtc *intel_crtc;
9190         int i;
9191
9192         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9193         if (intel_crtc == NULL)
9194                 return;
9195
9196         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9197
9198         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9199         for (i = 0; i < 256; i++) {
9200                 intel_crtc->lut_r[i] = i;
9201                 intel_crtc->lut_g[i] = i;
9202                 intel_crtc->lut_b[i] = i;
9203         }
9204
9205         /* Swap pipes & planes for FBC on pre-965 */
9206         intel_crtc->pipe = pipe;
9207         intel_crtc->plane = pipe;
9208         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9209                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9210                 intel_crtc->plane = !pipe;
9211         }
9212
9213         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9214                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9215         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9216         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9217
9218         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9219 }
9220
9221 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9222                                 struct drm_file *file)
9223 {
9224         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9225         struct drm_mode_object *drmmode_obj;
9226         struct intel_crtc *crtc;
9227
9228         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9229                 return -ENODEV;
9230
9231         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9232                         DRM_MODE_OBJECT_CRTC);
9233
9234         if (!drmmode_obj) {
9235                 DRM_ERROR("no such CRTC id\n");
9236                 return -EINVAL;
9237         }
9238
9239         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9240         pipe_from_crtc_id->pipe = crtc->pipe;
9241
9242         return 0;
9243 }
9244
9245 static int intel_encoder_clones(struct intel_encoder *encoder)
9246 {
9247         struct drm_device *dev = encoder->base.dev;
9248         struct intel_encoder *source_encoder;
9249         int index_mask = 0;
9250         int entry = 0;
9251
9252         list_for_each_entry(source_encoder,
9253                             &dev->mode_config.encoder_list, base.head) {
9254
9255                 if (encoder == source_encoder)
9256                         index_mask |= (1 << entry);
9257
9258                 /* Intel hw has only one MUX where enocoders could be cloned. */
9259                 if (encoder->cloneable && source_encoder->cloneable)
9260                         index_mask |= (1 << entry);
9261
9262                 entry++;
9263         }
9264
9265         return index_mask;
9266 }
9267
9268 static bool has_edp_a(struct drm_device *dev)
9269 {
9270         struct drm_i915_private *dev_priv = dev->dev_private;
9271
9272         if (!IS_MOBILE(dev))
9273                 return false;
9274
9275         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9276                 return false;
9277
9278         if (IS_GEN5(dev) &&
9279             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9280                 return false;
9281
9282         return true;
9283 }
9284
9285 static void intel_setup_outputs(struct drm_device *dev)
9286 {
9287         struct drm_i915_private *dev_priv = dev->dev_private;
9288         struct intel_encoder *encoder;
9289         bool dpd_is_edp = false;
9290
9291         intel_lvds_init(dev);
9292
9293         if (!IS_ULT(dev))
9294                 intel_crt_init(dev);
9295
9296         if (HAS_DDI(dev)) {
9297                 int found;
9298
9299                 /* Haswell uses DDI functions to detect digital outputs */
9300                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9301                 /* DDI A only supports eDP */
9302                 if (found)
9303                         intel_ddi_init(dev, PORT_A);
9304
9305                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9306                  * register */
9307                 found = I915_READ(SFUSE_STRAP);
9308
9309                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9310                         intel_ddi_init(dev, PORT_B);
9311                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9312                         intel_ddi_init(dev, PORT_C);
9313                 if (found & SFUSE_STRAP_DDID_DETECTED)
9314                         intel_ddi_init(dev, PORT_D);
9315         } else if (HAS_PCH_SPLIT(dev)) {
9316                 int found;
9317                 dpd_is_edp = intel_dpd_is_edp(dev);
9318
9319                 if (has_edp_a(dev))
9320                         intel_dp_init(dev, DP_A, PORT_A);
9321
9322                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9323                         /* PCH SDVOB multiplex with HDMIB */
9324                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9325                         if (!found)
9326                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9327                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9328                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9329                 }
9330
9331                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9332                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9333
9334                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9335                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9336
9337                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9338                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9339
9340                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9341                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9342         } else if (IS_VALLEYVIEW(dev)) {
9343                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9344                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9345                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9346
9347                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9348                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9349                                         PORT_B);
9350                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9351                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9352                 }
9353         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9354                 bool found = false;
9355
9356                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9357                         DRM_DEBUG_KMS("probing SDVOB\n");
9358                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9359                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9360                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9361                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9362                         }
9363
9364                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9365                                 intel_dp_init(dev, DP_B, PORT_B);
9366                 }
9367
9368                 /* Before G4X SDVOC doesn't have its own detect register */
9369
9370                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9371                         DRM_DEBUG_KMS("probing SDVOC\n");
9372                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9373                 }
9374
9375                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9376
9377                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9378                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9379                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9380                         }
9381                         if (SUPPORTS_INTEGRATED_DP(dev))
9382                                 intel_dp_init(dev, DP_C, PORT_C);
9383                 }
9384
9385                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9386                     (I915_READ(DP_D) & DP_DETECTED))
9387                         intel_dp_init(dev, DP_D, PORT_D);
9388         } else if (IS_GEN2(dev))
9389                 intel_dvo_init(dev);
9390
9391         if (SUPPORTS_TV(dev))
9392                 intel_tv_init(dev);
9393
9394         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9395                 encoder->base.possible_crtcs = encoder->crtc_mask;
9396                 encoder->base.possible_clones =
9397                         intel_encoder_clones(encoder);
9398         }
9399
9400         intel_init_pch_refclk(dev);
9401
9402         drm_helper_move_panel_connectors_to_head(dev);
9403 }
9404
9405 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9406 {
9407         drm_framebuffer_cleanup(&fb->base);
9408         drm_gem_object_unreference_unlocked(&fb->obj->base);
9409 }
9410
9411 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9412 {
9413         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9414
9415         intel_framebuffer_fini(intel_fb);
9416         kfree(intel_fb);
9417 }
9418
9419 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9420                                                 struct drm_file *file,
9421                                                 unsigned int *handle)
9422 {
9423         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9424         struct drm_i915_gem_object *obj = intel_fb->obj;
9425
9426         return drm_gem_handle_create(file, &obj->base, handle);
9427 }
9428
9429 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9430         .destroy = intel_user_framebuffer_destroy,
9431         .create_handle = intel_user_framebuffer_create_handle,
9432 };
9433
9434 int intel_framebuffer_init(struct drm_device *dev,
9435                            struct intel_framebuffer *intel_fb,
9436                            struct drm_mode_fb_cmd2 *mode_cmd,
9437                            struct drm_i915_gem_object *obj)
9438 {
9439         int pitch_limit;
9440         int ret;
9441
9442         if (obj->tiling_mode == I915_TILING_Y) {
9443                 DRM_DEBUG("hardware does not support tiling Y\n");
9444                 return -EINVAL;
9445         }
9446
9447         if (mode_cmd->pitches[0] & 63) {
9448                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9449                           mode_cmd->pitches[0]);
9450                 return -EINVAL;
9451         }
9452
9453         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9454                 pitch_limit = 32*1024;
9455         } else if (INTEL_INFO(dev)->gen >= 4) {
9456                 if (obj->tiling_mode)
9457                         pitch_limit = 16*1024;
9458                 else
9459                         pitch_limit = 32*1024;
9460         } else if (INTEL_INFO(dev)->gen >= 3) {
9461                 if (obj->tiling_mode)
9462                         pitch_limit = 8*1024;
9463                 else
9464                         pitch_limit = 16*1024;
9465         } else
9466                 /* XXX DSPC is limited to 4k tiled */
9467                 pitch_limit = 8*1024;
9468
9469         if (mode_cmd->pitches[0] > pitch_limit) {
9470                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9471                           obj->tiling_mode ? "tiled" : "linear",
9472                           mode_cmd->pitches[0], pitch_limit);
9473                 return -EINVAL;
9474         }
9475
9476         if (obj->tiling_mode != I915_TILING_NONE &&
9477             mode_cmd->pitches[0] != obj->stride) {
9478                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9479                           mode_cmd->pitches[0], obj->stride);
9480                 return -EINVAL;
9481         }
9482
9483         /* Reject formats not supported by any plane early. */
9484         switch (mode_cmd->pixel_format) {
9485         case DRM_FORMAT_C8:
9486         case DRM_FORMAT_RGB565:
9487         case DRM_FORMAT_XRGB8888:
9488         case DRM_FORMAT_ARGB8888:
9489                 break;
9490         case DRM_FORMAT_XRGB1555:
9491         case DRM_FORMAT_ARGB1555:
9492                 if (INTEL_INFO(dev)->gen > 3) {
9493                         DRM_DEBUG("unsupported pixel format: %s\n",
9494                                   drm_get_format_name(mode_cmd->pixel_format));
9495                         return -EINVAL;
9496                 }
9497                 break;
9498         case DRM_FORMAT_XBGR8888:
9499         case DRM_FORMAT_ABGR8888:
9500         case DRM_FORMAT_XRGB2101010:
9501         case DRM_FORMAT_ARGB2101010:
9502         case DRM_FORMAT_XBGR2101010:
9503         case DRM_FORMAT_ABGR2101010:
9504                 if (INTEL_INFO(dev)->gen < 4) {
9505                         DRM_DEBUG("unsupported pixel format: %s\n",
9506                                   drm_get_format_name(mode_cmd->pixel_format));
9507                         return -EINVAL;
9508                 }
9509                 break;
9510         case DRM_FORMAT_YUYV:
9511         case DRM_FORMAT_UYVY:
9512         case DRM_FORMAT_YVYU:
9513         case DRM_FORMAT_VYUY:
9514                 if (INTEL_INFO(dev)->gen < 5) {
9515                         DRM_DEBUG("unsupported pixel format: %s\n",
9516                                   drm_get_format_name(mode_cmd->pixel_format));
9517                         return -EINVAL;
9518                 }
9519                 break;
9520         default:
9521                 DRM_DEBUG("unsupported pixel format: %s\n",
9522                           drm_get_format_name(mode_cmd->pixel_format));
9523                 return -EINVAL;
9524         }
9525
9526         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9527         if (mode_cmd->offsets[0] != 0)
9528                 return -EINVAL;
9529
9530         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9531         intel_fb->obj = obj;
9532
9533         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9534         if (ret) {
9535                 DRM_ERROR("framebuffer init failed %d\n", ret);
9536                 return ret;
9537         }
9538
9539         return 0;
9540 }
9541
9542 static struct drm_framebuffer *
9543 intel_user_framebuffer_create(struct drm_device *dev,
9544                               struct drm_file *filp,
9545                               struct drm_mode_fb_cmd2 *mode_cmd)
9546 {
9547         struct drm_i915_gem_object *obj;
9548
9549         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9550                                                 mode_cmd->handles[0]));
9551         if (&obj->base == NULL)
9552                 return ERR_PTR(-ENOENT);
9553
9554         return intel_framebuffer_create(dev, mode_cmd, obj);
9555 }
9556
9557 static const struct drm_mode_config_funcs intel_mode_funcs = {
9558         .fb_create = intel_user_framebuffer_create,
9559         .output_poll_changed = intel_fb_output_poll_changed,
9560 };
9561
9562 /* Set up chip specific display functions */
9563 static void intel_init_display(struct drm_device *dev)
9564 {
9565         struct drm_i915_private *dev_priv = dev->dev_private;
9566
9567         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9568                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9569         else if (IS_VALLEYVIEW(dev))
9570                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9571         else if (IS_PINEVIEW(dev))
9572                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9573         else
9574                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9575
9576         if (HAS_DDI(dev)) {
9577                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9578                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9579                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9580                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9581                 dev_priv->display.off = haswell_crtc_off;
9582                 dev_priv->display.update_plane = ironlake_update_plane;
9583         } else if (HAS_PCH_SPLIT(dev)) {
9584                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9585                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9586                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9587                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9588                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9589                 dev_priv->display.off = ironlake_crtc_off;
9590                 dev_priv->display.update_plane = ironlake_update_plane;
9591         } else if (IS_VALLEYVIEW(dev)) {
9592                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9593                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9594                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9595                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9596                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9597                 dev_priv->display.off = i9xx_crtc_off;
9598                 dev_priv->display.update_plane = i9xx_update_plane;
9599         } else {
9600                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9601                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9602                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9603                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9604                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9605                 dev_priv->display.off = i9xx_crtc_off;
9606                 dev_priv->display.update_plane = i9xx_update_plane;
9607         }
9608
9609         /* Returns the core display clock speed */
9610         if (IS_VALLEYVIEW(dev))
9611                 dev_priv->display.get_display_clock_speed =
9612                         valleyview_get_display_clock_speed;
9613         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9614                 dev_priv->display.get_display_clock_speed =
9615                         i945_get_display_clock_speed;
9616         else if (IS_I915G(dev))
9617                 dev_priv->display.get_display_clock_speed =
9618                         i915_get_display_clock_speed;
9619         else if (IS_I945GM(dev) || IS_845G(dev))
9620                 dev_priv->display.get_display_clock_speed =
9621                         i9xx_misc_get_display_clock_speed;
9622         else if (IS_PINEVIEW(dev))
9623                 dev_priv->display.get_display_clock_speed =
9624                         pnv_get_display_clock_speed;
9625         else if (IS_I915GM(dev))
9626                 dev_priv->display.get_display_clock_speed =
9627                         i915gm_get_display_clock_speed;
9628         else if (IS_I865G(dev))
9629                 dev_priv->display.get_display_clock_speed =
9630                         i865_get_display_clock_speed;
9631         else if (IS_I85X(dev))
9632                 dev_priv->display.get_display_clock_speed =
9633                         i855_get_display_clock_speed;
9634         else /* 852, 830 */
9635                 dev_priv->display.get_display_clock_speed =
9636                         i830_get_display_clock_speed;
9637
9638         if (HAS_PCH_SPLIT(dev)) {
9639                 if (IS_GEN5(dev)) {
9640                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9641                         dev_priv->display.write_eld = ironlake_write_eld;
9642                 } else if (IS_GEN6(dev)) {
9643                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9644                         dev_priv->display.write_eld = ironlake_write_eld;
9645                 } else if (IS_IVYBRIDGE(dev)) {
9646                         /* FIXME: detect B0+ stepping and use auto training */
9647                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9648                         dev_priv->display.write_eld = ironlake_write_eld;
9649                         dev_priv->display.modeset_global_resources =
9650                                 ivb_modeset_global_resources;
9651                 } else if (IS_HASWELL(dev)) {
9652                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9653                         dev_priv->display.write_eld = haswell_write_eld;
9654                         dev_priv->display.modeset_global_resources =
9655                                 haswell_modeset_global_resources;
9656                 }
9657         } else if (IS_G4X(dev)) {
9658                 dev_priv->display.write_eld = g4x_write_eld;
9659         }
9660
9661         /* Default just returns -ENODEV to indicate unsupported */
9662         dev_priv->display.queue_flip = intel_default_queue_flip;
9663
9664         switch (INTEL_INFO(dev)->gen) {
9665         case 2:
9666                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9667                 break;
9668
9669         case 3:
9670                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9671                 break;
9672
9673         case 4:
9674         case 5:
9675                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9676                 break;
9677
9678         case 6:
9679                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9680                 break;
9681         case 7:
9682                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9683                 break;
9684         }
9685 }
9686
9687 /*
9688  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9689  * resume, or other times.  This quirk makes sure that's the case for
9690  * affected systems.
9691  */
9692 static void quirk_pipea_force(struct drm_device *dev)
9693 {
9694         struct drm_i915_private *dev_priv = dev->dev_private;
9695
9696         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9697         DRM_INFO("applying pipe a force quirk\n");
9698 }
9699
9700 /*
9701  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9702  */
9703 static void quirk_ssc_force_disable(struct drm_device *dev)
9704 {
9705         struct drm_i915_private *dev_priv = dev->dev_private;
9706         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9707         DRM_INFO("applying lvds SSC disable quirk\n");
9708 }
9709
9710 /*
9711  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9712  * brightness value
9713  */
9714 static void quirk_invert_brightness(struct drm_device *dev)
9715 {
9716         struct drm_i915_private *dev_priv = dev->dev_private;
9717         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9718         DRM_INFO("applying inverted panel brightness quirk\n");
9719 }
9720
9721 /*
9722  * Some machines (Dell XPS13) suffer broken backlight controls if
9723  * BLM_PCH_PWM_ENABLE is set.
9724  */
9725 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9726 {
9727         struct drm_i915_private *dev_priv = dev->dev_private;
9728         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9729         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9730 }
9731
9732 struct intel_quirk {
9733         int device;
9734         int subsystem_vendor;
9735         int subsystem_device;
9736         void (*hook)(struct drm_device *dev);
9737 };
9738
9739 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9740 struct intel_dmi_quirk {
9741         void (*hook)(struct drm_device *dev);
9742         const struct dmi_system_id (*dmi_id_list)[];
9743 };
9744
9745 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9746 {
9747         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9748         return 1;
9749 }
9750
9751 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9752         {
9753                 .dmi_id_list = &(const struct dmi_system_id[]) {
9754                         {
9755                                 .callback = intel_dmi_reverse_brightness,
9756                                 .ident = "NCR Corporation",
9757                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9758                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9759                                 },
9760                         },
9761                         { }  /* terminating entry */
9762                 },
9763                 .hook = quirk_invert_brightness,
9764         },
9765 };
9766
9767 static struct intel_quirk intel_quirks[] = {
9768         /* HP Mini needs pipe A force quirk (LP: #322104) */
9769         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9770
9771         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9772         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9773
9774         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9775         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9776
9777         /* 830/845 need to leave pipe A & dpll A up */
9778         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9779         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9780
9781         /* Lenovo U160 cannot use SSC on LVDS */
9782         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9783
9784         /* Sony Vaio Y cannot use SSC on LVDS */
9785         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9786
9787         /* Acer Aspire 5734Z must invert backlight brightness */
9788         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9789
9790         /* Acer/eMachines G725 */
9791         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9792
9793         /* Acer/eMachines e725 */
9794         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9795
9796         /* Acer/Packard Bell NCL20 */
9797         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9798
9799         /* Acer Aspire 4736Z */
9800         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9801
9802         /* Dell XPS13 HD Sandy Bridge */
9803         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9804         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9805         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9806 };
9807
9808 static void intel_init_quirks(struct drm_device *dev)
9809 {
9810         struct pci_dev *d = dev->pdev;
9811         int i;
9812
9813         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9814                 struct intel_quirk *q = &intel_quirks[i];
9815
9816                 if (d->device == q->device &&
9817                     (d->subsystem_vendor == q->subsystem_vendor ||
9818                      q->subsystem_vendor == PCI_ANY_ID) &&
9819                     (d->subsystem_device == q->subsystem_device ||
9820                      q->subsystem_device == PCI_ANY_ID))
9821                         q->hook(dev);
9822         }
9823         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9824                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9825                         intel_dmi_quirks[i].hook(dev);
9826         }
9827 }
9828
9829 /* Disable the VGA plane that we never use */
9830 static void i915_disable_vga(struct drm_device *dev)
9831 {
9832         struct drm_i915_private *dev_priv = dev->dev_private;
9833         u8 sr1;
9834         u32 vga_reg = i915_vgacntrl_reg(dev);
9835
9836         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9837         outb(SR01, VGA_SR_INDEX);
9838         sr1 = inb(VGA_SR_DATA);
9839         outb(sr1 | 1<<5, VGA_SR_DATA);
9840         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9841         udelay(300);
9842
9843         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9844         POSTING_READ(vga_reg);
9845 }
9846
9847 void intel_modeset_init_hw(struct drm_device *dev)
9848 {
9849         intel_init_power_well(dev);
9850
9851         intel_prepare_ddi(dev);
9852
9853         intel_init_clock_gating(dev);
9854
9855         mutex_lock(&dev->struct_mutex);
9856         intel_enable_gt_powersave(dev);
9857         mutex_unlock(&dev->struct_mutex);
9858 }
9859
9860 void intel_modeset_suspend_hw(struct drm_device *dev)
9861 {
9862         intel_suspend_hw(dev);
9863 }
9864
9865 void intel_modeset_init(struct drm_device *dev)
9866 {
9867         struct drm_i915_private *dev_priv = dev->dev_private;
9868         int i, j, ret;
9869
9870         drm_mode_config_init(dev);
9871
9872         dev->mode_config.min_width = 0;
9873         dev->mode_config.min_height = 0;
9874
9875         dev->mode_config.preferred_depth = 24;
9876         dev->mode_config.prefer_shadow = 1;
9877
9878         dev->mode_config.funcs = &intel_mode_funcs;
9879
9880         intel_init_quirks(dev);
9881
9882         intel_init_pm(dev);
9883
9884         if (INTEL_INFO(dev)->num_pipes == 0)
9885                 return;
9886
9887         intel_init_display(dev);
9888
9889         if (IS_GEN2(dev)) {
9890                 dev->mode_config.max_width = 2048;
9891                 dev->mode_config.max_height = 2048;
9892         } else if (IS_GEN3(dev)) {
9893                 dev->mode_config.max_width = 4096;
9894                 dev->mode_config.max_height = 4096;
9895         } else {
9896                 dev->mode_config.max_width = 8192;
9897                 dev->mode_config.max_height = 8192;
9898         }
9899         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9900
9901         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9902                       INTEL_INFO(dev)->num_pipes,
9903                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9904
9905         for_each_pipe(i) {
9906                 intel_crtc_init(dev, i);
9907                 for (j = 0; j < dev_priv->num_plane; j++) {
9908                         ret = intel_plane_init(dev, i, j);
9909                         if (ret)
9910                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9911                                               pipe_name(i), sprite_name(i, j), ret);
9912                 }
9913         }
9914
9915         intel_cpu_pll_init(dev);
9916         intel_shared_dpll_init(dev);
9917
9918         /* Just disable it once at startup */
9919         i915_disable_vga(dev);
9920         intel_setup_outputs(dev);
9921
9922         /* Just in case the BIOS is doing something questionable. */
9923         intel_disable_fbc(dev);
9924 }
9925
9926 static void
9927 intel_connector_break_all_links(struct intel_connector *connector)
9928 {
9929         connector->base.dpms = DRM_MODE_DPMS_OFF;
9930         connector->base.encoder = NULL;
9931         connector->encoder->connectors_active = false;
9932         connector->encoder->base.crtc = NULL;
9933 }
9934
9935 static void intel_enable_pipe_a(struct drm_device *dev)
9936 {
9937         struct intel_connector *connector;
9938         struct drm_connector *crt = NULL;
9939         struct intel_load_detect_pipe load_detect_temp;
9940
9941         /* We can't just switch on the pipe A, we need to set things up with a
9942          * proper mode and output configuration. As a gross hack, enable pipe A
9943          * by enabling the load detect pipe once. */
9944         list_for_each_entry(connector,
9945                             &dev->mode_config.connector_list,
9946                             base.head) {
9947                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9948                         crt = &connector->base;
9949                         break;
9950                 }
9951         }
9952
9953         if (!crt)
9954                 return;
9955
9956         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9957                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9958
9959
9960 }
9961
9962 static bool
9963 intel_check_plane_mapping(struct intel_crtc *crtc)
9964 {
9965         struct drm_device *dev = crtc->base.dev;
9966         struct drm_i915_private *dev_priv = dev->dev_private;
9967         u32 reg, val;
9968
9969         if (INTEL_INFO(dev)->num_pipes == 1)
9970                 return true;
9971
9972         reg = DSPCNTR(!crtc->plane);
9973         val = I915_READ(reg);
9974
9975         if ((val & DISPLAY_PLANE_ENABLE) &&
9976             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9977                 return false;
9978
9979         return true;
9980 }
9981
9982 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9983 {
9984         struct drm_device *dev = crtc->base.dev;
9985         struct drm_i915_private *dev_priv = dev->dev_private;
9986         u32 reg;
9987
9988         /* Clear any frame start delays used for debugging left by the BIOS */
9989         reg = PIPECONF(crtc->config.cpu_transcoder);
9990         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9991
9992         /* We need to sanitize the plane -> pipe mapping first because this will
9993          * disable the crtc (and hence change the state) if it is wrong. Note
9994          * that gen4+ has a fixed plane -> pipe mapping.  */
9995         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9996                 struct intel_connector *connector;
9997                 bool plane;
9998
9999                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10000                               crtc->base.base.id);
10001
10002                 /* Pipe has the wrong plane attached and the plane is active.
10003                  * Temporarily change the plane mapping and disable everything
10004                  * ...  */
10005                 plane = crtc->plane;
10006                 crtc->plane = !plane;
10007                 dev_priv->display.crtc_disable(&crtc->base);
10008                 crtc->plane = plane;
10009
10010                 /* ... and break all links. */
10011                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10012                                     base.head) {
10013                         if (connector->encoder->base.crtc != &crtc->base)
10014                                 continue;
10015
10016                         intel_connector_break_all_links(connector);
10017                 }
10018
10019                 WARN_ON(crtc->active);
10020                 crtc->base.enabled = false;
10021         }
10022
10023         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10024             crtc->pipe == PIPE_A && !crtc->active) {
10025                 /* BIOS forgot to enable pipe A, this mostly happens after
10026                  * resume. Force-enable the pipe to fix this, the update_dpms
10027                  * call below we restore the pipe to the right state, but leave
10028                  * the required bits on. */
10029                 intel_enable_pipe_a(dev);
10030         }
10031
10032         /* Adjust the state of the output pipe according to whether we
10033          * have active connectors/encoders. */
10034         intel_crtc_update_dpms(&crtc->base);
10035
10036         if (crtc->active != crtc->base.enabled) {
10037                 struct intel_encoder *encoder;
10038
10039                 /* This can happen either due to bugs in the get_hw_state
10040                  * functions or because the pipe is force-enabled due to the
10041                  * pipe A quirk. */
10042                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10043                               crtc->base.base.id,
10044                               crtc->base.enabled ? "enabled" : "disabled",
10045                               crtc->active ? "enabled" : "disabled");
10046
10047                 crtc->base.enabled = crtc->active;
10048
10049                 /* Because we only establish the connector -> encoder ->
10050                  * crtc links if something is active, this means the
10051                  * crtc is now deactivated. Break the links. connector
10052                  * -> encoder links are only establish when things are
10053                  *  actually up, hence no need to break them. */
10054                 WARN_ON(crtc->active);
10055
10056                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10057                         WARN_ON(encoder->connectors_active);
10058                         encoder->base.crtc = NULL;
10059                 }
10060         }
10061 }
10062
10063 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10064 {
10065         struct intel_connector *connector;
10066         struct drm_device *dev = encoder->base.dev;
10067
10068         /* We need to check both for a crtc link (meaning that the
10069          * encoder is active and trying to read from a pipe) and the
10070          * pipe itself being active. */
10071         bool has_active_crtc = encoder->base.crtc &&
10072                 to_intel_crtc(encoder->base.crtc)->active;
10073
10074         if (encoder->connectors_active && !has_active_crtc) {
10075                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10076                               encoder->base.base.id,
10077                               drm_get_encoder_name(&encoder->base));
10078
10079                 /* Connector is active, but has no active pipe. This is
10080                  * fallout from our resume register restoring. Disable
10081                  * the encoder manually again. */
10082                 if (encoder->base.crtc) {
10083                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10084                                       encoder->base.base.id,
10085                                       drm_get_encoder_name(&encoder->base));
10086                         encoder->disable(encoder);
10087                 }
10088
10089                 /* Inconsistent output/port/pipe state happens presumably due to
10090                  * a bug in one of the get_hw_state functions. Or someplace else
10091                  * in our code, like the register restore mess on resume. Clamp
10092                  * things to off as a safer default. */
10093                 list_for_each_entry(connector,
10094                                     &dev->mode_config.connector_list,
10095                                     base.head) {
10096                         if (connector->encoder != encoder)
10097                                 continue;
10098
10099                         intel_connector_break_all_links(connector);
10100                 }
10101         }
10102         /* Enabled encoders without active connectors will be fixed in
10103          * the crtc fixup. */
10104 }
10105
10106 void i915_redisable_vga(struct drm_device *dev)
10107 {
10108         struct drm_i915_private *dev_priv = dev->dev_private;
10109         u32 vga_reg = i915_vgacntrl_reg(dev);
10110
10111         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10112                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10113                 i915_disable_vga(dev);
10114         }
10115 }
10116
10117 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10118 {
10119         struct drm_i915_private *dev_priv = dev->dev_private;
10120         enum pipe pipe;
10121         struct intel_crtc *crtc;
10122         struct intel_encoder *encoder;
10123         struct intel_connector *connector;
10124         int i;
10125
10126         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10127                             base.head) {
10128                 memset(&crtc->config, 0, sizeof(crtc->config));
10129
10130                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10131                                                                  &crtc->config);
10132
10133                 crtc->base.enabled = crtc->active;
10134
10135                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10136                               crtc->base.base.id,
10137                               crtc->active ? "enabled" : "disabled");
10138         }
10139
10140         /* FIXME: Smash this into the new shared dpll infrastructure. */
10141         if (HAS_DDI(dev))
10142                 intel_ddi_setup_hw_pll_state(dev);
10143
10144         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10145                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10146
10147                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10148                 pll->active = 0;
10149                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10150                                     base.head) {
10151                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10152                                 pll->active++;
10153                 }
10154                 pll->refcount = pll->active;
10155
10156                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10157                               pll->name, pll->refcount, pll->on);
10158         }
10159
10160         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10161                             base.head) {
10162                 pipe = 0;
10163
10164                 if (encoder->get_hw_state(encoder, &pipe)) {
10165                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10166                         encoder->base.crtc = &crtc->base;
10167                         if (encoder->get_config)
10168                                 encoder->get_config(encoder, &crtc->config);
10169                 } else {
10170                         encoder->base.crtc = NULL;
10171                 }
10172
10173                 encoder->connectors_active = false;
10174                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10175                               encoder->base.base.id,
10176                               drm_get_encoder_name(&encoder->base),
10177                               encoder->base.crtc ? "enabled" : "disabled",
10178                               pipe);
10179         }
10180
10181         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10182                             base.head) {
10183                 if (!crtc->active)
10184                         continue;
10185                 if (dev_priv->display.get_clock)
10186                         dev_priv->display.get_clock(crtc,
10187                                                     &crtc->config);
10188         }
10189
10190         list_for_each_entry(connector, &dev->mode_config.connector_list,
10191                             base.head) {
10192                 if (connector->get_hw_state(connector)) {
10193                         connector->base.dpms = DRM_MODE_DPMS_ON;
10194                         connector->encoder->connectors_active = true;
10195                         connector->base.encoder = &connector->encoder->base;
10196                 } else {
10197                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10198                         connector->base.encoder = NULL;
10199                 }
10200                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10201                               connector->base.base.id,
10202                               drm_get_connector_name(&connector->base),
10203                               connector->base.encoder ? "enabled" : "disabled");
10204         }
10205 }
10206
10207 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10208  * and i915 state tracking structures. */
10209 void intel_modeset_setup_hw_state(struct drm_device *dev,
10210                                   bool force_restore)
10211 {
10212         struct drm_i915_private *dev_priv = dev->dev_private;
10213         enum pipe pipe;
10214         struct drm_plane *plane;
10215         struct intel_crtc *crtc;
10216         struct intel_encoder *encoder;
10217         int i;
10218
10219         intel_modeset_readout_hw_state(dev);
10220
10221         /*
10222          * Now that we have the config, copy it to each CRTC struct
10223          * Note that this could go away if we move to using crtc_config
10224          * checking everywhere.
10225          */
10226         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10227                             base.head) {
10228                 if (crtc->active && i915_fastboot) {
10229                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10230
10231                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10232                                       crtc->base.base.id);
10233                         drm_mode_debug_printmodeline(&crtc->base.mode);
10234                 }
10235         }
10236
10237         /* HW state is read out, now we need to sanitize this mess. */
10238         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10239                             base.head) {
10240                 intel_sanitize_encoder(encoder);
10241         }
10242
10243         for_each_pipe(pipe) {
10244                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10245                 intel_sanitize_crtc(crtc);
10246                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10247         }
10248
10249         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10250                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10251
10252                 if (!pll->on || pll->active)
10253                         continue;
10254
10255                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10256
10257                 pll->disable(dev_priv, pll);
10258                 pll->on = false;
10259         }
10260
10261         if (force_restore) {
10262                 /*
10263                  * We need to use raw interfaces for restoring state to avoid
10264                  * checking (bogus) intermediate states.
10265                  */
10266                 for_each_pipe(pipe) {
10267                         struct drm_crtc *crtc =
10268                                 dev_priv->pipe_to_crtc_mapping[pipe];
10269
10270                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10271                                          crtc->fb);
10272                 }
10273                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10274                         intel_plane_restore(plane);
10275
10276                 i915_redisable_vga(dev);
10277         } else {
10278                 intel_modeset_update_staged_output_state(dev);
10279         }
10280
10281         intel_modeset_check_state(dev);
10282
10283         drm_mode_config_reset(dev);
10284 }
10285
10286 void intel_modeset_gem_init(struct drm_device *dev)
10287 {
10288         intel_modeset_init_hw(dev);
10289
10290         intel_setup_overlay(dev);
10291
10292         intel_modeset_setup_hw_state(dev, false);
10293 }
10294
10295 void intel_modeset_cleanup(struct drm_device *dev)
10296 {
10297         struct drm_i915_private *dev_priv = dev->dev_private;
10298         struct drm_crtc *crtc;
10299         struct intel_crtc *intel_crtc;
10300
10301         /*
10302          * Interrupts and polling as the first thing to avoid creating havoc.
10303          * Too much stuff here (turning of rps, connectors, ...) would
10304          * experience fancy races otherwise.
10305          */
10306         drm_irq_uninstall(dev);
10307         cancel_work_sync(&dev_priv->hotplug_work);
10308         /*
10309          * Due to the hpd irq storm handling the hotplug work can re-arm the
10310          * poll handlers. Hence disable polling after hpd handling is shut down.
10311          */
10312         drm_kms_helper_poll_fini(dev);
10313
10314         mutex_lock(&dev->struct_mutex);
10315
10316         intel_unregister_dsm_handler();
10317
10318         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10319                 /* Skip inactive CRTCs */
10320                 if (!crtc->fb)
10321                         continue;
10322
10323                 intel_crtc = to_intel_crtc(crtc);
10324                 intel_increase_pllclock(crtc);
10325         }
10326
10327         intel_disable_fbc(dev);
10328
10329         intel_disable_gt_powersave(dev);
10330
10331         ironlake_teardown_rc6(dev);
10332
10333         mutex_unlock(&dev->struct_mutex);
10334
10335         /* flush any delayed tasks or pending work */
10336         flush_scheduled_work();
10337
10338         /* destroy backlight, if any, before the connectors */
10339         intel_panel_destroy_backlight(dev);
10340
10341         drm_mode_config_cleanup(dev);
10342
10343         intel_cleanup_overlay(dev);
10344 }
10345
10346 /*
10347  * Return which encoder is currently attached for connector.
10348  */
10349 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10350 {
10351         return &intel_attached_encoder(connector)->base;
10352 }
10353
10354 void intel_connector_attach_encoder(struct intel_connector *connector,
10355                                     struct intel_encoder *encoder)
10356 {
10357         connector->encoder = encoder;
10358         drm_mode_connector_attach_encoder(&connector->base,
10359                                           &encoder->base);
10360 }
10361
10362 /*
10363  * set vga decode state - true == enable VGA decode
10364  */
10365 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10366 {
10367         struct drm_i915_private *dev_priv = dev->dev_private;
10368         u16 gmch_ctrl;
10369
10370         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10371         if (state)
10372                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10373         else
10374                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10375         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10376         return 0;
10377 }
10378
10379 struct intel_display_error_state {
10380
10381         u32 power_well_driver;
10382
10383         struct intel_cursor_error_state {
10384                 u32 control;
10385                 u32 position;
10386                 u32 base;
10387                 u32 size;
10388         } cursor[I915_MAX_PIPES];
10389
10390         struct intel_pipe_error_state {
10391                 enum transcoder cpu_transcoder;
10392                 u32 conf;
10393                 u32 source;
10394
10395                 u32 htotal;
10396                 u32 hblank;
10397                 u32 hsync;
10398                 u32 vtotal;
10399                 u32 vblank;
10400                 u32 vsync;
10401         } pipe[I915_MAX_PIPES];
10402
10403         struct intel_plane_error_state {
10404                 u32 control;
10405                 u32 stride;
10406                 u32 size;
10407                 u32 pos;
10408                 u32 addr;
10409                 u32 surface;
10410                 u32 tile_offset;
10411         } plane[I915_MAX_PIPES];
10412 };
10413
10414 struct intel_display_error_state *
10415 intel_display_capture_error_state(struct drm_device *dev)
10416 {
10417         drm_i915_private_t *dev_priv = dev->dev_private;
10418         struct intel_display_error_state *error;
10419         enum transcoder cpu_transcoder;
10420         int i;
10421
10422         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10423         if (error == NULL)
10424                 return NULL;
10425
10426         if (HAS_POWER_WELL(dev))
10427                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10428
10429         for_each_pipe(i) {
10430                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10431                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10432
10433                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10434                         error->cursor[i].control = I915_READ(CURCNTR(i));
10435                         error->cursor[i].position = I915_READ(CURPOS(i));
10436                         error->cursor[i].base = I915_READ(CURBASE(i));
10437                 } else {
10438                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10439                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10440                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10441                 }
10442
10443                 error->plane[i].control = I915_READ(DSPCNTR(i));
10444                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10445                 if (INTEL_INFO(dev)->gen <= 3) {
10446                         error->plane[i].size = I915_READ(DSPSIZE(i));
10447                         error->plane[i].pos = I915_READ(DSPPOS(i));
10448                 }
10449                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10450                         error->plane[i].addr = I915_READ(DSPADDR(i));
10451                 if (INTEL_INFO(dev)->gen >= 4) {
10452                         error->plane[i].surface = I915_READ(DSPSURF(i));
10453                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10454                 }
10455
10456                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10457                 error->pipe[i].source = I915_READ(PIPESRC(i));
10458                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10459                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10460                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10461                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10462                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10463                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10464         }
10465
10466         /* In the code above we read the registers without checking if the power
10467          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10468          * prevent the next I915_WRITE from detecting it and printing an error
10469          * message. */
10470         intel_uncore_clear_errors(dev);
10471
10472         return error;
10473 }
10474
10475 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10476
10477 void
10478 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10479                                 struct drm_device *dev,
10480                                 struct intel_display_error_state *error)
10481 {
10482         int i;
10483
10484         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10485         if (HAS_POWER_WELL(dev))
10486                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10487                            error->power_well_driver);
10488         for_each_pipe(i) {
10489                 err_printf(m, "Pipe [%d]:\n", i);
10490                 err_printf(m, "  CPU transcoder: %c\n",
10491                            transcoder_name(error->pipe[i].cpu_transcoder));
10492                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10493                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10494                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10495                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10496                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10497                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10498                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10499                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10500
10501                 err_printf(m, "Plane [%d]:\n", i);
10502                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10503                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10504                 if (INTEL_INFO(dev)->gen <= 3) {
10505                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10506                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10507                 }
10508                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10509                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10510                 if (INTEL_INFO(dev)->gen >= 4) {
10511                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10512                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10513                 }
10514
10515                 err_printf(m, "Cursor [%d]:\n", i);
10516                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10517                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10518                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10519         }
10520 }