Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 int
  73 intel_pch_rawclk(struct drm_device *dev)
  74 {
  75         struct drm_i915_private *dev_priv = dev->dev_private;
  76
  77         WARN_ON(!HAS_PCH_SPLIT(dev));
  78
  79         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  80 }
  81
  82 static inline u32 /* units of 100MHz */
  83 intel_fdi_link_freq(struct drm_device *dev)
  84 {
  85         if (IS_GEN5(dev)) {
  86                 struct drm_i915_private *dev_priv = dev->dev_private;
  87                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  88         } else
  89                 return 27;
  90 }
  91
  92 static const intel_limit_t intel_limits_i8xx_dac = {
  93         .dot = { .min = 25000, .max = 350000 },
  94         .vco = { .min = 930000, .max = 1400000 },
  95         .n = { .min = 3, .max = 16 },
  96         .m = { .min = 96, .max = 140 },
  97         .m1 = { .min = 18, .max = 26 },
  98         .m2 = { .min = 6, .max = 16 },
  99         .p = { .min = 4, .max = 128 },
 100         .p1 = { .min = 2, .max = 33 },
 101         .p2 = { .dot_limit = 165000,
 102                 .p2_slow = 4, .p2_fast = 2 },
 103 };
 104
 105 static const intel_limit_t intel_limits_i8xx_dvo = {
 106         .dot = { .min = 25000, .max = 350000 },
 107         .vco = { .min = 930000, .max = 1400000 },
 108         .n = { .min = 3, .max = 16 },
 109         .m = { .min = 96, .max = 140 },
 110         .m1 = { .min = 18, .max = 26 },
 111         .m2 = { .min = 6, .max = 16 },
 112         .p = { .min = 4, .max = 128 },
 113         .p1 = { .min = 2, .max = 33 },
 114         .p2 = { .dot_limit = 165000,
 115                 .p2_slow = 4, .p2_fast = 4 },
 116 };
 117
 118 static const intel_limit_t intel_limits_i8xx_lvds = {
 119         .dot = { .min = 25000, .max = 350000 },
 120         .vco = { .min = 930000, .max = 1400000 },
 121         .n = { .min = 3, .max = 16 },
 122         .m = { .min = 96, .max = 140 },
 123         .m1 = { .min = 18, .max = 26 },
 124         .m2 = { .min = 6, .max = 16 },
 125         .p = { .min = 4, .max = 128 },
 126         .p1 = { .min = 1, .max = 6 },
 127         .p2 = { .dot_limit = 165000,
 128                 .p2_slow = 14, .p2_fast = 7 },
 129 };
 130
 131 static const intel_limit_t intel_limits_i9xx_sdvo = {
 132         .dot = { .min = 20000, .max = 400000 },
 133         .vco = { .min = 1400000, .max = 2800000 },
 134         .n = { .min = 1, .max = 6 },
 135         .m = { .min = 70, .max = 120 },
 136         .m1 = { .min = 8, .max = 18 },
 137         .m2 = { .min = 3, .max = 7 },
 138         .p = { .min = 5, .max = 80 },
 139         .p1 = { .min = 1, .max = 8 },
 140         .p2 = { .dot_limit = 200000,
 141                 .p2_slow = 10, .p2_fast = 5 },
 142 };
 143
 144 static const intel_limit_t intel_limits_i9xx_lvds = {
 145         .dot = { .min = 20000, .max = 400000 },
 146         .vco = { .min = 1400000, .max = 2800000 },
 147         .n = { .min = 1, .max = 6 },
 148         .m = { .min = 70, .max = 120 },
 149         .m1 = { .min = 8, .max = 18 },
 150         .m2 = { .min = 3, .max = 7 },
 151         .p = { .min = 7, .max = 98 },
 152         .p1 = { .min = 1, .max = 8 },
 153         .p2 = { .dot_limit = 112000,
 154                 .p2_slow = 14, .p2_fast = 7 },
 155 };
 156
 157
 158 static const intel_limit_t intel_limits_g4x_sdvo = {
 159         .dot = { .min = 25000, .max = 270000 },
 160         .vco = { .min = 1750000, .max = 3500000},
 161         .n = { .min = 1, .max = 4 },
 162         .m = { .min = 104, .max = 138 },
 163         .m1 = { .min = 17, .max = 23 },
 164         .m2 = { .min = 5, .max = 11 },
 165         .p = { .min = 10, .max = 30 },
 166         .p1 = { .min = 1, .max = 3},
 167         .p2 = { .dot_limit = 270000,
 168                 .p2_slow = 10,
 169                 .p2_fast = 10
 170         },
 171 };
 172
 173 static const intel_limit_t intel_limits_g4x_hdmi = {
 174         .dot = { .min = 22000, .max = 400000 },
 175         .vco = { .min = 1750000, .max = 3500000},
 176         .n = { .min = 1, .max = 4 },
 177         .m = { .min = 104, .max = 138 },
 178         .m1 = { .min = 16, .max = 23 },
 179         .m2 = { .min = 5, .max = 11 },
 180         .p = { .min = 5, .max = 80 },
 181         .p1 = { .min = 1, .max = 8},
 182         .p2 = { .dot_limit = 165000,
 183                 .p2_slow = 10, .p2_fast = 5 },
 184 };
 185
 186 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 187         .dot = { .min = 20000, .max = 115000 },
 188         .vco = { .min = 1750000, .max = 3500000 },
 189         .n = { .min = 1, .max = 3 },
 190         .m = { .min = 104, .max = 138 },
 191         .m1 = { .min = 17, .max = 23 },
 192         .m2 = { .min = 5, .max = 11 },
 193         .p = { .min = 28, .max = 112 },
 194         .p1 = { .min = 2, .max = 8 },
 195         .p2 = { .dot_limit = 0,
 196                 .p2_slow = 14, .p2_fast = 14
 197         },
 198 };
 199
 200 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 201         .dot = { .min = 80000, .max = 224000 },
 202         .vco = { .min = 1750000, .max = 3500000 },
 203         .n = { .min = 1, .max = 3 },
 204         .m = { .min = 104, .max = 138 },
 205         .m1 = { .min = 17, .max = 23 },
 206         .m2 = { .min = 5, .max = 11 },
 207         .p = { .min = 14, .max = 42 },
 208         .p1 = { .min = 2, .max = 6 },
 209         .p2 = { .dot_limit = 0,
 210                 .p2_slow = 7, .p2_fast = 7
 211         },
 212 };
 213
 214 static const intel_limit_t intel_limits_pineview_sdvo = {
 215         .dot = { .min = 20000, .max = 400000},
 216         .vco = { .min = 1700000, .max = 3500000 },
 217         /* Pineview's Ncounter is a ring counter */
 218         .n = { .min = 3, .max = 6 },
 219         .m = { .min = 2, .max = 256 },
 220         /* Pineview only has one combined m divider, which we treat as m2. */
 221         .m1 = { .min = 0, .max = 0 },
 222         .m2 = { .min = 0, .max = 254 },
 223         .p = { .min = 5, .max = 80 },
 224         .p1 = { .min = 1, .max = 8 },
 225         .p2 = { .dot_limit = 200000,
 226                 .p2_slow = 10, .p2_fast = 5 },
 227 };
 228
 229 static const intel_limit_t intel_limits_pineview_lvds = {
 230         .dot = { .min = 20000, .max = 400000 },
 231         .vco = { .min = 1700000, .max = 3500000 },
 232         .n = { .min = 3, .max = 6 },
 233         .m = { .min = 2, .max = 256 },
 234         .m1 = { .min = 0, .max = 0 },
 235         .m2 = { .min = 0, .max = 254 },
 236         .p = { .min = 7, .max = 112 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 112000,
 239                 .p2_slow = 14, .p2_fast = 14 },
 240 };
 241
 242 /* Ironlake / Sandybridge
 243  *
 244  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 245  * the range value for them is (actual_value - 2).
 246  */
 247 static const intel_limit_t intel_limits_ironlake_dac = {
 248         .dot = { .min = 25000, .max = 350000 },
 249         .vco = { .min = 1760000, .max = 3510000 },
 250         .n = { .min = 1, .max = 5 },
 251         .m = { .min = 79, .max = 127 },
 252         .m1 = { .min = 12, .max = 22 },
 253         .m2 = { .min = 5, .max = 9 },
 254         .p = { .min = 5, .max = 80 },
 255         .p1 = { .min = 1, .max = 8 },
 256         .p2 = { .dot_limit = 225000,
 257                 .p2_slow = 10, .p2_fast = 5 },
 258 };
 259
 260 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 261         .dot = { .min = 25000, .max = 350000 },
 262         .vco = { .min = 1760000, .max = 3510000 },
 263         .n = { .min = 1, .max = 3 },
 264         .m = { .min = 79, .max = 118 },
 265         .m1 = { .min = 12, .max = 22 },
 266         .m2 = { .min = 5, .max = 9 },
 267         .p = { .min = 28, .max = 112 },
 268         .p1 = { .min = 2, .max = 8 },
 269         .p2 = { .dot_limit = 225000,
 270                 .p2_slow = 14, .p2_fast = 14 },
 271 };
 272
 273 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 274         .dot = { .min = 25000, .max = 350000 },
 275         .vco = { .min = 1760000, .max = 3510000 },
 276         .n = { .min = 1, .max = 3 },
 277         .m = { .min = 79, .max = 127 },
 278         .m1 = { .min = 12, .max = 22 },
 279         .m2 = { .min = 5, .max = 9 },
 280         .p = { .min = 14, .max = 56 },
 281         .p1 = { .min = 2, .max = 8 },
 282         .p2 = { .dot_limit = 225000,
 283                 .p2_slow = 7, .p2_fast = 7 },
 284 };
 285
 286 /* LVDS 100mhz refclk limits. */
 287 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 288         .dot = { .min = 25000, .max = 350000 },
 289         .vco = { .min = 1760000, .max = 3510000 },
 290         .n = { .min = 1, .max = 2 },
 291         .m = { .min = 79, .max = 126 },
 292         .m1 = { .min = 12, .max = 22 },
 293         .m2 = { .min = 5, .max = 9 },
 294         .p = { .min = 28, .max = 112 },
 295         .p1 = { .min = 2, .max = 8 },
 296         .p2 = { .dot_limit = 225000,
 297                 .p2_slow = 14, .p2_fast = 14 },
 298 };
 299
 300 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 301         .dot = { .min = 25000, .max = 350000 },
 302         .vco = { .min = 1760000, .max = 3510000 },
 303         .n = { .min = 1, .max = 3 },
 304         .m = { .min = 79, .max = 126 },
 305         .m1 = { .min = 12, .max = 22 },
 306         .m2 = { .min = 5, .max = 9 },
 307         .p = { .min = 14, .max = 42 },
 308         .p1 = { .min = 2, .max = 6 },
 309         .p2 = { .dot_limit = 225000,
 310                 .p2_slow = 7, .p2_fast = 7 },
 311 };
 312
 313 static const intel_limit_t intel_limits_vlv_dac = {
 314         .dot = { .min = 25000, .max = 270000 },
 315         .vco = { .min = 4000000, .max = 6000000 },
 316         .n = { .min = 1, .max = 7 },
 317         .m = { .min = 22, .max = 450 }, /* guess */
 318         .m1 = { .min = 2, .max = 3 },
 319         .m2 = { .min = 11, .max = 156 },
 320         .p = { .min = 10, .max = 30 },
 321         .p1 = { .min = 1, .max = 3 },
 322         .p2 = { .dot_limit = 270000,
 323                 .p2_slow = 2, .p2_fast = 20 },
 324 };
 325
 326 static const intel_limit_t intel_limits_vlv_hdmi = {
 327         .dot = { .min = 25000, .max = 270000 },
 328         .vco = { .min = 4000000, .max = 6000000 },
 329         .n = { .min = 1, .max = 7 },
 330         .m = { .min = 60, .max = 300 }, /* guess */
 331         .m1 = { .min = 2, .max = 3 },
 332         .m2 = { .min = 11, .max = 156 },
 333         .p = { .min = 10, .max = 30 },
 334         .p1 = { .min = 2, .max = 3 },
 335         .p2 = { .dot_limit = 270000,
 336                 .p2_slow = 2, .p2_fast = 20 },
 337 };
 338
 339 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 340                                                 int refclk)
 341 {
 342         struct drm_device *dev = crtc->dev;
 343         const intel_limit_t *limit;
 344
 345         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 346                 if (intel_is_dual_link_lvds(dev)) {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_dual_lvds;
 351                 } else {
 352                         if (refclk == 100000)
 353                                 limit = &intel_limits_ironlake_single_lvds_100m;
 354                         else
 355                                 limit = &intel_limits_ironlake_single_lvds;
 356                 }
 357         } else
 358                 limit = &intel_limits_ironlake_dac;
 359
 360         return limit;
 361 }
 362
 363 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 364 {
 365         struct drm_device *dev = crtc->dev;
 366         const intel_limit_t *limit;
 367
 368         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 369                 if (intel_is_dual_link_lvds(dev))
 370                         limit = &intel_limits_g4x_dual_channel_lvds;
 371                 else
 372                         limit = &intel_limits_g4x_single_channel_lvds;
 373         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 374                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 375                 limit = &intel_limits_g4x_hdmi;
 376         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 377                 limit = &intel_limits_g4x_sdvo;
 378         } else /* The option is for other outputs */
 379                 limit = &intel_limits_i9xx_sdvo;
 380
 381         return limit;
 382 }
 383
 384 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 385 {
 386         struct drm_device *dev = crtc->dev;
 387         const intel_limit_t *limit;
 388
 389         if (HAS_PCH_SPLIT(dev))
 390                 limit = intel_ironlake_limit(crtc, refclk);
 391         else if (IS_G4X(dev)) {
 392                 limit = intel_g4x_limit(crtc);
 393         } else if (IS_PINEVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 395                         limit = &intel_limits_pineview_lvds;
 396                 else
 397                         limit = &intel_limits_pineview_sdvo;
 398         } else if (IS_VALLEYVIEW(dev)) {
 399                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 400                         limit = &intel_limits_vlv_dac;
 401                 else
 402                         limit = &intel_limits_vlv_hdmi;
 403         } else if (!IS_GEN2(dev)) {
 404                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 405                         limit = &intel_limits_i9xx_lvds;
 406                 else
 407                         limit = &intel_limits_i9xx_sdvo;
 408         } else {
 409                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 410                         limit = &intel_limits_i8xx_lvds;
 411                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 412                         limit = &intel_limits_i8xx_dvo;
 413                 else
 414                         limit = &intel_limits_i8xx_dac;
 415         }
 416         return limit;
 417 }
 418
 419 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 420 static void pineview_clock(int refclk, intel_clock_t *clock)
 421 {
 422         clock->m = clock->m2 + 2;
 423         clock->p = clock->p1 * clock->p2;
 424         clock->vco = refclk * clock->m / clock->n;
 425         clock->dot = clock->vco / clock->p;
 426 }
 427
 428 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 429 {
 430         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 431 }
 432
 433 static void i9xx_clock(int refclk, intel_clock_t *clock)
 434 {
 435         clock->m = i9xx_dpll_compute_m(clock);
 436         clock->p = clock->p1 * clock->p2;
 437         clock->vco = refclk * clock->m / (clock->n + 2);
 438         clock->dot = clock->vco / clock->p;
 439 }
 440
 441 /**
 442  * Returns whether any output on the specified pipe is of the specified type
 443  */
 444 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 445 {
 446         struct drm_device *dev = crtc->dev;
 447         struct intel_encoder *encoder;
 448
 449         for_each_encoder_on_crtc(dev, crtc, encoder)
 450                 if (encoder->type == type)
 451                         return true;
 452
 453         return false;
 454 }
 455
 456 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 457 /**
 458  * Returns whether the given set of divisors are valid for a given refclk with
 459  * the given connectors.
 460  */
 461
 462 static bool intel_PLL_is_valid(struct drm_device *dev,
 463                                const intel_limit_t *limit,
 464                                const intel_clock_t *clock)
 465 {
 466         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 467                 INTELPllInvalid("p1 out of range\n");
 468         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 469                 INTELPllInvalid("p out of range\n");
 470         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 471                 INTELPllInvalid("m2 out of range\n");
 472         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 473                 INTELPllInvalid("m1 out of range\n");
 474         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 475                 INTELPllInvalid("m1 <= m2\n");
 476         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 477                 INTELPllInvalid("m out of range\n");
 478         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 479                 INTELPllInvalid("n out of range\n");
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 674         u32 m, n, fastclk;
 675         u32 updrate, minupdate, p;
 676         unsigned long bestppm, ppm, absppm;
 677         int dotclk, flag;
 678
 679         flag = 0;
 680         dotclk = target * 1000;
 681         bestppm = 1000000;
 682         ppm = absppm = 0;
 683         fastclk = dotclk / (2*100);
 684         updrate = 0;
 685         minupdate = 19200;
 686         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 687         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 688
 689         /* based on hardware requirement, prefer smaller n to precision */
 690         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 691                 updrate = refclk / n;
 692                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 693                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 694                                 if (p2 > 10)
 695                                         p2 = p2 - 1;
 696                                 p = p1 * p2;
 697                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 698                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 699                                         m2 = (((2*(fastclk * p * n / m1 )) +
 700                                                refclk) / (2*refclk));
 701                                         m = m1 * m2;
 702                                         vco = updrate * m;
 703                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 704                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 705                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 706                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 707                                                         bestppm = 0;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (absppm < bestppm - 10) {
 711                                                         bestppm = absppm;
 712                                                         flag = 1;
 713                                                 }
 714                                                 if (flag) {
 715                                                         bestn = n;
 716                                                         bestm1 = m1;
 717                                                         bestm2 = m2;
 718                                                         bestp1 = p1;
 719                                                         bestp2 = p2;
 720                                                         flag = 0;
 721                                                 }
 722                                         }
 723                                 }
 724                         }
 725                 }
 726         }
 727         best_clock->n = bestn;
 728         best_clock->m1 = bestm1;
 729         best_clock->m2 = bestm2;
 730         best_clock->p1 = bestp1;
 731         best_clock->p2 = bestp2;
 732
 733         return true;
 734 }
 735
 736 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 737                                              enum pipe pipe)
 738 {
 739         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 741
 742         return intel_crtc->config.cpu_transcoder;
 743 }
 744
 745 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 746 {
 747         struct drm_i915_private *dev_priv = dev->dev_private;
 748         u32 frame, frame_reg = PIPEFRAME(pipe);
 749
 750         frame = I915_READ(frame_reg);
 751
 752         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 753                 DRM_DEBUG_KMS("vblank wait timed out\n");
 754 }
 755
 756 /**
 757  * intel_wait_for_vblank - wait for vblank on a given pipe
 758  * @dev: drm device
 759  * @pipe: pipe to wait for
 760  *
 761  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 762  * mode setting code.
 763  */
 764 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 765 {
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         int pipestat_reg = PIPESTAT(pipe);
 768
 769         if (INTEL_INFO(dev)->gen >= 5) {
 770                 ironlake_wait_for_vblank(dev, pipe);
 771                 return;
 772         }
 773
 774         /* Clear existing vblank status. Note this will clear any other
 775          * sticky status fields as well.
 776          *
 777          * This races with i915_driver_irq_handler() with the result
 778          * that either function could miss a vblank event.  Here it is not
 779          * fatal, as we will either wait upon the next vblank interrupt or
 780          * timeout.  Generally speaking intel_wait_for_vblank() is only
 781          * called during modeset at which time the GPU should be idle and
 782          * should *not* be performing page flips and thus not waiting on
 783          * vblanks...
 784          * Currently, the result of us stealing a vblank from the irq
 785          * handler is that a single frame will be skipped during swapbuffers.
 786          */
 787         I915_WRITE(pipestat_reg,
 788                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 789
 790         /* Wait for vblank interrupt bit to set */
 791         if (wait_for(I915_READ(pipestat_reg) &
 792                      PIPE_VBLANK_INTERRUPT_STATUS,
 793                      50))
 794                 DRM_DEBUG_KMS("vblank wait timed out\n");
 795 }
 796
 797 /*
 798  * intel_wait_for_pipe_off - wait for pipe to turn off
 799  * @dev: drm device
 800  * @pipe: pipe to wait for
 801  *
 802  * After disabling a pipe, we can't wait for vblank in the usual way,
 803  * spinning on the vblank interrupt status bit, since we won't actually
 804  * see an interrupt when the pipe is disabled.
 805  *
 806  * On Gen4 and above:
 807  *   wait for the pipe register state bit to turn off
 808  *
 809  * Otherwise:
 810  *   wait for the display line value to settle (it usually
 811  *   ends up stopping at the start of the next frame).
 812  *
 813  */
 814 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 818                                                                       pipe);
 819
 820         if (INTEL_INFO(dev)->gen >= 4) {
 821                 int reg = PIPECONF(cpu_transcoder);
 822
 823                 /* Wait for the Pipe State to go off */
 824                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 825                              100))
 826                         WARN(1, "pipe_off wait timed out\n");
 827         } else {
 828                 u32 last_line, line_mask;
 829                 int reg = PIPEDSL(pipe);
 830                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 831
 832                 if (IS_GEN2(dev))
 833                         line_mask = DSL_LINEMASK_GEN2;
 834                 else
 835                         line_mask = DSL_LINEMASK_GEN3;
 836
 837                 /* Wait for the display line to settle */
 838                 do {
 839                         last_line = I915_READ(reg) & line_mask;
 840                         mdelay(5);
 841                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 842                          time_after(timeout, jiffies));
 843                 if (time_after(jiffies, timeout))
 844                         WARN(1, "pipe_off wait timed out\n");
 845         }
 846 }
 847
 848 /*
 849  * ibx_digital_port_connected - is the specified port connected?
 850  * @dev_priv: i915 private structure
 851  * @port: the port to test
 852  *
 853  * Returns true if @port is connected, false otherwise.
 854  */
 855 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 856                                 struct intel_digital_port *port)
 857 {
 858         u32 bit;
 859
 860         if (HAS_PCH_IBX(dev_priv->dev)) {
 861                 switch(port->port) {
 862                 case PORT_B:
 863                         bit = SDE_PORTB_HOTPLUG;
 864                         break;
 865                 case PORT_C:
 866                         bit = SDE_PORTC_HOTPLUG;
 867                         break;
 868                 case PORT_D:
 869                         bit = SDE_PORTD_HOTPLUG;
 870                         break;
 871                 default:
 872                         return true;
 873                 }
 874         } else {
 875                 switch(port->port) {
 876                 case PORT_B:
 877                         bit = SDE_PORTB_HOTPLUG_CPT;
 878                         break;
 879                 case PORT_C:
 880                         bit = SDE_PORTC_HOTPLUG_CPT;
 881                         break;
 882                 case PORT_D:
 883                         bit = SDE_PORTD_HOTPLUG_CPT;
 884                         break;
 885                 default:
 886                         return true;
 887                 }
 888         }
 889
 890         return I915_READ(SDEISR) & bit;
 891 }
 892
 893 static const char *state_string(bool enabled)
 894 {
 895         return enabled ? "on" : "off";
 896 }
 897
 898 /* Only for pre-ILK configs */
 899 void assert_pll(struct drm_i915_private *dev_priv,
 900                 enum pipe pipe, bool state)
 901 {
 902         int reg;
 903         u32 val;
 904         bool cur_state;
 905
 906         reg = DPLL(pipe);
 907         val = I915_READ(reg);
 908         cur_state = !!(val & DPLL_VCO_ENABLE);
 909         WARN(cur_state != state,
 910              "PLL state assertion failure (expected %s, current %s)\n",
 911              state_string(state), state_string(cur_state));
 912 }
 913
 914 /* XXX: the dsi pll is shared between MIPI DSI ports */
 915 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 916 {
 917         u32 val;
 918         bool cur_state;
 919
 920         mutex_lock(&dev_priv->dpio_lock);
 921         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 922         mutex_unlock(&dev_priv->dpio_lock);
 923
 924         cur_state = val & DSI_PLL_VCO_EN;
 925         WARN(cur_state != state,
 926              "DSI PLL state assertion failure (expected %s, current %s)\n",
 927              state_string(state), state_string(cur_state));
 928 }
 929 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 930 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 931
 932 struct intel_shared_dpll *
 933 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 934 {
 935         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 936
 937         if (crtc->config.shared_dpll < 0)
 938                 return NULL;
 939
 940         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 941 }
 942
 943 /* For ILK+ */
 944 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 945                         struct intel_shared_dpll *pll,
 946                         bool state)
 947 {
 948         bool cur_state;
 949         struct intel_dpll_hw_state hw_state;
 950
 951         if (HAS_PCH_LPT(dev_priv->dev)) {
 952                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 953                 return;
 954         }
 955
 956         if (WARN (!pll,
 957                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 958                 return;
 959
 960         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 961         WARN(cur_state != state,
 962              "%s assertion failure (expected %s, current %s)\n",
 963              pll->name, state_string(state), state_string(cur_state));
 964 }
 965
 966 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 967                           enum pipe pipe, bool state)
 968 {
 969         int reg;
 970         u32 val;
 971         bool cur_state;
 972         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 973                                                                       pipe);
 974
 975         if (HAS_DDI(dev_priv->dev)) {
 976                 /* DDI does not have a specific FDI_TX register */
 977                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 978                 val = I915_READ(reg);
 979                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 980         } else {
 981                 reg = FDI_TX_CTL(pipe);
 982                 val = I915_READ(reg);
 983                 cur_state = !!(val & FDI_TX_ENABLE);
 984         }
 985         WARN(cur_state != state,
 986              "FDI TX state assertion failure (expected %s, current %s)\n",
 987              state_string(state), state_string(cur_state));
 988 }
 989 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 990 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 991
 992 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 993                           enum pipe pipe, bool state)
 994 {
 995         int reg;
 996         u32 val;
 997         bool cur_state;
 998
 999         reg = FDI_RX_CTL(pipe);
1000         val = I915_READ(reg);
1001         cur_state = !!(val & FDI_RX_ENABLE);
1002         WARN(cur_state != state,
1003              "FDI RX state assertion failure (expected %s, current %s)\n",
1004              state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010                                       enum pipe pipe)
1011 {
1012         int reg;
1013         u32 val;
1014
1015         /* ILK FDI PLL is always enabled */
1016         if (dev_priv->info->gen == 5)
1017                 return;
1018
1019         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1020         if (HAS_DDI(dev_priv->dev))
1021                 return;
1022
1023         reg = FDI_TX_CTL(pipe);
1024         val = I915_READ(reg);
1025         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026 }
1027
1028 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029                        enum pipe pipe, bool state)
1030 {
1031         int reg;
1032         u32 val;
1033         bool cur_state;
1034
1035         reg = FDI_RX_CTL(pipe);
1036         val = I915_READ(reg);
1037         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038         WARN(cur_state != state,
1039              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040              state_string(state), state_string(cur_state));
1041 }
1042
1043 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044                                   enum pipe pipe)
1045 {
1046         int pp_reg, lvds_reg;
1047         u32 val;
1048         enum pipe panel_pipe = PIPE_A;
1049         bool locked = true;
1050
1051         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052                 pp_reg = PCH_PP_CONTROL;
1053                 lvds_reg = PCH_LVDS;
1054         } else {
1055                 pp_reg = PP_CONTROL;
1056                 lvds_reg = LVDS;
1057         }
1058
1059         val = I915_READ(pp_reg);
1060         if (!(val & PANEL_POWER_ON) ||
1061             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062                 locked = false;
1063
1064         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065                 panel_pipe = PIPE_B;
1066
1067         WARN(panel_pipe == pipe && locked,
1068              "panel assertion failure, pipe %c regs locked\n",
1069              pipe_name(pipe));
1070 }
1071
1072 static void assert_cursor(struct drm_i915_private *dev_priv,
1073                           enum pipe pipe, bool state)
1074 {
1075         struct drm_device *dev = dev_priv->dev;
1076         bool cur_state;
1077
1078         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1079                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1080         else if (IS_845G(dev) || IS_I865G(dev))
1081                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1082         else
1083                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1084
1085         WARN(cur_state != state,
1086              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1087              pipe_name(pipe), state_string(state), state_string(cur_state));
1088 }
1089 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1090 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1091
1092 void assert_pipe(struct drm_i915_private *dev_priv,
1093                  enum pipe pipe, bool state)
1094 {
1095         int reg;
1096         u32 val;
1097         bool cur_state;
1098         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1099                                                                       pipe);
1100
1101         /* if we need the pipe A quirk it must be always on */
1102         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1103                 state = true;
1104
1105         if (!intel_display_power_enabled(dev_priv->dev,
1106                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1107                 cur_state = false;
1108         } else {
1109                 reg = PIPECONF(cpu_transcoder);
1110                 val = I915_READ(reg);
1111                 cur_state = !!(val & PIPECONF_ENABLE);
1112         }
1113
1114         WARN(cur_state != state,
1115              "pipe %c assertion failure (expected %s, current %s)\n",
1116              pipe_name(pipe), state_string(state), state_string(cur_state));
1117 }
1118
1119 static void assert_plane(struct drm_i915_private *dev_priv,
1120                          enum plane plane, bool state)
1121 {
1122         int reg;
1123         u32 val;
1124         bool cur_state;
1125
1126         reg = DSPCNTR(plane);
1127         val = I915_READ(reg);
1128         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1129         WARN(cur_state != state,
1130              "plane %c assertion failure (expected %s, current %s)\n",
1131              plane_name(plane), state_string(state), state_string(cur_state));
1132 }
1133
1134 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1135 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1136
1137 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1138                                    enum pipe pipe)
1139 {
1140         struct drm_device *dev = dev_priv->dev;
1141         int reg, i;
1142         u32 val;
1143         int cur_pipe;
1144
1145         /* Primary planes are fixed to pipes on gen4+ */
1146         if (INTEL_INFO(dev)->gen >= 4) {
1147                 reg = DSPCNTR(pipe);
1148                 val = I915_READ(reg);
1149                 WARN((val & DISPLAY_PLANE_ENABLE),
1150                      "plane %c assertion failure, should be disabled but not\n",
1151                      plane_name(pipe));
1152                 return;
1153         }
1154
1155         /* Need to check both planes against the pipe */
1156         for_each_pipe(i) {
1157                 reg = DSPCNTR(i);
1158                 val = I915_READ(reg);
1159                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1160                         DISPPLANE_SEL_PIPE_SHIFT;
1161                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1162                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1163                      plane_name(i), pipe_name(pipe));
1164         }
1165 }
1166
1167 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1168                                     enum pipe pipe)
1169 {
1170         struct drm_device *dev = dev_priv->dev;
1171         int reg, i;
1172         u32 val;
1173
1174         if (IS_VALLEYVIEW(dev)) {
1175                 for (i = 0; i < dev_priv->num_plane; i++) {
1176                         reg = SPCNTR(pipe, i);
1177                         val = I915_READ(reg);
1178                         WARN((val & SP_ENABLE),
1179                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1180                              sprite_name(pipe, i), pipe_name(pipe));
1181                 }
1182         } else if (INTEL_INFO(dev)->gen >= 7) {
1183                 reg = SPRCTL(pipe);
1184                 val = I915_READ(reg);
1185                 WARN((val & SPRITE_ENABLE),
1186                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1187                      plane_name(pipe), pipe_name(pipe));
1188         } else if (INTEL_INFO(dev)->gen >= 5) {
1189                 reg = DVSCNTR(pipe);
1190                 val = I915_READ(reg);
1191                 WARN((val & DVS_ENABLE),
1192                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1193                      plane_name(pipe), pipe_name(pipe));
1194         }
1195 }
1196
1197 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1198 {
1199         u32 val;
1200         bool enabled;
1201
1202         if (HAS_PCH_LPT(dev_priv->dev)) {
1203                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1204                 return;
1205         }
1206
1207         val = I915_READ(PCH_DREF_CONTROL);
1208         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1209                             DREF_SUPERSPREAD_SOURCE_MASK));
1210         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1211 }
1212
1213 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1214                                            enum pipe pipe)
1215 {
1216         int reg;
1217         u32 val;
1218         bool enabled;
1219
1220         reg = PCH_TRANSCONF(pipe);
1221         val = I915_READ(reg);
1222         enabled = !!(val & TRANS_ENABLE);
1223         WARN(enabled,
1224              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1225              pipe_name(pipe));
1226 }
1227
1228 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1229                             enum pipe pipe, u32 port_sel, u32 val)
1230 {
1231         if ((val & DP_PORT_EN) == 0)
1232                 return false;
1233
1234         if (HAS_PCH_CPT(dev_priv->dev)) {
1235                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1236                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1237                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1238                         return false;
1239         } else {
1240                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1241                         return false;
1242         }
1243         return true;
1244 }
1245
1246 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1247                               enum pipe pipe, u32 val)
1248 {
1249         if ((val & SDVO_ENABLE) == 0)
1250                 return false;
1251
1252         if (HAS_PCH_CPT(dev_priv->dev)) {
1253                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1254                         return false;
1255         } else {
1256                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1257                         return false;
1258         }
1259         return true;
1260 }
1261
1262 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1263                               enum pipe pipe, u32 val)
1264 {
1265         if ((val & LVDS_PORT_EN) == 0)
1266                 return false;
1267
1268         if (HAS_PCH_CPT(dev_priv->dev)) {
1269                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1270                         return false;
1271         } else {
1272                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1273                         return false;
1274         }
1275         return true;
1276 }
1277
1278 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1279                               enum pipe pipe, u32 val)
1280 {
1281         if ((val & ADPA_DAC_ENABLE) == 0)
1282                 return false;
1283         if (HAS_PCH_CPT(dev_priv->dev)) {
1284                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1285                         return false;
1286         } else {
1287                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1288                         return false;
1289         }
1290         return true;
1291 }
1292
1293 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1294                                    enum pipe pipe, int reg, u32 port_sel)
1295 {
1296         u32 val = I915_READ(reg);
1297         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1298              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1299              reg, pipe_name(pipe));
1300
1301         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1302              && (val & DP_PIPEB_SELECT),
1303              "IBX PCH dp port still using transcoder B\n");
1304 }
1305
1306 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1307                                      enum pipe pipe, int reg)
1308 {
1309         u32 val = I915_READ(reg);
1310         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1311              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1312              reg, pipe_name(pipe));
1313
1314         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1315              && (val & SDVO_PIPE_B_SELECT),
1316              "IBX PCH hdmi port still using transcoder B\n");
1317 }
1318
1319 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1320                                       enum pipe pipe)
1321 {
1322         int reg;
1323         u32 val;
1324
1325         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1326         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1327         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1328
1329         reg = PCH_ADPA;
1330         val = I915_READ(reg);
1331         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1332              "PCH VGA enabled on transcoder %c, should be disabled\n",
1333              pipe_name(pipe));
1334
1335         reg = PCH_LVDS;
1336         val = I915_READ(reg);
1337         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1338              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1339              pipe_name(pipe));
1340
1341         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1342         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1343         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1344 }
1345
1346 static void vlv_enable_pll(struct intel_crtc *crtc)
1347 {
1348         struct drm_device *dev = crtc->base.dev;
1349         struct drm_i915_private *dev_priv = dev->dev_private;
1350         int reg = DPLL(crtc->pipe);
1351         u32 dpll = crtc->config.dpll_hw_state.dpll;
1352
1353         assert_pipe_disabled(dev_priv, crtc->pipe);
1354
1355         /* No really, not for ILK+ */
1356         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1357
1358         /* PLL is protected by panel, make sure we can write it */
1359         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1360                 assert_panel_unlocked(dev_priv, crtc->pipe);
1361
1362         I915_WRITE(reg, dpll);
1363         POSTING_READ(reg);
1364         udelay(150);
1365
1366         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1367                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1368
1369         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1370         POSTING_READ(DPLL_MD(crtc->pipe));
1371
1372         /* We do this three times for luck */
1373         I915_WRITE(reg, dpll);
1374         POSTING_READ(reg);
1375         udelay(150); /* wait for warmup */
1376         I915_WRITE(reg, dpll);
1377         POSTING_READ(reg);
1378         udelay(150); /* wait for warmup */
1379         I915_WRITE(reg, dpll);
1380         POSTING_READ(reg);
1381         udelay(150); /* wait for warmup */
1382 }
1383
1384 static void i9xx_enable_pll(struct intel_crtc *crtc)
1385 {
1386         struct drm_device *dev = crtc->base.dev;
1387         struct drm_i915_private *dev_priv = dev->dev_private;
1388         int reg = DPLL(crtc->pipe);
1389         u32 dpll = crtc->config.dpll_hw_state.dpll;
1390
1391         assert_pipe_disabled(dev_priv, crtc->pipe);
1392
1393         /* No really, not for ILK+ */
1394         BUG_ON(dev_priv->info->gen >= 5);
1395
1396         /* PLL is protected by panel, make sure we can write it */
1397         if (IS_MOBILE(dev) && !IS_I830(dev))
1398                 assert_panel_unlocked(dev_priv, crtc->pipe);
1399
1400         I915_WRITE(reg, dpll);
1401
1402         /* Wait for the clocks to stabilize. */
1403         POSTING_READ(reg);
1404         udelay(150);
1405
1406         if (INTEL_INFO(dev)->gen >= 4) {
1407                 I915_WRITE(DPLL_MD(crtc->pipe),
1408                            crtc->config.dpll_hw_state.dpll_md);
1409         } else {
1410                 /* The pixel multiplier can only be updated once the
1411                  * DPLL is enabled and the clocks are stable.
1412                  *
1413                  * So write it again.
1414                  */
1415                 I915_WRITE(reg, dpll);
1416         }
1417
1418         /* We do this three times for luck */
1419         I915_WRITE(reg, dpll);
1420         POSTING_READ(reg);
1421         udelay(150); /* wait for warmup */
1422         I915_WRITE(reg, dpll);
1423         POSTING_READ(reg);
1424         udelay(150); /* wait for warmup */
1425         I915_WRITE(reg, dpll);
1426         POSTING_READ(reg);
1427         udelay(150); /* wait for warmup */
1428 }
1429
1430 /**
1431  * i9xx_disable_pll - disable a PLL
1432  * @dev_priv: i915 private structure
1433  * @pipe: pipe PLL to disable
1434  *
1435  * Disable the PLL for @pipe, making sure the pipe is off first.
1436  *
1437  * Note!  This is for pre-ILK only.
1438  */
1439 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1440 {
1441         /* Don't disable pipe A or pipe A PLLs if needed */
1442         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1443                 return;
1444
1445         /* Make sure the pipe isn't still relying on us */
1446         assert_pipe_disabled(dev_priv, pipe);
1447
1448         I915_WRITE(DPLL(pipe), 0);
1449         POSTING_READ(DPLL(pipe));
1450 }
1451
1452 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1453 {
1454         u32 port_mask;
1455
1456         if (!port)
1457                 port_mask = DPLL_PORTB_READY_MASK;
1458         else
1459                 port_mask = DPLL_PORTC_READY_MASK;
1460
1461         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1462                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1463                      'B' + port, I915_READ(DPLL(0)));
1464 }
1465
1466 /**
1467  * ironlake_enable_shared_dpll - enable PCH PLL
1468  * @dev_priv: i915 private structure
1469  * @pipe: pipe PLL to enable
1470  *
1471  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1472  * drives the transcoder clock.
1473  */
1474 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1475 {
1476         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1477         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1478
1479         /* PCH PLLs only available on ILK, SNB and IVB */
1480         BUG_ON(dev_priv->info->gen < 5);
1481         if (WARN_ON(pll == NULL))
1482                 return;
1483
1484         if (WARN_ON(pll->refcount == 0))
1485                 return;
1486
1487         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1488                       pll->name, pll->active, pll->on,
1489                       crtc->base.base.id);
1490
1491         if (pll->active++) {
1492                 WARN_ON(!pll->on);
1493                 assert_shared_dpll_enabled(dev_priv, pll);
1494                 return;
1495         }
1496         WARN_ON(pll->on);
1497
1498         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1499         pll->enable(dev_priv, pll);
1500         pll->on = true;
1501 }
1502
1503 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1504 {
1505         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1506         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1507
1508         /* PCH only available on ILK+ */
1509         BUG_ON(dev_priv->info->gen < 5);
1510         if (WARN_ON(pll == NULL))
1511                return;
1512
1513         if (WARN_ON(pll->refcount == 0))
1514                 return;
1515
1516         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1517                       pll->name, pll->active, pll->on,
1518                       crtc->base.base.id);
1519
1520         if (WARN_ON(pll->active == 0)) {
1521                 assert_shared_dpll_disabled(dev_priv, pll);
1522                 return;
1523         }
1524
1525         assert_shared_dpll_enabled(dev_priv, pll);
1526         WARN_ON(!pll->on);
1527         if (--pll->active)
1528                 return;
1529
1530         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1531         pll->disable(dev_priv, pll);
1532         pll->on = false;
1533 }
1534
1535 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1536                                            enum pipe pipe)
1537 {
1538         struct drm_device *dev = dev_priv->dev;
1539         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1541         uint32_t reg, val, pipeconf_val;
1542
1543         /* PCH only available on ILK+ */
1544         BUG_ON(dev_priv->info->gen < 5);
1545
1546         /* Make sure PCH DPLL is enabled */
1547         assert_shared_dpll_enabled(dev_priv,
1548                                    intel_crtc_to_shared_dpll(intel_crtc));
1549
1550         /* FDI must be feeding us bits for PCH ports */
1551         assert_fdi_tx_enabled(dev_priv, pipe);
1552         assert_fdi_rx_enabled(dev_priv, pipe);
1553
1554         if (HAS_PCH_CPT(dev)) {
1555                 /* Workaround: Set the timing override bit before enabling the
1556                  * pch transcoder. */
1557                 reg = TRANS_CHICKEN2(pipe);
1558                 val = I915_READ(reg);
1559                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1560                 I915_WRITE(reg, val);
1561         }
1562
1563         reg = PCH_TRANSCONF(pipe);
1564         val = I915_READ(reg);
1565         pipeconf_val = I915_READ(PIPECONF(pipe));
1566
1567         if (HAS_PCH_IBX(dev_priv->dev)) {
1568                 /*
1569                  * make the BPC in transcoder be consistent with
1570                  * that in pipeconf reg.
1571                  */
1572                 val &= ~PIPECONF_BPC_MASK;
1573                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1574         }
1575
1576         val &= ~TRANS_INTERLACE_MASK;
1577         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1578                 if (HAS_PCH_IBX(dev_priv->dev) &&
1579                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1580                         val |= TRANS_LEGACY_INTERLACED_ILK;
1581                 else
1582                         val |= TRANS_INTERLACED;
1583         else
1584                 val |= TRANS_PROGRESSIVE;
1585
1586         I915_WRITE(reg, val | TRANS_ENABLE);
1587         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1588                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1589 }
1590
1591 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1592                                       enum transcoder cpu_transcoder)
1593 {
1594         u32 val, pipeconf_val;
1595
1596         /* PCH only available on ILK+ */
1597         BUG_ON(dev_priv->info->gen < 5);
1598
1599         /* FDI must be feeding us bits for PCH ports */
1600         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1601         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1602
1603         /* Workaround: set timing override bit. */
1604         val = I915_READ(_TRANSA_CHICKEN2);
1605         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1606         I915_WRITE(_TRANSA_CHICKEN2, val);
1607
1608         val = TRANS_ENABLE;
1609         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1610
1611         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1612             PIPECONF_INTERLACED_ILK)
1613                 val |= TRANS_INTERLACED;
1614         else
1615                 val |= TRANS_PROGRESSIVE;
1616
1617         I915_WRITE(LPT_TRANSCONF, val);
1618         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1619                 DRM_ERROR("Failed to enable PCH transcoder\n");
1620 }
1621
1622 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1623                                             enum pipe pipe)
1624 {
1625         struct drm_device *dev = dev_priv->dev;
1626         uint32_t reg, val;
1627
1628         /* FDI relies on the transcoder */
1629         assert_fdi_tx_disabled(dev_priv, pipe);
1630         assert_fdi_rx_disabled(dev_priv, pipe);
1631
1632         /* Ports must be off as well */
1633         assert_pch_ports_disabled(dev_priv, pipe);
1634
1635         reg = PCH_TRANSCONF(pipe);
1636         val = I915_READ(reg);
1637         val &= ~TRANS_ENABLE;
1638         I915_WRITE(reg, val);
1639         /* wait for PCH transcoder off, transcoder state */
1640         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1641                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1642
1643         if (!HAS_PCH_IBX(dev)) {
1644                 /* Workaround: Clear the timing override chicken bit again. */
1645                 reg = TRANS_CHICKEN2(pipe);
1646                 val = I915_READ(reg);
1647                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1648                 I915_WRITE(reg, val);
1649         }
1650 }
1651
1652 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1653 {
1654         u32 val;
1655
1656         val = I915_READ(LPT_TRANSCONF);
1657         val &= ~TRANS_ENABLE;
1658         I915_WRITE(LPT_TRANSCONF, val);
1659         /* wait for PCH transcoder off, transcoder state */
1660         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1661                 DRM_ERROR("Failed to disable PCH transcoder\n");
1662
1663         /* Workaround: clear timing override bit. */
1664         val = I915_READ(_TRANSA_CHICKEN2);
1665         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1666         I915_WRITE(_TRANSA_CHICKEN2, val);
1667 }
1668
1669 /**
1670  * intel_enable_pipe - enable a pipe, asserting requirements
1671  * @dev_priv: i915 private structure
1672  * @pipe: pipe to enable
1673  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1674  *
1675  * Enable @pipe, making sure that various hardware specific requirements
1676  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1677  *
1678  * @pipe should be %PIPE_A or %PIPE_B.
1679  *
1680  * Will wait until the pipe is actually running (i.e. first vblank) before
1681  * returning.
1682  */
1683 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1684                               bool pch_port, bool dsi)
1685 {
1686         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1687                                                                       pipe);
1688         enum pipe pch_transcoder;
1689         int reg;
1690         u32 val;
1691
1692         assert_planes_disabled(dev_priv, pipe);
1693         assert_cursor_disabled(dev_priv, pipe);
1694         assert_sprites_disabled(dev_priv, pipe);
1695
1696         if (HAS_PCH_LPT(dev_priv->dev))
1697                 pch_transcoder = TRANSCODER_A;
1698         else
1699                 pch_transcoder = pipe;
1700
1701         /*
1702          * A pipe without a PLL won't actually be able to drive bits from
1703          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1704          * need the check.
1705          */
1706         if (!HAS_PCH_SPLIT(dev_priv->dev))
1707                 if (dsi)
1708                         assert_dsi_pll_enabled(dev_priv);
1709                 else
1710                         assert_pll_enabled(dev_priv, pipe);
1711         else {
1712                 if (pch_port) {
1713                         /* if driving the PCH, we need FDI enabled */
1714                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1715                         assert_fdi_tx_pll_enabled(dev_priv,
1716                                                   (enum pipe) cpu_transcoder);
1717                 }
1718                 /* FIXME: assert CPU port conditions for SNB+ */
1719         }
1720
1721         reg = PIPECONF(cpu_transcoder);
1722         val = I915_READ(reg);
1723         if (val & PIPECONF_ENABLE)
1724                 return;
1725
1726         I915_WRITE(reg, val | PIPECONF_ENABLE);
1727         intel_wait_for_vblank(dev_priv->dev, pipe);
1728 }
1729
1730 /**
1731  * intel_disable_pipe - disable a pipe, asserting requirements
1732  * @dev_priv: i915 private structure
1733  * @pipe: pipe to disable
1734  *
1735  * Disable @pipe, making sure that various hardware specific requirements
1736  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1737  *
1738  * @pipe should be %PIPE_A or %PIPE_B.
1739  *
1740  * Will wait until the pipe has shut down before returning.
1741  */
1742 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1743                                enum pipe pipe)
1744 {
1745         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1746                                                                       pipe);
1747         int reg;
1748         u32 val;
1749
1750         /*
1751          * Make sure planes won't keep trying to pump pixels to us,
1752          * or we might hang the display.
1753          */
1754         assert_planes_disabled(dev_priv, pipe);
1755         assert_cursor_disabled(dev_priv, pipe);
1756         assert_sprites_disabled(dev_priv, pipe);
1757
1758         /* Don't disable pipe A or pipe A PLLs if needed */
1759         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1760                 return;
1761
1762         reg = PIPECONF(cpu_transcoder);
1763         val = I915_READ(reg);
1764         if ((val & PIPECONF_ENABLE) == 0)
1765                 return;
1766
1767         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1768         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1769 }
1770
1771 /*
1772  * Plane regs are double buffered, going from enabled->disabled needs a
1773  * trigger in order to latch.  The display address reg provides this.
1774  */
1775 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1776                                       enum plane plane)
1777 {
1778         if (dev_priv->info->gen >= 4)
1779                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1780         else
1781                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1782 }
1783
1784 /**
1785  * intel_enable_plane - enable a display plane on a given pipe
1786  * @dev_priv: i915 private structure
1787  * @plane: plane to enable
1788  * @pipe: pipe being fed
1789  *
1790  * Enable @plane on @pipe, making sure that @pipe is running first.
1791  */
1792 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1793                                enum plane plane, enum pipe pipe)
1794 {
1795         int reg;
1796         u32 val;
1797
1798         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1799         assert_pipe_enabled(dev_priv, pipe);
1800
1801         reg = DSPCNTR(plane);
1802         val = I915_READ(reg);
1803         if (val & DISPLAY_PLANE_ENABLE)
1804                 return;
1805
1806         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1807         intel_flush_display_plane(dev_priv, plane);
1808         intel_wait_for_vblank(dev_priv->dev, pipe);
1809 }
1810
1811 /**
1812  * intel_disable_plane - disable a display plane
1813  * @dev_priv: i915 private structure
1814  * @plane: plane to disable
1815  * @pipe: pipe consuming the data
1816  *
1817  * Disable @plane; should be an independent operation.
1818  */
1819 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1820                                 enum plane plane, enum pipe pipe)
1821 {
1822         int reg;
1823         u32 val;
1824
1825         reg = DSPCNTR(plane);
1826         val = I915_READ(reg);
1827         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1828                 return;
1829
1830         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1831         intel_flush_display_plane(dev_priv, plane);
1832         intel_wait_for_vblank(dev_priv->dev, pipe);
1833 }
1834
1835 static bool need_vtd_wa(struct drm_device *dev)
1836 {
1837 #ifdef CONFIG_INTEL_IOMMU
1838         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1839                 return true;
1840 #endif
1841         return false;
1842 }
1843
1844 int
1845 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1846                            struct drm_i915_gem_object *obj,
1847                            struct intel_ring_buffer *pipelined)
1848 {
1849         struct drm_i915_private *dev_priv = dev->dev_private;
1850         u32 alignment;
1851         int ret;
1852
1853         switch (obj->tiling_mode) {
1854         case I915_TILING_NONE:
1855                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1856                         alignment = 128 * 1024;
1857                 else if (INTEL_INFO(dev)->gen >= 4)
1858                         alignment = 4 * 1024;
1859                 else
1860                         alignment = 64 * 1024;
1861                 break;
1862         case I915_TILING_X:
1863                 /* pin() will align the object as required by fence */
1864                 alignment = 0;
1865                 break;
1866         case I915_TILING_Y:
1867                 /* Despite that we check this in framebuffer_init userspace can
1868                  * screw us over and change the tiling after the fact. Only
1869                  * pinned buffers can't change their tiling. */
1870                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1871                 return -EINVAL;
1872         default:
1873                 BUG();
1874         }
1875
1876         /* Note that the w/a also requires 64 PTE of padding following the
1877          * bo. We currently fill all unused PTE with the shadow page and so
1878          * we should always have valid PTE following the scanout preventing
1879          * the VT-d warning.
1880          */
1881         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1882                 alignment = 256 * 1024;
1883
1884         dev_priv->mm.interruptible = false;
1885         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1886         if (ret)
1887                 goto err_interruptible;
1888
1889         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1890          * fence, whereas 965+ only requires a fence if using
1891          * framebuffer compression.  For simplicity, we always install
1892          * a fence as the cost is not that onerous.
1893          */
1894         ret = i915_gem_object_get_fence(obj);
1895         if (ret)
1896                 goto err_unpin;
1897
1898         i915_gem_object_pin_fence(obj);
1899
1900         dev_priv->mm.interruptible = true;
1901         return 0;
1902
1903 err_unpin:
1904         i915_gem_object_unpin_from_display_plane(obj);
1905 err_interruptible:
1906         dev_priv->mm.interruptible = true;
1907         return ret;
1908 }
1909
1910 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1911 {
1912         i915_gem_object_unpin_fence(obj);
1913         i915_gem_object_unpin_from_display_plane(obj);
1914 }
1915
1916 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1917  * is assumed to be a power-of-two. */
1918 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1919                                              unsigned int tiling_mode,
1920                                              unsigned int cpp,
1921                                              unsigned int pitch)
1922 {
1923         if (tiling_mode != I915_TILING_NONE) {
1924                 unsigned int tile_rows, tiles;
1925
1926                 tile_rows = *y / 8;
1927                 *y %= 8;
1928
1929                 tiles = *x / (512/cpp);
1930                 *x %= 512/cpp;
1931
1932                 return tile_rows * pitch * 8 + tiles * 4096;
1933         } else {
1934                 unsigned int offset;
1935
1936                 offset = *y * pitch + *x * cpp;
1937                 *y = 0;
1938                 *x = (offset & 4095) / cpp;
1939                 return offset & -4096;
1940         }
1941 }
1942
1943 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944                              int x, int y)
1945 {
1946         struct drm_device *dev = crtc->dev;
1947         struct drm_i915_private *dev_priv = dev->dev_private;
1948         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949         struct intel_framebuffer *intel_fb;
1950         struct drm_i915_gem_object *obj;
1951         int plane = intel_crtc->plane;
1952         unsigned long linear_offset;
1953         u32 dspcntr;
1954         u32 reg;
1955
1956         switch (plane) {
1957         case 0:
1958         case 1:
1959                 break;
1960         default:
1961                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1962                 return -EINVAL;
1963         }
1964
1965         intel_fb = to_intel_framebuffer(fb);
1966         obj = intel_fb->obj;
1967
1968         reg = DSPCNTR(plane);
1969         dspcntr = I915_READ(reg);
1970         /* Mask out pixel format bits in case we change it */
1971         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1972         switch (fb->pixel_format) {
1973         case DRM_FORMAT_C8:
1974                 dspcntr |= DISPPLANE_8BPP;
1975                 break;
1976         case DRM_FORMAT_XRGB1555:
1977         case DRM_FORMAT_ARGB1555:
1978                 dspcntr |= DISPPLANE_BGRX555;
1979                 break;
1980         case DRM_FORMAT_RGB565:
1981                 dspcntr |= DISPPLANE_BGRX565;
1982                 break;
1983         case DRM_FORMAT_XRGB8888:
1984         case DRM_FORMAT_ARGB8888:
1985                 dspcntr |= DISPPLANE_BGRX888;
1986                 break;
1987         case DRM_FORMAT_XBGR8888:
1988         case DRM_FORMAT_ABGR8888:
1989                 dspcntr |= DISPPLANE_RGBX888;
1990                 break;
1991         case DRM_FORMAT_XRGB2101010:
1992         case DRM_FORMAT_ARGB2101010:
1993                 dspcntr |= DISPPLANE_BGRX101010;
1994                 break;
1995         case DRM_FORMAT_XBGR2101010:
1996         case DRM_FORMAT_ABGR2101010:
1997                 dspcntr |= DISPPLANE_RGBX101010;
1998                 break;
1999         default:
2000                 BUG();
2001         }
2002
2003         if (INTEL_INFO(dev)->gen >= 4) {
2004                 if (obj->tiling_mode != I915_TILING_NONE)
2005                         dspcntr |= DISPPLANE_TILED;
2006                 else
2007                         dspcntr &= ~DISPPLANE_TILED;
2008         }
2009
2010         if (IS_G4X(dev))
2011                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2012
2013         I915_WRITE(reg, dspcntr);
2014
2015         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2016
2017         if (INTEL_INFO(dev)->gen >= 4) {
2018                 intel_crtc->dspaddr_offset =
2019                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2020                                                        fb->bits_per_pixel / 8,
2021                                                        fb->pitches[0]);
2022                 linear_offset -= intel_crtc->dspaddr_offset;
2023         } else {
2024                 intel_crtc->dspaddr_offset = linear_offset;
2025         }
2026
2027         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2028                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2029                       fb->pitches[0]);
2030         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2031         if (INTEL_INFO(dev)->gen >= 4) {
2032                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2033                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2034                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2035                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2036         } else
2037                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2038         POSTING_READ(reg);
2039
2040         return 0;
2041 }
2042
2043 static int ironlake_update_plane(struct drm_crtc *crtc,
2044                                  struct drm_framebuffer *fb, int x, int y)
2045 {
2046         struct drm_device *dev = crtc->dev;
2047         struct drm_i915_private *dev_priv = dev->dev_private;
2048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2049         struct intel_framebuffer *intel_fb;
2050         struct drm_i915_gem_object *obj;
2051         int plane = intel_crtc->plane;
2052         unsigned long linear_offset;
2053         u32 dspcntr;
2054         u32 reg;
2055
2056         switch (plane) {
2057         case 0:
2058         case 1:
2059         case 2:
2060                 break;
2061         default:
2062                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2063                 return -EINVAL;
2064         }
2065
2066         intel_fb = to_intel_framebuffer(fb);
2067         obj = intel_fb->obj;
2068
2069         reg = DSPCNTR(plane);
2070         dspcntr = I915_READ(reg);
2071         /* Mask out pixel format bits in case we change it */
2072         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2073         switch (fb->pixel_format) {
2074         case DRM_FORMAT_C8:
2075                 dspcntr |= DISPPLANE_8BPP;
2076                 break;
2077         case DRM_FORMAT_RGB565:
2078                 dspcntr |= DISPPLANE_BGRX565;
2079                 break;
2080         case DRM_FORMAT_XRGB8888:
2081         case DRM_FORMAT_ARGB8888:
2082                 dspcntr |= DISPPLANE_BGRX888;
2083                 break;
2084         case DRM_FORMAT_XBGR8888:
2085         case DRM_FORMAT_ABGR8888:
2086                 dspcntr |= DISPPLANE_RGBX888;
2087                 break;
2088         case DRM_FORMAT_XRGB2101010:
2089         case DRM_FORMAT_ARGB2101010:
2090                 dspcntr |= DISPPLANE_BGRX101010;
2091                 break;
2092         case DRM_FORMAT_XBGR2101010:
2093         case DRM_FORMAT_ABGR2101010:
2094                 dspcntr |= DISPPLANE_RGBX101010;
2095                 break;
2096         default:
2097                 BUG();
2098         }
2099
2100         if (obj->tiling_mode != I915_TILING_NONE)
2101                 dspcntr |= DISPPLANE_TILED;
2102         else
2103                 dspcntr &= ~DISPPLANE_TILED;
2104
2105         if (IS_HASWELL(dev))
2106                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2107         else
2108                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2109
2110         I915_WRITE(reg, dspcntr);
2111
2112         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2113         intel_crtc->dspaddr_offset =
2114                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2115                                                fb->bits_per_pixel / 8,
2116                                                fb->pitches[0]);
2117         linear_offset -= intel_crtc->dspaddr_offset;
2118
2119         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2120                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2121                       fb->pitches[0]);
2122         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2123         I915_MODIFY_DISPBASE(DSPSURF(plane),
2124                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2125         if (IS_HASWELL(dev)) {
2126                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2127         } else {
2128                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2130         }
2131         POSTING_READ(reg);
2132
2133         return 0;
2134 }
2135
2136 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2137 static int
2138 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2139                            int x, int y, enum mode_set_atomic state)
2140 {
2141         struct drm_device *dev = crtc->dev;
2142         struct drm_i915_private *dev_priv = dev->dev_private;
2143
2144         if (dev_priv->display.disable_fbc)
2145                 dev_priv->display.disable_fbc(dev);
2146         intel_increase_pllclock(crtc);
2147
2148         return dev_priv->display.update_plane(crtc, fb, x, y);
2149 }
2150
2151 void intel_display_handle_reset(struct drm_device *dev)
2152 {
2153         struct drm_i915_private *dev_priv = dev->dev_private;
2154         struct drm_crtc *crtc;
2155
2156         /*
2157          * Flips in the rings have been nuked by the reset,
2158          * so complete all pending flips so that user space
2159          * will get its events and not get stuck.
2160          *
2161          * Also update the base address of all primary
2162          * planes to the the last fb to make sure we're
2163          * showing the correct fb after a reset.
2164          *
2165          * Need to make two loops over the crtcs so that we
2166          * don't try to grab a crtc mutex before the
2167          * pending_flip_queue really got woken up.
2168          */
2169
2170         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2171                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2172                 enum plane plane = intel_crtc->plane;
2173
2174                 intel_prepare_page_flip(dev, plane);
2175                 intel_finish_page_flip_plane(dev, plane);
2176         }
2177
2178         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2179                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181                 mutex_lock(&crtc->mutex);
2182                 if (intel_crtc->active)
2183                         dev_priv->display.update_plane(crtc, crtc->fb,
2184                                                        crtc->x, crtc->y);
2185                 mutex_unlock(&crtc->mutex);
2186         }
2187 }
2188
2189 static int
2190 intel_finish_fb(struct drm_framebuffer *old_fb)
2191 {
2192         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2193         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194         bool was_interruptible = dev_priv->mm.interruptible;
2195         int ret;
2196
2197         /* Big Hammer, we also need to ensure that any pending
2198          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2199          * current scanout is retired before unpinning the old
2200          * framebuffer.
2201          *
2202          * This should only fail upon a hung GPU, in which case we
2203          * can safely continue.
2204          */
2205         dev_priv->mm.interruptible = false;
2206         ret = i915_gem_object_finish_gpu(obj);
2207         dev_priv->mm.interruptible = was_interruptible;
2208
2209         return ret;
2210 }
2211
2212 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2213 {
2214         struct drm_device *dev = crtc->dev;
2215         struct drm_i915_master_private *master_priv;
2216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217
2218         if (!dev->primary->master)
2219                 return;
2220
2221         master_priv = dev->primary->master->driver_priv;
2222         if (!master_priv->sarea_priv)
2223                 return;
2224
2225         switch (intel_crtc->pipe) {
2226         case 0:
2227                 master_priv->sarea_priv->pipeA_x = x;
2228                 master_priv->sarea_priv->pipeA_y = y;
2229                 break;
2230         case 1:
2231                 master_priv->sarea_priv->pipeB_x = x;
2232                 master_priv->sarea_priv->pipeB_y = y;
2233                 break;
2234         default:
2235                 break;
2236         }
2237 }
2238
2239 static int
2240 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2241                     struct drm_framebuffer *fb)
2242 {
2243         struct drm_device *dev = crtc->dev;
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2246         struct drm_framebuffer *old_fb;
2247         int ret;
2248
2249         /* no fb bound */
2250         if (!fb) {
2251                 DRM_ERROR("No FB bound\n");
2252                 return 0;
2253         }
2254
2255         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2256                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2257                           plane_name(intel_crtc->plane),
2258                           INTEL_INFO(dev)->num_pipes);
2259                 return -EINVAL;
2260         }
2261
2262         mutex_lock(&dev->struct_mutex);
2263         ret = intel_pin_and_fence_fb_obj(dev,
2264                                          to_intel_framebuffer(fb)->obj,
2265                                          NULL);
2266         if (ret != 0) {
2267                 mutex_unlock(&dev->struct_mutex);
2268                 DRM_ERROR("pin & fence failed\n");
2269                 return ret;
2270         }
2271
2272         /* Update pipe size and adjust fitter if needed */
2273         if (i915_fastboot) {
2274                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2275                            ((crtc->mode.hdisplay - 1) << 16) |
2276                            (crtc->mode.vdisplay - 1));
2277                 if (!intel_crtc->config.pch_pfit.size &&
2278                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2279                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2280                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2281                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2282                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2283                 }
2284         }
2285
2286         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2287         if (ret) {
2288                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2289                 mutex_unlock(&dev->struct_mutex);
2290                 DRM_ERROR("failed to update base address\n");
2291                 return ret;
2292         }
2293
2294         old_fb = crtc->fb;
2295         crtc->fb = fb;
2296         crtc->x = x;
2297         crtc->y = y;
2298
2299         if (old_fb) {
2300                 if (intel_crtc->active && old_fb != fb)
2301                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2302                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2303         }
2304
2305         intel_update_fbc(dev);
2306         intel_edp_psr_update(dev);
2307         mutex_unlock(&dev->struct_mutex);
2308
2309         intel_crtc_update_sarea_pos(crtc, x, y);
2310
2311         return 0;
2312 }
2313
2314 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2315 {
2316         struct drm_device *dev = crtc->dev;
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2319         int pipe = intel_crtc->pipe;
2320         u32 reg, temp;
2321
2322         /* enable normal train */
2323         reg = FDI_TX_CTL(pipe);
2324         temp = I915_READ(reg);
2325         if (IS_IVYBRIDGE(dev)) {
2326                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2327                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2328         } else {
2329                 temp &= ~FDI_LINK_TRAIN_NONE;
2330                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2331         }
2332         I915_WRITE(reg, temp);
2333
2334         reg = FDI_RX_CTL(pipe);
2335         temp = I915_READ(reg);
2336         if (HAS_PCH_CPT(dev)) {
2337                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2338                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2339         } else {
2340                 temp &= ~FDI_LINK_TRAIN_NONE;
2341                 temp |= FDI_LINK_TRAIN_NONE;
2342         }
2343         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2344
2345         /* wait one idle pattern time */
2346         POSTING_READ(reg);
2347         udelay(1000);
2348
2349         /* IVB wants error correction enabled */
2350         if (IS_IVYBRIDGE(dev))
2351                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2352                            FDI_FE_ERRC_ENABLE);
2353 }
2354
2355 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2356 {
2357         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2358 }
2359
2360 static void ivb_modeset_global_resources(struct drm_device *dev)
2361 {
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         struct intel_crtc *pipe_B_crtc =
2364                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2365         struct intel_crtc *pipe_C_crtc =
2366                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2367         uint32_t temp;
2368
2369         /*
2370          * When everything is off disable fdi C so that we could enable fdi B
2371          * with all lanes. Note that we don't care about enabled pipes without
2372          * an enabled pch encoder.
2373          */
2374         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2375             !pipe_has_enabled_pch(pipe_C_crtc)) {
2376                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2377                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2378
2379                 temp = I915_READ(SOUTH_CHICKEN1);
2380                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2381                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2382                 I915_WRITE(SOUTH_CHICKEN1, temp);
2383         }
2384 }
2385
2386 /* The FDI link training functions for ILK/Ibexpeak. */
2387 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2388 {
2389         struct drm_device *dev = crtc->dev;
2390         struct drm_i915_private *dev_priv = dev->dev_private;
2391         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2392         int pipe = intel_crtc->pipe;
2393         int plane = intel_crtc->plane;
2394         u32 reg, temp, tries;
2395
2396         /* FDI needs bits from pipe & plane first */
2397         assert_pipe_enabled(dev_priv, pipe);
2398         assert_plane_enabled(dev_priv, plane);
2399
2400         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2401            for train result */
2402         reg = FDI_RX_IMR(pipe);
2403         temp = I915_READ(reg);
2404         temp &= ~FDI_RX_SYMBOL_LOCK;
2405         temp &= ~FDI_RX_BIT_LOCK;
2406         I915_WRITE(reg, temp);
2407         I915_READ(reg);
2408         udelay(150);
2409
2410         /* enable CPU FDI TX and PCH FDI RX */
2411         reg = FDI_TX_CTL(pipe);
2412         temp = I915_READ(reg);
2413         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2414         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2415         temp &= ~FDI_LINK_TRAIN_NONE;
2416         temp |= FDI_LINK_TRAIN_PATTERN_1;
2417         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2418
2419         reg = FDI_RX_CTL(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_LINK_TRAIN_NONE;
2422         temp |= FDI_LINK_TRAIN_PATTERN_1;
2423         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2424
2425         POSTING_READ(reg);
2426         udelay(150);
2427
2428         /* Ironlake workaround, enable clock pointer after FDI enable*/
2429         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2430         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2431                    FDI_RX_PHASE_SYNC_POINTER_EN);
2432
2433         reg = FDI_RX_IIR(pipe);
2434         for (tries = 0; tries < 5; tries++) {
2435                 temp = I915_READ(reg);
2436                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438                 if ((temp & FDI_RX_BIT_LOCK)) {
2439                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2440                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2441                         break;
2442                 }
2443         }
2444         if (tries == 5)
2445                 DRM_ERROR("FDI train 1 fail!\n");
2446
2447         /* Train 2 */
2448         reg = FDI_TX_CTL(pipe);
2449         temp = I915_READ(reg);
2450         temp &= ~FDI_LINK_TRAIN_NONE;
2451         temp |= FDI_LINK_TRAIN_PATTERN_2;
2452         I915_WRITE(reg, temp);
2453
2454         reg = FDI_RX_CTL(pipe);
2455         temp = I915_READ(reg);
2456         temp &= ~FDI_LINK_TRAIN_NONE;
2457         temp |= FDI_LINK_TRAIN_PATTERN_2;
2458         I915_WRITE(reg, temp);
2459
2460         POSTING_READ(reg);
2461         udelay(150);
2462
2463         reg = FDI_RX_IIR(pipe);
2464         for (tries = 0; tries < 5; tries++) {
2465                 temp = I915_READ(reg);
2466                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2467
2468                 if (temp & FDI_RX_SYMBOL_LOCK) {
2469                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2470                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2471                         break;
2472                 }
2473         }
2474         if (tries == 5)
2475                 DRM_ERROR("FDI train 2 fail!\n");
2476
2477         DRM_DEBUG_KMS("FDI train done\n");
2478
2479 }
2480
2481 static const int snb_b_fdi_train_param[] = {
2482         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2483         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2484         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2485         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2486 };
2487
2488 /* The FDI link training functions for SNB/Cougarpoint. */
2489 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2490 {
2491         struct drm_device *dev = crtc->dev;
2492         struct drm_i915_private *dev_priv = dev->dev_private;
2493         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494         int pipe = intel_crtc->pipe;
2495         u32 reg, temp, i, retry;
2496
2497         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2498            for train result */
2499         reg = FDI_RX_IMR(pipe);
2500         temp = I915_READ(reg);
2501         temp &= ~FDI_RX_SYMBOL_LOCK;
2502         temp &= ~FDI_RX_BIT_LOCK;
2503         I915_WRITE(reg, temp);
2504
2505         POSTING_READ(reg);
2506         udelay(150);
2507
2508         /* enable CPU FDI TX and PCH FDI RX */
2509         reg = FDI_TX_CTL(pipe);
2510         temp = I915_READ(reg);
2511         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2512         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2513         temp &= ~FDI_LINK_TRAIN_NONE;
2514         temp |= FDI_LINK_TRAIN_PATTERN_1;
2515         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516         /* SNB-B */
2517         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2518         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2519
2520         I915_WRITE(FDI_RX_MISC(pipe),
2521                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2522
2523         reg = FDI_RX_CTL(pipe);
2524         temp = I915_READ(reg);
2525         if (HAS_PCH_CPT(dev)) {
2526                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2527                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2528         } else {
2529                 temp &= ~FDI_LINK_TRAIN_NONE;
2530                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2531         }
2532         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2533
2534         POSTING_READ(reg);
2535         udelay(150);
2536
2537         for (i = 0; i < 4; i++) {
2538                 reg = FDI_TX_CTL(pipe);
2539                 temp = I915_READ(reg);
2540                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541                 temp |= snb_b_fdi_train_param[i];
2542                 I915_WRITE(reg, temp);
2543
2544                 POSTING_READ(reg);
2545                 udelay(500);
2546
2547                 for (retry = 0; retry < 5; retry++) {
2548                         reg = FDI_RX_IIR(pipe);
2549                         temp = I915_READ(reg);
2550                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551                         if (temp & FDI_RX_BIT_LOCK) {
2552                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2553                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2554                                 break;
2555                         }
2556                         udelay(50);
2557                 }
2558                 if (retry < 5)
2559                         break;
2560         }
2561         if (i == 4)
2562                 DRM_ERROR("FDI train 1 fail!\n");
2563
2564         /* Train 2 */
2565         reg = FDI_TX_CTL(pipe);
2566         temp = I915_READ(reg);
2567         temp &= ~FDI_LINK_TRAIN_NONE;
2568         temp |= FDI_LINK_TRAIN_PATTERN_2;
2569         if (IS_GEN6(dev)) {
2570                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571                 /* SNB-B */
2572                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2573         }
2574         I915_WRITE(reg, temp);
2575
2576         reg = FDI_RX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         if (HAS_PCH_CPT(dev)) {
2579                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2580                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2581         } else {
2582                 temp &= ~FDI_LINK_TRAIN_NONE;
2583                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2584         }
2585         I915_WRITE(reg, temp);
2586
2587         POSTING_READ(reg);
2588         udelay(150);
2589
2590         for (i = 0; i < 4; i++) {
2591                 reg = FDI_TX_CTL(pipe);
2592                 temp = I915_READ(reg);
2593                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594                 temp |= snb_b_fdi_train_param[i];
2595                 I915_WRITE(reg, temp);
2596
2597                 POSTING_READ(reg);
2598                 udelay(500);
2599
2600                 for (retry = 0; retry < 5; retry++) {
2601                         reg = FDI_RX_IIR(pipe);
2602                         temp = I915_READ(reg);
2603                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2604                         if (temp & FDI_RX_SYMBOL_LOCK) {
2605                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2606                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2607                                 break;
2608                         }
2609                         udelay(50);
2610                 }
2611                 if (retry < 5)
2612                         break;
2613         }
2614         if (i == 4)
2615                 DRM_ERROR("FDI train 2 fail!\n");
2616
2617         DRM_DEBUG_KMS("FDI train done.\n");
2618 }
2619
2620 /* Manual link training for Ivy Bridge A0 parts */
2621 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2622 {
2623         struct drm_device *dev = crtc->dev;
2624         struct drm_i915_private *dev_priv = dev->dev_private;
2625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626         int pipe = intel_crtc->pipe;
2627         u32 reg, temp, i, j;
2628
2629         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2630            for train result */
2631         reg = FDI_RX_IMR(pipe);
2632         temp = I915_READ(reg);
2633         temp &= ~FDI_RX_SYMBOL_LOCK;
2634         temp &= ~FDI_RX_BIT_LOCK;
2635         I915_WRITE(reg, temp);
2636
2637         POSTING_READ(reg);
2638         udelay(150);
2639
2640         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2641                       I915_READ(FDI_RX_IIR(pipe)));
2642
2643         /* Try each vswing and preemphasis setting twice before moving on */
2644         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2645                 /* disable first in case we need to retry */
2646                 reg = FDI_TX_CTL(pipe);
2647                 temp = I915_READ(reg);
2648                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2649                 temp &= ~FDI_TX_ENABLE;
2650                 I915_WRITE(reg, temp);
2651
2652                 reg = FDI_RX_CTL(pipe);
2653                 temp = I915_READ(reg);
2654                 temp &= ~FDI_LINK_TRAIN_AUTO;
2655                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656                 temp &= ~FDI_RX_ENABLE;
2657                 I915_WRITE(reg, temp);
2658
2659                 /* enable CPU FDI TX and PCH FDI RX */
2660                 reg = FDI_TX_CTL(pipe);
2661                 temp = I915_READ(reg);
2662                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2663                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2664                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2665                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666                 temp |= snb_b_fdi_train_param[j/2];
2667                 temp |= FDI_COMPOSITE_SYNC;
2668                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2669
2670                 I915_WRITE(FDI_RX_MISC(pipe),
2671                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2672
2673                 reg = FDI_RX_CTL(pipe);
2674                 temp = I915_READ(reg);
2675                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2676                 temp |= FDI_COMPOSITE_SYNC;
2677                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2678
2679                 POSTING_READ(reg);
2680                 udelay(1); /* should be 0.5us */
2681
2682                 for (i = 0; i < 4; i++) {
2683                         reg = FDI_RX_IIR(pipe);
2684                         temp = I915_READ(reg);
2685                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2686
2687                         if (temp & FDI_RX_BIT_LOCK ||
2688                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2689                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2690                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2691                                               i);
2692                                 break;
2693                         }
2694                         udelay(1); /* should be 0.5us */
2695                 }
2696                 if (i == 4) {
2697                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2698                         continue;
2699                 }
2700
2701                 /* Train 2 */
2702                 reg = FDI_TX_CTL(pipe);
2703                 temp = I915_READ(reg);
2704                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2705                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2706                 I915_WRITE(reg, temp);
2707
2708                 reg = FDI_RX_CTL(pipe);
2709                 temp = I915_READ(reg);
2710                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2711                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2712                 I915_WRITE(reg, temp);
2713
2714                 POSTING_READ(reg);
2715                 udelay(2); /* should be 1.5us */
2716
2717                 for (i = 0; i < 4; i++) {
2718                         reg = FDI_RX_IIR(pipe);
2719                         temp = I915_READ(reg);
2720                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2721
2722                         if (temp & FDI_RX_SYMBOL_LOCK ||
2723                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2724                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2725                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2726                                               i);
2727                                 goto train_done;
2728                         }
2729                         udelay(2); /* should be 1.5us */
2730                 }
2731                 if (i == 4)
2732                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2733         }
2734
2735 train_done:
2736         DRM_DEBUG_KMS("FDI train done.\n");
2737 }
2738
2739 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2740 {
2741         struct drm_device *dev = intel_crtc->base.dev;
2742         struct drm_i915_private *dev_priv = dev->dev_private;
2743         int pipe = intel_crtc->pipe;
2744         u32 reg, temp;
2745
2746
2747         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2748         reg = FDI_RX_CTL(pipe);
2749         temp = I915_READ(reg);
2750         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2751         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2752         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2753         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2754
2755         POSTING_READ(reg);
2756         udelay(200);
2757
2758         /* Switch from Rawclk to PCDclk */
2759         temp = I915_READ(reg);
2760         I915_WRITE(reg, temp | FDI_PCDCLK);
2761
2762         POSTING_READ(reg);
2763         udelay(200);
2764
2765         /* Enable CPU FDI TX PLL, always on for Ironlake */
2766         reg = FDI_TX_CTL(pipe);
2767         temp = I915_READ(reg);
2768         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2769                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2770
2771                 POSTING_READ(reg);
2772                 udelay(100);
2773         }
2774 }
2775
2776 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2777 {
2778         struct drm_device *dev = intel_crtc->base.dev;
2779         struct drm_i915_private *dev_priv = dev->dev_private;
2780         int pipe = intel_crtc->pipe;
2781         u32 reg, temp;
2782
2783         /* Switch from PCDclk to Rawclk */
2784         reg = FDI_RX_CTL(pipe);
2785         temp = I915_READ(reg);
2786         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2787
2788         /* Disable CPU FDI TX PLL */
2789         reg = FDI_TX_CTL(pipe);
2790         temp = I915_READ(reg);
2791         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2792
2793         POSTING_READ(reg);
2794         udelay(100);
2795
2796         reg = FDI_RX_CTL(pipe);
2797         temp = I915_READ(reg);
2798         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2799
2800         /* Wait for the clocks to turn off. */
2801         POSTING_READ(reg);
2802         udelay(100);
2803 }
2804
2805 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2806 {
2807         struct drm_device *dev = crtc->dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810         int pipe = intel_crtc->pipe;
2811         u32 reg, temp;
2812
2813         /* disable CPU FDI tx and PCH FDI rx */
2814         reg = FDI_TX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2817         POSTING_READ(reg);
2818
2819         reg = FDI_RX_CTL(pipe);
2820         temp = I915_READ(reg);
2821         temp &= ~(0x7 << 16);
2822         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2823         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2824
2825         POSTING_READ(reg);
2826         udelay(100);
2827
2828         /* Ironlake workaround, disable clock pointer after downing FDI */
2829         if (HAS_PCH_IBX(dev)) {
2830                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2831         }
2832
2833         /* still set train pattern 1 */
2834         reg = FDI_TX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         temp &= ~FDI_LINK_TRAIN_NONE;
2837         temp |= FDI_LINK_TRAIN_PATTERN_1;
2838         I915_WRITE(reg, temp);
2839
2840         reg = FDI_RX_CTL(pipe);
2841         temp = I915_READ(reg);
2842         if (HAS_PCH_CPT(dev)) {
2843                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845         } else {
2846                 temp &= ~FDI_LINK_TRAIN_NONE;
2847                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848         }
2849         /* BPC in FDI rx is consistent with that in PIPECONF */
2850         temp &= ~(0x07 << 16);
2851         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2852         I915_WRITE(reg, temp);
2853
2854         POSTING_READ(reg);
2855         udelay(100);
2856 }
2857
2858 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2859 {
2860         struct drm_device *dev = crtc->dev;
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2863         unsigned long flags;
2864         bool pending;
2865
2866         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2867             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2868                 return false;
2869
2870         spin_lock_irqsave(&dev->event_lock, flags);
2871         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2872         spin_unlock_irqrestore(&dev->event_lock, flags);
2873
2874         return pending;
2875 }
2876
2877 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2878 {
2879         struct drm_device *dev = crtc->dev;
2880         struct drm_i915_private *dev_priv = dev->dev_private;
2881
2882         if (crtc->fb == NULL)
2883                 return;
2884
2885         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2886
2887         wait_event(dev_priv->pending_flip_queue,
2888                    !intel_crtc_has_pending_flip(crtc));
2889
2890         mutex_lock(&dev->struct_mutex);
2891         intel_finish_fb(crtc->fb);
2892         mutex_unlock(&dev->struct_mutex);
2893 }
2894
2895 /* Program iCLKIP clock to the desired frequency */
2896 static void lpt_program_iclkip(struct drm_crtc *crtc)
2897 {
2898         struct drm_device *dev = crtc->dev;
2899         struct drm_i915_private *dev_priv = dev->dev_private;
2900         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2901         u32 temp;
2902
2903         mutex_lock(&dev_priv->dpio_lock);
2904
2905         /* It is necessary to ungate the pixclk gate prior to programming
2906          * the divisors, and gate it back when it is done.
2907          */
2908         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2909
2910         /* Disable SSCCTL */
2911         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2912                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2913                                 SBI_SSCCTL_DISABLE,
2914                         SBI_ICLK);
2915
2916         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2917         if (crtc->mode.clock == 20000) {
2918                 auxdiv = 1;
2919                 divsel = 0x41;
2920                 phaseinc = 0x20;
2921         } else {
2922                 /* The iCLK virtual clock root frequency is in MHz,
2923                  * but the crtc->mode.clock in in KHz. To get the divisors,
2924                  * it is necessary to divide one by another, so we
2925                  * convert the virtual clock precision to KHz here for higher
2926                  * precision.
2927                  */
2928                 u32 iclk_virtual_root_freq = 172800 * 1000;
2929                 u32 iclk_pi_range = 64;
2930                 u32 desired_divisor, msb_divisor_value, pi_value;
2931
2932                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2933                 msb_divisor_value = desired_divisor / iclk_pi_range;
2934                 pi_value = desired_divisor % iclk_pi_range;
2935
2936                 auxdiv = 0;
2937                 divsel = msb_divisor_value - 2;
2938                 phaseinc = pi_value;
2939         }
2940
2941         /* This should not happen with any sane values */
2942         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2943                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2944         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2945                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2946
2947         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2948                         crtc->mode.clock,
2949                         auxdiv,
2950                         divsel,
2951                         phasedir,
2952                         phaseinc);
2953
2954         /* Program SSCDIVINTPHASE6 */
2955         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2956         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2957         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2958         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2959         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2960         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2961         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2962         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2963
2964         /* Program SSCAUXDIV */
2965         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2966         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2967         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2968         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2969
2970         /* Enable modulator and associated divider */
2971         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2972         temp &= ~SBI_SSCCTL_DISABLE;
2973         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2974
2975         /* Wait for initialization time */
2976         udelay(24);
2977
2978         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2979
2980         mutex_unlock(&dev_priv->dpio_lock);
2981 }
2982
2983 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2984                                                 enum pipe pch_transcoder)
2985 {
2986         struct drm_device *dev = crtc->base.dev;
2987         struct drm_i915_private *dev_priv = dev->dev_private;
2988         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2989
2990         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2991                    I915_READ(HTOTAL(cpu_transcoder)));
2992         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2993                    I915_READ(HBLANK(cpu_transcoder)));
2994         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2995                    I915_READ(HSYNC(cpu_transcoder)));
2996
2997         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2998                    I915_READ(VTOTAL(cpu_transcoder)));
2999         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3000                    I915_READ(VBLANK(cpu_transcoder)));
3001         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3002                    I915_READ(VSYNC(cpu_transcoder)));
3003         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3004                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3005 }
3006
3007 /*
3008  * Enable PCH resources required for PCH ports:
3009  *   - PCH PLLs
3010  *   - FDI training & RX/TX
3011  *   - update transcoder timings
3012  *   - DP transcoding bits
3013  *   - transcoder
3014  */
3015 static void ironlake_pch_enable(struct drm_crtc *crtc)
3016 {
3017         struct drm_device *dev = crtc->dev;
3018         struct drm_i915_private *dev_priv = dev->dev_private;
3019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020         int pipe = intel_crtc->pipe;
3021         u32 reg, temp;
3022
3023         assert_pch_transcoder_disabled(dev_priv, pipe);
3024
3025         /* Write the TU size bits before fdi link training, so that error
3026          * detection works. */
3027         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3028                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3029
3030         /* For PCH output, training FDI link */
3031         dev_priv->display.fdi_link_train(crtc);
3032
3033         /* We need to program the right clock selection before writing the pixel
3034          * mutliplier into the DPLL. */
3035         if (HAS_PCH_CPT(dev)) {
3036                 u32 sel;
3037
3038                 temp = I915_READ(PCH_DPLL_SEL);
3039                 temp |= TRANS_DPLL_ENABLE(pipe);
3040                 sel = TRANS_DPLLB_SEL(pipe);
3041                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3042                         temp |= sel;
3043                 else
3044                         temp &= ~sel;
3045                 I915_WRITE(PCH_DPLL_SEL, temp);
3046         }
3047
3048         /* XXX: pch pll's can be enabled any time before we enable the PCH
3049          * transcoder, and we actually should do this to not upset any PCH
3050          * transcoder that already use the clock when we share it.
3051          *
3052          * Note that enable_shared_dpll tries to do the right thing, but
3053          * get_shared_dpll unconditionally resets the pll - we need that to have
3054          * the right LVDS enable sequence. */
3055         ironlake_enable_shared_dpll(intel_crtc);
3056
3057         /* set transcoder timing, panel must allow it */
3058         assert_panel_unlocked(dev_priv, pipe);
3059         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3060
3061         intel_fdi_normal_train(crtc);
3062
3063         /* For PCH DP, enable TRANS_DP_CTL */
3064         if (HAS_PCH_CPT(dev) &&
3065             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3066              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3067                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3068                 reg = TRANS_DP_CTL(pipe);
3069                 temp = I915_READ(reg);
3070                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3071                           TRANS_DP_SYNC_MASK |
3072                           TRANS_DP_BPC_MASK);
3073                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3074                          TRANS_DP_ENH_FRAMING);
3075                 temp |= bpc << 9; /* same format but at 11:9 */
3076
3077                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3078                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3079                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3080                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3081
3082                 switch (intel_trans_dp_port_sel(crtc)) {
3083                 case PCH_DP_B:
3084                         temp |= TRANS_DP_PORT_SEL_B;
3085                         break;
3086                 case PCH_DP_C:
3087                         temp |= TRANS_DP_PORT_SEL_C;
3088                         break;
3089                 case PCH_DP_D:
3090                         temp |= TRANS_DP_PORT_SEL_D;
3091                         break;
3092                 default:
3093                         BUG();
3094                 }
3095
3096                 I915_WRITE(reg, temp);
3097         }
3098
3099         ironlake_enable_pch_transcoder(dev_priv, pipe);
3100 }
3101
3102 static void lpt_pch_enable(struct drm_crtc *crtc)
3103 {
3104         struct drm_device *dev = crtc->dev;
3105         struct drm_i915_private *dev_priv = dev->dev_private;
3106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3107         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3108
3109         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3110
3111         lpt_program_iclkip(crtc);
3112
3113         /* Set transcoder timing. */
3114         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3115
3116         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3117 }
3118
3119 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3120 {
3121         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3122
3123         if (pll == NULL)
3124                 return;
3125
3126         if (pll->refcount == 0) {
3127                 WARN(1, "bad %s refcount\n", pll->name);
3128                 return;
3129         }
3130
3131         if (--pll->refcount == 0) {
3132                 WARN_ON(pll->on);
3133                 WARN_ON(pll->active);
3134         }
3135
3136         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3137 }
3138
3139 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3140 {
3141         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3142         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3143         enum intel_dpll_id i;
3144
3145         if (pll) {
3146                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3147                               crtc->base.base.id, pll->name);
3148                 intel_put_shared_dpll(crtc);
3149         }
3150
3151         if (HAS_PCH_IBX(dev_priv->dev)) {
3152                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3153                 i = (enum intel_dpll_id) crtc->pipe;
3154                 pll = &dev_priv->shared_dplls[i];
3155
3156                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3157                               crtc->base.base.id, pll->name);
3158
3159                 goto found;
3160         }
3161
3162         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3163                 pll = &dev_priv->shared_dplls[i];
3164
3165                 /* Only want to check enabled timings first */
3166                 if (pll->refcount == 0)
3167                         continue;
3168
3169                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3170                            sizeof(pll->hw_state)) == 0) {
3171                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3172                                       crtc->base.base.id,
3173                                       pll->name, pll->refcount, pll->active);
3174
3175                         goto found;
3176                 }
3177         }
3178
3179         /* Ok no matching timings, maybe there's a free one? */
3180         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181                 pll = &dev_priv->shared_dplls[i];
3182                 if (pll->refcount == 0) {
3183                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3184                                       crtc->base.base.id, pll->name);
3185                         goto found;
3186                 }
3187         }
3188
3189         return NULL;
3190
3191 found:
3192         crtc->config.shared_dpll = i;
3193         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3194                          pipe_name(crtc->pipe));
3195
3196         if (pll->active == 0) {
3197                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3198                        sizeof(pll->hw_state));
3199
3200                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3201                 WARN_ON(pll->on);
3202                 assert_shared_dpll_disabled(dev_priv, pll);
3203
3204                 pll->mode_set(dev_priv, pll);
3205         }
3206         pll->refcount++;
3207
3208         return pll;
3209 }
3210
3211 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3212 {
3213         struct drm_i915_private *dev_priv = dev->dev_private;
3214         int dslreg = PIPEDSL(pipe);
3215         u32 temp;
3216
3217         temp = I915_READ(dslreg);
3218         udelay(500);
3219         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3220                 if (wait_for(I915_READ(dslreg) != temp, 5))
3221                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3222         }
3223 }
3224
3225 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->base.dev;
3228         struct drm_i915_private *dev_priv = dev->dev_private;
3229         int pipe = crtc->pipe;
3230
3231         if (crtc->config.pch_pfit.size) {
3232                 /* Force use of hard-coded filter coefficients
3233                  * as some pre-programmed values are broken,
3234                  * e.g. x201.
3235                  */
3236                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3237                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3238                                                  PF_PIPE_SEL_IVB(pipe));
3239                 else
3240                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3241                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3242                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3243         }
3244 }
3245
3246 static void intel_enable_planes(struct drm_crtc *crtc)
3247 {
3248         struct drm_device *dev = crtc->dev;
3249         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3250         struct intel_plane *intel_plane;
3251
3252         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3253                 if (intel_plane->pipe == pipe)
3254                         intel_plane_restore(&intel_plane->base);
3255 }
3256
3257 static void intel_disable_planes(struct drm_crtc *crtc)
3258 {
3259         struct drm_device *dev = crtc->dev;
3260         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3261         struct intel_plane *intel_plane;
3262
3263         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3264                 if (intel_plane->pipe == pipe)
3265                         intel_plane_disable(&intel_plane->base);
3266 }
3267
3268 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3269 {
3270         struct drm_device *dev = crtc->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273         struct intel_encoder *encoder;
3274         int pipe = intel_crtc->pipe;
3275         int plane = intel_crtc->plane;
3276
3277         WARN_ON(!crtc->enabled);
3278
3279         if (intel_crtc->active)
3280                 return;
3281
3282         intel_crtc->active = true;
3283
3284         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3286
3287         for_each_encoder_on_crtc(dev, crtc, encoder)
3288                 if (encoder->pre_enable)
3289                         encoder->pre_enable(encoder);
3290
3291         if (intel_crtc->config.has_pch_encoder) {
3292                 /* Note: FDI PLL enabling _must_ be done before we enable the
3293                  * cpu pipes, hence this is separate from all the other fdi/pch
3294                  * enabling. */
3295                 ironlake_fdi_pll_enable(intel_crtc);
3296         } else {
3297                 assert_fdi_tx_disabled(dev_priv, pipe);
3298                 assert_fdi_rx_disabled(dev_priv, pipe);
3299         }
3300
3301         ironlake_pfit_enable(intel_crtc);
3302
3303         /*
3304          * On ILK+ LUT must be loaded before the pipe is running but with
3305          * clocks enabled
3306          */
3307         intel_crtc_load_lut(crtc);
3308
3309         intel_update_watermarks(crtc);
3310         intel_enable_pipe(dev_priv, pipe,
3311                           intel_crtc->config.has_pch_encoder, false);
3312         intel_enable_plane(dev_priv, plane, pipe);
3313         intel_enable_planes(crtc);
3314         intel_crtc_update_cursor(crtc, true);
3315
3316         if (intel_crtc->config.has_pch_encoder)
3317                 ironlake_pch_enable(crtc);
3318
3319         mutex_lock(&dev->struct_mutex);
3320         intel_update_fbc(dev);
3321         mutex_unlock(&dev->struct_mutex);
3322
3323         for_each_encoder_on_crtc(dev, crtc, encoder)
3324                 encoder->enable(encoder);
3325
3326         if (HAS_PCH_CPT(dev))
3327                 cpt_verify_modeset(dev, intel_crtc->pipe);
3328
3329         /*
3330          * There seems to be a race in PCH platform hw (at least on some
3331          * outputs) where an enabled pipe still completes any pageflip right
3332          * away (as if the pipe is off) instead of waiting for vblank. As soon
3333          * as the first vblank happend, everything works as expected. Hence just
3334          * wait for one vblank before returning to avoid strange things
3335          * happening.
3336          */
3337         intel_wait_for_vblank(dev, intel_crtc->pipe);
3338 }
3339
3340 /* IPS only exists on ULT machines and is tied to pipe A. */
3341 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3342 {
3343         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3344 }
3345
3346 static void hsw_enable_ips(struct intel_crtc *crtc)
3347 {
3348         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3349
3350         if (!crtc->config.ips_enabled)
3351                 return;
3352
3353         /* We can only enable IPS after we enable a plane and wait for a vblank.
3354          * We guarantee that the plane is enabled by calling intel_enable_ips
3355          * only after intel_enable_plane. And intel_enable_plane already waits
3356          * for a vblank, so all we need to do here is to enable the IPS bit. */
3357         assert_plane_enabled(dev_priv, crtc->plane);
3358         I915_WRITE(IPS_CTL, IPS_ENABLE);
3359 }
3360
3361 static void hsw_disable_ips(struct intel_crtc *crtc)
3362 {
3363         struct drm_device *dev = crtc->base.dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366         if (!crtc->config.ips_enabled)
3367                 return;
3368
3369         assert_plane_enabled(dev_priv, crtc->plane);
3370         I915_WRITE(IPS_CTL, 0);
3371
3372         /* We need to wait for a vblank before we can disable the plane. */
3373         intel_wait_for_vblank(dev, crtc->pipe);
3374 }
3375
3376 static void haswell_crtc_enable(struct drm_crtc *crtc)
3377 {
3378         struct drm_device *dev = crtc->dev;
3379         struct drm_i915_private *dev_priv = dev->dev_private;
3380         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381         struct intel_encoder *encoder;
3382         int pipe = intel_crtc->pipe;
3383         int plane = intel_crtc->plane;
3384
3385         WARN_ON(!crtc->enabled);
3386
3387         if (intel_crtc->active)
3388                 return;
3389
3390         intel_crtc->active = true;
3391
3392         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3393         if (intel_crtc->config.has_pch_encoder)
3394                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3395
3396         if (intel_crtc->config.has_pch_encoder)
3397                 dev_priv->display.fdi_link_train(crtc);
3398
3399         for_each_encoder_on_crtc(dev, crtc, encoder)
3400                 if (encoder->pre_enable)
3401                         encoder->pre_enable(encoder);
3402
3403         intel_ddi_enable_pipe_clock(intel_crtc);
3404
3405         ironlake_pfit_enable(intel_crtc);
3406
3407         /*
3408          * On ILK+ LUT must be loaded before the pipe is running but with
3409          * clocks enabled
3410          */
3411         intel_crtc_load_lut(crtc);
3412
3413         intel_ddi_set_pipe_settings(crtc);
3414         intel_ddi_enable_transcoder_func(crtc);
3415
3416         intel_update_watermarks(crtc);
3417         intel_enable_pipe(dev_priv, pipe,
3418                           intel_crtc->config.has_pch_encoder, false);
3419         intel_enable_plane(dev_priv, plane, pipe);
3420         intel_enable_planes(crtc);
3421         intel_crtc_update_cursor(crtc, true);
3422
3423         hsw_enable_ips(intel_crtc);
3424
3425         if (intel_crtc->config.has_pch_encoder)
3426                 lpt_pch_enable(crtc);
3427
3428         mutex_lock(&dev->struct_mutex);
3429         intel_update_fbc(dev);
3430         mutex_unlock(&dev->struct_mutex);
3431
3432         for_each_encoder_on_crtc(dev, crtc, encoder) {
3433                 encoder->enable(encoder);
3434                 intel_opregion_notify_encoder(encoder, true);
3435         }
3436
3437         /*
3438          * There seems to be a race in PCH platform hw (at least on some
3439          * outputs) where an enabled pipe still completes any pageflip right
3440          * away (as if the pipe is off) instead of waiting for vblank. As soon
3441          * as the first vblank happend, everything works as expected. Hence just
3442          * wait for one vblank before returning to avoid strange things
3443          * happening.
3444          */
3445         intel_wait_for_vblank(dev, intel_crtc->pipe);
3446 }
3447
3448 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3449 {
3450         struct drm_device *dev = crtc->base.dev;
3451         struct drm_i915_private *dev_priv = dev->dev_private;
3452         int pipe = crtc->pipe;
3453
3454         /* To avoid upsetting the power well on haswell only disable the pfit if
3455          * it's in use. The hw state code will make sure we get this right. */
3456         if (crtc->config.pch_pfit.size) {
3457                 I915_WRITE(PF_CTL(pipe), 0);
3458                 I915_WRITE(PF_WIN_POS(pipe), 0);
3459                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3460         }
3461 }
3462
3463 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3464 {
3465         struct drm_device *dev = crtc->dev;
3466         struct drm_i915_private *dev_priv = dev->dev_private;
3467         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3468         struct intel_encoder *encoder;
3469         int pipe = intel_crtc->pipe;
3470         int plane = intel_crtc->plane;
3471         u32 reg, temp;
3472
3473
3474         if (!intel_crtc->active)
3475                 return;
3476
3477         for_each_encoder_on_crtc(dev, crtc, encoder)
3478                 encoder->disable(encoder);
3479
3480         intel_crtc_wait_for_pending_flips(crtc);
3481         drm_vblank_off(dev, pipe);
3482
3483         if (dev_priv->fbc.plane == plane)
3484                 intel_disable_fbc(dev);
3485
3486         intel_crtc_update_cursor(crtc, false);
3487         intel_disable_planes(crtc);
3488         intel_disable_plane(dev_priv, plane, pipe);
3489
3490         if (intel_crtc->config.has_pch_encoder)
3491                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3492
3493         intel_disable_pipe(dev_priv, pipe);
3494
3495         ironlake_pfit_disable(intel_crtc);
3496
3497         for_each_encoder_on_crtc(dev, crtc, encoder)
3498                 if (encoder->post_disable)
3499                         encoder->post_disable(encoder);
3500
3501         if (intel_crtc->config.has_pch_encoder) {
3502                 ironlake_fdi_disable(crtc);
3503
3504                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3505                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3506
3507                 if (HAS_PCH_CPT(dev)) {
3508                         /* disable TRANS_DP_CTL */
3509                         reg = TRANS_DP_CTL(pipe);
3510                         temp = I915_READ(reg);
3511                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3512                                   TRANS_DP_PORT_SEL_MASK);
3513                         temp |= TRANS_DP_PORT_SEL_NONE;
3514                         I915_WRITE(reg, temp);
3515
3516                         /* disable DPLL_SEL */
3517                         temp = I915_READ(PCH_DPLL_SEL);
3518                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3519                         I915_WRITE(PCH_DPLL_SEL, temp);
3520                 }
3521
3522                 /* disable PCH DPLL */
3523                 intel_disable_shared_dpll(intel_crtc);
3524
3525                 ironlake_fdi_pll_disable(intel_crtc);
3526         }
3527
3528         intel_crtc->active = false;
3529         intel_update_watermarks(crtc);
3530
3531         mutex_lock(&dev->struct_mutex);
3532         intel_update_fbc(dev);
3533         mutex_unlock(&dev->struct_mutex);
3534 }
3535
3536 static void haswell_crtc_disable(struct drm_crtc *crtc)
3537 {
3538         struct drm_device *dev = crtc->dev;
3539         struct drm_i915_private *dev_priv = dev->dev_private;
3540         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3541         struct intel_encoder *encoder;
3542         int pipe = intel_crtc->pipe;
3543         int plane = intel_crtc->plane;
3544         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3545
3546         if (!intel_crtc->active)
3547                 return;
3548
3549         for_each_encoder_on_crtc(dev, crtc, encoder) {
3550                 intel_opregion_notify_encoder(encoder, false);
3551                 encoder->disable(encoder);
3552         }
3553
3554         intel_crtc_wait_for_pending_flips(crtc);
3555         drm_vblank_off(dev, pipe);
3556
3557         /* FBC must be disabled before disabling the plane on HSW. */
3558         if (dev_priv->fbc.plane == plane)
3559                 intel_disable_fbc(dev);
3560
3561         hsw_disable_ips(intel_crtc);
3562
3563         intel_crtc_update_cursor(crtc, false);
3564         intel_disable_planes(crtc);
3565         intel_disable_plane(dev_priv, plane, pipe);
3566
3567         if (intel_crtc->config.has_pch_encoder)
3568                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3569         intel_disable_pipe(dev_priv, pipe);
3570
3571         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3572
3573         ironlake_pfit_disable(intel_crtc);
3574
3575         intel_ddi_disable_pipe_clock(intel_crtc);
3576
3577         for_each_encoder_on_crtc(dev, crtc, encoder)
3578                 if (encoder->post_disable)
3579                         encoder->post_disable(encoder);
3580
3581         if (intel_crtc->config.has_pch_encoder) {
3582                 lpt_disable_pch_transcoder(dev_priv);
3583                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3584                 intel_ddi_fdi_disable(crtc);
3585         }
3586
3587         intel_crtc->active = false;
3588         intel_update_watermarks(crtc);
3589
3590         mutex_lock(&dev->struct_mutex);
3591         intel_update_fbc(dev);
3592         mutex_unlock(&dev->struct_mutex);
3593 }
3594
3595 static void ironlake_crtc_off(struct drm_crtc *crtc)
3596 {
3597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3598         intel_put_shared_dpll(intel_crtc);
3599 }
3600
3601 static void haswell_crtc_off(struct drm_crtc *crtc)
3602 {
3603         intel_ddi_put_crtc_pll(crtc);
3604 }
3605
3606 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3607 {
3608         if (!enable && intel_crtc->overlay) {
3609                 struct drm_device *dev = intel_crtc->base.dev;
3610                 struct drm_i915_private *dev_priv = dev->dev_private;
3611
3612                 mutex_lock(&dev->struct_mutex);
3613                 dev_priv->mm.interruptible = false;
3614                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3615                 dev_priv->mm.interruptible = true;
3616                 mutex_unlock(&dev->struct_mutex);
3617         }
3618
3619         /* Let userspace switch the overlay on again. In most cases userspace
3620          * has to recompute where to put it anyway.
3621          */
3622 }
3623
3624 /**
3625  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3626  * cursor plane briefly if not already running after enabling the display
3627  * plane.
3628  * This workaround avoids occasional blank screens when self refresh is
3629  * enabled.
3630  */
3631 static void
3632 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3633 {
3634         u32 cntl = I915_READ(CURCNTR(pipe));
3635
3636         if ((cntl & CURSOR_MODE) == 0) {
3637                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3638
3639                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3640                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3641                 intel_wait_for_vblank(dev_priv->dev, pipe);
3642                 I915_WRITE(CURCNTR(pipe), cntl);
3643                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3644                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3645         }
3646 }
3647
3648 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3649 {
3650         struct drm_device *dev = crtc->base.dev;
3651         struct drm_i915_private *dev_priv = dev->dev_private;
3652         struct intel_crtc_config *pipe_config = &crtc->config;
3653
3654         if (!crtc->config.gmch_pfit.control)
3655                 return;
3656
3657         /*
3658          * The panel fitter should only be adjusted whilst the pipe is disabled,
3659          * according to register description and PRM.
3660          */
3661         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3662         assert_pipe_disabled(dev_priv, crtc->pipe);
3663
3664         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3665         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3666
3667         /* Border color in case we don't scale up to the full screen. Black by
3668          * default, change to something else for debugging. */
3669         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3670 }
3671
3672 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3673 {
3674         struct drm_device *dev = crtc->dev;
3675         struct drm_i915_private *dev_priv = dev->dev_private;
3676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677         struct intel_encoder *encoder;
3678         int pipe = intel_crtc->pipe;
3679         int plane = intel_crtc->plane;
3680         bool is_dsi;
3681
3682         WARN_ON(!crtc->enabled);
3683
3684         if (intel_crtc->active)
3685                 return;
3686
3687         intel_crtc->active = true;
3688
3689         for_each_encoder_on_crtc(dev, crtc, encoder)
3690                 if (encoder->pre_pll_enable)
3691                         encoder->pre_pll_enable(encoder);
3692
3693         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3694
3695         if (!is_dsi)
3696                 vlv_enable_pll(intel_crtc);
3697
3698         for_each_encoder_on_crtc(dev, crtc, encoder)
3699                 if (encoder->pre_enable)
3700                         encoder->pre_enable(encoder);
3701
3702         i9xx_pfit_enable(intel_crtc);
3703
3704         intel_crtc_load_lut(crtc);
3705
3706         intel_update_watermarks(crtc);
3707         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3708         intel_enable_plane(dev_priv, plane, pipe);
3709         intel_enable_planes(crtc);
3710         intel_crtc_update_cursor(crtc, true);
3711
3712         intel_update_fbc(dev);
3713
3714         for_each_encoder_on_crtc(dev, crtc, encoder)
3715                 encoder->enable(encoder);
3716 }
3717
3718 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3719 {
3720         struct drm_device *dev = crtc->dev;
3721         struct drm_i915_private *dev_priv = dev->dev_private;
3722         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3723         struct intel_encoder *encoder;
3724         int pipe = intel_crtc->pipe;
3725         int plane = intel_crtc->plane;
3726
3727         WARN_ON(!crtc->enabled);
3728
3729         if (intel_crtc->active)
3730                 return;
3731
3732         intel_crtc->active = true;
3733
3734         for_each_encoder_on_crtc(dev, crtc, encoder)
3735                 if (encoder->pre_enable)
3736                         encoder->pre_enable(encoder);
3737
3738         i9xx_enable_pll(intel_crtc);
3739
3740         i9xx_pfit_enable(intel_crtc);
3741
3742         intel_crtc_load_lut(crtc);
3743
3744         intel_update_watermarks(crtc);
3745         intel_enable_pipe(dev_priv, pipe, false, false);
3746         intel_enable_plane(dev_priv, plane, pipe);
3747         intel_enable_planes(crtc);
3748         /* The fixup needs to happen before cursor is enabled */
3749         if (IS_G4X(dev))
3750                 g4x_fixup_plane(dev_priv, pipe);
3751         intel_crtc_update_cursor(crtc, true);
3752
3753         /* Give the overlay scaler a chance to enable if it's on this pipe */
3754         intel_crtc_dpms_overlay(intel_crtc, true);
3755
3756         intel_update_fbc(dev);
3757
3758         for_each_encoder_on_crtc(dev, crtc, encoder)
3759                 encoder->enable(encoder);
3760 }
3761
3762 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->base.dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766
3767         if (!crtc->config.gmch_pfit.control)
3768                 return;
3769
3770         assert_pipe_disabled(dev_priv, crtc->pipe);
3771
3772         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3773                          I915_READ(PFIT_CONTROL));
3774         I915_WRITE(PFIT_CONTROL, 0);
3775 }
3776
3777 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3778 {
3779         struct drm_device *dev = crtc->dev;
3780         struct drm_i915_private *dev_priv = dev->dev_private;
3781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3782         struct intel_encoder *encoder;
3783         int pipe = intel_crtc->pipe;
3784         int plane = intel_crtc->plane;
3785
3786         if (!intel_crtc->active)
3787                 return;
3788
3789         for_each_encoder_on_crtc(dev, crtc, encoder)
3790                 encoder->disable(encoder);
3791
3792         /* Give the overlay scaler a chance to disable if it's on this pipe */
3793         intel_crtc_wait_for_pending_flips(crtc);
3794         drm_vblank_off(dev, pipe);
3795
3796         if (dev_priv->fbc.plane == plane)
3797                 intel_disable_fbc(dev);
3798
3799         intel_crtc_dpms_overlay(intel_crtc, false);
3800         intel_crtc_update_cursor(crtc, false);
3801         intel_disable_planes(crtc);
3802         intel_disable_plane(dev_priv, plane, pipe);
3803
3804         intel_disable_pipe(dev_priv, pipe);
3805
3806         i9xx_pfit_disable(intel_crtc);
3807
3808         for_each_encoder_on_crtc(dev, crtc, encoder)
3809                 if (encoder->post_disable)
3810                         encoder->post_disable(encoder);
3811
3812         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3813                 i9xx_disable_pll(dev_priv, pipe);
3814
3815         intel_crtc->active = false;
3816         intel_update_watermarks(crtc);
3817
3818         intel_update_fbc(dev);
3819 }
3820
3821 static void i9xx_crtc_off(struct drm_crtc *crtc)
3822 {
3823 }
3824
3825 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3826                                     bool enabled)
3827 {
3828         struct drm_device *dev = crtc->dev;
3829         struct drm_i915_master_private *master_priv;
3830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831         int pipe = intel_crtc->pipe;
3832
3833         if (!dev->primary->master)
3834                 return;
3835
3836         master_priv = dev->primary->master->driver_priv;
3837         if (!master_priv->sarea_priv)
3838                 return;
3839
3840         switch (pipe) {
3841         case 0:
3842                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3843                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3844                 break;
3845         case 1:
3846                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3847                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3848                 break;
3849         default:
3850                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3851                 break;
3852         }
3853 }
3854
3855 /**
3856  * Sets the power management mode of the pipe and plane.
3857  */
3858 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3859 {
3860         struct drm_device *dev = crtc->dev;
3861         struct drm_i915_private *dev_priv = dev->dev_private;
3862         struct intel_encoder *intel_encoder;
3863         bool enable = false;
3864
3865         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3866                 enable |= intel_encoder->connectors_active;
3867
3868         if (enable)
3869                 dev_priv->display.crtc_enable(crtc);
3870         else
3871                 dev_priv->display.crtc_disable(crtc);
3872
3873         intel_crtc_update_sarea(crtc, enable);
3874 }
3875
3876 static void intel_crtc_disable(struct drm_crtc *crtc)
3877 {
3878         struct drm_device *dev = crtc->dev;
3879         struct drm_connector *connector;
3880         struct drm_i915_private *dev_priv = dev->dev_private;
3881         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3882
3883         /* crtc should still be enabled when we disable it. */
3884         WARN_ON(!crtc->enabled);
3885
3886         dev_priv->display.crtc_disable(crtc);
3887         intel_crtc->eld_vld = false;
3888         intel_crtc_update_sarea(crtc, false);
3889         dev_priv->display.off(crtc);
3890
3891         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3892         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
3893         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3894
3895         if (crtc->fb) {
3896                 mutex_lock(&dev->struct_mutex);
3897                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3898                 mutex_unlock(&dev->struct_mutex);
3899                 crtc->fb = NULL;
3900         }
3901
3902         /* Update computed state. */
3903         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3904                 if (!connector->encoder || !connector->encoder->crtc)
3905                         continue;
3906
3907                 if (connector->encoder->crtc != crtc)
3908                         continue;
3909
3910                 connector->dpms = DRM_MODE_DPMS_OFF;
3911                 to_intel_encoder(connector->encoder)->connectors_active = false;
3912         }
3913 }
3914
3915 void intel_encoder_destroy(struct drm_encoder *encoder)
3916 {
3917         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3918
3919         drm_encoder_cleanup(encoder);
3920         kfree(intel_encoder);
3921 }
3922
3923 /* Simple dpms helper for encoders with just one connector, no cloning and only
3924  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3925  * state of the entire output pipe. */
3926 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3927 {
3928         if (mode == DRM_MODE_DPMS_ON) {
3929                 encoder->connectors_active = true;
3930
3931                 intel_crtc_update_dpms(encoder->base.crtc);
3932         } else {
3933                 encoder->connectors_active = false;
3934
3935                 intel_crtc_update_dpms(encoder->base.crtc);
3936         }
3937 }
3938
3939 /* Cross check the actual hw state with our own modeset state tracking (and it's
3940  * internal consistency). */
3941 static void intel_connector_check_state(struct intel_connector *connector)
3942 {
3943         if (connector->get_hw_state(connector)) {
3944                 struct intel_encoder *encoder = connector->encoder;
3945                 struct drm_crtc *crtc;
3946                 bool encoder_enabled;
3947                 enum pipe pipe;
3948
3949                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3950                               connector->base.base.id,
3951                               drm_get_connector_name(&connector->base));
3952
3953                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3954                      "wrong connector dpms state\n");
3955                 WARN(connector->base.encoder != &encoder->base,
3956                      "active connector not linked to encoder\n");
3957                 WARN(!encoder->connectors_active,
3958                      "encoder->connectors_active not set\n");
3959
3960                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3961                 WARN(!encoder_enabled, "encoder not enabled\n");
3962                 if (WARN_ON(!encoder->base.crtc))
3963                         return;
3964
3965                 crtc = encoder->base.crtc;
3966
3967                 WARN(!crtc->enabled, "crtc not enabled\n");
3968                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3969                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3970                      "encoder active on the wrong pipe\n");
3971         }
3972 }
3973
3974 /* Even simpler default implementation, if there's really no special case to
3975  * consider. */
3976 void intel_connector_dpms(struct drm_connector *connector, int mode)
3977 {
3978         struct intel_encoder *encoder = intel_attached_encoder(connector);
3979
3980         /* All the simple cases only support two dpms states. */
3981         if (mode != DRM_MODE_DPMS_ON)
3982                 mode = DRM_MODE_DPMS_OFF;
3983
3984         if (mode == connector->dpms)
3985                 return;
3986
3987         connector->dpms = mode;
3988
3989         /* Only need to change hw state when actually enabled */
3990         if (encoder->base.crtc)
3991                 intel_encoder_dpms(encoder, mode);
3992         else
3993                 WARN_ON(encoder->connectors_active != false);
3994
3995         intel_modeset_check_state(connector->dev);
3996 }
3997
3998 /* Simple connector->get_hw_state implementation for encoders that support only
3999  * one connector and no cloning and hence the encoder state determines the state
4000  * of the connector. */
4001 bool intel_connector_get_hw_state(struct intel_connector *connector)
4002 {
4003         enum pipe pipe = 0;
4004         struct intel_encoder *encoder = connector->encoder;
4005
4006         return encoder->get_hw_state(encoder, &pipe);
4007 }
4008
4009 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4010                                      struct intel_crtc_config *pipe_config)
4011 {
4012         struct drm_i915_private *dev_priv = dev->dev_private;
4013         struct intel_crtc *pipe_B_crtc =
4014                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4015
4016         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4017                       pipe_name(pipe), pipe_config->fdi_lanes);
4018         if (pipe_config->fdi_lanes > 4) {
4019                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4020                               pipe_name(pipe), pipe_config->fdi_lanes);
4021                 return false;
4022         }
4023
4024         if (IS_HASWELL(dev)) {
4025                 if (pipe_config->fdi_lanes > 2) {
4026                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4027                                       pipe_config->fdi_lanes);
4028                         return false;
4029                 } else {
4030                         return true;
4031                 }
4032         }
4033
4034         if (INTEL_INFO(dev)->num_pipes == 2)
4035                 return true;
4036
4037         /* Ivybridge 3 pipe is really complicated */
4038         switch (pipe) {
4039         case PIPE_A:
4040                 return true;
4041         case PIPE_B:
4042                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4043                     pipe_config->fdi_lanes > 2) {
4044                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4045                                       pipe_name(pipe), pipe_config->fdi_lanes);
4046                         return false;
4047                 }
4048                 return true;
4049         case PIPE_C:
4050                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4051                     pipe_B_crtc->config.fdi_lanes <= 2) {
4052                         if (pipe_config->fdi_lanes > 2) {
4053                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4054                                               pipe_name(pipe), pipe_config->fdi_lanes);
4055                                 return false;
4056                         }
4057                 } else {
4058                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4059                         return false;
4060                 }
4061                 return true;
4062         default:
4063                 BUG();
4064         }
4065 }
4066
4067 #define RETRY 1
4068 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4069                                        struct intel_crtc_config *pipe_config)
4070 {
4071         struct drm_device *dev = intel_crtc->base.dev;
4072         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4073         int lane, link_bw, fdi_dotclock;
4074         bool setup_ok, needs_recompute = false;
4075
4076 retry:
4077         /* FDI is a binary signal running at ~2.7GHz, encoding
4078          * each output octet as 10 bits. The actual frequency
4079          * is stored as a divider into a 100MHz clock, and the
4080          * mode pixel clock is stored in units of 1KHz.
4081          * Hence the bw of each lane in terms of the mode signal
4082          * is:
4083          */
4084         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4085
4086         fdi_dotclock = adjusted_mode->clock;
4087
4088         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4089                                            pipe_config->pipe_bpp);
4090
4091         pipe_config->fdi_lanes = lane;
4092
4093         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4094                                link_bw, &pipe_config->fdi_m_n);
4095
4096         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4097                                             intel_crtc->pipe, pipe_config);
4098         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4099                 pipe_config->pipe_bpp -= 2*3;
4100                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4101                               pipe_config->pipe_bpp);
4102                 needs_recompute = true;
4103                 pipe_config->bw_constrained = true;
4104
4105                 goto retry;
4106         }
4107
4108         if (needs_recompute)
4109                 return RETRY;
4110
4111         return setup_ok ? 0 : -EINVAL;
4112 }
4113
4114 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4115                                    struct intel_crtc_config *pipe_config)
4116 {
4117         pipe_config->ips_enabled = i915_enable_ips &&
4118                                    hsw_crtc_supports_ips(crtc) &&
4119                                    pipe_config->pipe_bpp <= 24;
4120 }
4121
4122 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4123                                      struct intel_crtc_config *pipe_config)
4124 {
4125         struct drm_device *dev = crtc->base.dev;
4126         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4127
4128         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4130          */
4131         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4133                 return -EINVAL;
4134
4135         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4136                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4137         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4138                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139                  * for lvds. */
4140                 pipe_config->pipe_bpp = 8*3;
4141         }
4142
4143         if (HAS_IPS(dev))
4144                 hsw_compute_ips_config(crtc, pipe_config);
4145
4146         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4147          * clock survives for now. */
4148         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4149                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4150
4151         if (pipe_config->has_pch_encoder)
4152                 return ironlake_fdi_compute_config(crtc, pipe_config);
4153
4154         return 0;
4155 }
4156
4157 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4158 {
4159         return 400000; /* FIXME */
4160 }
4161
4162 static int i945_get_display_clock_speed(struct drm_device *dev)
4163 {
4164         return 400000;
4165 }
4166
4167 static int i915_get_display_clock_speed(struct drm_device *dev)
4168 {
4169         return 333000;
4170 }
4171
4172 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4173 {
4174         return 200000;
4175 }
4176
4177 static int pnv_get_display_clock_speed(struct drm_device *dev)
4178 {
4179         u16 gcfgc = 0;
4180
4181         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4182
4183         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4184         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4185                 return 267000;
4186         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4187                 return 333000;
4188         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4189                 return 444000;
4190         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4191                 return 200000;
4192         default:
4193                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4194         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4195                 return 133000;
4196         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4197                 return 167000;
4198         }
4199 }
4200
4201 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4202 {
4203         u16 gcfgc = 0;
4204
4205         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4206
4207         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4208                 return 133000;
4209         else {
4210                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4211                 case GC_DISPLAY_CLOCK_333_MHZ:
4212                         return 333000;
4213                 default:
4214                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4215                         return 190000;
4216                 }
4217         }
4218 }
4219
4220 static int i865_get_display_clock_speed(struct drm_device *dev)
4221 {
4222         return 266000;
4223 }
4224
4225 static int i855_get_display_clock_speed(struct drm_device *dev)
4226 {
4227         u16 hpllcc = 0;
4228         /* Assume that the hardware is in the high speed state.  This
4229          * should be the default.
4230          */
4231         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4232         case GC_CLOCK_133_200:
4233         case GC_CLOCK_100_200:
4234                 return 200000;
4235         case GC_CLOCK_166_250:
4236                 return 250000;
4237         case GC_CLOCK_100_133:
4238                 return 133000;
4239         }
4240
4241         /* Shouldn't happen */
4242         return 0;
4243 }
4244
4245 static int i830_get_display_clock_speed(struct drm_device *dev)
4246 {
4247         return 133000;
4248 }
4249
4250 static void
4251 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4252 {
4253         while (*num > DATA_LINK_M_N_MASK ||
4254                *den > DATA_LINK_M_N_MASK) {
4255                 *num >>= 1;
4256                 *den >>= 1;
4257         }
4258 }
4259
4260 static void compute_m_n(unsigned int m, unsigned int n,
4261                         uint32_t *ret_m, uint32_t *ret_n)
4262 {
4263         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4264         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4265         intel_reduce_m_n_ratio(ret_m, ret_n);
4266 }
4267
4268 void
4269 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4270                        int pixel_clock, int link_clock,
4271                        struct intel_link_m_n *m_n)
4272 {
4273         m_n->tu = 64;
4274
4275         compute_m_n(bits_per_pixel * pixel_clock,
4276                     link_clock * nlanes * 8,
4277                     &m_n->gmch_m, &m_n->gmch_n);
4278
4279         compute_m_n(pixel_clock, link_clock,
4280                     &m_n->link_m, &m_n->link_n);
4281 }
4282
4283 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4284 {
4285         if (i915_panel_use_ssc >= 0)
4286                 return i915_panel_use_ssc != 0;
4287         return dev_priv->vbt.lvds_use_ssc
4288                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4289 }
4290
4291 static int vlv_get_refclk(struct drm_crtc *crtc)
4292 {
4293         struct drm_device *dev = crtc->dev;
4294         struct drm_i915_private *dev_priv = dev->dev_private;
4295         int refclk = 27000; /* for DP & HDMI */
4296
4297         return 100000; /* only one validated so far */
4298
4299         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4300                 refclk = 96000;
4301         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4302                 if (intel_panel_use_ssc(dev_priv))
4303                         refclk = 100000;
4304                 else
4305                         refclk = 96000;
4306         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4307                 refclk = 100000;
4308         }
4309
4310         return refclk;
4311 }
4312
4313 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4314 {
4315         struct drm_device *dev = crtc->dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         int refclk;
4318
4319         if (IS_VALLEYVIEW(dev)) {
4320                 refclk = vlv_get_refclk(crtc);
4321         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4322             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4323                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4324                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4325                               refclk / 1000);
4326         } else if (!IS_GEN2(dev)) {
4327                 refclk = 96000;
4328         } else {
4329                 refclk = 48000;
4330         }
4331
4332         return refclk;
4333 }
4334
4335 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4336 {
4337         return (1 << dpll->n) << 16 | dpll->m2;
4338 }
4339
4340 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4341 {
4342         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4343 }
4344
4345 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4346                                      intel_clock_t *reduced_clock)
4347 {
4348         struct drm_device *dev = crtc->base.dev;
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350         int pipe = crtc->pipe;
4351         u32 fp, fp2 = 0;
4352
4353         if (IS_PINEVIEW(dev)) {
4354                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4355                 if (reduced_clock)
4356                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4357         } else {
4358                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4359                 if (reduced_clock)
4360                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4361         }
4362
4363         I915_WRITE(FP0(pipe), fp);
4364         crtc->config.dpll_hw_state.fp0 = fp;
4365
4366         crtc->lowfreq_avail = false;
4367         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4368             reduced_clock && i915_powersave) {
4369                 I915_WRITE(FP1(pipe), fp2);
4370                 crtc->config.dpll_hw_state.fp1 = fp2;
4371                 crtc->lowfreq_avail = true;
4372         } else {
4373                 I915_WRITE(FP1(pipe), fp);
4374                 crtc->config.dpll_hw_state.fp1 = fp;
4375         }
4376 }
4377
4378 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4379                 pipe)
4380 {
4381         u32 reg_val;
4382
4383         /*
4384          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4385          * and set it to a reasonable value instead.
4386          */
4387         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4388         reg_val &= 0xffffff00;
4389         reg_val |= 0x00000030;
4390         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4391
4392         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4393         reg_val &= 0x8cffffff;
4394         reg_val = 0x8c000000;
4395         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4396
4397         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4398         reg_val &= 0xffffff00;
4399         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4400
4401         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4402         reg_val &= 0x00ffffff;
4403         reg_val |= 0xb0000000;
4404         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4405 }
4406
4407 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4408                                          struct intel_link_m_n *m_n)
4409 {
4410         struct drm_device *dev = crtc->base.dev;
4411         struct drm_i915_private *dev_priv = dev->dev_private;
4412         int pipe = crtc->pipe;
4413
4414         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4415         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4416         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4417         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4418 }
4419
4420 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4421                                          struct intel_link_m_n *m_n)
4422 {
4423         struct drm_device *dev = crtc->base.dev;
4424         struct drm_i915_private *dev_priv = dev->dev_private;
4425         int pipe = crtc->pipe;
4426         enum transcoder transcoder = crtc->config.cpu_transcoder;
4427
4428         if (INTEL_INFO(dev)->gen >= 5) {
4429                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4430                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4431                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4432                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4433         } else {
4434                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4435                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4436                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4437                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4438         }
4439 }
4440
4441 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4442 {
4443         if (crtc->config.has_pch_encoder)
4444                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4445         else
4446                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4447 }
4448
4449 static void vlv_update_pll(struct intel_crtc *crtc)
4450 {
4451         struct drm_device *dev = crtc->base.dev;
4452         struct drm_i915_private *dev_priv = dev->dev_private;
4453         int pipe = crtc->pipe;
4454         u32 dpll, mdiv;
4455         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4456         u32 coreclk, reg_val, dpll_md;
4457
4458         mutex_lock(&dev_priv->dpio_lock);
4459
4460         bestn = crtc->config.dpll.n;
4461         bestm1 = crtc->config.dpll.m1;
4462         bestm2 = crtc->config.dpll.m2;
4463         bestp1 = crtc->config.dpll.p1;
4464         bestp2 = crtc->config.dpll.p2;
4465
4466         /* See eDP HDMI DPIO driver vbios notes doc */
4467
4468         /* PLL B needs special handling */
4469         if (pipe)
4470                 vlv_pllb_recal_opamp(dev_priv, pipe);
4471
4472         /* Set up Tx target for periodic Rcomp update */
4473         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4474
4475         /* Disable target IRef on PLL */
4476         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4477         reg_val &= 0x00ffffff;
4478         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4479
4480         /* Disable fast lock */
4481         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4482
4483         /* Set idtafcrecal before PLL is enabled */
4484         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4485         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4486         mdiv |= ((bestn << DPIO_N_SHIFT));
4487         mdiv |= (1 << DPIO_K_SHIFT);
4488
4489         /*
4490          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4491          * but we don't support that).
4492          * Note: don't use the DAC post divider as it seems unstable.
4493          */
4494         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4495         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4496
4497         mdiv |= DPIO_ENABLE_CALIBRATION;
4498         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4499
4500         /* Set HBR and RBR LPF coefficients */
4501         if (crtc->config.port_clock == 162000 ||
4502             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4503             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4504                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4505                                  0x009f0003);
4506         else
4507                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4508                                  0x00d0000f);
4509
4510         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4511             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4512                 /* Use SSC source */
4513                 if (!pipe)
4514                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4515                                          0x0df40000);
4516                 else
4517                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4518                                          0x0df70000);
4519         } else { /* HDMI or VGA */
4520                 /* Use bend source */
4521                 if (!pipe)
4522                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4523                                          0x0df70000);
4524                 else
4525                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4526                                          0x0df40000);
4527         }
4528
4529         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4530         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4531         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4532             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4533                 coreclk |= 0x01000000;
4534         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4535
4536         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4537
4538         /* Enable DPIO clock input */
4539         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4540                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4541         if (pipe)
4542                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4543
4544         dpll |= DPLL_VCO_ENABLE;
4545         crtc->config.dpll_hw_state.dpll = dpll;
4546
4547         dpll_md = (crtc->config.pixel_multiplier - 1)
4548                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4549         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4550
4551         if (crtc->config.has_dp_encoder)
4552                 intel_dp_set_m_n(crtc);
4553
4554         mutex_unlock(&dev_priv->dpio_lock);
4555 }
4556
4557 static void i9xx_update_pll(struct intel_crtc *crtc,
4558                             intel_clock_t *reduced_clock,
4559                             int num_connectors)
4560 {
4561         struct drm_device *dev = crtc->base.dev;
4562         struct drm_i915_private *dev_priv = dev->dev_private;
4563         u32 dpll;
4564         bool is_sdvo;
4565         struct dpll *clock = &crtc->config.dpll;
4566
4567         i9xx_update_pll_dividers(crtc, reduced_clock);
4568
4569         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4570                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4571
4572         dpll = DPLL_VGA_MODE_DIS;
4573
4574         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4575                 dpll |= DPLLB_MODE_LVDS;
4576         else
4577                 dpll |= DPLLB_MODE_DAC_SERIAL;
4578
4579         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4580                 dpll |= (crtc->config.pixel_multiplier - 1)
4581                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4582         }
4583
4584         if (is_sdvo)
4585                 dpll |= DPLL_SDVO_HIGH_SPEED;
4586
4587         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4588                 dpll |= DPLL_SDVO_HIGH_SPEED;
4589
4590         /* compute bitmask from p1 value */
4591         if (IS_PINEVIEW(dev))
4592                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4593         else {
4594                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4595                 if (IS_G4X(dev) && reduced_clock)
4596                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4597         }
4598         switch (clock->p2) {
4599         case 5:
4600                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4601                 break;
4602         case 7:
4603                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4604                 break;
4605         case 10:
4606                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4607                 break;
4608         case 14:
4609                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4610                 break;
4611         }
4612         if (INTEL_INFO(dev)->gen >= 4)
4613                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4614
4615         if (crtc->config.sdvo_tv_clock)
4616                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4617         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4618                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4619                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4620         else
4621                 dpll |= PLL_REF_INPUT_DREFCLK;
4622
4623         dpll |= DPLL_VCO_ENABLE;
4624         crtc->config.dpll_hw_state.dpll = dpll;
4625
4626         if (INTEL_INFO(dev)->gen >= 4) {
4627                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4628                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4629                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4630         }
4631
4632         if (crtc->config.has_dp_encoder)
4633                 intel_dp_set_m_n(crtc);
4634 }
4635
4636 static void i8xx_update_pll(struct intel_crtc *crtc,
4637                             intel_clock_t *reduced_clock,
4638                             int num_connectors)
4639 {
4640         struct drm_device *dev = crtc->base.dev;
4641         struct drm_i915_private *dev_priv = dev->dev_private;
4642         u32 dpll;
4643         struct dpll *clock = &crtc->config.dpll;
4644
4645         i9xx_update_pll_dividers(crtc, reduced_clock);
4646
4647         dpll = DPLL_VGA_MODE_DIS;
4648
4649         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4650                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4651         } else {
4652                 if (clock->p1 == 2)
4653                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4654                 else
4655                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4656                 if (clock->p2 == 4)
4657                         dpll |= PLL_P2_DIVIDE_BY_4;
4658         }
4659
4660         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4661                 dpll |= DPLL_DVO_2X_MODE;
4662
4663         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4664                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4665                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4666         else
4667                 dpll |= PLL_REF_INPUT_DREFCLK;
4668
4669         dpll |= DPLL_VCO_ENABLE;
4670         crtc->config.dpll_hw_state.dpll = dpll;
4671 }
4672
4673 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4674 {
4675         struct drm_device *dev = intel_crtc->base.dev;
4676         struct drm_i915_private *dev_priv = dev->dev_private;
4677         enum pipe pipe = intel_crtc->pipe;
4678         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4679         struct drm_display_mode *adjusted_mode =
4680                 &intel_crtc->config.adjusted_mode;
4681         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4682         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4683
4684         /* We need to be careful not to changed the adjusted mode, for otherwise
4685          * the hw state checker will get angry at the mismatch. */
4686         crtc_vtotal = adjusted_mode->crtc_vtotal;
4687         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4688
4689         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4690                 /* the chip adds 2 halflines automatically */
4691                 crtc_vtotal -= 1;
4692                 crtc_vblank_end -= 1;
4693                 vsyncshift = adjusted_mode->crtc_hsync_start
4694                              - adjusted_mode->crtc_htotal / 2;
4695         } else {
4696                 vsyncshift = 0;
4697         }
4698
4699         if (INTEL_INFO(dev)->gen > 3)
4700                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4701
4702         I915_WRITE(HTOTAL(cpu_transcoder),
4703                    (adjusted_mode->crtc_hdisplay - 1) |
4704                    ((adjusted_mode->crtc_htotal - 1) << 16));
4705         I915_WRITE(HBLANK(cpu_transcoder),
4706                    (adjusted_mode->crtc_hblank_start - 1) |
4707                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4708         I915_WRITE(HSYNC(cpu_transcoder),
4709                    (adjusted_mode->crtc_hsync_start - 1) |
4710                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4711
4712         I915_WRITE(VTOTAL(cpu_transcoder),
4713                    (adjusted_mode->crtc_vdisplay - 1) |
4714                    ((crtc_vtotal - 1) << 16));
4715         I915_WRITE(VBLANK(cpu_transcoder),
4716                    (adjusted_mode->crtc_vblank_start - 1) |
4717                    ((crtc_vblank_end - 1) << 16));
4718         I915_WRITE(VSYNC(cpu_transcoder),
4719                    (adjusted_mode->crtc_vsync_start - 1) |
4720                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4721
4722         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4723          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4724          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4725          * bits. */
4726         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4727             (pipe == PIPE_B || pipe == PIPE_C))
4728                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4729
4730         /* pipesrc controls the size that is scaled from, which should
4731          * always be the user's requested size.
4732          */
4733         I915_WRITE(PIPESRC(pipe),
4734                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4735 }
4736
4737 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4738                                    struct intel_crtc_config *pipe_config)
4739 {
4740         struct drm_device *dev = crtc->base.dev;
4741         struct drm_i915_private *dev_priv = dev->dev_private;
4742         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4743         uint32_t tmp;
4744
4745         tmp = I915_READ(HTOTAL(cpu_transcoder));
4746         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4747         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4748         tmp = I915_READ(HBLANK(cpu_transcoder));
4749         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4750         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4751         tmp = I915_READ(HSYNC(cpu_transcoder));
4752         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4753         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4754
4755         tmp = I915_READ(VTOTAL(cpu_transcoder));
4756         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4757         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4758         tmp = I915_READ(VBLANK(cpu_transcoder));
4759         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4760         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4761         tmp = I915_READ(VSYNC(cpu_transcoder));
4762         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4763         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4764
4765         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4766                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4767                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4768                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4769         }
4770
4771         tmp = I915_READ(PIPESRC(crtc->pipe));
4772         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4773         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4774 }
4775
4776 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4777                                              struct intel_crtc_config *pipe_config)
4778 {
4779         struct drm_crtc *crtc = &intel_crtc->base;
4780
4781         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4782         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4783         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4784         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4785
4786         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4787         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4788         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4789         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4790
4791         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4792
4793         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4794         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4795 }
4796
4797 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4798 {
4799         struct drm_device *dev = intel_crtc->base.dev;
4800         struct drm_i915_private *dev_priv = dev->dev_private;
4801         uint32_t pipeconf;
4802
4803         pipeconf = 0;
4804
4805         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4806                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4807                  * core speed.
4808                  *
4809                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4810                  * pipe == 0 check?
4811                  */
4812                 if (intel_crtc->config.requested_mode.clock >
4813                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4814                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4815         }
4816
4817         /* only g4x and later have fancy bpc/dither controls */
4818         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4819                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4820                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4821                         pipeconf |= PIPECONF_DITHER_EN |
4822                                     PIPECONF_DITHER_TYPE_SP;
4823
4824                 switch (intel_crtc->config.pipe_bpp) {
4825                 case 18:
4826                         pipeconf |= PIPECONF_6BPC;
4827                         break;
4828                 case 24:
4829                         pipeconf |= PIPECONF_8BPC;
4830                         break;
4831                 case 30:
4832                         pipeconf |= PIPECONF_10BPC;
4833                         break;
4834                 default:
4835                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4836                         BUG();
4837                 }
4838         }
4839
4840         if (HAS_PIPE_CXSR(dev)) {
4841                 if (intel_crtc->lowfreq_avail) {
4842                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4843                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4844                 } else {
4845                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4846                 }
4847         }
4848
4849         if (!IS_GEN2(dev) &&
4850             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4851                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4852         else
4853                 pipeconf |= PIPECONF_PROGRESSIVE;
4854
4855         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4856                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4857
4858         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4859         POSTING_READ(PIPECONF(intel_crtc->pipe));
4860 }
4861
4862 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4863                               int x, int y,
4864                               struct drm_framebuffer *fb)
4865 {
4866         struct drm_device *dev = crtc->dev;
4867         struct drm_i915_private *dev_priv = dev->dev_private;
4868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4869         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4870         int pipe = intel_crtc->pipe;
4871         int plane = intel_crtc->plane;
4872         int refclk, num_connectors = 0;
4873         intel_clock_t clock, reduced_clock;
4874         u32 dspcntr;
4875         bool ok, has_reduced_clock = false;
4876         bool is_lvds = false, is_dsi = false;
4877         struct intel_encoder *encoder;
4878         const intel_limit_t *limit;
4879         int ret;
4880
4881         for_each_encoder_on_crtc(dev, crtc, encoder) {
4882                 switch (encoder->type) {
4883                 case INTEL_OUTPUT_LVDS:
4884                         is_lvds = true;
4885                         break;
4886                 case INTEL_OUTPUT_DSI:
4887                         is_dsi = true;
4888                         break;
4889                 }
4890
4891                 num_connectors++;
4892         }
4893
4894         refclk = i9xx_get_refclk(crtc, num_connectors);
4895
4896         if (!is_dsi && !intel_crtc->config.clock_set) {
4897                 /*
4898                  * Returns a set of divisors for the desired target clock with
4899                  * the given refclk, or FALSE.  The returned values represent
4900                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4901                  * 2) / p1 / p2.
4902                  */
4903                 limit = intel_limit(crtc, refclk);
4904                 ok = dev_priv->display.find_dpll(limit, crtc,
4905                                                  intel_crtc->config.port_clock,
4906                                                  refclk, NULL, &clock);
4907                 if (!ok && !intel_crtc->config.clock_set) {
4908                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
4909                         return -EINVAL;
4910                 }
4911         }
4912
4913         /* Ensure that the cursor is valid for the new mode before changing... */
4914         intel_crtc_update_cursor(crtc, true);
4915
4916         if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
4917                 /*
4918                  * Ensure we match the reduced clock's P to the target clock.
4919                  * If the clocks don't match, we can't switch the display clock
4920                  * by using the FP0/FP1. In such case we will disable the LVDS
4921                  * downclock feature.
4922                 */
4923                 limit = intel_limit(crtc, refclk);
4924                 has_reduced_clock =
4925                         dev_priv->display.find_dpll(limit, crtc,
4926                                                     dev_priv->lvds_downclock,
4927                                                     refclk, &clock,
4928                                                     &reduced_clock);
4929         }
4930         /* Compat-code for transition, will disappear. */
4931         if (!intel_crtc->config.clock_set) {
4932                 intel_crtc->config.dpll.n = clock.n;
4933                 intel_crtc->config.dpll.m1 = clock.m1;
4934                 intel_crtc->config.dpll.m2 = clock.m2;
4935                 intel_crtc->config.dpll.p1 = clock.p1;
4936                 intel_crtc->config.dpll.p2 = clock.p2;
4937         }
4938
4939         if (IS_GEN2(dev)) {
4940                 i8xx_update_pll(intel_crtc,
4941                                 has_reduced_clock ? &reduced_clock : NULL,
4942                                 num_connectors);
4943         } else if (IS_VALLEYVIEW(dev)) {
4944                 if (!is_dsi)
4945                         vlv_update_pll(intel_crtc);
4946         } else {
4947                 i9xx_update_pll(intel_crtc,
4948                                 has_reduced_clock ? &reduced_clock : NULL,
4949                                 num_connectors);
4950         }
4951
4952         /* Set up the display plane register */
4953         dspcntr = DISPPLANE_GAMMA_ENABLE;
4954
4955         if (!IS_VALLEYVIEW(dev)) {
4956                 if (pipe == 0)
4957                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4958                 else
4959                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4960         }
4961
4962         intel_set_pipe_timings(intel_crtc);
4963
4964         /* pipesrc and dspsize control the size that is scaled from,
4965          * which should always be the user's requested size.
4966          */
4967         I915_WRITE(DSPSIZE(plane),
4968                    ((mode->vdisplay - 1) << 16) |
4969                    (mode->hdisplay - 1));
4970         I915_WRITE(DSPPOS(plane), 0);
4971
4972         i9xx_set_pipeconf(intel_crtc);
4973
4974         I915_WRITE(DSPCNTR(plane), dspcntr);
4975         POSTING_READ(DSPCNTR(plane));
4976
4977         ret = intel_pipe_set_base(crtc, x, y, fb);
4978
4979         return ret;
4980 }
4981
4982 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4983                                  struct intel_crtc_config *pipe_config)
4984 {
4985         struct drm_device *dev = crtc->base.dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987         uint32_t tmp;
4988
4989         tmp = I915_READ(PFIT_CONTROL);
4990         if (!(tmp & PFIT_ENABLE))
4991                 return;
4992
4993         /* Check whether the pfit is attached to our pipe. */
4994         if (INTEL_INFO(dev)->gen < 4) {
4995                 if (crtc->pipe != PIPE_B)
4996                         return;
4997         } else {
4998                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4999                         return;
5000         }
5001
5002         pipe_config->gmch_pfit.control = tmp;
5003         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5004         if (INTEL_INFO(dev)->gen < 5)
5005                 pipe_config->gmch_pfit.lvds_border_bits =
5006                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5007 }
5008
5009 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5010                                  struct intel_crtc_config *pipe_config)
5011 {
5012         struct drm_device *dev = crtc->base.dev;
5013         struct drm_i915_private *dev_priv = dev->dev_private;
5014         uint32_t tmp;
5015
5016         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5017         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5018
5019         tmp = I915_READ(PIPECONF(crtc->pipe));
5020         if (!(tmp & PIPECONF_ENABLE))
5021                 return false;
5022
5023         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5024                 switch (tmp & PIPECONF_BPC_MASK) {
5025                 case PIPECONF_6BPC:
5026                         pipe_config->pipe_bpp = 18;
5027                         break;
5028                 case PIPECONF_8BPC:
5029                         pipe_config->pipe_bpp = 24;
5030                         break;
5031                 case PIPECONF_10BPC:
5032                         pipe_config->pipe_bpp = 30;
5033                         break;
5034                 default:
5035                         break;
5036                 }
5037         }
5038
5039         intel_get_pipe_timings(crtc, pipe_config);
5040
5041         i9xx_get_pfit_config(crtc, pipe_config);
5042
5043         if (INTEL_INFO(dev)->gen >= 4) {
5044                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5045                 pipe_config->pixel_multiplier =
5046                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5047                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5048                 pipe_config->dpll_hw_state.dpll_md = tmp;
5049         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5050                 tmp = I915_READ(DPLL(crtc->pipe));
5051                 pipe_config->pixel_multiplier =
5052                         ((tmp & SDVO_MULTIPLIER_MASK)
5053                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5054         } else {
5055                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5056                  * port and will be fixed up in the encoder->get_config
5057                  * function. */
5058                 pipe_config->pixel_multiplier = 1;
5059         }
5060         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5061         if (!IS_VALLEYVIEW(dev)) {
5062                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5063                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5064         } else {
5065                 /* Mask out read-only status bits. */
5066                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5067                                                      DPLL_PORTC_READY_MASK |
5068                                                      DPLL_PORTB_READY_MASK);
5069         }
5070
5071         return true;
5072 }
5073
5074 static void ironlake_init_pch_refclk(struct drm_device *dev)
5075 {
5076         struct drm_i915_private *dev_priv = dev->dev_private;
5077         struct drm_mode_config *mode_config = &dev->mode_config;
5078         struct intel_encoder *encoder;
5079         u32 val, final;
5080         bool has_lvds = false;
5081         bool has_cpu_edp = false;
5082         bool has_panel = false;
5083         bool has_ck505 = false;
5084         bool can_ssc = false;
5085
5086         /* We need to take the global config into account */
5087         list_for_each_entry(encoder, &mode_config->encoder_list,
5088                             base.head) {
5089                 switch (encoder->type) {
5090                 case INTEL_OUTPUT_LVDS:
5091                         has_panel = true;
5092                         has_lvds = true;
5093                         break;
5094                 case INTEL_OUTPUT_EDP:
5095                         has_panel = true;
5096                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5097                                 has_cpu_edp = true;
5098                         break;
5099                 }
5100         }
5101
5102         if (HAS_PCH_IBX(dev)) {
5103                 has_ck505 = dev_priv->vbt.display_clock_mode;
5104                 can_ssc = has_ck505;
5105         } else {
5106                 has_ck505 = false;
5107                 can_ssc = true;
5108         }
5109
5110         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5111                       has_panel, has_lvds, has_ck505);
5112
5113         /* Ironlake: try to setup display ref clock before DPLL
5114          * enabling. This is only under driver's control after
5115          * PCH B stepping, previous chipset stepping should be
5116          * ignoring this setting.
5117          */
5118         val = I915_READ(PCH_DREF_CONTROL);
5119
5120         /* As we must carefully and slowly disable/enable each source in turn,
5121          * compute the final state we want first and check if we need to
5122          * make any changes at all.
5123          */
5124         final = val;
5125         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5126         if (has_ck505)
5127                 final |= DREF_NONSPREAD_CK505_ENABLE;
5128         else
5129                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5130
5131         final &= ~DREF_SSC_SOURCE_MASK;
5132         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5133         final &= ~DREF_SSC1_ENABLE;
5134
5135         if (has_panel) {
5136                 final |= DREF_SSC_SOURCE_ENABLE;
5137
5138                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5139                         final |= DREF_SSC1_ENABLE;
5140
5141                 if (has_cpu_edp) {
5142                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5143                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5144                         else
5145                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5146                 } else
5147                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5148         } else {
5149                 final |= DREF_SSC_SOURCE_DISABLE;
5150                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5151         }
5152
5153         if (final == val)
5154                 return;
5155
5156         /* Always enable nonspread source */
5157         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5158
5159         if (has_ck505)
5160                 val |= DREF_NONSPREAD_CK505_ENABLE;
5161         else
5162                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5163
5164         if (has_panel) {
5165                 val &= ~DREF_SSC_SOURCE_MASK;
5166                 val |= DREF_SSC_SOURCE_ENABLE;
5167
5168                 /* SSC must be turned on before enabling the CPU output  */
5169                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5170                         DRM_DEBUG_KMS("Using SSC on panel\n");
5171                         val |= DREF_SSC1_ENABLE;
5172                 } else
5173                         val &= ~DREF_SSC1_ENABLE;
5174
5175                 /* Get SSC going before enabling the outputs */
5176                 I915_WRITE(PCH_DREF_CONTROL, val);
5177                 POSTING_READ(PCH_DREF_CONTROL);
5178                 udelay(200);
5179
5180                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5181
5182                 /* Enable CPU source on CPU attached eDP */
5183                 if (has_cpu_edp) {
5184                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5185                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5186                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5187                         }
5188                         else
5189                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5190                 } else
5191                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5192
5193                 I915_WRITE(PCH_DREF_CONTROL, val);
5194                 POSTING_READ(PCH_DREF_CONTROL);
5195                 udelay(200);
5196         } else {
5197                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5198
5199                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5200
5201                 /* Turn off CPU output */
5202                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5203
5204                 I915_WRITE(PCH_DREF_CONTROL, val);
5205                 POSTING_READ(PCH_DREF_CONTROL);
5206                 udelay(200);
5207
5208                 /* Turn off the SSC source */
5209                 val &= ~DREF_SSC_SOURCE_MASK;
5210                 val |= DREF_SSC_SOURCE_DISABLE;
5211
5212                 /* Turn off SSC1 */
5213                 val &= ~DREF_SSC1_ENABLE;
5214
5215                 I915_WRITE(PCH_DREF_CONTROL, val);
5216                 POSTING_READ(PCH_DREF_CONTROL);
5217                 udelay(200);
5218         }
5219
5220         BUG_ON(val != final);
5221 }
5222
5223 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5224 {
5225         uint32_t tmp;
5226
5227         tmp = I915_READ(SOUTH_CHICKEN2);
5228         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5229         I915_WRITE(SOUTH_CHICKEN2, tmp);
5230
5231         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5232                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5233                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5234
5235         tmp = I915_READ(SOUTH_CHICKEN2);
5236         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5237         I915_WRITE(SOUTH_CHICKEN2, tmp);
5238
5239         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5240                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5241                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5242 }
5243
5244 /* WaMPhyProgramming:hsw */
5245 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5246 {
5247         uint32_t tmp;
5248
5249         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5250         tmp &= ~(0xFF << 24);
5251         tmp |= (0x12 << 24);
5252         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5253
5254         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5255         tmp |= (1 << 11);
5256         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5257
5258         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5259         tmp |= (1 << 11);
5260         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5261
5262         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5263         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5264         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5265
5266         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5267         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5268         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5269
5270         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5271         tmp &= ~(7 << 13);
5272         tmp |= (5 << 13);
5273         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5274
5275         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5276         tmp &= ~(7 << 13);
5277         tmp |= (5 << 13);
5278         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5279
5280         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5281         tmp &= ~0xFF;
5282         tmp |= 0x1C;
5283         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5284
5285         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5286         tmp &= ~0xFF;
5287         tmp |= 0x1C;
5288         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5289
5290         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5291         tmp &= ~(0xFF << 16);
5292         tmp |= (0x1C << 16);
5293         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5294
5295         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5296         tmp &= ~(0xFF << 16);
5297         tmp |= (0x1C << 16);
5298         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5299
5300         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5301         tmp |= (1 << 27);
5302         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5303
5304         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5305         tmp |= (1 << 27);
5306         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5307
5308         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5309         tmp &= ~(0xF << 28);
5310         tmp |= (4 << 28);
5311         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5312
5313         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5314         tmp &= ~(0xF << 28);
5315         tmp |= (4 << 28);
5316         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5317 }
5318
5319 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5320  * Programming" based on the parameters passed:
5321  * - Sequence to enable CLKOUT_DP
5322  * - Sequence to enable CLKOUT_DP without spread
5323  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5324  */
5325 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5326                                  bool with_fdi)
5327 {
5328         struct drm_i915_private *dev_priv = dev->dev_private;
5329         uint32_t reg, tmp;
5330
5331         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5332                 with_spread = true;
5333         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5334                  with_fdi, "LP PCH doesn't have FDI\n"))
5335                 with_fdi = false;
5336
5337         mutex_lock(&dev_priv->dpio_lock);
5338
5339         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5340         tmp &= ~SBI_SSCCTL_DISABLE;
5341         tmp |= SBI_SSCCTL_PATHALT;
5342         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5343
5344         udelay(24);
5345
5346         if (with_spread) {
5347                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5348                 tmp &= ~SBI_SSCCTL_PATHALT;
5349                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5350
5351                 if (with_fdi) {
5352                         lpt_reset_fdi_mphy(dev_priv);
5353                         lpt_program_fdi_mphy(dev_priv);
5354                 }
5355         }
5356
5357         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5358                SBI_GEN0 : SBI_DBUFF0;
5359         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5360         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5361         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5362
5363         mutex_unlock(&dev_priv->dpio_lock);
5364 }
5365
5366 /* Sequence to disable CLKOUT_DP */
5367 static void lpt_disable_clkout_dp(struct drm_device *dev)
5368 {
5369         struct drm_i915_private *dev_priv = dev->dev_private;
5370         uint32_t reg, tmp;
5371
5372         mutex_lock(&dev_priv->dpio_lock);
5373
5374         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5375                SBI_GEN0 : SBI_DBUFF0;
5376         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5377         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5378         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5379
5380         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5381         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5382                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5383                         tmp |= SBI_SSCCTL_PATHALT;
5384                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5385                         udelay(32);
5386                 }
5387                 tmp |= SBI_SSCCTL_DISABLE;
5388                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5389         }
5390
5391         mutex_unlock(&dev_priv->dpio_lock);
5392 }
5393
5394 static void lpt_init_pch_refclk(struct drm_device *dev)
5395 {
5396         struct drm_mode_config *mode_config = &dev->mode_config;
5397         struct intel_encoder *encoder;
5398         bool has_vga = false;
5399
5400         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5401                 switch (encoder->type) {
5402                 case INTEL_OUTPUT_ANALOG:
5403                         has_vga = true;
5404                         break;
5405                 }
5406         }
5407
5408         if (has_vga)
5409                 lpt_enable_clkout_dp(dev, true, true);
5410         else
5411                 lpt_disable_clkout_dp(dev);
5412 }
5413
5414 /*
5415  * Initialize reference clocks when the driver loads
5416  */
5417 void intel_init_pch_refclk(struct drm_device *dev)
5418 {
5419         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5420                 ironlake_init_pch_refclk(dev);
5421         else if (HAS_PCH_LPT(dev))
5422                 lpt_init_pch_refclk(dev);
5423 }
5424
5425 static int ironlake_get_refclk(struct drm_crtc *crtc)
5426 {
5427         struct drm_device *dev = crtc->dev;
5428         struct drm_i915_private *dev_priv = dev->dev_private;
5429         struct intel_encoder *encoder;
5430         int num_connectors = 0;
5431         bool is_lvds = false;
5432
5433         for_each_encoder_on_crtc(dev, crtc, encoder) {
5434                 switch (encoder->type) {
5435                 case INTEL_OUTPUT_LVDS:
5436                         is_lvds = true;
5437                         break;
5438                 }
5439                 num_connectors++;
5440         }
5441
5442         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5443                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5444                               dev_priv->vbt.lvds_ssc_freq);
5445                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5446         }
5447
5448         return 120000;
5449 }
5450
5451 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5452 {
5453         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5454         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5455         int pipe = intel_crtc->pipe;
5456         uint32_t val;
5457
5458         val = 0;
5459
5460         switch (intel_crtc->config.pipe_bpp) {
5461         case 18:
5462                 val |= PIPECONF_6BPC;
5463                 break;
5464         case 24:
5465                 val |= PIPECONF_8BPC;
5466                 break;
5467         case 30:
5468                 val |= PIPECONF_10BPC;
5469                 break;
5470         case 36:
5471                 val |= PIPECONF_12BPC;
5472                 break;
5473         default:
5474                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5475                 BUG();
5476         }
5477
5478         if (intel_crtc->config.dither)
5479                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5480
5481         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5482                 val |= PIPECONF_INTERLACED_ILK;
5483         else
5484                 val |= PIPECONF_PROGRESSIVE;
5485
5486         if (intel_crtc->config.limited_color_range)
5487                 val |= PIPECONF_COLOR_RANGE_SELECT;
5488
5489         I915_WRITE(PIPECONF(pipe), val);
5490         POSTING_READ(PIPECONF(pipe));
5491 }
5492
5493 /*
5494  * Set up the pipe CSC unit.
5495  *
5496  * Currently only full range RGB to limited range RGB conversion
5497  * is supported, but eventually this should handle various
5498  * RGB<->YCbCr scenarios as well.
5499  */
5500 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5501 {
5502         struct drm_device *dev = crtc->dev;
5503         struct drm_i915_private *dev_priv = dev->dev_private;
5504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5505         int pipe = intel_crtc->pipe;
5506         uint16_t coeff = 0x7800; /* 1.0 */
5507
5508         /*
5509          * TODO: Check what kind of values actually come out of the pipe
5510          * with these coeff/postoff values and adjust to get the best
5511          * accuracy. Perhaps we even need to take the bpc value into
5512          * consideration.
5513          */
5514
5515         if (intel_crtc->config.limited_color_range)
5516                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5517
5518         /*
5519          * GY/GU and RY/RU should be the other way around according
5520          * to BSpec, but reality doesn't agree. Just set them up in
5521          * a way that results in the correct picture.
5522          */
5523         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5524         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5525
5526         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5527         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5528
5529         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5530         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5531
5532         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5533         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5534         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5535
5536         if (INTEL_INFO(dev)->gen > 6) {
5537                 uint16_t postoff = 0;
5538
5539                 if (intel_crtc->config.limited_color_range)
5540                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5541
5542                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5543                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5544                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5545
5546                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5547         } else {
5548                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5549
5550                 if (intel_crtc->config.limited_color_range)
5551                         mode |= CSC_BLACK_SCREEN_OFFSET;
5552
5553                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5554         }
5555 }
5556
5557 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5558 {
5559         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5560         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5561         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5562         uint32_t val;
5563
5564         val = 0;
5565
5566         if (intel_crtc->config.dither)
5567                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5568
5569         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5570                 val |= PIPECONF_INTERLACED_ILK;
5571         else
5572                 val |= PIPECONF_PROGRESSIVE;
5573
5574         I915_WRITE(PIPECONF(cpu_transcoder), val);
5575         POSTING_READ(PIPECONF(cpu_transcoder));
5576
5577         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5578         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5579 }
5580
5581 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5582                                     intel_clock_t *clock,
5583                                     bool *has_reduced_clock,
5584                                     intel_clock_t *reduced_clock)
5585 {
5586         struct drm_device *dev = crtc->dev;
5587         struct drm_i915_private *dev_priv = dev->dev_private;
5588         struct intel_encoder *intel_encoder;
5589         int refclk;
5590         const intel_limit_t *limit;
5591         bool ret, is_lvds = false;
5592
5593         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5594                 switch (intel_encoder->type) {
5595                 case INTEL_OUTPUT_LVDS:
5596                         is_lvds = true;
5597                         break;
5598                 }
5599         }
5600
5601         refclk = ironlake_get_refclk(crtc);
5602
5603         /*
5604          * Returns a set of divisors for the desired target clock with the given
5605          * refclk, or FALSE.  The returned values represent the clock equation:
5606          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5607          */
5608         limit = intel_limit(crtc, refclk);
5609         ret = dev_priv->display.find_dpll(limit, crtc,
5610                                           to_intel_crtc(crtc)->config.port_clock,
5611                                           refclk, NULL, clock);
5612         if (!ret)
5613                 return false;
5614
5615         if (is_lvds && dev_priv->lvds_downclock_avail) {
5616                 /*
5617                  * Ensure we match the reduced clock's P to the target clock.
5618                  * If the clocks don't match, we can't switch the display clock
5619                  * by using the FP0/FP1. In such case we will disable the LVDS
5620                  * downclock feature.
5621                 */
5622                 *has_reduced_clock =
5623                         dev_priv->display.find_dpll(limit, crtc,
5624                                                     dev_priv->lvds_downclock,
5625                                                     refclk, clock,
5626                                                     reduced_clock);
5627         }
5628
5629         return true;
5630 }
5631
5632 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5633 {
5634         struct drm_i915_private *dev_priv = dev->dev_private;
5635         uint32_t temp;
5636
5637         temp = I915_READ(SOUTH_CHICKEN1);
5638         if (temp & FDI_BC_BIFURCATION_SELECT)
5639                 return;
5640
5641         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5642         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5643
5644         temp |= FDI_BC_BIFURCATION_SELECT;
5645         DRM_DEBUG_KMS("enabling fdi C rx\n");
5646         I915_WRITE(SOUTH_CHICKEN1, temp);
5647         POSTING_READ(SOUTH_CHICKEN1);
5648 }
5649
5650 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5651 {
5652         struct drm_device *dev = intel_crtc->base.dev;
5653         struct drm_i915_private *dev_priv = dev->dev_private;
5654
5655         switch (intel_crtc->pipe) {
5656         case PIPE_A:
5657                 break;
5658         case PIPE_B:
5659                 if (intel_crtc->config.fdi_lanes > 2)
5660                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5661                 else
5662                         cpt_enable_fdi_bc_bifurcation(dev);
5663
5664                 break;
5665         case PIPE_C:
5666                 cpt_enable_fdi_bc_bifurcation(dev);
5667
5668                 break;
5669         default:
5670                 BUG();
5671         }
5672 }
5673
5674 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5675 {
5676         /*
5677          * Account for spread spectrum to avoid
5678          * oversubscribing the link. Max center spread
5679          * is 2.5%; use 5% for safety's sake.
5680          */
5681         u32 bps = target_clock * bpp * 21 / 20;
5682         return bps / (link_bw * 8) + 1;
5683 }
5684
5685 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5686 {
5687         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5688 }
5689
5690 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5691                                       u32 *fp,
5692                                       intel_clock_t *reduced_clock, u32 *fp2)
5693 {
5694         struct drm_crtc *crtc = &intel_crtc->base;
5695         struct drm_device *dev = crtc->dev;
5696         struct drm_i915_private *dev_priv = dev->dev_private;
5697         struct intel_encoder *intel_encoder;
5698         uint32_t dpll;
5699         int factor, num_connectors = 0;
5700         bool is_lvds = false, is_sdvo = false;
5701
5702         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5703                 switch (intel_encoder->type) {
5704                 case INTEL_OUTPUT_LVDS:
5705                         is_lvds = true;
5706                         break;
5707                 case INTEL_OUTPUT_SDVO:
5708                 case INTEL_OUTPUT_HDMI:
5709                         is_sdvo = true;
5710                         break;
5711                 }
5712
5713                 num_connectors++;
5714         }
5715
5716         /* Enable autotuning of the PLL clock (if permissible) */
5717         factor = 21;
5718         if (is_lvds) {
5719                 if ((intel_panel_use_ssc(dev_priv) &&
5720                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5721                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5722                         factor = 25;
5723         } else if (intel_crtc->config.sdvo_tv_clock)
5724                 factor = 20;
5725
5726         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5727                 *fp |= FP_CB_TUNE;
5728
5729         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5730                 *fp2 |= FP_CB_TUNE;
5731
5732         dpll = 0;
5733
5734         if (is_lvds)
5735                 dpll |= DPLLB_MODE_LVDS;
5736         else
5737                 dpll |= DPLLB_MODE_DAC_SERIAL;
5738
5739         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5740                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5741
5742         if (is_sdvo)
5743                 dpll |= DPLL_SDVO_HIGH_SPEED;
5744         if (intel_crtc->config.has_dp_encoder)
5745                 dpll |= DPLL_SDVO_HIGH_SPEED;
5746
5747         /* compute bitmask from p1 value */
5748         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5749         /* also FPA1 */
5750         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5751
5752         switch (intel_crtc->config.dpll.p2) {
5753         case 5:
5754                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5755                 break;
5756         case 7:
5757                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5758                 break;
5759         case 10:
5760                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5761                 break;
5762         case 14:
5763                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5764                 break;
5765         }
5766
5767         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5768                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5769         else
5770                 dpll |= PLL_REF_INPUT_DREFCLK;
5771
5772         return dpll | DPLL_VCO_ENABLE;
5773 }
5774
5775 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5776                                   int x, int y,
5777                                   struct drm_framebuffer *fb)
5778 {
5779         struct drm_device *dev = crtc->dev;
5780         struct drm_i915_private *dev_priv = dev->dev_private;
5781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5782         int pipe = intel_crtc->pipe;
5783         int plane = intel_crtc->plane;
5784         int num_connectors = 0;
5785         intel_clock_t clock, reduced_clock;
5786         u32 dpll = 0, fp = 0, fp2 = 0;
5787         bool ok, has_reduced_clock = false;
5788         bool is_lvds = false;
5789         struct intel_encoder *encoder;
5790         struct intel_shared_dpll *pll;
5791         int ret;
5792
5793         for_each_encoder_on_crtc(dev, crtc, encoder) {
5794                 switch (encoder->type) {
5795                 case INTEL_OUTPUT_LVDS:
5796                         is_lvds = true;
5797                         break;
5798                 }
5799
5800                 num_connectors++;
5801         }
5802
5803         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5804              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5805
5806         ok = ironlake_compute_clocks(crtc, &clock,
5807                                      &has_reduced_clock, &reduced_clock);
5808         if (!ok && !intel_crtc->config.clock_set) {
5809                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5810                 return -EINVAL;
5811         }
5812         /* Compat-code for transition, will disappear. */
5813         if (!intel_crtc->config.clock_set) {
5814                 intel_crtc->config.dpll.n = clock.n;
5815                 intel_crtc->config.dpll.m1 = clock.m1;
5816                 intel_crtc->config.dpll.m2 = clock.m2;
5817                 intel_crtc->config.dpll.p1 = clock.p1;
5818                 intel_crtc->config.dpll.p2 = clock.p2;
5819         }
5820
5821         /* Ensure that the cursor is valid for the new mode before changing... */
5822         intel_crtc_update_cursor(crtc, true);
5823
5824         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5825         if (intel_crtc->config.has_pch_encoder) {
5826                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5827                 if (has_reduced_clock)
5828                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5829
5830                 dpll = ironlake_compute_dpll(intel_crtc,
5831                                              &fp, &reduced_clock,
5832                                              has_reduced_clock ? &fp2 : NULL);
5833
5834                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5835                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5836                 if (has_reduced_clock)
5837                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5838                 else
5839                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5840
5841                 pll = intel_get_shared_dpll(intel_crtc);
5842                 if (pll == NULL) {
5843                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5844                                          pipe_name(pipe));
5845                         return -EINVAL;
5846                 }
5847         } else
5848                 intel_put_shared_dpll(intel_crtc);
5849
5850         if (intel_crtc->config.has_dp_encoder)
5851                 intel_dp_set_m_n(intel_crtc);
5852
5853         if (is_lvds && has_reduced_clock && i915_powersave)
5854                 intel_crtc->lowfreq_avail = true;
5855         else
5856                 intel_crtc->lowfreq_avail = false;
5857
5858         if (intel_crtc->config.has_pch_encoder) {
5859                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5860
5861         }
5862
5863         intel_set_pipe_timings(intel_crtc);
5864
5865         if (intel_crtc->config.has_pch_encoder) {
5866                 intel_cpu_transcoder_set_m_n(intel_crtc,
5867                                              &intel_crtc->config.fdi_m_n);
5868         }
5869
5870         if (IS_IVYBRIDGE(dev))
5871                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5872
5873         ironlake_set_pipeconf(crtc);
5874
5875         /* Set up the display plane register */
5876         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5877         POSTING_READ(DSPCNTR(plane));
5878
5879         ret = intel_pipe_set_base(crtc, x, y, fb);
5880
5881         return ret;
5882 }
5883
5884 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5885                                          struct intel_link_m_n *m_n)
5886 {
5887         struct drm_device *dev = crtc->base.dev;
5888         struct drm_i915_private *dev_priv = dev->dev_private;
5889         enum pipe pipe = crtc->pipe;
5890
5891         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5892         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5893         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5894                 & ~TU_SIZE_MASK;
5895         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5896         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5897                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5898 }
5899
5900 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5901                                          enum transcoder transcoder,
5902                                          struct intel_link_m_n *m_n)
5903 {
5904         struct drm_device *dev = crtc->base.dev;
5905         struct drm_i915_private *dev_priv = dev->dev_private;
5906         enum pipe pipe = crtc->pipe;
5907
5908         if (INTEL_INFO(dev)->gen >= 5) {
5909                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5910                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5911                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5912                         & ~TU_SIZE_MASK;
5913                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5914                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5915                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5916         } else {
5917                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5918                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5919                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5920                         & ~TU_SIZE_MASK;
5921                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5922                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5923                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5924         }
5925 }
5926
5927 void intel_dp_get_m_n(struct intel_crtc *crtc,
5928                       struct intel_crtc_config *pipe_config)
5929 {
5930         if (crtc->config.has_pch_encoder)
5931                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5932         else
5933                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5934                                              &pipe_config->dp_m_n);
5935 }
5936
5937 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5938                                         struct intel_crtc_config *pipe_config)
5939 {
5940         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5941                                      &pipe_config->fdi_m_n);
5942 }
5943
5944 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5945                                      struct intel_crtc_config *pipe_config)
5946 {
5947         struct drm_device *dev = crtc->base.dev;
5948         struct drm_i915_private *dev_priv = dev->dev_private;
5949         uint32_t tmp;
5950
5951         tmp = I915_READ(PF_CTL(crtc->pipe));
5952
5953         if (tmp & PF_ENABLE) {
5954                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5955                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5956
5957                 /* We currently do not free assignements of panel fitters on
5958                  * ivb/hsw (since we don't use the higher upscaling modes which
5959                  * differentiates them) so just WARN about this case for now. */
5960                 if (IS_GEN7(dev)) {
5961                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5962                                 PF_PIPE_SEL_IVB(crtc->pipe));
5963                 }
5964         }
5965 }
5966
5967 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5968                                      struct intel_crtc_config *pipe_config)
5969 {
5970         struct drm_device *dev = crtc->base.dev;
5971         struct drm_i915_private *dev_priv = dev->dev_private;
5972         uint32_t tmp;
5973
5974         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5975         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5976
5977         tmp = I915_READ(PIPECONF(crtc->pipe));
5978         if (!(tmp & PIPECONF_ENABLE))
5979                 return false;
5980
5981         switch (tmp & PIPECONF_BPC_MASK) {
5982         case PIPECONF_6BPC:
5983                 pipe_config->pipe_bpp = 18;
5984                 break;
5985         case PIPECONF_8BPC:
5986                 pipe_config->pipe_bpp = 24;
5987                 break;
5988         case PIPECONF_10BPC:
5989                 pipe_config->pipe_bpp = 30;
5990                 break;
5991         case PIPECONF_12BPC:
5992                 pipe_config->pipe_bpp = 36;
5993                 break;
5994         default:
5995                 break;
5996         }
5997
5998         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5999                 struct intel_shared_dpll *pll;
6000
6001                 pipe_config->has_pch_encoder = true;
6002
6003                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6004                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6005                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6006
6007                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6008
6009                 if (HAS_PCH_IBX(dev_priv->dev)) {
6010                         pipe_config->shared_dpll =
6011                                 (enum intel_dpll_id) crtc->pipe;
6012                 } else {
6013                         tmp = I915_READ(PCH_DPLL_SEL);
6014                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6015                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6016                         else
6017                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6018                 }
6019
6020                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6021
6022                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6023                                            &pipe_config->dpll_hw_state));
6024
6025                 tmp = pipe_config->dpll_hw_state.dpll;
6026                 pipe_config->pixel_multiplier =
6027                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6028                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6029         } else {
6030                 pipe_config->pixel_multiplier = 1;
6031         }
6032
6033         intel_get_pipe_timings(crtc, pipe_config);
6034
6035         ironlake_get_pfit_config(crtc, pipe_config);
6036
6037         return true;
6038 }
6039
6040 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6041 {
6042         struct drm_device *dev = dev_priv->dev;
6043         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6044         struct intel_crtc *crtc;
6045         unsigned long irqflags;
6046         uint32_t val;
6047
6048         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6049                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6050                      pipe_name(crtc->pipe));
6051
6052         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6053         WARN(plls->spll_refcount, "SPLL enabled\n");
6054         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6055         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6056         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6057         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6058              "CPU PWM1 enabled\n");
6059         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6060              "CPU PWM2 enabled\n");
6061         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6062              "PCH PWM1 enabled\n");
6063         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6064              "Utility pin enabled\n");
6065         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6066
6067         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6068         val = I915_READ(DEIMR);
6069         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6070              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6071         val = I915_READ(SDEIMR);
6072         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6073              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6074         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6075 }
6076
6077 /*
6078  * This function implements pieces of two sequences from BSpec:
6079  * - Sequence for display software to disable LCPLL
6080  * - Sequence for display software to allow package C8+
6081  * The steps implemented here are just the steps that actually touch the LCPLL
6082  * register. Callers should take care of disabling all the display engine
6083  * functions, doing the mode unset, fixing interrupts, etc.
6084  */
6085 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6086                        bool switch_to_fclk, bool allow_power_down)
6087 {
6088         uint32_t val;
6089
6090         assert_can_disable_lcpll(dev_priv);
6091
6092         val = I915_READ(LCPLL_CTL);
6093
6094         if (switch_to_fclk) {
6095                 val |= LCPLL_CD_SOURCE_FCLK;
6096                 I915_WRITE(LCPLL_CTL, val);
6097
6098                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6099                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6100                         DRM_ERROR("Switching to FCLK failed\n");
6101
6102                 val = I915_READ(LCPLL_CTL);
6103         }
6104
6105         val |= LCPLL_PLL_DISABLE;
6106         I915_WRITE(LCPLL_CTL, val);
6107         POSTING_READ(LCPLL_CTL);
6108
6109         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6110                 DRM_ERROR("LCPLL still locked\n");
6111
6112         val = I915_READ(D_COMP);
6113         val |= D_COMP_COMP_DISABLE;
6114         I915_WRITE(D_COMP, val);
6115         POSTING_READ(D_COMP);
6116         ndelay(100);
6117
6118         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6119                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6120
6121         if (allow_power_down) {
6122                 val = I915_READ(LCPLL_CTL);
6123                 val |= LCPLL_POWER_DOWN_ALLOW;
6124                 I915_WRITE(LCPLL_CTL, val);
6125                 POSTING_READ(LCPLL_CTL);
6126         }
6127 }
6128
6129 /*
6130  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6131  * source.
6132  */
6133 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6134 {
6135         uint32_t val;
6136
6137         val = I915_READ(LCPLL_CTL);
6138
6139         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6140                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6141                 return;
6142
6143         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6144          * we'll hang the machine! */
6145         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6146
6147         if (val & LCPLL_POWER_DOWN_ALLOW) {
6148                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6149                 I915_WRITE(LCPLL_CTL, val);
6150                 POSTING_READ(LCPLL_CTL);
6151         }
6152
6153         val = I915_READ(D_COMP);
6154         val |= D_COMP_COMP_FORCE;
6155         val &= ~D_COMP_COMP_DISABLE;
6156         I915_WRITE(D_COMP, val);
6157         POSTING_READ(D_COMP);
6158
6159         val = I915_READ(LCPLL_CTL);
6160         val &= ~LCPLL_PLL_DISABLE;
6161         I915_WRITE(LCPLL_CTL, val);
6162
6163         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6164                 DRM_ERROR("LCPLL not locked yet\n");
6165
6166         if (val & LCPLL_CD_SOURCE_FCLK) {
6167                 val = I915_READ(LCPLL_CTL);
6168                 val &= ~LCPLL_CD_SOURCE_FCLK;
6169                 I915_WRITE(LCPLL_CTL, val);
6170
6171                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6172                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6173                         DRM_ERROR("Switching back to LCPLL failed\n");
6174         }
6175
6176         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6177 }
6178
6179 void hsw_enable_pc8_work(struct work_struct *__work)
6180 {
6181         struct drm_i915_private *dev_priv =
6182                 container_of(to_delayed_work(__work), struct drm_i915_private,
6183                              pc8.enable_work);
6184         struct drm_device *dev = dev_priv->dev;
6185         uint32_t val;
6186
6187         if (dev_priv->pc8.enabled)
6188                 return;
6189
6190         DRM_DEBUG_KMS("Enabling package C8+\n");
6191
6192         dev_priv->pc8.enabled = true;
6193
6194         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6195                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6196                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6197                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6198         }
6199
6200         lpt_disable_clkout_dp(dev);
6201         hsw_pc8_disable_interrupts(dev);
6202         hsw_disable_lcpll(dev_priv, true, true);
6203 }
6204
6205 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6206 {
6207         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6208         WARN(dev_priv->pc8.disable_count < 1,
6209              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6210
6211         dev_priv->pc8.disable_count--;
6212         if (dev_priv->pc8.disable_count != 0)
6213                 return;
6214
6215         schedule_delayed_work(&dev_priv->pc8.enable_work,
6216                               msecs_to_jiffies(i915_pc8_timeout));
6217 }
6218
6219 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6220 {
6221         struct drm_device *dev = dev_priv->dev;
6222         uint32_t val;
6223
6224         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6225         WARN(dev_priv->pc8.disable_count < 0,
6226              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6227
6228         dev_priv->pc8.disable_count++;
6229         if (dev_priv->pc8.disable_count != 1)
6230                 return;
6231
6232         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6233         if (!dev_priv->pc8.enabled)
6234                 return;
6235
6236         DRM_DEBUG_KMS("Disabling package C8+\n");
6237
6238         hsw_restore_lcpll(dev_priv);
6239         hsw_pc8_restore_interrupts(dev);
6240         lpt_init_pch_refclk(dev);
6241
6242         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6243                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6244                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6245                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6246         }
6247
6248         intel_prepare_ddi(dev);
6249         i915_gem_init_swizzling(dev);
6250         mutex_lock(&dev_priv->rps.hw_lock);
6251         gen6_update_ring_freq(dev);
6252         mutex_unlock(&dev_priv->rps.hw_lock);
6253         dev_priv->pc8.enabled = false;
6254 }
6255
6256 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6257 {
6258         mutex_lock(&dev_priv->pc8.lock);
6259         __hsw_enable_package_c8(dev_priv);
6260         mutex_unlock(&dev_priv->pc8.lock);
6261 }
6262
6263 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6264 {
6265         mutex_lock(&dev_priv->pc8.lock);
6266         __hsw_disable_package_c8(dev_priv);
6267         mutex_unlock(&dev_priv->pc8.lock);
6268 }
6269
6270 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6271 {
6272         struct drm_device *dev = dev_priv->dev;
6273         struct intel_crtc *crtc;
6274         uint32_t val;
6275
6276         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6277                 if (crtc->base.enabled)
6278                         return false;
6279
6280         /* This case is still possible since we have the i915.disable_power_well
6281          * parameter and also the KVMr or something else might be requesting the
6282          * power well. */
6283         val = I915_READ(HSW_PWR_WELL_DRIVER);
6284         if (val != 0) {
6285                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6286                 return false;
6287         }
6288
6289         return true;
6290 }
6291
6292 /* Since we're called from modeset_global_resources there's no way to
6293  * symmetrically increase and decrease the refcount, so we use
6294  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6295  * or not.
6296  */
6297 static void hsw_update_package_c8(struct drm_device *dev)
6298 {
6299         struct drm_i915_private *dev_priv = dev->dev_private;
6300         bool allow;
6301
6302         if (!i915_enable_pc8)
6303                 return;
6304
6305         mutex_lock(&dev_priv->pc8.lock);
6306
6307         allow = hsw_can_enable_package_c8(dev_priv);
6308
6309         if (allow == dev_priv->pc8.requirements_met)
6310                 goto done;
6311
6312         dev_priv->pc8.requirements_met = allow;
6313
6314         if (allow)
6315                 __hsw_enable_package_c8(dev_priv);
6316         else
6317                 __hsw_disable_package_c8(dev_priv);
6318
6319 done:
6320         mutex_unlock(&dev_priv->pc8.lock);
6321 }
6322
6323 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6324 {
6325         if (!dev_priv->pc8.gpu_idle) {
6326                 dev_priv->pc8.gpu_idle = true;
6327                 hsw_enable_package_c8(dev_priv);
6328         }
6329 }
6330
6331 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6332 {
6333         if (dev_priv->pc8.gpu_idle) {
6334                 dev_priv->pc8.gpu_idle = false;
6335                 hsw_disable_package_c8(dev_priv);
6336         }
6337 }
6338
6339 static void haswell_modeset_global_resources(struct drm_device *dev)
6340 {
6341         bool enable = false;
6342         struct intel_crtc *crtc;
6343
6344         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6345                 if (!crtc->base.enabled)
6346                         continue;
6347
6348                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6349                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6350                         enable = true;
6351         }
6352
6353         intel_set_power_well(dev, enable);
6354
6355         hsw_update_package_c8(dev);
6356 }
6357
6358 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6359                                  int x, int y,
6360                                  struct drm_framebuffer *fb)
6361 {
6362         struct drm_device *dev = crtc->dev;
6363         struct drm_i915_private *dev_priv = dev->dev_private;
6364         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6365         int plane = intel_crtc->plane;
6366         int ret;
6367
6368         if (!intel_ddi_pll_mode_set(crtc))
6369                 return -EINVAL;
6370
6371         /* Ensure that the cursor is valid for the new mode before changing... */
6372         intel_crtc_update_cursor(crtc, true);
6373
6374         if (intel_crtc->config.has_dp_encoder)
6375                 intel_dp_set_m_n(intel_crtc);
6376
6377         intel_crtc->lowfreq_avail = false;
6378
6379         intel_set_pipe_timings(intel_crtc);
6380
6381         if (intel_crtc->config.has_pch_encoder) {
6382                 intel_cpu_transcoder_set_m_n(intel_crtc,
6383                                              &intel_crtc->config.fdi_m_n);
6384         }
6385
6386         haswell_set_pipeconf(crtc);
6387
6388         intel_set_pipe_csc(crtc);
6389
6390         /* Set up the display plane register */
6391         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6392         POSTING_READ(DSPCNTR(plane));
6393
6394         ret = intel_pipe_set_base(crtc, x, y, fb);
6395
6396         return ret;
6397 }
6398
6399 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6400                                     struct intel_crtc_config *pipe_config)
6401 {
6402         struct drm_device *dev = crtc->base.dev;
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         enum intel_display_power_domain pfit_domain;
6405         uint32_t tmp;
6406
6407         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6408         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6409
6410         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6411         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6412                 enum pipe trans_edp_pipe;
6413                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6414                 default:
6415                         WARN(1, "unknown pipe linked to edp transcoder\n");
6416                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6417                 case TRANS_DDI_EDP_INPUT_A_ON:
6418                         trans_edp_pipe = PIPE_A;
6419                         break;
6420                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6421                         trans_edp_pipe = PIPE_B;
6422                         break;
6423                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6424                         trans_edp_pipe = PIPE_C;
6425                         break;
6426                 }
6427
6428                 if (trans_edp_pipe == crtc->pipe)
6429                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6430         }
6431
6432         if (!intel_display_power_enabled(dev,
6433                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6434                 return false;
6435
6436         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6437         if (!(tmp & PIPECONF_ENABLE))
6438                 return false;
6439
6440         /*
6441          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6442          * DDI E. So just check whether this pipe is wired to DDI E and whether
6443          * the PCH transcoder is on.
6444          */
6445         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6446         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6447             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6448                 pipe_config->has_pch_encoder = true;
6449
6450                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6451                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6452                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6453
6454                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6455         }
6456
6457         intel_get_pipe_timings(crtc, pipe_config);
6458
6459         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6460         if (intel_display_power_enabled(dev, pfit_domain))
6461                 ironlake_get_pfit_config(crtc, pipe_config);
6462
6463         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6464                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6465
6466         pipe_config->pixel_multiplier = 1;
6467
6468         return true;
6469 }
6470
6471 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6472                                int x, int y,
6473                                struct drm_framebuffer *fb)
6474 {
6475         struct drm_device *dev = crtc->dev;
6476         struct drm_i915_private *dev_priv = dev->dev_private;
6477         struct intel_encoder *encoder;
6478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6479         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6480         int pipe = intel_crtc->pipe;
6481         int ret;
6482
6483         drm_vblank_pre_modeset(dev, pipe);
6484
6485         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6486
6487         drm_vblank_post_modeset(dev, pipe);
6488
6489         if (ret != 0)
6490                 return ret;
6491
6492         for_each_encoder_on_crtc(dev, crtc, encoder) {
6493                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6494                         encoder->base.base.id,
6495                         drm_get_encoder_name(&encoder->base),
6496                         mode->base.id, mode->name);
6497                 encoder->mode_set(encoder);
6498         }
6499
6500         return 0;
6501 }
6502
6503 static bool intel_eld_uptodate(struct drm_connector *connector,
6504                                int reg_eldv, uint32_t bits_eldv,
6505                                int reg_elda, uint32_t bits_elda,
6506                                int reg_edid)
6507 {
6508         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6509         uint8_t *eld = connector->eld;
6510         uint32_t i;
6511
6512         i = I915_READ(reg_eldv);
6513         i &= bits_eldv;
6514
6515         if (!eld[0])
6516                 return !i;
6517
6518         if (!i)
6519                 return false;
6520
6521         i = I915_READ(reg_elda);
6522         i &= ~bits_elda;
6523         I915_WRITE(reg_elda, i);
6524
6525         for (i = 0; i < eld[2]; i++)
6526                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6527                         return false;
6528
6529         return true;
6530 }
6531
6532 static void g4x_write_eld(struct drm_connector *connector,
6533                           struct drm_crtc *crtc)
6534 {
6535         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6536         uint8_t *eld = connector->eld;
6537         uint32_t eldv;
6538         uint32_t len;
6539         uint32_t i;
6540
6541         i = I915_READ(G4X_AUD_VID_DID);
6542
6543         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6544                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6545         else
6546                 eldv = G4X_ELDV_DEVCTG;
6547
6548         if (intel_eld_uptodate(connector,
6549                                G4X_AUD_CNTL_ST, eldv,
6550                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6551                                G4X_HDMIW_HDMIEDID))
6552                 return;
6553
6554         i = I915_READ(G4X_AUD_CNTL_ST);
6555         i &= ~(eldv | G4X_ELD_ADDR);
6556         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6557         I915_WRITE(G4X_AUD_CNTL_ST, i);
6558
6559         if (!eld[0])
6560                 return;
6561
6562         len = min_t(uint8_t, eld[2], len);
6563         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6564         for (i = 0; i < len; i++)
6565                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6566
6567         i = I915_READ(G4X_AUD_CNTL_ST);
6568         i |= eldv;
6569         I915_WRITE(G4X_AUD_CNTL_ST, i);
6570 }
6571
6572 static void haswell_write_eld(struct drm_connector *connector,
6573                                      struct drm_crtc *crtc)
6574 {
6575         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6576         uint8_t *eld = connector->eld;
6577         struct drm_device *dev = crtc->dev;
6578         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6579         uint32_t eldv;
6580         uint32_t i;
6581         int len;
6582         int pipe = to_intel_crtc(crtc)->pipe;
6583         int tmp;
6584
6585         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6586         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6587         int aud_config = HSW_AUD_CFG(pipe);
6588         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6589
6590
6591         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6592
6593         /* Audio output enable */
6594         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6595         tmp = I915_READ(aud_cntrl_st2);
6596         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6597         I915_WRITE(aud_cntrl_st2, tmp);
6598
6599         /* Wait for 1 vertical blank */
6600         intel_wait_for_vblank(dev, pipe);
6601
6602         /* Set ELD valid state */
6603         tmp = I915_READ(aud_cntrl_st2);
6604         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6605         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6606         I915_WRITE(aud_cntrl_st2, tmp);
6607         tmp = I915_READ(aud_cntrl_st2);
6608         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6609
6610         /* Enable HDMI mode */
6611         tmp = I915_READ(aud_config);
6612         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6613         /* clear N_programing_enable and N_value_index */
6614         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6615         I915_WRITE(aud_config, tmp);
6616
6617         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6618
6619         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6620         intel_crtc->eld_vld = true;
6621
6622         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6623                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6624                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6625                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6626         } else
6627                 I915_WRITE(aud_config, 0);
6628
6629         if (intel_eld_uptodate(connector,
6630                                aud_cntrl_st2, eldv,
6631                                aud_cntl_st, IBX_ELD_ADDRESS,
6632                                hdmiw_hdmiedid))
6633                 return;
6634
6635         i = I915_READ(aud_cntrl_st2);
6636         i &= ~eldv;
6637         I915_WRITE(aud_cntrl_st2, i);
6638
6639         if (!eld[0])
6640                 return;
6641
6642         i = I915_READ(aud_cntl_st);
6643         i &= ~IBX_ELD_ADDRESS;
6644         I915_WRITE(aud_cntl_st, i);
6645         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6646         DRM_DEBUG_DRIVER("port num:%d\n", i);
6647
6648         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6649         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6650         for (i = 0; i < len; i++)
6651                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6652
6653         i = I915_READ(aud_cntrl_st2);
6654         i |= eldv;
6655         I915_WRITE(aud_cntrl_st2, i);
6656
6657 }
6658
6659 static void ironlake_write_eld(struct drm_connector *connector,
6660                                      struct drm_crtc *crtc)
6661 {
6662         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6663         uint8_t *eld = connector->eld;
6664         uint32_t eldv;
6665         uint32_t i;
6666         int len;
6667         int hdmiw_hdmiedid;
6668         int aud_config;
6669         int aud_cntl_st;
6670         int aud_cntrl_st2;
6671         int pipe = to_intel_crtc(crtc)->pipe;
6672
6673         if (HAS_PCH_IBX(connector->dev)) {
6674                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6675                 aud_config = IBX_AUD_CFG(pipe);
6676                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6677                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6678         } else {
6679                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6680                 aud_config = CPT_AUD_CFG(pipe);
6681                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6682                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6683         }
6684
6685         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6686
6687         i = I915_READ(aud_cntl_st);
6688         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6689         if (!i) {
6690                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6691                 /* operate blindly on all ports */
6692                 eldv = IBX_ELD_VALIDB;
6693                 eldv |= IBX_ELD_VALIDB << 4;
6694                 eldv |= IBX_ELD_VALIDB << 8;
6695         } else {
6696                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6697                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6698         }
6699
6700         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6701                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6702                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6703                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6704         } else
6705                 I915_WRITE(aud_config, 0);
6706
6707         if (intel_eld_uptodate(connector,
6708                                aud_cntrl_st2, eldv,
6709                                aud_cntl_st, IBX_ELD_ADDRESS,
6710                                hdmiw_hdmiedid))
6711                 return;
6712
6713         i = I915_READ(aud_cntrl_st2);
6714         i &= ~eldv;
6715         I915_WRITE(aud_cntrl_st2, i);
6716
6717         if (!eld[0])
6718                 return;
6719
6720         i = I915_READ(aud_cntl_st);
6721         i &= ~IBX_ELD_ADDRESS;
6722         I915_WRITE(aud_cntl_st, i);
6723
6724         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6725         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6726         for (i = 0; i < len; i++)
6727                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6728
6729         i = I915_READ(aud_cntrl_st2);
6730         i |= eldv;
6731         I915_WRITE(aud_cntrl_st2, i);
6732 }
6733
6734 void intel_write_eld(struct drm_encoder *encoder,
6735                      struct drm_display_mode *mode)
6736 {
6737         struct drm_crtc *crtc = encoder->crtc;
6738         struct drm_connector *connector;
6739         struct drm_device *dev = encoder->dev;
6740         struct drm_i915_private *dev_priv = dev->dev_private;
6741
6742         connector = drm_select_eld(encoder, mode);
6743         if (!connector)
6744                 return;
6745
6746         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6747                          connector->base.id,
6748                          drm_get_connector_name(connector),
6749                          connector->encoder->base.id,
6750                          drm_get_encoder_name(connector->encoder));
6751
6752         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6753
6754         if (dev_priv->display.write_eld)
6755                 dev_priv->display.write_eld(connector, crtc);
6756 }
6757
6758 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6759 void intel_crtc_load_lut(struct drm_crtc *crtc)
6760 {
6761         struct drm_device *dev = crtc->dev;
6762         struct drm_i915_private *dev_priv = dev->dev_private;
6763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6764         enum pipe pipe = intel_crtc->pipe;
6765         int palreg = PALETTE(pipe);
6766         int i;
6767         bool reenable_ips = false;
6768
6769         /* The clocks have to be on to load the palette. */
6770         if (!crtc->enabled || !intel_crtc->active)
6771                 return;
6772
6773         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6774                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6775                         assert_dsi_pll_enabled(dev_priv);
6776                 else
6777                         assert_pll_enabled(dev_priv, pipe);
6778         }
6779
6780         /* use legacy palette for Ironlake */
6781         if (HAS_PCH_SPLIT(dev))
6782                 palreg = LGC_PALETTE(pipe);
6783
6784         /* Workaround : Do not read or write the pipe palette/gamma data while
6785          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6786          */
6787         if (intel_crtc->config.ips_enabled &&
6788             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6789              GAMMA_MODE_MODE_SPLIT)) {
6790                 hsw_disable_ips(intel_crtc);
6791                 reenable_ips = true;
6792         }
6793
6794         for (i = 0; i < 256; i++) {
6795                 I915_WRITE(palreg + 4 * i,
6796                            (intel_crtc->lut_r[i] << 16) |
6797                            (intel_crtc->lut_g[i] << 8) |
6798                            intel_crtc->lut_b[i]);
6799         }
6800
6801         if (reenable_ips)
6802                 hsw_enable_ips(intel_crtc);
6803 }
6804
6805 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6806 {
6807         struct drm_device *dev = crtc->dev;
6808         struct drm_i915_private *dev_priv = dev->dev_private;
6809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6810         bool visible = base != 0;
6811         u32 cntl;
6812
6813         if (intel_crtc->cursor_visible == visible)
6814                 return;
6815
6816         cntl = I915_READ(_CURACNTR);
6817         if (visible) {
6818                 /* On these chipsets we can only modify the base whilst
6819                  * the cursor is disabled.
6820                  */
6821                 I915_WRITE(_CURABASE, base);
6822
6823                 cntl &= ~(CURSOR_FORMAT_MASK);
6824                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6825                 cntl |= CURSOR_ENABLE |
6826                         CURSOR_GAMMA_ENABLE |
6827                         CURSOR_FORMAT_ARGB;
6828         } else
6829                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6830         I915_WRITE(_CURACNTR, cntl);
6831
6832         intel_crtc->cursor_visible = visible;
6833 }
6834
6835 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6836 {
6837         struct drm_device *dev = crtc->dev;
6838         struct drm_i915_private *dev_priv = dev->dev_private;
6839         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6840         int pipe = intel_crtc->pipe;
6841         bool visible = base != 0;
6842
6843         if (intel_crtc->cursor_visible != visible) {
6844                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6845                 if (base) {
6846                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6847                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6848                         cntl |= pipe << 28; /* Connect to correct pipe */
6849                 } else {
6850                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6851                         cntl |= CURSOR_MODE_DISABLE;
6852                 }
6853                 I915_WRITE(CURCNTR(pipe), cntl);
6854
6855                 intel_crtc->cursor_visible = visible;
6856         }
6857         /* and commit changes on next vblank */
6858         I915_WRITE(CURBASE(pipe), base);
6859 }
6860
6861 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6862 {
6863         struct drm_device *dev = crtc->dev;
6864         struct drm_i915_private *dev_priv = dev->dev_private;
6865         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6866         int pipe = intel_crtc->pipe;
6867         bool visible = base != 0;
6868
6869         if (intel_crtc->cursor_visible != visible) {
6870                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6871                 if (base) {
6872                         cntl &= ~CURSOR_MODE;
6873                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6874                 } else {
6875                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6876                         cntl |= CURSOR_MODE_DISABLE;
6877                 }
6878                 if (IS_HASWELL(dev)) {
6879                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6880                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6881                 }
6882                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6883
6884                 intel_crtc->cursor_visible = visible;
6885         }
6886         /* and commit changes on next vblank */
6887         I915_WRITE(CURBASE_IVB(pipe), base);
6888 }
6889
6890 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6891 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6892                                      bool on)
6893 {
6894         struct drm_device *dev = crtc->dev;
6895         struct drm_i915_private *dev_priv = dev->dev_private;
6896         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6897         int pipe = intel_crtc->pipe;
6898         int x = intel_crtc->cursor_x;
6899         int y = intel_crtc->cursor_y;
6900         u32 base, pos;
6901         bool visible;
6902
6903         pos = 0;
6904
6905         if (on && crtc->enabled && crtc->fb) {
6906                 base = intel_crtc->cursor_addr;
6907                 if (x > (int) crtc->fb->width)
6908                         base = 0;
6909
6910                 if (y > (int) crtc->fb->height)
6911                         base = 0;
6912         } else
6913                 base = 0;
6914
6915         if (x < 0) {
6916                 if (x + intel_crtc->cursor_width < 0)
6917                         base = 0;
6918
6919                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6920                 x = -x;
6921         }
6922         pos |= x << CURSOR_X_SHIFT;
6923
6924         if (y < 0) {
6925                 if (y + intel_crtc->cursor_height < 0)
6926                         base = 0;
6927
6928                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6929                 y = -y;
6930         }
6931         pos |= y << CURSOR_Y_SHIFT;
6932
6933         visible = base != 0;
6934         if (!visible && !intel_crtc->cursor_visible)
6935                 return;
6936
6937         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6938                 I915_WRITE(CURPOS_IVB(pipe), pos);
6939                 ivb_update_cursor(crtc, base);
6940         } else {
6941                 I915_WRITE(CURPOS(pipe), pos);
6942                 if (IS_845G(dev) || IS_I865G(dev))
6943                         i845_update_cursor(crtc, base);
6944                 else
6945                         i9xx_update_cursor(crtc, base);
6946         }
6947 }
6948
6949 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6950                                  struct drm_file *file,
6951                                  uint32_t handle,
6952                                  uint32_t width, uint32_t height)
6953 {
6954         struct drm_device *dev = crtc->dev;
6955         struct drm_i915_private *dev_priv = dev->dev_private;
6956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957         struct drm_i915_gem_object *obj;
6958         uint32_t addr;
6959         int ret;
6960
6961         /* if we want to turn off the cursor ignore width and height */
6962         if (!handle) {
6963                 DRM_DEBUG_KMS("cursor off\n");
6964                 addr = 0;
6965                 obj = NULL;
6966                 mutex_lock(&dev->struct_mutex);
6967                 goto finish;
6968         }
6969
6970         /* Currently we only support 64x64 cursors */
6971         if (width != 64 || height != 64) {
6972                 DRM_ERROR("we currently only support 64x64 cursors\n");
6973                 return -EINVAL;
6974         }
6975
6976         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6977         if (&obj->base == NULL)
6978                 return -ENOENT;
6979
6980         if (obj->base.size < width * height * 4) {
6981                 DRM_ERROR("buffer is to small\n");
6982                 ret = -ENOMEM;
6983                 goto fail;
6984         }
6985
6986         /* we only need to pin inside GTT if cursor is non-phy */
6987         mutex_lock(&dev->struct_mutex);
6988         if (!dev_priv->info->cursor_needs_physical) {
6989                 unsigned alignment;
6990
6991                 if (obj->tiling_mode) {
6992                         DRM_ERROR("cursor cannot be tiled\n");
6993                         ret = -EINVAL;
6994                         goto fail_locked;
6995                 }
6996
6997                 /* Note that the w/a also requires 2 PTE of padding following
6998                  * the bo. We currently fill all unused PTE with the shadow
6999                  * page and so we should always have valid PTE following the
7000                  * cursor preventing the VT-d warning.
7001                  */
7002                 alignment = 0;
7003                 if (need_vtd_wa(dev))
7004                         alignment = 64*1024;
7005
7006                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7007                 if (ret) {
7008                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7009                         goto fail_locked;
7010                 }
7011
7012                 ret = i915_gem_object_put_fence(obj);
7013                 if (ret) {
7014                         DRM_ERROR("failed to release fence for cursor");
7015                         goto fail_unpin;
7016                 }
7017
7018                 addr = i915_gem_obj_ggtt_offset(obj);
7019         } else {
7020                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7021                 ret = i915_gem_attach_phys_object(dev, obj,
7022                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7023                                                   align);
7024                 if (ret) {
7025                         DRM_ERROR("failed to attach phys object\n");
7026                         goto fail_locked;
7027                 }
7028                 addr = obj->phys_obj->handle->busaddr;
7029         }
7030
7031         if (IS_GEN2(dev))
7032                 I915_WRITE(CURSIZE, (height << 12) | width);
7033
7034  finish:
7035         if (intel_crtc->cursor_bo) {
7036                 if (dev_priv->info->cursor_needs_physical) {
7037                         if (intel_crtc->cursor_bo != obj)
7038                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7039                 } else
7040                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7041                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7042         }
7043
7044         mutex_unlock(&dev->struct_mutex);
7045
7046         intel_crtc->cursor_addr = addr;
7047         intel_crtc->cursor_bo = obj;
7048         intel_crtc->cursor_width = width;
7049         intel_crtc->cursor_height = height;
7050
7051         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7052
7053         return 0;
7054 fail_unpin:
7055         i915_gem_object_unpin_from_display_plane(obj);
7056 fail_locked:
7057         mutex_unlock(&dev->struct_mutex);
7058 fail:
7059         drm_gem_object_unreference_unlocked(&obj->base);
7060         return ret;
7061 }
7062
7063 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7064 {
7065         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7066
7067         intel_crtc->cursor_x = x;
7068         intel_crtc->cursor_y = y;
7069
7070         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7071
7072         return 0;
7073 }
7074
7075 /** Sets the color ramps on behalf of RandR */
7076 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7077                                  u16 blue, int regno)
7078 {
7079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7080
7081         intel_crtc->lut_r[regno] = red >> 8;
7082         intel_crtc->lut_g[regno] = green >> 8;
7083         intel_crtc->lut_b[regno] = blue >> 8;
7084 }
7085
7086 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7087                              u16 *blue, int regno)
7088 {
7089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090
7091         *red = intel_crtc->lut_r[regno] << 8;
7092         *green = intel_crtc->lut_g[regno] << 8;
7093         *blue = intel_crtc->lut_b[regno] << 8;
7094 }
7095
7096 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7097                                  u16 *blue, uint32_t start, uint32_t size)
7098 {
7099         int end = (start + size > 256) ? 256 : start + size, i;
7100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101
7102         for (i = start; i < end; i++) {
7103                 intel_crtc->lut_r[i] = red[i] >> 8;
7104                 intel_crtc->lut_g[i] = green[i] >> 8;
7105                 intel_crtc->lut_b[i] = blue[i] >> 8;
7106         }
7107
7108         intel_crtc_load_lut(crtc);
7109 }
7110
7111 /* VESA 640x480x72Hz mode to set on the pipe */
7112 static struct drm_display_mode load_detect_mode = {
7113         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7114                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7115 };
7116
7117 static struct drm_framebuffer *
7118 intel_framebuffer_create(struct drm_device *dev,
7119                          struct drm_mode_fb_cmd2 *mode_cmd,
7120                          struct drm_i915_gem_object *obj)
7121 {
7122         struct intel_framebuffer *intel_fb;
7123         int ret;
7124
7125         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7126         if (!intel_fb) {
7127                 drm_gem_object_unreference_unlocked(&obj->base);
7128                 return ERR_PTR(-ENOMEM);
7129         }
7130
7131         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7132         if (ret) {
7133                 drm_gem_object_unreference_unlocked(&obj->base);
7134                 kfree(intel_fb);
7135                 return ERR_PTR(ret);
7136         }
7137
7138         return &intel_fb->base;
7139 }
7140
7141 static u32
7142 intel_framebuffer_pitch_for_width(int width, int bpp)
7143 {
7144         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7145         return ALIGN(pitch, 64);
7146 }
7147
7148 static u32
7149 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7150 {
7151         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7152         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7153 }
7154
7155 static struct drm_framebuffer *
7156 intel_framebuffer_create_for_mode(struct drm_device *dev,
7157                                   struct drm_display_mode *mode,
7158                                   int depth, int bpp)
7159 {
7160         struct drm_i915_gem_object *obj;
7161         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7162
7163         obj = i915_gem_alloc_object(dev,
7164                                     intel_framebuffer_size_for_mode(mode, bpp));
7165         if (obj == NULL)
7166                 return ERR_PTR(-ENOMEM);
7167
7168         mode_cmd.width = mode->hdisplay;
7169         mode_cmd.height = mode->vdisplay;
7170         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7171                                                                 bpp);
7172         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7173
7174         return intel_framebuffer_create(dev, &mode_cmd, obj);
7175 }
7176
7177 static struct drm_framebuffer *
7178 mode_fits_in_fbdev(struct drm_device *dev,
7179                    struct drm_display_mode *mode)
7180 {
7181         struct drm_i915_private *dev_priv = dev->dev_private;
7182         struct drm_i915_gem_object *obj;
7183         struct drm_framebuffer *fb;
7184
7185         if (dev_priv->fbdev == NULL)
7186                 return NULL;
7187
7188         obj = dev_priv->fbdev->ifb.obj;
7189         if (obj == NULL)
7190                 return NULL;
7191
7192         fb = &dev_priv->fbdev->ifb.base;
7193         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7194                                                                fb->bits_per_pixel))
7195                 return NULL;
7196
7197         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7198                 return NULL;
7199
7200         return fb;
7201 }
7202
7203 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7204                                 struct drm_display_mode *mode,
7205                                 struct intel_load_detect_pipe *old)
7206 {
7207         struct intel_crtc *intel_crtc;
7208         struct intel_encoder *intel_encoder =
7209                 intel_attached_encoder(connector);
7210         struct drm_crtc *possible_crtc;
7211         struct drm_encoder *encoder = &intel_encoder->base;
7212         struct drm_crtc *crtc = NULL;
7213         struct drm_device *dev = encoder->dev;
7214         struct drm_framebuffer *fb;
7215         int i = -1;
7216
7217         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7218                       connector->base.id, drm_get_connector_name(connector),
7219                       encoder->base.id, drm_get_encoder_name(encoder));
7220
7221         /*
7222          * Algorithm gets a little messy:
7223          *
7224          *   - if the connector already has an assigned crtc, use it (but make
7225          *     sure it's on first)
7226          *
7227          *   - try to find the first unused crtc that can drive this connector,
7228          *     and use that if we find one
7229          */
7230
7231         /* See if we already have a CRTC for this connector */
7232         if (encoder->crtc) {
7233                 crtc = encoder->crtc;
7234
7235                 mutex_lock(&crtc->mutex);
7236
7237                 old->dpms_mode = connector->dpms;
7238                 old->load_detect_temp = false;
7239
7240                 /* Make sure the crtc and connector are running */
7241                 if (connector->dpms != DRM_MODE_DPMS_ON)
7242                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7243
7244                 return true;
7245         }
7246
7247         /* Find an unused one (if possible) */
7248         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7249                 i++;
7250                 if (!(encoder->possible_crtcs & (1 << i)))
7251                         continue;
7252                 if (!possible_crtc->enabled) {
7253                         crtc = possible_crtc;
7254                         break;
7255                 }
7256         }
7257
7258         /*
7259          * If we didn't find an unused CRTC, don't use any.
7260          */
7261         if (!crtc) {
7262                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7263                 return false;
7264         }
7265
7266         mutex_lock(&crtc->mutex);
7267         intel_encoder->new_crtc = to_intel_crtc(crtc);
7268         to_intel_connector(connector)->new_encoder = intel_encoder;
7269
7270         intel_crtc = to_intel_crtc(crtc);
7271         old->dpms_mode = connector->dpms;
7272         old->load_detect_temp = true;
7273         old->release_fb = NULL;
7274
7275         if (!mode)
7276                 mode = &load_detect_mode;
7277
7278         /* We need a framebuffer large enough to accommodate all accesses
7279          * that the plane may generate whilst we perform load detection.
7280          * We can not rely on the fbcon either being present (we get called
7281          * during its initialisation to detect all boot displays, or it may
7282          * not even exist) or that it is large enough to satisfy the
7283          * requested mode.
7284          */
7285         fb = mode_fits_in_fbdev(dev, mode);
7286         if (fb == NULL) {
7287                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7288                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7289                 old->release_fb = fb;
7290         } else
7291                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7292         if (IS_ERR(fb)) {
7293                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7294                 mutex_unlock(&crtc->mutex);
7295                 return false;
7296         }
7297
7298         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7299                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7300                 if (old->release_fb)
7301                         old->release_fb->funcs->destroy(old->release_fb);
7302                 mutex_unlock(&crtc->mutex);
7303                 return false;
7304         }
7305
7306         /* let the connector get through one full cycle before testing */
7307         intel_wait_for_vblank(dev, intel_crtc->pipe);
7308         return true;
7309 }
7310
7311 void intel_release_load_detect_pipe(struct drm_connector *connector,
7312                                     struct intel_load_detect_pipe *old)
7313 {
7314         struct intel_encoder *intel_encoder =
7315                 intel_attached_encoder(connector);
7316         struct drm_encoder *encoder = &intel_encoder->base;
7317         struct drm_crtc *crtc = encoder->crtc;
7318
7319         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7320                       connector->base.id, drm_get_connector_name(connector),
7321                       encoder->base.id, drm_get_encoder_name(encoder));
7322
7323         if (old->load_detect_temp) {
7324                 to_intel_connector(connector)->new_encoder = NULL;
7325                 intel_encoder->new_crtc = NULL;
7326                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7327
7328                 if (old->release_fb) {
7329                         drm_framebuffer_unregister_private(old->release_fb);
7330                         drm_framebuffer_unreference(old->release_fb);
7331                 }
7332
7333                 mutex_unlock(&crtc->mutex);
7334                 return;
7335         }
7336
7337         /* Switch crtc and encoder back off if necessary */
7338         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7339                 connector->funcs->dpms(connector, old->dpms_mode);
7340
7341         mutex_unlock(&crtc->mutex);
7342 }
7343
7344 /* Returns the clock of the currently programmed mode of the given pipe. */
7345 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7346                                 struct intel_crtc_config *pipe_config)
7347 {
7348         struct drm_device *dev = crtc->base.dev;
7349         struct drm_i915_private *dev_priv = dev->dev_private;
7350         int pipe = pipe_config->cpu_transcoder;
7351         u32 dpll = I915_READ(DPLL(pipe));
7352         u32 fp;
7353         intel_clock_t clock;
7354
7355         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7356                 fp = I915_READ(FP0(pipe));
7357         else
7358                 fp = I915_READ(FP1(pipe));
7359
7360         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7361         if (IS_PINEVIEW(dev)) {
7362                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7363                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7364         } else {
7365                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7366                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7367         }
7368
7369         if (!IS_GEN2(dev)) {
7370                 if (IS_PINEVIEW(dev))
7371                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7372                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7373                 else
7374                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7375                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7376
7377                 switch (dpll & DPLL_MODE_MASK) {
7378                 case DPLLB_MODE_DAC_SERIAL:
7379                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7380                                 5 : 10;
7381                         break;
7382                 case DPLLB_MODE_LVDS:
7383                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7384                                 7 : 14;
7385                         break;
7386                 default:
7387                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7388                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7389                         pipe_config->adjusted_mode.clock = 0;
7390                         return;
7391                 }
7392
7393                 if (IS_PINEVIEW(dev))
7394                         pineview_clock(96000, &clock);
7395                 else
7396                         i9xx_clock(96000, &clock);
7397         } else {
7398                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7399
7400                 if (is_lvds) {
7401                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7402                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7403                         clock.p2 = 14;
7404
7405                         if ((dpll & PLL_REF_INPUT_MASK) ==
7406                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7407                                 /* XXX: might not be 66MHz */
7408                                 i9xx_clock(66000, &clock);
7409                         } else
7410                                 i9xx_clock(48000, &clock);
7411                 } else {
7412                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7413                                 clock.p1 = 2;
7414                         else {
7415                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7416                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7417                         }
7418                         if (dpll & PLL_P2_DIVIDE_BY_4)
7419                                 clock.p2 = 4;
7420                         else
7421                                 clock.p2 = 2;
7422
7423                         i9xx_clock(48000, &clock);
7424                 }
7425         }
7426
7427         pipe_config->adjusted_mode.clock = clock.dot;
7428 }
7429
7430 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7431                                     struct intel_crtc_config *pipe_config)
7432 {
7433         struct drm_device *dev = crtc->base.dev;
7434         struct drm_i915_private *dev_priv = dev->dev_private;
7435         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7436         int link_freq;
7437         u64 clock;
7438         u32 link_m, link_n;
7439
7440         /*
7441          * The calculation for the data clock is:
7442          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7443          * But we want to avoid losing precison if possible, so:
7444          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7445          *
7446          * and the link clock is simpler:
7447          * link_clock = (m * link_clock) / n
7448          */
7449
7450         /*
7451          * We need to get the FDI or DP link clock here to derive
7452          * the M/N dividers.
7453          *
7454          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7455          * For DP, it's either 1.62GHz or 2.7GHz.
7456          * We do our calculations in 10*MHz since we don't need much precison.
7457          */
7458         if (pipe_config->has_pch_encoder)
7459                 link_freq = intel_fdi_link_freq(dev) * 10000;
7460         else
7461                 link_freq = pipe_config->port_clock;
7462
7463         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7464         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7465
7466         if (!link_m || !link_n)
7467                 return;
7468
7469         clock = ((u64)link_m * (u64)link_freq);
7470         do_div(clock, link_n);
7471
7472         pipe_config->adjusted_mode.clock = clock;
7473 }
7474
7475 /** Returns the currently programmed mode of the given pipe. */
7476 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7477                                              struct drm_crtc *crtc)
7478 {
7479         struct drm_i915_private *dev_priv = dev->dev_private;
7480         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7481         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7482         struct drm_display_mode *mode;
7483         struct intel_crtc_config pipe_config;
7484         int htot = I915_READ(HTOTAL(cpu_transcoder));
7485         int hsync = I915_READ(HSYNC(cpu_transcoder));
7486         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7487         int vsync = I915_READ(VSYNC(cpu_transcoder));
7488
7489         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7490         if (!mode)
7491                 return NULL;
7492
7493         /*
7494          * Construct a pipe_config sufficient for getting the clock info
7495          * back out of crtc_clock_get.
7496          *
7497          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7498          * to use a real value here instead.
7499          */
7500         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7501         pipe_config.pixel_multiplier = 1;
7502         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7503
7504         mode->clock = pipe_config.adjusted_mode.clock;
7505         mode->hdisplay = (htot & 0xffff) + 1;
7506         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7507         mode->hsync_start = (hsync & 0xffff) + 1;
7508         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7509         mode->vdisplay = (vtot & 0xffff) + 1;
7510         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7511         mode->vsync_start = (vsync & 0xffff) + 1;
7512         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7513
7514         drm_mode_set_name(mode);
7515
7516         return mode;
7517 }
7518
7519 static void intel_increase_pllclock(struct drm_crtc *crtc)
7520 {
7521         struct drm_device *dev = crtc->dev;
7522         drm_i915_private_t *dev_priv = dev->dev_private;
7523         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7524         int pipe = intel_crtc->pipe;
7525         int dpll_reg = DPLL(pipe);
7526         int dpll;
7527
7528         if (HAS_PCH_SPLIT(dev))
7529                 return;
7530
7531         if (!dev_priv->lvds_downclock_avail)
7532                 return;
7533
7534         dpll = I915_READ(dpll_reg);
7535         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7536                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7537
7538                 assert_panel_unlocked(dev_priv, pipe);
7539
7540                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7541                 I915_WRITE(dpll_reg, dpll);
7542                 intel_wait_for_vblank(dev, pipe);
7543
7544                 dpll = I915_READ(dpll_reg);
7545                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7546                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7547         }
7548 }
7549
7550 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7551 {
7552         struct drm_device *dev = crtc->dev;
7553         drm_i915_private_t *dev_priv = dev->dev_private;
7554         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7555
7556         if (HAS_PCH_SPLIT(dev))
7557                 return;
7558
7559         if (!dev_priv->lvds_downclock_avail)
7560                 return;
7561
7562         /*
7563          * Since this is called by a timer, we should never get here in
7564          * the manual case.
7565          */
7566         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7567                 int pipe = intel_crtc->pipe;
7568                 int dpll_reg = DPLL(pipe);
7569                 int dpll;
7570
7571                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7572
7573                 assert_panel_unlocked(dev_priv, pipe);
7574
7575                 dpll = I915_READ(dpll_reg);
7576                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7577                 I915_WRITE(dpll_reg, dpll);
7578                 intel_wait_for_vblank(dev, pipe);
7579                 dpll = I915_READ(dpll_reg);
7580                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7581                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7582         }
7583
7584 }
7585
7586 void intel_mark_busy(struct drm_device *dev)
7587 {
7588         struct drm_i915_private *dev_priv = dev->dev_private;
7589
7590         hsw_package_c8_gpu_busy(dev_priv);
7591         i915_update_gfx_val(dev_priv);
7592 }
7593
7594 void intel_mark_idle(struct drm_device *dev)
7595 {
7596         struct drm_i915_private *dev_priv = dev->dev_private;
7597         struct drm_crtc *crtc;
7598
7599         hsw_package_c8_gpu_idle(dev_priv);
7600
7601         if (!i915_powersave)
7602                 return;
7603
7604         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7605                 if (!crtc->fb)
7606                         continue;
7607
7608                 intel_decrease_pllclock(crtc);
7609         }
7610 }
7611
7612 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7613                         struct intel_ring_buffer *ring)
7614 {
7615         struct drm_device *dev = obj->base.dev;
7616         struct drm_crtc *crtc;
7617
7618         if (!i915_powersave)
7619                 return;
7620
7621         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7622                 if (!crtc->fb)
7623                         continue;
7624
7625                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7626                         continue;
7627
7628                 intel_increase_pllclock(crtc);
7629                 if (ring && intel_fbc_enabled(dev))
7630                         ring->fbc_dirty = true;
7631         }
7632 }
7633
7634 static void intel_crtc_destroy(struct drm_crtc *crtc)
7635 {
7636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7637         struct drm_device *dev = crtc->dev;
7638         struct intel_unpin_work *work;
7639         unsigned long flags;
7640
7641         spin_lock_irqsave(&dev->event_lock, flags);
7642         work = intel_crtc->unpin_work;
7643         intel_crtc->unpin_work = NULL;
7644         spin_unlock_irqrestore(&dev->event_lock, flags);
7645
7646         if (work) {
7647                 cancel_work_sync(&work->work);
7648                 kfree(work);
7649         }
7650
7651         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7652
7653         drm_crtc_cleanup(crtc);
7654
7655         kfree(intel_crtc);
7656 }
7657
7658 static void intel_unpin_work_fn(struct work_struct *__work)
7659 {
7660         struct intel_unpin_work *work =
7661                 container_of(__work, struct intel_unpin_work, work);
7662         struct drm_device *dev = work->crtc->dev;
7663
7664         mutex_lock(&dev->struct_mutex);
7665         intel_unpin_fb_obj(work->old_fb_obj);
7666         drm_gem_object_unreference(&work->pending_flip_obj->base);
7667         drm_gem_object_unreference(&work->old_fb_obj->base);
7668
7669         intel_update_fbc(dev);
7670         mutex_unlock(&dev->struct_mutex);
7671
7672         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7673         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7674
7675         kfree(work);
7676 }
7677
7678 static void do_intel_finish_page_flip(struct drm_device *dev,
7679                                       struct drm_crtc *crtc)
7680 {
7681         drm_i915_private_t *dev_priv = dev->dev_private;
7682         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7683         struct intel_unpin_work *work;
7684         unsigned long flags;
7685
7686         /* Ignore early vblank irqs */
7687         if (intel_crtc == NULL)
7688                 return;
7689
7690         spin_lock_irqsave(&dev->event_lock, flags);
7691         work = intel_crtc->unpin_work;
7692
7693         /* Ensure we don't miss a work->pending update ... */
7694         smp_rmb();
7695
7696         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7697                 spin_unlock_irqrestore(&dev->event_lock, flags);
7698                 return;
7699         }
7700
7701         /* and that the unpin work is consistent wrt ->pending. */
7702         smp_rmb();
7703
7704         intel_crtc->unpin_work = NULL;
7705
7706         if (work->event)
7707                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7708
7709         drm_vblank_put(dev, intel_crtc->pipe);
7710
7711         spin_unlock_irqrestore(&dev->event_lock, flags);
7712
7713         wake_up_all(&dev_priv->pending_flip_queue);
7714
7715         queue_work(dev_priv->wq, &work->work);
7716
7717         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7718 }
7719
7720 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7721 {
7722         drm_i915_private_t *dev_priv = dev->dev_private;
7723         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7724
7725         do_intel_finish_page_flip(dev, crtc);
7726 }
7727
7728 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7729 {
7730         drm_i915_private_t *dev_priv = dev->dev_private;
7731         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7732
7733         do_intel_finish_page_flip(dev, crtc);
7734 }
7735
7736 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7737 {
7738         drm_i915_private_t *dev_priv = dev->dev_private;
7739         struct intel_crtc *intel_crtc =
7740                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7741         unsigned long flags;
7742
7743         /* NB: An MMIO update of the plane base pointer will also
7744          * generate a page-flip completion irq, i.e. every modeset
7745          * is also accompanied by a spurious intel_prepare_page_flip().
7746          */
7747         spin_lock_irqsave(&dev->event_lock, flags);
7748         if (intel_crtc->unpin_work)
7749                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7750         spin_unlock_irqrestore(&dev->event_lock, flags);
7751 }
7752
7753 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7754 {
7755         /* Ensure that the work item is consistent when activating it ... */
7756         smp_wmb();
7757         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7758         /* and that it is marked active as soon as the irq could fire. */
7759         smp_wmb();
7760 }
7761
7762 static int intel_gen2_queue_flip(struct drm_device *dev,
7763                                  struct drm_crtc *crtc,
7764                                  struct drm_framebuffer *fb,
7765                                  struct drm_i915_gem_object *obj,
7766                                  uint32_t flags)
7767 {
7768         struct drm_i915_private *dev_priv = dev->dev_private;
7769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7770         u32 flip_mask;
7771         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7772         int ret;
7773
7774         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7775         if (ret)
7776                 goto err;
7777
7778         ret = intel_ring_begin(ring, 6);
7779         if (ret)
7780                 goto err_unpin;
7781
7782         /* Can't queue multiple flips, so wait for the previous
7783          * one to finish before executing the next.
7784          */
7785         if (intel_crtc->plane)
7786                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7787         else
7788                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7789         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7790         intel_ring_emit(ring, MI_NOOP);
7791         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7792                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7793         intel_ring_emit(ring, fb->pitches[0]);
7794         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7795         intel_ring_emit(ring, 0); /* aux display base address, unused */
7796
7797         intel_mark_page_flip_active(intel_crtc);
7798         __intel_ring_advance(ring);
7799         return 0;
7800
7801 err_unpin:
7802         intel_unpin_fb_obj(obj);
7803 err:
7804         return ret;
7805 }
7806
7807 static int intel_gen3_queue_flip(struct drm_device *dev,
7808                                  struct drm_crtc *crtc,
7809                                  struct drm_framebuffer *fb,
7810                                  struct drm_i915_gem_object *obj,
7811                                  uint32_t flags)
7812 {
7813         struct drm_i915_private *dev_priv = dev->dev_private;
7814         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7815         u32 flip_mask;
7816         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7817         int ret;
7818
7819         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7820         if (ret)
7821                 goto err;
7822
7823         ret = intel_ring_begin(ring, 6);
7824         if (ret)
7825                 goto err_unpin;
7826
7827         if (intel_crtc->plane)
7828                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7829         else
7830                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7831         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7832         intel_ring_emit(ring, MI_NOOP);
7833         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7834                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7835         intel_ring_emit(ring, fb->pitches[0]);
7836         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7837         intel_ring_emit(ring, MI_NOOP);
7838
7839         intel_mark_page_flip_active(intel_crtc);
7840         __intel_ring_advance(ring);
7841         return 0;
7842
7843 err_unpin:
7844         intel_unpin_fb_obj(obj);
7845 err:
7846         return ret;
7847 }
7848
7849 static int intel_gen4_queue_flip(struct drm_device *dev,
7850                                  struct drm_crtc *crtc,
7851                                  struct drm_framebuffer *fb,
7852                                  struct drm_i915_gem_object *obj,
7853                                  uint32_t flags)
7854 {
7855         struct drm_i915_private *dev_priv = dev->dev_private;
7856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7857         uint32_t pf, pipesrc;
7858         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7859         int ret;
7860
7861         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7862         if (ret)
7863                 goto err;
7864
7865         ret = intel_ring_begin(ring, 4);
7866         if (ret)
7867                 goto err_unpin;
7868
7869         /* i965+ uses the linear or tiled offsets from the
7870          * Display Registers (which do not change across a page-flip)
7871          * so we need only reprogram the base address.
7872          */
7873         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7874                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7875         intel_ring_emit(ring, fb->pitches[0]);
7876         intel_ring_emit(ring,
7877                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7878                         obj->tiling_mode);
7879
7880         /* XXX Enabling the panel-fitter across page-flip is so far
7881          * untested on non-native modes, so ignore it for now.
7882          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7883          */
7884         pf = 0;
7885         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7886         intel_ring_emit(ring, pf | pipesrc);
7887
7888         intel_mark_page_flip_active(intel_crtc);
7889         __intel_ring_advance(ring);
7890         return 0;
7891
7892 err_unpin:
7893         intel_unpin_fb_obj(obj);
7894 err:
7895         return ret;
7896 }
7897
7898 static int intel_gen6_queue_flip(struct drm_device *dev,
7899                                  struct drm_crtc *crtc,
7900                                  struct drm_framebuffer *fb,
7901                                  struct drm_i915_gem_object *obj,
7902                                  uint32_t flags)
7903 {
7904         struct drm_i915_private *dev_priv = dev->dev_private;
7905         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7906         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7907         uint32_t pf, pipesrc;
7908         int ret;
7909
7910         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7911         if (ret)
7912                 goto err;
7913
7914         ret = intel_ring_begin(ring, 4);
7915         if (ret)
7916                 goto err_unpin;
7917
7918         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7919                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7920         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7921         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7922
7923         /* Contrary to the suggestions in the documentation,
7924          * "Enable Panel Fitter" does not seem to be required when page
7925          * flipping with a non-native mode, and worse causes a normal
7926          * modeset to fail.
7927          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7928          */
7929         pf = 0;
7930         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7931         intel_ring_emit(ring, pf | pipesrc);
7932
7933         intel_mark_page_flip_active(intel_crtc);
7934         __intel_ring_advance(ring);
7935         return 0;
7936
7937 err_unpin:
7938         intel_unpin_fb_obj(obj);
7939 err:
7940         return ret;
7941 }
7942
7943 static int intel_gen7_queue_flip(struct drm_device *dev,
7944                                  struct drm_crtc *crtc,
7945                                  struct drm_framebuffer *fb,
7946                                  struct drm_i915_gem_object *obj,
7947                                  uint32_t flags)
7948 {
7949         struct drm_i915_private *dev_priv = dev->dev_private;
7950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7951         struct intel_ring_buffer *ring;
7952         uint32_t plane_bit = 0;
7953         int len, ret;
7954
7955         ring = obj->ring;
7956         if (ring == NULL || ring->id != RCS)
7957                 ring = &dev_priv->ring[BCS];
7958
7959         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7960         if (ret)
7961                 goto err;
7962
7963         switch(intel_crtc->plane) {
7964         case PLANE_A:
7965                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7966                 break;
7967         case PLANE_B:
7968                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7969                 break;
7970         case PLANE_C:
7971                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7972                 break;
7973         default:
7974                 WARN_ONCE(1, "unknown plane in flip command\n");
7975                 ret = -ENODEV;
7976                 goto err_unpin;
7977         }
7978
7979         len = 4;
7980         if (ring->id == RCS)
7981                 len += 6;
7982
7983         ret = intel_ring_begin(ring, len);
7984         if (ret)
7985                 goto err_unpin;
7986
7987         /* Unmask the flip-done completion message. Note that the bspec says that
7988          * we should do this for both the BCS and RCS, and that we must not unmask
7989          * more than one flip event at any time (or ensure that one flip message
7990          * can be sent by waiting for flip-done prior to queueing new flips).
7991          * Experimentation says that BCS works despite DERRMR masking all
7992          * flip-done completion events and that unmasking all planes at once
7993          * for the RCS also doesn't appear to drop events. Setting the DERRMR
7994          * to zero does lead to lockups within MI_DISPLAY_FLIP.
7995          */
7996         if (ring->id == RCS) {
7997                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7998                 intel_ring_emit(ring, DERRMR);
7999                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8000                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8001                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8002                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8003                 intel_ring_emit(ring, DERRMR);
8004                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8005         }
8006
8007         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8008         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8009         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8010         intel_ring_emit(ring, (MI_NOOP));
8011
8012         intel_mark_page_flip_active(intel_crtc);
8013         __intel_ring_advance(ring);
8014         return 0;
8015
8016 err_unpin:
8017         intel_unpin_fb_obj(obj);
8018 err:
8019         return ret;
8020 }
8021
8022 static int intel_default_queue_flip(struct drm_device *dev,
8023                                     struct drm_crtc *crtc,
8024                                     struct drm_framebuffer *fb,
8025                                     struct drm_i915_gem_object *obj,
8026                                     uint32_t flags)
8027 {
8028         return -ENODEV;
8029 }
8030
8031 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8032                                 struct drm_framebuffer *fb,
8033                                 struct drm_pending_vblank_event *event,
8034                                 uint32_t page_flip_flags)
8035 {
8036         struct drm_device *dev = crtc->dev;
8037         struct drm_i915_private *dev_priv = dev->dev_private;
8038         struct drm_framebuffer *old_fb = crtc->fb;
8039         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8040         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8041         struct intel_unpin_work *work;
8042         unsigned long flags;
8043         int ret;
8044
8045         /* Can't change pixel format via MI display flips. */
8046         if (fb->pixel_format != crtc->fb->pixel_format)
8047                 return -EINVAL;
8048
8049         /*
8050          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8051          * Note that pitch changes could also affect these register.
8052          */
8053         if (INTEL_INFO(dev)->gen > 3 &&
8054             (fb->offsets[0] != crtc->fb->offsets[0] ||
8055              fb->pitches[0] != crtc->fb->pitches[0]))
8056                 return -EINVAL;
8057
8058         work = kzalloc(sizeof *work, GFP_KERNEL);
8059         if (work == NULL)
8060                 return -ENOMEM;
8061
8062         work->event = event;
8063         work->crtc = crtc;
8064         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8065         INIT_WORK(&work->work, intel_unpin_work_fn);
8066
8067         ret = drm_vblank_get(dev, intel_crtc->pipe);
8068         if (ret)
8069                 goto free_work;
8070
8071         /* We borrow the event spin lock for protecting unpin_work */
8072         spin_lock_irqsave(&dev->event_lock, flags);
8073         if (intel_crtc->unpin_work) {
8074                 spin_unlock_irqrestore(&dev->event_lock, flags);
8075                 kfree(work);
8076                 drm_vblank_put(dev, intel_crtc->pipe);
8077
8078                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8079                 return -EBUSY;
8080         }
8081         intel_crtc->unpin_work = work;
8082         spin_unlock_irqrestore(&dev->event_lock, flags);
8083
8084         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8085                 flush_workqueue(dev_priv->wq);
8086
8087         ret = i915_mutex_lock_interruptible(dev);
8088         if (ret)
8089                 goto cleanup;
8090
8091         /* Reference the objects for the scheduled work. */
8092         drm_gem_object_reference(&work->old_fb_obj->base);
8093         drm_gem_object_reference(&obj->base);
8094
8095         crtc->fb = fb;
8096
8097         work->pending_flip_obj = obj;
8098
8099         work->enable_stall_check = true;
8100
8101         atomic_inc(&intel_crtc->unpin_work_count);
8102         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8103
8104         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8105         if (ret)
8106                 goto cleanup_pending;
8107
8108         intel_disable_fbc(dev);
8109         intel_mark_fb_busy(obj, NULL);
8110         mutex_unlock(&dev->struct_mutex);
8111
8112         trace_i915_flip_request(intel_crtc->plane, obj);
8113
8114         return 0;
8115
8116 cleanup_pending:
8117         atomic_dec(&intel_crtc->unpin_work_count);
8118         crtc->fb = old_fb;
8119         drm_gem_object_unreference(&work->old_fb_obj->base);
8120         drm_gem_object_unreference(&obj->base);
8121         mutex_unlock(&dev->struct_mutex);
8122
8123 cleanup:
8124         spin_lock_irqsave(&dev->event_lock, flags);
8125         intel_crtc->unpin_work = NULL;
8126         spin_unlock_irqrestore(&dev->event_lock, flags);
8127
8128         drm_vblank_put(dev, intel_crtc->pipe);
8129 free_work:
8130         kfree(work);
8131
8132         return ret;
8133 }
8134
8135 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8136         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8137         .load_lut = intel_crtc_load_lut,
8138 };
8139
8140 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8141                                   struct drm_crtc *crtc)
8142 {
8143         struct drm_device *dev;
8144         struct drm_crtc *tmp;
8145         int crtc_mask = 1;
8146
8147         WARN(!crtc, "checking null crtc?\n");
8148
8149         dev = crtc->dev;
8150
8151         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8152                 if (tmp == crtc)
8153                         break;
8154                 crtc_mask <<= 1;
8155         }
8156
8157         if (encoder->possible_crtcs & crtc_mask)
8158                 return true;
8159         return false;
8160 }
8161
8162 /**
8163  * intel_modeset_update_staged_output_state
8164  *
8165  * Updates the staged output configuration state, e.g. after we've read out the
8166  * current hw state.
8167  */
8168 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8169 {
8170         struct intel_encoder *encoder;
8171         struct intel_connector *connector;
8172
8173         list_for_each_entry(connector, &dev->mode_config.connector_list,
8174                             base.head) {
8175                 connector->new_encoder =
8176                         to_intel_encoder(connector->base.encoder);
8177         }
8178
8179         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8180                             base.head) {
8181                 encoder->new_crtc =
8182                         to_intel_crtc(encoder->base.crtc);
8183         }
8184 }
8185
8186 /**
8187  * intel_modeset_commit_output_state
8188  *
8189  * This function copies the stage display pipe configuration to the real one.
8190  */
8191 static void intel_modeset_commit_output_state(struct drm_device *dev)
8192 {
8193         struct intel_encoder *encoder;
8194         struct intel_connector *connector;
8195
8196         list_for_each_entry(connector, &dev->mode_config.connector_list,
8197                             base.head) {
8198                 connector->base.encoder = &connector->new_encoder->base;
8199         }
8200
8201         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8202                             base.head) {
8203                 encoder->base.crtc = &encoder->new_crtc->base;
8204         }
8205 }
8206
8207 static void
8208 connected_sink_compute_bpp(struct intel_connector * connector,
8209                            struct intel_crtc_config *pipe_config)
8210 {
8211         int bpp = pipe_config->pipe_bpp;
8212
8213         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8214                 connector->base.base.id,
8215                 drm_get_connector_name(&connector->base));
8216
8217         /* Don't use an invalid EDID bpc value */
8218         if (connector->base.display_info.bpc &&
8219             connector->base.display_info.bpc * 3 < bpp) {
8220                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8221                               bpp, connector->base.display_info.bpc*3);
8222                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8223         }
8224
8225         /* Clamp bpp to 8 on screens without EDID 1.4 */
8226         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8227                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8228                               bpp);
8229                 pipe_config->pipe_bpp = 24;
8230         }
8231 }
8232
8233 static int
8234 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8235                           struct drm_framebuffer *fb,
8236                           struct intel_crtc_config *pipe_config)
8237 {
8238         struct drm_device *dev = crtc->base.dev;
8239         struct intel_connector *connector;
8240         int bpp;
8241
8242         switch (fb->pixel_format) {
8243         case DRM_FORMAT_C8:
8244                 bpp = 8*3; /* since we go through a colormap */
8245                 break;
8246         case DRM_FORMAT_XRGB1555:
8247         case DRM_FORMAT_ARGB1555:
8248                 /* checked in intel_framebuffer_init already */
8249                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8250                         return -EINVAL;
8251         case DRM_FORMAT_RGB565:
8252                 bpp = 6*3; /* min is 18bpp */
8253                 break;
8254         case DRM_FORMAT_XBGR8888:
8255         case DRM_FORMAT_ABGR8888:
8256                 /* checked in intel_framebuffer_init already */
8257                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8258                         return -EINVAL;
8259         case DRM_FORMAT_XRGB8888:
8260         case DRM_FORMAT_ARGB8888:
8261                 bpp = 8*3;
8262                 break;
8263         case DRM_FORMAT_XRGB2101010:
8264         case DRM_FORMAT_ARGB2101010:
8265         case DRM_FORMAT_XBGR2101010:
8266         case DRM_FORMAT_ABGR2101010:
8267                 /* checked in intel_framebuffer_init already */
8268                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8269                         return -EINVAL;
8270                 bpp = 10*3;
8271                 break;
8272         /* TODO: gen4+ supports 16 bpc floating point, too. */
8273         default:
8274                 DRM_DEBUG_KMS("unsupported depth\n");
8275                 return -EINVAL;
8276         }
8277
8278         pipe_config->pipe_bpp = bpp;
8279
8280         /* Clamp display bpp to EDID value */
8281         list_for_each_entry(connector, &dev->mode_config.connector_list,
8282                             base.head) {
8283                 if (!connector->new_encoder ||
8284                     connector->new_encoder->new_crtc != crtc)
8285                         continue;
8286
8287                 connected_sink_compute_bpp(connector, pipe_config);
8288         }
8289
8290         return bpp;
8291 }
8292
8293 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8294                                    struct intel_crtc_config *pipe_config,
8295                                    const char *context)
8296 {
8297         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8298                       context, pipe_name(crtc->pipe));
8299
8300         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8301         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8302                       pipe_config->pipe_bpp, pipe_config->dither);
8303         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8304                       pipe_config->has_pch_encoder,
8305                       pipe_config->fdi_lanes,
8306                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8307                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8308                       pipe_config->fdi_m_n.tu);
8309         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8310                       pipe_config->has_dp_encoder,
8311                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8312                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8313                       pipe_config->dp_m_n.tu);
8314         DRM_DEBUG_KMS("requested mode:\n");
8315         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8316         DRM_DEBUG_KMS("adjusted mode:\n");
8317         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8318         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8319                       pipe_config->gmch_pfit.control,
8320                       pipe_config->gmch_pfit.pgm_ratios,
8321                       pipe_config->gmch_pfit.lvds_border_bits);
8322         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8323                       pipe_config->pch_pfit.pos,
8324                       pipe_config->pch_pfit.size);
8325         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8326 }
8327
8328 static bool check_encoder_cloning(struct drm_crtc *crtc)
8329 {
8330         int num_encoders = 0;
8331         bool uncloneable_encoders = false;
8332         struct intel_encoder *encoder;
8333
8334         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8335                             base.head) {
8336                 if (&encoder->new_crtc->base != crtc)
8337                         continue;
8338
8339                 num_encoders++;
8340                 if (!encoder->cloneable)
8341                         uncloneable_encoders = true;
8342         }
8343
8344         return !(num_encoders > 1 && uncloneable_encoders);
8345 }
8346
8347 static struct intel_crtc_config *
8348 intel_modeset_pipe_config(struct drm_crtc *crtc,
8349                           struct drm_framebuffer *fb,
8350                           struct drm_display_mode *mode)
8351 {
8352         struct drm_device *dev = crtc->dev;
8353         struct intel_encoder *encoder;
8354         struct intel_crtc_config *pipe_config;
8355         int plane_bpp, ret = -EINVAL;
8356         bool retry = true;
8357
8358         if (!check_encoder_cloning(crtc)) {
8359                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8360                 return ERR_PTR(-EINVAL);
8361         }
8362
8363         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8364         if (!pipe_config)
8365                 return ERR_PTR(-ENOMEM);
8366
8367         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8368         drm_mode_copy(&pipe_config->requested_mode, mode);
8369         pipe_config->cpu_transcoder =
8370                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8371         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8372
8373         /*
8374          * Sanitize sync polarity flags based on requested ones. If neither
8375          * positive or negative polarity is requested, treat this as meaning
8376          * negative polarity.
8377          */
8378         if (!(pipe_config->adjusted_mode.flags &
8379               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8380                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8381
8382         if (!(pipe_config->adjusted_mode.flags &
8383               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8384                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8385
8386         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8387          * plane pixel format and any sink constraints into account. Returns the
8388          * source plane bpp so that dithering can be selected on mismatches
8389          * after encoders and crtc also have had their say. */
8390         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8391                                               fb, pipe_config);
8392         if (plane_bpp < 0)
8393                 goto fail;
8394
8395 encoder_retry:
8396         /* Ensure the port clock defaults are reset when retrying. */
8397         pipe_config->port_clock = 0;
8398         pipe_config->pixel_multiplier = 1;
8399
8400         /* Fill in default crtc timings, allow encoders to overwrite them. */
8401         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8402
8403         /* Pass our mode to the connectors and the CRTC to give them a chance to
8404          * adjust it according to limitations or connector properties, and also
8405          * a chance to reject the mode entirely.
8406          */
8407         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8408                             base.head) {
8409
8410                 if (&encoder->new_crtc->base != crtc)
8411                         continue;
8412
8413                 if (!(encoder->compute_config(encoder, pipe_config))) {
8414                         DRM_DEBUG_KMS("Encoder config failure\n");
8415                         goto fail;
8416                 }
8417         }
8418
8419         /* Set default port clock if not overwritten by the encoder. Needs to be
8420          * done afterwards in case the encoder adjusts the mode. */
8421         if (!pipe_config->port_clock)
8422                 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8423                         pipe_config->pixel_multiplier;
8424
8425         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8426         if (ret < 0) {
8427                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8428                 goto fail;
8429         }
8430
8431         if (ret == RETRY) {
8432                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8433                         ret = -EINVAL;
8434                         goto fail;
8435                 }
8436
8437                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8438                 retry = false;
8439                 goto encoder_retry;
8440         }
8441
8442         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8443         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8444                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8445
8446         return pipe_config;
8447 fail:
8448         kfree(pipe_config);
8449         return ERR_PTR(ret);
8450 }
8451
8452 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8453  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8454 static void
8455 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8456                              unsigned *prepare_pipes, unsigned *disable_pipes)
8457 {
8458         struct intel_crtc *intel_crtc;
8459         struct drm_device *dev = crtc->dev;
8460         struct intel_encoder *encoder;
8461         struct intel_connector *connector;
8462         struct drm_crtc *tmp_crtc;
8463
8464         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8465
8466         /* Check which crtcs have changed outputs connected to them, these need
8467          * to be part of the prepare_pipes mask. We don't (yet) support global
8468          * modeset across multiple crtcs, so modeset_pipes will only have one
8469          * bit set at most. */
8470         list_for_each_entry(connector, &dev->mode_config.connector_list,
8471                             base.head) {
8472                 if (connector->base.encoder == &connector->new_encoder->base)
8473                         continue;
8474
8475                 if (connector->base.encoder) {
8476                         tmp_crtc = connector->base.encoder->crtc;
8477
8478                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8479                 }
8480
8481                 if (connector->new_encoder)
8482                         *prepare_pipes |=
8483                                 1 << connector->new_encoder->new_crtc->pipe;
8484         }
8485
8486         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8487                             base.head) {
8488                 if (encoder->base.crtc == &encoder->new_crtc->base)
8489                         continue;
8490
8491                 if (encoder->base.crtc) {
8492                         tmp_crtc = encoder->base.crtc;
8493
8494                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8495                 }
8496
8497                 if (encoder->new_crtc)
8498                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8499         }
8500
8501         /* Check for any pipes that will be fully disabled ... */
8502         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8503                             base.head) {
8504                 bool used = false;
8505
8506                 /* Don't try to disable disabled crtcs. */
8507                 if (!intel_crtc->base.enabled)
8508                         continue;
8509
8510                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8511                                     base.head) {
8512                         if (encoder->new_crtc == intel_crtc)
8513                                 used = true;
8514                 }
8515
8516                 if (!used)
8517                         *disable_pipes |= 1 << intel_crtc->pipe;
8518         }
8519
8520
8521         /* set_mode is also used to update properties on life display pipes. */
8522         intel_crtc = to_intel_crtc(crtc);
8523         if (crtc->enabled)
8524                 *prepare_pipes |= 1 << intel_crtc->pipe;
8525
8526         /*
8527          * For simplicity do a full modeset on any pipe where the output routing
8528          * changed. We could be more clever, but that would require us to be
8529          * more careful with calling the relevant encoder->mode_set functions.
8530          */
8531         if (*prepare_pipes)
8532                 *modeset_pipes = *prepare_pipes;
8533
8534         /* ... and mask these out. */
8535         *modeset_pipes &= ~(*disable_pipes);
8536         *prepare_pipes &= ~(*disable_pipes);
8537
8538         /*
8539          * HACK: We don't (yet) fully support global modesets. intel_set_config
8540          * obies this rule, but the modeset restore mode of
8541          * intel_modeset_setup_hw_state does not.
8542          */
8543         *modeset_pipes &= 1 << intel_crtc->pipe;
8544         *prepare_pipes &= 1 << intel_crtc->pipe;
8545
8546         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8547                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8548 }
8549
8550 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8551 {
8552         struct drm_encoder *encoder;
8553         struct drm_device *dev = crtc->dev;
8554
8555         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8556                 if (encoder->crtc == crtc)
8557                         return true;
8558
8559         return false;
8560 }
8561
8562 static void
8563 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8564 {
8565         struct intel_encoder *intel_encoder;
8566         struct intel_crtc *intel_crtc;
8567         struct drm_connector *connector;
8568
8569         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8570                             base.head) {
8571                 if (!intel_encoder->base.crtc)
8572                         continue;
8573
8574                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8575
8576                 if (prepare_pipes & (1 << intel_crtc->pipe))
8577                         intel_encoder->connectors_active = false;
8578         }
8579
8580         intel_modeset_commit_output_state(dev);
8581
8582         /* Update computed state. */
8583         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8584                             base.head) {
8585                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8586         }
8587
8588         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8589                 if (!connector->encoder || !connector->encoder->crtc)
8590                         continue;
8591
8592                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8593
8594                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8595                         struct drm_property *dpms_property =
8596                                 dev->mode_config.dpms_property;
8597
8598                         connector->dpms = DRM_MODE_DPMS_ON;
8599                         drm_object_property_set_value(&connector->base,
8600                                                          dpms_property,
8601                                                          DRM_MODE_DPMS_ON);
8602
8603                         intel_encoder = to_intel_encoder(connector->encoder);
8604                         intel_encoder->connectors_active = true;
8605                 }
8606         }
8607
8608 }
8609
8610 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8611 {
8612         int diff;
8613
8614         if (clock1 == clock2)
8615                 return true;
8616
8617         if (!clock1 || !clock2)
8618                 return false;
8619
8620         diff = abs(clock1 - clock2);
8621
8622         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8623                 return true;
8624
8625         return false;
8626 }
8627
8628 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8629         list_for_each_entry((intel_crtc), \
8630                             &(dev)->mode_config.crtc_list, \
8631                             base.head) \
8632                 if (mask & (1 <<(intel_crtc)->pipe))
8633
8634 static bool
8635 intel_pipe_config_compare(struct drm_device *dev,
8636                           struct intel_crtc_config *current_config,
8637                           struct intel_crtc_config *pipe_config)
8638 {
8639 #define PIPE_CONF_CHECK_X(name) \
8640         if (current_config->name != pipe_config->name) { \
8641                 DRM_ERROR("mismatch in " #name " " \
8642                           "(expected 0x%08x, found 0x%08x)\n", \
8643                           current_config->name, \
8644                           pipe_config->name); \
8645                 return false; \
8646         }
8647
8648 #define PIPE_CONF_CHECK_I(name) \
8649         if (current_config->name != pipe_config->name) { \
8650                 DRM_ERROR("mismatch in " #name " " \
8651                           "(expected %i, found %i)\n", \
8652                           current_config->name, \
8653                           pipe_config->name); \
8654                 return false; \
8655         }
8656
8657 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8658         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8659                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8660                           "(expected %i, found %i)\n", \
8661                           current_config->name & (mask), \
8662                           pipe_config->name & (mask)); \
8663                 return false; \
8664         }
8665
8666 #define PIPE_CONF_QUIRK(quirk)  \
8667         ((current_config->quirks | pipe_config->quirks) & (quirk))
8668
8669         PIPE_CONF_CHECK_I(cpu_transcoder);
8670
8671         PIPE_CONF_CHECK_I(has_pch_encoder);
8672         PIPE_CONF_CHECK_I(fdi_lanes);
8673         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8674         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8675         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8676         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8677         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8678
8679         PIPE_CONF_CHECK_I(has_dp_encoder);
8680         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8681         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8682         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8683         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8684         PIPE_CONF_CHECK_I(dp_m_n.tu);
8685
8686         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8687         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8688         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8689         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8690         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8691         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8692
8693         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8694         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8695         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8696         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8697         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8698         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8699
8700         PIPE_CONF_CHECK_I(pixel_multiplier);
8701
8702         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8703                               DRM_MODE_FLAG_INTERLACE);
8704
8705         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8706                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8707                                       DRM_MODE_FLAG_PHSYNC);
8708                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8709                                       DRM_MODE_FLAG_NHSYNC);
8710                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8711                                       DRM_MODE_FLAG_PVSYNC);
8712                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8713                                       DRM_MODE_FLAG_NVSYNC);
8714         }
8715
8716         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8717         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8718
8719         PIPE_CONF_CHECK_I(gmch_pfit.control);
8720         /* pfit ratios are autocomputed by the hw on gen4+ */
8721         if (INTEL_INFO(dev)->gen < 4)
8722                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8723         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8724         PIPE_CONF_CHECK_I(pch_pfit.pos);
8725         PIPE_CONF_CHECK_I(pch_pfit.size);
8726
8727         PIPE_CONF_CHECK_I(ips_enabled);
8728
8729         PIPE_CONF_CHECK_I(shared_dpll);
8730         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8731         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8732         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8733         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8734
8735         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8736                 PIPE_CONF_CHECK_I(pipe_bpp);
8737
8738 #undef PIPE_CONF_CHECK_X
8739 #undef PIPE_CONF_CHECK_I
8740 #undef PIPE_CONF_CHECK_FLAGS
8741 #undef PIPE_CONF_QUIRK
8742
8743         if (!IS_HASWELL(dev)) {
8744                 if (!intel_fuzzy_clock_check(current_config->adjusted_mode.clock,
8745                                              pipe_config->adjusted_mode.clock)) {
8746                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8747                                   current_config->adjusted_mode.clock,
8748                                   pipe_config->adjusted_mode.clock);
8749                         return false;
8750                 }
8751         }
8752
8753         return true;
8754 }
8755
8756 static void
8757 check_connector_state(struct drm_device *dev)
8758 {
8759         struct intel_connector *connector;
8760
8761         list_for_each_entry(connector, &dev->mode_config.connector_list,
8762                             base.head) {
8763                 /* This also checks the encoder/connector hw state with the
8764                  * ->get_hw_state callbacks. */
8765                 intel_connector_check_state(connector);
8766
8767                 WARN(&connector->new_encoder->base != connector->base.encoder,
8768                      "connector's staged encoder doesn't match current encoder\n");
8769         }
8770 }
8771
8772 static void
8773 check_encoder_state(struct drm_device *dev)
8774 {
8775         struct intel_encoder *encoder;
8776         struct intel_connector *connector;
8777
8778         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8779                             base.head) {
8780                 bool enabled = false;
8781                 bool active = false;
8782                 enum pipe pipe, tracked_pipe;
8783
8784                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8785                               encoder->base.base.id,
8786                               drm_get_encoder_name(&encoder->base));
8787
8788                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8789                      "encoder's stage crtc doesn't match current crtc\n");
8790                 WARN(encoder->connectors_active && !encoder->base.crtc,
8791                      "encoder's active_connectors set, but no crtc\n");
8792
8793                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8794                                     base.head) {
8795                         if (connector->base.encoder != &encoder->base)
8796                                 continue;
8797                         enabled = true;
8798                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8799                                 active = true;
8800                 }
8801                 WARN(!!encoder->base.crtc != enabled,
8802                      "encoder's enabled state mismatch "
8803                      "(expected %i, found %i)\n",
8804                      !!encoder->base.crtc, enabled);
8805                 WARN(active && !encoder->base.crtc,
8806                      "active encoder with no crtc\n");
8807
8808                 WARN(encoder->connectors_active != active,
8809                      "encoder's computed active state doesn't match tracked active state "
8810                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8811
8812                 active = encoder->get_hw_state(encoder, &pipe);
8813                 WARN(active != encoder->connectors_active,
8814                      "encoder's hw state doesn't match sw tracking "
8815                      "(expected %i, found %i)\n",
8816                      encoder->connectors_active, active);
8817
8818                 if (!encoder->base.crtc)
8819                         continue;
8820
8821                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8822                 WARN(active && pipe != tracked_pipe,
8823                      "active encoder's pipe doesn't match"
8824                      "(expected %i, found %i)\n",
8825                      tracked_pipe, pipe);
8826
8827         }
8828 }
8829
8830 static void
8831 check_crtc_state(struct drm_device *dev)
8832 {
8833         drm_i915_private_t *dev_priv = dev->dev_private;
8834         struct intel_crtc *crtc;
8835         struct intel_encoder *encoder;
8836         struct intel_crtc_config pipe_config;
8837
8838         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8839                             base.head) {
8840                 bool enabled = false;
8841                 bool active = false;
8842
8843                 memset(&pipe_config, 0, sizeof(pipe_config));
8844
8845                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8846                               crtc->base.base.id);
8847
8848                 WARN(crtc->active && !crtc->base.enabled,
8849                      "active crtc, but not enabled in sw tracking\n");
8850
8851                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8852                                     base.head) {
8853                         if (encoder->base.crtc != &crtc->base)
8854                                 continue;
8855                         enabled = true;
8856                         if (encoder->connectors_active)
8857                                 active = true;
8858                 }
8859
8860                 WARN(active != crtc->active,
8861                      "crtc's computed active state doesn't match tracked active state "
8862                      "(expected %i, found %i)\n", active, crtc->active);
8863                 WARN(enabled != crtc->base.enabled,
8864                      "crtc's computed enabled state doesn't match tracked enabled state "
8865                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8866
8867                 active = dev_priv->display.get_pipe_config(crtc,
8868                                                            &pipe_config);
8869
8870                 /* hw state is inconsistent with the pipe A quirk */
8871                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8872                         active = crtc->active;
8873
8874                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8875                                     base.head) {
8876                         enum pipe pipe;
8877                         if (encoder->base.crtc != &crtc->base)
8878                                 continue;
8879                         if (encoder->get_config &&
8880                             encoder->get_hw_state(encoder, &pipe))
8881                                 encoder->get_config(encoder, &pipe_config);
8882                 }
8883
8884                 if (dev_priv->display.get_clock)
8885                         dev_priv->display.get_clock(crtc, &pipe_config);
8886
8887                 WARN(crtc->active != active,
8888                      "crtc active state doesn't match with hw state "
8889                      "(expected %i, found %i)\n", crtc->active, active);
8890
8891                 if (active &&
8892                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8893                         WARN(1, "pipe state doesn't match!\n");
8894                         intel_dump_pipe_config(crtc, &pipe_config,
8895                                                "[hw state]");
8896                         intel_dump_pipe_config(crtc, &crtc->config,
8897                                                "[sw state]");
8898                 }
8899         }
8900 }
8901
8902 static void
8903 check_shared_dpll_state(struct drm_device *dev)
8904 {
8905         drm_i915_private_t *dev_priv = dev->dev_private;
8906         struct intel_crtc *crtc;
8907         struct intel_dpll_hw_state dpll_hw_state;
8908         int i;
8909
8910         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8911                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8912                 int enabled_crtcs = 0, active_crtcs = 0;
8913                 bool active;
8914
8915                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8916
8917                 DRM_DEBUG_KMS("%s\n", pll->name);
8918
8919                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8920
8921                 WARN(pll->active > pll->refcount,
8922                      "more active pll users than references: %i vs %i\n",
8923                      pll->active, pll->refcount);
8924                 WARN(pll->active && !pll->on,
8925                      "pll in active use but not on in sw tracking\n");
8926                 WARN(pll->on && !pll->active,
8927                      "pll in on but not on in use in sw tracking\n");
8928                 WARN(pll->on != active,
8929                      "pll on state mismatch (expected %i, found %i)\n",
8930                      pll->on, active);
8931
8932                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8933                                     base.head) {
8934                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8935                                 enabled_crtcs++;
8936                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8937                                 active_crtcs++;
8938                 }
8939                 WARN(pll->active != active_crtcs,
8940                      "pll active crtcs mismatch (expected %i, found %i)\n",
8941                      pll->active, active_crtcs);
8942                 WARN(pll->refcount != enabled_crtcs,
8943                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8944                      pll->refcount, enabled_crtcs);
8945
8946                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8947                                        sizeof(dpll_hw_state)),
8948                      "pll hw state mismatch\n");
8949         }
8950 }
8951
8952 void
8953 intel_modeset_check_state(struct drm_device *dev)
8954 {
8955         check_connector_state(dev);
8956         check_encoder_state(dev);
8957         check_crtc_state(dev);
8958         check_shared_dpll_state(dev);
8959 }
8960
8961 static int __intel_set_mode(struct drm_crtc *crtc,
8962                             struct drm_display_mode *mode,
8963                             int x, int y, struct drm_framebuffer *fb)
8964 {
8965         struct drm_device *dev = crtc->dev;
8966         drm_i915_private_t *dev_priv = dev->dev_private;
8967         struct drm_display_mode *saved_mode, *saved_hwmode;
8968         struct intel_crtc_config *pipe_config = NULL;
8969         struct intel_crtc *intel_crtc;
8970         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8971         int ret = 0;
8972
8973         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8974         if (!saved_mode)
8975                 return -ENOMEM;
8976         saved_hwmode = saved_mode + 1;
8977
8978         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8979                                      &prepare_pipes, &disable_pipes);
8980
8981         *saved_hwmode = crtc->hwmode;
8982         *saved_mode = crtc->mode;
8983
8984         /* Hack: Because we don't (yet) support global modeset on multiple
8985          * crtcs, we don't keep track of the new mode for more than one crtc.
8986          * Hence simply check whether any bit is set in modeset_pipes in all the
8987          * pieces of code that are not yet converted to deal with mutliple crtcs
8988          * changing their mode at the same time. */
8989         if (modeset_pipes) {
8990                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8991                 if (IS_ERR(pipe_config)) {
8992                         ret = PTR_ERR(pipe_config);
8993                         pipe_config = NULL;
8994
8995                         goto out;
8996                 }
8997                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8998                                        "[modeset]");
8999         }
9000
9001         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9002                 intel_crtc_disable(&intel_crtc->base);
9003
9004         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9005                 if (intel_crtc->base.enabled)
9006                         dev_priv->display.crtc_disable(&intel_crtc->base);
9007         }
9008
9009         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9010          * to set it here already despite that we pass it down the callchain.
9011          */
9012         if (modeset_pipes) {
9013                 crtc->mode = *mode;
9014                 /* mode_set/enable/disable functions rely on a correct pipe
9015                  * config. */
9016                 to_intel_crtc(crtc)->config = *pipe_config;
9017         }
9018
9019         /* Only after disabling all output pipelines that will be changed can we
9020          * update the the output configuration. */
9021         intel_modeset_update_state(dev, prepare_pipes);
9022
9023         if (dev_priv->display.modeset_global_resources)
9024                 dev_priv->display.modeset_global_resources(dev);
9025
9026         /* Set up the DPLL and any encoders state that needs to adjust or depend
9027          * on the DPLL.
9028          */
9029         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9030                 ret = intel_crtc_mode_set(&intel_crtc->base,
9031                                           x, y, fb);
9032                 if (ret)
9033                         goto done;
9034         }
9035
9036         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9037         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9038                 dev_priv->display.crtc_enable(&intel_crtc->base);
9039
9040         if (modeset_pipes) {
9041                 /* Store real post-adjustment hardware mode. */
9042                 crtc->hwmode = pipe_config->adjusted_mode;
9043
9044                 /* Calculate and store various constants which
9045                  * are later needed by vblank and swap-completion
9046                  * timestamping. They are derived from true hwmode.
9047                  */
9048                 drm_calc_timestamping_constants(crtc);
9049         }
9050
9051         /* FIXME: add subpixel order */
9052 done:
9053         if (ret && crtc->enabled) {
9054                 crtc->hwmode = *saved_hwmode;
9055                 crtc->mode = *saved_mode;
9056         }
9057
9058 out:
9059         kfree(pipe_config);
9060         kfree(saved_mode);
9061         return ret;
9062 }
9063
9064 static int intel_set_mode(struct drm_crtc *crtc,
9065                           struct drm_display_mode *mode,
9066                           int x, int y, struct drm_framebuffer *fb)
9067 {
9068         int ret;
9069
9070         ret = __intel_set_mode(crtc, mode, x, y, fb);
9071
9072         if (ret == 0)
9073                 intel_modeset_check_state(crtc->dev);
9074
9075         return ret;
9076 }
9077
9078 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9079 {
9080         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9081 }
9082
9083 #undef for_each_intel_crtc_masked
9084
9085 static void intel_set_config_free(struct intel_set_config *config)
9086 {
9087         if (!config)
9088                 return;
9089
9090         kfree(config->save_connector_encoders);
9091         kfree(config->save_encoder_crtcs);
9092         kfree(config);
9093 }
9094
9095 static int intel_set_config_save_state(struct drm_device *dev,
9096                                        struct intel_set_config *config)
9097 {
9098         struct drm_encoder *encoder;
9099         struct drm_connector *connector;
9100         int count;
9101
9102         config->save_encoder_crtcs =
9103                 kcalloc(dev->mode_config.num_encoder,
9104                         sizeof(struct drm_crtc *), GFP_KERNEL);
9105         if (!config->save_encoder_crtcs)
9106                 return -ENOMEM;
9107
9108         config->save_connector_encoders =
9109                 kcalloc(dev->mode_config.num_connector,
9110                         sizeof(struct drm_encoder *), GFP_KERNEL);
9111         if (!config->save_connector_encoders)
9112                 return -ENOMEM;
9113
9114         /* Copy data. Note that driver private data is not affected.
9115          * Should anything bad happen only the expected state is
9116          * restored, not the drivers personal bookkeeping.
9117          */
9118         count = 0;
9119         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9120                 config->save_encoder_crtcs[count++] = encoder->crtc;
9121         }
9122
9123         count = 0;
9124         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9125                 config->save_connector_encoders[count++] = connector->encoder;
9126         }
9127
9128         return 0;
9129 }
9130
9131 static void intel_set_config_restore_state(struct drm_device *dev,
9132                                            struct intel_set_config *config)
9133 {
9134         struct intel_encoder *encoder;
9135         struct intel_connector *connector;
9136         int count;
9137
9138         count = 0;
9139         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9140                 encoder->new_crtc =
9141                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9142         }
9143
9144         count = 0;
9145         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9146                 connector->new_encoder =
9147                         to_intel_encoder(config->save_connector_encoders[count++]);
9148         }
9149 }
9150
9151 static bool
9152 is_crtc_connector_off(struct drm_mode_set *set)
9153 {
9154         int i;
9155
9156         if (set->num_connectors == 0)
9157                 return false;
9158
9159         if (WARN_ON(set->connectors == NULL))
9160                 return false;
9161
9162         for (i = 0; i < set->num_connectors; i++)
9163                 if (set->connectors[i]->encoder &&
9164                     set->connectors[i]->encoder->crtc == set->crtc &&
9165                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9166                         return true;
9167
9168         return false;
9169 }
9170
9171 static void
9172 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9173                                       struct intel_set_config *config)
9174 {
9175
9176         /* We should be able to check here if the fb has the same properties
9177          * and then just flip_or_move it */
9178         if (is_crtc_connector_off(set)) {
9179                 config->mode_changed = true;
9180         } else if (set->crtc->fb != set->fb) {
9181                 /* If we have no fb then treat it as a full mode set */
9182                 if (set->crtc->fb == NULL) {
9183                         struct intel_crtc *intel_crtc =
9184                                 to_intel_crtc(set->crtc);
9185
9186                         if (intel_crtc->active && i915_fastboot) {
9187                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9188                                 config->fb_changed = true;
9189                         } else {
9190                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9191                                 config->mode_changed = true;
9192                         }
9193                 } else if (set->fb == NULL) {
9194                         config->mode_changed = true;
9195                 } else if (set->fb->pixel_format !=
9196                            set->crtc->fb->pixel_format) {
9197                         config->mode_changed = true;
9198                 } else {
9199                         config->fb_changed = true;
9200                 }
9201         }
9202
9203         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9204                 config->fb_changed = true;
9205
9206         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9207                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9208                 drm_mode_debug_printmodeline(&set->crtc->mode);
9209                 drm_mode_debug_printmodeline(set->mode);
9210                 config->mode_changed = true;
9211         }
9212
9213         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9214                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9215 }
9216
9217 static int
9218 intel_modeset_stage_output_state(struct drm_device *dev,
9219                                  struct drm_mode_set *set,
9220                                  struct intel_set_config *config)
9221 {
9222         struct drm_crtc *new_crtc;
9223         struct intel_connector *connector;
9224         struct intel_encoder *encoder;
9225         int ro;
9226
9227         /* The upper layers ensure that we either disable a crtc or have a list
9228          * of connectors. For paranoia, double-check this. */
9229         WARN_ON(!set->fb && (set->num_connectors != 0));
9230         WARN_ON(set->fb && (set->num_connectors == 0));
9231
9232         list_for_each_entry(connector, &dev->mode_config.connector_list,
9233                             base.head) {
9234                 /* Otherwise traverse passed in connector list and get encoders
9235                  * for them. */
9236                 for (ro = 0; ro < set->num_connectors; ro++) {
9237                         if (set->connectors[ro] == &connector->base) {
9238                                 connector->new_encoder = connector->encoder;
9239                                 break;
9240                         }
9241                 }
9242
9243                 /* If we disable the crtc, disable all its connectors. Also, if
9244                  * the connector is on the changing crtc but not on the new
9245                  * connector list, disable it. */
9246                 if ((!set->fb || ro == set->num_connectors) &&
9247                     connector->base.encoder &&
9248                     connector->base.encoder->crtc == set->crtc) {
9249                         connector->new_encoder = NULL;
9250
9251                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9252                                 connector->base.base.id,
9253                                 drm_get_connector_name(&connector->base));
9254                 }
9255
9256
9257                 if (&connector->new_encoder->base != connector->base.encoder) {
9258                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9259                         config->mode_changed = true;
9260                 }
9261         }
9262         /* connector->new_encoder is now updated for all connectors. */
9263
9264         /* Update crtc of enabled connectors. */
9265         list_for_each_entry(connector, &dev->mode_config.connector_list,
9266                             base.head) {
9267                 if (!connector->new_encoder)
9268                         continue;
9269
9270                 new_crtc = connector->new_encoder->base.crtc;
9271
9272                 for (ro = 0; ro < set->num_connectors; ro++) {
9273                         if (set->connectors[ro] == &connector->base)
9274                                 new_crtc = set->crtc;
9275                 }
9276
9277                 /* Make sure the new CRTC will work with the encoder */
9278                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9279                                            new_crtc)) {
9280                         return -EINVAL;
9281                 }
9282                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9283
9284                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9285                         connector->base.base.id,
9286                         drm_get_connector_name(&connector->base),
9287                         new_crtc->base.id);
9288         }
9289
9290         /* Check for any encoders that needs to be disabled. */
9291         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9292                             base.head) {
9293                 list_for_each_entry(connector,
9294                                     &dev->mode_config.connector_list,
9295                                     base.head) {
9296                         if (connector->new_encoder == encoder) {
9297                                 WARN_ON(!connector->new_encoder->new_crtc);
9298
9299                                 goto next_encoder;
9300                         }
9301                 }
9302                 encoder->new_crtc = NULL;
9303 next_encoder:
9304                 /* Only now check for crtc changes so we don't miss encoders
9305                  * that will be disabled. */
9306                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9307                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9308                         config->mode_changed = true;
9309                 }
9310         }
9311         /* Now we've also updated encoder->new_crtc for all encoders. */
9312
9313         return 0;
9314 }
9315
9316 static int intel_crtc_set_config(struct drm_mode_set *set)
9317 {
9318         struct drm_device *dev;
9319         struct drm_mode_set save_set;
9320         struct intel_set_config *config;
9321         int ret;
9322
9323         BUG_ON(!set);
9324         BUG_ON(!set->crtc);
9325         BUG_ON(!set->crtc->helper_private);
9326
9327         /* Enforce sane interface api - has been abused by the fb helper. */
9328         BUG_ON(!set->mode && set->fb);
9329         BUG_ON(set->fb && set->num_connectors == 0);
9330
9331         if (set->fb) {
9332                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9333                                 set->crtc->base.id, set->fb->base.id,
9334                                 (int)set->num_connectors, set->x, set->y);
9335         } else {
9336                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9337         }
9338
9339         dev = set->crtc->dev;
9340
9341         ret = -ENOMEM;
9342         config = kzalloc(sizeof(*config), GFP_KERNEL);
9343         if (!config)
9344                 goto out_config;
9345
9346         ret = intel_set_config_save_state(dev, config);
9347         if (ret)
9348                 goto out_config;
9349
9350         save_set.crtc = set->crtc;
9351         save_set.mode = &set->crtc->mode;
9352         save_set.x = set->crtc->x;
9353         save_set.y = set->crtc->y;
9354         save_set.fb = set->crtc->fb;
9355
9356         /* Compute whether we need a full modeset, only an fb base update or no
9357          * change at all. In the future we might also check whether only the
9358          * mode changed, e.g. for LVDS where we only change the panel fitter in
9359          * such cases. */
9360         intel_set_config_compute_mode_changes(set, config);
9361
9362         ret = intel_modeset_stage_output_state(dev, set, config);
9363         if (ret)
9364                 goto fail;
9365
9366         if (config->mode_changed) {
9367                 ret = intel_set_mode(set->crtc, set->mode,
9368                                      set->x, set->y, set->fb);
9369         } else if (config->fb_changed) {
9370                 intel_crtc_wait_for_pending_flips(set->crtc);
9371
9372                 ret = intel_pipe_set_base(set->crtc,
9373                                           set->x, set->y, set->fb);
9374         }
9375
9376         if (ret) {
9377                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9378                               set->crtc->base.id, ret);
9379 fail:
9380                 intel_set_config_restore_state(dev, config);
9381
9382                 /* Try to restore the config */
9383                 if (config->mode_changed &&
9384                     intel_set_mode(save_set.crtc, save_set.mode,
9385                                    save_set.x, save_set.y, save_set.fb))
9386                         DRM_ERROR("failed to restore config after modeset failure\n");
9387         }
9388
9389 out_config:
9390         intel_set_config_free(config);
9391         return ret;
9392 }
9393
9394 static const struct drm_crtc_funcs intel_crtc_funcs = {
9395         .cursor_set = intel_crtc_cursor_set,
9396         .cursor_move = intel_crtc_cursor_move,
9397         .gamma_set = intel_crtc_gamma_set,
9398         .set_config = intel_crtc_set_config,
9399         .destroy = intel_crtc_destroy,
9400         .page_flip = intel_crtc_page_flip,
9401 };
9402
9403 static void intel_cpu_pll_init(struct drm_device *dev)
9404 {
9405         if (HAS_DDI(dev))
9406                 intel_ddi_pll_init(dev);
9407 }
9408
9409 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9410                                       struct intel_shared_dpll *pll,
9411                                       struct intel_dpll_hw_state *hw_state)
9412 {
9413         uint32_t val;
9414
9415         val = I915_READ(PCH_DPLL(pll->id));
9416         hw_state->dpll = val;
9417         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9418         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9419
9420         return val & DPLL_VCO_ENABLE;
9421 }
9422
9423 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9424                                   struct intel_shared_dpll *pll)
9425 {
9426         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9427         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9428 }
9429
9430 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9431                                 struct intel_shared_dpll *pll)
9432 {
9433         /* PCH refclock must be enabled first */
9434         assert_pch_refclk_enabled(dev_priv);
9435
9436         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9437
9438         /* Wait for the clocks to stabilize. */
9439         POSTING_READ(PCH_DPLL(pll->id));
9440         udelay(150);
9441
9442         /* The pixel multiplier can only be updated once the
9443          * DPLL is enabled and the clocks are stable.
9444          *
9445          * So write it again.
9446          */
9447         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9448         POSTING_READ(PCH_DPLL(pll->id));
9449         udelay(200);
9450 }
9451
9452 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9453                                  struct intel_shared_dpll *pll)
9454 {
9455         struct drm_device *dev = dev_priv->dev;
9456         struct intel_crtc *crtc;
9457
9458         /* Make sure no transcoder isn't still depending on us. */
9459         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9460                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9461                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9462         }
9463
9464         I915_WRITE(PCH_DPLL(pll->id), 0);
9465         POSTING_READ(PCH_DPLL(pll->id));
9466         udelay(200);
9467 }
9468
9469 static char *ibx_pch_dpll_names[] = {
9470         "PCH DPLL A",
9471         "PCH DPLL B",
9472 };
9473
9474 static void ibx_pch_dpll_init(struct drm_device *dev)
9475 {
9476         struct drm_i915_private *dev_priv = dev->dev_private;
9477         int i;
9478
9479         dev_priv->num_shared_dpll = 2;
9480
9481         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9482                 dev_priv->shared_dplls[i].id = i;
9483                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9484                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9485                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9486                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9487                 dev_priv->shared_dplls[i].get_hw_state =
9488                         ibx_pch_dpll_get_hw_state;
9489         }
9490 }
9491
9492 static void intel_shared_dpll_init(struct drm_device *dev)
9493 {
9494         struct drm_i915_private *dev_priv = dev->dev_private;
9495
9496         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9497                 ibx_pch_dpll_init(dev);
9498         else
9499                 dev_priv->num_shared_dpll = 0;
9500
9501         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9502         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9503                       dev_priv->num_shared_dpll);
9504 }
9505
9506 static void intel_crtc_init(struct drm_device *dev, int pipe)
9507 {
9508         drm_i915_private_t *dev_priv = dev->dev_private;
9509         struct intel_crtc *intel_crtc;
9510         int i;
9511
9512         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9513         if (intel_crtc == NULL)
9514                 return;
9515
9516         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9517
9518         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9519         for (i = 0; i < 256; i++) {
9520                 intel_crtc->lut_r[i] = i;
9521                 intel_crtc->lut_g[i] = i;
9522                 intel_crtc->lut_b[i] = i;
9523         }
9524
9525         /* Swap pipes & planes for FBC on pre-965 */
9526         intel_crtc->pipe = pipe;
9527         intel_crtc->plane = pipe;
9528         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9529                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9530                 intel_crtc->plane = !pipe;
9531         }
9532
9533         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9534                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9535         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9536         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9537
9538         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9539 }
9540
9541 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9542                                 struct drm_file *file)
9543 {
9544         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9545         struct drm_mode_object *drmmode_obj;
9546         struct intel_crtc *crtc;
9547
9548         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9549                 return -ENODEV;
9550
9551         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9552                         DRM_MODE_OBJECT_CRTC);
9553
9554         if (!drmmode_obj) {
9555                 DRM_ERROR("no such CRTC id\n");
9556                 return -EINVAL;
9557         }
9558
9559         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9560         pipe_from_crtc_id->pipe = crtc->pipe;
9561
9562         return 0;
9563 }
9564
9565 static int intel_encoder_clones(struct intel_encoder *encoder)
9566 {
9567         struct drm_device *dev = encoder->base.dev;
9568         struct intel_encoder *source_encoder;
9569         int index_mask = 0;
9570         int entry = 0;
9571
9572         list_for_each_entry(source_encoder,
9573                             &dev->mode_config.encoder_list, base.head) {
9574
9575                 if (encoder == source_encoder)
9576                         index_mask |= (1 << entry);
9577
9578                 /* Intel hw has only one MUX where enocoders could be cloned. */
9579                 if (encoder->cloneable && source_encoder->cloneable)
9580                         index_mask |= (1 << entry);
9581
9582                 entry++;
9583         }
9584
9585         return index_mask;
9586 }
9587
9588 static bool has_edp_a(struct drm_device *dev)
9589 {
9590         struct drm_i915_private *dev_priv = dev->dev_private;
9591
9592         if (!IS_MOBILE(dev))
9593                 return false;
9594
9595         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9596                 return false;
9597
9598         if (IS_GEN5(dev) &&
9599             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9600                 return false;
9601
9602         return true;
9603 }
9604
9605 static void intel_setup_outputs(struct drm_device *dev)
9606 {
9607         struct drm_i915_private *dev_priv = dev->dev_private;
9608         struct intel_encoder *encoder;
9609         bool dpd_is_edp = false;
9610
9611         intel_lvds_init(dev);
9612
9613         if (!IS_ULT(dev))
9614                 intel_crt_init(dev);
9615
9616         if (HAS_DDI(dev)) {
9617                 int found;
9618
9619                 /* Haswell uses DDI functions to detect digital outputs */
9620                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9621                 /* DDI A only supports eDP */
9622                 if (found)
9623                         intel_ddi_init(dev, PORT_A);
9624
9625                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9626                  * register */
9627                 found = I915_READ(SFUSE_STRAP);
9628
9629                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9630                         intel_ddi_init(dev, PORT_B);
9631                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9632                         intel_ddi_init(dev, PORT_C);
9633                 if (found & SFUSE_STRAP_DDID_DETECTED)
9634                         intel_ddi_init(dev, PORT_D);
9635         } else if (HAS_PCH_SPLIT(dev)) {
9636                 int found;
9637                 dpd_is_edp = intel_dpd_is_edp(dev);
9638
9639                 if (has_edp_a(dev))
9640                         intel_dp_init(dev, DP_A, PORT_A);
9641
9642                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9643                         /* PCH SDVOB multiplex with HDMIB */
9644                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9645                         if (!found)
9646                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9647                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9648                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9649                 }
9650
9651                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9652                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9653
9654                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9655                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9656
9657                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9658                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9659
9660                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9661                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9662         } else if (IS_VALLEYVIEW(dev)) {
9663                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9664                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9665                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9666                                         PORT_C);
9667                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9668                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9669                                               PORT_C);
9670                 }
9671
9672                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9673                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9674                                         PORT_B);
9675                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9676                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9677                 }
9678
9679                 intel_dsi_init(dev);
9680         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9681                 bool found = false;
9682
9683                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9684                         DRM_DEBUG_KMS("probing SDVOB\n");
9685                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9686                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9687                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9688                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9689                         }
9690
9691                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9692                                 intel_dp_init(dev, DP_B, PORT_B);
9693                 }
9694
9695                 /* Before G4X SDVOC doesn't have its own detect register */
9696
9697                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9698                         DRM_DEBUG_KMS("probing SDVOC\n");
9699                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9700                 }
9701
9702                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9703
9704                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9705                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9706                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9707                         }
9708                         if (SUPPORTS_INTEGRATED_DP(dev))
9709                                 intel_dp_init(dev, DP_C, PORT_C);
9710                 }
9711
9712                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9713                     (I915_READ(DP_D) & DP_DETECTED))
9714                         intel_dp_init(dev, DP_D, PORT_D);
9715         } else if (IS_GEN2(dev))
9716                 intel_dvo_init(dev);
9717
9718         if (SUPPORTS_TV(dev))
9719                 intel_tv_init(dev);
9720
9721         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9722                 encoder->base.possible_crtcs = encoder->crtc_mask;
9723                 encoder->base.possible_clones =
9724                         intel_encoder_clones(encoder);
9725         }
9726
9727         intel_init_pch_refclk(dev);
9728
9729         drm_helper_move_panel_connectors_to_head(dev);
9730 }
9731
9732 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9733 {
9734         drm_framebuffer_cleanup(&fb->base);
9735         drm_gem_object_unreference_unlocked(&fb->obj->base);
9736 }
9737
9738 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9739 {
9740         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9741
9742         intel_framebuffer_fini(intel_fb);
9743         kfree(intel_fb);
9744 }
9745
9746 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9747                                                 struct drm_file *file,
9748                                                 unsigned int *handle)
9749 {
9750         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9751         struct drm_i915_gem_object *obj = intel_fb->obj;
9752
9753         return drm_gem_handle_create(file, &obj->base, handle);
9754 }
9755
9756 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9757         .destroy = intel_user_framebuffer_destroy,
9758         .create_handle = intel_user_framebuffer_create_handle,
9759 };
9760
9761 int intel_framebuffer_init(struct drm_device *dev,
9762                            struct intel_framebuffer *intel_fb,
9763                            struct drm_mode_fb_cmd2 *mode_cmd,
9764                            struct drm_i915_gem_object *obj)
9765 {
9766         int pitch_limit;
9767         int ret;
9768
9769         if (obj->tiling_mode == I915_TILING_Y) {
9770                 DRM_DEBUG("hardware does not support tiling Y\n");
9771                 return -EINVAL;
9772         }
9773
9774         if (mode_cmd->pitches[0] & 63) {
9775                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9776                           mode_cmd->pitches[0]);
9777                 return -EINVAL;
9778         }
9779
9780         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9781                 pitch_limit = 32*1024;
9782         } else if (INTEL_INFO(dev)->gen >= 4) {
9783                 if (obj->tiling_mode)
9784                         pitch_limit = 16*1024;
9785                 else
9786                         pitch_limit = 32*1024;
9787         } else if (INTEL_INFO(dev)->gen >= 3) {
9788                 if (obj->tiling_mode)
9789                         pitch_limit = 8*1024;
9790                 else
9791                         pitch_limit = 16*1024;
9792         } else
9793                 /* XXX DSPC is limited to 4k tiled */
9794                 pitch_limit = 8*1024;
9795
9796         if (mode_cmd->pitches[0] > pitch_limit) {
9797                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9798                           obj->tiling_mode ? "tiled" : "linear",
9799                           mode_cmd->pitches[0], pitch_limit);
9800                 return -EINVAL;
9801         }
9802
9803         if (obj->tiling_mode != I915_TILING_NONE &&
9804             mode_cmd->pitches[0] != obj->stride) {
9805                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9806                           mode_cmd->pitches[0], obj->stride);
9807                 return -EINVAL;
9808         }
9809
9810         /* Reject formats not supported by any plane early. */
9811         switch (mode_cmd->pixel_format) {
9812         case DRM_FORMAT_C8:
9813         case DRM_FORMAT_RGB565:
9814         case DRM_FORMAT_XRGB8888:
9815         case DRM_FORMAT_ARGB8888:
9816                 break;
9817         case DRM_FORMAT_XRGB1555:
9818         case DRM_FORMAT_ARGB1555:
9819                 if (INTEL_INFO(dev)->gen > 3) {
9820                         DRM_DEBUG("unsupported pixel format: %s\n",
9821                                   drm_get_format_name(mode_cmd->pixel_format));
9822                         return -EINVAL;
9823                 }
9824                 break;
9825         case DRM_FORMAT_XBGR8888:
9826         case DRM_FORMAT_ABGR8888:
9827         case DRM_FORMAT_XRGB2101010:
9828         case DRM_FORMAT_ARGB2101010:
9829         case DRM_FORMAT_XBGR2101010:
9830         case DRM_FORMAT_ABGR2101010:
9831                 if (INTEL_INFO(dev)->gen < 4) {
9832                         DRM_DEBUG("unsupported pixel format: %s\n",
9833                                   drm_get_format_name(mode_cmd->pixel_format));
9834                         return -EINVAL;
9835                 }
9836                 break;
9837         case DRM_FORMAT_YUYV:
9838         case DRM_FORMAT_UYVY:
9839         case DRM_FORMAT_YVYU:
9840         case DRM_FORMAT_VYUY:
9841                 if (INTEL_INFO(dev)->gen < 5) {
9842                         DRM_DEBUG("unsupported pixel format: %s\n",
9843                                   drm_get_format_name(mode_cmd->pixel_format));
9844                         return -EINVAL;
9845                 }
9846                 break;
9847         default:
9848                 DRM_DEBUG("unsupported pixel format: %s\n",
9849                           drm_get_format_name(mode_cmd->pixel_format));
9850                 return -EINVAL;
9851         }
9852
9853         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9854         if (mode_cmd->offsets[0] != 0)
9855                 return -EINVAL;
9856
9857         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9858         intel_fb->obj = obj;
9859
9860         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9861         if (ret) {
9862                 DRM_ERROR("framebuffer init failed %d\n", ret);
9863                 return ret;
9864         }
9865
9866         return 0;
9867 }
9868
9869 static struct drm_framebuffer *
9870 intel_user_framebuffer_create(struct drm_device *dev,
9871                               struct drm_file *filp,
9872                               struct drm_mode_fb_cmd2 *mode_cmd)
9873 {
9874         struct drm_i915_gem_object *obj;
9875
9876         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9877                                                 mode_cmd->handles[0]));
9878         if (&obj->base == NULL)
9879                 return ERR_PTR(-ENOENT);
9880
9881         return intel_framebuffer_create(dev, mode_cmd, obj);
9882 }
9883
9884 static const struct drm_mode_config_funcs intel_mode_funcs = {
9885         .fb_create = intel_user_framebuffer_create,
9886         .output_poll_changed = intel_fb_output_poll_changed,
9887 };
9888
9889 /* Set up chip specific display functions */
9890 static void intel_init_display(struct drm_device *dev)
9891 {
9892         struct drm_i915_private *dev_priv = dev->dev_private;
9893
9894         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9895                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9896         else if (IS_VALLEYVIEW(dev))
9897                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9898         else if (IS_PINEVIEW(dev))
9899                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9900         else
9901                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9902
9903         if (HAS_DDI(dev)) {
9904                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9905                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9906                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9907                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9908                 dev_priv->display.off = haswell_crtc_off;
9909                 dev_priv->display.update_plane = ironlake_update_plane;
9910         } else if (HAS_PCH_SPLIT(dev)) {
9911                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9912                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9913                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9914                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9915                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9916                 dev_priv->display.off = ironlake_crtc_off;
9917                 dev_priv->display.update_plane = ironlake_update_plane;
9918         } else if (IS_VALLEYVIEW(dev)) {
9919                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9920                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9921                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9922                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9923                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9924                 dev_priv->display.off = i9xx_crtc_off;
9925                 dev_priv->display.update_plane = i9xx_update_plane;
9926         } else {
9927                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9928                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9929                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9930                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9931                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9932                 dev_priv->display.off = i9xx_crtc_off;
9933                 dev_priv->display.update_plane = i9xx_update_plane;
9934         }
9935
9936         /* Returns the core display clock speed */
9937         if (IS_VALLEYVIEW(dev))
9938                 dev_priv->display.get_display_clock_speed =
9939                         valleyview_get_display_clock_speed;
9940         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9941                 dev_priv->display.get_display_clock_speed =
9942                         i945_get_display_clock_speed;
9943         else if (IS_I915G(dev))
9944                 dev_priv->display.get_display_clock_speed =
9945                         i915_get_display_clock_speed;
9946         else if (IS_I945GM(dev) || IS_845G(dev))
9947                 dev_priv->display.get_display_clock_speed =
9948                         i9xx_misc_get_display_clock_speed;
9949         else if (IS_PINEVIEW(dev))
9950                 dev_priv->display.get_display_clock_speed =
9951                         pnv_get_display_clock_speed;
9952         else if (IS_I915GM(dev))
9953                 dev_priv->display.get_display_clock_speed =
9954                         i915gm_get_display_clock_speed;
9955         else if (IS_I865G(dev))
9956                 dev_priv->display.get_display_clock_speed =
9957                         i865_get_display_clock_speed;
9958         else if (IS_I85X(dev))
9959                 dev_priv->display.get_display_clock_speed =
9960                         i855_get_display_clock_speed;
9961         else /* 852, 830 */
9962                 dev_priv->display.get_display_clock_speed =
9963                         i830_get_display_clock_speed;
9964
9965         if (HAS_PCH_SPLIT(dev)) {
9966                 if (IS_GEN5(dev)) {
9967                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9968                         dev_priv->display.write_eld = ironlake_write_eld;
9969                 } else if (IS_GEN6(dev)) {
9970                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9971                         dev_priv->display.write_eld = ironlake_write_eld;
9972                 } else if (IS_IVYBRIDGE(dev)) {
9973                         /* FIXME: detect B0+ stepping and use auto training */
9974                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9975                         dev_priv->display.write_eld = ironlake_write_eld;
9976                         dev_priv->display.modeset_global_resources =
9977                                 ivb_modeset_global_resources;
9978                 } else if (IS_HASWELL(dev)) {
9979                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9980                         dev_priv->display.write_eld = haswell_write_eld;
9981                         dev_priv->display.modeset_global_resources =
9982                                 haswell_modeset_global_resources;
9983                 }
9984         } else if (IS_G4X(dev)) {
9985                 dev_priv->display.write_eld = g4x_write_eld;
9986         }
9987
9988         /* Default just returns -ENODEV to indicate unsupported */
9989         dev_priv->display.queue_flip = intel_default_queue_flip;
9990
9991         switch (INTEL_INFO(dev)->gen) {
9992         case 2:
9993                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9994                 break;
9995
9996         case 3:
9997                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9998                 break;
9999
10000         case 4:
10001         case 5:
10002                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10003                 break;
10004
10005         case 6:
10006                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10007                 break;
10008         case 7:
10009                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10010                 break;
10011         }
10012 }
10013
10014 /*
10015  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10016  * resume, or other times.  This quirk makes sure that's the case for
10017  * affected systems.
10018  */
10019 static void quirk_pipea_force(struct drm_device *dev)
10020 {
10021         struct drm_i915_private *dev_priv = dev->dev_private;
10022
10023         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10024         DRM_INFO("applying pipe a force quirk\n");
10025 }
10026
10027 /*
10028  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10029  */
10030 static void quirk_ssc_force_disable(struct drm_device *dev)
10031 {
10032         struct drm_i915_private *dev_priv = dev->dev_private;
10033         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10034         DRM_INFO("applying lvds SSC disable quirk\n");
10035 }
10036
10037 /*
10038  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10039  * brightness value
10040  */
10041 static void quirk_invert_brightness(struct drm_device *dev)
10042 {
10043         struct drm_i915_private *dev_priv = dev->dev_private;
10044         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10045         DRM_INFO("applying inverted panel brightness quirk\n");
10046 }
10047
10048 /*
10049  * Some machines (Dell XPS13) suffer broken backlight controls if
10050  * BLM_PCH_PWM_ENABLE is set.
10051  */
10052 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10053 {
10054         struct drm_i915_private *dev_priv = dev->dev_private;
10055         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10056         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10057 }
10058
10059 struct intel_quirk {
10060         int device;
10061         int subsystem_vendor;
10062         int subsystem_device;
10063         void (*hook)(struct drm_device *dev);
10064 };
10065
10066 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10067 struct intel_dmi_quirk {
10068         void (*hook)(struct drm_device *dev);
10069         const struct dmi_system_id (*dmi_id_list)[];
10070 };
10071
10072 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10073 {
10074         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10075         return 1;
10076 }
10077
10078 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10079         {
10080                 .dmi_id_list = &(const struct dmi_system_id[]) {
10081                         {
10082                                 .callback = intel_dmi_reverse_brightness,
10083                                 .ident = "NCR Corporation",
10084                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10085                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10086                                 },
10087                         },
10088                         { }  /* terminating entry */
10089                 },
10090                 .hook = quirk_invert_brightness,
10091         },
10092 };
10093
10094 static struct intel_quirk intel_quirks[] = {
10095         /* HP Mini needs pipe A force quirk (LP: #322104) */
10096         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10097
10098         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10099         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10100
10101         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10102         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10103
10104         /* 830/845 need to leave pipe A & dpll A up */
10105         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10106         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10107
10108         /* Lenovo U160 cannot use SSC on LVDS */
10109         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10110
10111         /* Sony Vaio Y cannot use SSC on LVDS */
10112         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10113
10114         /* Acer Aspire 5734Z must invert backlight brightness */
10115         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10116
10117         /* Acer/eMachines G725 */
10118         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10119
10120         /* Acer/eMachines e725 */
10121         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10122
10123         /* Acer/Packard Bell NCL20 */
10124         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10125
10126         /* Acer Aspire 4736Z */
10127         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10128
10129         /* Dell XPS13 HD Sandy Bridge */
10130         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10131         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10132         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10133 };
10134
10135 static void intel_init_quirks(struct drm_device *dev)
10136 {
10137         struct pci_dev *d = dev->pdev;
10138         int i;
10139
10140         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10141                 struct intel_quirk *q = &intel_quirks[i];
10142
10143                 if (d->device == q->device &&
10144                     (d->subsystem_vendor == q->subsystem_vendor ||
10145                      q->subsystem_vendor == PCI_ANY_ID) &&
10146                     (d->subsystem_device == q->subsystem_device ||
10147                      q->subsystem_device == PCI_ANY_ID))
10148                         q->hook(dev);
10149         }
10150         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10151                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10152                         intel_dmi_quirks[i].hook(dev);
10153         }
10154 }
10155
10156 /* Disable the VGA plane that we never use */
10157 static void i915_disable_vga(struct drm_device *dev)
10158 {
10159         struct drm_i915_private *dev_priv = dev->dev_private;
10160         u8 sr1;
10161         u32 vga_reg = i915_vgacntrl_reg(dev);
10162
10163         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10164         outb(SR01, VGA_SR_INDEX);
10165         sr1 = inb(VGA_SR_DATA);
10166         outb(sr1 | 1<<5, VGA_SR_DATA);
10167
10168         /* Disable VGA memory on Intel HD */
10169         if (HAS_PCH_SPLIT(dev)) {
10170                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10171                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10172                                                    VGA_RSRC_NORMAL_IO |
10173                                                    VGA_RSRC_NORMAL_MEM);
10174         }
10175
10176         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10177         udelay(300);
10178
10179         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10180         POSTING_READ(vga_reg);
10181 }
10182
10183 static void i915_enable_vga(struct drm_device *dev)
10184 {
10185         /* Enable VGA memory on Intel HD */
10186         if (HAS_PCH_SPLIT(dev)) {
10187                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10188                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10189                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10190                                                    VGA_RSRC_LEGACY_MEM |
10191                                                    VGA_RSRC_NORMAL_IO |
10192                                                    VGA_RSRC_NORMAL_MEM);
10193                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10194         }
10195 }
10196
10197 void intel_modeset_init_hw(struct drm_device *dev)
10198 {
10199         intel_init_power_well(dev);
10200
10201         intel_prepare_ddi(dev);
10202
10203         intel_init_clock_gating(dev);
10204
10205         mutex_lock(&dev->struct_mutex);
10206         intel_enable_gt_powersave(dev);
10207         mutex_unlock(&dev->struct_mutex);
10208 }
10209
10210 void intel_modeset_suspend_hw(struct drm_device *dev)
10211 {
10212         intel_suspend_hw(dev);
10213 }
10214
10215 void intel_modeset_init(struct drm_device *dev)
10216 {
10217         struct drm_i915_private *dev_priv = dev->dev_private;
10218         int i, j, ret;
10219
10220         drm_mode_config_init(dev);
10221
10222         dev->mode_config.min_width = 0;
10223         dev->mode_config.min_height = 0;
10224
10225         dev->mode_config.preferred_depth = 24;
10226         dev->mode_config.prefer_shadow = 1;
10227
10228         dev->mode_config.funcs = &intel_mode_funcs;
10229
10230         intel_init_quirks(dev);
10231
10232         intel_init_pm(dev);
10233
10234         if (INTEL_INFO(dev)->num_pipes == 0)
10235                 return;
10236
10237         intel_init_display(dev);
10238
10239         if (IS_GEN2(dev)) {
10240                 dev->mode_config.max_width = 2048;
10241                 dev->mode_config.max_height = 2048;
10242         } else if (IS_GEN3(dev)) {
10243                 dev->mode_config.max_width = 4096;
10244                 dev->mode_config.max_height = 4096;
10245         } else {
10246                 dev->mode_config.max_width = 8192;
10247                 dev->mode_config.max_height = 8192;
10248         }
10249         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10250
10251         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10252                       INTEL_INFO(dev)->num_pipes,
10253                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10254
10255         for_each_pipe(i) {
10256                 intel_crtc_init(dev, i);
10257                 for (j = 0; j < dev_priv->num_plane; j++) {
10258                         ret = intel_plane_init(dev, i, j);
10259                         if (ret)
10260                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10261                                               pipe_name(i), sprite_name(i, j), ret);
10262                 }
10263         }
10264
10265         intel_cpu_pll_init(dev);
10266         intel_shared_dpll_init(dev);
10267
10268         /* Just disable it once at startup */
10269         i915_disable_vga(dev);
10270         intel_setup_outputs(dev);
10271
10272         /* Just in case the BIOS is doing something questionable. */
10273         intel_disable_fbc(dev);
10274 }
10275
10276 static void
10277 intel_connector_break_all_links(struct intel_connector *connector)
10278 {
10279         connector->base.dpms = DRM_MODE_DPMS_OFF;
10280         connector->base.encoder = NULL;
10281         connector->encoder->connectors_active = false;
10282         connector->encoder->base.crtc = NULL;
10283 }
10284
10285 static void intel_enable_pipe_a(struct drm_device *dev)
10286 {
10287         struct intel_connector *connector;
10288         struct drm_connector *crt = NULL;
10289         struct intel_load_detect_pipe load_detect_temp;
10290
10291         /* We can't just switch on the pipe A, we need to set things up with a
10292          * proper mode and output configuration. As a gross hack, enable pipe A
10293          * by enabling the load detect pipe once. */
10294         list_for_each_entry(connector,
10295                             &dev->mode_config.connector_list,
10296                             base.head) {
10297                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10298                         crt = &connector->base;
10299                         break;
10300                 }
10301         }
10302
10303         if (!crt)
10304                 return;
10305
10306         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10307                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10308
10309
10310 }
10311
10312 static bool
10313 intel_check_plane_mapping(struct intel_crtc *crtc)
10314 {
10315         struct drm_device *dev = crtc->base.dev;
10316         struct drm_i915_private *dev_priv = dev->dev_private;
10317         u32 reg, val;
10318
10319         if (INTEL_INFO(dev)->num_pipes == 1)
10320                 return true;
10321
10322         reg = DSPCNTR(!crtc->plane);
10323         val = I915_READ(reg);
10324
10325         if ((val & DISPLAY_PLANE_ENABLE) &&
10326             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10327                 return false;
10328
10329         return true;
10330 }
10331
10332 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10333 {
10334         struct drm_device *dev = crtc->base.dev;
10335         struct drm_i915_private *dev_priv = dev->dev_private;
10336         u32 reg;
10337
10338         /* Clear any frame start delays used for debugging left by the BIOS */
10339         reg = PIPECONF(crtc->config.cpu_transcoder);
10340         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10341
10342         /* We need to sanitize the plane -> pipe mapping first because this will
10343          * disable the crtc (and hence change the state) if it is wrong. Note
10344          * that gen4+ has a fixed plane -> pipe mapping.  */
10345         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10346                 struct intel_connector *connector;
10347                 bool plane;
10348
10349                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10350                               crtc->base.base.id);
10351
10352                 /* Pipe has the wrong plane attached and the plane is active.
10353                  * Temporarily change the plane mapping and disable everything
10354                  * ...  */
10355                 plane = crtc->plane;
10356                 crtc->plane = !plane;
10357                 dev_priv->display.crtc_disable(&crtc->base);
10358                 crtc->plane = plane;
10359
10360                 /* ... and break all links. */
10361                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10362                                     base.head) {
10363                         if (connector->encoder->base.crtc != &crtc->base)
10364                                 continue;
10365
10366                         intel_connector_break_all_links(connector);
10367                 }
10368
10369                 WARN_ON(crtc->active);
10370                 crtc->base.enabled = false;
10371         }
10372
10373         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10374             crtc->pipe == PIPE_A && !crtc->active) {
10375                 /* BIOS forgot to enable pipe A, this mostly happens after
10376                  * resume. Force-enable the pipe to fix this, the update_dpms
10377                  * call below we restore the pipe to the right state, but leave
10378                  * the required bits on. */
10379                 intel_enable_pipe_a(dev);
10380         }
10381
10382         /* Adjust the state of the output pipe according to whether we
10383          * have active connectors/encoders. */
10384         intel_crtc_update_dpms(&crtc->base);
10385
10386         if (crtc->active != crtc->base.enabled) {
10387                 struct intel_encoder *encoder;
10388
10389                 /* This can happen either due to bugs in the get_hw_state
10390                  * functions or because the pipe is force-enabled due to the
10391                  * pipe A quirk. */
10392                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10393                               crtc->base.base.id,
10394                               crtc->base.enabled ? "enabled" : "disabled",
10395                               crtc->active ? "enabled" : "disabled");
10396
10397                 crtc->base.enabled = crtc->active;
10398
10399                 /* Because we only establish the connector -> encoder ->
10400                  * crtc links if something is active, this means the
10401                  * crtc is now deactivated. Break the links. connector
10402                  * -> encoder links are only establish when things are
10403                  *  actually up, hence no need to break them. */
10404                 WARN_ON(crtc->active);
10405
10406                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10407                         WARN_ON(encoder->connectors_active);
10408                         encoder->base.crtc = NULL;
10409                 }
10410         }
10411 }
10412
10413 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10414 {
10415         struct intel_connector *connector;
10416         struct drm_device *dev = encoder->base.dev;
10417
10418         /* We need to check both for a crtc link (meaning that the
10419          * encoder is active and trying to read from a pipe) and the
10420          * pipe itself being active. */
10421         bool has_active_crtc = encoder->base.crtc &&
10422                 to_intel_crtc(encoder->base.crtc)->active;
10423
10424         if (encoder->connectors_active && !has_active_crtc) {
10425                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10426                               encoder->base.base.id,
10427                               drm_get_encoder_name(&encoder->base));
10428
10429                 /* Connector is active, but has no active pipe. This is
10430                  * fallout from our resume register restoring. Disable
10431                  * the encoder manually again. */
10432                 if (encoder->base.crtc) {
10433                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10434                                       encoder->base.base.id,
10435                                       drm_get_encoder_name(&encoder->base));
10436                         encoder->disable(encoder);
10437                 }
10438
10439                 /* Inconsistent output/port/pipe state happens presumably due to
10440                  * a bug in one of the get_hw_state functions. Or someplace else
10441                  * in our code, like the register restore mess on resume. Clamp
10442                  * things to off as a safer default. */
10443                 list_for_each_entry(connector,
10444                                     &dev->mode_config.connector_list,
10445                                     base.head) {
10446                         if (connector->encoder != encoder)
10447                                 continue;
10448
10449                         intel_connector_break_all_links(connector);
10450                 }
10451         }
10452         /* Enabled encoders without active connectors will be fixed in
10453          * the crtc fixup. */
10454 }
10455
10456 void i915_redisable_vga(struct drm_device *dev)
10457 {
10458         struct drm_i915_private *dev_priv = dev->dev_private;
10459         u32 vga_reg = i915_vgacntrl_reg(dev);
10460
10461         /* This function can be called both from intel_modeset_setup_hw_state or
10462          * at a very early point in our resume sequence, where the power well
10463          * structures are not yet restored. Since this function is at a very
10464          * paranoid "someone might have enabled VGA while we were not looking"
10465          * level, just check if the power well is enabled instead of trying to
10466          * follow the "don't touch the power well if we don't need it" policy
10467          * the rest of the driver uses. */
10468         if (HAS_POWER_WELL(dev) &&
10469             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10470                 return;
10471
10472         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10473                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10474                 i915_disable_vga(dev);
10475         }
10476 }
10477
10478 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10479 {
10480         struct drm_i915_private *dev_priv = dev->dev_private;
10481         enum pipe pipe;
10482         struct intel_crtc *crtc;
10483         struct intel_encoder *encoder;
10484         struct intel_connector *connector;
10485         int i;
10486
10487         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10488                             base.head) {
10489                 memset(&crtc->config, 0, sizeof(crtc->config));
10490
10491                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10492                                                                  &crtc->config);
10493
10494                 crtc->base.enabled = crtc->active;
10495
10496                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10497                               crtc->base.base.id,
10498                               crtc->active ? "enabled" : "disabled");
10499         }
10500
10501         /* FIXME: Smash this into the new shared dpll infrastructure. */
10502         if (HAS_DDI(dev))
10503                 intel_ddi_setup_hw_pll_state(dev);
10504
10505         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10506                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10507
10508                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10509                 pll->active = 0;
10510                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10511                                     base.head) {
10512                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10513                                 pll->active++;
10514                 }
10515                 pll->refcount = pll->active;
10516
10517                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10518                               pll->name, pll->refcount, pll->on);
10519         }
10520
10521         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10522                             base.head) {
10523                 pipe = 0;
10524
10525                 if (encoder->get_hw_state(encoder, &pipe)) {
10526                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10527                         encoder->base.crtc = &crtc->base;
10528                         if (encoder->get_config)
10529                                 encoder->get_config(encoder, &crtc->config);
10530                 } else {
10531                         encoder->base.crtc = NULL;
10532                 }
10533
10534                 encoder->connectors_active = false;
10535                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10536                               encoder->base.base.id,
10537                               drm_get_encoder_name(&encoder->base),
10538                               encoder->base.crtc ? "enabled" : "disabled",
10539                               pipe);
10540         }
10541
10542         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10543                             base.head) {
10544                 if (!crtc->active)
10545                         continue;
10546                 if (dev_priv->display.get_clock)
10547                         dev_priv->display.get_clock(crtc,
10548                                                     &crtc->config);
10549         }
10550
10551         list_for_each_entry(connector, &dev->mode_config.connector_list,
10552                             base.head) {
10553                 if (connector->get_hw_state(connector)) {
10554                         connector->base.dpms = DRM_MODE_DPMS_ON;
10555                         connector->encoder->connectors_active = true;
10556                         connector->base.encoder = &connector->encoder->base;
10557                 } else {
10558                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10559                         connector->base.encoder = NULL;
10560                 }
10561                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10562                               connector->base.base.id,
10563                               drm_get_connector_name(&connector->base),
10564                               connector->base.encoder ? "enabled" : "disabled");
10565         }
10566 }
10567
10568 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10569  * and i915 state tracking structures. */
10570 void intel_modeset_setup_hw_state(struct drm_device *dev,
10571                                   bool force_restore)
10572 {
10573         struct drm_i915_private *dev_priv = dev->dev_private;
10574         enum pipe pipe;
10575         struct drm_plane *plane;
10576         struct intel_crtc *crtc;
10577         struct intel_encoder *encoder;
10578         int i;
10579
10580         intel_modeset_readout_hw_state(dev);
10581
10582         /*
10583          * Now that we have the config, copy it to each CRTC struct
10584          * Note that this could go away if we move to using crtc_config
10585          * checking everywhere.
10586          */
10587         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10588                             base.head) {
10589                 if (crtc->active && i915_fastboot) {
10590                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10591
10592                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10593                                       crtc->base.base.id);
10594                         drm_mode_debug_printmodeline(&crtc->base.mode);
10595                 }
10596         }
10597
10598         /* HW state is read out, now we need to sanitize this mess. */
10599         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10600                             base.head) {
10601                 intel_sanitize_encoder(encoder);
10602         }
10603
10604         for_each_pipe(pipe) {
10605                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10606                 intel_sanitize_crtc(crtc);
10607                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10608         }
10609
10610         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10611                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10612
10613                 if (!pll->on || pll->active)
10614                         continue;
10615
10616                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10617
10618                 pll->disable(dev_priv, pll);
10619                 pll->on = false;
10620         }
10621
10622         if (force_restore) {
10623                 /*
10624                  * We need to use raw interfaces for restoring state to avoid
10625                  * checking (bogus) intermediate states.
10626                  */
10627                 for_each_pipe(pipe) {
10628                         struct drm_crtc *crtc =
10629                                 dev_priv->pipe_to_crtc_mapping[pipe];
10630
10631                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10632                                          crtc->fb);
10633                 }
10634                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10635                         intel_plane_restore(plane);
10636
10637                 i915_redisable_vga(dev);
10638         } else {
10639                 intel_modeset_update_staged_output_state(dev);
10640         }
10641
10642         intel_modeset_check_state(dev);
10643
10644         drm_mode_config_reset(dev);
10645 }
10646
10647 void intel_modeset_gem_init(struct drm_device *dev)
10648 {
10649         intel_modeset_init_hw(dev);
10650
10651         intel_setup_overlay(dev);
10652
10653         intel_modeset_setup_hw_state(dev, false);
10654 }
10655
10656 void intel_modeset_cleanup(struct drm_device *dev)
10657 {
10658         struct drm_i915_private *dev_priv = dev->dev_private;
10659         struct drm_crtc *crtc;
10660
10661         /*
10662          * Interrupts and polling as the first thing to avoid creating havoc.
10663          * Too much stuff here (turning of rps, connectors, ...) would
10664          * experience fancy races otherwise.
10665          */
10666         drm_irq_uninstall(dev);
10667         cancel_work_sync(&dev_priv->hotplug_work);
10668         /*
10669          * Due to the hpd irq storm handling the hotplug work can re-arm the
10670          * poll handlers. Hence disable polling after hpd handling is shut down.
10671          */
10672         drm_kms_helper_poll_fini(dev);
10673
10674         mutex_lock(&dev->struct_mutex);
10675
10676         intel_unregister_dsm_handler();
10677
10678         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10679                 /* Skip inactive CRTCs */
10680                 if (!crtc->fb)
10681                         continue;
10682
10683                 intel_increase_pllclock(crtc);
10684         }
10685
10686         intel_disable_fbc(dev);
10687
10688         i915_enable_vga(dev);
10689
10690         intel_disable_gt_powersave(dev);
10691
10692         ironlake_teardown_rc6(dev);
10693
10694         mutex_unlock(&dev->struct_mutex);
10695
10696         /* flush any delayed tasks or pending work */
10697         flush_scheduled_work();
10698
10699         /* destroy backlight, if any, before the connectors */
10700         intel_panel_destroy_backlight(dev);
10701
10702         drm_mode_config_cleanup(dev);
10703
10704         intel_cleanup_overlay(dev);
10705 }
10706
10707 /*
10708  * Return which encoder is currently attached for connector.
10709  */
10710 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10711 {
10712         return &intel_attached_encoder(connector)->base;
10713 }
10714
10715 void intel_connector_attach_encoder(struct intel_connector *connector,
10716                                     struct intel_encoder *encoder)
10717 {
10718         connector->encoder = encoder;
10719         drm_mode_connector_attach_encoder(&connector->base,
10720                                           &encoder->base);
10721 }
10722
10723 /*
10724  * set vga decode state - true == enable VGA decode
10725  */
10726 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10727 {
10728         struct drm_i915_private *dev_priv = dev->dev_private;
10729         u16 gmch_ctrl;
10730
10731         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10732         if (state)
10733                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10734         else
10735                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10736         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10737         return 0;
10738 }
10739
10740 struct intel_display_error_state {
10741
10742         u32 power_well_driver;
10743
10744         int num_transcoders;
10745
10746         struct intel_cursor_error_state {
10747                 u32 control;
10748                 u32 position;
10749                 u32 base;
10750                 u32 size;
10751         } cursor[I915_MAX_PIPES];
10752
10753         struct intel_pipe_error_state {
10754                 u32 source;
10755         } pipe[I915_MAX_PIPES];
10756
10757         struct intel_plane_error_state {
10758                 u32 control;
10759                 u32 stride;
10760                 u32 size;
10761                 u32 pos;
10762                 u32 addr;
10763                 u32 surface;
10764                 u32 tile_offset;
10765         } plane[I915_MAX_PIPES];
10766
10767         struct intel_transcoder_error_state {
10768                 enum transcoder cpu_transcoder;
10769
10770                 u32 conf;
10771
10772                 u32 htotal;
10773                 u32 hblank;
10774                 u32 hsync;
10775                 u32 vtotal;
10776                 u32 vblank;
10777                 u32 vsync;
10778         } transcoder[4];
10779 };
10780
10781 struct intel_display_error_state *
10782 intel_display_capture_error_state(struct drm_device *dev)
10783 {
10784         drm_i915_private_t *dev_priv = dev->dev_private;
10785         struct intel_display_error_state *error;
10786         int transcoders[] = {
10787                 TRANSCODER_A,
10788                 TRANSCODER_B,
10789                 TRANSCODER_C,
10790                 TRANSCODER_EDP,
10791         };
10792         int i;
10793
10794         if (INTEL_INFO(dev)->num_pipes == 0)
10795                 return NULL;
10796
10797         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10798         if (error == NULL)
10799                 return NULL;
10800
10801         if (HAS_POWER_WELL(dev))
10802                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10803
10804         for_each_pipe(i) {
10805                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10806                         error->cursor[i].control = I915_READ(CURCNTR(i));
10807                         error->cursor[i].position = I915_READ(CURPOS(i));
10808                         error->cursor[i].base = I915_READ(CURBASE(i));
10809                 } else {
10810                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10811                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10812                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10813                 }
10814
10815                 error->plane[i].control = I915_READ(DSPCNTR(i));
10816                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10817                 if (INTEL_INFO(dev)->gen <= 3) {
10818                         error->plane[i].size = I915_READ(DSPSIZE(i));
10819                         error->plane[i].pos = I915_READ(DSPPOS(i));
10820                 }
10821                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10822                         error->plane[i].addr = I915_READ(DSPADDR(i));
10823                 if (INTEL_INFO(dev)->gen >= 4) {
10824                         error->plane[i].surface = I915_READ(DSPSURF(i));
10825                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10826                 }
10827
10828                 error->pipe[i].source = I915_READ(PIPESRC(i));
10829         }
10830
10831         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10832         if (HAS_DDI(dev_priv->dev))
10833                 error->num_transcoders++; /* Account for eDP. */
10834
10835         for (i = 0; i < error->num_transcoders; i++) {
10836                 enum transcoder cpu_transcoder = transcoders[i];
10837
10838                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10839
10840                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10841                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10842                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10843                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10844                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10845                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10846                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10847         }
10848
10849         /* In the code above we read the registers without checking if the power
10850          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10851          * prevent the next I915_WRITE from detecting it and printing an error
10852          * message. */
10853         intel_uncore_clear_errors(dev);
10854
10855         return error;
10856 }
10857
10858 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10859
10860 void
10861 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10862                                 struct drm_device *dev,
10863                                 struct intel_display_error_state *error)
10864 {
10865         int i;
10866
10867         if (!error)
10868                 return;
10869
10870         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10871         if (HAS_POWER_WELL(dev))
10872                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10873                            error->power_well_driver);
10874         for_each_pipe(i) {
10875                 err_printf(m, "Pipe [%d]:\n", i);
10876                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10877
10878                 err_printf(m, "Plane [%d]:\n", i);
10879                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10880                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10881                 if (INTEL_INFO(dev)->gen <= 3) {
10882                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10883                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10884                 }
10885                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10886                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10887                 if (INTEL_INFO(dev)->gen >= 4) {
10888                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10889                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10890                 }
10891
10892                 err_printf(m, "Cursor [%d]:\n", i);
10893                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10894                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10895                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10896         }
10897
10898         for (i = 0; i < error->num_transcoders; i++) {
10899                 err_printf(m, "  CPU transcoder: %c\n",
10900                            transcoder_name(error->transcoder[i].cpu_transcoder));
10901                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10902                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10903                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10904                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10905                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10906                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10907                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10908         }
10909 }