Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * intel_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674                                     enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694                 return;
1695         }
1696         reg = TRANSCONF(pipe);
1697         val = I915_READ(reg);
1698         pipeconf_val = I915_READ(PIPECONF(pipe));
1699
1700         if (HAS_PCH_IBX(dev_priv->dev)) {
1701                 /*
1702                  * make the BPC in transcoder be consistent with
1703                  * that in pipeconf reg.
1704                  */
1705                 val &= ~PIPE_BPC_MASK;
1706                 val |= pipeconf_val & PIPE_BPC_MASK;
1707         }
1708
1709         val &= ~TRANS_INTERLACE_MASK;
1710         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711                 if (HAS_PCH_IBX(dev_priv->dev) &&
1712                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713                         val |= TRANS_LEGACY_INTERLACED_ILK;
1714                 else
1715                         val |= TRANS_INTERLACED;
1716         else
1717                 val |= TRANS_PROGRESSIVE;
1718
1719         I915_WRITE(reg, val | TRANS_ENABLE);
1720         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 }
1723
1724 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725                                      enum pipe pipe)
1726 {
1727         int reg;
1728         u32 val;
1729
1730         /* FDI relies on the transcoder */
1731         assert_fdi_tx_disabled(dev_priv, pipe);
1732         assert_fdi_rx_disabled(dev_priv, pipe);
1733
1734         /* Ports must be off as well */
1735         assert_pch_ports_disabled(dev_priv, pipe);
1736
1737         reg = TRANSCONF(pipe);
1738         val = I915_READ(reg);
1739         val &= ~TRANS_ENABLE;
1740         I915_WRITE(reg, val);
1741         /* wait for PCH transcoder off, transcoder state */
1742         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1743                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1744 }
1745
1746 /**
1747  * intel_enable_pipe - enable a pipe, asserting requirements
1748  * @dev_priv: i915 private structure
1749  * @pipe: pipe to enable
1750  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751  *
1752  * Enable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe is actually running (i.e. first vblank) before
1758  * returning.
1759  */
1760 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761                               bool pch_port)
1762 {
1763         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764                                                                       pipe);
1765         int reg;
1766         u32 val;
1767
1768         /*
1769          * A pipe without a PLL won't actually be able to drive bits from
1770          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1771          * need the check.
1772          */
1773         if (!HAS_PCH_SPLIT(dev_priv->dev))
1774                 assert_pll_enabled(dev_priv, pipe);
1775         else {
1776                 if (pch_port) {
1777                         /* if driving the PCH, we need FDI enabled */
1778                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780                 }
1781                 /* FIXME: assert CPU port conditions for SNB+ */
1782         }
1783
1784         reg = PIPECONF(cpu_transcoder);
1785         val = I915_READ(reg);
1786         if (val & PIPECONF_ENABLE)
1787                 return;
1788
1789         I915_WRITE(reg, val | PIPECONF_ENABLE);
1790         intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794  * intel_disable_pipe - disable a pipe, asserting requirements
1795  * @dev_priv: i915 private structure
1796  * @pipe: pipe to disable
1797  *
1798  * Disable @pipe, making sure that various hardware specific requirements
1799  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800  *
1801  * @pipe should be %PIPE_A or %PIPE_B.
1802  *
1803  * Will wait until the pipe has shut down before returning.
1804  */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806                                enum pipe pipe)
1807 {
1808         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809                                                                       pipe);
1810         int reg;
1811         u32 val;
1812
1813         /*
1814          * Make sure planes won't keep trying to pump pixels to us,
1815          * or we might hang the display.
1816          */
1817         assert_planes_disabled(dev_priv, pipe);
1818
1819         /* Don't disable pipe A or pipe A PLLs if needed */
1820         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821                 return;
1822
1823         reg = PIPECONF(cpu_transcoder);
1824         val = I915_READ(reg);
1825         if ((val & PIPECONF_ENABLE) == 0)
1826                 return;
1827
1828         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1829         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830 }
1831
1832 /*
1833  * Plane regs are double buffered, going from enabled->disabled needs a
1834  * trigger in order to latch.  The display address reg provides this.
1835  */
1836 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1837                                       enum plane plane)
1838 {
1839         if (dev_priv->info->gen >= 4)
1840                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841         else
1842                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1843 }
1844
1845 /**
1846  * intel_enable_plane - enable a display plane on a given pipe
1847  * @dev_priv: i915 private structure
1848  * @plane: plane to enable
1849  * @pipe: pipe being fed
1850  *
1851  * Enable @plane on @pipe, making sure that @pipe is running first.
1852  */
1853 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854                                enum plane plane, enum pipe pipe)
1855 {
1856         int reg;
1857         u32 val;
1858
1859         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860         assert_pipe_enabled(dev_priv, pipe);
1861
1862         reg = DSPCNTR(plane);
1863         val = I915_READ(reg);
1864         if (val & DISPLAY_PLANE_ENABLE)
1865                 return;
1866
1867         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1868         intel_flush_display_plane(dev_priv, plane);
1869         intel_wait_for_vblank(dev_priv->dev, pipe);
1870 }
1871
1872 /**
1873  * intel_disable_plane - disable a display plane
1874  * @dev_priv: i915 private structure
1875  * @plane: plane to disable
1876  * @pipe: pipe consuming the data
1877  *
1878  * Disable @plane; should be an independent operation.
1879  */
1880 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881                                 enum plane plane, enum pipe pipe)
1882 {
1883         int reg;
1884         u32 val;
1885
1886         reg = DSPCNTR(plane);
1887         val = I915_READ(reg);
1888         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889                 return;
1890
1891         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1892         intel_flush_display_plane(dev_priv, plane);
1893         intel_wait_for_vblank(dev_priv->dev, pipe);
1894 }
1895
1896 int
1897 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1898                            struct drm_i915_gem_object *obj,
1899                            struct intel_ring_buffer *pipelined)
1900 {
1901         struct drm_i915_private *dev_priv = dev->dev_private;
1902         u32 alignment;
1903         int ret;
1904
1905         switch (obj->tiling_mode) {
1906         case I915_TILING_NONE:
1907                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908                         alignment = 128 * 1024;
1909                 else if (INTEL_INFO(dev)->gen >= 4)
1910                         alignment = 4 * 1024;
1911                 else
1912                         alignment = 64 * 1024;
1913                 break;
1914         case I915_TILING_X:
1915                 /* pin() will align the object as required by fence */
1916                 alignment = 0;
1917                 break;
1918         case I915_TILING_Y:
1919                 /* FIXME: Is this true? */
1920                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921                 return -EINVAL;
1922         default:
1923                 BUG();
1924         }
1925
1926         dev_priv->mm.interruptible = false;
1927         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1928         if (ret)
1929                 goto err_interruptible;
1930
1931         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932          * fence, whereas 965+ only requires a fence if using
1933          * framebuffer compression.  For simplicity, we always install
1934          * a fence as the cost is not that onerous.
1935          */
1936         ret = i915_gem_object_get_fence(obj);
1937         if (ret)
1938                 goto err_unpin;
1939
1940         i915_gem_object_pin_fence(obj);
1941
1942         dev_priv->mm.interruptible = true;
1943         return 0;
1944
1945 err_unpin:
1946         i915_gem_object_unpin(obj);
1947 err_interruptible:
1948         dev_priv->mm.interruptible = true;
1949         return ret;
1950 }
1951
1952 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953 {
1954         i915_gem_object_unpin_fence(obj);
1955         i915_gem_object_unpin(obj);
1956 }
1957
1958 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959  * is assumed to be a power-of-two. */
1960 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961                                                unsigned int bpp,
1962                                                unsigned int pitch)
1963 {
1964         int tile_rows, tiles;
1965
1966         tile_rows = *y / 8;
1967         *y %= 8;
1968         tiles = *x / (512/bpp);
1969         *x %= 512/bpp;
1970
1971         return tile_rows * pitch * 8 + tiles * 4096;
1972 }
1973
1974 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975                              int x, int y)
1976 {
1977         struct drm_device *dev = crtc->dev;
1978         struct drm_i915_private *dev_priv = dev->dev_private;
1979         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980         struct intel_framebuffer *intel_fb;
1981         struct drm_i915_gem_object *obj;
1982         int plane = intel_crtc->plane;
1983         unsigned long linear_offset;
1984         u32 dspcntr;
1985         u32 reg;
1986
1987         switch (plane) {
1988         case 0:
1989         case 1:
1990                 break;
1991         default:
1992                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993                 return -EINVAL;
1994         }
1995
1996         intel_fb = to_intel_framebuffer(fb);
1997         obj = intel_fb->obj;
1998
1999         reg = DSPCNTR(plane);
2000         dspcntr = I915_READ(reg);
2001         /* Mask out pixel format bits in case we change it */
2002         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2003         switch (fb->pixel_format) {
2004         case DRM_FORMAT_C8:
2005                 dspcntr |= DISPPLANE_8BPP;
2006                 break;
2007         case DRM_FORMAT_XRGB1555:
2008         case DRM_FORMAT_ARGB1555:
2009                 dspcntr |= DISPPLANE_BGRX555;
2010                 break;
2011         case DRM_FORMAT_RGB565:
2012                 dspcntr |= DISPPLANE_BGRX565;
2013                 break;
2014         case DRM_FORMAT_XRGB8888:
2015         case DRM_FORMAT_ARGB8888:
2016                 dspcntr |= DISPPLANE_BGRX888;
2017                 break;
2018         case DRM_FORMAT_XBGR8888:
2019         case DRM_FORMAT_ABGR8888:
2020                 dspcntr |= DISPPLANE_RGBX888;
2021                 break;
2022         case DRM_FORMAT_XRGB2101010:
2023         case DRM_FORMAT_ARGB2101010:
2024                 dspcntr |= DISPPLANE_BGRX101010;
2025                 break;
2026         case DRM_FORMAT_XBGR2101010:
2027         case DRM_FORMAT_ABGR2101010:
2028                 dspcntr |= DISPPLANE_RGBX101010;
2029                 break;
2030         default:
2031                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2032                 return -EINVAL;
2033         }
2034
2035         if (INTEL_INFO(dev)->gen >= 4) {
2036                 if (obj->tiling_mode != I915_TILING_NONE)
2037                         dspcntr |= DISPPLANE_TILED;
2038                 else
2039                         dspcntr &= ~DISPPLANE_TILED;
2040         }
2041
2042         I915_WRITE(reg, dspcntr);
2043
2044         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2045
2046         if (INTEL_INFO(dev)->gen >= 4) {
2047                 intel_crtc->dspaddr_offset =
2048                         intel_gen4_compute_offset_xtiled(&x, &y,
2049                                                          fb->bits_per_pixel / 8,
2050                                                          fb->pitches[0]);
2051                 linear_offset -= intel_crtc->dspaddr_offset;
2052         } else {
2053                 intel_crtc->dspaddr_offset = linear_offset;
2054         }
2055
2056         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2057                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2058         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2059         if (INTEL_INFO(dev)->gen >= 4) {
2060                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2061                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2062                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2063                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2064         } else
2065                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2066         POSTING_READ(reg);
2067
2068         return 0;
2069 }
2070
2071 static int ironlake_update_plane(struct drm_crtc *crtc,
2072                                  struct drm_framebuffer *fb, int x, int y)
2073 {
2074         struct drm_device *dev = crtc->dev;
2075         struct drm_i915_private *dev_priv = dev->dev_private;
2076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077         struct intel_framebuffer *intel_fb;
2078         struct drm_i915_gem_object *obj;
2079         int plane = intel_crtc->plane;
2080         unsigned long linear_offset;
2081         u32 dspcntr;
2082         u32 reg;
2083
2084         switch (plane) {
2085         case 0:
2086         case 1:
2087         case 2:
2088                 break;
2089         default:
2090                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091                 return -EINVAL;
2092         }
2093
2094         intel_fb = to_intel_framebuffer(fb);
2095         obj = intel_fb->obj;
2096
2097         reg = DSPCNTR(plane);
2098         dspcntr = I915_READ(reg);
2099         /* Mask out pixel format bits in case we change it */
2100         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2101         switch (fb->pixel_format) {
2102         case DRM_FORMAT_C8:
2103                 dspcntr |= DISPPLANE_8BPP;
2104                 break;
2105         case DRM_FORMAT_RGB565:
2106                 dspcntr |= DISPPLANE_BGRX565;
2107                 break;
2108         case DRM_FORMAT_XRGB8888:
2109         case DRM_FORMAT_ARGB8888:
2110                 dspcntr |= DISPPLANE_BGRX888;
2111                 break;
2112         case DRM_FORMAT_XBGR8888:
2113         case DRM_FORMAT_ABGR8888:
2114                 dspcntr |= DISPPLANE_RGBX888;
2115                 break;
2116         case DRM_FORMAT_XRGB2101010:
2117         case DRM_FORMAT_ARGB2101010:
2118                 dspcntr |= DISPPLANE_BGRX101010;
2119                 break;
2120         case DRM_FORMAT_XBGR2101010:
2121         case DRM_FORMAT_ABGR2101010:
2122                 dspcntr |= DISPPLANE_RGBX101010;
2123                 break;
2124         default:
2125                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2126                 return -EINVAL;
2127         }
2128
2129         if (obj->tiling_mode != I915_TILING_NONE)
2130                 dspcntr |= DISPPLANE_TILED;
2131         else
2132                 dspcntr &= ~DISPPLANE_TILED;
2133
2134         /* must disable */
2135         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137         I915_WRITE(reg, dspcntr);
2138
2139         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2140         intel_crtc->dspaddr_offset =
2141                 intel_gen4_compute_offset_xtiled(&x, &y,
2142                                                  fb->bits_per_pixel / 8,
2143                                                  fb->pitches[0]);
2144         linear_offset -= intel_crtc->dspaddr_offset;
2145
2146         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2148         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2149         I915_MODIFY_DISPBASE(DSPSURF(plane),
2150                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2151         if (IS_HASWELL(dev)) {
2152                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2153         } else {
2154                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2155                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2156         }
2157         POSTING_READ(reg);
2158
2159         return 0;
2160 }
2161
2162 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2163 static int
2164 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2165                            int x, int y, enum mode_set_atomic state)
2166 {
2167         struct drm_device *dev = crtc->dev;
2168         struct drm_i915_private *dev_priv = dev->dev_private;
2169
2170         if (dev_priv->display.disable_fbc)
2171                 dev_priv->display.disable_fbc(dev);
2172         intel_increase_pllclock(crtc);
2173
2174         return dev_priv->display.update_plane(crtc, fb, x, y);
2175 }
2176
2177 static int
2178 intel_finish_fb(struct drm_framebuffer *old_fb)
2179 {
2180         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2181         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182         bool was_interruptible = dev_priv->mm.interruptible;
2183         int ret;
2184
2185         wait_event(dev_priv->pending_flip_queue,
2186                    atomic_read(&dev_priv->mm.wedged) ||
2187                    atomic_read(&obj->pending_flip) == 0);
2188
2189         /* Big Hammer, we also need to ensure that any pending
2190          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2191          * current scanout is retired before unpinning the old
2192          * framebuffer.
2193          *
2194          * This should only fail upon a hung GPU, in which case we
2195          * can safely continue.
2196          */
2197         dev_priv->mm.interruptible = false;
2198         ret = i915_gem_object_finish_gpu(obj);
2199         dev_priv->mm.interruptible = was_interruptible;
2200
2201         return ret;
2202 }
2203
2204 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2205 {
2206         struct drm_device *dev = crtc->dev;
2207         struct drm_i915_master_private *master_priv;
2208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210         if (!dev->primary->master)
2211                 return;
2212
2213         master_priv = dev->primary->master->driver_priv;
2214         if (!master_priv->sarea_priv)
2215                 return;
2216
2217         switch (intel_crtc->pipe) {
2218         case 0:
2219                 master_priv->sarea_priv->pipeA_x = x;
2220                 master_priv->sarea_priv->pipeA_y = y;
2221                 break;
2222         case 1:
2223                 master_priv->sarea_priv->pipeB_x = x;
2224                 master_priv->sarea_priv->pipeB_y = y;
2225                 break;
2226         default:
2227                 break;
2228         }
2229 }
2230
2231 static int
2232 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2233                     struct drm_framebuffer *fb)
2234 {
2235         struct drm_device *dev = crtc->dev;
2236         struct drm_i915_private *dev_priv = dev->dev_private;
2237         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2238         struct drm_framebuffer *old_fb;
2239         int ret;
2240
2241         /* no fb bound */
2242         if (!fb) {
2243                 DRM_ERROR("No FB bound\n");
2244                 return 0;
2245         }
2246
2247         if(intel_crtc->plane > dev_priv->num_pipe) {
2248                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2249                                 intel_crtc->plane,
2250                                 dev_priv->num_pipe);
2251                 return -EINVAL;
2252         }
2253
2254         mutex_lock(&dev->struct_mutex);
2255         ret = intel_pin_and_fence_fb_obj(dev,
2256                                          to_intel_framebuffer(fb)->obj,
2257                                          NULL);
2258         if (ret != 0) {
2259                 mutex_unlock(&dev->struct_mutex);
2260                 DRM_ERROR("pin & fence failed\n");
2261                 return ret;
2262         }
2263
2264         if (crtc->fb)
2265                 intel_finish_fb(crtc->fb);
2266
2267         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2268         if (ret) {
2269                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2270                 mutex_unlock(&dev->struct_mutex);
2271                 DRM_ERROR("failed to update base address\n");
2272                 return ret;
2273         }
2274
2275         old_fb = crtc->fb;
2276         crtc->fb = fb;
2277         crtc->x = x;
2278         crtc->y = y;
2279
2280         if (old_fb) {
2281                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2282                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2283         }
2284
2285         intel_update_fbc(dev);
2286         mutex_unlock(&dev->struct_mutex);
2287
2288         intel_crtc_update_sarea_pos(crtc, x, y);
2289
2290         return 0;
2291 }
2292
2293 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         u32 dpa_ctl;
2298
2299         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2300         dpa_ctl = I915_READ(DP_A);
2301         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2302
2303         if (clock < 200000) {
2304                 u32 temp;
2305                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2306                 /* workaround for 160Mhz:
2307                    1) program 0x4600c bits 15:0 = 0x8124
2308                    2) program 0x46010 bit 0 = 1
2309                    3) program 0x46034 bit 24 = 1
2310                    4) program 0x64000 bit 14 = 1
2311                    */
2312                 temp = I915_READ(0x4600c);
2313                 temp &= 0xffff0000;
2314                 I915_WRITE(0x4600c, temp | 0x8124);
2315
2316                 temp = I915_READ(0x46010);
2317                 I915_WRITE(0x46010, temp | 1);
2318
2319                 temp = I915_READ(0x46034);
2320                 I915_WRITE(0x46034, temp | (1 << 24));
2321         } else {
2322                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2323         }
2324         I915_WRITE(DP_A, dpa_ctl);
2325
2326         POSTING_READ(DP_A);
2327         udelay(500);
2328 }
2329
2330 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331 {
2332         struct drm_device *dev = crtc->dev;
2333         struct drm_i915_private *dev_priv = dev->dev_private;
2334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335         int pipe = intel_crtc->pipe;
2336         u32 reg, temp;
2337
2338         /* enable normal train */
2339         reg = FDI_TX_CTL(pipe);
2340         temp = I915_READ(reg);
2341         if (IS_IVYBRIDGE(dev)) {
2342                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2344         } else {
2345                 temp &= ~FDI_LINK_TRAIN_NONE;
2346                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2347         }
2348         I915_WRITE(reg, temp);
2349
2350         reg = FDI_RX_CTL(pipe);
2351         temp = I915_READ(reg);
2352         if (HAS_PCH_CPT(dev)) {
2353                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355         } else {
2356                 temp &= ~FDI_LINK_TRAIN_NONE;
2357                 temp |= FDI_LINK_TRAIN_NONE;
2358         }
2359         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361         /* wait one idle pattern time */
2362         POSTING_READ(reg);
2363         udelay(1000);
2364
2365         /* IVB wants error correction enabled */
2366         if (IS_IVYBRIDGE(dev))
2367                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368                            FDI_FE_ERRC_ENABLE);
2369 }
2370
2371 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2372 {
2373         struct drm_i915_private *dev_priv = dev->dev_private;
2374         u32 flags = I915_READ(SOUTH_CHICKEN1);
2375
2376         flags |= FDI_PHASE_SYNC_OVR(pipe);
2377         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2378         flags |= FDI_PHASE_SYNC_EN(pipe);
2379         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2380         POSTING_READ(SOUTH_CHICKEN1);
2381 }
2382
2383 static void ivb_modeset_global_resources(struct drm_device *dev)
2384 {
2385         struct drm_i915_private *dev_priv = dev->dev_private;
2386         struct intel_crtc *pipe_B_crtc =
2387                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2388         struct intel_crtc *pipe_C_crtc =
2389                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2390         uint32_t temp;
2391
2392         /* When everything is off disable fdi C so that we could enable fdi B
2393          * with all lanes. XXX: This misses the case where a pipe is not using
2394          * any pch resources and so doesn't need any fdi lanes. */
2395         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2396                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2397                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2398
2399                 temp = I915_READ(SOUTH_CHICKEN1);
2400                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2401                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2402                 I915_WRITE(SOUTH_CHICKEN1, temp);
2403         }
2404 }
2405
2406 /* The FDI link training functions for ILK/Ibexpeak. */
2407 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2408 {
2409         struct drm_device *dev = crtc->dev;
2410         struct drm_i915_private *dev_priv = dev->dev_private;
2411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412         int pipe = intel_crtc->pipe;
2413         int plane = intel_crtc->plane;
2414         u32 reg, temp, tries;
2415
2416         /* FDI needs bits from pipe & plane first */
2417         assert_pipe_enabled(dev_priv, pipe);
2418         assert_plane_enabled(dev_priv, plane);
2419
2420         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2421            for train result */
2422         reg = FDI_RX_IMR(pipe);
2423         temp = I915_READ(reg);
2424         temp &= ~FDI_RX_SYMBOL_LOCK;
2425         temp &= ~FDI_RX_BIT_LOCK;
2426         I915_WRITE(reg, temp);
2427         I915_READ(reg);
2428         udelay(150);
2429
2430         /* enable CPU FDI TX and PCH FDI RX */
2431         reg = FDI_TX_CTL(pipe);
2432         temp = I915_READ(reg);
2433         temp &= ~(7 << 19);
2434         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2435         temp &= ~FDI_LINK_TRAIN_NONE;
2436         temp |= FDI_LINK_TRAIN_PATTERN_1;
2437         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2438
2439         reg = FDI_RX_CTL(pipe);
2440         temp = I915_READ(reg);
2441         temp &= ~FDI_LINK_TRAIN_NONE;
2442         temp |= FDI_LINK_TRAIN_PATTERN_1;
2443         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2444
2445         POSTING_READ(reg);
2446         udelay(150);
2447
2448         /* Ironlake workaround, enable clock pointer after FDI enable*/
2449         if (HAS_PCH_IBX(dev)) {
2450                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2451                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2452                            FDI_RX_PHASE_SYNC_POINTER_EN);
2453         }
2454
2455         reg = FDI_RX_IIR(pipe);
2456         for (tries = 0; tries < 5; tries++) {
2457                 temp = I915_READ(reg);
2458                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460                 if ((temp & FDI_RX_BIT_LOCK)) {
2461                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2462                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2463                         break;
2464                 }
2465         }
2466         if (tries == 5)
2467                 DRM_ERROR("FDI train 1 fail!\n");
2468
2469         /* Train 2 */
2470         reg = FDI_TX_CTL(pipe);
2471         temp = I915_READ(reg);
2472         temp &= ~FDI_LINK_TRAIN_NONE;
2473         temp |= FDI_LINK_TRAIN_PATTERN_2;
2474         I915_WRITE(reg, temp);
2475
2476         reg = FDI_RX_CTL(pipe);
2477         temp = I915_READ(reg);
2478         temp &= ~FDI_LINK_TRAIN_NONE;
2479         temp |= FDI_LINK_TRAIN_PATTERN_2;
2480         I915_WRITE(reg, temp);
2481
2482         POSTING_READ(reg);
2483         udelay(150);
2484
2485         reg = FDI_RX_IIR(pipe);
2486         for (tries = 0; tries < 5; tries++) {
2487                 temp = I915_READ(reg);
2488                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490                 if (temp & FDI_RX_SYMBOL_LOCK) {
2491                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2492                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2493                         break;
2494                 }
2495         }
2496         if (tries == 5)
2497                 DRM_ERROR("FDI train 2 fail!\n");
2498
2499         DRM_DEBUG_KMS("FDI train done\n");
2500
2501 }
2502
2503 static const int snb_b_fdi_train_param[] = {
2504         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508 };
2509
2510 /* The FDI link training functions for SNB/Cougarpoint. */
2511 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512 {
2513         struct drm_device *dev = crtc->dev;
2514         struct drm_i915_private *dev_priv = dev->dev_private;
2515         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516         int pipe = intel_crtc->pipe;
2517         u32 reg, temp, i, retry;
2518
2519         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520            for train result */
2521         reg = FDI_RX_IMR(pipe);
2522         temp = I915_READ(reg);
2523         temp &= ~FDI_RX_SYMBOL_LOCK;
2524         temp &= ~FDI_RX_BIT_LOCK;
2525         I915_WRITE(reg, temp);
2526
2527         POSTING_READ(reg);
2528         udelay(150);
2529
2530         /* enable CPU FDI TX and PCH FDI RX */
2531         reg = FDI_TX_CTL(pipe);
2532         temp = I915_READ(reg);
2533         temp &= ~(7 << 19);
2534         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2535         temp &= ~FDI_LINK_TRAIN_NONE;
2536         temp |= FDI_LINK_TRAIN_PATTERN_1;
2537         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538         /* SNB-B */
2539         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2540         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2541
2542         I915_WRITE(FDI_RX_MISC(pipe),
2543                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
2545         reg = FDI_RX_CTL(pipe);
2546         temp = I915_READ(reg);
2547         if (HAS_PCH_CPT(dev)) {
2548                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550         } else {
2551                 temp &= ~FDI_LINK_TRAIN_NONE;
2552                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553         }
2554         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556         POSTING_READ(reg);
2557         udelay(150);
2558
2559         if (HAS_PCH_CPT(dev))
2560                 cpt_phase_pointer_enable(dev, pipe);
2561
2562         for (i = 0; i < 4; i++) {
2563                 reg = FDI_TX_CTL(pipe);
2564                 temp = I915_READ(reg);
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 temp |= snb_b_fdi_train_param[i];
2567                 I915_WRITE(reg, temp);
2568
2569                 POSTING_READ(reg);
2570                 udelay(500);
2571
2572                 for (retry = 0; retry < 5; retry++) {
2573                         reg = FDI_RX_IIR(pipe);
2574                         temp = I915_READ(reg);
2575                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576                         if (temp & FDI_RX_BIT_LOCK) {
2577                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579                                 break;
2580                         }
2581                         udelay(50);
2582                 }
2583                 if (retry < 5)
2584                         break;
2585         }
2586         if (i == 4)
2587                 DRM_ERROR("FDI train 1 fail!\n");
2588
2589         /* Train 2 */
2590         reg = FDI_TX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         temp &= ~FDI_LINK_TRAIN_NONE;
2593         temp |= FDI_LINK_TRAIN_PATTERN_2;
2594         if (IS_GEN6(dev)) {
2595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596                 /* SNB-B */
2597                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598         }
2599         I915_WRITE(reg, temp);
2600
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         if (HAS_PCH_CPT(dev)) {
2604                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606         } else {
2607                 temp &= ~FDI_LINK_TRAIN_NONE;
2608                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609         }
2610         I915_WRITE(reg, temp);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         for (i = 0; i < 4; i++) {
2616                 reg = FDI_TX_CTL(pipe);
2617                 temp = I915_READ(reg);
2618                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619                 temp |= snb_b_fdi_train_param[i];
2620                 I915_WRITE(reg, temp);
2621
2622                 POSTING_READ(reg);
2623                 udelay(500);
2624
2625                 for (retry = 0; retry < 5; retry++) {
2626                         reg = FDI_RX_IIR(pipe);
2627                         temp = I915_READ(reg);
2628                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629                         if (temp & FDI_RX_SYMBOL_LOCK) {
2630                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632                                 break;
2633                         }
2634                         udelay(50);
2635                 }
2636                 if (retry < 5)
2637                         break;
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 2 fail!\n");
2641
2642         DRM_DEBUG_KMS("FDI train done.\n");
2643 }
2644
2645 /* Manual link training for Ivy Bridge A0 parts */
2646 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647 {
2648         struct drm_device *dev = crtc->dev;
2649         struct drm_i915_private *dev_priv = dev->dev_private;
2650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651         int pipe = intel_crtc->pipe;
2652         u32 reg, temp, i;
2653
2654         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655            for train result */
2656         reg = FDI_RX_IMR(pipe);
2657         temp = I915_READ(reg);
2658         temp &= ~FDI_RX_SYMBOL_LOCK;
2659         temp &= ~FDI_RX_BIT_LOCK;
2660         I915_WRITE(reg, temp);
2661
2662         POSTING_READ(reg);
2663         udelay(150);
2664
2665         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666                       I915_READ(FDI_RX_IIR(pipe)));
2667
2668         /* enable CPU FDI TX and PCH FDI RX */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~(7 << 19);
2672         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2677         temp |= FDI_COMPOSITE_SYNC;
2678         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
2680         I915_WRITE(FDI_RX_MISC(pipe),
2681                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
2683         reg = FDI_RX_CTL(pipe);
2684         temp = I915_READ(reg);
2685         temp &= ~FDI_LINK_TRAIN_AUTO;
2686         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2688         temp |= FDI_COMPOSITE_SYNC;
2689         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691         POSTING_READ(reg);
2692         udelay(150);
2693
2694         if (HAS_PCH_CPT(dev))
2695                 cpt_phase_pointer_enable(dev, pipe);
2696
2697         for (i = 0; i < 4; i++) {
2698                 reg = FDI_TX_CTL(pipe);
2699                 temp = I915_READ(reg);
2700                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701                 temp |= snb_b_fdi_train_param[i];
2702                 I915_WRITE(reg, temp);
2703
2704                 POSTING_READ(reg);
2705                 udelay(500);
2706
2707                 reg = FDI_RX_IIR(pipe);
2708                 temp = I915_READ(reg);
2709                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711                 if (temp & FDI_RX_BIT_LOCK ||
2712                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2713                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2714                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2715                         break;
2716                 }
2717         }
2718         if (i == 4)
2719                 DRM_ERROR("FDI train 1 fail!\n");
2720
2721         /* Train 2 */
2722         reg = FDI_TX_CTL(pipe);
2723         temp = I915_READ(reg);
2724         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2725         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2726         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2728         I915_WRITE(reg, temp);
2729
2730         reg = FDI_RX_CTL(pipe);
2731         temp = I915_READ(reg);
2732         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2733         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2734         I915_WRITE(reg, temp);
2735
2736         POSTING_READ(reg);
2737         udelay(150);
2738
2739         for (i = 0; i < 4; i++) {
2740                 reg = FDI_TX_CTL(pipe);
2741                 temp = I915_READ(reg);
2742                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743                 temp |= snb_b_fdi_train_param[i];
2744                 I915_WRITE(reg, temp);
2745
2746                 POSTING_READ(reg);
2747                 udelay(500);
2748
2749                 reg = FDI_RX_IIR(pipe);
2750                 temp = I915_READ(reg);
2751                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753                 if (temp & FDI_RX_SYMBOL_LOCK) {
2754                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2755                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2756                         break;
2757                 }
2758         }
2759         if (i == 4)
2760                 DRM_ERROR("FDI train 2 fail!\n");
2761
2762         DRM_DEBUG_KMS("FDI train done.\n");
2763 }
2764
2765 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2766 {
2767         struct drm_device *dev = intel_crtc->base.dev;
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         int pipe = intel_crtc->pipe;
2770         u32 reg, temp;
2771
2772
2773         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2774         reg = FDI_RX_CTL(pipe);
2775         temp = I915_READ(reg);
2776         temp &= ~((0x7 << 19) | (0x7 << 16));
2777         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2778         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2780
2781         POSTING_READ(reg);
2782         udelay(200);
2783
2784         /* Switch from Rawclk to PCDclk */
2785         temp = I915_READ(reg);
2786         I915_WRITE(reg, temp | FDI_PCDCLK);
2787
2788         POSTING_READ(reg);
2789         udelay(200);
2790
2791         /* On Haswell, the PLL configuration for ports and pipes is handled
2792          * separately, as part of DDI setup */
2793         if (!IS_HASWELL(dev)) {
2794                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2795                 reg = FDI_TX_CTL(pipe);
2796                 temp = I915_READ(reg);
2797                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2798                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2799
2800                         POSTING_READ(reg);
2801                         udelay(100);
2802                 }
2803         }
2804 }
2805
2806 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2807 {
2808         struct drm_device *dev = intel_crtc->base.dev;
2809         struct drm_i915_private *dev_priv = dev->dev_private;
2810         int pipe = intel_crtc->pipe;
2811         u32 reg, temp;
2812
2813         /* Switch from PCDclk to Rawclk */
2814         reg = FDI_RX_CTL(pipe);
2815         temp = I915_READ(reg);
2816         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2817
2818         /* Disable CPU FDI TX PLL */
2819         reg = FDI_TX_CTL(pipe);
2820         temp = I915_READ(reg);
2821         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823         POSTING_READ(reg);
2824         udelay(100);
2825
2826         reg = FDI_RX_CTL(pipe);
2827         temp = I915_READ(reg);
2828         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2829
2830         /* Wait for the clocks to turn off. */
2831         POSTING_READ(reg);
2832         udelay(100);
2833 }
2834
2835 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2836 {
2837         struct drm_i915_private *dev_priv = dev->dev_private;
2838         u32 flags = I915_READ(SOUTH_CHICKEN1);
2839
2840         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2841         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2842         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2843         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2844         POSTING_READ(SOUTH_CHICKEN1);
2845 }
2846 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2847 {
2848         struct drm_device *dev = crtc->dev;
2849         struct drm_i915_private *dev_priv = dev->dev_private;
2850         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851         int pipe = intel_crtc->pipe;
2852         u32 reg, temp;
2853
2854         /* disable CPU FDI tx and PCH FDI rx */
2855         reg = FDI_TX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2858         POSTING_READ(reg);
2859
2860         reg = FDI_RX_CTL(pipe);
2861         temp = I915_READ(reg);
2862         temp &= ~(0x7 << 16);
2863         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2864         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2865
2866         POSTING_READ(reg);
2867         udelay(100);
2868
2869         /* Ironlake workaround, disable clock pointer after downing FDI */
2870         if (HAS_PCH_IBX(dev)) {
2871                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2872                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2873                            I915_READ(FDI_RX_CHICKEN(pipe) &
2874                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2875         } else if (HAS_PCH_CPT(dev)) {
2876                 cpt_phase_pointer_disable(dev, pipe);
2877         }
2878
2879         /* still set train pattern 1 */
2880         reg = FDI_TX_CTL(pipe);
2881         temp = I915_READ(reg);
2882         temp &= ~FDI_LINK_TRAIN_NONE;
2883         temp |= FDI_LINK_TRAIN_PATTERN_1;
2884         I915_WRITE(reg, temp);
2885
2886         reg = FDI_RX_CTL(pipe);
2887         temp = I915_READ(reg);
2888         if (HAS_PCH_CPT(dev)) {
2889                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2890                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2891         } else {
2892                 temp &= ~FDI_LINK_TRAIN_NONE;
2893                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2894         }
2895         /* BPC in FDI rx is consistent with that in PIPECONF */
2896         temp &= ~(0x07 << 16);
2897         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2898         I915_WRITE(reg, temp);
2899
2900         POSTING_READ(reg);
2901         udelay(100);
2902 }
2903
2904 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2905 {
2906         struct drm_device *dev = crtc->dev;
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908         unsigned long flags;
2909         bool pending;
2910
2911         if (atomic_read(&dev_priv->mm.wedged))
2912                 return false;
2913
2914         spin_lock_irqsave(&dev->event_lock, flags);
2915         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916         spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918         return pending;
2919 }
2920
2921 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922 {
2923         struct drm_device *dev = crtc->dev;
2924         struct drm_i915_private *dev_priv = dev->dev_private;
2925
2926         if (crtc->fb == NULL)
2927                 return;
2928
2929         wait_event(dev_priv->pending_flip_queue,
2930                    !intel_crtc_has_pending_flip(crtc));
2931
2932         mutex_lock(&dev->struct_mutex);
2933         intel_finish_fb(crtc->fb);
2934         mutex_unlock(&dev->struct_mutex);
2935 }
2936
2937 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2938 {
2939         struct drm_device *dev = crtc->dev;
2940         struct intel_encoder *intel_encoder;
2941
2942         /*
2943          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2944          * must be driven by its own crtc; no sharing is possible.
2945          */
2946         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2947                 switch (intel_encoder->type) {
2948                 case INTEL_OUTPUT_EDP:
2949                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2950                                 return false;
2951                         continue;
2952                 }
2953         }
2954
2955         return true;
2956 }
2957
2958 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2959 {
2960         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2961 }
2962
2963 /* Program iCLKIP clock to the desired frequency */
2964 static void lpt_program_iclkip(struct drm_crtc *crtc)
2965 {
2966         struct drm_device *dev = crtc->dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969         u32 temp;
2970
2971         /* It is necessary to ungate the pixclk gate prior to programming
2972          * the divisors, and gate it back when it is done.
2973          */
2974         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2975
2976         /* Disable SSCCTL */
2977         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2978                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2979                                         SBI_SSCCTL_DISABLE);
2980
2981         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2982         if (crtc->mode.clock == 20000) {
2983                 auxdiv = 1;
2984                 divsel = 0x41;
2985                 phaseinc = 0x20;
2986         } else {
2987                 /* The iCLK virtual clock root frequency is in MHz,
2988                  * but the crtc->mode.clock in in KHz. To get the divisors,
2989                  * it is necessary to divide one by another, so we
2990                  * convert the virtual clock precision to KHz here for higher
2991                  * precision.
2992                  */
2993                 u32 iclk_virtual_root_freq = 172800 * 1000;
2994                 u32 iclk_pi_range = 64;
2995                 u32 desired_divisor, msb_divisor_value, pi_value;
2996
2997                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2998                 msb_divisor_value = desired_divisor / iclk_pi_range;
2999                 pi_value = desired_divisor % iclk_pi_range;
3000
3001                 auxdiv = 0;
3002                 divsel = msb_divisor_value - 2;
3003                 phaseinc = pi_value;
3004         }
3005
3006         /* This should not happen with any sane values */
3007         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3008                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3009         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3010                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3011
3012         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3013                         crtc->mode.clock,
3014                         auxdiv,
3015                         divsel,
3016                         phasedir,
3017                         phaseinc);
3018
3019         /* Program SSCDIVINTPHASE6 */
3020         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3021         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3022         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3023         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3024         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3025         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3026         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3027
3028         intel_sbi_write(dev_priv,
3029                         SBI_SSCDIVINTPHASE6,
3030                         temp);
3031
3032         /* Program SSCAUXDIV */
3033         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3034         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036         intel_sbi_write(dev_priv,
3037                         SBI_SSCAUXDIV6,
3038                         temp);
3039
3040
3041         /* Enable modulator and associated divider */
3042         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3043         temp &= ~SBI_SSCCTL_DISABLE;
3044         intel_sbi_write(dev_priv,
3045                         SBI_SSCCTL6,
3046                         temp);
3047
3048         /* Wait for initialization time */
3049         udelay(24);
3050
3051         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3052 }
3053
3054 /*
3055  * Enable PCH resources required for PCH ports:
3056  *   - PCH PLLs
3057  *   - FDI training & RX/TX
3058  *   - update transcoder timings
3059  *   - DP transcoding bits
3060  *   - transcoder
3061  */
3062 static void ironlake_pch_enable(struct drm_crtc *crtc)
3063 {
3064         struct drm_device *dev = crtc->dev;
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067         int pipe = intel_crtc->pipe;
3068         u32 reg, temp;
3069
3070         assert_transcoder_disabled(dev_priv, pipe);
3071
3072         /* Write the TU size bits before fdi link training, so that error
3073          * detection works. */
3074         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3075                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3076
3077         /* For PCH output, training FDI link */
3078         dev_priv->display.fdi_link_train(crtc);
3079
3080         /* XXX: pch pll's can be enabled any time before we enable the PCH
3081          * transcoder, and we actually should do this to not upset any PCH
3082          * transcoder that already use the clock when we share it.
3083          *
3084          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3085          * unconditionally resets the pll - we need that to have the right LVDS
3086          * enable sequence. */
3087         intel_enable_pch_pll(intel_crtc);
3088
3089         if (HAS_PCH_CPT(dev)) {
3090                 u32 sel;
3091
3092                 temp = I915_READ(PCH_DPLL_SEL);
3093                 switch (pipe) {
3094                 default:
3095                 case 0:
3096                         temp |= TRANSA_DPLL_ENABLE;
3097                         sel = TRANSA_DPLLB_SEL;
3098                         break;
3099                 case 1:
3100                         temp |= TRANSB_DPLL_ENABLE;
3101                         sel = TRANSB_DPLLB_SEL;
3102                         break;
3103                 case 2:
3104                         temp |= TRANSC_DPLL_ENABLE;
3105                         sel = TRANSC_DPLLB_SEL;
3106                         break;
3107                 }
3108                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3109                         temp |= sel;
3110                 else
3111                         temp &= ~sel;
3112                 I915_WRITE(PCH_DPLL_SEL, temp);
3113         }
3114
3115         /* set transcoder timing, panel must allow it */
3116         assert_panel_unlocked(dev_priv, pipe);
3117         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3118         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3119         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3120
3121         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3122         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3123         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3124         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3125
3126         intel_fdi_normal_train(crtc);
3127
3128         /* For PCH DP, enable TRANS_DP_CTL */
3129         if (HAS_PCH_CPT(dev) &&
3130             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3131              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3132                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3133                 reg = TRANS_DP_CTL(pipe);
3134                 temp = I915_READ(reg);
3135                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3136                           TRANS_DP_SYNC_MASK |
3137                           TRANS_DP_BPC_MASK);
3138                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3139                          TRANS_DP_ENH_FRAMING);
3140                 temp |= bpc << 9; /* same format but at 11:9 */
3141
3142                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3143                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3144                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3145                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3146
3147                 switch (intel_trans_dp_port_sel(crtc)) {
3148                 case PCH_DP_B:
3149                         temp |= TRANS_DP_PORT_SEL_B;
3150                         break;
3151                 case PCH_DP_C:
3152                         temp |= TRANS_DP_PORT_SEL_C;
3153                         break;
3154                 case PCH_DP_D:
3155                         temp |= TRANS_DP_PORT_SEL_D;
3156                         break;
3157                 default:
3158                         BUG();
3159                 }
3160
3161                 I915_WRITE(reg, temp);
3162         }
3163
3164         intel_enable_transcoder(dev_priv, pipe);
3165 }
3166
3167 static void lpt_pch_enable(struct drm_crtc *crtc)
3168 {
3169         struct drm_device *dev = crtc->dev;
3170         struct drm_i915_private *dev_priv = dev->dev_private;
3171         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172         int pipe = intel_crtc->pipe;
3173         u32 reg, temp;
3174
3175         assert_transcoder_disabled(dev_priv, pipe);
3176
3177         /* Write the TU size bits before fdi link training, so that error
3178          * detection works. */
3179         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3180                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3181
3182         /* For PCH output, training FDI link */
3183         dev_priv->display.fdi_link_train(crtc);
3184
3185         /* XXX: pch pll's can be enabled any time before we enable the PCH
3186          * transcoder, and we actually should do this to not upset any PCH
3187          * transcoder that already use the clock when we share it.
3188          *
3189          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3190          * unconditionally resets the pll - we need that to have the right LVDS
3191          * enable sequence. */
3192         intel_enable_pch_pll(intel_crtc);
3193
3194         if (HAS_PCH_LPT(dev)) {
3195                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3196                 lpt_program_iclkip(crtc);
3197         } else if (HAS_PCH_CPT(dev)) {
3198                 u32 sel;
3199
3200                 temp = I915_READ(PCH_DPLL_SEL);
3201                 switch (pipe) {
3202                 default:
3203                 case 0:
3204                         temp |= TRANSA_DPLL_ENABLE;
3205                         sel = TRANSA_DPLLB_SEL;
3206                         break;
3207                 case 1:
3208                         temp |= TRANSB_DPLL_ENABLE;
3209                         sel = TRANSB_DPLLB_SEL;
3210                         break;
3211                 case 2:
3212                         temp |= TRANSC_DPLL_ENABLE;
3213                         sel = TRANSC_DPLLB_SEL;
3214                         break;
3215                 }
3216                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3217                         temp |= sel;
3218                 else
3219                         temp &= ~sel;
3220                 I915_WRITE(PCH_DPLL_SEL, temp);
3221         }
3222
3223         /* set transcoder timing, panel must allow it */
3224         assert_panel_unlocked(dev_priv, pipe);
3225         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3226         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3227         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3228
3229         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3230         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3231         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3232         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3233
3234         if (!IS_HASWELL(dev))
3235                 intel_fdi_normal_train(crtc);
3236
3237         /* For PCH DP, enable TRANS_DP_CTL */
3238         if (HAS_PCH_CPT(dev) &&
3239             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3240              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3241                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3242                 reg = TRANS_DP_CTL(pipe);
3243                 temp = I915_READ(reg);
3244                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3245                           TRANS_DP_SYNC_MASK |
3246                           TRANS_DP_BPC_MASK);
3247                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3248                          TRANS_DP_ENH_FRAMING);
3249                 temp |= bpc << 9; /* same format but at 11:9 */
3250
3251                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3252                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3253                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3254                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3255
3256                 switch (intel_trans_dp_port_sel(crtc)) {
3257                 case PCH_DP_B:
3258                         temp |= TRANS_DP_PORT_SEL_B;
3259                         break;
3260                 case PCH_DP_C:
3261                         temp |= TRANS_DP_PORT_SEL_C;
3262                         break;
3263                 case PCH_DP_D:
3264                         temp |= TRANS_DP_PORT_SEL_D;
3265                         break;
3266                 default:
3267                         BUG();
3268                 }
3269
3270                 I915_WRITE(reg, temp);
3271         }
3272
3273         intel_enable_transcoder(dev_priv, pipe);
3274 }
3275
3276 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3277 {
3278         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3279
3280         if (pll == NULL)
3281                 return;
3282
3283         if (pll->refcount == 0) {
3284                 WARN(1, "bad PCH PLL refcount\n");
3285                 return;
3286         }
3287
3288         --pll->refcount;
3289         intel_crtc->pch_pll = NULL;
3290 }
3291
3292 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3293 {
3294         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3295         struct intel_pch_pll *pll;
3296         int i;
3297
3298         pll = intel_crtc->pch_pll;
3299         if (pll) {
3300                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3301                               intel_crtc->base.base.id, pll->pll_reg);
3302                 goto prepare;
3303         }
3304
3305         if (HAS_PCH_IBX(dev_priv->dev)) {
3306                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3307                 i = intel_crtc->pipe;
3308                 pll = &dev_priv->pch_plls[i];
3309
3310                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3311                               intel_crtc->base.base.id, pll->pll_reg);
3312
3313                 goto found;
3314         }
3315
3316         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3317                 pll = &dev_priv->pch_plls[i];
3318
3319                 /* Only want to check enabled timings first */
3320                 if (pll->refcount == 0)
3321                         continue;
3322
3323                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3324                     fp == I915_READ(pll->fp0_reg)) {
3325                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3326                                       intel_crtc->base.base.id,
3327                                       pll->pll_reg, pll->refcount, pll->active);
3328
3329                         goto found;
3330                 }
3331         }
3332
3333         /* Ok no matching timings, maybe there's a free one? */
3334         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3335                 pll = &dev_priv->pch_plls[i];
3336                 if (pll->refcount == 0) {
3337                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3338                                       intel_crtc->base.base.id, pll->pll_reg);
3339                         goto found;
3340                 }
3341         }
3342
3343         return NULL;
3344
3345 found:
3346         intel_crtc->pch_pll = pll;
3347         pll->refcount++;
3348         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3349 prepare: /* separate function? */
3350         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3351
3352         /* Wait for the clocks to stabilize before rewriting the regs */
3353         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3354         POSTING_READ(pll->pll_reg);
3355         udelay(150);
3356
3357         I915_WRITE(pll->fp0_reg, fp);
3358         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3359         pll->on = false;
3360         return pll;
3361 }
3362
3363 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3364 {
3365         struct drm_i915_private *dev_priv = dev->dev_private;
3366         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3367         u32 temp;
3368
3369         temp = I915_READ(dslreg);
3370         udelay(500);
3371         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3372                 /* Without this, mode sets may fail silently on FDI */
3373                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3374                 udelay(250);
3375                 I915_WRITE(tc2reg, 0);
3376                 if (wait_for(I915_READ(dslreg) != temp, 5))
3377                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3378         }
3379 }
3380
3381 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3382 {
3383         struct drm_device *dev = crtc->dev;
3384         struct drm_i915_private *dev_priv = dev->dev_private;
3385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386         struct intel_encoder *encoder;
3387         int pipe = intel_crtc->pipe;
3388         int plane = intel_crtc->plane;
3389         u32 temp;
3390         bool is_pch_port;
3391
3392         WARN_ON(!crtc->enabled);
3393
3394         if (intel_crtc->active)
3395                 return;
3396
3397         intel_crtc->active = true;
3398         intel_update_watermarks(dev);
3399
3400         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3401                 temp = I915_READ(PCH_LVDS);
3402                 if ((temp & LVDS_PORT_EN) == 0)
3403                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3404         }
3405
3406         is_pch_port = ironlake_crtc_driving_pch(crtc);
3407
3408         if (is_pch_port) {
3409                 /* Note: FDI PLL enabling _must_ be done before we enable the
3410                  * cpu pipes, hence this is separate from all the other fdi/pch
3411                  * enabling. */
3412                 ironlake_fdi_pll_enable(intel_crtc);
3413         } else {
3414                 assert_fdi_tx_disabled(dev_priv, pipe);
3415                 assert_fdi_rx_disabled(dev_priv, pipe);
3416         }
3417
3418         for_each_encoder_on_crtc(dev, crtc, encoder)
3419                 if (encoder->pre_enable)
3420                         encoder->pre_enable(encoder);
3421
3422         /* Enable panel fitting for LVDS */
3423         if (dev_priv->pch_pf_size &&
3424             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3425                 /* Force use of hard-coded filter coefficients
3426                  * as some pre-programmed values are broken,
3427                  * e.g. x201.
3428                  */
3429                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3430                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3431                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3432         }
3433
3434         /*
3435          * On ILK+ LUT must be loaded before the pipe is running but with
3436          * clocks enabled
3437          */
3438         intel_crtc_load_lut(crtc);
3439
3440         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3441         intel_enable_plane(dev_priv, plane, pipe);
3442
3443         if (is_pch_port)
3444                 ironlake_pch_enable(crtc);
3445
3446         mutex_lock(&dev->struct_mutex);
3447         intel_update_fbc(dev);
3448         mutex_unlock(&dev->struct_mutex);
3449
3450         intel_crtc_update_cursor(crtc, true);
3451
3452         for_each_encoder_on_crtc(dev, crtc, encoder)
3453                 encoder->enable(encoder);
3454
3455         if (HAS_PCH_CPT(dev))
3456                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3457
3458         /*
3459          * There seems to be a race in PCH platform hw (at least on some
3460          * outputs) where an enabled pipe still completes any pageflip right
3461          * away (as if the pipe is off) instead of waiting for vblank. As soon
3462          * as the first vblank happend, everything works as expected. Hence just
3463          * wait for one vblank before returning to avoid strange things
3464          * happening.
3465          */
3466         intel_wait_for_vblank(dev, intel_crtc->pipe);
3467 }
3468
3469 static void haswell_crtc_enable(struct drm_crtc *crtc)
3470 {
3471         struct drm_device *dev = crtc->dev;
3472         struct drm_i915_private *dev_priv = dev->dev_private;
3473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3474         struct intel_encoder *encoder;
3475         int pipe = intel_crtc->pipe;
3476         int plane = intel_crtc->plane;
3477         bool is_pch_port;
3478
3479         WARN_ON(!crtc->enabled);
3480
3481         if (intel_crtc->active)
3482                 return;
3483
3484         intel_crtc->active = true;
3485         intel_update_watermarks(dev);
3486
3487         is_pch_port = haswell_crtc_driving_pch(crtc);
3488
3489         if (is_pch_port)
3490                 ironlake_fdi_pll_enable(intel_crtc);
3491
3492         for_each_encoder_on_crtc(dev, crtc, encoder)
3493                 if (encoder->pre_enable)
3494                         encoder->pre_enable(encoder);
3495
3496         intel_ddi_enable_pipe_clock(intel_crtc);
3497
3498         /* Enable panel fitting for eDP */
3499         if (dev_priv->pch_pf_size && HAS_eDP) {
3500                 /* Force use of hard-coded filter coefficients
3501                  * as some pre-programmed values are broken,
3502                  * e.g. x201.
3503                  */
3504                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3505                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3506                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3507         }
3508
3509         /*
3510          * On ILK+ LUT must be loaded before the pipe is running but with
3511          * clocks enabled
3512          */
3513         intel_crtc_load_lut(crtc);
3514
3515         intel_ddi_set_pipe_settings(crtc);
3516         intel_ddi_enable_pipe_func(crtc);
3517
3518         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3519         intel_enable_plane(dev_priv, plane, pipe);
3520
3521         if (is_pch_port)
3522                 lpt_pch_enable(crtc);
3523
3524         mutex_lock(&dev->struct_mutex);
3525         intel_update_fbc(dev);
3526         mutex_unlock(&dev->struct_mutex);
3527
3528         intel_crtc_update_cursor(crtc, true);
3529
3530         for_each_encoder_on_crtc(dev, crtc, encoder)
3531                 encoder->enable(encoder);
3532
3533         /*
3534          * There seems to be a race in PCH platform hw (at least on some
3535          * outputs) where an enabled pipe still completes any pageflip right
3536          * away (as if the pipe is off) instead of waiting for vblank. As soon
3537          * as the first vblank happend, everything works as expected. Hence just
3538          * wait for one vblank before returning to avoid strange things
3539          * happening.
3540          */
3541         intel_wait_for_vblank(dev, intel_crtc->pipe);
3542 }
3543
3544 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3545 {
3546         struct drm_device *dev = crtc->dev;
3547         struct drm_i915_private *dev_priv = dev->dev_private;
3548         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3549         struct intel_encoder *encoder;
3550         int pipe = intel_crtc->pipe;
3551         int plane = intel_crtc->plane;
3552         u32 reg, temp;
3553
3554
3555         if (!intel_crtc->active)
3556                 return;
3557
3558         for_each_encoder_on_crtc(dev, crtc, encoder)
3559                 encoder->disable(encoder);
3560
3561         intel_crtc_wait_for_pending_flips(crtc);
3562         drm_vblank_off(dev, pipe);
3563         intel_crtc_update_cursor(crtc, false);
3564
3565         intel_disable_plane(dev_priv, plane, pipe);
3566
3567         if (dev_priv->cfb_plane == plane)
3568                 intel_disable_fbc(dev);
3569
3570         intel_disable_pipe(dev_priv, pipe);
3571
3572         /* Disable PF */
3573         I915_WRITE(PF_CTL(pipe), 0);
3574         I915_WRITE(PF_WIN_SZ(pipe), 0);
3575
3576         for_each_encoder_on_crtc(dev, crtc, encoder)
3577                 if (encoder->post_disable)
3578                         encoder->post_disable(encoder);
3579
3580         ironlake_fdi_disable(crtc);
3581
3582         intel_disable_transcoder(dev_priv, pipe);
3583
3584         if (HAS_PCH_CPT(dev)) {
3585                 /* disable TRANS_DP_CTL */
3586                 reg = TRANS_DP_CTL(pipe);
3587                 temp = I915_READ(reg);
3588                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3589                 temp |= TRANS_DP_PORT_SEL_NONE;
3590                 I915_WRITE(reg, temp);
3591
3592                 /* disable DPLL_SEL */
3593                 temp = I915_READ(PCH_DPLL_SEL);
3594                 switch (pipe) {
3595                 case 0:
3596                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3597                         break;
3598                 case 1:
3599                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3600                         break;
3601                 case 2:
3602                         /* C shares PLL A or B */
3603                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3604                         break;
3605                 default:
3606                         BUG(); /* wtf */
3607                 }
3608                 I915_WRITE(PCH_DPLL_SEL, temp);
3609         }
3610
3611         /* disable PCH DPLL */
3612         intel_disable_pch_pll(intel_crtc);
3613
3614         ironlake_fdi_pll_disable(intel_crtc);
3615
3616         intel_crtc->active = false;
3617         intel_update_watermarks(dev);
3618
3619         mutex_lock(&dev->struct_mutex);
3620         intel_update_fbc(dev);
3621         mutex_unlock(&dev->struct_mutex);
3622 }
3623
3624 static void haswell_crtc_disable(struct drm_crtc *crtc)
3625 {
3626         struct drm_device *dev = crtc->dev;
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629         struct intel_encoder *encoder;
3630         int pipe = intel_crtc->pipe;
3631         int plane = intel_crtc->plane;
3632         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3633         bool is_pch_port;
3634
3635         if (!intel_crtc->active)
3636                 return;
3637
3638         is_pch_port = haswell_crtc_driving_pch(crtc);
3639
3640         for_each_encoder_on_crtc(dev, crtc, encoder)
3641                 encoder->disable(encoder);
3642
3643         intel_crtc_wait_for_pending_flips(crtc);
3644         drm_vblank_off(dev, pipe);
3645         intel_crtc_update_cursor(crtc, false);
3646
3647         intel_disable_plane(dev_priv, plane, pipe);
3648
3649         if (dev_priv->cfb_plane == plane)
3650                 intel_disable_fbc(dev);
3651
3652         intel_disable_pipe(dev_priv, pipe);
3653
3654         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3655
3656         /* Disable PF */
3657         I915_WRITE(PF_CTL(pipe), 0);
3658         I915_WRITE(PF_WIN_SZ(pipe), 0);
3659
3660         intel_ddi_disable_pipe_clock(intel_crtc);
3661
3662         for_each_encoder_on_crtc(dev, crtc, encoder)
3663                 if (encoder->post_disable)
3664                         encoder->post_disable(encoder);
3665
3666         if (is_pch_port) {
3667                 ironlake_fdi_disable(crtc);
3668                 intel_disable_transcoder(dev_priv, pipe);
3669                 intel_disable_pch_pll(intel_crtc);
3670                 ironlake_fdi_pll_disable(intel_crtc);
3671         }
3672
3673         intel_crtc->active = false;
3674         intel_update_watermarks(dev);
3675
3676         mutex_lock(&dev->struct_mutex);
3677         intel_update_fbc(dev);
3678         mutex_unlock(&dev->struct_mutex);
3679 }
3680
3681 static void ironlake_crtc_off(struct drm_crtc *crtc)
3682 {
3683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3684         intel_put_pch_pll(intel_crtc);
3685 }
3686
3687 static void haswell_crtc_off(struct drm_crtc *crtc)
3688 {
3689         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3690
3691         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3692          * start using it. */
3693         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3694
3695         intel_ddi_put_crtc_pll(crtc);
3696 }
3697
3698 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3699 {
3700         if (!enable && intel_crtc->overlay) {
3701                 struct drm_device *dev = intel_crtc->base.dev;
3702                 struct drm_i915_private *dev_priv = dev->dev_private;
3703
3704                 mutex_lock(&dev->struct_mutex);
3705                 dev_priv->mm.interruptible = false;
3706                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3707                 dev_priv->mm.interruptible = true;
3708                 mutex_unlock(&dev->struct_mutex);
3709         }
3710
3711         /* Let userspace switch the overlay on again. In most cases userspace
3712          * has to recompute where to put it anyway.
3713          */
3714 }
3715
3716 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3717 {
3718         struct drm_device *dev = crtc->dev;
3719         struct drm_i915_private *dev_priv = dev->dev_private;
3720         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3721         struct intel_encoder *encoder;
3722         int pipe = intel_crtc->pipe;
3723         int plane = intel_crtc->plane;
3724
3725         WARN_ON(!crtc->enabled);
3726
3727         if (intel_crtc->active)
3728                 return;
3729
3730         intel_crtc->active = true;
3731         intel_update_watermarks(dev);
3732
3733         intel_enable_pll(dev_priv, pipe);
3734         intel_enable_pipe(dev_priv, pipe, false);
3735         intel_enable_plane(dev_priv, plane, pipe);
3736
3737         intel_crtc_load_lut(crtc);
3738         intel_update_fbc(dev);
3739
3740         /* Give the overlay scaler a chance to enable if it's on this pipe */
3741         intel_crtc_dpms_overlay(intel_crtc, true);
3742         intel_crtc_update_cursor(crtc, true);
3743
3744         for_each_encoder_on_crtc(dev, crtc, encoder)
3745                 encoder->enable(encoder);
3746 }
3747
3748 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3749 {
3750         struct drm_device *dev = crtc->dev;
3751         struct drm_i915_private *dev_priv = dev->dev_private;
3752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3753         struct intel_encoder *encoder;
3754         int pipe = intel_crtc->pipe;
3755         int plane = intel_crtc->plane;
3756
3757
3758         if (!intel_crtc->active)
3759                 return;
3760
3761         for_each_encoder_on_crtc(dev, crtc, encoder)
3762                 encoder->disable(encoder);
3763
3764         /* Give the overlay scaler a chance to disable if it's on this pipe */
3765         intel_crtc_wait_for_pending_flips(crtc);
3766         drm_vblank_off(dev, pipe);
3767         intel_crtc_dpms_overlay(intel_crtc, false);
3768         intel_crtc_update_cursor(crtc, false);
3769
3770         if (dev_priv->cfb_plane == plane)
3771                 intel_disable_fbc(dev);
3772
3773         intel_disable_plane(dev_priv, plane, pipe);
3774         intel_disable_pipe(dev_priv, pipe);
3775         intel_disable_pll(dev_priv, pipe);
3776
3777         intel_crtc->active = false;
3778         intel_update_fbc(dev);
3779         intel_update_watermarks(dev);
3780 }
3781
3782 static void i9xx_crtc_off(struct drm_crtc *crtc)
3783 {
3784 }
3785
3786 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3787                                     bool enabled)
3788 {
3789         struct drm_device *dev = crtc->dev;
3790         struct drm_i915_master_private *master_priv;
3791         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792         int pipe = intel_crtc->pipe;
3793
3794         if (!dev->primary->master)
3795                 return;
3796
3797         master_priv = dev->primary->master->driver_priv;
3798         if (!master_priv->sarea_priv)
3799                 return;
3800
3801         switch (pipe) {
3802         case 0:
3803                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3804                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3805                 break;
3806         case 1:
3807                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3808                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3809                 break;
3810         default:
3811                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3812                 break;
3813         }
3814 }
3815
3816 /**
3817  * Sets the power management mode of the pipe and plane.
3818  */
3819 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         struct intel_encoder *intel_encoder;
3824         bool enable = false;
3825
3826         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3827                 enable |= intel_encoder->connectors_active;
3828
3829         if (enable)
3830                 dev_priv->display.crtc_enable(crtc);
3831         else
3832                 dev_priv->display.crtc_disable(crtc);
3833
3834         intel_crtc_update_sarea(crtc, enable);
3835 }
3836
3837 static void intel_crtc_noop(struct drm_crtc *crtc)
3838 {
3839 }
3840
3841 static void intel_crtc_disable(struct drm_crtc *crtc)
3842 {
3843         struct drm_device *dev = crtc->dev;
3844         struct drm_connector *connector;
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846
3847         /* crtc should still be enabled when we disable it. */
3848         WARN_ON(!crtc->enabled);
3849
3850         dev_priv->display.crtc_disable(crtc);
3851         intel_crtc_update_sarea(crtc, false);
3852         dev_priv->display.off(crtc);
3853
3854         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3855         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3856
3857         if (crtc->fb) {
3858                 mutex_lock(&dev->struct_mutex);
3859                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3860                 mutex_unlock(&dev->struct_mutex);
3861                 crtc->fb = NULL;
3862         }
3863
3864         /* Update computed state. */
3865         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3866                 if (!connector->encoder || !connector->encoder->crtc)
3867                         continue;
3868
3869                 if (connector->encoder->crtc != crtc)
3870                         continue;
3871
3872                 connector->dpms = DRM_MODE_DPMS_OFF;
3873                 to_intel_encoder(connector->encoder)->connectors_active = false;
3874         }
3875 }
3876
3877 void intel_modeset_disable(struct drm_device *dev)
3878 {
3879         struct drm_crtc *crtc;
3880
3881         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3882                 if (crtc->enabled)
3883                         intel_crtc_disable(crtc);
3884         }
3885 }
3886
3887 void intel_encoder_noop(struct drm_encoder *encoder)
3888 {
3889 }
3890
3891 void intel_encoder_destroy(struct drm_encoder *encoder)
3892 {
3893         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3894
3895         drm_encoder_cleanup(encoder);
3896         kfree(intel_encoder);
3897 }
3898
3899 /* Simple dpms helper for encodres with just one connector, no cloning and only
3900  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3901  * state of the entire output pipe. */
3902 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3903 {
3904         if (mode == DRM_MODE_DPMS_ON) {
3905                 encoder->connectors_active = true;
3906
3907                 intel_crtc_update_dpms(encoder->base.crtc);
3908         } else {
3909                 encoder->connectors_active = false;
3910
3911                 intel_crtc_update_dpms(encoder->base.crtc);
3912         }
3913 }
3914
3915 /* Cross check the actual hw state with our own modeset state tracking (and it's
3916  * internal consistency). */
3917 static void intel_connector_check_state(struct intel_connector *connector)
3918 {
3919         if (connector->get_hw_state(connector)) {
3920                 struct intel_encoder *encoder = connector->encoder;
3921                 struct drm_crtc *crtc;
3922                 bool encoder_enabled;
3923                 enum pipe pipe;
3924
3925                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3926                               connector->base.base.id,
3927                               drm_get_connector_name(&connector->base));
3928
3929                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3930                      "wrong connector dpms state\n");
3931                 WARN(connector->base.encoder != &encoder->base,
3932                      "active connector not linked to encoder\n");
3933                 WARN(!encoder->connectors_active,
3934                      "encoder->connectors_active not set\n");
3935
3936                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3937                 WARN(!encoder_enabled, "encoder not enabled\n");
3938                 if (WARN_ON(!encoder->base.crtc))
3939                         return;
3940
3941                 crtc = encoder->base.crtc;
3942
3943                 WARN(!crtc->enabled, "crtc not enabled\n");
3944                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3945                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3946                      "encoder active on the wrong pipe\n");
3947         }
3948 }
3949
3950 /* Even simpler default implementation, if there's really no special case to
3951  * consider. */
3952 void intel_connector_dpms(struct drm_connector *connector, int mode)
3953 {
3954         struct intel_encoder *encoder = intel_attached_encoder(connector);
3955
3956         /* All the simple cases only support two dpms states. */
3957         if (mode != DRM_MODE_DPMS_ON)
3958                 mode = DRM_MODE_DPMS_OFF;
3959
3960         if (mode == connector->dpms)
3961                 return;
3962
3963         connector->dpms = mode;
3964
3965         /* Only need to change hw state when actually enabled */
3966         if (encoder->base.crtc)
3967                 intel_encoder_dpms(encoder, mode);
3968         else
3969                 WARN_ON(encoder->connectors_active != false);
3970
3971         intel_modeset_check_state(connector->dev);
3972 }
3973
3974 /* Simple connector->get_hw_state implementation for encoders that support only
3975  * one connector and no cloning and hence the encoder state determines the state
3976  * of the connector. */
3977 bool intel_connector_get_hw_state(struct intel_connector *connector)
3978 {
3979         enum pipe pipe = 0;
3980         struct intel_encoder *encoder = connector->encoder;
3981
3982         return encoder->get_hw_state(encoder, &pipe);
3983 }
3984
3985 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3986                                   const struct drm_display_mode *mode,
3987                                   struct drm_display_mode *adjusted_mode)
3988 {
3989         struct drm_device *dev = crtc->dev;
3990
3991         if (HAS_PCH_SPLIT(dev)) {
3992                 /* FDI link clock is fixed at 2.7G */
3993                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3994                         return false;
3995         }
3996
3997         /* All interlaced capable intel hw wants timings in frames. Note though
3998          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3999          * timings, so we need to be careful not to clobber these.*/
4000         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
4001                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4002
4003         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4004          * with a hsync front porch of 0.
4005          */
4006         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4007                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4008                 return false;
4009
4010         return true;
4011 }
4012
4013 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4014 {
4015         return 400000; /* FIXME */
4016 }
4017
4018 static int i945_get_display_clock_speed(struct drm_device *dev)
4019 {
4020         return 400000;
4021 }
4022
4023 static int i915_get_display_clock_speed(struct drm_device *dev)
4024 {
4025         return 333000;
4026 }
4027
4028 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4029 {
4030         return 200000;
4031 }
4032
4033 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4034 {
4035         u16 gcfgc = 0;
4036
4037         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4038
4039         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4040                 return 133000;
4041         else {
4042                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4043                 case GC_DISPLAY_CLOCK_333_MHZ:
4044                         return 333000;
4045                 default:
4046                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4047                         return 190000;
4048                 }
4049         }
4050 }
4051
4052 static int i865_get_display_clock_speed(struct drm_device *dev)
4053 {
4054         return 266000;
4055 }
4056
4057 static int i855_get_display_clock_speed(struct drm_device *dev)
4058 {
4059         u16 hpllcc = 0;
4060         /* Assume that the hardware is in the high speed state.  This
4061          * should be the default.
4062          */
4063         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4064         case GC_CLOCK_133_200:
4065         case GC_CLOCK_100_200:
4066                 return 200000;
4067         case GC_CLOCK_166_250:
4068                 return 250000;
4069         case GC_CLOCK_100_133:
4070                 return 133000;
4071         }
4072
4073         /* Shouldn't happen */
4074         return 0;
4075 }
4076
4077 static int i830_get_display_clock_speed(struct drm_device *dev)
4078 {
4079         return 133000;
4080 }
4081
4082 struct fdi_m_n {
4083         u32        tu;
4084         u32        gmch_m;
4085         u32        gmch_n;
4086         u32        link_m;
4087         u32        link_n;
4088 };
4089
4090 static void
4091 fdi_reduce_ratio(u32 *num, u32 *den)
4092 {
4093         while (*num > 0xffffff || *den > 0xffffff) {
4094                 *num >>= 1;
4095                 *den >>= 1;
4096         }
4097 }
4098
4099 static void
4100 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4101                      int link_clock, struct fdi_m_n *m_n)
4102 {
4103         m_n->tu = 64; /* default size */
4104
4105         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4106         m_n->gmch_m = bits_per_pixel * pixel_clock;
4107         m_n->gmch_n = link_clock * nlanes * 8;
4108         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4109
4110         m_n->link_m = pixel_clock;
4111         m_n->link_n = link_clock;
4112         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4113 }
4114
4115 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4116 {
4117         if (i915_panel_use_ssc >= 0)
4118                 return i915_panel_use_ssc != 0;
4119         return dev_priv->lvds_use_ssc
4120                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4121 }
4122
4123 /**
4124  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4125  * @crtc: CRTC structure
4126  * @mode: requested mode
4127  *
4128  * A pipe may be connected to one or more outputs.  Based on the depth of the
4129  * attached framebuffer, choose a good color depth to use on the pipe.
4130  *
4131  * If possible, match the pipe depth to the fb depth.  In some cases, this
4132  * isn't ideal, because the connected output supports a lesser or restricted
4133  * set of depths.  Resolve that here:
4134  *    LVDS typically supports only 6bpc, so clamp down in that case
4135  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4136  *    Displays may support a restricted set as well, check EDID and clamp as
4137  *      appropriate.
4138  *    DP may want to dither down to 6bpc to fit larger modes
4139  *
4140  * RETURNS:
4141  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4142  * true if they don't match).
4143  */
4144 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4145                                          struct drm_framebuffer *fb,
4146                                          unsigned int *pipe_bpp,
4147                                          struct drm_display_mode *mode)
4148 {
4149         struct drm_device *dev = crtc->dev;
4150         struct drm_i915_private *dev_priv = dev->dev_private;
4151         struct drm_connector *connector;
4152         struct intel_encoder *intel_encoder;
4153         unsigned int display_bpc = UINT_MAX, bpc;
4154
4155         /* Walk the encoders & connectors on this crtc, get min bpc */
4156         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4157
4158                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4159                         unsigned int lvds_bpc;
4160
4161                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4162                             LVDS_A3_POWER_UP)
4163                                 lvds_bpc = 8;
4164                         else
4165                                 lvds_bpc = 6;
4166
4167                         if (lvds_bpc < display_bpc) {
4168                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4169                                 display_bpc = lvds_bpc;
4170                         }
4171                         continue;
4172                 }
4173
4174                 /* Not one of the known troublemakers, check the EDID */
4175                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4176                                     head) {
4177                         if (connector->encoder != &intel_encoder->base)
4178                                 continue;
4179
4180                         /* Don't use an invalid EDID bpc value */
4181                         if (connector->display_info.bpc &&
4182                             connector->display_info.bpc < display_bpc) {
4183                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4184                                 display_bpc = connector->display_info.bpc;
4185                         }
4186                 }
4187
4188                 /*
4189                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4190                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4191                  */
4192                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4193                         if (display_bpc > 8 && display_bpc < 12) {
4194                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4195                                 display_bpc = 12;
4196                         } else {
4197                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4198                                 display_bpc = 8;
4199                         }
4200                 }
4201         }
4202
4203         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4204                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4205                 display_bpc = 6;
4206         }
4207
4208         /*
4209          * We could just drive the pipe at the highest bpc all the time and
4210          * enable dithering as needed, but that costs bandwidth.  So choose
4211          * the minimum value that expresses the full color range of the fb but
4212          * also stays within the max display bpc discovered above.
4213          */
4214
4215         switch (fb->depth) {
4216         case 8:
4217                 bpc = 8; /* since we go through a colormap */
4218                 break;
4219         case 15:
4220         case 16:
4221                 bpc = 6; /* min is 18bpp */
4222                 break;
4223         case 24:
4224                 bpc = 8;
4225                 break;
4226         case 30:
4227                 bpc = 10;
4228                 break;
4229         case 48:
4230                 bpc = 12;
4231                 break;
4232         default:
4233                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4234                 bpc = min((unsigned int)8, display_bpc);
4235                 break;
4236         }
4237
4238         display_bpc = min(display_bpc, bpc);
4239
4240         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4241                       bpc, display_bpc);
4242
4243         *pipe_bpp = display_bpc * 3;
4244
4245         return display_bpc != bpc;
4246 }
4247
4248 static int vlv_get_refclk(struct drm_crtc *crtc)
4249 {
4250         struct drm_device *dev = crtc->dev;
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         int refclk = 27000; /* for DP & HDMI */
4253
4254         return 100000; /* only one validated so far */
4255
4256         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4257                 refclk = 96000;
4258         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4259                 if (intel_panel_use_ssc(dev_priv))
4260                         refclk = 100000;
4261                 else
4262                         refclk = 96000;
4263         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4264                 refclk = 100000;
4265         }
4266
4267         return refclk;
4268 }
4269
4270 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4271 {
4272         struct drm_device *dev = crtc->dev;
4273         struct drm_i915_private *dev_priv = dev->dev_private;
4274         int refclk;
4275
4276         if (IS_VALLEYVIEW(dev)) {
4277                 refclk = vlv_get_refclk(crtc);
4278         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4279             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4280                 refclk = dev_priv->lvds_ssc_freq * 1000;
4281                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4282                               refclk / 1000);
4283         } else if (!IS_GEN2(dev)) {
4284                 refclk = 96000;
4285         } else {
4286                 refclk = 48000;
4287         }
4288
4289         return refclk;
4290 }
4291
4292 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4293                                       intel_clock_t *clock)
4294 {
4295         /* SDVO TV has fixed PLL values depend on its clock range,
4296            this mirrors vbios setting. */
4297         if (adjusted_mode->clock >= 100000
4298             && adjusted_mode->clock < 140500) {
4299                 clock->p1 = 2;
4300                 clock->p2 = 10;
4301                 clock->n = 3;
4302                 clock->m1 = 16;
4303                 clock->m2 = 8;
4304         } else if (adjusted_mode->clock >= 140500
4305                    && adjusted_mode->clock <= 200000) {
4306                 clock->p1 = 1;
4307                 clock->p2 = 10;
4308                 clock->n = 6;
4309                 clock->m1 = 12;
4310                 clock->m2 = 8;
4311         }
4312 }
4313
4314 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4315                                      intel_clock_t *clock,
4316                                      intel_clock_t *reduced_clock)
4317 {
4318         struct drm_device *dev = crtc->dev;
4319         struct drm_i915_private *dev_priv = dev->dev_private;
4320         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4321         int pipe = intel_crtc->pipe;
4322         u32 fp, fp2 = 0;
4323
4324         if (IS_PINEVIEW(dev)) {
4325                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4326                 if (reduced_clock)
4327                         fp2 = (1 << reduced_clock->n) << 16 |
4328                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4329         } else {
4330                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4331                 if (reduced_clock)
4332                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4333                                 reduced_clock->m2;
4334         }
4335
4336         I915_WRITE(FP0(pipe), fp);
4337
4338         intel_crtc->lowfreq_avail = false;
4339         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4340             reduced_clock && i915_powersave) {
4341                 I915_WRITE(FP1(pipe), fp2);
4342                 intel_crtc->lowfreq_avail = true;
4343         } else {
4344                 I915_WRITE(FP1(pipe), fp);
4345         }
4346 }
4347
4348 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4349                               struct drm_display_mode *adjusted_mode)
4350 {
4351         struct drm_device *dev = crtc->dev;
4352         struct drm_i915_private *dev_priv = dev->dev_private;
4353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4354         int pipe = intel_crtc->pipe;
4355         u32 temp;
4356
4357         temp = I915_READ(LVDS);
4358         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4359         if (pipe == 1) {
4360                 temp |= LVDS_PIPEB_SELECT;
4361         } else {
4362                 temp &= ~LVDS_PIPEB_SELECT;
4363         }
4364         /* set the corresponsding LVDS_BORDER bit */
4365         temp |= dev_priv->lvds_border_bits;
4366         /* Set the B0-B3 data pairs corresponding to whether we're going to
4367          * set the DPLLs for dual-channel mode or not.
4368          */
4369         if (clock->p2 == 7)
4370                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4371         else
4372                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4373
4374         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4375          * appropriately here, but we need to look more thoroughly into how
4376          * panels behave in the two modes.
4377          */
4378         /* set the dithering flag on LVDS as needed */
4379         if (INTEL_INFO(dev)->gen >= 4) {
4380                 if (dev_priv->lvds_dither)
4381                         temp |= LVDS_ENABLE_DITHER;
4382                 else
4383                         temp &= ~LVDS_ENABLE_DITHER;
4384         }
4385         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4386         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4387                 temp |= LVDS_HSYNC_POLARITY;
4388         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4389                 temp |= LVDS_VSYNC_POLARITY;
4390         I915_WRITE(LVDS, temp);
4391 }
4392
4393 static void vlv_update_pll(struct drm_crtc *crtc,
4394                            struct drm_display_mode *mode,
4395                            struct drm_display_mode *adjusted_mode,
4396                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4397                            int num_connectors)
4398 {
4399         struct drm_device *dev = crtc->dev;
4400         struct drm_i915_private *dev_priv = dev->dev_private;
4401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4402         int pipe = intel_crtc->pipe;
4403         u32 dpll, mdiv, pdiv;
4404         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4405         bool is_sdvo;
4406         u32 temp;
4407
4408         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4409                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4410
4411         dpll = DPLL_VGA_MODE_DIS;
4412         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4413         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4414         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4415
4416         I915_WRITE(DPLL(pipe), dpll);
4417         POSTING_READ(DPLL(pipe));
4418
4419         bestn = clock->n;
4420         bestm1 = clock->m1;
4421         bestm2 = clock->m2;
4422         bestp1 = clock->p1;
4423         bestp2 = clock->p2;
4424
4425         /*
4426          * In Valleyview PLL and program lane counter registers are exposed
4427          * through DPIO interface
4428          */
4429         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4430         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4431         mdiv |= ((bestn << DPIO_N_SHIFT));
4432         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4433         mdiv |= (1 << DPIO_K_SHIFT);
4434         mdiv |= DPIO_ENABLE_CALIBRATION;
4435         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4436
4437         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4438
4439         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4440                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4441                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4442                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4443         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4444
4445         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4446
4447         dpll |= DPLL_VCO_ENABLE;
4448         I915_WRITE(DPLL(pipe), dpll);
4449         POSTING_READ(DPLL(pipe));
4450         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4451                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4452
4453         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4454
4455         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4456                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4457
4458         I915_WRITE(DPLL(pipe), dpll);
4459
4460         /* Wait for the clocks to stabilize. */
4461         POSTING_READ(DPLL(pipe));
4462         udelay(150);
4463
4464         temp = 0;
4465         if (is_sdvo) {
4466                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4467                 if (temp > 1)
4468                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4469                 else
4470                         temp = 0;
4471         }
4472         I915_WRITE(DPLL_MD(pipe), temp);
4473         POSTING_READ(DPLL_MD(pipe));
4474
4475         /* Now program lane control registers */
4476         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4477                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4478         {
4479                 temp = 0x1000C4;
4480                 if(pipe == 1)
4481                         temp |= (1 << 21);
4482                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4483         }
4484         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4485         {
4486                 temp = 0x1000C4;
4487                 if(pipe == 1)
4488                         temp |= (1 << 21);
4489                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4490         }
4491 }
4492
4493 static void i9xx_update_pll(struct drm_crtc *crtc,
4494                             struct drm_display_mode *mode,
4495                             struct drm_display_mode *adjusted_mode,
4496                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4497                             int num_connectors)
4498 {
4499         struct drm_device *dev = crtc->dev;
4500         struct drm_i915_private *dev_priv = dev->dev_private;
4501         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4502         int pipe = intel_crtc->pipe;
4503         u32 dpll;
4504         bool is_sdvo;
4505
4506         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4507
4508         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4509                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4510
4511         dpll = DPLL_VGA_MODE_DIS;
4512
4513         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4514                 dpll |= DPLLB_MODE_LVDS;
4515         else
4516                 dpll |= DPLLB_MODE_DAC_SERIAL;
4517         if (is_sdvo) {
4518                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4519                 if (pixel_multiplier > 1) {
4520                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4521                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4522                 }
4523                 dpll |= DPLL_DVO_HIGH_SPEED;
4524         }
4525         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4526                 dpll |= DPLL_DVO_HIGH_SPEED;
4527
4528         /* compute bitmask from p1 value */
4529         if (IS_PINEVIEW(dev))
4530                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4531         else {
4532                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4533                 if (IS_G4X(dev) && reduced_clock)
4534                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4535         }
4536         switch (clock->p2) {
4537         case 5:
4538                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4539                 break;
4540         case 7:
4541                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4542                 break;
4543         case 10:
4544                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4545                 break;
4546         case 14:
4547                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4548                 break;
4549         }
4550         if (INTEL_INFO(dev)->gen >= 4)
4551                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4552
4553         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4554                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4555         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4556                 /* XXX: just matching BIOS for now */
4557                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4558                 dpll |= 3;
4559         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4560                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4561                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4562         else
4563                 dpll |= PLL_REF_INPUT_DREFCLK;
4564
4565         dpll |= DPLL_VCO_ENABLE;
4566         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4567         POSTING_READ(DPLL(pipe));
4568         udelay(150);
4569
4570         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4571          * This is an exception to the general rule that mode_set doesn't turn
4572          * things on.
4573          */
4574         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4575                 intel_update_lvds(crtc, clock, adjusted_mode);
4576
4577         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4578                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4579
4580         I915_WRITE(DPLL(pipe), dpll);
4581
4582         /* Wait for the clocks to stabilize. */
4583         POSTING_READ(DPLL(pipe));
4584         udelay(150);
4585
4586         if (INTEL_INFO(dev)->gen >= 4) {
4587                 u32 temp = 0;
4588                 if (is_sdvo) {
4589                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4590                         if (temp > 1)
4591                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4592                         else
4593                                 temp = 0;
4594                 }
4595                 I915_WRITE(DPLL_MD(pipe), temp);
4596         } else {
4597                 /* The pixel multiplier can only be updated once the
4598                  * DPLL is enabled and the clocks are stable.
4599                  *
4600                  * So write it again.
4601                  */
4602                 I915_WRITE(DPLL(pipe), dpll);
4603         }
4604 }
4605
4606 static void i8xx_update_pll(struct drm_crtc *crtc,
4607                             struct drm_display_mode *adjusted_mode,
4608                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4609                             int num_connectors)
4610 {
4611         struct drm_device *dev = crtc->dev;
4612         struct drm_i915_private *dev_priv = dev->dev_private;
4613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4614         int pipe = intel_crtc->pipe;
4615         u32 dpll;
4616
4617         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4618
4619         dpll = DPLL_VGA_MODE_DIS;
4620
4621         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4622                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4623         } else {
4624                 if (clock->p1 == 2)
4625                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4626                 else
4627                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4628                 if (clock->p2 == 4)
4629                         dpll |= PLL_P2_DIVIDE_BY_4;
4630         }
4631
4632         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4633                 /* XXX: just matching BIOS for now */
4634                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4635                 dpll |= 3;
4636         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4637                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4638                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4639         else
4640                 dpll |= PLL_REF_INPUT_DREFCLK;
4641
4642         dpll |= DPLL_VCO_ENABLE;
4643         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4644         POSTING_READ(DPLL(pipe));
4645         udelay(150);
4646
4647         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4648          * This is an exception to the general rule that mode_set doesn't turn
4649          * things on.
4650          */
4651         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4652                 intel_update_lvds(crtc, clock, adjusted_mode);
4653
4654         I915_WRITE(DPLL(pipe), dpll);
4655
4656         /* Wait for the clocks to stabilize. */
4657         POSTING_READ(DPLL(pipe));
4658         udelay(150);
4659
4660         /* The pixel multiplier can only be updated once the
4661          * DPLL is enabled and the clocks are stable.
4662          *
4663          * So write it again.
4664          */
4665         I915_WRITE(DPLL(pipe), dpll);
4666 }
4667
4668 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4669                                    struct drm_display_mode *mode,
4670                                    struct drm_display_mode *adjusted_mode)
4671 {
4672         struct drm_device *dev = intel_crtc->base.dev;
4673         struct drm_i915_private *dev_priv = dev->dev_private;
4674         enum pipe pipe = intel_crtc->pipe;
4675         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4676         uint32_t vsyncshift;
4677
4678         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4679                 /* the chip adds 2 halflines automatically */
4680                 adjusted_mode->crtc_vtotal -= 1;
4681                 adjusted_mode->crtc_vblank_end -= 1;
4682                 vsyncshift = adjusted_mode->crtc_hsync_start
4683                              - adjusted_mode->crtc_htotal / 2;
4684         } else {
4685                 vsyncshift = 0;
4686         }
4687
4688         if (INTEL_INFO(dev)->gen > 3)
4689                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4690
4691         I915_WRITE(HTOTAL(cpu_transcoder),
4692                    (adjusted_mode->crtc_hdisplay - 1) |
4693                    ((adjusted_mode->crtc_htotal - 1) << 16));
4694         I915_WRITE(HBLANK(cpu_transcoder),
4695                    (adjusted_mode->crtc_hblank_start - 1) |
4696                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4697         I915_WRITE(HSYNC(cpu_transcoder),
4698                    (adjusted_mode->crtc_hsync_start - 1) |
4699                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4700
4701         I915_WRITE(VTOTAL(cpu_transcoder),
4702                    (adjusted_mode->crtc_vdisplay - 1) |
4703                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4704         I915_WRITE(VBLANK(cpu_transcoder),
4705                    (adjusted_mode->crtc_vblank_start - 1) |
4706                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4707         I915_WRITE(VSYNC(cpu_transcoder),
4708                    (adjusted_mode->crtc_vsync_start - 1) |
4709                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4710
4711         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4712          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4713          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4714          * bits. */
4715         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4716             (pipe == PIPE_B || pipe == PIPE_C))
4717                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4718
4719         /* pipesrc controls the size that is scaled from, which should
4720          * always be the user's requested size.
4721          */
4722         I915_WRITE(PIPESRC(pipe),
4723                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4724 }
4725
4726 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4727                               struct drm_display_mode *mode,
4728                               struct drm_display_mode *adjusted_mode,
4729                               int x, int y,
4730                               struct drm_framebuffer *fb)
4731 {
4732         struct drm_device *dev = crtc->dev;
4733         struct drm_i915_private *dev_priv = dev->dev_private;
4734         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4735         int pipe = intel_crtc->pipe;
4736         int plane = intel_crtc->plane;
4737         int refclk, num_connectors = 0;
4738         intel_clock_t clock, reduced_clock;
4739         u32 dspcntr, pipeconf;
4740         bool ok, has_reduced_clock = false, is_sdvo = false;
4741         bool is_lvds = false, is_tv = false, is_dp = false;
4742         struct intel_encoder *encoder;
4743         const intel_limit_t *limit;
4744         int ret;
4745
4746         for_each_encoder_on_crtc(dev, crtc, encoder) {
4747                 switch (encoder->type) {
4748                 case INTEL_OUTPUT_LVDS:
4749                         is_lvds = true;
4750                         break;
4751                 case INTEL_OUTPUT_SDVO:
4752                 case INTEL_OUTPUT_HDMI:
4753                         is_sdvo = true;
4754                         if (encoder->needs_tv_clock)
4755                                 is_tv = true;
4756                         break;
4757                 case INTEL_OUTPUT_TVOUT:
4758                         is_tv = true;
4759                         break;
4760                 case INTEL_OUTPUT_DISPLAYPORT:
4761                         is_dp = true;
4762                         break;
4763                 }
4764
4765                 num_connectors++;
4766         }
4767
4768         refclk = i9xx_get_refclk(crtc, num_connectors);
4769
4770         /*
4771          * Returns a set of divisors for the desired target clock with the given
4772          * refclk, or FALSE.  The returned values represent the clock equation:
4773          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4774          */
4775         limit = intel_limit(crtc, refclk);
4776         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4777                              &clock);
4778         if (!ok) {
4779                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4780                 return -EINVAL;
4781         }
4782
4783         /* Ensure that the cursor is valid for the new mode before changing... */
4784         intel_crtc_update_cursor(crtc, true);
4785
4786         if (is_lvds && dev_priv->lvds_downclock_avail) {
4787                 /*
4788                  * Ensure we match the reduced clock's P to the target clock.
4789                  * If the clocks don't match, we can't switch the display clock
4790                  * by using the FP0/FP1. In such case we will disable the LVDS
4791                  * downclock feature.
4792                 */
4793                 has_reduced_clock = limit->find_pll(limit, crtc,
4794                                                     dev_priv->lvds_downclock,
4795                                                     refclk,
4796                                                     &clock,
4797                                                     &reduced_clock);
4798         }
4799
4800         if (is_sdvo && is_tv)
4801                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4802
4803         if (IS_GEN2(dev))
4804                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4805                                 has_reduced_clock ? &reduced_clock : NULL,
4806                                 num_connectors);
4807         else if (IS_VALLEYVIEW(dev))
4808                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4809                                 has_reduced_clock ? &reduced_clock : NULL,
4810                                 num_connectors);
4811         else
4812                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4813                                 has_reduced_clock ? &reduced_clock : NULL,
4814                                 num_connectors);
4815
4816         /* setup pipeconf */
4817         pipeconf = I915_READ(PIPECONF(pipe));
4818
4819         /* Set up the display plane register */
4820         dspcntr = DISPPLANE_GAMMA_ENABLE;
4821
4822         if (pipe == 0)
4823                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4824         else
4825                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4826
4827         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4828                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4829                  * core speed.
4830                  *
4831                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4832                  * pipe == 0 check?
4833                  */
4834                 if (mode->clock >
4835                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4836                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4837                 else
4838                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4839         }
4840
4841         /* default to 8bpc */
4842         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4843         if (is_dp) {
4844                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4845                         pipeconf |= PIPECONF_BPP_6 |
4846                                     PIPECONF_DITHER_EN |
4847                                     PIPECONF_DITHER_TYPE_SP;
4848                 }
4849         }
4850
4851         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4852                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4853                         pipeconf |= PIPECONF_BPP_6 |
4854                                         PIPECONF_ENABLE |
4855                                         I965_PIPECONF_ACTIVE;
4856                 }
4857         }
4858
4859         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4860         drm_mode_debug_printmodeline(mode);
4861
4862         if (HAS_PIPE_CXSR(dev)) {
4863                 if (intel_crtc->lowfreq_avail) {
4864                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4865                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4866                 } else {
4867                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4868                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4869                 }
4870         }
4871
4872         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4873         if (!IS_GEN2(dev) &&
4874             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4875                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4876         else
4877                 pipeconf |= PIPECONF_PROGRESSIVE;
4878
4879         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4880
4881         /* pipesrc and dspsize control the size that is scaled from,
4882          * which should always be the user's requested size.
4883          */
4884         I915_WRITE(DSPSIZE(plane),
4885                    ((mode->vdisplay - 1) << 16) |
4886                    (mode->hdisplay - 1));
4887         I915_WRITE(DSPPOS(plane), 0);
4888
4889         I915_WRITE(PIPECONF(pipe), pipeconf);
4890         POSTING_READ(PIPECONF(pipe));
4891         intel_enable_pipe(dev_priv, pipe, false);
4892
4893         intel_wait_for_vblank(dev, pipe);
4894
4895         I915_WRITE(DSPCNTR(plane), dspcntr);
4896         POSTING_READ(DSPCNTR(plane));
4897
4898         ret = intel_pipe_set_base(crtc, x, y, fb);
4899
4900         intel_update_watermarks(dev);
4901
4902         return ret;
4903 }
4904
4905 /*
4906  * Initialize reference clocks when the driver loads
4907  */
4908 void ironlake_init_pch_refclk(struct drm_device *dev)
4909 {
4910         struct drm_i915_private *dev_priv = dev->dev_private;
4911         struct drm_mode_config *mode_config = &dev->mode_config;
4912         struct intel_encoder *encoder;
4913         u32 temp;
4914         bool has_lvds = false;
4915         bool has_cpu_edp = false;
4916         bool has_pch_edp = false;
4917         bool has_panel = false;
4918         bool has_ck505 = false;
4919         bool can_ssc = false;
4920
4921         /* We need to take the global config into account */
4922         list_for_each_entry(encoder, &mode_config->encoder_list,
4923                             base.head) {
4924                 switch (encoder->type) {
4925                 case INTEL_OUTPUT_LVDS:
4926                         has_panel = true;
4927                         has_lvds = true;
4928                         break;
4929                 case INTEL_OUTPUT_EDP:
4930                         has_panel = true;
4931                         if (intel_encoder_is_pch_edp(&encoder->base))
4932                                 has_pch_edp = true;
4933                         else
4934                                 has_cpu_edp = true;
4935                         break;
4936                 }
4937         }
4938
4939         if (HAS_PCH_IBX(dev)) {
4940                 has_ck505 = dev_priv->display_clock_mode;
4941                 can_ssc = has_ck505;
4942         } else {
4943                 has_ck505 = false;
4944                 can_ssc = true;
4945         }
4946
4947         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4948                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4949                       has_ck505);
4950
4951         /* Ironlake: try to setup display ref clock before DPLL
4952          * enabling. This is only under driver's control after
4953          * PCH B stepping, previous chipset stepping should be
4954          * ignoring this setting.
4955          */
4956         temp = I915_READ(PCH_DREF_CONTROL);
4957         /* Always enable nonspread source */
4958         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4959
4960         if (has_ck505)
4961                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4962         else
4963                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4964
4965         if (has_panel) {
4966                 temp &= ~DREF_SSC_SOURCE_MASK;
4967                 temp |= DREF_SSC_SOURCE_ENABLE;
4968
4969                 /* SSC must be turned on before enabling the CPU output  */
4970                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4971                         DRM_DEBUG_KMS("Using SSC on panel\n");
4972                         temp |= DREF_SSC1_ENABLE;
4973                 } else
4974                         temp &= ~DREF_SSC1_ENABLE;
4975
4976                 /* Get SSC going before enabling the outputs */
4977                 I915_WRITE(PCH_DREF_CONTROL, temp);
4978                 POSTING_READ(PCH_DREF_CONTROL);
4979                 udelay(200);
4980
4981                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4982
4983                 /* Enable CPU source on CPU attached eDP */
4984                 if (has_cpu_edp) {
4985                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4986                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4987                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4988                         }
4989                         else
4990                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4991                 } else
4992                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4993
4994                 I915_WRITE(PCH_DREF_CONTROL, temp);
4995                 POSTING_READ(PCH_DREF_CONTROL);
4996                 udelay(200);
4997         } else {
4998                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4999
5000                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5001
5002                 /* Turn off CPU output */
5003                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5004
5005                 I915_WRITE(PCH_DREF_CONTROL, temp);
5006                 POSTING_READ(PCH_DREF_CONTROL);
5007                 udelay(200);
5008
5009                 /* Turn off the SSC source */
5010                 temp &= ~DREF_SSC_SOURCE_MASK;
5011                 temp |= DREF_SSC_SOURCE_DISABLE;
5012
5013                 /* Turn off SSC1 */
5014                 temp &= ~ DREF_SSC1_ENABLE;
5015
5016                 I915_WRITE(PCH_DREF_CONTROL, temp);
5017                 POSTING_READ(PCH_DREF_CONTROL);
5018                 udelay(200);
5019         }
5020 }
5021
5022 static int ironlake_get_refclk(struct drm_crtc *crtc)
5023 {
5024         struct drm_device *dev = crtc->dev;
5025         struct drm_i915_private *dev_priv = dev->dev_private;
5026         struct intel_encoder *encoder;
5027         struct intel_encoder *edp_encoder = NULL;
5028         int num_connectors = 0;
5029         bool is_lvds = false;
5030
5031         for_each_encoder_on_crtc(dev, crtc, encoder) {
5032                 switch (encoder->type) {
5033                 case INTEL_OUTPUT_LVDS:
5034                         is_lvds = true;
5035                         break;
5036                 case INTEL_OUTPUT_EDP:
5037                         edp_encoder = encoder;
5038                         break;
5039                 }
5040                 num_connectors++;
5041         }
5042
5043         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5044                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5045                               dev_priv->lvds_ssc_freq);
5046                 return dev_priv->lvds_ssc_freq * 1000;
5047         }
5048
5049         return 120000;
5050 }
5051
5052 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5053                                   struct drm_display_mode *adjusted_mode,
5054                                   bool dither)
5055 {
5056         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5057         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058         int pipe = intel_crtc->pipe;
5059         uint32_t val;
5060
5061         val = I915_READ(PIPECONF(pipe));
5062
5063         val &= ~PIPE_BPC_MASK;
5064         switch (intel_crtc->bpp) {
5065         case 18:
5066                 val |= PIPE_6BPC;
5067                 break;
5068         case 24:
5069                 val |= PIPE_8BPC;
5070                 break;
5071         case 30:
5072                 val |= PIPE_10BPC;
5073                 break;
5074         case 36:
5075                 val |= PIPE_12BPC;
5076                 break;
5077         default:
5078                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5079                 BUG();
5080         }
5081
5082         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5083         if (dither)
5084                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5085
5086         val &= ~PIPECONF_INTERLACE_MASK;
5087         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5088                 val |= PIPECONF_INTERLACED_ILK;
5089         else
5090                 val |= PIPECONF_PROGRESSIVE;
5091
5092         I915_WRITE(PIPECONF(pipe), val);
5093         POSTING_READ(PIPECONF(pipe));
5094 }
5095
5096 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5097                                  struct drm_display_mode *adjusted_mode,
5098                                  bool dither)
5099 {
5100         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5102         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5103         uint32_t val;
5104
5105         val = I915_READ(PIPECONF(cpu_transcoder));
5106
5107         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5108         if (dither)
5109                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5110
5111         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5112         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5113                 val |= PIPECONF_INTERLACED_ILK;
5114         else
5115                 val |= PIPECONF_PROGRESSIVE;
5116
5117         I915_WRITE(PIPECONF(cpu_transcoder), val);
5118         POSTING_READ(PIPECONF(cpu_transcoder));
5119 }
5120
5121 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5122                                     struct drm_display_mode *adjusted_mode,
5123                                     intel_clock_t *clock,
5124                                     bool *has_reduced_clock,
5125                                     intel_clock_t *reduced_clock)
5126 {
5127         struct drm_device *dev = crtc->dev;
5128         struct drm_i915_private *dev_priv = dev->dev_private;
5129         struct intel_encoder *intel_encoder;
5130         int refclk;
5131         const intel_limit_t *limit;
5132         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5133
5134         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5135                 switch (intel_encoder->type) {
5136                 case INTEL_OUTPUT_LVDS:
5137                         is_lvds = true;
5138                         break;
5139                 case INTEL_OUTPUT_SDVO:
5140                 case INTEL_OUTPUT_HDMI:
5141                         is_sdvo = true;
5142                         if (intel_encoder->needs_tv_clock)
5143                                 is_tv = true;
5144                         break;
5145                 case INTEL_OUTPUT_TVOUT:
5146                         is_tv = true;
5147                         break;
5148                 }
5149         }
5150
5151         refclk = ironlake_get_refclk(crtc);
5152
5153         /*
5154          * Returns a set of divisors for the desired target clock with the given
5155          * refclk, or FALSE.  The returned values represent the clock equation:
5156          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5157          */
5158         limit = intel_limit(crtc, refclk);
5159         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5160                               clock);
5161         if (!ret)
5162                 return false;
5163
5164         if (is_lvds && dev_priv->lvds_downclock_avail) {
5165                 /*
5166                  * Ensure we match the reduced clock's P to the target clock.
5167                  * If the clocks don't match, we can't switch the display clock
5168                  * by using the FP0/FP1. In such case we will disable the LVDS
5169                  * downclock feature.
5170                 */
5171                 *has_reduced_clock = limit->find_pll(limit, crtc,
5172                                                      dev_priv->lvds_downclock,
5173                                                      refclk,
5174                                                      clock,
5175                                                      reduced_clock);
5176         }
5177
5178         if (is_sdvo && is_tv)
5179                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5180
5181         return true;
5182 }
5183
5184 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5185 {
5186         struct drm_i915_private *dev_priv = dev->dev_private;
5187         uint32_t temp;
5188
5189         temp = I915_READ(SOUTH_CHICKEN1);
5190         if (temp & FDI_BC_BIFURCATION_SELECT)
5191                 return;
5192
5193         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5194         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5195
5196         temp |= FDI_BC_BIFURCATION_SELECT;
5197         DRM_DEBUG_KMS("enabling fdi C rx\n");
5198         I915_WRITE(SOUTH_CHICKEN1, temp);
5199         POSTING_READ(SOUTH_CHICKEN1);
5200 }
5201
5202 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5203 {
5204         struct drm_device *dev = intel_crtc->base.dev;
5205         struct drm_i915_private *dev_priv = dev->dev_private;
5206         struct intel_crtc *pipe_B_crtc =
5207                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5208
5209         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5210                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5211         if (intel_crtc->fdi_lanes > 4) {
5212                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5213                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5214                 /* Clamp lanes to avoid programming the hw with bogus values. */
5215                 intel_crtc->fdi_lanes = 4;
5216
5217                 return false;
5218         }
5219
5220         if (dev_priv->num_pipe == 2)
5221                 return true;
5222
5223         switch (intel_crtc->pipe) {
5224         case PIPE_A:
5225                 return true;
5226         case PIPE_B:
5227                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5228                     intel_crtc->fdi_lanes > 2) {
5229                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5230                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5231                         /* Clamp lanes to avoid programming the hw with bogus values. */
5232                         intel_crtc->fdi_lanes = 2;
5233
5234                         return false;
5235                 }
5236
5237                 if (intel_crtc->fdi_lanes > 2)
5238                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5239                 else
5240                         cpt_enable_fdi_bc_bifurcation(dev);
5241
5242                 return true;
5243         case PIPE_C:
5244                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5245                         if (intel_crtc->fdi_lanes > 2) {
5246                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5247                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5248                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5249                                 intel_crtc->fdi_lanes = 2;
5250
5251                                 return false;
5252                         }
5253                 } else {
5254                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5255                         return false;
5256                 }
5257
5258                 cpt_enable_fdi_bc_bifurcation(dev);
5259
5260                 return true;
5261         default:
5262                 BUG();
5263         }
5264 }
5265
5266 static void ironlake_set_m_n(struct drm_crtc *crtc,
5267                              struct drm_display_mode *mode,
5268                              struct drm_display_mode *adjusted_mode)
5269 {
5270         struct drm_device *dev = crtc->dev;
5271         struct drm_i915_private *dev_priv = dev->dev_private;
5272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5273         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5274         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5275         struct fdi_m_n m_n = {0};
5276         int target_clock, pixel_multiplier, lane, link_bw;
5277         bool is_dp = false, is_cpu_edp = false;
5278
5279         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5280                 switch (intel_encoder->type) {
5281                 case INTEL_OUTPUT_DISPLAYPORT:
5282                         is_dp = true;
5283                         break;
5284                 case INTEL_OUTPUT_EDP:
5285                         is_dp = true;
5286                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5287                                 is_cpu_edp = true;
5288                         edp_encoder = intel_encoder;
5289                         break;
5290                 }
5291         }
5292
5293         /* FDI link */
5294         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5295         lane = 0;
5296         /* CPU eDP doesn't require FDI link, so just set DP M/N
5297            according to current link config */
5298         if (is_cpu_edp) {
5299                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5300         } else {
5301                 /* FDI is a binary signal running at ~2.7GHz, encoding
5302                  * each output octet as 10 bits. The actual frequency
5303                  * is stored as a divider into a 100MHz clock, and the
5304                  * mode pixel clock is stored in units of 1KHz.
5305                  * Hence the bw of each lane in terms of the mode signal
5306                  * is:
5307                  */
5308                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5309         }
5310
5311         /* [e]DP over FDI requires target mode clock instead of link clock. */
5312         if (edp_encoder)
5313                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5314         else if (is_dp)
5315                 target_clock = mode->clock;
5316         else
5317                 target_clock = adjusted_mode->clock;
5318
5319         if (!lane) {
5320                 /*
5321                  * Account for spread spectrum to avoid
5322                  * oversubscribing the link. Max center spread
5323                  * is 2.5%; use 5% for safety's sake.
5324                  */
5325                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5326                 lane = bps / (link_bw * 8) + 1;
5327         }
5328
5329         intel_crtc->fdi_lanes = lane;
5330
5331         if (pixel_multiplier > 1)
5332                 link_bw *= pixel_multiplier;
5333         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5334                              &m_n);
5335
5336         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5337         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5338         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5339         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5340 }
5341
5342 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5343                                       struct drm_display_mode *adjusted_mode,
5344                                       intel_clock_t *clock, u32 fp)
5345 {
5346         struct drm_crtc *crtc = &intel_crtc->base;
5347         struct drm_device *dev = crtc->dev;
5348         struct drm_i915_private *dev_priv = dev->dev_private;
5349         struct intel_encoder *intel_encoder;
5350         uint32_t dpll;
5351         int factor, pixel_multiplier, num_connectors = 0;
5352         bool is_lvds = false, is_sdvo = false, is_tv = false;
5353         bool is_dp = false, is_cpu_edp = false;
5354
5355         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5356                 switch (intel_encoder->type) {
5357                 case INTEL_OUTPUT_LVDS:
5358                         is_lvds = true;
5359                         break;
5360                 case INTEL_OUTPUT_SDVO:
5361                 case INTEL_OUTPUT_HDMI:
5362                         is_sdvo = true;
5363                         if (intel_encoder->needs_tv_clock)
5364                                 is_tv = true;
5365                         break;
5366                 case INTEL_OUTPUT_TVOUT:
5367                         is_tv = true;
5368                         break;
5369                 case INTEL_OUTPUT_DISPLAYPORT:
5370                         is_dp = true;
5371                         break;
5372                 case INTEL_OUTPUT_EDP:
5373                         is_dp = true;
5374                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5375                                 is_cpu_edp = true;
5376                         break;
5377                 }
5378
5379                 num_connectors++;
5380         }
5381
5382         /* Enable autotuning of the PLL clock (if permissible) */
5383         factor = 21;
5384         if (is_lvds) {
5385                 if ((intel_panel_use_ssc(dev_priv) &&
5386                      dev_priv->lvds_ssc_freq == 100) ||
5387                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5388                         factor = 25;
5389         } else if (is_sdvo && is_tv)
5390                 factor = 20;
5391
5392         if (clock->m < factor * clock->n)
5393                 fp |= FP_CB_TUNE;
5394
5395         dpll = 0;
5396
5397         if (is_lvds)
5398                 dpll |= DPLLB_MODE_LVDS;
5399         else
5400                 dpll |= DPLLB_MODE_DAC_SERIAL;
5401         if (is_sdvo) {
5402                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5403                 if (pixel_multiplier > 1) {
5404                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5405                 }
5406                 dpll |= DPLL_DVO_HIGH_SPEED;
5407         }
5408         if (is_dp && !is_cpu_edp)
5409                 dpll |= DPLL_DVO_HIGH_SPEED;
5410
5411         /* compute bitmask from p1 value */
5412         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5413         /* also FPA1 */
5414         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5415
5416         switch (clock->p2) {
5417         case 5:
5418                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5419                 break;
5420         case 7:
5421                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5422                 break;
5423         case 10:
5424                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5425                 break;
5426         case 14:
5427                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5428                 break;
5429         }
5430
5431         if (is_sdvo && is_tv)
5432                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5433         else if (is_tv)
5434                 /* XXX: just matching BIOS for now */
5435                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5436                 dpll |= 3;
5437         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5438                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5439         else
5440                 dpll |= PLL_REF_INPUT_DREFCLK;
5441
5442         return dpll;
5443 }
5444
5445 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5446                                   struct drm_display_mode *mode,
5447                                   struct drm_display_mode *adjusted_mode,
5448                                   int x, int y,
5449                                   struct drm_framebuffer *fb)
5450 {
5451         struct drm_device *dev = crtc->dev;
5452         struct drm_i915_private *dev_priv = dev->dev_private;
5453         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5454         int pipe = intel_crtc->pipe;
5455         int plane = intel_crtc->plane;
5456         int num_connectors = 0;
5457         intel_clock_t clock, reduced_clock;
5458         u32 dpll, fp = 0, fp2 = 0;
5459         bool ok, has_reduced_clock = false;
5460         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5461         struct intel_encoder *encoder;
5462         u32 temp;
5463         int ret;
5464         bool dither, fdi_config_ok;
5465
5466         for_each_encoder_on_crtc(dev, crtc, encoder) {
5467                 switch (encoder->type) {
5468                 case INTEL_OUTPUT_LVDS:
5469                         is_lvds = true;
5470                         break;
5471                 case INTEL_OUTPUT_DISPLAYPORT:
5472                         is_dp = true;
5473                         break;
5474                 case INTEL_OUTPUT_EDP:
5475                         is_dp = true;
5476                         if (!intel_encoder_is_pch_edp(&encoder->base))
5477                                 is_cpu_edp = true;
5478                         break;
5479                 }
5480
5481                 num_connectors++;
5482         }
5483
5484         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5485              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5486
5487         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5488                                      &has_reduced_clock, &reduced_clock);
5489         if (!ok) {
5490                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5491                 return -EINVAL;
5492         }
5493
5494         /* Ensure that the cursor is valid for the new mode before changing... */
5495         intel_crtc_update_cursor(crtc, true);
5496
5497         /* determine panel color depth */
5498         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5499                                               adjusted_mode);
5500         if (is_lvds && dev_priv->lvds_dither)
5501                 dither = true;
5502
5503         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5504         if (has_reduced_clock)
5505                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5506                         reduced_clock.m2;
5507
5508         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5509
5510         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5511         drm_mode_debug_printmodeline(mode);
5512
5513         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5514         if (!is_cpu_edp) {
5515                 struct intel_pch_pll *pll;
5516
5517                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5518                 if (pll == NULL) {
5519                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5520                                          pipe);
5521                         return -EINVAL;
5522                 }
5523         } else
5524                 intel_put_pch_pll(intel_crtc);
5525
5526         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5527          * This is an exception to the general rule that mode_set doesn't turn
5528          * things on.
5529          */
5530         if (is_lvds) {
5531                 temp = I915_READ(PCH_LVDS);
5532                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5533                 if (HAS_PCH_CPT(dev)) {
5534                         temp &= ~PORT_TRANS_SEL_MASK;
5535                         temp |= PORT_TRANS_SEL_CPT(pipe);
5536                 } else {
5537                         if (pipe == 1)
5538                                 temp |= LVDS_PIPEB_SELECT;
5539                         else
5540                                 temp &= ~LVDS_PIPEB_SELECT;
5541                 }
5542
5543                 /* set the corresponsding LVDS_BORDER bit */
5544                 temp |= dev_priv->lvds_border_bits;
5545                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5546                  * set the DPLLs for dual-channel mode or not.
5547                  */
5548                 if (clock.p2 == 7)
5549                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5550                 else
5551                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5552
5553                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5554                  * appropriately here, but we need to look more thoroughly into how
5555                  * panels behave in the two modes.
5556                  */
5557                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5558                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5559                         temp |= LVDS_HSYNC_POLARITY;
5560                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5561                         temp |= LVDS_VSYNC_POLARITY;
5562                 I915_WRITE(PCH_LVDS, temp);
5563         }
5564
5565         if (is_dp && !is_cpu_edp) {
5566                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5567         } else {
5568                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5569                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5570                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5571                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5572                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5573         }
5574
5575         if (intel_crtc->pch_pll) {
5576                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5577
5578                 /* Wait for the clocks to stabilize. */
5579                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5580                 udelay(150);
5581
5582                 /* The pixel multiplier can only be updated once the
5583                  * DPLL is enabled and the clocks are stable.
5584                  *
5585                  * So write it again.
5586                  */
5587                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5588         }
5589
5590         intel_crtc->lowfreq_avail = false;
5591         if (intel_crtc->pch_pll) {
5592                 if (is_lvds && has_reduced_clock && i915_powersave) {
5593                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5594                         intel_crtc->lowfreq_avail = true;
5595                 } else {
5596                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5597                 }
5598         }
5599
5600         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5601
5602         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5603          * ironlake_check_fdi_lanes. */
5604         ironlake_set_m_n(crtc, mode, adjusted_mode);
5605
5606         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5607
5608         if (is_cpu_edp)
5609                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5610
5611         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5612
5613         intel_wait_for_vblank(dev, pipe);
5614
5615         /* Set up the display plane register */
5616         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5617         POSTING_READ(DSPCNTR(plane));
5618
5619         ret = intel_pipe_set_base(crtc, x, y, fb);
5620
5621         intel_update_watermarks(dev);
5622
5623         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5624
5625         return fdi_config_ok ? ret : -EINVAL;
5626 }
5627
5628 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5629                                  struct drm_display_mode *mode,
5630                                  struct drm_display_mode *adjusted_mode,
5631                                  int x, int y,
5632                                  struct drm_framebuffer *fb)
5633 {
5634         struct drm_device *dev = crtc->dev;
5635         struct drm_i915_private *dev_priv = dev->dev_private;
5636         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5637         int pipe = intel_crtc->pipe;
5638         int plane = intel_crtc->plane;
5639         int num_connectors = 0;
5640         intel_clock_t clock, reduced_clock;
5641         u32 dpll = 0, fp = 0, fp2 = 0;
5642         bool ok, has_reduced_clock = false;
5643         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5644         struct intel_encoder *encoder;
5645         u32 temp;
5646         int ret;
5647         bool dither;
5648
5649         for_each_encoder_on_crtc(dev, crtc, encoder) {
5650                 switch (encoder->type) {
5651                 case INTEL_OUTPUT_LVDS:
5652                         is_lvds = true;
5653                         break;
5654                 case INTEL_OUTPUT_DISPLAYPORT:
5655                         is_dp = true;
5656                         break;
5657                 case INTEL_OUTPUT_EDP:
5658                         is_dp = true;
5659                         if (!intel_encoder_is_pch_edp(&encoder->base))
5660                                 is_cpu_edp = true;
5661                         break;
5662                 }
5663
5664                 num_connectors++;
5665         }
5666
5667         if (is_cpu_edp)
5668                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5669         else
5670                 intel_crtc->cpu_transcoder = pipe;
5671
5672         /* We are not sure yet this won't happen. */
5673         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5674              INTEL_PCH_TYPE(dev));
5675
5676         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5677              num_connectors, pipe_name(pipe));
5678
5679         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5680                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5681
5682         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5683
5684         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5685                 return -EINVAL;
5686
5687         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5688                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5689                                              &has_reduced_clock,
5690                                              &reduced_clock);
5691                 if (!ok) {
5692                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5693                         return -EINVAL;
5694                 }
5695         }
5696
5697         /* Ensure that the cursor is valid for the new mode before changing... */
5698         intel_crtc_update_cursor(crtc, true);
5699
5700         /* determine panel color depth */
5701         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5702                                               adjusted_mode);
5703         if (is_lvds && dev_priv->lvds_dither)
5704                 dither = true;
5705
5706         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5707         drm_mode_debug_printmodeline(mode);
5708
5709         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5710                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5711                 if (has_reduced_clock)
5712                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5713                               reduced_clock.m2;
5714
5715                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5716                                              fp);
5717
5718                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5719                  * own on pre-Haswell/LPT generation */
5720                 if (!is_cpu_edp) {
5721                         struct intel_pch_pll *pll;
5722
5723                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5724                         if (pll == NULL) {
5725                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5726                                                  pipe);
5727                                 return -EINVAL;
5728                         }
5729                 } else
5730                         intel_put_pch_pll(intel_crtc);
5731
5732                 /* The LVDS pin pair needs to be on before the DPLLs are
5733                  * enabled.  This is an exception to the general rule that
5734                  * mode_set doesn't turn things on.
5735                  */
5736                 if (is_lvds) {
5737                         temp = I915_READ(PCH_LVDS);
5738                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5739                         if (HAS_PCH_CPT(dev)) {
5740                                 temp &= ~PORT_TRANS_SEL_MASK;
5741                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5742                         } else {
5743                                 if (pipe == 1)
5744                                         temp |= LVDS_PIPEB_SELECT;
5745                                 else
5746                                         temp &= ~LVDS_PIPEB_SELECT;
5747                         }
5748
5749                         /* set the corresponsding LVDS_BORDER bit */
5750                         temp |= dev_priv->lvds_border_bits;
5751                         /* Set the B0-B3 data pairs corresponding to whether
5752                          * we're going to set the DPLLs for dual-channel mode or
5753                          * not.
5754                          */
5755                         if (clock.p2 == 7)
5756                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5757                         else
5758                                 temp &= ~(LVDS_B0B3_POWER_UP |
5759                                           LVDS_CLKB_POWER_UP);
5760
5761                         /* It would be nice to set 24 vs 18-bit mode
5762                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5763                          * look more thoroughly into how panels behave in the
5764                          * two modes.
5765                          */
5766                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5767                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5768                                 temp |= LVDS_HSYNC_POLARITY;
5769                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5770                                 temp |= LVDS_VSYNC_POLARITY;
5771                         I915_WRITE(PCH_LVDS, temp);
5772                 }
5773         }
5774
5775         if (is_dp && !is_cpu_edp) {
5776                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5777         } else {
5778                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5779                         /* For non-DP output, clear any trans DP clock recovery
5780                          * setting.*/
5781                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5782                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5783                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5784                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5785                 }
5786         }
5787
5788         intel_crtc->lowfreq_avail = false;
5789         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5790                 if (intel_crtc->pch_pll) {
5791                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5792
5793                         /* Wait for the clocks to stabilize. */
5794                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5795                         udelay(150);
5796
5797                         /* The pixel multiplier can only be updated once the
5798                          * DPLL is enabled and the clocks are stable.
5799                          *
5800                          * So write it again.
5801                          */
5802                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5803                 }
5804
5805                 if (intel_crtc->pch_pll) {
5806                         if (is_lvds && has_reduced_clock && i915_powersave) {
5807                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5808                                 intel_crtc->lowfreq_avail = true;
5809                         } else {
5810                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5811                         }
5812                 }
5813         }
5814
5815         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5816
5817         if (!is_dp || is_cpu_edp)
5818                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5819
5820         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5821                 if (is_cpu_edp)
5822                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5823
5824         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5825
5826         /* Set up the display plane register */
5827         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5828         POSTING_READ(DSPCNTR(plane));
5829
5830         ret = intel_pipe_set_base(crtc, x, y, fb);
5831
5832         intel_update_watermarks(dev);
5833
5834         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5835
5836         return ret;
5837 }
5838
5839 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5840                                struct drm_display_mode *mode,
5841                                struct drm_display_mode *adjusted_mode,
5842                                int x, int y,
5843                                struct drm_framebuffer *fb)
5844 {
5845         struct drm_device *dev = crtc->dev;
5846         struct drm_i915_private *dev_priv = dev->dev_private;
5847         struct drm_encoder_helper_funcs *encoder_funcs;
5848         struct intel_encoder *encoder;
5849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5850         int pipe = intel_crtc->pipe;
5851         int ret;
5852
5853         drm_vblank_pre_modeset(dev, pipe);
5854
5855         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5856                                               x, y, fb);
5857         drm_vblank_post_modeset(dev, pipe);
5858
5859         if (ret != 0)
5860                 return ret;
5861
5862         for_each_encoder_on_crtc(dev, crtc, encoder) {
5863                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5864                         encoder->base.base.id,
5865                         drm_get_encoder_name(&encoder->base),
5866                         mode->base.id, mode->name);
5867                 encoder_funcs = encoder->base.helper_private;
5868                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5869         }
5870
5871         return 0;
5872 }
5873
5874 static bool intel_eld_uptodate(struct drm_connector *connector,
5875                                int reg_eldv, uint32_t bits_eldv,
5876                                int reg_elda, uint32_t bits_elda,
5877                                int reg_edid)
5878 {
5879         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5880         uint8_t *eld = connector->eld;
5881         uint32_t i;
5882
5883         i = I915_READ(reg_eldv);
5884         i &= bits_eldv;
5885
5886         if (!eld[0])
5887                 return !i;
5888
5889         if (!i)
5890                 return false;
5891
5892         i = I915_READ(reg_elda);
5893         i &= ~bits_elda;
5894         I915_WRITE(reg_elda, i);
5895
5896         for (i = 0; i < eld[2]; i++)
5897                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5898                         return false;
5899
5900         return true;
5901 }
5902
5903 static void g4x_write_eld(struct drm_connector *connector,
5904                           struct drm_crtc *crtc)
5905 {
5906         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5907         uint8_t *eld = connector->eld;
5908         uint32_t eldv;
5909         uint32_t len;
5910         uint32_t i;
5911
5912         i = I915_READ(G4X_AUD_VID_DID);
5913
5914         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5915                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5916         else
5917                 eldv = G4X_ELDV_DEVCTG;
5918
5919         if (intel_eld_uptodate(connector,
5920                                G4X_AUD_CNTL_ST, eldv,
5921                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5922                                G4X_HDMIW_HDMIEDID))
5923                 return;
5924
5925         i = I915_READ(G4X_AUD_CNTL_ST);
5926         i &= ~(eldv | G4X_ELD_ADDR);
5927         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5928         I915_WRITE(G4X_AUD_CNTL_ST, i);
5929
5930         if (!eld[0])
5931                 return;
5932
5933         len = min_t(uint8_t, eld[2], len);
5934         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5935         for (i = 0; i < len; i++)
5936                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5937
5938         i = I915_READ(G4X_AUD_CNTL_ST);
5939         i |= eldv;
5940         I915_WRITE(G4X_AUD_CNTL_ST, i);
5941 }
5942
5943 static void haswell_write_eld(struct drm_connector *connector,
5944                                      struct drm_crtc *crtc)
5945 {
5946         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5947         uint8_t *eld = connector->eld;
5948         struct drm_device *dev = crtc->dev;
5949         uint32_t eldv;
5950         uint32_t i;
5951         int len;
5952         int pipe = to_intel_crtc(crtc)->pipe;
5953         int tmp;
5954
5955         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5956         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5957         int aud_config = HSW_AUD_CFG(pipe);
5958         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5959
5960
5961         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5962
5963         /* Audio output enable */
5964         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5965         tmp = I915_READ(aud_cntrl_st2);
5966         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5967         I915_WRITE(aud_cntrl_st2, tmp);
5968
5969         /* Wait for 1 vertical blank */
5970         intel_wait_for_vblank(dev, pipe);
5971
5972         /* Set ELD valid state */
5973         tmp = I915_READ(aud_cntrl_st2);
5974         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5975         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5976         I915_WRITE(aud_cntrl_st2, tmp);
5977         tmp = I915_READ(aud_cntrl_st2);
5978         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5979
5980         /* Enable HDMI mode */
5981         tmp = I915_READ(aud_config);
5982         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5983         /* clear N_programing_enable and N_value_index */
5984         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5985         I915_WRITE(aud_config, tmp);
5986
5987         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5988
5989         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5990
5991         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5992                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5993                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5994                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5995         } else
5996                 I915_WRITE(aud_config, 0);
5997
5998         if (intel_eld_uptodate(connector,
5999                                aud_cntrl_st2, eldv,
6000                                aud_cntl_st, IBX_ELD_ADDRESS,
6001                                hdmiw_hdmiedid))
6002                 return;
6003
6004         i = I915_READ(aud_cntrl_st2);
6005         i &= ~eldv;
6006         I915_WRITE(aud_cntrl_st2, i);
6007
6008         if (!eld[0])
6009                 return;
6010
6011         i = I915_READ(aud_cntl_st);
6012         i &= ~IBX_ELD_ADDRESS;
6013         I915_WRITE(aud_cntl_st, i);
6014         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6015         DRM_DEBUG_DRIVER("port num:%d\n", i);
6016
6017         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6018         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6019         for (i = 0; i < len; i++)
6020                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6021
6022         i = I915_READ(aud_cntrl_st2);
6023         i |= eldv;
6024         I915_WRITE(aud_cntrl_st2, i);
6025
6026 }
6027
6028 static void ironlake_write_eld(struct drm_connector *connector,
6029                                      struct drm_crtc *crtc)
6030 {
6031         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6032         uint8_t *eld = connector->eld;
6033         uint32_t eldv;
6034         uint32_t i;
6035         int len;
6036         int hdmiw_hdmiedid;
6037         int aud_config;
6038         int aud_cntl_st;
6039         int aud_cntrl_st2;
6040         int pipe = to_intel_crtc(crtc)->pipe;
6041
6042         if (HAS_PCH_IBX(connector->dev)) {
6043                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6044                 aud_config = IBX_AUD_CFG(pipe);
6045                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6046                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6047         } else {
6048                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6049                 aud_config = CPT_AUD_CFG(pipe);
6050                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6051                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6052         }
6053
6054         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6055
6056         i = I915_READ(aud_cntl_st);
6057         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6058         if (!i) {
6059                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6060                 /* operate blindly on all ports */
6061                 eldv = IBX_ELD_VALIDB;
6062                 eldv |= IBX_ELD_VALIDB << 4;
6063                 eldv |= IBX_ELD_VALIDB << 8;
6064         } else {
6065                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6066                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6067         }
6068
6069         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6070                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6071                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6072                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6073         } else
6074                 I915_WRITE(aud_config, 0);
6075
6076         if (intel_eld_uptodate(connector,
6077                                aud_cntrl_st2, eldv,
6078                                aud_cntl_st, IBX_ELD_ADDRESS,
6079                                hdmiw_hdmiedid))
6080                 return;
6081
6082         i = I915_READ(aud_cntrl_st2);
6083         i &= ~eldv;
6084         I915_WRITE(aud_cntrl_st2, i);
6085
6086         if (!eld[0])
6087                 return;
6088
6089         i = I915_READ(aud_cntl_st);
6090         i &= ~IBX_ELD_ADDRESS;
6091         I915_WRITE(aud_cntl_st, i);
6092
6093         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6094         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6095         for (i = 0; i < len; i++)
6096                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6097
6098         i = I915_READ(aud_cntrl_st2);
6099         i |= eldv;
6100         I915_WRITE(aud_cntrl_st2, i);
6101 }
6102
6103 void intel_write_eld(struct drm_encoder *encoder,
6104                      struct drm_display_mode *mode)
6105 {
6106         struct drm_crtc *crtc = encoder->crtc;
6107         struct drm_connector *connector;
6108         struct drm_device *dev = encoder->dev;
6109         struct drm_i915_private *dev_priv = dev->dev_private;
6110
6111         connector = drm_select_eld(encoder, mode);
6112         if (!connector)
6113                 return;
6114
6115         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6116                          connector->base.id,
6117                          drm_get_connector_name(connector),
6118                          connector->encoder->base.id,
6119                          drm_get_encoder_name(connector->encoder));
6120
6121         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6122
6123         if (dev_priv->display.write_eld)
6124                 dev_priv->display.write_eld(connector, crtc);
6125 }
6126
6127 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6128 void intel_crtc_load_lut(struct drm_crtc *crtc)
6129 {
6130         struct drm_device *dev = crtc->dev;
6131         struct drm_i915_private *dev_priv = dev->dev_private;
6132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133         int palreg = PALETTE(intel_crtc->pipe);
6134         int i;
6135
6136         /* The clocks have to be on to load the palette. */
6137         if (!crtc->enabled || !intel_crtc->active)
6138                 return;
6139
6140         /* use legacy palette for Ironlake */
6141         if (HAS_PCH_SPLIT(dev))
6142                 palreg = LGC_PALETTE(intel_crtc->pipe);
6143
6144         for (i = 0; i < 256; i++) {
6145                 I915_WRITE(palreg + 4 * i,
6146                            (intel_crtc->lut_r[i] << 16) |
6147                            (intel_crtc->lut_g[i] << 8) |
6148                            intel_crtc->lut_b[i]);
6149         }
6150 }
6151
6152 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6153 {
6154         struct drm_device *dev = crtc->dev;
6155         struct drm_i915_private *dev_priv = dev->dev_private;
6156         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157         bool visible = base != 0;
6158         u32 cntl;
6159
6160         if (intel_crtc->cursor_visible == visible)
6161                 return;
6162
6163         cntl = I915_READ(_CURACNTR);
6164         if (visible) {
6165                 /* On these chipsets we can only modify the base whilst
6166                  * the cursor is disabled.
6167                  */
6168                 I915_WRITE(_CURABASE, base);
6169
6170                 cntl &= ~(CURSOR_FORMAT_MASK);
6171                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6172                 cntl |= CURSOR_ENABLE |
6173                         CURSOR_GAMMA_ENABLE |
6174                         CURSOR_FORMAT_ARGB;
6175         } else
6176                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6177         I915_WRITE(_CURACNTR, cntl);
6178
6179         intel_crtc->cursor_visible = visible;
6180 }
6181
6182 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6183 {
6184         struct drm_device *dev = crtc->dev;
6185         struct drm_i915_private *dev_priv = dev->dev_private;
6186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6187         int pipe = intel_crtc->pipe;
6188         bool visible = base != 0;
6189
6190         if (intel_crtc->cursor_visible != visible) {
6191                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6192                 if (base) {
6193                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6194                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6195                         cntl |= pipe << 28; /* Connect to correct pipe */
6196                 } else {
6197                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6198                         cntl |= CURSOR_MODE_DISABLE;
6199                 }
6200                 I915_WRITE(CURCNTR(pipe), cntl);
6201
6202                 intel_crtc->cursor_visible = visible;
6203         }
6204         /* and commit changes on next vblank */
6205         I915_WRITE(CURBASE(pipe), base);
6206 }
6207
6208 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6209 {
6210         struct drm_device *dev = crtc->dev;
6211         struct drm_i915_private *dev_priv = dev->dev_private;
6212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6213         int pipe = intel_crtc->pipe;
6214         bool visible = base != 0;
6215
6216         if (intel_crtc->cursor_visible != visible) {
6217                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6218                 if (base) {
6219                         cntl &= ~CURSOR_MODE;
6220                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6221                 } else {
6222                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6223                         cntl |= CURSOR_MODE_DISABLE;
6224                 }
6225                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6226
6227                 intel_crtc->cursor_visible = visible;
6228         }
6229         /* and commit changes on next vblank */
6230         I915_WRITE(CURBASE_IVB(pipe), base);
6231 }
6232
6233 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6234 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6235                                      bool on)
6236 {
6237         struct drm_device *dev = crtc->dev;
6238         struct drm_i915_private *dev_priv = dev->dev_private;
6239         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6240         int pipe = intel_crtc->pipe;
6241         int x = intel_crtc->cursor_x;
6242         int y = intel_crtc->cursor_y;
6243         u32 base, pos;
6244         bool visible;
6245
6246         pos = 0;
6247
6248         if (on && crtc->enabled && crtc->fb) {
6249                 base = intel_crtc->cursor_addr;
6250                 if (x > (int) crtc->fb->width)
6251                         base = 0;
6252
6253                 if (y > (int) crtc->fb->height)
6254                         base = 0;
6255         } else
6256                 base = 0;
6257
6258         if (x < 0) {
6259                 if (x + intel_crtc->cursor_width < 0)
6260                         base = 0;
6261
6262                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6263                 x = -x;
6264         }
6265         pos |= x << CURSOR_X_SHIFT;
6266
6267         if (y < 0) {
6268                 if (y + intel_crtc->cursor_height < 0)
6269                         base = 0;
6270
6271                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6272                 y = -y;
6273         }
6274         pos |= y << CURSOR_Y_SHIFT;
6275
6276         visible = base != 0;
6277         if (!visible && !intel_crtc->cursor_visible)
6278                 return;
6279
6280         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6281                 I915_WRITE(CURPOS_IVB(pipe), pos);
6282                 ivb_update_cursor(crtc, base);
6283         } else {
6284                 I915_WRITE(CURPOS(pipe), pos);
6285                 if (IS_845G(dev) || IS_I865G(dev))
6286                         i845_update_cursor(crtc, base);
6287                 else
6288                         i9xx_update_cursor(crtc, base);
6289         }
6290 }
6291
6292 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6293                                  struct drm_file *file,
6294                                  uint32_t handle,
6295                                  uint32_t width, uint32_t height)
6296 {
6297         struct drm_device *dev = crtc->dev;
6298         struct drm_i915_private *dev_priv = dev->dev_private;
6299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6300         struct drm_i915_gem_object *obj;
6301         uint32_t addr;
6302         int ret;
6303
6304         /* if we want to turn off the cursor ignore width and height */
6305         if (!handle) {
6306                 DRM_DEBUG_KMS("cursor off\n");
6307                 addr = 0;
6308                 obj = NULL;
6309                 mutex_lock(&dev->struct_mutex);
6310                 goto finish;
6311         }
6312
6313         /* Currently we only support 64x64 cursors */
6314         if (width != 64 || height != 64) {
6315                 DRM_ERROR("we currently only support 64x64 cursors\n");
6316                 return -EINVAL;
6317         }
6318
6319         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6320         if (&obj->base == NULL)
6321                 return -ENOENT;
6322
6323         if (obj->base.size < width * height * 4) {
6324                 DRM_ERROR("buffer is to small\n");
6325                 ret = -ENOMEM;
6326                 goto fail;
6327         }
6328
6329         /* we only need to pin inside GTT if cursor is non-phy */
6330         mutex_lock(&dev->struct_mutex);
6331         if (!dev_priv->info->cursor_needs_physical) {
6332                 if (obj->tiling_mode) {
6333                         DRM_ERROR("cursor cannot be tiled\n");
6334                         ret = -EINVAL;
6335                         goto fail_locked;
6336                 }
6337
6338                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6339                 if (ret) {
6340                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6341                         goto fail_locked;
6342                 }
6343
6344                 ret = i915_gem_object_put_fence(obj);
6345                 if (ret) {
6346                         DRM_ERROR("failed to release fence for cursor");
6347                         goto fail_unpin;
6348                 }
6349
6350                 addr = obj->gtt_offset;
6351         } else {
6352                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6353                 ret = i915_gem_attach_phys_object(dev, obj,
6354                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6355                                                   align);
6356                 if (ret) {
6357                         DRM_ERROR("failed to attach phys object\n");
6358                         goto fail_locked;
6359                 }
6360                 addr = obj->phys_obj->handle->busaddr;
6361         }
6362
6363         if (IS_GEN2(dev))
6364                 I915_WRITE(CURSIZE, (height << 12) | width);
6365
6366  finish:
6367         if (intel_crtc->cursor_bo) {
6368                 if (dev_priv->info->cursor_needs_physical) {
6369                         if (intel_crtc->cursor_bo != obj)
6370                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6371                 } else
6372                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6373                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6374         }
6375
6376         mutex_unlock(&dev->struct_mutex);
6377
6378         intel_crtc->cursor_addr = addr;
6379         intel_crtc->cursor_bo = obj;
6380         intel_crtc->cursor_width = width;
6381         intel_crtc->cursor_height = height;
6382
6383         intel_crtc_update_cursor(crtc, true);
6384
6385         return 0;
6386 fail_unpin:
6387         i915_gem_object_unpin(obj);
6388 fail_locked:
6389         mutex_unlock(&dev->struct_mutex);
6390 fail:
6391         drm_gem_object_unreference_unlocked(&obj->base);
6392         return ret;
6393 }
6394
6395 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6396 {
6397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398
6399         intel_crtc->cursor_x = x;
6400         intel_crtc->cursor_y = y;
6401
6402         intel_crtc_update_cursor(crtc, true);
6403
6404         return 0;
6405 }
6406
6407 /** Sets the color ramps on behalf of RandR */
6408 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6409                                  u16 blue, int regno)
6410 {
6411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6412
6413         intel_crtc->lut_r[regno] = red >> 8;
6414         intel_crtc->lut_g[regno] = green >> 8;
6415         intel_crtc->lut_b[regno] = blue >> 8;
6416 }
6417
6418 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6419                              u16 *blue, int regno)
6420 {
6421         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422
6423         *red = intel_crtc->lut_r[regno] << 8;
6424         *green = intel_crtc->lut_g[regno] << 8;
6425         *blue = intel_crtc->lut_b[regno] << 8;
6426 }
6427
6428 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6429                                  u16 *blue, uint32_t start, uint32_t size)
6430 {
6431         int end = (start + size > 256) ? 256 : start + size, i;
6432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433
6434         for (i = start; i < end; i++) {
6435                 intel_crtc->lut_r[i] = red[i] >> 8;
6436                 intel_crtc->lut_g[i] = green[i] >> 8;
6437                 intel_crtc->lut_b[i] = blue[i] >> 8;
6438         }
6439
6440         intel_crtc_load_lut(crtc);
6441 }
6442
6443 /**
6444  * Get a pipe with a simple mode set on it for doing load-based monitor
6445  * detection.
6446  *
6447  * It will be up to the load-detect code to adjust the pipe as appropriate for
6448  * its requirements.  The pipe will be connected to no other encoders.
6449  *
6450  * Currently this code will only succeed if there is a pipe with no encoders
6451  * configured for it.  In the future, it could choose to temporarily disable
6452  * some outputs to free up a pipe for its use.
6453  *
6454  * \return crtc, or NULL if no pipes are available.
6455  */
6456
6457 /* VESA 640x480x72Hz mode to set on the pipe */
6458 static struct drm_display_mode load_detect_mode = {
6459         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6460                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6461 };
6462
6463 static struct drm_framebuffer *
6464 intel_framebuffer_create(struct drm_device *dev,
6465                          struct drm_mode_fb_cmd2 *mode_cmd,
6466                          struct drm_i915_gem_object *obj)
6467 {
6468         struct intel_framebuffer *intel_fb;
6469         int ret;
6470
6471         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6472         if (!intel_fb) {
6473                 drm_gem_object_unreference_unlocked(&obj->base);
6474                 return ERR_PTR(-ENOMEM);
6475         }
6476
6477         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6478         if (ret) {
6479                 drm_gem_object_unreference_unlocked(&obj->base);
6480                 kfree(intel_fb);
6481                 return ERR_PTR(ret);
6482         }
6483
6484         return &intel_fb->base;
6485 }
6486
6487 static u32
6488 intel_framebuffer_pitch_for_width(int width, int bpp)
6489 {
6490         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6491         return ALIGN(pitch, 64);
6492 }
6493
6494 static u32
6495 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6496 {
6497         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6498         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6499 }
6500
6501 static struct drm_framebuffer *
6502 intel_framebuffer_create_for_mode(struct drm_device *dev,
6503                                   struct drm_display_mode *mode,
6504                                   int depth, int bpp)
6505 {
6506         struct drm_i915_gem_object *obj;
6507         struct drm_mode_fb_cmd2 mode_cmd;
6508
6509         obj = i915_gem_alloc_object(dev,
6510                                     intel_framebuffer_size_for_mode(mode, bpp));
6511         if (obj == NULL)
6512                 return ERR_PTR(-ENOMEM);
6513
6514         mode_cmd.width = mode->hdisplay;
6515         mode_cmd.height = mode->vdisplay;
6516         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6517                                                                 bpp);
6518         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6519
6520         return intel_framebuffer_create(dev, &mode_cmd, obj);
6521 }
6522
6523 static struct drm_framebuffer *
6524 mode_fits_in_fbdev(struct drm_device *dev,
6525                    struct drm_display_mode *mode)
6526 {
6527         struct drm_i915_private *dev_priv = dev->dev_private;
6528         struct drm_i915_gem_object *obj;
6529         struct drm_framebuffer *fb;
6530
6531         if (dev_priv->fbdev == NULL)
6532                 return NULL;
6533
6534         obj = dev_priv->fbdev->ifb.obj;
6535         if (obj == NULL)
6536                 return NULL;
6537
6538         fb = &dev_priv->fbdev->ifb.base;
6539         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6540                                                                fb->bits_per_pixel))
6541                 return NULL;
6542
6543         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6544                 return NULL;
6545
6546         return fb;
6547 }
6548
6549 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6550                                 struct drm_display_mode *mode,
6551                                 struct intel_load_detect_pipe *old)
6552 {
6553         struct intel_crtc *intel_crtc;
6554         struct intel_encoder *intel_encoder =
6555                 intel_attached_encoder(connector);
6556         struct drm_crtc *possible_crtc;
6557         struct drm_encoder *encoder = &intel_encoder->base;
6558         struct drm_crtc *crtc = NULL;
6559         struct drm_device *dev = encoder->dev;
6560         struct drm_framebuffer *fb;
6561         int i = -1;
6562
6563         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6564                       connector->base.id, drm_get_connector_name(connector),
6565                       encoder->base.id, drm_get_encoder_name(encoder));
6566
6567         /*
6568          * Algorithm gets a little messy:
6569          *
6570          *   - if the connector already has an assigned crtc, use it (but make
6571          *     sure it's on first)
6572          *
6573          *   - try to find the first unused crtc that can drive this connector,
6574          *     and use that if we find one
6575          */
6576
6577         /* See if we already have a CRTC for this connector */
6578         if (encoder->crtc) {
6579                 crtc = encoder->crtc;
6580
6581                 old->dpms_mode = connector->dpms;
6582                 old->load_detect_temp = false;
6583
6584                 /* Make sure the crtc and connector are running */
6585                 if (connector->dpms != DRM_MODE_DPMS_ON)
6586                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6587
6588                 return true;
6589         }
6590
6591         /* Find an unused one (if possible) */
6592         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6593                 i++;
6594                 if (!(encoder->possible_crtcs & (1 << i)))
6595                         continue;
6596                 if (!possible_crtc->enabled) {
6597                         crtc = possible_crtc;
6598                         break;
6599                 }
6600         }
6601
6602         /*
6603          * If we didn't find an unused CRTC, don't use any.
6604          */
6605         if (!crtc) {
6606                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6607                 return false;
6608         }
6609
6610         intel_encoder->new_crtc = to_intel_crtc(crtc);
6611         to_intel_connector(connector)->new_encoder = intel_encoder;
6612
6613         intel_crtc = to_intel_crtc(crtc);
6614         old->dpms_mode = connector->dpms;
6615         old->load_detect_temp = true;
6616         old->release_fb = NULL;
6617
6618         if (!mode)
6619                 mode = &load_detect_mode;
6620
6621         /* We need a framebuffer large enough to accommodate all accesses
6622          * that the plane may generate whilst we perform load detection.
6623          * We can not rely on the fbcon either being present (we get called
6624          * during its initialisation to detect all boot displays, or it may
6625          * not even exist) or that it is large enough to satisfy the
6626          * requested mode.
6627          */
6628         fb = mode_fits_in_fbdev(dev, mode);
6629         if (fb == NULL) {
6630                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6631                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6632                 old->release_fb = fb;
6633         } else
6634                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6635         if (IS_ERR(fb)) {
6636                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6637                 goto fail;
6638         }
6639
6640         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6641                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6642                 if (old->release_fb)
6643                         old->release_fb->funcs->destroy(old->release_fb);
6644                 goto fail;
6645         }
6646
6647         /* let the connector get through one full cycle before testing */
6648         intel_wait_for_vblank(dev, intel_crtc->pipe);
6649
6650         return true;
6651 fail:
6652         connector->encoder = NULL;
6653         encoder->crtc = NULL;
6654         return false;
6655 }
6656
6657 void intel_release_load_detect_pipe(struct drm_connector *connector,
6658                                     struct intel_load_detect_pipe *old)
6659 {
6660         struct intel_encoder *intel_encoder =
6661                 intel_attached_encoder(connector);
6662         struct drm_encoder *encoder = &intel_encoder->base;
6663
6664         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6665                       connector->base.id, drm_get_connector_name(connector),
6666                       encoder->base.id, drm_get_encoder_name(encoder));
6667
6668         if (old->load_detect_temp) {
6669                 struct drm_crtc *crtc = encoder->crtc;
6670
6671                 to_intel_connector(connector)->new_encoder = NULL;
6672                 intel_encoder->new_crtc = NULL;
6673                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6674
6675                 if (old->release_fb)
6676                         old->release_fb->funcs->destroy(old->release_fb);
6677
6678                 return;
6679         }
6680
6681         /* Switch crtc and encoder back off if necessary */
6682         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6683                 connector->funcs->dpms(connector, old->dpms_mode);
6684 }
6685
6686 /* Returns the clock of the currently programmed mode of the given pipe. */
6687 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6688 {
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6691         int pipe = intel_crtc->pipe;
6692         u32 dpll = I915_READ(DPLL(pipe));
6693         u32 fp;
6694         intel_clock_t clock;
6695
6696         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6697                 fp = I915_READ(FP0(pipe));
6698         else
6699                 fp = I915_READ(FP1(pipe));
6700
6701         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6702         if (IS_PINEVIEW(dev)) {
6703                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6704                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6705         } else {
6706                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6707                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6708         }
6709
6710         if (!IS_GEN2(dev)) {
6711                 if (IS_PINEVIEW(dev))
6712                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6713                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6714                 else
6715                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6716                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6717
6718                 switch (dpll & DPLL_MODE_MASK) {
6719                 case DPLLB_MODE_DAC_SERIAL:
6720                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6721                                 5 : 10;
6722                         break;
6723                 case DPLLB_MODE_LVDS:
6724                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6725                                 7 : 14;
6726                         break;
6727                 default:
6728                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6729                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6730                         return 0;
6731                 }
6732
6733                 /* XXX: Handle the 100Mhz refclk */
6734                 intel_clock(dev, 96000, &clock);
6735         } else {
6736                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6737
6738                 if (is_lvds) {
6739                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6740                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6741                         clock.p2 = 14;
6742
6743                         if ((dpll & PLL_REF_INPUT_MASK) ==
6744                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6745                                 /* XXX: might not be 66MHz */
6746                                 intel_clock(dev, 66000, &clock);
6747                         } else
6748                                 intel_clock(dev, 48000, &clock);
6749                 } else {
6750                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6751                                 clock.p1 = 2;
6752                         else {
6753                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6754                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6755                         }
6756                         if (dpll & PLL_P2_DIVIDE_BY_4)
6757                                 clock.p2 = 4;
6758                         else
6759                                 clock.p2 = 2;
6760
6761                         intel_clock(dev, 48000, &clock);
6762                 }
6763         }
6764
6765         /* XXX: It would be nice to validate the clocks, but we can't reuse
6766          * i830PllIsValid() because it relies on the xf86_config connector
6767          * configuration being accurate, which it isn't necessarily.
6768          */
6769
6770         return clock.dot;
6771 }
6772
6773 /** Returns the currently programmed mode of the given pipe. */
6774 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6775                                              struct drm_crtc *crtc)
6776 {
6777         struct drm_i915_private *dev_priv = dev->dev_private;
6778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6779         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6780         struct drm_display_mode *mode;
6781         int htot = I915_READ(HTOTAL(cpu_transcoder));
6782         int hsync = I915_READ(HSYNC(cpu_transcoder));
6783         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6784         int vsync = I915_READ(VSYNC(cpu_transcoder));
6785
6786         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6787         if (!mode)
6788                 return NULL;
6789
6790         mode->clock = intel_crtc_clock_get(dev, crtc);
6791         mode->hdisplay = (htot & 0xffff) + 1;
6792         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6793         mode->hsync_start = (hsync & 0xffff) + 1;
6794         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6795         mode->vdisplay = (vtot & 0xffff) + 1;
6796         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6797         mode->vsync_start = (vsync & 0xffff) + 1;
6798         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6799
6800         drm_mode_set_name(mode);
6801
6802         return mode;
6803 }
6804
6805 static void intel_increase_pllclock(struct drm_crtc *crtc)
6806 {
6807         struct drm_device *dev = crtc->dev;
6808         drm_i915_private_t *dev_priv = dev->dev_private;
6809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6810         int pipe = intel_crtc->pipe;
6811         int dpll_reg = DPLL(pipe);
6812         int dpll;
6813
6814         if (HAS_PCH_SPLIT(dev))
6815                 return;
6816
6817         if (!dev_priv->lvds_downclock_avail)
6818                 return;
6819
6820         dpll = I915_READ(dpll_reg);
6821         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6822                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6823
6824                 assert_panel_unlocked(dev_priv, pipe);
6825
6826                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6827                 I915_WRITE(dpll_reg, dpll);
6828                 intel_wait_for_vblank(dev, pipe);
6829
6830                 dpll = I915_READ(dpll_reg);
6831                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6832                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6833         }
6834 }
6835
6836 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6837 {
6838         struct drm_device *dev = crtc->dev;
6839         drm_i915_private_t *dev_priv = dev->dev_private;
6840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6841
6842         if (HAS_PCH_SPLIT(dev))
6843                 return;
6844
6845         if (!dev_priv->lvds_downclock_avail)
6846                 return;
6847
6848         /*
6849          * Since this is called by a timer, we should never get here in
6850          * the manual case.
6851          */
6852         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6853                 int pipe = intel_crtc->pipe;
6854                 int dpll_reg = DPLL(pipe);
6855                 int dpll;
6856
6857                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6858
6859                 assert_panel_unlocked(dev_priv, pipe);
6860
6861                 dpll = I915_READ(dpll_reg);
6862                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6863                 I915_WRITE(dpll_reg, dpll);
6864                 intel_wait_for_vblank(dev, pipe);
6865                 dpll = I915_READ(dpll_reg);
6866                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6867                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6868         }
6869
6870 }
6871
6872 void intel_mark_busy(struct drm_device *dev)
6873 {
6874         i915_update_gfx_val(dev->dev_private);
6875 }
6876
6877 void intel_mark_idle(struct drm_device *dev)
6878 {
6879 }
6880
6881 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6882 {
6883         struct drm_device *dev = obj->base.dev;
6884         struct drm_crtc *crtc;
6885
6886         if (!i915_powersave)
6887                 return;
6888
6889         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6890                 if (!crtc->fb)
6891                         continue;
6892
6893                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6894                         intel_increase_pllclock(crtc);
6895         }
6896 }
6897
6898 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6899 {
6900         struct drm_device *dev = obj->base.dev;
6901         struct drm_crtc *crtc;
6902
6903         if (!i915_powersave)
6904                 return;
6905
6906         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6907                 if (!crtc->fb)
6908                         continue;
6909
6910                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6911                         intel_decrease_pllclock(crtc);
6912         }
6913 }
6914
6915 static void intel_crtc_destroy(struct drm_crtc *crtc)
6916 {
6917         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6918         struct drm_device *dev = crtc->dev;
6919         struct intel_unpin_work *work;
6920         unsigned long flags;
6921
6922         spin_lock_irqsave(&dev->event_lock, flags);
6923         work = intel_crtc->unpin_work;
6924         intel_crtc->unpin_work = NULL;
6925         spin_unlock_irqrestore(&dev->event_lock, flags);
6926
6927         if (work) {
6928                 cancel_work_sync(&work->work);
6929                 kfree(work);
6930         }
6931
6932         drm_crtc_cleanup(crtc);
6933
6934         kfree(intel_crtc);
6935 }
6936
6937 static void intel_unpin_work_fn(struct work_struct *__work)
6938 {
6939         struct intel_unpin_work *work =
6940                 container_of(__work, struct intel_unpin_work, work);
6941
6942         mutex_lock(&work->dev->struct_mutex);
6943         intel_unpin_fb_obj(work->old_fb_obj);
6944         drm_gem_object_unreference(&work->pending_flip_obj->base);
6945         drm_gem_object_unreference(&work->old_fb_obj->base);
6946
6947         intel_update_fbc(work->dev);
6948         mutex_unlock(&work->dev->struct_mutex);
6949         kfree(work);
6950 }
6951
6952 static void do_intel_finish_page_flip(struct drm_device *dev,
6953                                       struct drm_crtc *crtc)
6954 {
6955         drm_i915_private_t *dev_priv = dev->dev_private;
6956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957         struct intel_unpin_work *work;
6958         struct drm_i915_gem_object *obj;
6959         struct drm_pending_vblank_event *e;
6960         struct timeval tvbl;
6961         unsigned long flags;
6962
6963         /* Ignore early vblank irqs */
6964         if (intel_crtc == NULL)
6965                 return;
6966
6967         spin_lock_irqsave(&dev->event_lock, flags);
6968         work = intel_crtc->unpin_work;
6969         if (work == NULL || !work->pending) {
6970                 spin_unlock_irqrestore(&dev->event_lock, flags);
6971                 return;
6972         }
6973
6974         intel_crtc->unpin_work = NULL;
6975
6976         if (work->event) {
6977                 e = work->event;
6978                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6979
6980                 e->event.tv_sec = tvbl.tv_sec;
6981                 e->event.tv_usec = tvbl.tv_usec;
6982
6983                 list_add_tail(&e->base.link,
6984                               &e->base.file_priv->event_list);
6985                 wake_up_interruptible(&e->base.file_priv->event_wait);
6986         }
6987
6988         drm_vblank_put(dev, intel_crtc->pipe);
6989
6990         spin_unlock_irqrestore(&dev->event_lock, flags);
6991
6992         obj = work->old_fb_obj;
6993
6994         atomic_clear_mask(1 << intel_crtc->plane,
6995                           &obj->pending_flip.counter);
6996
6997         wake_up(&dev_priv->pending_flip_queue);
6998         schedule_work(&work->work);
6999
7000         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7001 }
7002
7003 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7004 {
7005         drm_i915_private_t *dev_priv = dev->dev_private;
7006         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7007
7008         do_intel_finish_page_flip(dev, crtc);
7009 }
7010
7011 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7012 {
7013         drm_i915_private_t *dev_priv = dev->dev_private;
7014         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7015
7016         do_intel_finish_page_flip(dev, crtc);
7017 }
7018
7019 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7020 {
7021         drm_i915_private_t *dev_priv = dev->dev_private;
7022         struct intel_crtc *intel_crtc =
7023                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7024         unsigned long flags;
7025
7026         spin_lock_irqsave(&dev->event_lock, flags);
7027         if (intel_crtc->unpin_work) {
7028                 if ((++intel_crtc->unpin_work->pending) > 1)
7029                         DRM_ERROR("Prepared flip multiple times\n");
7030         } else {
7031                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7032         }
7033         spin_unlock_irqrestore(&dev->event_lock, flags);
7034 }
7035
7036 static int intel_gen2_queue_flip(struct drm_device *dev,
7037                                  struct drm_crtc *crtc,
7038                                  struct drm_framebuffer *fb,
7039                                  struct drm_i915_gem_object *obj)
7040 {
7041         struct drm_i915_private *dev_priv = dev->dev_private;
7042         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7043         u32 flip_mask;
7044         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7045         int ret;
7046
7047         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7048         if (ret)
7049                 goto err;
7050
7051         ret = intel_ring_begin(ring, 6);
7052         if (ret)
7053                 goto err_unpin;
7054
7055         /* Can't queue multiple flips, so wait for the previous
7056          * one to finish before executing the next.
7057          */
7058         if (intel_crtc->plane)
7059                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7060         else
7061                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7062         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7063         intel_ring_emit(ring, MI_NOOP);
7064         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7065                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7066         intel_ring_emit(ring, fb->pitches[0]);
7067         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7068         intel_ring_emit(ring, 0); /* aux display base address, unused */
7069         intel_ring_advance(ring);
7070         return 0;
7071
7072 err_unpin:
7073         intel_unpin_fb_obj(obj);
7074 err:
7075         return ret;
7076 }
7077
7078 static int intel_gen3_queue_flip(struct drm_device *dev,
7079                                  struct drm_crtc *crtc,
7080                                  struct drm_framebuffer *fb,
7081                                  struct drm_i915_gem_object *obj)
7082 {
7083         struct drm_i915_private *dev_priv = dev->dev_private;
7084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7085         u32 flip_mask;
7086         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7087         int ret;
7088
7089         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7090         if (ret)
7091                 goto err;
7092
7093         ret = intel_ring_begin(ring, 6);
7094         if (ret)
7095                 goto err_unpin;
7096
7097         if (intel_crtc->plane)
7098                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7099         else
7100                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7101         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7102         intel_ring_emit(ring, MI_NOOP);
7103         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7104                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7105         intel_ring_emit(ring, fb->pitches[0]);
7106         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7107         intel_ring_emit(ring, MI_NOOP);
7108
7109         intel_ring_advance(ring);
7110         return 0;
7111
7112 err_unpin:
7113         intel_unpin_fb_obj(obj);
7114 err:
7115         return ret;
7116 }
7117
7118 static int intel_gen4_queue_flip(struct drm_device *dev,
7119                                  struct drm_crtc *crtc,
7120                                  struct drm_framebuffer *fb,
7121                                  struct drm_i915_gem_object *obj)
7122 {
7123         struct drm_i915_private *dev_priv = dev->dev_private;
7124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7125         uint32_t pf, pipesrc;
7126         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7127         int ret;
7128
7129         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7130         if (ret)
7131                 goto err;
7132
7133         ret = intel_ring_begin(ring, 4);
7134         if (ret)
7135                 goto err_unpin;
7136
7137         /* i965+ uses the linear or tiled offsets from the
7138          * Display Registers (which do not change across a page-flip)
7139          * so we need only reprogram the base address.
7140          */
7141         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7142                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7143         intel_ring_emit(ring, fb->pitches[0]);
7144         intel_ring_emit(ring,
7145                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7146                         obj->tiling_mode);
7147
7148         /* XXX Enabling the panel-fitter across page-flip is so far
7149          * untested on non-native modes, so ignore it for now.
7150          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7151          */
7152         pf = 0;
7153         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7154         intel_ring_emit(ring, pf | pipesrc);
7155         intel_ring_advance(ring);
7156         return 0;
7157
7158 err_unpin:
7159         intel_unpin_fb_obj(obj);
7160 err:
7161         return ret;
7162 }
7163
7164 static int intel_gen6_queue_flip(struct drm_device *dev,
7165                                  struct drm_crtc *crtc,
7166                                  struct drm_framebuffer *fb,
7167                                  struct drm_i915_gem_object *obj)
7168 {
7169         struct drm_i915_private *dev_priv = dev->dev_private;
7170         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7171         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7172         uint32_t pf, pipesrc;
7173         int ret;
7174
7175         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7176         if (ret)
7177                 goto err;
7178
7179         ret = intel_ring_begin(ring, 4);
7180         if (ret)
7181                 goto err_unpin;
7182
7183         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7184                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7185         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7186         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7187
7188         /* Contrary to the suggestions in the documentation,
7189          * "Enable Panel Fitter" does not seem to be required when page
7190          * flipping with a non-native mode, and worse causes a normal
7191          * modeset to fail.
7192          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7193          */
7194         pf = 0;
7195         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7196         intel_ring_emit(ring, pf | pipesrc);
7197         intel_ring_advance(ring);
7198         return 0;
7199
7200 err_unpin:
7201         intel_unpin_fb_obj(obj);
7202 err:
7203         return ret;
7204 }
7205
7206 /*
7207  * On gen7 we currently use the blit ring because (in early silicon at least)
7208  * the render ring doesn't give us interrpts for page flip completion, which
7209  * means clients will hang after the first flip is queued.  Fortunately the
7210  * blit ring generates interrupts properly, so use it instead.
7211  */
7212 static int intel_gen7_queue_flip(struct drm_device *dev,
7213                                  struct drm_crtc *crtc,
7214                                  struct drm_framebuffer *fb,
7215                                  struct drm_i915_gem_object *obj)
7216 {
7217         struct drm_i915_private *dev_priv = dev->dev_private;
7218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7219         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7220         uint32_t plane_bit = 0;
7221         int ret;
7222
7223         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7224         if (ret)
7225                 goto err;
7226
7227         switch(intel_crtc->plane) {
7228         case PLANE_A:
7229                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7230                 break;
7231         case PLANE_B:
7232                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7233                 break;
7234         case PLANE_C:
7235                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7236                 break;
7237         default:
7238                 WARN_ONCE(1, "unknown plane in flip command\n");
7239                 ret = -ENODEV;
7240                 goto err_unpin;
7241         }
7242
7243         ret = intel_ring_begin(ring, 4);
7244         if (ret)
7245                 goto err_unpin;
7246
7247         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7248         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7249         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7250         intel_ring_emit(ring, (MI_NOOP));
7251         intel_ring_advance(ring);
7252         return 0;
7253
7254 err_unpin:
7255         intel_unpin_fb_obj(obj);
7256 err:
7257         return ret;
7258 }
7259
7260 static int intel_default_queue_flip(struct drm_device *dev,
7261                                     struct drm_crtc *crtc,
7262                                     struct drm_framebuffer *fb,
7263                                     struct drm_i915_gem_object *obj)
7264 {
7265         return -ENODEV;
7266 }
7267
7268 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7269                                 struct drm_framebuffer *fb,
7270                                 struct drm_pending_vblank_event *event)
7271 {
7272         struct drm_device *dev = crtc->dev;
7273         struct drm_i915_private *dev_priv = dev->dev_private;
7274         struct intel_framebuffer *intel_fb;
7275         struct drm_i915_gem_object *obj;
7276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7277         struct intel_unpin_work *work;
7278         unsigned long flags;
7279         int ret;
7280
7281         /* Can't change pixel format via MI display flips. */
7282         if (fb->pixel_format != crtc->fb->pixel_format)
7283                 return -EINVAL;
7284
7285         /*
7286          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7287          * Note that pitch changes could also affect these register.
7288          */
7289         if (INTEL_INFO(dev)->gen > 3 &&
7290             (fb->offsets[0] != crtc->fb->offsets[0] ||
7291              fb->pitches[0] != crtc->fb->pitches[0]))
7292                 return -EINVAL;
7293
7294         work = kzalloc(sizeof *work, GFP_KERNEL);
7295         if (work == NULL)
7296                 return -ENOMEM;
7297
7298         work->event = event;
7299         work->dev = crtc->dev;
7300         intel_fb = to_intel_framebuffer(crtc->fb);
7301         work->old_fb_obj = intel_fb->obj;
7302         INIT_WORK(&work->work, intel_unpin_work_fn);
7303
7304         ret = drm_vblank_get(dev, intel_crtc->pipe);
7305         if (ret)
7306                 goto free_work;
7307
7308         /* We borrow the event spin lock for protecting unpin_work */
7309         spin_lock_irqsave(&dev->event_lock, flags);
7310         if (intel_crtc->unpin_work) {
7311                 spin_unlock_irqrestore(&dev->event_lock, flags);
7312                 kfree(work);
7313                 drm_vblank_put(dev, intel_crtc->pipe);
7314
7315                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7316                 return -EBUSY;
7317         }
7318         intel_crtc->unpin_work = work;
7319         spin_unlock_irqrestore(&dev->event_lock, flags);
7320
7321         intel_fb = to_intel_framebuffer(fb);
7322         obj = intel_fb->obj;
7323
7324         ret = i915_mutex_lock_interruptible(dev);
7325         if (ret)
7326                 goto cleanup;
7327
7328         /* Reference the objects for the scheduled work. */
7329         drm_gem_object_reference(&work->old_fb_obj->base);
7330         drm_gem_object_reference(&obj->base);
7331
7332         crtc->fb = fb;
7333
7334         work->pending_flip_obj = obj;
7335
7336         work->enable_stall_check = true;
7337
7338         /* Block clients from rendering to the new back buffer until
7339          * the flip occurs and the object is no longer visible.
7340          */
7341         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7342
7343         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7344         if (ret)
7345                 goto cleanup_pending;
7346
7347         intel_disable_fbc(dev);
7348         intel_mark_fb_busy(obj);
7349         mutex_unlock(&dev->struct_mutex);
7350
7351         trace_i915_flip_request(intel_crtc->plane, obj);
7352
7353         return 0;
7354
7355 cleanup_pending:
7356         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7357         drm_gem_object_unreference(&work->old_fb_obj->base);
7358         drm_gem_object_unreference(&obj->base);
7359         mutex_unlock(&dev->struct_mutex);
7360
7361 cleanup:
7362         spin_lock_irqsave(&dev->event_lock, flags);
7363         intel_crtc->unpin_work = NULL;
7364         spin_unlock_irqrestore(&dev->event_lock, flags);
7365
7366         drm_vblank_put(dev, intel_crtc->pipe);
7367 free_work:
7368         kfree(work);
7369
7370         return ret;
7371 }
7372
7373 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7374         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7375         .load_lut = intel_crtc_load_lut,
7376         .disable = intel_crtc_noop,
7377 };
7378
7379 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7380 {
7381         struct intel_encoder *other_encoder;
7382         struct drm_crtc *crtc = &encoder->new_crtc->base;
7383
7384         if (WARN_ON(!crtc))
7385                 return false;
7386
7387         list_for_each_entry(other_encoder,
7388                             &crtc->dev->mode_config.encoder_list,
7389                             base.head) {
7390
7391                 if (&other_encoder->new_crtc->base != crtc ||
7392                     encoder == other_encoder)
7393                         continue;
7394                 else
7395                         return true;
7396         }
7397
7398         return false;
7399 }
7400
7401 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7402                                   struct drm_crtc *crtc)
7403 {
7404         struct drm_device *dev;
7405         struct drm_crtc *tmp;
7406         int crtc_mask = 1;
7407
7408         WARN(!crtc, "checking null crtc?\n");
7409
7410         dev = crtc->dev;
7411
7412         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7413                 if (tmp == crtc)
7414                         break;
7415                 crtc_mask <<= 1;
7416         }
7417
7418         if (encoder->possible_crtcs & crtc_mask)
7419                 return true;
7420         return false;
7421 }
7422
7423 /**
7424  * intel_modeset_update_staged_output_state
7425  *
7426  * Updates the staged output configuration state, e.g. after we've read out the
7427  * current hw state.
7428  */
7429 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7430 {
7431         struct intel_encoder *encoder;
7432         struct intel_connector *connector;
7433
7434         list_for_each_entry(connector, &dev->mode_config.connector_list,
7435                             base.head) {
7436                 connector->new_encoder =
7437                         to_intel_encoder(connector->base.encoder);
7438         }
7439
7440         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7441                             base.head) {
7442                 encoder->new_crtc =
7443                         to_intel_crtc(encoder->base.crtc);
7444         }
7445 }
7446
7447 /**
7448  * intel_modeset_commit_output_state
7449  *
7450  * This function copies the stage display pipe configuration to the real one.
7451  */
7452 static void intel_modeset_commit_output_state(struct drm_device *dev)
7453 {
7454         struct intel_encoder *encoder;
7455         struct intel_connector *connector;
7456
7457         list_for_each_entry(connector, &dev->mode_config.connector_list,
7458                             base.head) {
7459                 connector->base.encoder = &connector->new_encoder->base;
7460         }
7461
7462         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7463                             base.head) {
7464                 encoder->base.crtc = &encoder->new_crtc->base;
7465         }
7466 }
7467
7468 static struct drm_display_mode *
7469 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7470                             struct drm_display_mode *mode)
7471 {
7472         struct drm_device *dev = crtc->dev;
7473         struct drm_display_mode *adjusted_mode;
7474         struct drm_encoder_helper_funcs *encoder_funcs;
7475         struct intel_encoder *encoder;
7476
7477         adjusted_mode = drm_mode_duplicate(dev, mode);
7478         if (!adjusted_mode)
7479                 return ERR_PTR(-ENOMEM);
7480
7481         /* Pass our mode to the connectors and the CRTC to give them a chance to
7482          * adjust it according to limitations or connector properties, and also
7483          * a chance to reject the mode entirely.
7484          */
7485         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7486                             base.head) {
7487
7488                 if (&encoder->new_crtc->base != crtc)
7489                         continue;
7490                 encoder_funcs = encoder->base.helper_private;
7491                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7492                                                 adjusted_mode))) {
7493                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7494                         goto fail;
7495                 }
7496         }
7497
7498         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7499                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7500                 goto fail;
7501         }
7502         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7503
7504         return adjusted_mode;
7505 fail:
7506         drm_mode_destroy(dev, adjusted_mode);
7507         return ERR_PTR(-EINVAL);
7508 }
7509
7510 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7511  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7512 static void
7513 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7514                              unsigned *prepare_pipes, unsigned *disable_pipes)
7515 {
7516         struct intel_crtc *intel_crtc;
7517         struct drm_device *dev = crtc->dev;
7518         struct intel_encoder *encoder;
7519         struct intel_connector *connector;
7520         struct drm_crtc *tmp_crtc;
7521
7522         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7523
7524         /* Check which crtcs have changed outputs connected to them, these need
7525          * to be part of the prepare_pipes mask. We don't (yet) support global
7526          * modeset across multiple crtcs, so modeset_pipes will only have one
7527          * bit set at most. */
7528         list_for_each_entry(connector, &dev->mode_config.connector_list,
7529                             base.head) {
7530                 if (connector->base.encoder == &connector->new_encoder->base)
7531                         continue;
7532
7533                 if (connector->base.encoder) {
7534                         tmp_crtc = connector->base.encoder->crtc;
7535
7536                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7537                 }
7538
7539                 if (connector->new_encoder)
7540                         *prepare_pipes |=
7541                                 1 << connector->new_encoder->new_crtc->pipe;
7542         }
7543
7544         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7545                             base.head) {
7546                 if (encoder->base.crtc == &encoder->new_crtc->base)
7547                         continue;
7548
7549                 if (encoder->base.crtc) {
7550                         tmp_crtc = encoder->base.crtc;
7551
7552                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7553                 }
7554
7555                 if (encoder->new_crtc)
7556                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7557         }
7558
7559         /* Check for any pipes that will be fully disabled ... */
7560         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7561                             base.head) {
7562                 bool used = false;
7563
7564                 /* Don't try to disable disabled crtcs. */
7565                 if (!intel_crtc->base.enabled)
7566                         continue;
7567
7568                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7569                                     base.head) {
7570                         if (encoder->new_crtc == intel_crtc)
7571                                 used = true;
7572                 }
7573
7574                 if (!used)
7575                         *disable_pipes |= 1 << intel_crtc->pipe;
7576         }
7577
7578
7579         /* set_mode is also used to update properties on life display pipes. */
7580         intel_crtc = to_intel_crtc(crtc);
7581         if (crtc->enabled)
7582                 *prepare_pipes |= 1 << intel_crtc->pipe;
7583
7584         /* We only support modeset on one single crtc, hence we need to do that
7585          * only for the passed in crtc iff we change anything else than just
7586          * disable crtcs.
7587          *
7588          * This is actually not true, to be fully compatible with the old crtc
7589          * helper we automatically disable _any_ output (i.e. doesn't need to be
7590          * connected to the crtc we're modesetting on) if it's disconnected.
7591          * Which is a rather nutty api (since changed the output configuration
7592          * without userspace's explicit request can lead to confusion), but
7593          * alas. Hence we currently need to modeset on all pipes we prepare. */
7594         if (*prepare_pipes)
7595                 *modeset_pipes = *prepare_pipes;
7596
7597         /* ... and mask these out. */
7598         *modeset_pipes &= ~(*disable_pipes);
7599         *prepare_pipes &= ~(*disable_pipes);
7600 }
7601
7602 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7603 {
7604         struct drm_encoder *encoder;
7605         struct drm_device *dev = crtc->dev;
7606
7607         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7608                 if (encoder->crtc == crtc)
7609                         return true;
7610
7611         return false;
7612 }
7613
7614 static void
7615 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7616 {
7617         struct intel_encoder *intel_encoder;
7618         struct intel_crtc *intel_crtc;
7619         struct drm_connector *connector;
7620
7621         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7622                             base.head) {
7623                 if (!intel_encoder->base.crtc)
7624                         continue;
7625
7626                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7627
7628                 if (prepare_pipes & (1 << intel_crtc->pipe))
7629                         intel_encoder->connectors_active = false;
7630         }
7631
7632         intel_modeset_commit_output_state(dev);
7633
7634         /* Update computed state. */
7635         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7636                             base.head) {
7637                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7638         }
7639
7640         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7641                 if (!connector->encoder || !connector->encoder->crtc)
7642                         continue;
7643
7644                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7645
7646                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7647                         struct drm_property *dpms_property =
7648                                 dev->mode_config.dpms_property;
7649
7650                         connector->dpms = DRM_MODE_DPMS_ON;
7651                         drm_connector_property_set_value(connector,
7652                                                          dpms_property,
7653                                                          DRM_MODE_DPMS_ON);
7654
7655                         intel_encoder = to_intel_encoder(connector->encoder);
7656                         intel_encoder->connectors_active = true;
7657                 }
7658         }
7659
7660 }
7661
7662 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7663         list_for_each_entry((intel_crtc), \
7664                             &(dev)->mode_config.crtc_list, \
7665                             base.head) \
7666                 if (mask & (1 <<(intel_crtc)->pipe)) \
7667
7668 void
7669 intel_modeset_check_state(struct drm_device *dev)
7670 {
7671         struct intel_crtc *crtc;
7672         struct intel_encoder *encoder;
7673         struct intel_connector *connector;
7674
7675         list_for_each_entry(connector, &dev->mode_config.connector_list,
7676                             base.head) {
7677                 /* This also checks the encoder/connector hw state with the
7678                  * ->get_hw_state callbacks. */
7679                 intel_connector_check_state(connector);
7680
7681                 WARN(&connector->new_encoder->base != connector->base.encoder,
7682                      "connector's staged encoder doesn't match current encoder\n");
7683         }
7684
7685         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7686                             base.head) {
7687                 bool enabled = false;
7688                 bool active = false;
7689                 enum pipe pipe, tracked_pipe;
7690
7691                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7692                               encoder->base.base.id,
7693                               drm_get_encoder_name(&encoder->base));
7694
7695                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7696                      "encoder's stage crtc doesn't match current crtc\n");
7697                 WARN(encoder->connectors_active && !encoder->base.crtc,
7698                      "encoder's active_connectors set, but no crtc\n");
7699
7700                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7701                                     base.head) {
7702                         if (connector->base.encoder != &encoder->base)
7703                                 continue;
7704                         enabled = true;
7705                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7706                                 active = true;
7707                 }
7708                 WARN(!!encoder->base.crtc != enabled,
7709                      "encoder's enabled state mismatch "
7710                      "(expected %i, found %i)\n",
7711                      !!encoder->base.crtc, enabled);
7712                 WARN(active && !encoder->base.crtc,
7713                      "active encoder with no crtc\n");
7714
7715                 WARN(encoder->connectors_active != active,
7716                      "encoder's computed active state doesn't match tracked active state "
7717                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7718
7719                 active = encoder->get_hw_state(encoder, &pipe);
7720                 WARN(active != encoder->connectors_active,
7721                      "encoder's hw state doesn't match sw tracking "
7722                      "(expected %i, found %i)\n",
7723                      encoder->connectors_active, active);
7724
7725                 if (!encoder->base.crtc)
7726                         continue;
7727
7728                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7729                 WARN(active && pipe != tracked_pipe,
7730                      "active encoder's pipe doesn't match"
7731                      "(expected %i, found %i)\n",
7732                      tracked_pipe, pipe);
7733
7734         }
7735
7736         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7737                             base.head) {
7738                 bool enabled = false;
7739                 bool active = false;
7740
7741                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7742                               crtc->base.base.id);
7743
7744                 WARN(crtc->active && !crtc->base.enabled,
7745                      "active crtc, but not enabled in sw tracking\n");
7746
7747                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7748                                     base.head) {
7749                         if (encoder->base.crtc != &crtc->base)
7750                                 continue;
7751                         enabled = true;
7752                         if (encoder->connectors_active)
7753                                 active = true;
7754                 }
7755                 WARN(active != crtc->active,
7756                      "crtc's computed active state doesn't match tracked active state "
7757                      "(expected %i, found %i)\n", active, crtc->active);
7758                 WARN(enabled != crtc->base.enabled,
7759                      "crtc's computed enabled state doesn't match tracked enabled state "
7760                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7761
7762                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7763         }
7764 }
7765
7766 bool intel_set_mode(struct drm_crtc *crtc,
7767                     struct drm_display_mode *mode,
7768                     int x, int y, struct drm_framebuffer *fb)
7769 {
7770         struct drm_device *dev = crtc->dev;
7771         drm_i915_private_t *dev_priv = dev->dev_private;
7772         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7773         struct intel_crtc *intel_crtc;
7774         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7775         bool ret = true;
7776
7777         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7778                                      &prepare_pipes, &disable_pipes);
7779
7780         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7781                       modeset_pipes, prepare_pipes, disable_pipes);
7782
7783         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7784                 intel_crtc_disable(&intel_crtc->base);
7785
7786         saved_hwmode = crtc->hwmode;
7787         saved_mode = crtc->mode;
7788
7789         /* Hack: Because we don't (yet) support global modeset on multiple
7790          * crtcs, we don't keep track of the new mode for more than one crtc.
7791          * Hence simply check whether any bit is set in modeset_pipes in all the
7792          * pieces of code that are not yet converted to deal with mutliple crtcs
7793          * changing their mode at the same time. */
7794         adjusted_mode = NULL;
7795         if (modeset_pipes) {
7796                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7797                 if (IS_ERR(adjusted_mode)) {
7798                         return false;
7799                 }
7800         }
7801
7802         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7803                 if (intel_crtc->base.enabled)
7804                         dev_priv->display.crtc_disable(&intel_crtc->base);
7805         }
7806
7807         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7808          * to set it here already despite that we pass it down the callchain.
7809          */
7810         if (modeset_pipes)
7811                 crtc->mode = *mode;
7812
7813         /* Only after disabling all output pipelines that will be changed can we
7814          * update the the output configuration. */
7815         intel_modeset_update_state(dev, prepare_pipes);
7816
7817         if (dev_priv->display.modeset_global_resources)
7818                 dev_priv->display.modeset_global_resources(dev);
7819
7820         /* Set up the DPLL and any encoders state that needs to adjust or depend
7821          * on the DPLL.
7822          */
7823         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7824                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7825                                            mode, adjusted_mode,
7826                                            x, y, fb);
7827                 if (!ret)
7828                     goto done;
7829         }
7830
7831         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7832         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7833                 dev_priv->display.crtc_enable(&intel_crtc->base);
7834
7835         if (modeset_pipes) {
7836                 /* Store real post-adjustment hardware mode. */
7837                 crtc->hwmode = *adjusted_mode;
7838
7839                 /* Calculate and store various constants which
7840                  * are later needed by vblank and swap-completion
7841                  * timestamping. They are derived from true hwmode.
7842                  */
7843                 drm_calc_timestamping_constants(crtc);
7844         }
7845
7846         /* FIXME: add subpixel order */
7847 done:
7848         drm_mode_destroy(dev, adjusted_mode);
7849         if (!ret && crtc->enabled) {
7850                 crtc->hwmode = saved_hwmode;
7851                 crtc->mode = saved_mode;
7852         } else {
7853                 intel_modeset_check_state(dev);
7854         }
7855
7856         return ret;
7857 }
7858
7859 #undef for_each_intel_crtc_masked
7860
7861 static void intel_set_config_free(struct intel_set_config *config)
7862 {
7863         if (!config)
7864                 return;
7865
7866         kfree(config->save_connector_encoders);
7867         kfree(config->save_encoder_crtcs);
7868         kfree(config);
7869 }
7870
7871 static int intel_set_config_save_state(struct drm_device *dev,
7872                                        struct intel_set_config *config)
7873 {
7874         struct drm_encoder *encoder;
7875         struct drm_connector *connector;
7876         int count;
7877
7878         config->save_encoder_crtcs =
7879                 kcalloc(dev->mode_config.num_encoder,
7880                         sizeof(struct drm_crtc *), GFP_KERNEL);
7881         if (!config->save_encoder_crtcs)
7882                 return -ENOMEM;
7883
7884         config->save_connector_encoders =
7885                 kcalloc(dev->mode_config.num_connector,
7886                         sizeof(struct drm_encoder *), GFP_KERNEL);
7887         if (!config->save_connector_encoders)
7888                 return -ENOMEM;
7889
7890         /* Copy data. Note that driver private data is not affected.
7891          * Should anything bad happen only the expected state is
7892          * restored, not the drivers personal bookkeeping.
7893          */
7894         count = 0;
7895         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7896                 config->save_encoder_crtcs[count++] = encoder->crtc;
7897         }
7898
7899         count = 0;
7900         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7901                 config->save_connector_encoders[count++] = connector->encoder;
7902         }
7903
7904         return 0;
7905 }
7906
7907 static void intel_set_config_restore_state(struct drm_device *dev,
7908                                            struct intel_set_config *config)
7909 {
7910         struct intel_encoder *encoder;
7911         struct intel_connector *connector;
7912         int count;
7913
7914         count = 0;
7915         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7916                 encoder->new_crtc =
7917                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7918         }
7919
7920         count = 0;
7921         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7922                 connector->new_encoder =
7923                         to_intel_encoder(config->save_connector_encoders[count++]);
7924         }
7925 }
7926
7927 static void
7928 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7929                                       struct intel_set_config *config)
7930 {
7931
7932         /* We should be able to check here if the fb has the same properties
7933          * and then just flip_or_move it */
7934         if (set->crtc->fb != set->fb) {
7935                 /* If we have no fb then treat it as a full mode set */
7936                 if (set->crtc->fb == NULL) {
7937                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7938                         config->mode_changed = true;
7939                 } else if (set->fb == NULL) {
7940                         config->mode_changed = true;
7941                 } else if (set->fb->depth != set->crtc->fb->depth) {
7942                         config->mode_changed = true;
7943                 } else if (set->fb->bits_per_pixel !=
7944                            set->crtc->fb->bits_per_pixel) {
7945                         config->mode_changed = true;
7946                 } else
7947                         config->fb_changed = true;
7948         }
7949
7950         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7951                 config->fb_changed = true;
7952
7953         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7954                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7955                 drm_mode_debug_printmodeline(&set->crtc->mode);
7956                 drm_mode_debug_printmodeline(set->mode);
7957                 config->mode_changed = true;
7958         }
7959 }
7960
7961 static int
7962 intel_modeset_stage_output_state(struct drm_device *dev,
7963                                  struct drm_mode_set *set,
7964                                  struct intel_set_config *config)
7965 {
7966         struct drm_crtc *new_crtc;
7967         struct intel_connector *connector;
7968         struct intel_encoder *encoder;
7969         int count, ro;
7970
7971         /* The upper layers ensure that we either disabl a crtc or have a list
7972          * of connectors. For paranoia, double-check this. */
7973         WARN_ON(!set->fb && (set->num_connectors != 0));
7974         WARN_ON(set->fb && (set->num_connectors == 0));
7975
7976         count = 0;
7977         list_for_each_entry(connector, &dev->mode_config.connector_list,
7978                             base.head) {
7979                 /* Otherwise traverse passed in connector list and get encoders
7980                  * for them. */
7981                 for (ro = 0; ro < set->num_connectors; ro++) {
7982                         if (set->connectors[ro] == &connector->base) {
7983                                 connector->new_encoder = connector->encoder;
7984                                 break;
7985                         }
7986                 }
7987
7988                 /* If we disable the crtc, disable all its connectors. Also, if
7989                  * the connector is on the changing crtc but not on the new
7990                  * connector list, disable it. */
7991                 if ((!set->fb || ro == set->num_connectors) &&
7992                     connector->base.encoder &&
7993                     connector->base.encoder->crtc == set->crtc) {
7994                         connector->new_encoder = NULL;
7995
7996                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7997                                 connector->base.base.id,
7998                                 drm_get_connector_name(&connector->base));
7999                 }
8000
8001
8002                 if (&connector->new_encoder->base != connector->base.encoder) {
8003                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8004                         config->mode_changed = true;
8005                 }
8006
8007                 /* Disable all disconnected encoders. */
8008                 if (connector->base.status == connector_status_disconnected)
8009                         connector->new_encoder = NULL;
8010         }
8011         /* connector->new_encoder is now updated for all connectors. */
8012
8013         /* Update crtc of enabled connectors. */
8014         count = 0;
8015         list_for_each_entry(connector, &dev->mode_config.connector_list,
8016                             base.head) {
8017                 if (!connector->new_encoder)
8018                         continue;
8019
8020                 new_crtc = connector->new_encoder->base.crtc;
8021
8022                 for (ro = 0; ro < set->num_connectors; ro++) {
8023                         if (set->connectors[ro] == &connector->base)
8024                                 new_crtc = set->crtc;
8025                 }
8026
8027                 /* Make sure the new CRTC will work with the encoder */
8028                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8029                                            new_crtc)) {
8030                         return -EINVAL;
8031                 }
8032                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8033
8034                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8035                         connector->base.base.id,
8036                         drm_get_connector_name(&connector->base),
8037                         new_crtc->base.id);
8038         }
8039
8040         /* Check for any encoders that needs to be disabled. */
8041         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8042                             base.head) {
8043                 list_for_each_entry(connector,
8044                                     &dev->mode_config.connector_list,
8045                                     base.head) {
8046                         if (connector->new_encoder == encoder) {
8047                                 WARN_ON(!connector->new_encoder->new_crtc);
8048
8049                                 goto next_encoder;
8050                         }
8051                 }
8052                 encoder->new_crtc = NULL;
8053 next_encoder:
8054                 /* Only now check for crtc changes so we don't miss encoders
8055                  * that will be disabled. */
8056                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8057                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8058                         config->mode_changed = true;
8059                 }
8060         }
8061         /* Now we've also updated encoder->new_crtc for all encoders. */
8062
8063         return 0;
8064 }
8065
8066 static int intel_crtc_set_config(struct drm_mode_set *set)
8067 {
8068         struct drm_device *dev;
8069         struct drm_mode_set save_set;
8070         struct intel_set_config *config;
8071         int ret;
8072
8073         BUG_ON(!set);
8074         BUG_ON(!set->crtc);
8075         BUG_ON(!set->crtc->helper_private);
8076
8077         if (!set->mode)
8078                 set->fb = NULL;
8079
8080         /* The fb helper likes to play gross jokes with ->mode_set_config.
8081          * Unfortunately the crtc helper doesn't do much at all for this case,
8082          * so we have to cope with this madness until the fb helper is fixed up. */
8083         if (set->fb && set->num_connectors == 0)
8084                 return 0;
8085
8086         if (set->fb) {
8087                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8088                                 set->crtc->base.id, set->fb->base.id,
8089                                 (int)set->num_connectors, set->x, set->y);
8090         } else {
8091                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8092         }
8093
8094         dev = set->crtc->dev;
8095
8096         ret = -ENOMEM;
8097         config = kzalloc(sizeof(*config), GFP_KERNEL);
8098         if (!config)
8099                 goto out_config;
8100
8101         ret = intel_set_config_save_state(dev, config);
8102         if (ret)
8103                 goto out_config;
8104
8105         save_set.crtc = set->crtc;
8106         save_set.mode = &set->crtc->mode;
8107         save_set.x = set->crtc->x;
8108         save_set.y = set->crtc->y;
8109         save_set.fb = set->crtc->fb;
8110
8111         /* Compute whether we need a full modeset, only an fb base update or no
8112          * change at all. In the future we might also check whether only the
8113          * mode changed, e.g. for LVDS where we only change the panel fitter in
8114          * such cases. */
8115         intel_set_config_compute_mode_changes(set, config);
8116
8117         ret = intel_modeset_stage_output_state(dev, set, config);
8118         if (ret)
8119                 goto fail;
8120
8121         if (config->mode_changed) {
8122                 if (set->mode) {
8123                         DRM_DEBUG_KMS("attempting to set mode from"
8124                                         " userspace\n");
8125                         drm_mode_debug_printmodeline(set->mode);
8126                 }
8127
8128                 if (!intel_set_mode(set->crtc, set->mode,
8129                                     set->x, set->y, set->fb)) {
8130                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8131                                   set->crtc->base.id);
8132                         ret = -EINVAL;
8133                         goto fail;
8134                 }
8135         } else if (config->fb_changed) {
8136                 ret = intel_pipe_set_base(set->crtc,
8137                                           set->x, set->y, set->fb);
8138         }
8139
8140         intel_set_config_free(config);
8141
8142         return 0;
8143
8144 fail:
8145         intel_set_config_restore_state(dev, config);
8146
8147         /* Try to restore the config */
8148         if (config->mode_changed &&
8149             !intel_set_mode(save_set.crtc, save_set.mode,
8150                             save_set.x, save_set.y, save_set.fb))
8151                 DRM_ERROR("failed to restore config after modeset failure\n");
8152
8153 out_config:
8154         intel_set_config_free(config);
8155         return ret;
8156 }
8157
8158 static const struct drm_crtc_funcs intel_crtc_funcs = {
8159         .cursor_set = intel_crtc_cursor_set,
8160         .cursor_move = intel_crtc_cursor_move,
8161         .gamma_set = intel_crtc_gamma_set,
8162         .set_config = intel_crtc_set_config,
8163         .destroy = intel_crtc_destroy,
8164         .page_flip = intel_crtc_page_flip,
8165 };
8166
8167 static void intel_cpu_pll_init(struct drm_device *dev)
8168 {
8169         if (IS_HASWELL(dev))
8170                 intel_ddi_pll_init(dev);
8171 }
8172
8173 static void intel_pch_pll_init(struct drm_device *dev)
8174 {
8175         drm_i915_private_t *dev_priv = dev->dev_private;
8176         int i;
8177
8178         if (dev_priv->num_pch_pll == 0) {
8179                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8180                 return;
8181         }
8182
8183         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8184                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8185                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8186                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8187         }
8188 }
8189
8190 static void intel_crtc_init(struct drm_device *dev, int pipe)
8191 {
8192         drm_i915_private_t *dev_priv = dev->dev_private;
8193         struct intel_crtc *intel_crtc;
8194         int i;
8195
8196         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8197         if (intel_crtc == NULL)
8198                 return;
8199
8200         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8201
8202         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8203         for (i = 0; i < 256; i++) {
8204                 intel_crtc->lut_r[i] = i;
8205                 intel_crtc->lut_g[i] = i;
8206                 intel_crtc->lut_b[i] = i;
8207         }
8208
8209         /* Swap pipes & planes for FBC on pre-965 */
8210         intel_crtc->pipe = pipe;
8211         intel_crtc->plane = pipe;
8212         intel_crtc->cpu_transcoder = pipe;
8213         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8214                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8215                 intel_crtc->plane = !pipe;
8216         }
8217
8218         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8219                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8220         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8221         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8222
8223         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8224
8225         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8226 }
8227
8228 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8229                                 struct drm_file *file)
8230 {
8231         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8232         struct drm_mode_object *drmmode_obj;
8233         struct intel_crtc *crtc;
8234
8235         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8236                 return -ENODEV;
8237
8238         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8239                         DRM_MODE_OBJECT_CRTC);
8240
8241         if (!drmmode_obj) {
8242                 DRM_ERROR("no such CRTC id\n");
8243                 return -EINVAL;
8244         }
8245
8246         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8247         pipe_from_crtc_id->pipe = crtc->pipe;
8248
8249         return 0;
8250 }
8251
8252 static int intel_encoder_clones(struct intel_encoder *encoder)
8253 {
8254         struct drm_device *dev = encoder->base.dev;
8255         struct intel_encoder *source_encoder;
8256         int index_mask = 0;
8257         int entry = 0;
8258
8259         list_for_each_entry(source_encoder,
8260                             &dev->mode_config.encoder_list, base.head) {
8261
8262                 if (encoder == source_encoder)
8263                         index_mask |= (1 << entry);
8264
8265                 /* Intel hw has only one MUX where enocoders could be cloned. */
8266                 if (encoder->cloneable && source_encoder->cloneable)
8267                         index_mask |= (1 << entry);
8268
8269                 entry++;
8270         }
8271
8272         return index_mask;
8273 }
8274
8275 static bool has_edp_a(struct drm_device *dev)
8276 {
8277         struct drm_i915_private *dev_priv = dev->dev_private;
8278
8279         if (!IS_MOBILE(dev))
8280                 return false;
8281
8282         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8283                 return false;
8284
8285         if (IS_GEN5(dev) &&
8286             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8287                 return false;
8288
8289         return true;
8290 }
8291
8292 static void intel_setup_outputs(struct drm_device *dev)
8293 {
8294         struct drm_i915_private *dev_priv = dev->dev_private;
8295         struct intel_encoder *encoder;
8296         bool dpd_is_edp = false;
8297         bool has_lvds;
8298
8299         has_lvds = intel_lvds_init(dev);
8300         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8301                 /* disable the panel fitter on everything but LVDS */
8302                 I915_WRITE(PFIT_CONTROL, 0);
8303         }
8304
8305         if (HAS_PCH_SPLIT(dev)) {
8306                 dpd_is_edp = intel_dpd_is_edp(dev);
8307
8308                 if (has_edp_a(dev))
8309                         intel_dp_init(dev, DP_A, PORT_A);
8310
8311                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8312                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8313         }
8314
8315         intel_crt_init(dev);
8316
8317         if (IS_HASWELL(dev)) {
8318                 int found;
8319
8320                 /* Haswell uses DDI functions to detect digital outputs */
8321                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8322                 /* DDI A only supports eDP */
8323                 if (found)
8324                         intel_ddi_init(dev, PORT_A);
8325
8326                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8327                  * register */
8328                 found = I915_READ(SFUSE_STRAP);
8329
8330                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8331                         intel_ddi_init(dev, PORT_B);
8332                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8333                         intel_ddi_init(dev, PORT_C);
8334                 if (found & SFUSE_STRAP_DDID_DETECTED)
8335                         intel_ddi_init(dev, PORT_D);
8336         } else if (HAS_PCH_SPLIT(dev)) {
8337                 int found;
8338
8339                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8340                         /* PCH SDVOB multiplex with HDMIB */
8341                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8342                         if (!found)
8343                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8344                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8345                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8346                 }
8347
8348                 if (I915_READ(HDMIC) & PORT_DETECTED)
8349                         intel_hdmi_init(dev, HDMIC, PORT_C);
8350
8351                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8352                         intel_hdmi_init(dev, HDMID, PORT_D);
8353
8354                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8355                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8356
8357                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8358                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8359         } else if (IS_VALLEYVIEW(dev)) {
8360                 int found;
8361
8362                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8363                 if (I915_READ(DP_C) & DP_DETECTED)
8364                         intel_dp_init(dev, DP_C, PORT_C);
8365
8366                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8367                         /* SDVOB multiplex with HDMIB */
8368                         found = intel_sdvo_init(dev, SDVOB, true);
8369                         if (!found)
8370                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8371                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8372                                 intel_dp_init(dev, DP_B, PORT_B);
8373                 }
8374
8375                 if (I915_READ(SDVOC) & PORT_DETECTED)
8376                         intel_hdmi_init(dev, SDVOC, PORT_C);
8377
8378         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8379                 bool found = false;
8380
8381                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8382                         DRM_DEBUG_KMS("probing SDVOB\n");
8383                         found = intel_sdvo_init(dev, SDVOB, true);
8384                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8385                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8386                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8387                         }
8388
8389                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8390                                 DRM_DEBUG_KMS("probing DP_B\n");
8391                                 intel_dp_init(dev, DP_B, PORT_B);
8392                         }
8393                 }
8394
8395                 /* Before G4X SDVOC doesn't have its own detect register */
8396
8397                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8398                         DRM_DEBUG_KMS("probing SDVOC\n");
8399                         found = intel_sdvo_init(dev, SDVOC, false);
8400                 }
8401
8402                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8403
8404                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8405                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8406                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8407                         }
8408                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8409                                 DRM_DEBUG_KMS("probing DP_C\n");
8410                                 intel_dp_init(dev, DP_C, PORT_C);
8411                         }
8412                 }
8413
8414                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8415                     (I915_READ(DP_D) & DP_DETECTED)) {
8416                         DRM_DEBUG_KMS("probing DP_D\n");
8417                         intel_dp_init(dev, DP_D, PORT_D);
8418                 }
8419         } else if (IS_GEN2(dev))
8420                 intel_dvo_init(dev);
8421
8422         if (SUPPORTS_TV(dev))
8423                 intel_tv_init(dev);
8424
8425         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8426                 encoder->base.possible_crtcs = encoder->crtc_mask;
8427                 encoder->base.possible_clones =
8428                         intel_encoder_clones(encoder);
8429         }
8430
8431         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8432                 ironlake_init_pch_refclk(dev);
8433 }
8434
8435 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8436 {
8437         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8438
8439         drm_framebuffer_cleanup(fb);
8440         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8441
8442         kfree(intel_fb);
8443 }
8444
8445 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8446                                                 struct drm_file *file,
8447                                                 unsigned int *handle)
8448 {
8449         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8450         struct drm_i915_gem_object *obj = intel_fb->obj;
8451
8452         return drm_gem_handle_create(file, &obj->base, handle);
8453 }
8454
8455 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8456         .destroy = intel_user_framebuffer_destroy,
8457         .create_handle = intel_user_framebuffer_create_handle,
8458 };
8459
8460 int intel_framebuffer_init(struct drm_device *dev,
8461                            struct intel_framebuffer *intel_fb,
8462                            struct drm_mode_fb_cmd2 *mode_cmd,
8463                            struct drm_i915_gem_object *obj)
8464 {
8465         int ret;
8466
8467         if (obj->tiling_mode == I915_TILING_Y)
8468                 return -EINVAL;
8469
8470         if (mode_cmd->pitches[0] & 63)
8471                 return -EINVAL;
8472
8473         /* FIXME <= Gen4 stride limits are bit unclear */
8474         if (mode_cmd->pitches[0] > 32768)
8475                 return -EINVAL;
8476
8477         if (obj->tiling_mode != I915_TILING_NONE &&
8478             mode_cmd->pitches[0] != obj->stride)
8479                 return -EINVAL;
8480
8481         /* Reject formats not supported by any plane early. */
8482         switch (mode_cmd->pixel_format) {
8483         case DRM_FORMAT_C8:
8484         case DRM_FORMAT_RGB565:
8485         case DRM_FORMAT_XRGB8888:
8486         case DRM_FORMAT_ARGB8888:
8487                 break;
8488         case DRM_FORMAT_XRGB1555:
8489         case DRM_FORMAT_ARGB1555:
8490                 if (INTEL_INFO(dev)->gen > 3)
8491                         return -EINVAL;
8492                 break;
8493         case DRM_FORMAT_XBGR8888:
8494         case DRM_FORMAT_ABGR8888:
8495         case DRM_FORMAT_XRGB2101010:
8496         case DRM_FORMAT_ARGB2101010:
8497         case DRM_FORMAT_XBGR2101010:
8498         case DRM_FORMAT_ABGR2101010:
8499                 if (INTEL_INFO(dev)->gen < 4)
8500                         return -EINVAL;
8501                 break;
8502         case DRM_FORMAT_YUYV:
8503         case DRM_FORMAT_UYVY:
8504         case DRM_FORMAT_YVYU:
8505         case DRM_FORMAT_VYUY:
8506                 if (INTEL_INFO(dev)->gen < 6)
8507                         return -EINVAL;
8508                 break;
8509         default:
8510                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8511                 return -EINVAL;
8512         }
8513
8514         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8515         if (mode_cmd->offsets[0] != 0)
8516                 return -EINVAL;
8517
8518         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8519         if (ret) {
8520                 DRM_ERROR("framebuffer init failed %d\n", ret);
8521                 return ret;
8522         }
8523
8524         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8525         intel_fb->obj = obj;
8526         return 0;
8527 }
8528
8529 static struct drm_framebuffer *
8530 intel_user_framebuffer_create(struct drm_device *dev,
8531                               struct drm_file *filp,
8532                               struct drm_mode_fb_cmd2 *mode_cmd)
8533 {
8534         struct drm_i915_gem_object *obj;
8535
8536         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8537                                                 mode_cmd->handles[0]));
8538         if (&obj->base == NULL)
8539                 return ERR_PTR(-ENOENT);
8540
8541         return intel_framebuffer_create(dev, mode_cmd, obj);
8542 }
8543
8544 static const struct drm_mode_config_funcs intel_mode_funcs = {
8545         .fb_create = intel_user_framebuffer_create,
8546         .output_poll_changed = intel_fb_output_poll_changed,
8547 };
8548
8549 /* Set up chip specific display functions */
8550 static void intel_init_display(struct drm_device *dev)
8551 {
8552         struct drm_i915_private *dev_priv = dev->dev_private;
8553
8554         /* We always want a DPMS function */
8555         if (IS_HASWELL(dev)) {
8556                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8557                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8558                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8559                 dev_priv->display.off = haswell_crtc_off;
8560                 dev_priv->display.update_plane = ironlake_update_plane;
8561         } else if (HAS_PCH_SPLIT(dev)) {
8562                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8563                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8564                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8565                 dev_priv->display.off = ironlake_crtc_off;
8566                 dev_priv->display.update_plane = ironlake_update_plane;
8567         } else {
8568                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8569                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8570                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8571                 dev_priv->display.off = i9xx_crtc_off;
8572                 dev_priv->display.update_plane = i9xx_update_plane;
8573         }
8574
8575         /* Returns the core display clock speed */
8576         if (IS_VALLEYVIEW(dev))
8577                 dev_priv->display.get_display_clock_speed =
8578                         valleyview_get_display_clock_speed;
8579         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8580                 dev_priv->display.get_display_clock_speed =
8581                         i945_get_display_clock_speed;
8582         else if (IS_I915G(dev))
8583                 dev_priv->display.get_display_clock_speed =
8584                         i915_get_display_clock_speed;
8585         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8586                 dev_priv->display.get_display_clock_speed =
8587                         i9xx_misc_get_display_clock_speed;
8588         else if (IS_I915GM(dev))
8589                 dev_priv->display.get_display_clock_speed =
8590                         i915gm_get_display_clock_speed;
8591         else if (IS_I865G(dev))
8592                 dev_priv->display.get_display_clock_speed =
8593                         i865_get_display_clock_speed;
8594         else if (IS_I85X(dev))
8595                 dev_priv->display.get_display_clock_speed =
8596                         i855_get_display_clock_speed;
8597         else /* 852, 830 */
8598                 dev_priv->display.get_display_clock_speed =
8599                         i830_get_display_clock_speed;
8600
8601         if (HAS_PCH_SPLIT(dev)) {
8602                 if (IS_GEN5(dev)) {
8603                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8604                         dev_priv->display.write_eld = ironlake_write_eld;
8605                 } else if (IS_GEN6(dev)) {
8606                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8607                         dev_priv->display.write_eld = ironlake_write_eld;
8608                 } else if (IS_IVYBRIDGE(dev)) {
8609                         /* FIXME: detect B0+ stepping and use auto training */
8610                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8611                         dev_priv->display.write_eld = ironlake_write_eld;
8612                         dev_priv->display.modeset_global_resources =
8613                                 ivb_modeset_global_resources;
8614                 } else if (IS_HASWELL(dev)) {
8615                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8616                         dev_priv->display.write_eld = haswell_write_eld;
8617                 } else
8618                         dev_priv->display.update_wm = NULL;
8619         } else if (IS_G4X(dev)) {
8620                 dev_priv->display.write_eld = g4x_write_eld;
8621         }
8622
8623         /* Default just returns -ENODEV to indicate unsupported */
8624         dev_priv->display.queue_flip = intel_default_queue_flip;
8625
8626         switch (INTEL_INFO(dev)->gen) {
8627         case 2:
8628                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8629                 break;
8630
8631         case 3:
8632                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8633                 break;
8634
8635         case 4:
8636         case 5:
8637                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8638                 break;
8639
8640         case 6:
8641                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8642                 break;
8643         case 7:
8644                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8645                 break;
8646         }
8647 }
8648
8649 /*
8650  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8651  * resume, or other times.  This quirk makes sure that's the case for
8652  * affected systems.
8653  */
8654 static void quirk_pipea_force(struct drm_device *dev)
8655 {
8656         struct drm_i915_private *dev_priv = dev->dev_private;
8657
8658         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8659         DRM_INFO("applying pipe a force quirk\n");
8660 }
8661
8662 /*
8663  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8664  */
8665 static void quirk_ssc_force_disable(struct drm_device *dev)
8666 {
8667         struct drm_i915_private *dev_priv = dev->dev_private;
8668         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8669         DRM_INFO("applying lvds SSC disable quirk\n");
8670 }
8671
8672 /*
8673  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8674  * brightness value
8675  */
8676 static void quirk_invert_brightness(struct drm_device *dev)
8677 {
8678         struct drm_i915_private *dev_priv = dev->dev_private;
8679         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8680         DRM_INFO("applying inverted panel brightness quirk\n");
8681 }
8682
8683 struct intel_quirk {
8684         int device;
8685         int subsystem_vendor;
8686         int subsystem_device;
8687         void (*hook)(struct drm_device *dev);
8688 };
8689
8690 static struct intel_quirk intel_quirks[] = {
8691         /* HP Mini needs pipe A force quirk (LP: #322104) */
8692         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8693
8694         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8695         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8696
8697         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8698         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8699
8700         /* 830/845 need to leave pipe A & dpll A up */
8701         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8702         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8703
8704         /* Lenovo U160 cannot use SSC on LVDS */
8705         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8706
8707         /* Sony Vaio Y cannot use SSC on LVDS */
8708         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8709
8710         /* Acer Aspire 5734Z must invert backlight brightness */
8711         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8712 };
8713
8714 static void intel_init_quirks(struct drm_device *dev)
8715 {
8716         struct pci_dev *d = dev->pdev;
8717         int i;
8718
8719         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8720                 struct intel_quirk *q = &intel_quirks[i];
8721
8722                 if (d->device == q->device &&
8723                     (d->subsystem_vendor == q->subsystem_vendor ||
8724                      q->subsystem_vendor == PCI_ANY_ID) &&
8725                     (d->subsystem_device == q->subsystem_device ||
8726                      q->subsystem_device == PCI_ANY_ID))
8727                         q->hook(dev);
8728         }
8729 }
8730
8731 /* Disable the VGA plane that we never use */
8732 static void i915_disable_vga(struct drm_device *dev)
8733 {
8734         struct drm_i915_private *dev_priv = dev->dev_private;
8735         u8 sr1;
8736         u32 vga_reg;
8737
8738         if (HAS_PCH_SPLIT(dev))
8739                 vga_reg = CPU_VGACNTRL;
8740         else
8741                 vga_reg = VGACNTRL;
8742
8743         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8744         outb(SR01, VGA_SR_INDEX);
8745         sr1 = inb(VGA_SR_DATA);
8746         outb(sr1 | 1<<5, VGA_SR_DATA);
8747         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8748         udelay(300);
8749
8750         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8751         POSTING_READ(vga_reg);
8752 }
8753
8754 void intel_modeset_init_hw(struct drm_device *dev)
8755 {
8756         /* We attempt to init the necessary power wells early in the initialization
8757          * time, so the subsystems that expect power to be enabled can work.
8758          */
8759         intel_init_power_wells(dev);
8760
8761         intel_prepare_ddi(dev);
8762
8763         intel_init_clock_gating(dev);
8764
8765         mutex_lock(&dev->struct_mutex);
8766         intel_enable_gt_powersave(dev);
8767         mutex_unlock(&dev->struct_mutex);
8768 }
8769
8770 void intel_modeset_init(struct drm_device *dev)
8771 {
8772         struct drm_i915_private *dev_priv = dev->dev_private;
8773         int i, ret;
8774
8775         drm_mode_config_init(dev);
8776
8777         dev->mode_config.min_width = 0;
8778         dev->mode_config.min_height = 0;
8779
8780         dev->mode_config.preferred_depth = 24;
8781         dev->mode_config.prefer_shadow = 1;
8782
8783         dev->mode_config.funcs = &intel_mode_funcs;
8784
8785         intel_init_quirks(dev);
8786
8787         intel_init_pm(dev);
8788
8789         intel_init_display(dev);
8790
8791         if (IS_GEN2(dev)) {
8792                 dev->mode_config.max_width = 2048;
8793                 dev->mode_config.max_height = 2048;
8794         } else if (IS_GEN3(dev)) {
8795                 dev->mode_config.max_width = 4096;
8796                 dev->mode_config.max_height = 4096;
8797         } else {
8798                 dev->mode_config.max_width = 8192;
8799                 dev->mode_config.max_height = 8192;
8800         }
8801         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8802
8803         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8804                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8805
8806         for (i = 0; i < dev_priv->num_pipe; i++) {
8807                 intel_crtc_init(dev, i);
8808                 ret = intel_plane_init(dev, i);
8809                 if (ret)
8810                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8811         }
8812
8813         intel_cpu_pll_init(dev);
8814         intel_pch_pll_init(dev);
8815
8816         /* Just disable it once at startup */
8817         i915_disable_vga(dev);
8818         intel_setup_outputs(dev);
8819 }
8820
8821 static void
8822 intel_connector_break_all_links(struct intel_connector *connector)
8823 {
8824         connector->base.dpms = DRM_MODE_DPMS_OFF;
8825         connector->base.encoder = NULL;
8826         connector->encoder->connectors_active = false;
8827         connector->encoder->base.crtc = NULL;
8828 }
8829
8830 static void intel_enable_pipe_a(struct drm_device *dev)
8831 {
8832         struct intel_connector *connector;
8833         struct drm_connector *crt = NULL;
8834         struct intel_load_detect_pipe load_detect_temp;
8835
8836         /* We can't just switch on the pipe A, we need to set things up with a
8837          * proper mode and output configuration. As a gross hack, enable pipe A
8838          * by enabling the load detect pipe once. */
8839         list_for_each_entry(connector,
8840                             &dev->mode_config.connector_list,
8841                             base.head) {
8842                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8843                         crt = &connector->base;
8844                         break;
8845                 }
8846         }
8847
8848         if (!crt)
8849                 return;
8850
8851         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8852                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8853
8854
8855 }
8856
8857 static bool
8858 intel_check_plane_mapping(struct intel_crtc *crtc)
8859 {
8860         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8861         u32 reg, val;
8862
8863         if (dev_priv->num_pipe == 1)
8864                 return true;
8865
8866         reg = DSPCNTR(!crtc->plane);
8867         val = I915_READ(reg);
8868
8869         if ((val & DISPLAY_PLANE_ENABLE) &&
8870             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8871                 return false;
8872
8873         return true;
8874 }
8875
8876 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8877 {
8878         struct drm_device *dev = crtc->base.dev;
8879         struct drm_i915_private *dev_priv = dev->dev_private;
8880         u32 reg;
8881
8882         /* Clear any frame start delays used for debugging left by the BIOS */
8883         reg = PIPECONF(crtc->cpu_transcoder);
8884         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8885
8886         /* We need to sanitize the plane -> pipe mapping first because this will
8887          * disable the crtc (and hence change the state) if it is wrong. Note
8888          * that gen4+ has a fixed plane -> pipe mapping.  */
8889         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8890                 struct intel_connector *connector;
8891                 bool plane;
8892
8893                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8894                               crtc->base.base.id);
8895
8896                 /* Pipe has the wrong plane attached and the plane is active.
8897                  * Temporarily change the plane mapping and disable everything
8898                  * ...  */
8899                 plane = crtc->plane;
8900                 crtc->plane = !plane;
8901                 dev_priv->display.crtc_disable(&crtc->base);
8902                 crtc->plane = plane;
8903
8904                 /* ... and break all links. */
8905                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8906                                     base.head) {
8907                         if (connector->encoder->base.crtc != &crtc->base)
8908                                 continue;
8909
8910                         intel_connector_break_all_links(connector);
8911                 }
8912
8913                 WARN_ON(crtc->active);
8914                 crtc->base.enabled = false;
8915         }
8916
8917         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8918             crtc->pipe == PIPE_A && !crtc->active) {
8919                 /* BIOS forgot to enable pipe A, this mostly happens after
8920                  * resume. Force-enable the pipe to fix this, the update_dpms
8921                  * call below we restore the pipe to the right state, but leave
8922                  * the required bits on. */
8923                 intel_enable_pipe_a(dev);
8924         }
8925
8926         /* Adjust the state of the output pipe according to whether we
8927          * have active connectors/encoders. */
8928         intel_crtc_update_dpms(&crtc->base);
8929
8930         if (crtc->active != crtc->base.enabled) {
8931                 struct intel_encoder *encoder;
8932
8933                 /* This can happen either due to bugs in the get_hw_state
8934                  * functions or because the pipe is force-enabled due to the
8935                  * pipe A quirk. */
8936                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8937                               crtc->base.base.id,
8938                               crtc->base.enabled ? "enabled" : "disabled",
8939                               crtc->active ? "enabled" : "disabled");
8940
8941                 crtc->base.enabled = crtc->active;
8942
8943                 /* Because we only establish the connector -> encoder ->
8944                  * crtc links if something is active, this means the
8945                  * crtc is now deactivated. Break the links. connector
8946                  * -> encoder links are only establish when things are
8947                  *  actually up, hence no need to break them. */
8948                 WARN_ON(crtc->active);
8949
8950                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8951                         WARN_ON(encoder->connectors_active);
8952                         encoder->base.crtc = NULL;
8953                 }
8954         }
8955 }
8956
8957 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8958 {
8959         struct intel_connector *connector;
8960         struct drm_device *dev = encoder->base.dev;
8961
8962         /* We need to check both for a crtc link (meaning that the
8963          * encoder is active and trying to read from a pipe) and the
8964          * pipe itself being active. */
8965         bool has_active_crtc = encoder->base.crtc &&
8966                 to_intel_crtc(encoder->base.crtc)->active;
8967
8968         if (encoder->connectors_active && !has_active_crtc) {
8969                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8970                               encoder->base.base.id,
8971                               drm_get_encoder_name(&encoder->base));
8972
8973                 /* Connector is active, but has no active pipe. This is
8974                  * fallout from our resume register restoring. Disable
8975                  * the encoder manually again. */
8976                 if (encoder->base.crtc) {
8977                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8978                                       encoder->base.base.id,
8979                                       drm_get_encoder_name(&encoder->base));
8980                         encoder->disable(encoder);
8981                 }
8982
8983                 /* Inconsistent output/port/pipe state happens presumably due to
8984                  * a bug in one of the get_hw_state functions. Or someplace else
8985                  * in our code, like the register restore mess on resume. Clamp
8986                  * things to off as a safer default. */
8987                 list_for_each_entry(connector,
8988                                     &dev->mode_config.connector_list,
8989                                     base.head) {
8990                         if (connector->encoder != encoder)
8991                                 continue;
8992
8993                         intel_connector_break_all_links(connector);
8994                 }
8995         }
8996         /* Enabled encoders without active connectors will be fixed in
8997          * the crtc fixup. */
8998 }
8999
9000 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9001  * and i915 state tracking structures. */
9002 void intel_modeset_setup_hw_state(struct drm_device *dev)
9003 {
9004         struct drm_i915_private *dev_priv = dev->dev_private;
9005         enum pipe pipe;
9006         u32 tmp;
9007         struct intel_crtc *crtc;
9008         struct intel_encoder *encoder;
9009         struct intel_connector *connector;
9010
9011         if (IS_HASWELL(dev)) {
9012                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9013
9014                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9015                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9016                         case TRANS_DDI_EDP_INPUT_A_ON:
9017                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9018                                 pipe = PIPE_A;
9019                                 break;
9020                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9021                                 pipe = PIPE_B;
9022                                 break;
9023                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9024                                 pipe = PIPE_C;
9025                                 break;
9026                         }
9027
9028                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9029                         crtc->cpu_transcoder = TRANSCODER_EDP;
9030
9031                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9032                                       pipe_name(pipe));
9033                 }
9034         }
9035
9036         for_each_pipe(pipe) {
9037                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9038
9039                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9040                 if (tmp & PIPECONF_ENABLE)
9041                         crtc->active = true;
9042                 else
9043                         crtc->active = false;
9044
9045                 crtc->base.enabled = crtc->active;
9046
9047                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9048                               crtc->base.base.id,
9049                               crtc->active ? "enabled" : "disabled");
9050         }
9051
9052         if (IS_HASWELL(dev))
9053                 intel_ddi_setup_hw_pll_state(dev);
9054
9055         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9056                             base.head) {
9057                 pipe = 0;
9058
9059                 if (encoder->get_hw_state(encoder, &pipe)) {
9060                         encoder->base.crtc =
9061                                 dev_priv->pipe_to_crtc_mapping[pipe];
9062                 } else {
9063                         encoder->base.crtc = NULL;
9064                 }
9065
9066                 encoder->connectors_active = false;
9067                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9068                               encoder->base.base.id,
9069                               drm_get_encoder_name(&encoder->base),
9070                               encoder->base.crtc ? "enabled" : "disabled",
9071                               pipe);
9072         }
9073
9074         list_for_each_entry(connector, &dev->mode_config.connector_list,
9075                             base.head) {
9076                 if (connector->get_hw_state(connector)) {
9077                         connector->base.dpms = DRM_MODE_DPMS_ON;
9078                         connector->encoder->connectors_active = true;
9079                         connector->base.encoder = &connector->encoder->base;
9080                 } else {
9081                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9082                         connector->base.encoder = NULL;
9083                 }
9084                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9085                               connector->base.base.id,
9086                               drm_get_connector_name(&connector->base),
9087                               connector->base.encoder ? "enabled" : "disabled");
9088         }
9089
9090         /* HW state is read out, now we need to sanitize this mess. */
9091         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9092                             base.head) {
9093                 intel_sanitize_encoder(encoder);
9094         }
9095
9096         for_each_pipe(pipe) {
9097                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9098                 intel_sanitize_crtc(crtc);
9099         }
9100
9101         intel_modeset_update_staged_output_state(dev);
9102
9103         intel_modeset_check_state(dev);
9104
9105         drm_mode_config_reset(dev);
9106 }
9107
9108 void intel_modeset_gem_init(struct drm_device *dev)
9109 {
9110         intel_modeset_init_hw(dev);
9111
9112         intel_setup_overlay(dev);
9113
9114         intel_modeset_setup_hw_state(dev);
9115 }
9116
9117 void intel_modeset_cleanup(struct drm_device *dev)
9118 {
9119         struct drm_i915_private *dev_priv = dev->dev_private;
9120         struct drm_crtc *crtc;
9121         struct intel_crtc *intel_crtc;
9122
9123         drm_kms_helper_poll_fini(dev);
9124         mutex_lock(&dev->struct_mutex);
9125
9126         intel_unregister_dsm_handler();
9127
9128
9129         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9130                 /* Skip inactive CRTCs */
9131                 if (!crtc->fb)
9132                         continue;
9133
9134                 intel_crtc = to_intel_crtc(crtc);
9135                 intel_increase_pllclock(crtc);
9136         }
9137
9138         intel_disable_fbc(dev);
9139
9140         intel_disable_gt_powersave(dev);
9141
9142         ironlake_teardown_rc6(dev);
9143
9144         if (IS_VALLEYVIEW(dev))
9145                 vlv_init_dpio(dev);
9146
9147         mutex_unlock(&dev->struct_mutex);
9148
9149         /* Disable the irq before mode object teardown, for the irq might
9150          * enqueue unpin/hotplug work. */
9151         drm_irq_uninstall(dev);
9152         cancel_work_sync(&dev_priv->hotplug_work);
9153         cancel_work_sync(&dev_priv->rps.work);
9154
9155         /* flush any delayed tasks or pending work */
9156         flush_scheduled_work();
9157
9158         drm_mode_config_cleanup(dev);
9159 }
9160
9161 /*
9162  * Return which encoder is currently attached for connector.
9163  */
9164 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9165 {
9166         return &intel_attached_encoder(connector)->base;
9167 }
9168
9169 void intel_connector_attach_encoder(struct intel_connector *connector,
9170                                     struct intel_encoder *encoder)
9171 {
9172         connector->encoder = encoder;
9173         drm_mode_connector_attach_encoder(&connector->base,
9174                                           &encoder->base);
9175 }
9176
9177 /*
9178  * set vga decode state - true == enable VGA decode
9179  */
9180 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9181 {
9182         struct drm_i915_private *dev_priv = dev->dev_private;
9183         u16 gmch_ctrl;
9184
9185         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9186         if (state)
9187                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9188         else
9189                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9190         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9191         return 0;
9192 }
9193
9194 #ifdef CONFIG_DEBUG_FS
9195 #include <linux/seq_file.h>
9196
9197 struct intel_display_error_state {
9198         struct intel_cursor_error_state {
9199                 u32 control;
9200                 u32 position;
9201                 u32 base;
9202                 u32 size;
9203         } cursor[I915_MAX_PIPES];
9204
9205         struct intel_pipe_error_state {
9206                 u32 conf;
9207                 u32 source;
9208
9209                 u32 htotal;
9210                 u32 hblank;
9211                 u32 hsync;
9212                 u32 vtotal;
9213                 u32 vblank;
9214                 u32 vsync;
9215         } pipe[I915_MAX_PIPES];
9216
9217         struct intel_plane_error_state {
9218                 u32 control;
9219                 u32 stride;
9220                 u32 size;
9221                 u32 pos;
9222                 u32 addr;
9223                 u32 surface;
9224                 u32 tile_offset;
9225         } plane[I915_MAX_PIPES];
9226 };
9227
9228 struct intel_display_error_state *
9229 intel_display_capture_error_state(struct drm_device *dev)
9230 {
9231         drm_i915_private_t *dev_priv = dev->dev_private;
9232         struct intel_display_error_state *error;
9233         enum transcoder cpu_transcoder;
9234         int i;
9235
9236         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9237         if (error == NULL)
9238                 return NULL;
9239
9240         for_each_pipe(i) {
9241                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9242
9243                 error->cursor[i].control = I915_READ(CURCNTR(i));
9244                 error->cursor[i].position = I915_READ(CURPOS(i));
9245                 error->cursor[i].base = I915_READ(CURBASE(i));
9246
9247                 error->plane[i].control = I915_READ(DSPCNTR(i));
9248                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9249                 error->plane[i].size = I915_READ(DSPSIZE(i));
9250                 error->plane[i].pos = I915_READ(DSPPOS(i));
9251                 error->plane[i].addr = I915_READ(DSPADDR(i));
9252                 if (INTEL_INFO(dev)->gen >= 4) {
9253                         error->plane[i].surface = I915_READ(DSPSURF(i));
9254                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9255                 }
9256
9257                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9258                 error->pipe[i].source = I915_READ(PIPESRC(i));
9259                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9260                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9261                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9262                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9263                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9264                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9265         }
9266
9267         return error;
9268 }
9269
9270 void
9271 intel_display_print_error_state(struct seq_file *m,
9272                                 struct drm_device *dev,
9273                                 struct intel_display_error_state *error)
9274 {
9275         drm_i915_private_t *dev_priv = dev->dev_private;
9276         int i;
9277
9278         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9279         for_each_pipe(i) {
9280                 seq_printf(m, "Pipe [%d]:\n", i);
9281                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9282                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9283                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9284                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9285                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9286                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9287                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9288                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9289
9290                 seq_printf(m, "Plane [%d]:\n", i);
9291                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9292                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9293                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9294                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9295                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9296                 if (INTEL_INFO(dev)->gen >= 4) {
9297                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9298                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9299                 }
9300
9301                 seq_printf(m, "Cursor [%d]:\n", i);
9302                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9303                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9304                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9305         }
9306 }
9307 #endif