Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62 };
  63
  64 /* FDI */
  65 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  66
  67 int
  68 intel_pch_rawclk(struct drm_device *dev)
  69 {
  70         struct drm_i915_private *dev_priv = dev->dev_private;
  71
  72         WARN_ON(!HAS_PCH_SPLIT(dev));
  73
  74         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  75 }
  76
  77 static inline u32 /* units of 100MHz */
  78 intel_fdi_link_freq(struct drm_device *dev)
  79 {
  80         if (IS_GEN5(dev)) {
  81                 struct drm_i915_private *dev_priv = dev->dev_private;
  82                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  83         } else
  84                 return 27;
  85 }
  86
  87 static const intel_limit_t intel_limits_i8xx_dvo = {
  88         .dot = { .min = 25000, .max = 350000 },
  89         .vco = { .min = 930000, .max = 1400000 },
  90         .n = { .min = 3, .max = 16 },
  91         .m = { .min = 96, .max = 140 },
  92         .m1 = { .min = 18, .max = 26 },
  93         .m2 = { .min = 6, .max = 16 },
  94         .p = { .min = 4, .max = 128 },
  95         .p1 = { .min = 2, .max = 33 },
  96         .p2 = { .dot_limit = 165000,
  97                 .p2_slow = 4, .p2_fast = 2 },
  98 };
  99
 100 static const intel_limit_t intel_limits_i8xx_lvds = {
 101         .dot = { .min = 25000, .max = 350000 },
 102         .vco = { .min = 930000, .max = 1400000 },
 103         .n = { .min = 3, .max = 16 },
 104         .m = { .min = 96, .max = 140 },
 105         .m1 = { .min = 18, .max = 26 },
 106         .m2 = { .min = 6, .max = 16 },
 107         .p = { .min = 4, .max = 128 },
 108         .p1 = { .min = 1, .max = 6 },
 109         .p2 = { .dot_limit = 165000,
 110                 .p2_slow = 14, .p2_fast = 7 },
 111 };
 112
 113 static const intel_limit_t intel_limits_i9xx_sdvo = {
 114         .dot = { .min = 20000, .max = 400000 },
 115         .vco = { .min = 1400000, .max = 2800000 },
 116         .n = { .min = 1, .max = 6 },
 117         .m = { .min = 70, .max = 120 },
 118         .m1 = { .min = 8, .max = 18 },
 119         .m2 = { .min = 3, .max = 7 },
 120         .p = { .min = 5, .max = 80 },
 121         .p1 = { .min = 1, .max = 8 },
 122         .p2 = { .dot_limit = 200000,
 123                 .p2_slow = 10, .p2_fast = 5 },
 124 };
 125
 126 static const intel_limit_t intel_limits_i9xx_lvds = {
 127         .dot = { .min = 20000, .max = 400000 },
 128         .vco = { .min = 1400000, .max = 2800000 },
 129         .n = { .min = 1, .max = 6 },
 130         .m = { .min = 70, .max = 120 },
 131         .m1 = { .min = 8, .max = 18 },
 132         .m2 = { .min = 3, .max = 7 },
 133         .p = { .min = 7, .max = 98 },
 134         .p1 = { .min = 1, .max = 8 },
 135         .p2 = { .dot_limit = 112000,
 136                 .p2_slow = 14, .p2_fast = 7 },
 137 };
 138
 139
 140 static const intel_limit_t intel_limits_g4x_sdvo = {
 141         .dot = { .min = 25000, .max = 270000 },
 142         .vco = { .min = 1750000, .max = 3500000},
 143         .n = { .min = 1, .max = 4 },
 144         .m = { .min = 104, .max = 138 },
 145         .m1 = { .min = 17, .max = 23 },
 146         .m2 = { .min = 5, .max = 11 },
 147         .p = { .min = 10, .max = 30 },
 148         .p1 = { .min = 1, .max = 3},
 149         .p2 = { .dot_limit = 270000,
 150                 .p2_slow = 10,
 151                 .p2_fast = 10
 152         },
 153 };
 154
 155 static const intel_limit_t intel_limits_g4x_hdmi = {
 156         .dot = { .min = 22000, .max = 400000 },
 157         .vco = { .min = 1750000, .max = 3500000},
 158         .n = { .min = 1, .max = 4 },
 159         .m = { .min = 104, .max = 138 },
 160         .m1 = { .min = 16, .max = 23 },
 161         .m2 = { .min = 5, .max = 11 },
 162         .p = { .min = 5, .max = 80 },
 163         .p1 = { .min = 1, .max = 8},
 164         .p2 = { .dot_limit = 165000,
 165                 .p2_slow = 10, .p2_fast = 5 },
 166 };
 167
 168 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 169         .dot = { .min = 20000, .max = 115000 },
 170         .vco = { .min = 1750000, .max = 3500000 },
 171         .n = { .min = 1, .max = 3 },
 172         .m = { .min = 104, .max = 138 },
 173         .m1 = { .min = 17, .max = 23 },
 174         .m2 = { .min = 5, .max = 11 },
 175         .p = { .min = 28, .max = 112 },
 176         .p1 = { .min = 2, .max = 8 },
 177         .p2 = { .dot_limit = 0,
 178                 .p2_slow = 14, .p2_fast = 14
 179         },
 180 };
 181
 182 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 183         .dot = { .min = 80000, .max = 224000 },
 184         .vco = { .min = 1750000, .max = 3500000 },
 185         .n = { .min = 1, .max = 3 },
 186         .m = { .min = 104, .max = 138 },
 187         .m1 = { .min = 17, .max = 23 },
 188         .m2 = { .min = 5, .max = 11 },
 189         .p = { .min = 14, .max = 42 },
 190         .p1 = { .min = 2, .max = 6 },
 191         .p2 = { .dot_limit = 0,
 192                 .p2_slow = 7, .p2_fast = 7
 193         },
 194 };
 195
 196 static const intel_limit_t intel_limits_pineview_sdvo = {
 197         .dot = { .min = 20000, .max = 400000},
 198         .vco = { .min = 1700000, .max = 3500000 },
 199         /* Pineview's Ncounter is a ring counter */
 200         .n = { .min = 3, .max = 6 },
 201         .m = { .min = 2, .max = 256 },
 202         /* Pineview only has one combined m divider, which we treat as m2. */
 203         .m1 = { .min = 0, .max = 0 },
 204         .m2 = { .min = 0, .max = 254 },
 205         .p = { .min = 5, .max = 80 },
 206         .p1 = { .min = 1, .max = 8 },
 207         .p2 = { .dot_limit = 200000,
 208                 .p2_slow = 10, .p2_fast = 5 },
 209 };
 210
 211 static const intel_limit_t intel_limits_pineview_lvds = {
 212         .dot = { .min = 20000, .max = 400000 },
 213         .vco = { .min = 1700000, .max = 3500000 },
 214         .n = { .min = 3, .max = 6 },
 215         .m = { .min = 2, .max = 256 },
 216         .m1 = { .min = 0, .max = 0 },
 217         .m2 = { .min = 0, .max = 254 },
 218         .p = { .min = 7, .max = 112 },
 219         .p1 = { .min = 1, .max = 8 },
 220         .p2 = { .dot_limit = 112000,
 221                 .p2_slow = 14, .p2_fast = 14 },
 222 };
 223
 224 /* Ironlake / Sandybridge
 225  *
 226  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 227  * the range value for them is (actual_value - 2).
 228  */
 229 static const intel_limit_t intel_limits_ironlake_dac = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 1760000, .max = 3510000 },
 232         .n = { .min = 1, .max = 5 },
 233         .m = { .min = 79, .max = 127 },
 234         .m1 = { .min = 12, .max = 22 },
 235         .m2 = { .min = 5, .max = 9 },
 236         .p = { .min = 5, .max = 80 },
 237         .p1 = { .min = 1, .max = 8 },
 238         .p2 = { .dot_limit = 225000,
 239                 .p2_slow = 10, .p2_fast = 5 },
 240 };
 241
 242 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 243         .dot = { .min = 25000, .max = 350000 },
 244         .vco = { .min = 1760000, .max = 3510000 },
 245         .n = { .min = 1, .max = 3 },
 246         .m = { .min = 79, .max = 118 },
 247         .m1 = { .min = 12, .max = 22 },
 248         .m2 = { .min = 5, .max = 9 },
 249         .p = { .min = 28, .max = 112 },
 250         .p1 = { .min = 2, .max = 8 },
 251         .p2 = { .dot_limit = 225000,
 252                 .p2_slow = 14, .p2_fast = 14 },
 253 };
 254
 255 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 256         .dot = { .min = 25000, .max = 350000 },
 257         .vco = { .min = 1760000, .max = 3510000 },
 258         .n = { .min = 1, .max = 3 },
 259         .m = { .min = 79, .max = 127 },
 260         .m1 = { .min = 12, .max = 22 },
 261         .m2 = { .min = 5, .max = 9 },
 262         .p = { .min = 14, .max = 56 },
 263         .p1 = { .min = 2, .max = 8 },
 264         .p2 = { .dot_limit = 225000,
 265                 .p2_slow = 7, .p2_fast = 7 },
 266 };
 267
 268 /* LVDS 100mhz refclk limits. */
 269 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 270         .dot = { .min = 25000, .max = 350000 },
 271         .vco = { .min = 1760000, .max = 3510000 },
 272         .n = { .min = 1, .max = 2 },
 273         .m = { .min = 79, .max = 126 },
 274         .m1 = { .min = 12, .max = 22 },
 275         .m2 = { .min = 5, .max = 9 },
 276         .p = { .min = 28, .max = 112 },
 277         .p1 = { .min = 2, .max = 8 },
 278         .p2 = { .dot_limit = 225000,
 279                 .p2_slow = 14, .p2_fast = 14 },
 280 };
 281
 282 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 283         .dot = { .min = 25000, .max = 350000 },
 284         .vco = { .min = 1760000, .max = 3510000 },
 285         .n = { .min = 1, .max = 3 },
 286         .m = { .min = 79, .max = 126 },
 287         .m1 = { .min = 12, .max = 22 },
 288         .m2 = { .min = 5, .max = 9 },
 289         .p = { .min = 14, .max = 42 },
 290         .p1 = { .min = 2, .max = 6 },
 291         .p2 = { .dot_limit = 225000,
 292                 .p2_slow = 7, .p2_fast = 7 },
 293 };
 294
 295 static const intel_limit_t intel_limits_vlv_dac = {
 296         .dot = { .min = 25000, .max = 270000 },
 297         .vco = { .min = 4000000, .max = 6000000 },
 298         .n = { .min = 1, .max = 7 },
 299         .m = { .min = 22, .max = 450 }, /* guess */
 300         .m1 = { .min = 2, .max = 3 },
 301         .m2 = { .min = 11, .max = 156 },
 302         .p = { .min = 10, .max = 30 },
 303         .p1 = { .min = 1, .max = 3 },
 304         .p2 = { .dot_limit = 270000,
 305                 .p2_slow = 2, .p2_fast = 20 },
 306 };
 307
 308 static const intel_limit_t intel_limits_vlv_hdmi = {
 309         .dot = { .min = 25000, .max = 270000 },
 310         .vco = { .min = 4000000, .max = 6000000 },
 311         .n = { .min = 1, .max = 7 },
 312         .m = { .min = 60, .max = 300 }, /* guess */
 313         .m1 = { .min = 2, .max = 3 },
 314         .m2 = { .min = 11, .max = 156 },
 315         .p = { .min = 10, .max = 30 },
 316         .p1 = { .min = 2, .max = 3 },
 317         .p2 = { .dot_limit = 270000,
 318                 .p2_slow = 2, .p2_fast = 20 },
 319 };
 320
 321 static const intel_limit_t intel_limits_vlv_dp = {
 322         .dot = { .min = 25000, .max = 270000 },
 323         .vco = { .min = 4000000, .max = 6000000 },
 324         .n = { .min = 1, .max = 7 },
 325         .m = { .min = 22, .max = 450 },
 326         .m1 = { .min = 2, .max = 3 },
 327         .m2 = { .min = 11, .max = 156 },
 328         .p = { .min = 10, .max = 30 },
 329         .p1 = { .min = 1, .max = 3 },
 330         .p2 = { .dot_limit = 270000,
 331                 .p2_slow = 2, .p2_fast = 20 },
 332 };
 333
 334 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 335                                                 int refclk)
 336 {
 337         struct drm_device *dev = crtc->dev;
 338         const intel_limit_t *limit;
 339
 340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 341                 if (intel_is_dual_link_lvds(dev)) {
 342                         if (refclk == 100000)
 343                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 344                         else
 345                                 limit = &intel_limits_ironlake_dual_lvds;
 346                 } else {
 347                         if (refclk == 100000)
 348                                 limit = &intel_limits_ironlake_single_lvds_100m;
 349                         else
 350                                 limit = &intel_limits_ironlake_single_lvds;
 351                 }
 352         } else
 353                 limit = &intel_limits_ironlake_dac;
 354
 355         return limit;
 356 }
 357
 358 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 359 {
 360         struct drm_device *dev = crtc->dev;
 361         const intel_limit_t *limit;
 362
 363         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 364                 if (intel_is_dual_link_lvds(dev))
 365                         limit = &intel_limits_g4x_dual_channel_lvds;
 366                 else
 367                         limit = &intel_limits_g4x_single_channel_lvds;
 368         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 369                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 370                 limit = &intel_limits_g4x_hdmi;
 371         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 372                 limit = &intel_limits_g4x_sdvo;
 373         } else /* The option is for other outputs */
 374                 limit = &intel_limits_i9xx_sdvo;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (HAS_PCH_SPLIT(dev))
 385                 limit = intel_ironlake_limit(crtc, refclk);
 386         else if (IS_G4X(dev)) {
 387                 limit = intel_g4x_limit(crtc);
 388         } else if (IS_PINEVIEW(dev)) {
 389                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 390                         limit = &intel_limits_pineview_lvds;
 391                 else
 392                         limit = &intel_limits_pineview_sdvo;
 393         } else if (IS_VALLEYVIEW(dev)) {
 394                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 395                         limit = &intel_limits_vlv_dac;
 396                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 397                         limit = &intel_limits_vlv_hdmi;
 398                 else
 399                         limit = &intel_limits_vlv_dp;
 400         } else if (!IS_GEN2(dev)) {
 401                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 402                         limit = &intel_limits_i9xx_lvds;
 403                 else
 404                         limit = &intel_limits_i9xx_sdvo;
 405         } else {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_i8xx_lvds;
 408                 else
 409                         limit = &intel_limits_i8xx_dvo;
 410         }
 411         return limit;
 412 }
 413
 414 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 415 static void pineview_clock(int refclk, intel_clock_t *clock)
 416 {
 417         clock->m = clock->m2 + 2;
 418         clock->p = clock->p1 * clock->p2;
 419         clock->vco = refclk * clock->m / clock->n;
 420         clock->dot = clock->vco / clock->p;
 421 }
 422
 423 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 424 {
 425         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 426 }
 427
 428 static void i9xx_clock(int refclk, intel_clock_t *clock)
 429 {
 430         clock->m = i9xx_dpll_compute_m(clock);
 431         clock->p = clock->p1 * clock->p2;
 432         clock->vco = refclk * clock->m / (clock->n + 2);
 433         clock->dot = clock->vco / clock->p;
 434 }
 435
 436 /**
 437  * Returns whether any output on the specified pipe is of the specified type
 438  */
 439 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 440 {
 441         struct drm_device *dev = crtc->dev;
 442         struct intel_encoder *encoder;
 443
 444         for_each_encoder_on_crtc(dev, crtc, encoder)
 445                 if (encoder->type == type)
 446                         return true;
 447
 448         return false;
 449 }
 450
 451 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 452 /**
 453  * Returns whether the given set of divisors are valid for a given refclk with
 454  * the given connectors.
 455  */
 456
 457 static bool intel_PLL_is_valid(struct drm_device *dev,
 458                                const intel_limit_t *limit,
 459                                const intel_clock_t *clock)
 460 {
 461         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 462                 INTELPllInvalid("p1 out of range\n");
 463         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 464                 INTELPllInvalid("p out of range\n");
 465         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 466                 INTELPllInvalid("m2 out of range\n");
 467         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 468                 INTELPllInvalid("m1 out of range\n");
 469         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 470                 INTELPllInvalid("m1 <= m2\n");
 471         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 472                 INTELPllInvalid("m out of range\n");
 473         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 474                 INTELPllInvalid("n out of range\n");
 475         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 476                 INTELPllInvalid("vco out of range\n");
 477         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 478          * connector, etc., rather than just a single range.
 479          */
 480         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 481                 INTELPllInvalid("dot out of range\n");
 482
 483         return true;
 484 }
 485
 486 static bool
 487 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 488                     int target, int refclk, intel_clock_t *match_clock,
 489                     intel_clock_t *best_clock)
 490 {
 491         struct drm_device *dev = crtc->dev;
 492         intel_clock_t clock;
 493         int err = target;
 494
 495         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 496                 /*
 497                  * For LVDS just rely on its current settings for dual-channel.
 498                  * We haven't figured out how to reliably set up different
 499                  * single/dual channel state, if we even can.
 500                  */
 501                 if (intel_is_dual_link_lvds(dev))
 502                         clock.p2 = limit->p2.p2_fast;
 503                 else
 504                         clock.p2 = limit->p2.p2_slow;
 505         } else {
 506                 if (target < limit->p2.dot_limit)
 507                         clock.p2 = limit->p2.p2_slow;
 508                 else
 509                         clock.p2 = limit->p2.p2_fast;
 510         }
 511
 512         memset(best_clock, 0, sizeof(*best_clock));
 513
 514         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 515              clock.m1++) {
 516                 for (clock.m2 = limit->m2.min;
 517                      clock.m2 <= limit->m2.max; clock.m2++) {
 518                         if (clock.m2 >= clock.m1)
 519                                 break;
 520                         for (clock.n = limit->n.min;
 521                              clock.n <= limit->n.max; clock.n++) {
 522                                 for (clock.p1 = limit->p1.min;
 523                                         clock.p1 <= limit->p1.max; clock.p1++) {
 524                                         int this_err;
 525
 526                                         i9xx_clock(refclk, &clock);
 527                                         if (!intel_PLL_is_valid(dev, limit,
 528                                                                 &clock))
 529                                                 continue;
 530                                         if (match_clock &&
 531                                             clock.p != match_clock->p)
 532                                                 continue;
 533
 534                                         this_err = abs(clock.dot - target);
 535                                         if (this_err < err) {
 536                                                 *best_clock = clock;
 537                                                 err = this_err;
 538                                         }
 539                                 }
 540                         }
 541                 }
 542         }
 543
 544         return (err != target);
 545 }
 546
 547 static bool
 548 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 549                    int target, int refclk, intel_clock_t *match_clock,
 550                    intel_clock_t *best_clock)
 551 {
 552         struct drm_device *dev = crtc->dev;
 553         intel_clock_t clock;
 554         int err = target;
 555
 556         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 557                 /*
 558                  * For LVDS just rely on its current settings for dual-channel.
 559                  * We haven't figured out how to reliably set up different
 560                  * single/dual channel state, if we even can.
 561                  */
 562                 if (intel_is_dual_link_lvds(dev))
 563                         clock.p2 = limit->p2.p2_fast;
 564                 else
 565                         clock.p2 = limit->p2.p2_slow;
 566         } else {
 567                 if (target < limit->p2.dot_limit)
 568                         clock.p2 = limit->p2.p2_slow;
 569                 else
 570                         clock.p2 = limit->p2.p2_fast;
 571         }
 572
 573         memset(best_clock, 0, sizeof(*best_clock));
 574
 575         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 576              clock.m1++) {
 577                 for (clock.m2 = limit->m2.min;
 578                      clock.m2 <= limit->m2.max; clock.m2++) {
 579                         for (clock.n = limit->n.min;
 580                              clock.n <= limit->n.max; clock.n++) {
 581                                 for (clock.p1 = limit->p1.min;
 582                                         clock.p1 <= limit->p1.max; clock.p1++) {
 583                                         int this_err;
 584
 585                                         pineview_clock(refclk, &clock);
 586                                         if (!intel_PLL_is_valid(dev, limit,
 587                                                                 &clock))
 588                                                 continue;
 589                                         if (match_clock &&
 590                                             clock.p != match_clock->p)
 591                                                 continue;
 592
 593                                         this_err = abs(clock.dot - target);
 594                                         if (this_err < err) {
 595                                                 *best_clock = clock;
 596                                                 err = this_err;
 597                                         }
 598                                 }
 599                         }
 600                 }
 601         }
 602
 603         return (err != target);
 604 }
 605
 606 static bool
 607 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 608                    int target, int refclk, intel_clock_t *match_clock,
 609                    intel_clock_t *best_clock)
 610 {
 611         struct drm_device *dev = crtc->dev;
 612         intel_clock_t clock;
 613         int max_n;
 614         bool found;
 615         /* approximately equals target * 0.00585 */
 616         int err_most = (target >> 8) + (target >> 9);
 617         found = false;
 618
 619         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 620                 if (intel_is_dual_link_lvds(dev))
 621                         clock.p2 = limit->p2.p2_fast;
 622                 else
 623                         clock.p2 = limit->p2.p2_slow;
 624         } else {
 625                 if (target < limit->p2.dot_limit)
 626                         clock.p2 = limit->p2.p2_slow;
 627                 else
 628                         clock.p2 = limit->p2.p2_fast;
 629         }
 630
 631         memset(best_clock, 0, sizeof(*best_clock));
 632         max_n = limit->n.max;
 633         /* based on hardware requirement, prefer smaller n to precision */
 634         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 635                 /* based on hardware requirement, prefere larger m1,m2 */
 636                 for (clock.m1 = limit->m1.max;
 637                      clock.m1 >= limit->m1.min; clock.m1--) {
 638                         for (clock.m2 = limit->m2.max;
 639                              clock.m2 >= limit->m2.min; clock.m2--) {
 640                                 for (clock.p1 = limit->p1.max;
 641                                      clock.p1 >= limit->p1.min; clock.p1--) {
 642                                         int this_err;
 643
 644                                         i9xx_clock(refclk, &clock);
 645                                         if (!intel_PLL_is_valid(dev, limit,
 646                                                                 &clock))
 647                                                 continue;
 648
 649                                         this_err = abs(clock.dot - target);
 650                                         if (this_err < err_most) {
 651                                                 *best_clock = clock;
 652                                                 err_most = this_err;
 653                                                 max_n = clock.n;
 654                                                 found = true;
 655                                         }
 656                                 }
 657                         }
 658                 }
 659         }
 660         return found;
 661 }
 662
 663 static bool
 664 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 665                    int target, int refclk, intel_clock_t *match_clock,
 666                    intel_clock_t *best_clock)
 667 {
 668         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 669         u32 m, n, fastclk;
 670         u32 updrate, minupdate, fracbits, p;
 671         unsigned long bestppm, ppm, absppm;
 672         int dotclk, flag;
 673
 674         flag = 0;
 675         dotclk = target * 1000;
 676         bestppm = 1000000;
 677         ppm = absppm = 0;
 678         fastclk = dotclk / (2*100);
 679         updrate = 0;
 680         minupdate = 19200;
 681         fracbits = 1;
 682         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 683         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 684
 685         /* based on hardware requirement, prefer smaller n to precision */
 686         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 687                 updrate = refclk / n;
 688                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 689                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 690                                 if (p2 > 10)
 691                                         p2 = p2 - 1;
 692                                 p = p1 * p2;
 693                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 694                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 695                                         m2 = (((2*(fastclk * p * n / m1 )) +
 696                                                refclk) / (2*refclk));
 697                                         m = m1 * m2;
 698                                         vco = updrate * m;
 699                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 700                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 701                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 702                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 703                                                         bestppm = 0;
 704                                                         flag = 1;
 705                                                 }
 706                                                 if (absppm < bestppm - 10) {
 707                                                         bestppm = absppm;
 708                                                         flag = 1;
 709                                                 }
 710                                                 if (flag) {
 711                                                         bestn = n;
 712                                                         bestm1 = m1;
 713                                                         bestm2 = m2;
 714                                                         bestp1 = p1;
 715                                                         bestp2 = p2;
 716                                                         flag = 0;
 717                                                 }
 718                                         }
 719                                 }
 720                         }
 721                 }
 722         }
 723         best_clock->n = bestn;
 724         best_clock->m1 = bestm1;
 725         best_clock->m2 = bestm2;
 726         best_clock->p1 = bestp1;
 727         best_clock->p2 = bestp2;
 728
 729         return true;
 730 }
 731
 732 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 733                                              enum pipe pipe)
 734 {
 735         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 737
 738         return intel_crtc->config.cpu_transcoder;
 739 }
 740
 741 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 742 {
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         u32 frame, frame_reg = PIPEFRAME(pipe);
 745
 746         frame = I915_READ(frame_reg);
 747
 748         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 749                 DRM_DEBUG_KMS("vblank wait timed out\n");
 750 }
 751
 752 /**
 753  * intel_wait_for_vblank - wait for vblank on a given pipe
 754  * @dev: drm device
 755  * @pipe: pipe to wait for
 756  *
 757  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 758  * mode setting code.
 759  */
 760 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int pipestat_reg = PIPESTAT(pipe);
 764
 765         if (INTEL_INFO(dev)->gen >= 5) {
 766                 ironlake_wait_for_vblank(dev, pipe);
 767                 return;
 768         }
 769
 770         /* Clear existing vblank status. Note this will clear any other
 771          * sticky status fields as well.
 772          *
 773          * This races with i915_driver_irq_handler() with the result
 774          * that either function could miss a vblank event.  Here it is not
 775          * fatal, as we will either wait upon the next vblank interrupt or
 776          * timeout.  Generally speaking intel_wait_for_vblank() is only
 777          * called during modeset at which time the GPU should be idle and
 778          * should *not* be performing page flips and thus not waiting on
 779          * vblanks...
 780          * Currently, the result of us stealing a vblank from the irq
 781          * handler is that a single frame will be skipped during swapbuffers.
 782          */
 783         I915_WRITE(pipestat_reg,
 784                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 785
 786         /* Wait for vblank interrupt bit to set */
 787         if (wait_for(I915_READ(pipestat_reg) &
 788                      PIPE_VBLANK_INTERRUPT_STATUS,
 789                      50))
 790                 DRM_DEBUG_KMS("vblank wait timed out\n");
 791 }
 792
 793 /*
 794  * intel_wait_for_pipe_off - wait for pipe to turn off
 795  * @dev: drm device
 796  * @pipe: pipe to wait for
 797  *
 798  * After disabling a pipe, we can't wait for vblank in the usual way,
 799  * spinning on the vblank interrupt status bit, since we won't actually
 800  * see an interrupt when the pipe is disabled.
 801  *
 802  * On Gen4 and above:
 803  *   wait for the pipe register state bit to turn off
 804  *
 805  * Otherwise:
 806  *   wait for the display line value to settle (it usually
 807  *   ends up stopping at the start of the next frame).
 808  *
 809  */
 810 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 811 {
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 814                                                                       pipe);
 815
 816         if (INTEL_INFO(dev)->gen >= 4) {
 817                 int reg = PIPECONF(cpu_transcoder);
 818
 819                 /* Wait for the Pipe State to go off */
 820                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 821                              100))
 822                         WARN(1, "pipe_off wait timed out\n");
 823         } else {
 824                 u32 last_line, line_mask;
 825                 int reg = PIPEDSL(pipe);
 826                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 827
 828                 if (IS_GEN2(dev))
 829                         line_mask = DSL_LINEMASK_GEN2;
 830                 else
 831                         line_mask = DSL_LINEMASK_GEN3;
 832
 833                 /* Wait for the display line to settle */
 834                 do {
 835                         last_line = I915_READ(reg) & line_mask;
 836                         mdelay(5);
 837                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 838                          time_after(timeout, jiffies));
 839                 if (time_after(jiffies, timeout))
 840                         WARN(1, "pipe_off wait timed out\n");
 841         }
 842 }
 843
 844 /*
 845  * ibx_digital_port_connected - is the specified port connected?
 846  * @dev_priv: i915 private structure
 847  * @port: the port to test
 848  *
 849  * Returns true if @port is connected, false otherwise.
 850  */
 851 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 852                                 struct intel_digital_port *port)
 853 {
 854         u32 bit;
 855
 856         if (HAS_PCH_IBX(dev_priv->dev)) {
 857                 switch(port->port) {
 858                 case PORT_B:
 859                         bit = SDE_PORTB_HOTPLUG;
 860                         break;
 861                 case PORT_C:
 862                         bit = SDE_PORTC_HOTPLUG;
 863                         break;
 864                 case PORT_D:
 865                         bit = SDE_PORTD_HOTPLUG;
 866                         break;
 867                 default:
 868                         return true;
 869                 }
 870         } else {
 871                 switch(port->port) {
 872                 case PORT_B:
 873                         bit = SDE_PORTB_HOTPLUG_CPT;
 874                         break;
 875                 case PORT_C:
 876                         bit = SDE_PORTC_HOTPLUG_CPT;
 877                         break;
 878                 case PORT_D:
 879                         bit = SDE_PORTD_HOTPLUG_CPT;
 880                         break;
 881                 default:
 882                         return true;
 883                 }
 884         }
 885
 886         return I915_READ(SDEISR) & bit;
 887 }
 888
 889 static const char *state_string(bool enabled)
 890 {
 891         return enabled ? "on" : "off";
 892 }
 893
 894 /* Only for pre-ILK configs */
 895 void assert_pll(struct drm_i915_private *dev_priv,
 896                 enum pipe pipe, bool state)
 897 {
 898         int reg;
 899         u32 val;
 900         bool cur_state;
 901
 902         reg = DPLL(pipe);
 903         val = I915_READ(reg);
 904         cur_state = !!(val & DPLL_VCO_ENABLE);
 905         WARN(cur_state != state,
 906              "PLL state assertion failure (expected %s, current %s)\n",
 907              state_string(state), state_string(cur_state));
 908 }
 909
 910 struct intel_shared_dpll *
 911 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 912 {
 913         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 914
 915         if (crtc->config.shared_dpll < 0)
 916                 return NULL;
 917
 918         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 919 }
 920
 921 /* For ILK+ */
 922 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 923                         struct intel_shared_dpll *pll,
 924                         bool state)
 925 {
 926         bool cur_state;
 927         struct intel_dpll_hw_state hw_state;
 928
 929         if (HAS_PCH_LPT(dev_priv->dev)) {
 930                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 931                 return;
 932         }
 933
 934         if (WARN (!pll,
 935                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 936                 return;
 937
 938         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 939         WARN(cur_state != state,
 940              "%s assertion failure (expected %s, current %s)\n",
 941              pll->name, state_string(state), state_string(cur_state));
 942 }
 943
 944 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 945                           enum pipe pipe, bool state)
 946 {
 947         int reg;
 948         u32 val;
 949         bool cur_state;
 950         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 951                                                                       pipe);
 952
 953         if (HAS_DDI(dev_priv->dev)) {
 954                 /* DDI does not have a specific FDI_TX register */
 955                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 956                 val = I915_READ(reg);
 957                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 958         } else {
 959                 reg = FDI_TX_CTL(pipe);
 960                 val = I915_READ(reg);
 961                 cur_state = !!(val & FDI_TX_ENABLE);
 962         }
 963         WARN(cur_state != state,
 964              "FDI TX state assertion failure (expected %s, current %s)\n",
 965              state_string(state), state_string(cur_state));
 966 }
 967 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
 968 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
 969
 970 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 971                           enum pipe pipe, bool state)
 972 {
 973         int reg;
 974         u32 val;
 975         bool cur_state;
 976
 977         reg = FDI_RX_CTL(pipe);
 978         val = I915_READ(reg);
 979         cur_state = !!(val & FDI_RX_ENABLE);
 980         WARN(cur_state != state,
 981              "FDI RX state assertion failure (expected %s, current %s)\n",
 982              state_string(state), state_string(cur_state));
 983 }
 984 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
 985 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
 986
 987 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 988                                       enum pipe pipe)
 989 {
 990         int reg;
 991         u32 val;
 992
 993         /* ILK FDI PLL is always enabled */
 994         if (dev_priv->info->gen == 5)
 995                 return;
 996
 997         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
 998         if (HAS_DDI(dev_priv->dev))
 999                 return;
1000
1001         reg = FDI_TX_CTL(pipe);
1002         val = I915_READ(reg);
1003         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1004 }
1005
1006 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1007                        enum pipe pipe, bool state)
1008 {
1009         int reg;
1010         u32 val;
1011         bool cur_state;
1012
1013         reg = FDI_RX_CTL(pipe);
1014         val = I915_READ(reg);
1015         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1016         WARN(cur_state != state,
1017              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1018              state_string(state), state_string(cur_state));
1019 }
1020
1021 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022                                   enum pipe pipe)
1023 {
1024         int pp_reg, lvds_reg;
1025         u32 val;
1026         enum pipe panel_pipe = PIPE_A;
1027         bool locked = true;
1028
1029         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030                 pp_reg = PCH_PP_CONTROL;
1031                 lvds_reg = PCH_LVDS;
1032         } else {
1033                 pp_reg = PP_CONTROL;
1034                 lvds_reg = LVDS;
1035         }
1036
1037         val = I915_READ(pp_reg);
1038         if (!(val & PANEL_POWER_ON) ||
1039             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040                 locked = false;
1041
1042         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043                 panel_pipe = PIPE_B;
1044
1045         WARN(panel_pipe == pipe && locked,
1046              "panel assertion failure, pipe %c regs locked\n",
1047              pipe_name(pipe));
1048 }
1049
1050 void assert_pipe(struct drm_i915_private *dev_priv,
1051                  enum pipe pipe, bool state)
1052 {
1053         int reg;
1054         u32 val;
1055         bool cur_state;
1056         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057                                                                       pipe);
1058
1059         /* if we need the pipe A quirk it must be always on */
1060         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061                 state = true;
1062
1063         if (!intel_display_power_enabled(dev_priv->dev,
1064                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1065                 cur_state = false;
1066         } else {
1067                 reg = PIPECONF(cpu_transcoder);
1068                 val = I915_READ(reg);
1069                 cur_state = !!(val & PIPECONF_ENABLE);
1070         }
1071
1072         WARN(cur_state != state,
1073              "pipe %c assertion failure (expected %s, current %s)\n",
1074              pipe_name(pipe), state_string(state), state_string(cur_state));
1075 }
1076
1077 static void assert_plane(struct drm_i915_private *dev_priv,
1078                          enum plane plane, bool state)
1079 {
1080         int reg;
1081         u32 val;
1082         bool cur_state;
1083
1084         reg = DSPCNTR(plane);
1085         val = I915_READ(reg);
1086         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087         WARN(cur_state != state,
1088              "plane %c assertion failure (expected %s, current %s)\n",
1089              plane_name(plane), state_string(state), state_string(cur_state));
1090 }
1091
1092 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
1095 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096                                    enum pipe pipe)
1097 {
1098         struct drm_device *dev = dev_priv->dev;
1099         int reg, i;
1100         u32 val;
1101         int cur_pipe;
1102
1103         /* Primary planes are fixed to pipes on gen4+ */
1104         if (INTEL_INFO(dev)->gen >= 4) {
1105                 reg = DSPCNTR(pipe);
1106                 val = I915_READ(reg);
1107                 WARN((val & DISPLAY_PLANE_ENABLE),
1108                      "plane %c assertion failure, should be disabled but not\n",
1109                      plane_name(pipe));
1110                 return;
1111         }
1112
1113         /* Need to check both planes against the pipe */
1114         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1115                 reg = DSPCNTR(i);
1116                 val = I915_READ(reg);
1117                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118                         DISPPLANE_SEL_PIPE_SHIFT;
1119                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1120                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121                      plane_name(i), pipe_name(pipe));
1122         }
1123 }
1124
1125 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126                                     enum pipe pipe)
1127 {
1128         struct drm_device *dev = dev_priv->dev;
1129         int reg, i;
1130         u32 val;
1131
1132         if (IS_VALLEYVIEW(dev)) {
1133                 for (i = 0; i < dev_priv->num_plane; i++) {
1134                         reg = SPCNTR(pipe, i);
1135                         val = I915_READ(reg);
1136                         WARN((val & SP_ENABLE),
1137                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138                              sprite_name(pipe, i), pipe_name(pipe));
1139                 }
1140         } else if (INTEL_INFO(dev)->gen >= 7) {
1141                 reg = SPRCTL(pipe);
1142                 val = I915_READ(reg);
1143                 WARN((val & SPRITE_ENABLE),
1144                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1145                      plane_name(pipe), pipe_name(pipe));
1146         } else if (INTEL_INFO(dev)->gen >= 5) {
1147                 reg = DVSCNTR(pipe);
1148                 val = I915_READ(reg);
1149                 WARN((val & DVS_ENABLE),
1150                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1151                      plane_name(pipe), pipe_name(pipe));
1152         }
1153 }
1154
1155 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156 {
1157         u32 val;
1158         bool enabled;
1159
1160         if (HAS_PCH_LPT(dev_priv->dev)) {
1161                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162                 return;
1163         }
1164
1165         val = I915_READ(PCH_DREF_CONTROL);
1166         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167                             DREF_SUPERSPREAD_SOURCE_MASK));
1168         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172                                            enum pipe pipe)
1173 {
1174         int reg;
1175         u32 val;
1176         bool enabled;
1177
1178         reg = PCH_TRANSCONF(pipe);
1179         val = I915_READ(reg);
1180         enabled = !!(val & TRANS_ENABLE);
1181         WARN(enabled,
1182              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183              pipe_name(pipe));
1184 }
1185
1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187                             enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189         if ((val & DP_PORT_EN) == 0)
1190                 return false;
1191
1192         if (HAS_PCH_CPT(dev_priv->dev)) {
1193                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196                         return false;
1197         } else {
1198                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199                         return false;
1200         }
1201         return true;
1202 }
1203
1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205                               enum pipe pipe, u32 val)
1206 {
1207         if ((val & SDVO_ENABLE) == 0)
1208                 return false;
1209
1210         if (HAS_PCH_CPT(dev_priv->dev)) {
1211                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212                         return false;
1213         } else {
1214                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215                         return false;
1216         }
1217         return true;
1218 }
1219
1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221                               enum pipe pipe, u32 val)
1222 {
1223         if ((val & LVDS_PORT_EN) == 0)
1224                 return false;
1225
1226         if (HAS_PCH_CPT(dev_priv->dev)) {
1227                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228                         return false;
1229         } else {
1230                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231                         return false;
1232         }
1233         return true;
1234 }
1235
1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237                               enum pipe pipe, u32 val)
1238 {
1239         if ((val & ADPA_DAC_ENABLE) == 0)
1240                 return false;
1241         if (HAS_PCH_CPT(dev_priv->dev)) {
1242                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243                         return false;
1244         } else {
1245                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246                         return false;
1247         }
1248         return true;
1249 }
1250
1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252                                    enum pipe pipe, int reg, u32 port_sel)
1253 {
1254         u32 val = I915_READ(reg);
1255         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1256              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257              reg, pipe_name(pipe));
1258
1259         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260              && (val & DP_PIPEB_SELECT),
1261              "IBX PCH dp port still using transcoder B\n");
1262 }
1263
1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265                                      enum pipe pipe, int reg)
1266 {
1267         u32 val = I915_READ(reg);
1268         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1269              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270              reg, pipe_name(pipe));
1271
1272         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273              && (val & SDVO_PIPE_B_SELECT),
1274              "IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278                                       enum pipe pipe)
1279 {
1280         int reg;
1281         u32 val;
1282
1283         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287         reg = PCH_ADPA;
1288         val = I915_READ(reg);
1289         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1290              "PCH VGA enabled on transcoder %c, should be disabled\n",
1291              pipe_name(pipe));
1292
1293         reg = PCH_LVDS;
1294         val = I915_READ(reg);
1295         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1296              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1297              pipe_name(pipe));
1298
1299         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1305 {
1306         int reg;
1307         u32 val;
1308
1309         assert_pipe_disabled(dev_priv, pipe);
1310
1311         /* No really, not for ILK+ */
1312         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1313
1314         /* PLL is protected by panel, make sure we can write it */
1315         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1316                 assert_panel_unlocked(dev_priv, pipe);
1317
1318         reg = DPLL(pipe);
1319         val = I915_READ(reg);
1320         val |= DPLL_VCO_ENABLE;
1321
1322         /* We do this three times for luck */
1323         I915_WRITE(reg, val);
1324         POSTING_READ(reg);
1325         udelay(150); /* wait for warmup */
1326         I915_WRITE(reg, val);
1327         POSTING_READ(reg);
1328         udelay(150); /* wait for warmup */
1329         I915_WRITE(reg, val);
1330         POSTING_READ(reg);
1331         udelay(150); /* wait for warmup */
1332 }
1333
1334 static void i9xx_enable_pll(struct intel_crtc *crtc)
1335 {
1336         struct drm_device *dev = crtc->base.dev;
1337         struct drm_i915_private *dev_priv = dev->dev_private;
1338         int reg = DPLL(crtc->pipe);
1339         u32 dpll = crtc->config.dpll_hw_state.dpll;
1340
1341         assert_pipe_disabled(dev_priv, crtc->pipe);
1342
1343         /* No really, not for ILK+ */
1344         BUG_ON(dev_priv->info->gen >= 5);
1345
1346         /* PLL is protected by panel, make sure we can write it */
1347         if (IS_MOBILE(dev) && !IS_I830(dev))
1348                 assert_panel_unlocked(dev_priv, crtc->pipe);
1349
1350         I915_WRITE(reg, dpll);
1351
1352         /* Wait for the clocks to stabilize. */
1353         POSTING_READ(reg);
1354         udelay(150);
1355
1356         if (INTEL_INFO(dev)->gen >= 4) {
1357                 I915_WRITE(DPLL_MD(crtc->pipe),
1358                            crtc->config.dpll_hw_state.dpll_md);
1359         } else {
1360                 /* The pixel multiplier can only be updated once the
1361                  * DPLL is enabled and the clocks are stable.
1362                  *
1363                  * So write it again.
1364                  */
1365                 I915_WRITE(reg, dpll);
1366         }
1367
1368         /* We do this three times for luck */
1369         I915_WRITE(reg, dpll);
1370         POSTING_READ(reg);
1371         udelay(150); /* wait for warmup */
1372         I915_WRITE(reg, dpll);
1373         POSTING_READ(reg);
1374         udelay(150); /* wait for warmup */
1375         I915_WRITE(reg, dpll);
1376         POSTING_READ(reg);
1377         udelay(150); /* wait for warmup */
1378 }
1379
1380 /**
1381  * intel_disable_pll - disable a PLL
1382  * @dev_priv: i915 private structure
1383  * @pipe: pipe PLL to disable
1384  *
1385  * Disable the PLL for @pipe, making sure the pipe is off first.
1386  *
1387  * Note!  This is for pre-ILK only.
1388  */
1389 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1390 {
1391         int reg;
1392         u32 val;
1393
1394         /* Don't disable pipe A or pipe A PLLs if needed */
1395         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1396                 return;
1397
1398         /* Make sure the pipe isn't still relying on us */
1399         assert_pipe_disabled(dev_priv, pipe);
1400
1401         reg = DPLL(pipe);
1402         val = I915_READ(reg);
1403         val &= ~DPLL_VCO_ENABLE;
1404         I915_WRITE(reg, val);
1405         POSTING_READ(reg);
1406 }
1407
1408 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1409 {
1410         u32 port_mask;
1411
1412         if (!port)
1413                 port_mask = DPLL_PORTB_READY_MASK;
1414         else
1415                 port_mask = DPLL_PORTC_READY_MASK;
1416
1417         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1418                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1419                      'B' + port, I915_READ(DPLL(0)));
1420 }
1421
1422 /**
1423  * ironlake_enable_shared_dpll - enable PCH PLL
1424  * @dev_priv: i915 private structure
1425  * @pipe: pipe PLL to enable
1426  *
1427  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1428  * drives the transcoder clock.
1429  */
1430 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1431 {
1432         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1433         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1434
1435         /* PCH PLLs only available on ILK, SNB and IVB */
1436         BUG_ON(dev_priv->info->gen < 5);
1437         if (WARN_ON(pll == NULL))
1438                 return;
1439
1440         if (WARN_ON(pll->refcount == 0))
1441                 return;
1442
1443         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1444                       pll->name, pll->active, pll->on,
1445                       crtc->base.base.id);
1446
1447         if (pll->active++) {
1448                 WARN_ON(!pll->on);
1449                 assert_shared_dpll_enabled(dev_priv, pll);
1450                 return;
1451         }
1452         WARN_ON(pll->on);
1453
1454         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1455         pll->enable(dev_priv, pll);
1456         pll->on = true;
1457 }
1458
1459 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1460 {
1461         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1462         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1463
1464         /* PCH only available on ILK+ */
1465         BUG_ON(dev_priv->info->gen < 5);
1466         if (WARN_ON(pll == NULL))
1467                return;
1468
1469         if (WARN_ON(pll->refcount == 0))
1470                 return;
1471
1472         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1473                       pll->name, pll->active, pll->on,
1474                       crtc->base.base.id);
1475
1476         if (WARN_ON(pll->active == 0)) {
1477                 assert_shared_dpll_disabled(dev_priv, pll);
1478                 return;
1479         }
1480
1481         assert_shared_dpll_enabled(dev_priv, pll);
1482         WARN_ON(!pll->on);
1483         if (--pll->active)
1484                 return;
1485
1486         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1487         pll->disable(dev_priv, pll);
1488         pll->on = false;
1489 }
1490
1491 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492                                            enum pipe pipe)
1493 {
1494         struct drm_device *dev = dev_priv->dev;
1495         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1496         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1497         uint32_t reg, val, pipeconf_val;
1498
1499         /* PCH only available on ILK+ */
1500         BUG_ON(dev_priv->info->gen < 5);
1501
1502         /* Make sure PCH DPLL is enabled */
1503         assert_shared_dpll_enabled(dev_priv,
1504                                    intel_crtc_to_shared_dpll(intel_crtc));
1505
1506         /* FDI must be feeding us bits for PCH ports */
1507         assert_fdi_tx_enabled(dev_priv, pipe);
1508         assert_fdi_rx_enabled(dev_priv, pipe);
1509
1510         if (HAS_PCH_CPT(dev)) {
1511                 /* Workaround: Set the timing override bit before enabling the
1512                  * pch transcoder. */
1513                 reg = TRANS_CHICKEN2(pipe);
1514                 val = I915_READ(reg);
1515                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516                 I915_WRITE(reg, val);
1517         }
1518
1519         reg = PCH_TRANSCONF(pipe);
1520         val = I915_READ(reg);
1521         pipeconf_val = I915_READ(PIPECONF(pipe));
1522
1523         if (HAS_PCH_IBX(dev_priv->dev)) {
1524                 /*
1525                  * make the BPC in transcoder be consistent with
1526                  * that in pipeconf reg.
1527                  */
1528                 val &= ~PIPECONF_BPC_MASK;
1529                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1530         }
1531
1532         val &= ~TRANS_INTERLACE_MASK;
1533         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1534                 if (HAS_PCH_IBX(dev_priv->dev) &&
1535                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536                         val |= TRANS_LEGACY_INTERLACED_ILK;
1537                 else
1538                         val |= TRANS_INTERLACED;
1539         else
1540                 val |= TRANS_PROGRESSIVE;
1541
1542         I915_WRITE(reg, val | TRANS_ENABLE);
1543         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1544                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1545 }
1546
1547 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1548                                       enum transcoder cpu_transcoder)
1549 {
1550         u32 val, pipeconf_val;
1551
1552         /* PCH only available on ILK+ */
1553         BUG_ON(dev_priv->info->gen < 5);
1554
1555         /* FDI must be feeding us bits for PCH ports */
1556         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1557         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1558
1559         /* Workaround: set timing override bit. */
1560         val = I915_READ(_TRANSA_CHICKEN2);
1561         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1562         I915_WRITE(_TRANSA_CHICKEN2, val);
1563
1564         val = TRANS_ENABLE;
1565         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1566
1567         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568             PIPECONF_INTERLACED_ILK)
1569                 val |= TRANS_INTERLACED;
1570         else
1571                 val |= TRANS_PROGRESSIVE;
1572
1573         I915_WRITE(LPT_TRANSCONF, val);
1574         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1575                 DRM_ERROR("Failed to enable PCH transcoder\n");
1576 }
1577
1578 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579                                             enum pipe pipe)
1580 {
1581         struct drm_device *dev = dev_priv->dev;
1582         uint32_t reg, val;
1583
1584         /* FDI relies on the transcoder */
1585         assert_fdi_tx_disabled(dev_priv, pipe);
1586         assert_fdi_rx_disabled(dev_priv, pipe);
1587
1588         /* Ports must be off as well */
1589         assert_pch_ports_disabled(dev_priv, pipe);
1590
1591         reg = PCH_TRANSCONF(pipe);
1592         val = I915_READ(reg);
1593         val &= ~TRANS_ENABLE;
1594         I915_WRITE(reg, val);
1595         /* wait for PCH transcoder off, transcoder state */
1596         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1597                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1598
1599         if (!HAS_PCH_IBX(dev)) {
1600                 /* Workaround: Clear the timing override chicken bit again. */
1601                 reg = TRANS_CHICKEN2(pipe);
1602                 val = I915_READ(reg);
1603                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604                 I915_WRITE(reg, val);
1605         }
1606 }
1607
1608 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1609 {
1610         u32 val;
1611
1612         val = I915_READ(LPT_TRANSCONF);
1613         val &= ~TRANS_ENABLE;
1614         I915_WRITE(LPT_TRANSCONF, val);
1615         /* wait for PCH transcoder off, transcoder state */
1616         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1617                 DRM_ERROR("Failed to disable PCH transcoder\n");
1618
1619         /* Workaround: clear timing override bit. */
1620         val = I915_READ(_TRANSA_CHICKEN2);
1621         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1622         I915_WRITE(_TRANSA_CHICKEN2, val);
1623 }
1624
1625 /**
1626  * intel_enable_pipe - enable a pipe, asserting requirements
1627  * @dev_priv: i915 private structure
1628  * @pipe: pipe to enable
1629  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1630  *
1631  * Enable @pipe, making sure that various hardware specific requirements
1632  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633  *
1634  * @pipe should be %PIPE_A or %PIPE_B.
1635  *
1636  * Will wait until the pipe is actually running (i.e. first vblank) before
1637  * returning.
1638  */
1639 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640                               bool pch_port)
1641 {
1642         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643                                                                       pipe);
1644         enum pipe pch_transcoder;
1645         int reg;
1646         u32 val;
1647
1648         assert_planes_disabled(dev_priv, pipe);
1649         assert_sprites_disabled(dev_priv, pipe);
1650
1651         if (HAS_PCH_LPT(dev_priv->dev))
1652                 pch_transcoder = TRANSCODER_A;
1653         else
1654                 pch_transcoder = pipe;
1655
1656         /*
1657          * A pipe without a PLL won't actually be able to drive bits from
1658          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1659          * need the check.
1660          */
1661         if (!HAS_PCH_SPLIT(dev_priv->dev))
1662                 assert_pll_enabled(dev_priv, pipe);
1663         else {
1664                 if (pch_port) {
1665                         /* if driving the PCH, we need FDI enabled */
1666                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1667                         assert_fdi_tx_pll_enabled(dev_priv,
1668                                                   (enum pipe) cpu_transcoder);
1669                 }
1670                 /* FIXME: assert CPU port conditions for SNB+ */
1671         }
1672
1673         reg = PIPECONF(cpu_transcoder);
1674         val = I915_READ(reg);
1675         if (val & PIPECONF_ENABLE)
1676                 return;
1677
1678         I915_WRITE(reg, val | PIPECONF_ENABLE);
1679         intel_wait_for_vblank(dev_priv->dev, pipe);
1680 }
1681
1682 /**
1683  * intel_disable_pipe - disable a pipe, asserting requirements
1684  * @dev_priv: i915 private structure
1685  * @pipe: pipe to disable
1686  *
1687  * Disable @pipe, making sure that various hardware specific requirements
1688  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689  *
1690  * @pipe should be %PIPE_A or %PIPE_B.
1691  *
1692  * Will wait until the pipe has shut down before returning.
1693  */
1694 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695                                enum pipe pipe)
1696 {
1697         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698                                                                       pipe);
1699         int reg;
1700         u32 val;
1701
1702         /*
1703          * Make sure planes won't keep trying to pump pixels to us,
1704          * or we might hang the display.
1705          */
1706         assert_planes_disabled(dev_priv, pipe);
1707         assert_sprites_disabled(dev_priv, pipe);
1708
1709         /* Don't disable pipe A or pipe A PLLs if needed */
1710         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711                 return;
1712
1713         reg = PIPECONF(cpu_transcoder);
1714         val = I915_READ(reg);
1715         if ((val & PIPECONF_ENABLE) == 0)
1716                 return;
1717
1718         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1719         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720 }
1721
1722 /*
1723  * Plane regs are double buffered, going from enabled->disabled needs a
1724  * trigger in order to latch.  The display address reg provides this.
1725  */
1726 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1727                                       enum plane plane)
1728 {
1729         if (dev_priv->info->gen >= 4)
1730                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731         else
1732                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1733 }
1734
1735 /**
1736  * intel_enable_plane - enable a display plane on a given pipe
1737  * @dev_priv: i915 private structure
1738  * @plane: plane to enable
1739  * @pipe: pipe being fed
1740  *
1741  * Enable @plane on @pipe, making sure that @pipe is running first.
1742  */
1743 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744                                enum plane plane, enum pipe pipe)
1745 {
1746         int reg;
1747         u32 val;
1748
1749         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750         assert_pipe_enabled(dev_priv, pipe);
1751
1752         reg = DSPCNTR(plane);
1753         val = I915_READ(reg);
1754         if (val & DISPLAY_PLANE_ENABLE)
1755                 return;
1756
1757         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1758         intel_flush_display_plane(dev_priv, plane);
1759         intel_wait_for_vblank(dev_priv->dev, pipe);
1760 }
1761
1762 /**
1763  * intel_disable_plane - disable a display plane
1764  * @dev_priv: i915 private structure
1765  * @plane: plane to disable
1766  * @pipe: pipe consuming the data
1767  *
1768  * Disable @plane; should be an independent operation.
1769  */
1770 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771                                 enum plane plane, enum pipe pipe)
1772 {
1773         int reg;
1774         u32 val;
1775
1776         reg = DSPCNTR(plane);
1777         val = I915_READ(reg);
1778         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779                 return;
1780
1781         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1782         intel_flush_display_plane(dev_priv, plane);
1783         intel_wait_for_vblank(dev_priv->dev, pipe);
1784 }
1785
1786 static bool need_vtd_wa(struct drm_device *dev)
1787 {
1788 #ifdef CONFIG_INTEL_IOMMU
1789         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790                 return true;
1791 #endif
1792         return false;
1793 }
1794
1795 int
1796 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1797                            struct drm_i915_gem_object *obj,
1798                            struct intel_ring_buffer *pipelined)
1799 {
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         u32 alignment;
1802         int ret;
1803
1804         switch (obj->tiling_mode) {
1805         case I915_TILING_NONE:
1806                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807                         alignment = 128 * 1024;
1808                 else if (INTEL_INFO(dev)->gen >= 4)
1809                         alignment = 4 * 1024;
1810                 else
1811                         alignment = 64 * 1024;
1812                 break;
1813         case I915_TILING_X:
1814                 /* pin() will align the object as required by fence */
1815                 alignment = 0;
1816                 break;
1817         case I915_TILING_Y:
1818                 /* Despite that we check this in framebuffer_init userspace can
1819                  * screw us over and change the tiling after the fact. Only
1820                  * pinned buffers can't change their tiling. */
1821                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1822                 return -EINVAL;
1823         default:
1824                 BUG();
1825         }
1826
1827         /* Note that the w/a also requires 64 PTE of padding following the
1828          * bo. We currently fill all unused PTE with the shadow page and so
1829          * we should always have valid PTE following the scanout preventing
1830          * the VT-d warning.
1831          */
1832         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833                 alignment = 256 * 1024;
1834
1835         dev_priv->mm.interruptible = false;
1836         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1837         if (ret)
1838                 goto err_interruptible;
1839
1840         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841          * fence, whereas 965+ only requires a fence if using
1842          * framebuffer compression.  For simplicity, we always install
1843          * a fence as the cost is not that onerous.
1844          */
1845         ret = i915_gem_object_get_fence(obj);
1846         if (ret)
1847                 goto err_unpin;
1848
1849         i915_gem_object_pin_fence(obj);
1850
1851         dev_priv->mm.interruptible = true;
1852         return 0;
1853
1854 err_unpin:
1855         i915_gem_object_unpin(obj);
1856 err_interruptible:
1857         dev_priv->mm.interruptible = true;
1858         return ret;
1859 }
1860
1861 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862 {
1863         i915_gem_object_unpin_fence(obj);
1864         i915_gem_object_unpin(obj);
1865 }
1866
1867 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868  * is assumed to be a power-of-two. */
1869 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870                                              unsigned int tiling_mode,
1871                                              unsigned int cpp,
1872                                              unsigned int pitch)
1873 {
1874         if (tiling_mode != I915_TILING_NONE) {
1875                 unsigned int tile_rows, tiles;
1876
1877                 tile_rows = *y / 8;
1878                 *y %= 8;
1879
1880                 tiles = *x / (512/cpp);
1881                 *x %= 512/cpp;
1882
1883                 return tile_rows * pitch * 8 + tiles * 4096;
1884         } else {
1885                 unsigned int offset;
1886
1887                 offset = *y * pitch + *x * cpp;
1888                 *y = 0;
1889                 *x = (offset & 4095) / cpp;
1890                 return offset & -4096;
1891         }
1892 }
1893
1894 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895                              int x, int y)
1896 {
1897         struct drm_device *dev = crtc->dev;
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900         struct intel_framebuffer *intel_fb;
1901         struct drm_i915_gem_object *obj;
1902         int plane = intel_crtc->plane;
1903         unsigned long linear_offset;
1904         u32 dspcntr;
1905         u32 reg;
1906
1907         switch (plane) {
1908         case 0:
1909         case 1:
1910                 break;
1911         default:
1912                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1913                 return -EINVAL;
1914         }
1915
1916         intel_fb = to_intel_framebuffer(fb);
1917         obj = intel_fb->obj;
1918
1919         reg = DSPCNTR(plane);
1920         dspcntr = I915_READ(reg);
1921         /* Mask out pixel format bits in case we change it */
1922         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1923         switch (fb->pixel_format) {
1924         case DRM_FORMAT_C8:
1925                 dspcntr |= DISPPLANE_8BPP;
1926                 break;
1927         case DRM_FORMAT_XRGB1555:
1928         case DRM_FORMAT_ARGB1555:
1929                 dspcntr |= DISPPLANE_BGRX555;
1930                 break;
1931         case DRM_FORMAT_RGB565:
1932                 dspcntr |= DISPPLANE_BGRX565;
1933                 break;
1934         case DRM_FORMAT_XRGB8888:
1935         case DRM_FORMAT_ARGB8888:
1936                 dspcntr |= DISPPLANE_BGRX888;
1937                 break;
1938         case DRM_FORMAT_XBGR8888:
1939         case DRM_FORMAT_ABGR8888:
1940                 dspcntr |= DISPPLANE_RGBX888;
1941                 break;
1942         case DRM_FORMAT_XRGB2101010:
1943         case DRM_FORMAT_ARGB2101010:
1944                 dspcntr |= DISPPLANE_BGRX101010;
1945                 break;
1946         case DRM_FORMAT_XBGR2101010:
1947         case DRM_FORMAT_ABGR2101010:
1948                 dspcntr |= DISPPLANE_RGBX101010;
1949                 break;
1950         default:
1951                 BUG();
1952         }
1953
1954         if (INTEL_INFO(dev)->gen >= 4) {
1955                 if (obj->tiling_mode != I915_TILING_NONE)
1956                         dspcntr |= DISPPLANE_TILED;
1957                 else
1958                         dspcntr &= ~DISPPLANE_TILED;
1959         }
1960
1961         if (IS_G4X(dev))
1962                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1963
1964         I915_WRITE(reg, dspcntr);
1965
1966         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1967
1968         if (INTEL_INFO(dev)->gen >= 4) {
1969                 intel_crtc->dspaddr_offset =
1970                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1971                                                        fb->bits_per_pixel / 8,
1972                                                        fb->pitches[0]);
1973                 linear_offset -= intel_crtc->dspaddr_offset;
1974         } else {
1975                 intel_crtc->dspaddr_offset = linear_offset;
1976         }
1977
1978         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1980         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1981         if (INTEL_INFO(dev)->gen >= 4) {
1982                 I915_MODIFY_DISPBASE(DSPSURF(plane),
1983                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
1984                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1985                 I915_WRITE(DSPLINOFF(plane), linear_offset);
1986         } else
1987                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1988         POSTING_READ(reg);
1989
1990         return 0;
1991 }
1992
1993 static int ironlake_update_plane(struct drm_crtc *crtc,
1994                                  struct drm_framebuffer *fb, int x, int y)
1995 {
1996         struct drm_device *dev = crtc->dev;
1997         struct drm_i915_private *dev_priv = dev->dev_private;
1998         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999         struct intel_framebuffer *intel_fb;
2000         struct drm_i915_gem_object *obj;
2001         int plane = intel_crtc->plane;
2002         unsigned long linear_offset;
2003         u32 dspcntr;
2004         u32 reg;
2005
2006         switch (plane) {
2007         case 0:
2008         case 1:
2009         case 2:
2010                 break;
2011         default:
2012                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2013                 return -EINVAL;
2014         }
2015
2016         intel_fb = to_intel_framebuffer(fb);
2017         obj = intel_fb->obj;
2018
2019         reg = DSPCNTR(plane);
2020         dspcntr = I915_READ(reg);
2021         /* Mask out pixel format bits in case we change it */
2022         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023         switch (fb->pixel_format) {
2024         case DRM_FORMAT_C8:
2025                 dspcntr |= DISPPLANE_8BPP;
2026                 break;
2027         case DRM_FORMAT_RGB565:
2028                 dspcntr |= DISPPLANE_BGRX565;
2029                 break;
2030         case DRM_FORMAT_XRGB8888:
2031         case DRM_FORMAT_ARGB8888:
2032                 dspcntr |= DISPPLANE_BGRX888;
2033                 break;
2034         case DRM_FORMAT_XBGR8888:
2035         case DRM_FORMAT_ABGR8888:
2036                 dspcntr |= DISPPLANE_RGBX888;
2037                 break;
2038         case DRM_FORMAT_XRGB2101010:
2039         case DRM_FORMAT_ARGB2101010:
2040                 dspcntr |= DISPPLANE_BGRX101010;
2041                 break;
2042         case DRM_FORMAT_XBGR2101010:
2043         case DRM_FORMAT_ABGR2101010:
2044                 dspcntr |= DISPPLANE_RGBX101010;
2045                 break;
2046         default:
2047                 BUG();
2048         }
2049
2050         if (obj->tiling_mode != I915_TILING_NONE)
2051                 dspcntr |= DISPPLANE_TILED;
2052         else
2053                 dspcntr &= ~DISPPLANE_TILED;
2054
2055         /* must disable */
2056         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058         I915_WRITE(reg, dspcntr);
2059
2060         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2061         intel_crtc->dspaddr_offset =
2062                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063                                                fb->bits_per_pixel / 8,
2064                                                fb->pitches[0]);
2065         linear_offset -= intel_crtc->dspaddr_offset;
2066
2067         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2069         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2070         I915_MODIFY_DISPBASE(DSPSURF(plane),
2071                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2072         if (IS_HASWELL(dev)) {
2073                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2074         } else {
2075                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2076                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2077         }
2078         POSTING_READ(reg);
2079
2080         return 0;
2081 }
2082
2083 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2084 static int
2085 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2086                            int x, int y, enum mode_set_atomic state)
2087 {
2088         struct drm_device *dev = crtc->dev;
2089         struct drm_i915_private *dev_priv = dev->dev_private;
2090
2091         if (dev_priv->display.disable_fbc)
2092                 dev_priv->display.disable_fbc(dev);
2093         intel_increase_pllclock(crtc);
2094
2095         return dev_priv->display.update_plane(crtc, fb, x, y);
2096 }
2097
2098 void intel_display_handle_reset(struct drm_device *dev)
2099 {
2100         struct drm_i915_private *dev_priv = dev->dev_private;
2101         struct drm_crtc *crtc;
2102
2103         /*
2104          * Flips in the rings have been nuked by the reset,
2105          * so complete all pending flips so that user space
2106          * will get its events and not get stuck.
2107          *
2108          * Also update the base address of all primary
2109          * planes to the the last fb to make sure we're
2110          * showing the correct fb after a reset.
2111          *
2112          * Need to make two loops over the crtcs so that we
2113          * don't try to grab a crtc mutex before the
2114          * pending_flip_queue really got woken up.
2115          */
2116
2117         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2118                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119                 enum plane plane = intel_crtc->plane;
2120
2121                 intel_prepare_page_flip(dev, plane);
2122                 intel_finish_page_flip_plane(dev, plane);
2123         }
2124
2125         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2126                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127
2128                 mutex_lock(&crtc->mutex);
2129                 if (intel_crtc->active)
2130                         dev_priv->display.update_plane(crtc, crtc->fb,
2131                                                        crtc->x, crtc->y);
2132                 mutex_unlock(&crtc->mutex);
2133         }
2134 }
2135
2136 static int
2137 intel_finish_fb(struct drm_framebuffer *old_fb)
2138 {
2139         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2140         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141         bool was_interruptible = dev_priv->mm.interruptible;
2142         int ret;
2143
2144         /* Big Hammer, we also need to ensure that any pending
2145          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146          * current scanout is retired before unpinning the old
2147          * framebuffer.
2148          *
2149          * This should only fail upon a hung GPU, in which case we
2150          * can safely continue.
2151          */
2152         dev_priv->mm.interruptible = false;
2153         ret = i915_gem_object_finish_gpu(obj);
2154         dev_priv->mm.interruptible = was_interruptible;
2155
2156         return ret;
2157 }
2158
2159 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2160 {
2161         struct drm_device *dev = crtc->dev;
2162         struct drm_i915_master_private *master_priv;
2163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164
2165         if (!dev->primary->master)
2166                 return;
2167
2168         master_priv = dev->primary->master->driver_priv;
2169         if (!master_priv->sarea_priv)
2170                 return;
2171
2172         switch (intel_crtc->pipe) {
2173         case 0:
2174                 master_priv->sarea_priv->pipeA_x = x;
2175                 master_priv->sarea_priv->pipeA_y = y;
2176                 break;
2177         case 1:
2178                 master_priv->sarea_priv->pipeB_x = x;
2179                 master_priv->sarea_priv->pipeB_y = y;
2180                 break;
2181         default:
2182                 break;
2183         }
2184 }
2185
2186 static int
2187 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2188                     struct drm_framebuffer *fb)
2189 {
2190         struct drm_device *dev = crtc->dev;
2191         struct drm_i915_private *dev_priv = dev->dev_private;
2192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2193         struct drm_framebuffer *old_fb;
2194         int ret;
2195
2196         /* no fb bound */
2197         if (!fb) {
2198                 DRM_ERROR("No FB bound\n");
2199                 return 0;
2200         }
2201
2202         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2203                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204                           plane_name(intel_crtc->plane),
2205                           INTEL_INFO(dev)->num_pipes);
2206                 return -EINVAL;
2207         }
2208
2209         mutex_lock(&dev->struct_mutex);
2210         ret = intel_pin_and_fence_fb_obj(dev,
2211                                          to_intel_framebuffer(fb)->obj,
2212                                          NULL);
2213         if (ret != 0) {
2214                 mutex_unlock(&dev->struct_mutex);
2215                 DRM_ERROR("pin & fence failed\n");
2216                 return ret;
2217         }
2218
2219         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2220         if (ret) {
2221                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2222                 mutex_unlock(&dev->struct_mutex);
2223                 DRM_ERROR("failed to update base address\n");
2224                 return ret;
2225         }
2226
2227         old_fb = crtc->fb;
2228         crtc->fb = fb;
2229         crtc->x = x;
2230         crtc->y = y;
2231
2232         if (old_fb) {
2233                 if (intel_crtc->active && old_fb != fb)
2234                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2235                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2236         }
2237
2238         intel_update_fbc(dev);
2239         mutex_unlock(&dev->struct_mutex);
2240
2241         intel_crtc_update_sarea_pos(crtc, x, y);
2242
2243         return 0;
2244 }
2245
2246 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2247 {
2248         struct drm_device *dev = crtc->dev;
2249         struct drm_i915_private *dev_priv = dev->dev_private;
2250         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251         int pipe = intel_crtc->pipe;
2252         u32 reg, temp;
2253
2254         /* enable normal train */
2255         reg = FDI_TX_CTL(pipe);
2256         temp = I915_READ(reg);
2257         if (IS_IVYBRIDGE(dev)) {
2258                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2259                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2260         } else {
2261                 temp &= ~FDI_LINK_TRAIN_NONE;
2262                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2263         }
2264         I915_WRITE(reg, temp);
2265
2266         reg = FDI_RX_CTL(pipe);
2267         temp = I915_READ(reg);
2268         if (HAS_PCH_CPT(dev)) {
2269                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2270                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2271         } else {
2272                 temp &= ~FDI_LINK_TRAIN_NONE;
2273                 temp |= FDI_LINK_TRAIN_NONE;
2274         }
2275         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276
2277         /* wait one idle pattern time */
2278         POSTING_READ(reg);
2279         udelay(1000);
2280
2281         /* IVB wants error correction enabled */
2282         if (IS_IVYBRIDGE(dev))
2283                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2284                            FDI_FE_ERRC_ENABLE);
2285 }
2286
2287 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2288 {
2289         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2290 }
2291
2292 static void ivb_modeset_global_resources(struct drm_device *dev)
2293 {
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         struct intel_crtc *pipe_B_crtc =
2296                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2297         struct intel_crtc *pipe_C_crtc =
2298                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2299         uint32_t temp;
2300
2301         /*
2302          * When everything is off disable fdi C so that we could enable fdi B
2303          * with all lanes. Note that we don't care about enabled pipes without
2304          * an enabled pch encoder.
2305          */
2306         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2307             !pipe_has_enabled_pch(pipe_C_crtc)) {
2308                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2309                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2310
2311                 temp = I915_READ(SOUTH_CHICKEN1);
2312                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2313                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314                 I915_WRITE(SOUTH_CHICKEN1, temp);
2315         }
2316 }
2317
2318 /* The FDI link training functions for ILK/Ibexpeak. */
2319 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320 {
2321         struct drm_device *dev = crtc->dev;
2322         struct drm_i915_private *dev_priv = dev->dev_private;
2323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324         int pipe = intel_crtc->pipe;
2325         int plane = intel_crtc->plane;
2326         u32 reg, temp, tries;
2327
2328         /* FDI needs bits from pipe & plane first */
2329         assert_pipe_enabled(dev_priv, pipe);
2330         assert_plane_enabled(dev_priv, plane);
2331
2332         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333            for train result */
2334         reg = FDI_RX_IMR(pipe);
2335         temp = I915_READ(reg);
2336         temp &= ~FDI_RX_SYMBOL_LOCK;
2337         temp &= ~FDI_RX_BIT_LOCK;
2338         I915_WRITE(reg, temp);
2339         I915_READ(reg);
2340         udelay(150);
2341
2342         /* enable CPU FDI TX and PCH FDI RX */
2343         reg = FDI_TX_CTL(pipe);
2344         temp = I915_READ(reg);
2345         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2346         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2347         temp &= ~FDI_LINK_TRAIN_NONE;
2348         temp |= FDI_LINK_TRAIN_PATTERN_1;
2349         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         temp &= ~FDI_LINK_TRAIN_NONE;
2354         temp |= FDI_LINK_TRAIN_PATTERN_1;
2355         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2356
2357         POSTING_READ(reg);
2358         udelay(150);
2359
2360         /* Ironlake workaround, enable clock pointer after FDI enable*/
2361         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363                    FDI_RX_PHASE_SYNC_POINTER_EN);
2364
2365         reg = FDI_RX_IIR(pipe);
2366         for (tries = 0; tries < 5; tries++) {
2367                 temp = I915_READ(reg);
2368                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2369
2370                 if ((temp & FDI_RX_BIT_LOCK)) {
2371                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2372                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2373                         break;
2374                 }
2375         }
2376         if (tries == 5)
2377                 DRM_ERROR("FDI train 1 fail!\n");
2378
2379         /* Train 2 */
2380         reg = FDI_TX_CTL(pipe);
2381         temp = I915_READ(reg);
2382         temp &= ~FDI_LINK_TRAIN_NONE;
2383         temp |= FDI_LINK_TRAIN_PATTERN_2;
2384         I915_WRITE(reg, temp);
2385
2386         reg = FDI_RX_CTL(pipe);
2387         temp = I915_READ(reg);
2388         temp &= ~FDI_LINK_TRAIN_NONE;
2389         temp |= FDI_LINK_TRAIN_PATTERN_2;
2390         I915_WRITE(reg, temp);
2391
2392         POSTING_READ(reg);
2393         udelay(150);
2394
2395         reg = FDI_RX_IIR(pipe);
2396         for (tries = 0; tries < 5; tries++) {
2397                 temp = I915_READ(reg);
2398                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400                 if (temp & FDI_RX_SYMBOL_LOCK) {
2401                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2402                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2403                         break;
2404                 }
2405         }
2406         if (tries == 5)
2407                 DRM_ERROR("FDI train 2 fail!\n");
2408
2409         DRM_DEBUG_KMS("FDI train done\n");
2410
2411 }
2412
2413 static const int snb_b_fdi_train_param[] = {
2414         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2415         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2416         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2417         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2418 };
2419
2420 /* The FDI link training functions for SNB/Cougarpoint. */
2421 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2422 {
2423         struct drm_device *dev = crtc->dev;
2424         struct drm_i915_private *dev_priv = dev->dev_private;
2425         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426         int pipe = intel_crtc->pipe;
2427         u32 reg, temp, i, retry;
2428
2429         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430            for train result */
2431         reg = FDI_RX_IMR(pipe);
2432         temp = I915_READ(reg);
2433         temp &= ~FDI_RX_SYMBOL_LOCK;
2434         temp &= ~FDI_RX_BIT_LOCK;
2435         I915_WRITE(reg, temp);
2436
2437         POSTING_READ(reg);
2438         udelay(150);
2439
2440         /* enable CPU FDI TX and PCH FDI RX */
2441         reg = FDI_TX_CTL(pipe);
2442         temp = I915_READ(reg);
2443         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2444         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2445         temp &= ~FDI_LINK_TRAIN_NONE;
2446         temp |= FDI_LINK_TRAIN_PATTERN_1;
2447         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448         /* SNB-B */
2449         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2450         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2451
2452         I915_WRITE(FDI_RX_MISC(pipe),
2453                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2454
2455         reg = FDI_RX_CTL(pipe);
2456         temp = I915_READ(reg);
2457         if (HAS_PCH_CPT(dev)) {
2458                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2459                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2460         } else {
2461                 temp &= ~FDI_LINK_TRAIN_NONE;
2462                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463         }
2464         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2465
2466         POSTING_READ(reg);
2467         udelay(150);
2468
2469         for (i = 0; i < 4; i++) {
2470                 reg = FDI_TX_CTL(pipe);
2471                 temp = I915_READ(reg);
2472                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473                 temp |= snb_b_fdi_train_param[i];
2474                 I915_WRITE(reg, temp);
2475
2476                 POSTING_READ(reg);
2477                 udelay(500);
2478
2479                 for (retry = 0; retry < 5; retry++) {
2480                         reg = FDI_RX_IIR(pipe);
2481                         temp = I915_READ(reg);
2482                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483                         if (temp & FDI_RX_BIT_LOCK) {
2484                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486                                 break;
2487                         }
2488                         udelay(50);
2489                 }
2490                 if (retry < 5)
2491                         break;
2492         }
2493         if (i == 4)
2494                 DRM_ERROR("FDI train 1 fail!\n");
2495
2496         /* Train 2 */
2497         reg = FDI_TX_CTL(pipe);
2498         temp = I915_READ(reg);
2499         temp &= ~FDI_LINK_TRAIN_NONE;
2500         temp |= FDI_LINK_TRAIN_PATTERN_2;
2501         if (IS_GEN6(dev)) {
2502                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503                 /* SNB-B */
2504                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505         }
2506         I915_WRITE(reg, temp);
2507
2508         reg = FDI_RX_CTL(pipe);
2509         temp = I915_READ(reg);
2510         if (HAS_PCH_CPT(dev)) {
2511                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2513         } else {
2514                 temp &= ~FDI_LINK_TRAIN_NONE;
2515                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2516         }
2517         I915_WRITE(reg, temp);
2518
2519         POSTING_READ(reg);
2520         udelay(150);
2521
2522         for (i = 0; i < 4; i++) {
2523                 reg = FDI_TX_CTL(pipe);
2524                 temp = I915_READ(reg);
2525                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526                 temp |= snb_b_fdi_train_param[i];
2527                 I915_WRITE(reg, temp);
2528
2529                 POSTING_READ(reg);
2530                 udelay(500);
2531
2532                 for (retry = 0; retry < 5; retry++) {
2533                         reg = FDI_RX_IIR(pipe);
2534                         temp = I915_READ(reg);
2535                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536                         if (temp & FDI_RX_SYMBOL_LOCK) {
2537                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539                                 break;
2540                         }
2541                         udelay(50);
2542                 }
2543                 if (retry < 5)
2544                         break;
2545         }
2546         if (i == 4)
2547                 DRM_ERROR("FDI train 2 fail!\n");
2548
2549         DRM_DEBUG_KMS("FDI train done.\n");
2550 }
2551
2552 /* Manual link training for Ivy Bridge A0 parts */
2553 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2554 {
2555         struct drm_device *dev = crtc->dev;
2556         struct drm_i915_private *dev_priv = dev->dev_private;
2557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558         int pipe = intel_crtc->pipe;
2559         u32 reg, temp, i;
2560
2561         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562            for train result */
2563         reg = FDI_RX_IMR(pipe);
2564         temp = I915_READ(reg);
2565         temp &= ~FDI_RX_SYMBOL_LOCK;
2566         temp &= ~FDI_RX_BIT_LOCK;
2567         I915_WRITE(reg, temp);
2568
2569         POSTING_READ(reg);
2570         udelay(150);
2571
2572         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573                       I915_READ(FDI_RX_IIR(pipe)));
2574
2575         /* enable CPU FDI TX and PCH FDI RX */
2576         reg = FDI_TX_CTL(pipe);
2577         temp = I915_READ(reg);
2578         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2580         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2581         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2582         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584         temp |= FDI_COMPOSITE_SYNC;
2585         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
2587         I915_WRITE(FDI_RX_MISC(pipe),
2588                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
2590         reg = FDI_RX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         temp &= ~FDI_LINK_TRAIN_AUTO;
2593         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2595         temp |= FDI_COMPOSITE_SYNC;
2596         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598         POSTING_READ(reg);
2599         udelay(150);
2600
2601         for (i = 0; i < 4; i++) {
2602                 reg = FDI_TX_CTL(pipe);
2603                 temp = I915_READ(reg);
2604                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605                 temp |= snb_b_fdi_train_param[i];
2606                 I915_WRITE(reg, temp);
2607
2608                 POSTING_READ(reg);
2609                 udelay(500);
2610
2611                 reg = FDI_RX_IIR(pipe);
2612                 temp = I915_READ(reg);
2613                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614
2615                 if (temp & FDI_RX_BIT_LOCK ||
2616                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2617                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2618                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2619                         break;
2620                 }
2621         }
2622         if (i == 4)
2623                 DRM_ERROR("FDI train 1 fail!\n");
2624
2625         /* Train 2 */
2626         reg = FDI_TX_CTL(pipe);
2627         temp = I915_READ(reg);
2628         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2629         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2630         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632         I915_WRITE(reg, temp);
2633
2634         reg = FDI_RX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638         I915_WRITE(reg, temp);
2639
2640         POSTING_READ(reg);
2641         udelay(150);
2642
2643         for (i = 0; i < 4; i++) {
2644                 reg = FDI_TX_CTL(pipe);
2645                 temp = I915_READ(reg);
2646                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647                 temp |= snb_b_fdi_train_param[i];
2648                 I915_WRITE(reg, temp);
2649
2650                 POSTING_READ(reg);
2651                 udelay(500);
2652
2653                 reg = FDI_RX_IIR(pipe);
2654                 temp = I915_READ(reg);
2655                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657                 if (temp & FDI_RX_SYMBOL_LOCK) {
2658                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2659                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2660                         break;
2661                 }
2662         }
2663         if (i == 4)
2664                 DRM_ERROR("FDI train 2 fail!\n");
2665
2666         DRM_DEBUG_KMS("FDI train done.\n");
2667 }
2668
2669 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2670 {
2671         struct drm_device *dev = intel_crtc->base.dev;
2672         struct drm_i915_private *dev_priv = dev->dev_private;
2673         int pipe = intel_crtc->pipe;
2674         u32 reg, temp;
2675
2676
2677         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2678         reg = FDI_RX_CTL(pipe);
2679         temp = I915_READ(reg);
2680         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2681         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2682         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2683         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2684
2685         POSTING_READ(reg);
2686         udelay(200);
2687
2688         /* Switch from Rawclk to PCDclk */
2689         temp = I915_READ(reg);
2690         I915_WRITE(reg, temp | FDI_PCDCLK);
2691
2692         POSTING_READ(reg);
2693         udelay(200);
2694
2695         /* Enable CPU FDI TX PLL, always on for Ironlake */
2696         reg = FDI_TX_CTL(pipe);
2697         temp = I915_READ(reg);
2698         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2699                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2700
2701                 POSTING_READ(reg);
2702                 udelay(100);
2703         }
2704 }
2705
2706 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2707 {
2708         struct drm_device *dev = intel_crtc->base.dev;
2709         struct drm_i915_private *dev_priv = dev->dev_private;
2710         int pipe = intel_crtc->pipe;
2711         u32 reg, temp;
2712
2713         /* Switch from PCDclk to Rawclk */
2714         reg = FDI_RX_CTL(pipe);
2715         temp = I915_READ(reg);
2716         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2717
2718         /* Disable CPU FDI TX PLL */
2719         reg = FDI_TX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2722
2723         POSTING_READ(reg);
2724         udelay(100);
2725
2726         reg = FDI_RX_CTL(pipe);
2727         temp = I915_READ(reg);
2728         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2729
2730         /* Wait for the clocks to turn off. */
2731         POSTING_READ(reg);
2732         udelay(100);
2733 }
2734
2735 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740         int pipe = intel_crtc->pipe;
2741         u32 reg, temp;
2742
2743         /* disable CPU FDI tx and PCH FDI rx */
2744         reg = FDI_TX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747         POSTING_READ(reg);
2748
2749         reg = FDI_RX_CTL(pipe);
2750         temp = I915_READ(reg);
2751         temp &= ~(0x7 << 16);
2752         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2753         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755         POSTING_READ(reg);
2756         udelay(100);
2757
2758         /* Ironlake workaround, disable clock pointer after downing FDI */
2759         if (HAS_PCH_IBX(dev)) {
2760                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2761         }
2762
2763         /* still set train pattern 1 */
2764         reg = FDI_TX_CTL(pipe);
2765         temp = I915_READ(reg);
2766         temp &= ~FDI_LINK_TRAIN_NONE;
2767         temp |= FDI_LINK_TRAIN_PATTERN_1;
2768         I915_WRITE(reg, temp);
2769
2770         reg = FDI_RX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         if (HAS_PCH_CPT(dev)) {
2773                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775         } else {
2776                 temp &= ~FDI_LINK_TRAIN_NONE;
2777                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778         }
2779         /* BPC in FDI rx is consistent with that in PIPECONF */
2780         temp &= ~(0x07 << 16);
2781         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2782         I915_WRITE(reg, temp);
2783
2784         POSTING_READ(reg);
2785         udelay(100);
2786 }
2787
2788 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2789 {
2790         struct drm_device *dev = crtc->dev;
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2793         unsigned long flags;
2794         bool pending;
2795
2796         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2797             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2798                 return false;
2799
2800         spin_lock_irqsave(&dev->event_lock, flags);
2801         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2802         spin_unlock_irqrestore(&dev->event_lock, flags);
2803
2804         return pending;
2805 }
2806
2807 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808 {
2809         struct drm_device *dev = crtc->dev;
2810         struct drm_i915_private *dev_priv = dev->dev_private;
2811
2812         if (crtc->fb == NULL)
2813                 return;
2814
2815         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2816
2817         wait_event(dev_priv->pending_flip_queue,
2818                    !intel_crtc_has_pending_flip(crtc));
2819
2820         mutex_lock(&dev->struct_mutex);
2821         intel_finish_fb(crtc->fb);
2822         mutex_unlock(&dev->struct_mutex);
2823 }
2824
2825 /* Program iCLKIP clock to the desired frequency */
2826 static void lpt_program_iclkip(struct drm_crtc *crtc)
2827 {
2828         struct drm_device *dev = crtc->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2831         u32 temp;
2832
2833         mutex_lock(&dev_priv->dpio_lock);
2834
2835         /* It is necessary to ungate the pixclk gate prior to programming
2836          * the divisors, and gate it back when it is done.
2837          */
2838         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2839
2840         /* Disable SSCCTL */
2841         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2842                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2843                                 SBI_SSCCTL_DISABLE,
2844                         SBI_ICLK);
2845
2846         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847         if (crtc->mode.clock == 20000) {
2848                 auxdiv = 1;
2849                 divsel = 0x41;
2850                 phaseinc = 0x20;
2851         } else {
2852                 /* The iCLK virtual clock root frequency is in MHz,
2853                  * but the crtc->mode.clock in in KHz. To get the divisors,
2854                  * it is necessary to divide one by another, so we
2855                  * convert the virtual clock precision to KHz here for higher
2856                  * precision.
2857                  */
2858                 u32 iclk_virtual_root_freq = 172800 * 1000;
2859                 u32 iclk_pi_range = 64;
2860                 u32 desired_divisor, msb_divisor_value, pi_value;
2861
2862                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2863                 msb_divisor_value = desired_divisor / iclk_pi_range;
2864                 pi_value = desired_divisor % iclk_pi_range;
2865
2866                 auxdiv = 0;
2867                 divsel = msb_divisor_value - 2;
2868                 phaseinc = pi_value;
2869         }
2870
2871         /* This should not happen with any sane values */
2872         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2873                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2874         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2875                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2876
2877         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2878                         crtc->mode.clock,
2879                         auxdiv,
2880                         divsel,
2881                         phasedir,
2882                         phaseinc);
2883
2884         /* Program SSCDIVINTPHASE6 */
2885         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2886         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2887         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2888         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2889         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2890         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2891         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2892         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2893
2894         /* Program SSCAUXDIV */
2895         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2896         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2898         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2899
2900         /* Enable modulator and associated divider */
2901         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2902         temp &= ~SBI_SSCCTL_DISABLE;
2903         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2904
2905         /* Wait for initialization time */
2906         udelay(24);
2907
2908         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2909
2910         mutex_unlock(&dev_priv->dpio_lock);
2911 }
2912
2913 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2914                                                 enum pipe pch_transcoder)
2915 {
2916         struct drm_device *dev = crtc->base.dev;
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2919
2920         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2921                    I915_READ(HTOTAL(cpu_transcoder)));
2922         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2923                    I915_READ(HBLANK(cpu_transcoder)));
2924         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2925                    I915_READ(HSYNC(cpu_transcoder)));
2926
2927         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2928                    I915_READ(VTOTAL(cpu_transcoder)));
2929         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2930                    I915_READ(VBLANK(cpu_transcoder)));
2931         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2932                    I915_READ(VSYNC(cpu_transcoder)));
2933         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2934                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
2935 }
2936
2937 /*
2938  * Enable PCH resources required for PCH ports:
2939  *   - PCH PLLs
2940  *   - FDI training & RX/TX
2941  *   - update transcoder timings
2942  *   - DP transcoding bits
2943  *   - transcoder
2944  */
2945 static void ironlake_pch_enable(struct drm_crtc *crtc)
2946 {
2947         struct drm_device *dev = crtc->dev;
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950         int pipe = intel_crtc->pipe;
2951         u32 reg, temp;
2952
2953         assert_pch_transcoder_disabled(dev_priv, pipe);
2954
2955         /* Write the TU size bits before fdi link training, so that error
2956          * detection works. */
2957         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2958                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2959
2960         /* For PCH output, training FDI link */
2961         dev_priv->display.fdi_link_train(crtc);
2962
2963         /* XXX: pch pll's can be enabled any time before we enable the PCH
2964          * transcoder, and we actually should do this to not upset any PCH
2965          * transcoder that already use the clock when we share it.
2966          *
2967          * Note that enable_shared_dpll tries to do the right thing, but
2968          * get_shared_dpll unconditionally resets the pll - we need that to have
2969          * the right LVDS enable sequence. */
2970         ironlake_enable_shared_dpll(intel_crtc);
2971
2972         if (HAS_PCH_CPT(dev)) {
2973                 u32 sel;
2974
2975                 temp = I915_READ(PCH_DPLL_SEL);
2976                 temp |= TRANS_DPLL_ENABLE(pipe);
2977                 sel = TRANS_DPLLB_SEL(pipe);
2978                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2979                         temp |= sel;
2980                 else
2981                         temp &= ~sel;
2982                 I915_WRITE(PCH_DPLL_SEL, temp);
2983         }
2984
2985         /* set transcoder timing, panel must allow it */
2986         assert_panel_unlocked(dev_priv, pipe);
2987         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2988
2989         intel_fdi_normal_train(crtc);
2990
2991         /* For PCH DP, enable TRANS_DP_CTL */
2992         if (HAS_PCH_CPT(dev) &&
2993             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2994              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2995                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2996                 reg = TRANS_DP_CTL(pipe);
2997                 temp = I915_READ(reg);
2998                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2999                           TRANS_DP_SYNC_MASK |
3000                           TRANS_DP_BPC_MASK);
3001                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3002                          TRANS_DP_ENH_FRAMING);
3003                 temp |= bpc << 9; /* same format but at 11:9 */
3004
3005                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3006                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3007                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3008                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3009
3010                 switch (intel_trans_dp_port_sel(crtc)) {
3011                 case PCH_DP_B:
3012                         temp |= TRANS_DP_PORT_SEL_B;
3013                         break;
3014                 case PCH_DP_C:
3015                         temp |= TRANS_DP_PORT_SEL_C;
3016                         break;
3017                 case PCH_DP_D:
3018                         temp |= TRANS_DP_PORT_SEL_D;
3019                         break;
3020                 default:
3021                         BUG();
3022                 }
3023
3024                 I915_WRITE(reg, temp);
3025         }
3026
3027         ironlake_enable_pch_transcoder(dev_priv, pipe);
3028 }
3029
3030 static void lpt_pch_enable(struct drm_crtc *crtc)
3031 {
3032         struct drm_device *dev = crtc->dev;
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3036
3037         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3038
3039         lpt_program_iclkip(crtc);
3040
3041         /* Set transcoder timing. */
3042         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3043
3044         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3045 }
3046
3047 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3048 {
3049         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3050
3051         if (pll == NULL)
3052                 return;
3053
3054         if (pll->refcount == 0) {
3055                 WARN(1, "bad %s refcount\n", pll->name);
3056                 return;
3057         }
3058
3059         if (--pll->refcount == 0) {
3060                 WARN_ON(pll->on);
3061                 WARN_ON(pll->active);
3062         }
3063
3064         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3065 }
3066
3067 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3068 {
3069         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3070         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3071         enum intel_dpll_id i;
3072
3073         if (pll) {
3074                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3075                               crtc->base.base.id, pll->name);
3076                 intel_put_shared_dpll(crtc);
3077         }
3078
3079         if (HAS_PCH_IBX(dev_priv->dev)) {
3080                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3081                 i = crtc->pipe;
3082                 pll = &dev_priv->shared_dplls[i];
3083
3084                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3085                               crtc->base.base.id, pll->name);
3086
3087                 goto found;
3088         }
3089
3090         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3091                 pll = &dev_priv->shared_dplls[i];
3092
3093                 /* Only want to check enabled timings first */
3094                 if (pll->refcount == 0)
3095                         continue;
3096
3097                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3098                            sizeof(pll->hw_state)) == 0) {
3099                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3100                                       crtc->base.base.id,
3101                                       pll->name, pll->refcount, pll->active);
3102
3103                         goto found;
3104                 }
3105         }
3106
3107         /* Ok no matching timings, maybe there's a free one? */
3108         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3109                 pll = &dev_priv->shared_dplls[i];
3110                 if (pll->refcount == 0) {
3111                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3112                                       crtc->base.base.id, pll->name);
3113                         goto found;
3114                 }
3115         }
3116
3117         return NULL;
3118
3119 found:
3120         crtc->config.shared_dpll = i;
3121         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3122                          pipe_name(crtc->pipe));
3123
3124         if (pll->active == 0) {
3125                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3126                        sizeof(pll->hw_state));
3127
3128                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3129                 WARN_ON(pll->on);
3130                 assert_shared_dpll_disabled(dev_priv, pll);
3131
3132                 pll->mode_set(dev_priv, pll);
3133         }
3134         pll->refcount++;
3135
3136         return pll;
3137 }
3138
3139 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3140 {
3141         struct drm_i915_private *dev_priv = dev->dev_private;
3142         int dslreg = PIPEDSL(pipe);
3143         u32 temp;
3144
3145         temp = I915_READ(dslreg);
3146         udelay(500);
3147         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3148                 if (wait_for(I915_READ(dslreg) != temp, 5))
3149                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3150         }
3151 }
3152
3153 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3154 {
3155         struct drm_device *dev = crtc->base.dev;
3156         struct drm_i915_private *dev_priv = dev->dev_private;
3157         int pipe = crtc->pipe;
3158
3159         if (crtc->config.pch_pfit.size) {
3160                 /* Force use of hard-coded filter coefficients
3161                  * as some pre-programmed values are broken,
3162                  * e.g. x201.
3163                  */
3164                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3165                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3166                                                  PF_PIPE_SEL_IVB(pipe));
3167                 else
3168                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3169                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3170                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3171         }
3172 }
3173
3174 static void intel_enable_planes(struct drm_crtc *crtc)
3175 {
3176         struct drm_device *dev = crtc->dev;
3177         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3178         struct intel_plane *intel_plane;
3179
3180         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3181                 if (intel_plane->pipe == pipe)
3182                         intel_plane_restore(&intel_plane->base);
3183 }
3184
3185 static void intel_disable_planes(struct drm_crtc *crtc)
3186 {
3187         struct drm_device *dev = crtc->dev;
3188         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3189         struct intel_plane *intel_plane;
3190
3191         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3192                 if (intel_plane->pipe == pipe)
3193                         intel_plane_disable(&intel_plane->base);
3194 }
3195
3196 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3197 {
3198         struct drm_device *dev = crtc->dev;
3199         struct drm_i915_private *dev_priv = dev->dev_private;
3200         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201         struct intel_encoder *encoder;
3202         int pipe = intel_crtc->pipe;
3203         int plane = intel_crtc->plane;
3204
3205         WARN_ON(!crtc->enabled);
3206
3207         if (intel_crtc->active)
3208                 return;
3209
3210         intel_crtc->active = true;
3211
3212         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3213         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3214
3215         intel_update_watermarks(dev);
3216
3217         for_each_encoder_on_crtc(dev, crtc, encoder) {
3218                 if (encoder->pre_pll_enable)
3219                         encoder->pre_pll_enable(encoder);
3220                 if (encoder->pre_enable)
3221                         encoder->pre_enable(encoder);
3222         }
3223
3224         if (intel_crtc->config.has_pch_encoder) {
3225                 /* Note: FDI PLL enabling _must_ be done before we enable the
3226                  * cpu pipes, hence this is separate from all the other fdi/pch
3227                  * enabling. */
3228                 ironlake_fdi_pll_enable(intel_crtc);
3229         } else {
3230                 assert_fdi_tx_disabled(dev_priv, pipe);
3231                 assert_fdi_rx_disabled(dev_priv, pipe);
3232         }
3233
3234         ironlake_pfit_enable(intel_crtc);
3235
3236         /*
3237          * On ILK+ LUT must be loaded before the pipe is running but with
3238          * clocks enabled
3239          */
3240         intel_crtc_load_lut(crtc);
3241
3242         intel_enable_pipe(dev_priv, pipe,
3243                           intel_crtc->config.has_pch_encoder);
3244         intel_enable_plane(dev_priv, plane, pipe);
3245         intel_enable_planes(crtc);
3246         intel_crtc_update_cursor(crtc, true);
3247
3248         if (intel_crtc->config.has_pch_encoder)
3249                 ironlake_pch_enable(crtc);
3250
3251         mutex_lock(&dev->struct_mutex);
3252         intel_update_fbc(dev);
3253         mutex_unlock(&dev->struct_mutex);
3254
3255         for_each_encoder_on_crtc(dev, crtc, encoder)
3256                 encoder->enable(encoder);
3257
3258         if (HAS_PCH_CPT(dev))
3259                 cpt_verify_modeset(dev, intel_crtc->pipe);
3260
3261         /*
3262          * There seems to be a race in PCH platform hw (at least on some
3263          * outputs) where an enabled pipe still completes any pageflip right
3264          * away (as if the pipe is off) instead of waiting for vblank. As soon
3265          * as the first vblank happend, everything works as expected. Hence just
3266          * wait for one vblank before returning to avoid strange things
3267          * happening.
3268          */
3269         intel_wait_for_vblank(dev, intel_crtc->pipe);
3270 }
3271
3272 /* IPS only exists on ULT machines and is tied to pipe A. */
3273 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3274 {
3275         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3276 }
3277
3278 static void hsw_enable_ips(struct intel_crtc *crtc)
3279 {
3280         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3281
3282         if (!crtc->config.ips_enabled)
3283                 return;
3284
3285         /* We can only enable IPS after we enable a plane and wait for a vblank.
3286          * We guarantee that the plane is enabled by calling intel_enable_ips
3287          * only after intel_enable_plane. And intel_enable_plane already waits
3288          * for a vblank, so all we need to do here is to enable the IPS bit. */
3289         assert_plane_enabled(dev_priv, crtc->plane);
3290         I915_WRITE(IPS_CTL, IPS_ENABLE);
3291 }
3292
3293 static void hsw_disable_ips(struct intel_crtc *crtc)
3294 {
3295         struct drm_device *dev = crtc->base.dev;
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297
3298         if (!crtc->config.ips_enabled)
3299                 return;
3300
3301         assert_plane_enabled(dev_priv, crtc->plane);
3302         I915_WRITE(IPS_CTL, 0);
3303
3304         /* We need to wait for a vblank before we can disable the plane. */
3305         intel_wait_for_vblank(dev, crtc->pipe);
3306 }
3307
3308 static void haswell_crtc_enable(struct drm_crtc *crtc)
3309 {
3310         struct drm_device *dev = crtc->dev;
3311         struct drm_i915_private *dev_priv = dev->dev_private;
3312         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3313         struct intel_encoder *encoder;
3314         int pipe = intel_crtc->pipe;
3315         int plane = intel_crtc->plane;
3316
3317         WARN_ON(!crtc->enabled);
3318
3319         if (intel_crtc->active)
3320                 return;
3321
3322         intel_crtc->active = true;
3323
3324         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3325         if (intel_crtc->config.has_pch_encoder)
3326                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3327
3328         intel_update_watermarks(dev);
3329
3330         if (intel_crtc->config.has_pch_encoder)
3331                 dev_priv->display.fdi_link_train(crtc);
3332
3333         for_each_encoder_on_crtc(dev, crtc, encoder)
3334                 if (encoder->pre_enable)
3335                         encoder->pre_enable(encoder);
3336
3337         intel_ddi_enable_pipe_clock(intel_crtc);
3338
3339         ironlake_pfit_enable(intel_crtc);
3340
3341         /*
3342          * On ILK+ LUT must be loaded before the pipe is running but with
3343          * clocks enabled
3344          */
3345         intel_crtc_load_lut(crtc);
3346
3347         intel_ddi_set_pipe_settings(crtc);
3348         intel_ddi_enable_transcoder_func(crtc);
3349
3350         intel_enable_pipe(dev_priv, pipe,
3351                           intel_crtc->config.has_pch_encoder);
3352         intel_enable_plane(dev_priv, plane, pipe);
3353         intel_enable_planes(crtc);
3354         intel_crtc_update_cursor(crtc, true);
3355
3356         hsw_enable_ips(intel_crtc);
3357
3358         if (intel_crtc->config.has_pch_encoder)
3359                 lpt_pch_enable(crtc);
3360
3361         mutex_lock(&dev->struct_mutex);
3362         intel_update_fbc(dev);
3363         mutex_unlock(&dev->struct_mutex);
3364
3365         for_each_encoder_on_crtc(dev, crtc, encoder)
3366                 encoder->enable(encoder);
3367
3368         /*
3369          * There seems to be a race in PCH platform hw (at least on some
3370          * outputs) where an enabled pipe still completes any pageflip right
3371          * away (as if the pipe is off) instead of waiting for vblank. As soon
3372          * as the first vblank happend, everything works as expected. Hence just
3373          * wait for one vblank before returning to avoid strange things
3374          * happening.
3375          */
3376         intel_wait_for_vblank(dev, intel_crtc->pipe);
3377 }
3378
3379 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3380 {
3381         struct drm_device *dev = crtc->base.dev;
3382         struct drm_i915_private *dev_priv = dev->dev_private;
3383         int pipe = crtc->pipe;
3384
3385         /* To avoid upsetting the power well on haswell only disable the pfit if
3386          * it's in use. The hw state code will make sure we get this right. */
3387         if (crtc->config.pch_pfit.size) {
3388                 I915_WRITE(PF_CTL(pipe), 0);
3389                 I915_WRITE(PF_WIN_POS(pipe), 0);
3390                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3391         }
3392 }
3393
3394 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3395 {
3396         struct drm_device *dev = crtc->dev;
3397         struct drm_i915_private *dev_priv = dev->dev_private;
3398         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399         struct intel_encoder *encoder;
3400         int pipe = intel_crtc->pipe;
3401         int plane = intel_crtc->plane;
3402         u32 reg, temp;
3403
3404
3405         if (!intel_crtc->active)
3406                 return;
3407
3408         for_each_encoder_on_crtc(dev, crtc, encoder)
3409                 encoder->disable(encoder);
3410
3411         intel_crtc_wait_for_pending_flips(crtc);
3412         drm_vblank_off(dev, pipe);
3413
3414         if (dev_priv->cfb_plane == plane)
3415                 intel_disable_fbc(dev);
3416
3417         intel_crtc_update_cursor(crtc, false);
3418         intel_disable_planes(crtc);
3419         intel_disable_plane(dev_priv, plane, pipe);
3420
3421         if (intel_crtc->config.has_pch_encoder)
3422                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3423
3424         intel_disable_pipe(dev_priv, pipe);
3425
3426         ironlake_pfit_disable(intel_crtc);
3427
3428         for_each_encoder_on_crtc(dev, crtc, encoder)
3429                 if (encoder->post_disable)
3430                         encoder->post_disable(encoder);
3431
3432         if (intel_crtc->config.has_pch_encoder) {
3433                 ironlake_fdi_disable(crtc);
3434
3435                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3436                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3437
3438                 if (HAS_PCH_CPT(dev)) {
3439                         /* disable TRANS_DP_CTL */
3440                         reg = TRANS_DP_CTL(pipe);
3441                         temp = I915_READ(reg);
3442                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3443                                   TRANS_DP_PORT_SEL_MASK);
3444                         temp |= TRANS_DP_PORT_SEL_NONE;
3445                         I915_WRITE(reg, temp);
3446
3447                         /* disable DPLL_SEL */
3448                         temp = I915_READ(PCH_DPLL_SEL);
3449                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3450                         I915_WRITE(PCH_DPLL_SEL, temp);
3451                 }
3452
3453                 /* disable PCH DPLL */
3454                 intel_disable_shared_dpll(intel_crtc);
3455
3456                 ironlake_fdi_pll_disable(intel_crtc);
3457         }
3458
3459         intel_crtc->active = false;
3460         intel_update_watermarks(dev);
3461
3462         mutex_lock(&dev->struct_mutex);
3463         intel_update_fbc(dev);
3464         mutex_unlock(&dev->struct_mutex);
3465 }
3466
3467 static void haswell_crtc_disable(struct drm_crtc *crtc)
3468 {
3469         struct drm_device *dev = crtc->dev;
3470         struct drm_i915_private *dev_priv = dev->dev_private;
3471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3472         struct intel_encoder *encoder;
3473         int pipe = intel_crtc->pipe;
3474         int plane = intel_crtc->plane;
3475         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3476
3477         if (!intel_crtc->active)
3478                 return;
3479
3480         for_each_encoder_on_crtc(dev, crtc, encoder)
3481                 encoder->disable(encoder);
3482
3483         intel_crtc_wait_for_pending_flips(crtc);
3484         drm_vblank_off(dev, pipe);
3485
3486         /* FBC must be disabled before disabling the plane on HSW. */
3487         if (dev_priv->cfb_plane == plane)
3488                 intel_disable_fbc(dev);
3489
3490         hsw_disable_ips(intel_crtc);
3491
3492         intel_crtc_update_cursor(crtc, false);
3493         intel_disable_planes(crtc);
3494         intel_disable_plane(dev_priv, plane, pipe);
3495
3496         if (intel_crtc->config.has_pch_encoder)
3497                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3498         intel_disable_pipe(dev_priv, pipe);
3499
3500         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3501
3502         ironlake_pfit_disable(intel_crtc);
3503
3504         intel_ddi_disable_pipe_clock(intel_crtc);
3505
3506         for_each_encoder_on_crtc(dev, crtc, encoder)
3507                 if (encoder->post_disable)
3508                         encoder->post_disable(encoder);
3509
3510         if (intel_crtc->config.has_pch_encoder) {
3511                 lpt_disable_pch_transcoder(dev_priv);
3512                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3513                 intel_ddi_fdi_disable(crtc);
3514         }
3515
3516         intel_crtc->active = false;
3517         intel_update_watermarks(dev);
3518
3519         mutex_lock(&dev->struct_mutex);
3520         intel_update_fbc(dev);
3521         mutex_unlock(&dev->struct_mutex);
3522 }
3523
3524 static void ironlake_crtc_off(struct drm_crtc *crtc)
3525 {
3526         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3527         intel_put_shared_dpll(intel_crtc);
3528 }
3529
3530 static void haswell_crtc_off(struct drm_crtc *crtc)
3531 {
3532         intel_ddi_put_crtc_pll(crtc);
3533 }
3534
3535 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3536 {
3537         if (!enable && intel_crtc->overlay) {
3538                 struct drm_device *dev = intel_crtc->base.dev;
3539                 struct drm_i915_private *dev_priv = dev->dev_private;
3540
3541                 mutex_lock(&dev->struct_mutex);
3542                 dev_priv->mm.interruptible = false;
3543                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3544                 dev_priv->mm.interruptible = true;
3545                 mutex_unlock(&dev->struct_mutex);
3546         }
3547
3548         /* Let userspace switch the overlay on again. In most cases userspace
3549          * has to recompute where to put it anyway.
3550          */
3551 }
3552
3553 /**
3554  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3555  * cursor plane briefly if not already running after enabling the display
3556  * plane.
3557  * This workaround avoids occasional blank screens when self refresh is
3558  * enabled.
3559  */
3560 static void
3561 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3562 {
3563         u32 cntl = I915_READ(CURCNTR(pipe));
3564
3565         if ((cntl & CURSOR_MODE) == 0) {
3566                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3567
3568                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3569                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3570                 intel_wait_for_vblank(dev_priv->dev, pipe);
3571                 I915_WRITE(CURCNTR(pipe), cntl);
3572                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3573                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3574         }
3575 }
3576
3577 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3578 {
3579         struct drm_device *dev = crtc->base.dev;
3580         struct drm_i915_private *dev_priv = dev->dev_private;
3581         struct intel_crtc_config *pipe_config = &crtc->config;
3582
3583         if (!crtc->config.gmch_pfit.control)
3584                 return;
3585
3586         /*
3587          * The panel fitter should only be adjusted whilst the pipe is disabled,
3588          * according to register description and PRM.
3589          */
3590         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3591         assert_pipe_disabled(dev_priv, crtc->pipe);
3592
3593         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3594         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3595
3596         /* Border color in case we don't scale up to the full screen. Black by
3597          * default, change to something else for debugging. */
3598         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3599 }
3600
3601 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3602 {
3603         struct drm_device *dev = crtc->dev;
3604         struct drm_i915_private *dev_priv = dev->dev_private;
3605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3606         struct intel_encoder *encoder;
3607         int pipe = intel_crtc->pipe;
3608         int plane = intel_crtc->plane;
3609
3610         WARN_ON(!crtc->enabled);
3611
3612         if (intel_crtc->active)
3613                 return;
3614
3615         intel_crtc->active = true;
3616         intel_update_watermarks(dev);
3617
3618         mutex_lock(&dev_priv->dpio_lock);
3619
3620         for_each_encoder_on_crtc(dev, crtc, encoder)
3621                 if (encoder->pre_pll_enable)
3622                         encoder->pre_pll_enable(encoder);
3623
3624         vlv_enable_pll(dev_priv, pipe);
3625
3626         for_each_encoder_on_crtc(dev, crtc, encoder)
3627                 if (encoder->pre_enable)
3628                         encoder->pre_enable(encoder);
3629
3630         /* VLV wants encoder enabling _before_ the pipe is up. */
3631         for_each_encoder_on_crtc(dev, crtc, encoder)
3632                 encoder->enable(encoder);
3633
3634         i9xx_pfit_enable(intel_crtc);
3635
3636         intel_crtc_load_lut(crtc);
3637
3638         intel_enable_pipe(dev_priv, pipe, false);
3639         intel_enable_plane(dev_priv, plane, pipe);
3640         intel_enable_planes(crtc);
3641         intel_crtc_update_cursor(crtc, true);
3642
3643         intel_update_fbc(dev);
3644
3645         mutex_unlock(&dev_priv->dpio_lock);
3646 }
3647
3648 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3649 {
3650         struct drm_device *dev = crtc->dev;
3651         struct drm_i915_private *dev_priv = dev->dev_private;
3652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653         struct intel_encoder *encoder;
3654         int pipe = intel_crtc->pipe;
3655         int plane = intel_crtc->plane;
3656
3657         WARN_ON(!crtc->enabled);
3658
3659         if (intel_crtc->active)
3660                 return;
3661
3662         intel_crtc->active = true;
3663         intel_update_watermarks(dev);
3664
3665         for_each_encoder_on_crtc(dev, crtc, encoder)
3666                 if (encoder->pre_pll_enable)
3667                         encoder->pre_pll_enable(encoder);
3668
3669         i9xx_enable_pll(intel_crtc);
3670
3671         for_each_encoder_on_crtc(dev, crtc, encoder)
3672                 if (encoder->pre_enable)
3673                         encoder->pre_enable(encoder);
3674
3675         i9xx_pfit_enable(intel_crtc);
3676
3677         intel_crtc_load_lut(crtc);
3678
3679         intel_enable_pipe(dev_priv, pipe, false);
3680         intel_enable_plane(dev_priv, plane, pipe);
3681         intel_enable_planes(crtc);
3682         /* The fixup needs to happen before cursor is enabled */
3683         if (IS_G4X(dev))
3684                 g4x_fixup_plane(dev_priv, pipe);
3685         intel_crtc_update_cursor(crtc, true);
3686
3687         /* Give the overlay scaler a chance to enable if it's on this pipe */
3688         intel_crtc_dpms_overlay(intel_crtc, true);
3689
3690         intel_update_fbc(dev);
3691
3692         for_each_encoder_on_crtc(dev, crtc, encoder)
3693                 encoder->enable(encoder);
3694 }
3695
3696 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3697 {
3698         struct drm_device *dev = crtc->base.dev;
3699         struct drm_i915_private *dev_priv = dev->dev_private;
3700
3701         if (!crtc->config.gmch_pfit.control)
3702                 return;
3703
3704         assert_pipe_disabled(dev_priv, crtc->pipe);
3705
3706         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3707                          I915_READ(PFIT_CONTROL));
3708         I915_WRITE(PFIT_CONTROL, 0);
3709 }
3710
3711 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3712 {
3713         struct drm_device *dev = crtc->dev;
3714         struct drm_i915_private *dev_priv = dev->dev_private;
3715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716         struct intel_encoder *encoder;
3717         int pipe = intel_crtc->pipe;
3718         int plane = intel_crtc->plane;
3719
3720         if (!intel_crtc->active)
3721                 return;
3722
3723         for_each_encoder_on_crtc(dev, crtc, encoder)
3724                 encoder->disable(encoder);
3725
3726         /* Give the overlay scaler a chance to disable if it's on this pipe */
3727         intel_crtc_wait_for_pending_flips(crtc);
3728         drm_vblank_off(dev, pipe);
3729
3730         if (dev_priv->cfb_plane == plane)
3731                 intel_disable_fbc(dev);
3732
3733         intel_crtc_dpms_overlay(intel_crtc, false);
3734         intel_crtc_update_cursor(crtc, false);
3735         intel_disable_planes(crtc);
3736         intel_disable_plane(dev_priv, plane, pipe);
3737
3738         intel_disable_pipe(dev_priv, pipe);
3739
3740         i9xx_pfit_disable(intel_crtc);
3741
3742         for_each_encoder_on_crtc(dev, crtc, encoder)
3743                 if (encoder->post_disable)
3744                         encoder->post_disable(encoder);
3745
3746         intel_disable_pll(dev_priv, pipe);
3747
3748         intel_crtc->active = false;
3749         intel_update_fbc(dev);
3750         intel_update_watermarks(dev);
3751 }
3752
3753 static void i9xx_crtc_off(struct drm_crtc *crtc)
3754 {
3755 }
3756
3757 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3758                                     bool enabled)
3759 {
3760         struct drm_device *dev = crtc->dev;
3761         struct drm_i915_master_private *master_priv;
3762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3763         int pipe = intel_crtc->pipe;
3764
3765         if (!dev->primary->master)
3766                 return;
3767
3768         master_priv = dev->primary->master->driver_priv;
3769         if (!master_priv->sarea_priv)
3770                 return;
3771
3772         switch (pipe) {
3773         case 0:
3774                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3775                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3776                 break;
3777         case 1:
3778                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3779                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3780                 break;
3781         default:
3782                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3783                 break;
3784         }
3785 }
3786
3787 /**
3788  * Sets the power management mode of the pipe and plane.
3789  */
3790 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3791 {
3792         struct drm_device *dev = crtc->dev;
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794         struct intel_encoder *intel_encoder;
3795         bool enable = false;
3796
3797         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3798                 enable |= intel_encoder->connectors_active;
3799
3800         if (enable)
3801                 dev_priv->display.crtc_enable(crtc);
3802         else
3803                 dev_priv->display.crtc_disable(crtc);
3804
3805         intel_crtc_update_sarea(crtc, enable);
3806 }
3807
3808 static void intel_crtc_disable(struct drm_crtc *crtc)
3809 {
3810         struct drm_device *dev = crtc->dev;
3811         struct drm_connector *connector;
3812         struct drm_i915_private *dev_priv = dev->dev_private;
3813         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3814
3815         /* crtc should still be enabled when we disable it. */
3816         WARN_ON(!crtc->enabled);
3817
3818         dev_priv->display.crtc_disable(crtc);
3819         intel_crtc->eld_vld = false;
3820         intel_crtc_update_sarea(crtc, false);
3821         dev_priv->display.off(crtc);
3822
3823         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3824         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3825
3826         if (crtc->fb) {
3827                 mutex_lock(&dev->struct_mutex);
3828                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3829                 mutex_unlock(&dev->struct_mutex);
3830                 crtc->fb = NULL;
3831         }
3832
3833         /* Update computed state. */
3834         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3835                 if (!connector->encoder || !connector->encoder->crtc)
3836                         continue;
3837
3838                 if (connector->encoder->crtc != crtc)
3839                         continue;
3840
3841                 connector->dpms = DRM_MODE_DPMS_OFF;
3842                 to_intel_encoder(connector->encoder)->connectors_active = false;
3843         }
3844 }
3845
3846 void intel_modeset_disable(struct drm_device *dev)
3847 {
3848         struct drm_crtc *crtc;
3849
3850         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3851                 if (crtc->enabled)
3852                         intel_crtc_disable(crtc);
3853         }
3854 }
3855
3856 void intel_encoder_destroy(struct drm_encoder *encoder)
3857 {
3858         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3859
3860         drm_encoder_cleanup(encoder);
3861         kfree(intel_encoder);
3862 }
3863
3864 /* Simple dpms helper for encodres with just one connector, no cloning and only
3865  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3866  * state of the entire output pipe. */
3867 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3868 {
3869         if (mode == DRM_MODE_DPMS_ON) {
3870                 encoder->connectors_active = true;
3871
3872                 intel_crtc_update_dpms(encoder->base.crtc);
3873         } else {
3874                 encoder->connectors_active = false;
3875
3876                 intel_crtc_update_dpms(encoder->base.crtc);
3877         }
3878 }
3879
3880 /* Cross check the actual hw state with our own modeset state tracking (and it's
3881  * internal consistency). */
3882 static void intel_connector_check_state(struct intel_connector *connector)
3883 {
3884         if (connector->get_hw_state(connector)) {
3885                 struct intel_encoder *encoder = connector->encoder;
3886                 struct drm_crtc *crtc;
3887                 bool encoder_enabled;
3888                 enum pipe pipe;
3889
3890                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3891                               connector->base.base.id,
3892                               drm_get_connector_name(&connector->base));
3893
3894                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3895                      "wrong connector dpms state\n");
3896                 WARN(connector->base.encoder != &encoder->base,
3897                      "active connector not linked to encoder\n");
3898                 WARN(!encoder->connectors_active,
3899                      "encoder->connectors_active not set\n");
3900
3901                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3902                 WARN(!encoder_enabled, "encoder not enabled\n");
3903                 if (WARN_ON(!encoder->base.crtc))
3904                         return;
3905
3906                 crtc = encoder->base.crtc;
3907
3908                 WARN(!crtc->enabled, "crtc not enabled\n");
3909                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3910                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3911                      "encoder active on the wrong pipe\n");
3912         }
3913 }
3914
3915 /* Even simpler default implementation, if there's really no special case to
3916  * consider. */
3917 void intel_connector_dpms(struct drm_connector *connector, int mode)
3918 {
3919         struct intel_encoder *encoder = intel_attached_encoder(connector);
3920
3921         /* All the simple cases only support two dpms states. */
3922         if (mode != DRM_MODE_DPMS_ON)
3923                 mode = DRM_MODE_DPMS_OFF;
3924
3925         if (mode == connector->dpms)
3926                 return;
3927
3928         connector->dpms = mode;
3929
3930         /* Only need to change hw state when actually enabled */
3931         if (encoder->base.crtc)
3932                 intel_encoder_dpms(encoder, mode);
3933         else
3934                 WARN_ON(encoder->connectors_active != false);
3935
3936         intel_modeset_check_state(connector->dev);
3937 }
3938
3939 /* Simple connector->get_hw_state implementation for encoders that support only
3940  * one connector and no cloning and hence the encoder state determines the state
3941  * of the connector. */
3942 bool intel_connector_get_hw_state(struct intel_connector *connector)
3943 {
3944         enum pipe pipe = 0;
3945         struct intel_encoder *encoder = connector->encoder;
3946
3947         return encoder->get_hw_state(encoder, &pipe);
3948 }
3949
3950 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3951                                      struct intel_crtc_config *pipe_config)
3952 {
3953         struct drm_i915_private *dev_priv = dev->dev_private;
3954         struct intel_crtc *pipe_B_crtc =
3955                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3956
3957         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3958                       pipe_name(pipe), pipe_config->fdi_lanes);
3959         if (pipe_config->fdi_lanes > 4) {
3960                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3961                               pipe_name(pipe), pipe_config->fdi_lanes);
3962                 return false;
3963         }
3964
3965         if (IS_HASWELL(dev)) {
3966                 if (pipe_config->fdi_lanes > 2) {
3967                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3968                                       pipe_config->fdi_lanes);
3969                         return false;
3970                 } else {
3971                         return true;
3972                 }
3973         }
3974
3975         if (INTEL_INFO(dev)->num_pipes == 2)
3976                 return true;
3977
3978         /* Ivybridge 3 pipe is really complicated */
3979         switch (pipe) {
3980         case PIPE_A:
3981                 return true;
3982         case PIPE_B:
3983                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3984                     pipe_config->fdi_lanes > 2) {
3985                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3986                                       pipe_name(pipe), pipe_config->fdi_lanes);
3987                         return false;
3988                 }
3989                 return true;
3990         case PIPE_C:
3991                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3992                     pipe_B_crtc->config.fdi_lanes <= 2) {
3993                         if (pipe_config->fdi_lanes > 2) {
3994                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3995                                               pipe_name(pipe), pipe_config->fdi_lanes);
3996                                 return false;
3997                         }
3998                 } else {
3999                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4000                         return false;
4001                 }
4002                 return true;
4003         default:
4004                 BUG();
4005         }
4006 }
4007
4008 #define RETRY 1
4009 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4010                                        struct intel_crtc_config *pipe_config)
4011 {
4012         struct drm_device *dev = intel_crtc->base.dev;
4013         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4014         int lane, link_bw, fdi_dotclock;
4015         bool setup_ok, needs_recompute = false;
4016
4017 retry:
4018         /* FDI is a binary signal running at ~2.7GHz, encoding
4019          * each output octet as 10 bits. The actual frequency
4020          * is stored as a divider into a 100MHz clock, and the
4021          * mode pixel clock is stored in units of 1KHz.
4022          * Hence the bw of each lane in terms of the mode signal
4023          * is:
4024          */
4025         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4026
4027         fdi_dotclock = adjusted_mode->clock;
4028         fdi_dotclock /= pipe_config->pixel_multiplier;
4029
4030         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4031                                            pipe_config->pipe_bpp);
4032
4033         pipe_config->fdi_lanes = lane;
4034
4035         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4036                                link_bw, &pipe_config->fdi_m_n);
4037
4038         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4039                                             intel_crtc->pipe, pipe_config);
4040         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4041                 pipe_config->pipe_bpp -= 2*3;
4042                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4043                               pipe_config->pipe_bpp);
4044                 needs_recompute = true;
4045                 pipe_config->bw_constrained = true;
4046
4047                 goto retry;
4048         }
4049
4050         if (needs_recompute)
4051                 return RETRY;
4052
4053         return setup_ok ? 0 : -EINVAL;
4054 }
4055
4056 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4057                                    struct intel_crtc_config *pipe_config)
4058 {
4059         pipe_config->ips_enabled = i915_enable_ips &&
4060                                    hsw_crtc_supports_ips(crtc) &&
4061                                    pipe_config->pipe_bpp == 24;
4062 }
4063
4064 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4065                                      struct intel_crtc_config *pipe_config)
4066 {
4067         struct drm_device *dev = crtc->base.dev;
4068         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4069
4070         if (HAS_PCH_SPLIT(dev)) {
4071                 /* FDI link clock is fixed at 2.7G */
4072                 if (pipe_config->requested_mode.clock * 3
4073                     > IRONLAKE_FDI_FREQ * 4)
4074                         return -EINVAL;
4075         }
4076
4077         /* All interlaced capable intel hw wants timings in frames. Note though
4078          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4079          * timings, so we need to be careful not to clobber these.*/
4080         if (!pipe_config->timings_set)
4081                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4082
4083         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4084          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4085          */
4086         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4087                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4088                 return -EINVAL;
4089
4090         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4091                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4092         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4093                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4094                  * for lvds. */
4095                 pipe_config->pipe_bpp = 8*3;
4096         }
4097
4098         if (HAS_IPS(dev))
4099                 hsw_compute_ips_config(crtc, pipe_config);
4100
4101         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4102          * clock survives for now. */
4103         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4104                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4105
4106         if (pipe_config->has_pch_encoder)
4107                 return ironlake_fdi_compute_config(crtc, pipe_config);
4108
4109         return 0;
4110 }
4111
4112 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4113 {
4114         return 400000; /* FIXME */
4115 }
4116
4117 static int i945_get_display_clock_speed(struct drm_device *dev)
4118 {
4119         return 400000;
4120 }
4121
4122 static int i915_get_display_clock_speed(struct drm_device *dev)
4123 {
4124         return 333000;
4125 }
4126
4127 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4128 {
4129         return 200000;
4130 }
4131
4132 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4133 {
4134         u16 gcfgc = 0;
4135
4136         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4137
4138         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4139                 return 133000;
4140         else {
4141                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4142                 case GC_DISPLAY_CLOCK_333_MHZ:
4143                         return 333000;
4144                 default:
4145                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4146                         return 190000;
4147                 }
4148         }
4149 }
4150
4151 static int i865_get_display_clock_speed(struct drm_device *dev)
4152 {
4153         return 266000;
4154 }
4155
4156 static int i855_get_display_clock_speed(struct drm_device *dev)
4157 {
4158         u16 hpllcc = 0;
4159         /* Assume that the hardware is in the high speed state.  This
4160          * should be the default.
4161          */
4162         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4163         case GC_CLOCK_133_200:
4164         case GC_CLOCK_100_200:
4165                 return 200000;
4166         case GC_CLOCK_166_250:
4167                 return 250000;
4168         case GC_CLOCK_100_133:
4169                 return 133000;
4170         }
4171
4172         /* Shouldn't happen */
4173         return 0;
4174 }
4175
4176 static int i830_get_display_clock_speed(struct drm_device *dev)
4177 {
4178         return 133000;
4179 }
4180
4181 static void
4182 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4183 {
4184         while (*num > DATA_LINK_M_N_MASK ||
4185                *den > DATA_LINK_M_N_MASK) {
4186                 *num >>= 1;
4187                 *den >>= 1;
4188         }
4189 }
4190
4191 static void compute_m_n(unsigned int m, unsigned int n,
4192                         uint32_t *ret_m, uint32_t *ret_n)
4193 {
4194         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4195         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4196         intel_reduce_m_n_ratio(ret_m, ret_n);
4197 }
4198
4199 void
4200 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4201                        int pixel_clock, int link_clock,
4202                        struct intel_link_m_n *m_n)
4203 {
4204         m_n->tu = 64;
4205
4206         compute_m_n(bits_per_pixel * pixel_clock,
4207                     link_clock * nlanes * 8,
4208                     &m_n->gmch_m, &m_n->gmch_n);
4209
4210         compute_m_n(pixel_clock, link_clock,
4211                     &m_n->link_m, &m_n->link_n);
4212 }
4213
4214 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4215 {
4216         if (i915_panel_use_ssc >= 0)
4217                 return i915_panel_use_ssc != 0;
4218         return dev_priv->vbt.lvds_use_ssc
4219                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4220 }
4221
4222 static int vlv_get_refclk(struct drm_crtc *crtc)
4223 {
4224         struct drm_device *dev = crtc->dev;
4225         struct drm_i915_private *dev_priv = dev->dev_private;
4226         int refclk = 27000; /* for DP & HDMI */
4227
4228         return 100000; /* only one validated so far */
4229
4230         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4231                 refclk = 96000;
4232         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4233                 if (intel_panel_use_ssc(dev_priv))
4234                         refclk = 100000;
4235                 else
4236                         refclk = 96000;
4237         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4238                 refclk = 100000;
4239         }
4240
4241         return refclk;
4242 }
4243
4244 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4245 {
4246         struct drm_device *dev = crtc->dev;
4247         struct drm_i915_private *dev_priv = dev->dev_private;
4248         int refclk;
4249
4250         if (IS_VALLEYVIEW(dev)) {
4251                 refclk = vlv_get_refclk(crtc);
4252         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4253             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4254                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4255                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4256                               refclk / 1000);
4257         } else if (!IS_GEN2(dev)) {
4258                 refclk = 96000;
4259         } else {
4260                 refclk = 48000;
4261         }
4262
4263         return refclk;
4264 }
4265
4266 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4267 {
4268         return (1 << dpll->n) << 16 | dpll->m2;
4269 }
4270
4271 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4272 {
4273         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4274 }
4275
4276 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4277                                      intel_clock_t *reduced_clock)
4278 {
4279         struct drm_device *dev = crtc->base.dev;
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281         int pipe = crtc->pipe;
4282         u32 fp, fp2 = 0;
4283
4284         if (IS_PINEVIEW(dev)) {
4285                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4286                 if (reduced_clock)
4287                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4288         } else {
4289                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4290                 if (reduced_clock)
4291                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4292         }
4293
4294         I915_WRITE(FP0(pipe), fp);
4295         crtc->config.dpll_hw_state.fp0 = fp;
4296
4297         crtc->lowfreq_avail = false;
4298         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4299             reduced_clock && i915_powersave) {
4300                 I915_WRITE(FP1(pipe), fp2);
4301                 crtc->config.dpll_hw_state.fp1 = fp2;
4302                 crtc->lowfreq_avail = true;
4303         } else {
4304                 I915_WRITE(FP1(pipe), fp);
4305                 crtc->config.dpll_hw_state.fp1 = fp;
4306         }
4307 }
4308
4309 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4310 {
4311         u32 reg_val;
4312
4313         /*
4314          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4315          * and set it to a reasonable value instead.
4316          */
4317         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4318         reg_val &= 0xffffff00;
4319         reg_val |= 0x00000030;
4320         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4321
4322         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4323         reg_val &= 0x8cffffff;
4324         reg_val = 0x8c000000;
4325         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4326
4327         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4328         reg_val &= 0xffffff00;
4329         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4330
4331         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4332         reg_val &= 0x00ffffff;
4333         reg_val |= 0xb0000000;
4334         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4335 }
4336
4337 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4338                                          struct intel_link_m_n *m_n)
4339 {
4340         struct drm_device *dev = crtc->base.dev;
4341         struct drm_i915_private *dev_priv = dev->dev_private;
4342         int pipe = crtc->pipe;
4343
4344         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4345         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4346         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4347         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4348 }
4349
4350 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4351                                          struct intel_link_m_n *m_n)
4352 {
4353         struct drm_device *dev = crtc->base.dev;
4354         struct drm_i915_private *dev_priv = dev->dev_private;
4355         int pipe = crtc->pipe;
4356         enum transcoder transcoder = crtc->config.cpu_transcoder;
4357
4358         if (INTEL_INFO(dev)->gen >= 5) {
4359                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4360                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4361                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4362                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4363         } else {
4364                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4365                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4366                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4367                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4368         }
4369 }
4370
4371 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4372 {
4373         if (crtc->config.has_pch_encoder)
4374                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4375         else
4376                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4377 }
4378
4379 static void vlv_update_pll(struct intel_crtc *crtc)
4380 {
4381         struct drm_device *dev = crtc->base.dev;
4382         struct drm_i915_private *dev_priv = dev->dev_private;
4383         struct intel_encoder *encoder;
4384         int pipe = crtc->pipe;
4385         u32 dpll, mdiv;
4386         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4387         bool is_hdmi;
4388         u32 coreclk, reg_val, dpll_md;
4389
4390         mutex_lock(&dev_priv->dpio_lock);
4391
4392         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4393
4394         bestn = crtc->config.dpll.n;
4395         bestm1 = crtc->config.dpll.m1;
4396         bestm2 = crtc->config.dpll.m2;
4397         bestp1 = crtc->config.dpll.p1;
4398         bestp2 = crtc->config.dpll.p2;
4399
4400         /* See eDP HDMI DPIO driver vbios notes doc */
4401
4402         /* PLL B needs special handling */
4403         if (pipe)
4404                 vlv_pllb_recal_opamp(dev_priv);
4405
4406         /* Set up Tx target for periodic Rcomp update */
4407         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4408
4409         /* Disable target IRef on PLL */
4410         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4411         reg_val &= 0x00ffffff;
4412         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4413
4414         /* Disable fast lock */
4415         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4416
4417         /* Set idtafcrecal before PLL is enabled */
4418         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4419         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4420         mdiv |= ((bestn << DPIO_N_SHIFT));
4421         mdiv |= (1 << DPIO_K_SHIFT);
4422
4423         /*
4424          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4425          * but we don't support that).
4426          * Note: don't use the DAC post divider as it seems unstable.
4427          */
4428         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4429         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4430
4431         mdiv |= DPIO_ENABLE_CALIBRATION;
4432         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4433
4434         /* Set HBR and RBR LPF coefficients */
4435         if (crtc->config.port_clock == 162000 ||
4436             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4437             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4438                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4439                                  0x005f0021);
4440         else
4441                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4442                                  0x00d0000f);
4443
4444         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4445             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4446                 /* Use SSC source */
4447                 if (!pipe)
4448                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4449                                          0x0df40000);
4450                 else
4451                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4452                                          0x0df70000);
4453         } else { /* HDMI or VGA */
4454                 /* Use bend source */
4455                 if (!pipe)
4456                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4457                                          0x0df70000);
4458                 else
4459                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4460                                          0x0df40000);
4461         }
4462
4463         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4464         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4465         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4466             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4467                 coreclk |= 0x01000000;
4468         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4469
4470         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4471
4472         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4473                 if (encoder->pre_pll_enable)
4474                         encoder->pre_pll_enable(encoder);
4475
4476         /* Enable DPIO clock input */
4477         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4478                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4479         if (pipe)
4480                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4481
4482         dpll |= DPLL_VCO_ENABLE;
4483         crtc->config.dpll_hw_state.dpll = dpll;
4484
4485         I915_WRITE(DPLL(pipe), dpll);
4486         POSTING_READ(DPLL(pipe));
4487         udelay(150);
4488
4489         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4490                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4491
4492         dpll_md = (crtc->config.pixel_multiplier - 1)
4493                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4494         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4495
4496         I915_WRITE(DPLL_MD(pipe), dpll_md);
4497         POSTING_READ(DPLL_MD(pipe));
4498
4499         if (crtc->config.has_dp_encoder)
4500                 intel_dp_set_m_n(crtc);
4501
4502         mutex_unlock(&dev_priv->dpio_lock);
4503 }
4504
4505 static void i9xx_update_pll(struct intel_crtc *crtc,
4506                             intel_clock_t *reduced_clock,
4507                             int num_connectors)
4508 {
4509         struct drm_device *dev = crtc->base.dev;
4510         struct drm_i915_private *dev_priv = dev->dev_private;
4511         u32 dpll;
4512         bool is_sdvo;
4513         struct dpll *clock = &crtc->config.dpll;
4514
4515         i9xx_update_pll_dividers(crtc, reduced_clock);
4516
4517         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4518                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4519
4520         dpll = DPLL_VGA_MODE_DIS;
4521
4522         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4523                 dpll |= DPLLB_MODE_LVDS;
4524         else
4525                 dpll |= DPLLB_MODE_DAC_SERIAL;
4526
4527         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4528                 dpll |= (crtc->config.pixel_multiplier - 1)
4529                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4530         }
4531
4532         if (is_sdvo)
4533                 dpll |= DPLL_DVO_HIGH_SPEED;
4534
4535         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4536                 dpll |= DPLL_DVO_HIGH_SPEED;
4537
4538         /* compute bitmask from p1 value */
4539         if (IS_PINEVIEW(dev))
4540                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4541         else {
4542                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4543                 if (IS_G4X(dev) && reduced_clock)
4544                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4545         }
4546         switch (clock->p2) {
4547         case 5:
4548                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4549                 break;
4550         case 7:
4551                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4552                 break;
4553         case 10:
4554                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4555                 break;
4556         case 14:
4557                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4558                 break;
4559         }
4560         if (INTEL_INFO(dev)->gen >= 4)
4561                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4562
4563         if (crtc->config.sdvo_tv_clock)
4564                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4565         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4566                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4567                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4568         else
4569                 dpll |= PLL_REF_INPUT_DREFCLK;
4570
4571         dpll |= DPLL_VCO_ENABLE;
4572         crtc->config.dpll_hw_state.dpll = dpll;
4573
4574         if (INTEL_INFO(dev)->gen >= 4) {
4575                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4576                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4577                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4578         }
4579
4580         if (crtc->config.has_dp_encoder)
4581                 intel_dp_set_m_n(crtc);
4582 }
4583
4584 static void i8xx_update_pll(struct intel_crtc *crtc,
4585                             intel_clock_t *reduced_clock,
4586                             int num_connectors)
4587 {
4588         struct drm_device *dev = crtc->base.dev;
4589         struct drm_i915_private *dev_priv = dev->dev_private;
4590         u32 dpll;
4591         struct dpll *clock = &crtc->config.dpll;
4592
4593         i9xx_update_pll_dividers(crtc, reduced_clock);
4594
4595         dpll = DPLL_VGA_MODE_DIS;
4596
4597         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4598                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4599         } else {
4600                 if (clock->p1 == 2)
4601                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4602                 else
4603                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4604                 if (clock->p2 == 4)
4605                         dpll |= PLL_P2_DIVIDE_BY_4;
4606         }
4607
4608         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4609                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4610                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4611         else
4612                 dpll |= PLL_REF_INPUT_DREFCLK;
4613
4614         dpll |= DPLL_VCO_ENABLE;
4615         crtc->config.dpll_hw_state.dpll = dpll;
4616 }
4617
4618 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4619 {
4620         struct drm_device *dev = intel_crtc->base.dev;
4621         struct drm_i915_private *dev_priv = dev->dev_private;
4622         enum pipe pipe = intel_crtc->pipe;
4623         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4624         struct drm_display_mode *adjusted_mode =
4625                 &intel_crtc->config.adjusted_mode;
4626         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4627         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4628
4629         /* We need to be careful not to changed the adjusted mode, for otherwise
4630          * the hw state checker will get angry at the mismatch. */
4631         crtc_vtotal = adjusted_mode->crtc_vtotal;
4632         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4633
4634         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4635                 /* the chip adds 2 halflines automatically */
4636                 crtc_vtotal -= 1;
4637                 crtc_vblank_end -= 1;
4638                 vsyncshift = adjusted_mode->crtc_hsync_start
4639                              - adjusted_mode->crtc_htotal / 2;
4640         } else {
4641                 vsyncshift = 0;
4642         }
4643
4644         if (INTEL_INFO(dev)->gen > 3)
4645                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4646
4647         I915_WRITE(HTOTAL(cpu_transcoder),
4648                    (adjusted_mode->crtc_hdisplay - 1) |
4649                    ((adjusted_mode->crtc_htotal - 1) << 16));
4650         I915_WRITE(HBLANK(cpu_transcoder),
4651                    (adjusted_mode->crtc_hblank_start - 1) |
4652                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4653         I915_WRITE(HSYNC(cpu_transcoder),
4654                    (adjusted_mode->crtc_hsync_start - 1) |
4655                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4656
4657         I915_WRITE(VTOTAL(cpu_transcoder),
4658                    (adjusted_mode->crtc_vdisplay - 1) |
4659                    ((crtc_vtotal - 1) << 16));
4660         I915_WRITE(VBLANK(cpu_transcoder),
4661                    (adjusted_mode->crtc_vblank_start - 1) |
4662                    ((crtc_vblank_end - 1) << 16));
4663         I915_WRITE(VSYNC(cpu_transcoder),
4664                    (adjusted_mode->crtc_vsync_start - 1) |
4665                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4666
4667         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4668          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4669          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4670          * bits. */
4671         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4672             (pipe == PIPE_B || pipe == PIPE_C))
4673                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4674
4675         /* pipesrc controls the size that is scaled from, which should
4676          * always be the user's requested size.
4677          */
4678         I915_WRITE(PIPESRC(pipe),
4679                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4680 }
4681
4682 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4683                                    struct intel_crtc_config *pipe_config)
4684 {
4685         struct drm_device *dev = crtc->base.dev;
4686         struct drm_i915_private *dev_priv = dev->dev_private;
4687         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4688         uint32_t tmp;
4689
4690         tmp = I915_READ(HTOTAL(cpu_transcoder));
4691         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4692         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4693         tmp = I915_READ(HBLANK(cpu_transcoder));
4694         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4695         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4696         tmp = I915_READ(HSYNC(cpu_transcoder));
4697         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4698         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4699
4700         tmp = I915_READ(VTOTAL(cpu_transcoder));
4701         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4702         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4703         tmp = I915_READ(VBLANK(cpu_transcoder));
4704         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4705         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4706         tmp = I915_READ(VSYNC(cpu_transcoder));
4707         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4708         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4709
4710         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4711                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4712                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4713                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4714         }
4715
4716         tmp = I915_READ(PIPESRC(crtc->pipe));
4717         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4718         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4719 }
4720
4721 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4722 {
4723         struct drm_device *dev = intel_crtc->base.dev;
4724         struct drm_i915_private *dev_priv = dev->dev_private;
4725         uint32_t pipeconf;
4726
4727         pipeconf = 0;
4728
4729         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4730                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4731                  * core speed.
4732                  *
4733                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4734                  * pipe == 0 check?
4735                  */
4736                 if (intel_crtc->config.requested_mode.clock >
4737                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4738                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4739         }
4740
4741         /* only g4x and later have fancy bpc/dither controls */
4742         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4743                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4744                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4745                         pipeconf |= PIPECONF_DITHER_EN |
4746                                     PIPECONF_DITHER_TYPE_SP;
4747
4748                 switch (intel_crtc->config.pipe_bpp) {
4749                 case 18:
4750                         pipeconf |= PIPECONF_6BPC;
4751                         break;
4752                 case 24:
4753                         pipeconf |= PIPECONF_8BPC;
4754                         break;
4755                 case 30:
4756                         pipeconf |= PIPECONF_10BPC;
4757                         break;
4758                 default:
4759                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4760                         BUG();
4761                 }
4762         }
4763
4764         if (HAS_PIPE_CXSR(dev)) {
4765                 if (intel_crtc->lowfreq_avail) {
4766                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4767                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4768                 } else {
4769                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4770                 }
4771         }
4772
4773         if (!IS_GEN2(dev) &&
4774             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4775                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4776         else
4777                 pipeconf |= PIPECONF_PROGRESSIVE;
4778
4779         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4780                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4781
4782         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4783         POSTING_READ(PIPECONF(intel_crtc->pipe));
4784 }
4785
4786 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4787                               int x, int y,
4788                               struct drm_framebuffer *fb)
4789 {
4790         struct drm_device *dev = crtc->dev;
4791         struct drm_i915_private *dev_priv = dev->dev_private;
4792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4793         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4794         int pipe = intel_crtc->pipe;
4795         int plane = intel_crtc->plane;
4796         int refclk, num_connectors = 0;
4797         intel_clock_t clock, reduced_clock;
4798         u32 dspcntr;
4799         bool ok, has_reduced_clock = false;
4800         bool is_lvds = false;
4801         struct intel_encoder *encoder;
4802         const intel_limit_t *limit;
4803         int ret;
4804
4805         for_each_encoder_on_crtc(dev, crtc, encoder) {
4806                 switch (encoder->type) {
4807                 case INTEL_OUTPUT_LVDS:
4808                         is_lvds = true;
4809                         break;
4810                 }
4811
4812                 num_connectors++;
4813         }
4814
4815         refclk = i9xx_get_refclk(crtc, num_connectors);
4816
4817         /*
4818          * Returns a set of divisors for the desired target clock with the given
4819          * refclk, or FALSE.  The returned values represent the clock equation:
4820          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4821          */
4822         limit = intel_limit(crtc, refclk);
4823         ok = dev_priv->display.find_dpll(limit, crtc,
4824                                          intel_crtc->config.port_clock,
4825                                          refclk, NULL, &clock);
4826         if (!ok && !intel_crtc->config.clock_set) {
4827                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4828                 return -EINVAL;
4829         }
4830
4831         /* Ensure that the cursor is valid for the new mode before changing... */
4832         intel_crtc_update_cursor(crtc, true);
4833
4834         if (is_lvds && dev_priv->lvds_downclock_avail) {
4835                 /*
4836                  * Ensure we match the reduced clock's P to the target clock.
4837                  * If the clocks don't match, we can't switch the display clock
4838                  * by using the FP0/FP1. In such case we will disable the LVDS
4839                  * downclock feature.
4840                 */
4841                 has_reduced_clock =
4842                         dev_priv->display.find_dpll(limit, crtc,
4843                                                     dev_priv->lvds_downclock,
4844                                                     refclk, &clock,
4845                                                     &reduced_clock);
4846         }
4847         /* Compat-code for transition, will disappear. */
4848         if (!intel_crtc->config.clock_set) {
4849                 intel_crtc->config.dpll.n = clock.n;
4850                 intel_crtc->config.dpll.m1 = clock.m1;
4851                 intel_crtc->config.dpll.m2 = clock.m2;
4852                 intel_crtc->config.dpll.p1 = clock.p1;
4853                 intel_crtc->config.dpll.p2 = clock.p2;
4854         }
4855
4856         if (IS_GEN2(dev))
4857                 i8xx_update_pll(intel_crtc,
4858                                 has_reduced_clock ? &reduced_clock : NULL,
4859                                 num_connectors);
4860         else if (IS_VALLEYVIEW(dev))
4861                 vlv_update_pll(intel_crtc);
4862         else
4863                 i9xx_update_pll(intel_crtc,
4864                                 has_reduced_clock ? &reduced_clock : NULL,
4865                                 num_connectors);
4866
4867         /* Set up the display plane register */
4868         dspcntr = DISPPLANE_GAMMA_ENABLE;
4869
4870         if (!IS_VALLEYVIEW(dev)) {
4871                 if (pipe == 0)
4872                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4873                 else
4874                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4875         }
4876
4877         intel_set_pipe_timings(intel_crtc);
4878
4879         /* pipesrc and dspsize control the size that is scaled from,
4880          * which should always be the user's requested size.
4881          */
4882         I915_WRITE(DSPSIZE(plane),
4883                    ((mode->vdisplay - 1) << 16) |
4884                    (mode->hdisplay - 1));
4885         I915_WRITE(DSPPOS(plane), 0);
4886
4887         i9xx_set_pipeconf(intel_crtc);
4888
4889         I915_WRITE(DSPCNTR(plane), dspcntr);
4890         POSTING_READ(DSPCNTR(plane));
4891
4892         ret = intel_pipe_set_base(crtc, x, y, fb);
4893
4894         intel_update_watermarks(dev);
4895
4896         return ret;
4897 }
4898
4899 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4900                                  struct intel_crtc_config *pipe_config)
4901 {
4902         struct drm_device *dev = crtc->base.dev;
4903         struct drm_i915_private *dev_priv = dev->dev_private;
4904         uint32_t tmp;
4905
4906         tmp = I915_READ(PFIT_CONTROL);
4907
4908         if (INTEL_INFO(dev)->gen < 4) {
4909                 if (crtc->pipe != PIPE_B)
4910                         return;
4911
4912                 /* gen2/3 store dither state in pfit control, needs to match */
4913                 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4914         } else {
4915                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4916                         return;
4917         }
4918
4919         if (!(tmp & PFIT_ENABLE))
4920                 return;
4921
4922         pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4923         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4924         if (INTEL_INFO(dev)->gen < 5)
4925                 pipe_config->gmch_pfit.lvds_border_bits =
4926                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4927 }
4928
4929 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4930                                  struct intel_crtc_config *pipe_config)
4931 {
4932         struct drm_device *dev = crtc->base.dev;
4933         struct drm_i915_private *dev_priv = dev->dev_private;
4934         uint32_t tmp;
4935
4936         pipe_config->cpu_transcoder = crtc->pipe;
4937         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4938
4939         tmp = I915_READ(PIPECONF(crtc->pipe));
4940         if (!(tmp & PIPECONF_ENABLE))
4941                 return false;
4942
4943         intel_get_pipe_timings(crtc, pipe_config);
4944
4945         i9xx_get_pfit_config(crtc, pipe_config);
4946
4947         if (INTEL_INFO(dev)->gen >= 4) {
4948                 tmp = I915_READ(DPLL_MD(crtc->pipe));
4949                 pipe_config->pixel_multiplier =
4950                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4951                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4952                 pipe_config->dpll_hw_state.dpll_md = tmp;
4953         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4954                 tmp = I915_READ(DPLL(crtc->pipe));
4955                 pipe_config->pixel_multiplier =
4956                         ((tmp & SDVO_MULTIPLIER_MASK)
4957                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4958         } else {
4959                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4960                  * port and will be fixed up in the encoder->get_config
4961                  * function. */
4962                 pipe_config->pixel_multiplier = 1;
4963         }
4964         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4965         if (!IS_VALLEYVIEW(dev)) {
4966                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
4967                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
4968         }
4969
4970         return true;
4971 }
4972
4973 static void ironlake_init_pch_refclk(struct drm_device *dev)
4974 {
4975         struct drm_i915_private *dev_priv = dev->dev_private;
4976         struct drm_mode_config *mode_config = &dev->mode_config;
4977         struct intel_encoder *encoder;
4978         u32 val, final;
4979         bool has_lvds = false;
4980         bool has_cpu_edp = false;
4981         bool has_panel = false;
4982         bool has_ck505 = false;
4983         bool can_ssc = false;
4984
4985         /* We need to take the global config into account */
4986         list_for_each_entry(encoder, &mode_config->encoder_list,
4987                             base.head) {
4988                 switch (encoder->type) {
4989                 case INTEL_OUTPUT_LVDS:
4990                         has_panel = true;
4991                         has_lvds = true;
4992                         break;
4993                 case INTEL_OUTPUT_EDP:
4994                         has_panel = true;
4995                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
4996                                 has_cpu_edp = true;
4997                         break;
4998                 }
4999         }
5000
5001         if (HAS_PCH_IBX(dev)) {
5002                 has_ck505 = dev_priv->vbt.display_clock_mode;
5003                 can_ssc = has_ck505;
5004         } else {
5005                 has_ck505 = false;
5006                 can_ssc = true;
5007         }
5008
5009         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5010                       has_panel, has_lvds, has_ck505);
5011
5012         /* Ironlake: try to setup display ref clock before DPLL
5013          * enabling. This is only under driver's control after
5014          * PCH B stepping, previous chipset stepping should be
5015          * ignoring this setting.
5016          */
5017         val = I915_READ(PCH_DREF_CONTROL);
5018
5019         /* As we must carefully and slowly disable/enable each source in turn,
5020          * compute the final state we want first and check if we need to
5021          * make any changes at all.
5022          */
5023         final = val;
5024         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5025         if (has_ck505)
5026                 final |= DREF_NONSPREAD_CK505_ENABLE;
5027         else
5028                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5029
5030         final &= ~DREF_SSC_SOURCE_MASK;
5031         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5032         final &= ~DREF_SSC1_ENABLE;
5033
5034         if (has_panel) {
5035                 final |= DREF_SSC_SOURCE_ENABLE;
5036
5037                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5038                         final |= DREF_SSC1_ENABLE;
5039
5040                 if (has_cpu_edp) {
5041                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5042                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5043                         else
5044                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5045                 } else
5046                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5047         } else {
5048                 final |= DREF_SSC_SOURCE_DISABLE;
5049                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5050         }
5051
5052         if (final == val)
5053                 return;
5054
5055         /* Always enable nonspread source */
5056         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5057
5058         if (has_ck505)
5059                 val |= DREF_NONSPREAD_CK505_ENABLE;
5060         else
5061                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5062
5063         if (has_panel) {
5064                 val &= ~DREF_SSC_SOURCE_MASK;
5065                 val |= DREF_SSC_SOURCE_ENABLE;
5066
5067                 /* SSC must be turned on before enabling the CPU output  */
5068                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5069                         DRM_DEBUG_KMS("Using SSC on panel\n");
5070                         val |= DREF_SSC1_ENABLE;
5071                 } else
5072                         val &= ~DREF_SSC1_ENABLE;
5073
5074                 /* Get SSC going before enabling the outputs */
5075                 I915_WRITE(PCH_DREF_CONTROL, val);
5076                 POSTING_READ(PCH_DREF_CONTROL);
5077                 udelay(200);
5078
5079                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5080
5081                 /* Enable CPU source on CPU attached eDP */
5082                 if (has_cpu_edp) {
5083                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5084                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5085                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5086                         }
5087                         else
5088                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5089                 } else
5090                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5091
5092                 I915_WRITE(PCH_DREF_CONTROL, val);
5093                 POSTING_READ(PCH_DREF_CONTROL);
5094                 udelay(200);
5095         } else {
5096                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5097
5098                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5099
5100                 /* Turn off CPU output */
5101                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5102
5103                 I915_WRITE(PCH_DREF_CONTROL, val);
5104                 POSTING_READ(PCH_DREF_CONTROL);
5105                 udelay(200);
5106
5107                 /* Turn off the SSC source */
5108                 val &= ~DREF_SSC_SOURCE_MASK;
5109                 val |= DREF_SSC_SOURCE_DISABLE;
5110
5111                 /* Turn off SSC1 */
5112                 val &= ~DREF_SSC1_ENABLE;
5113
5114                 I915_WRITE(PCH_DREF_CONTROL, val);
5115                 POSTING_READ(PCH_DREF_CONTROL);
5116                 udelay(200);
5117         }
5118
5119         BUG_ON(val != final);
5120 }
5121
5122 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5123 static void lpt_init_pch_refclk(struct drm_device *dev)
5124 {
5125         struct drm_i915_private *dev_priv = dev->dev_private;
5126         struct drm_mode_config *mode_config = &dev->mode_config;
5127         struct intel_encoder *encoder;
5128         bool has_vga = false;
5129         bool is_sdv = false;
5130         u32 tmp;
5131
5132         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5133                 switch (encoder->type) {
5134                 case INTEL_OUTPUT_ANALOG:
5135                         has_vga = true;
5136                         break;
5137                 }
5138         }
5139
5140         if (!has_vga)
5141                 return;
5142
5143         mutex_lock(&dev_priv->dpio_lock);
5144
5145         /* XXX: Rip out SDV support once Haswell ships for real. */
5146         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5147                 is_sdv = true;
5148
5149         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5150         tmp &= ~SBI_SSCCTL_DISABLE;
5151         tmp |= SBI_SSCCTL_PATHALT;
5152         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5153
5154         udelay(24);
5155
5156         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5157         tmp &= ~SBI_SSCCTL_PATHALT;
5158         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5159
5160         if (!is_sdv) {
5161                 tmp = I915_READ(SOUTH_CHICKEN2);
5162                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5163                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5164
5165                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5166                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5167                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5168
5169                 tmp = I915_READ(SOUTH_CHICKEN2);
5170                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5171                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5172
5173                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5174                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5175                                        100))
5176                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5177         }
5178
5179         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5180         tmp &= ~(0xFF << 24);
5181         tmp |= (0x12 << 24);
5182         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5183
5184         if (is_sdv) {
5185                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5186                 tmp |= 0x7FFF;
5187                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5188         }
5189
5190         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5191         tmp |= (1 << 11);
5192         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5193
5194         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5195         tmp |= (1 << 11);
5196         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5197
5198         if (is_sdv) {
5199                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5200                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5201                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5202
5203                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5204                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5205                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5206
5207                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5208                 tmp |= (0x3F << 8);
5209                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5210
5211                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5212                 tmp |= (0x3F << 8);
5213                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5214         }
5215
5216         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5217         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5218         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5219
5220         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5221         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5222         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5223
5224         if (!is_sdv) {
5225                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5226                 tmp &= ~(7 << 13);
5227                 tmp |= (5 << 13);
5228                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5229
5230                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5231                 tmp &= ~(7 << 13);
5232                 tmp |= (5 << 13);
5233                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5234         }
5235
5236         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5237         tmp &= ~0xFF;
5238         tmp |= 0x1C;
5239         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5240
5241         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5242         tmp &= ~0xFF;
5243         tmp |= 0x1C;
5244         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5245
5246         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5247         tmp &= ~(0xFF << 16);
5248         tmp |= (0x1C << 16);
5249         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5250
5251         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5252         tmp &= ~(0xFF << 16);
5253         tmp |= (0x1C << 16);
5254         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5255
5256         if (!is_sdv) {
5257                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5258                 tmp |= (1 << 27);
5259                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5260
5261                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5262                 tmp |= (1 << 27);
5263                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5264
5265                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5266                 tmp &= ~(0xF << 28);
5267                 tmp |= (4 << 28);
5268                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5269
5270                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5271                 tmp &= ~(0xF << 28);
5272                 tmp |= (4 << 28);
5273                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5274         }
5275
5276         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5277         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5278         tmp |= SBI_DBUFF0_ENABLE;
5279         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5280
5281         mutex_unlock(&dev_priv->dpio_lock);
5282 }
5283
5284 /*
5285  * Initialize reference clocks when the driver loads
5286  */
5287 void intel_init_pch_refclk(struct drm_device *dev)
5288 {
5289         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5290                 ironlake_init_pch_refclk(dev);
5291         else if (HAS_PCH_LPT(dev))
5292                 lpt_init_pch_refclk(dev);
5293 }
5294
5295 static int ironlake_get_refclk(struct drm_crtc *crtc)
5296 {
5297         struct drm_device *dev = crtc->dev;
5298         struct drm_i915_private *dev_priv = dev->dev_private;
5299         struct intel_encoder *encoder;
5300         int num_connectors = 0;
5301         bool is_lvds = false;
5302
5303         for_each_encoder_on_crtc(dev, crtc, encoder) {
5304                 switch (encoder->type) {
5305                 case INTEL_OUTPUT_LVDS:
5306                         is_lvds = true;
5307                         break;
5308                 }
5309                 num_connectors++;
5310         }
5311
5312         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5313                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5314                               dev_priv->vbt.lvds_ssc_freq);
5315                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5316         }
5317
5318         return 120000;
5319 }
5320
5321 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5322 {
5323         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5324         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5325         int pipe = intel_crtc->pipe;
5326         uint32_t val;
5327
5328         val = 0;
5329
5330         switch (intel_crtc->config.pipe_bpp) {
5331         case 18:
5332                 val |= PIPECONF_6BPC;
5333                 break;
5334         case 24:
5335                 val |= PIPECONF_8BPC;
5336                 break;
5337         case 30:
5338                 val |= PIPECONF_10BPC;
5339                 break;
5340         case 36:
5341                 val |= PIPECONF_12BPC;
5342                 break;
5343         default:
5344                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5345                 BUG();
5346         }
5347
5348         if (intel_crtc->config.dither)
5349                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5350
5351         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5352                 val |= PIPECONF_INTERLACED_ILK;
5353         else
5354                 val |= PIPECONF_PROGRESSIVE;
5355
5356         if (intel_crtc->config.limited_color_range)
5357                 val |= PIPECONF_COLOR_RANGE_SELECT;
5358
5359         I915_WRITE(PIPECONF(pipe), val);
5360         POSTING_READ(PIPECONF(pipe));
5361 }
5362
5363 /*
5364  * Set up the pipe CSC unit.
5365  *
5366  * Currently only full range RGB to limited range RGB conversion
5367  * is supported, but eventually this should handle various
5368  * RGB<->YCbCr scenarios as well.
5369  */
5370 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5371 {
5372         struct drm_device *dev = crtc->dev;
5373         struct drm_i915_private *dev_priv = dev->dev_private;
5374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375         int pipe = intel_crtc->pipe;
5376         uint16_t coeff = 0x7800; /* 1.0 */
5377
5378         /*
5379          * TODO: Check what kind of values actually come out of the pipe
5380          * with these coeff/postoff values and adjust to get the best
5381          * accuracy. Perhaps we even need to take the bpc value into
5382          * consideration.
5383          */
5384
5385         if (intel_crtc->config.limited_color_range)
5386                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5387
5388         /*
5389          * GY/GU and RY/RU should be the other way around according
5390          * to BSpec, but reality doesn't agree. Just set them up in
5391          * a way that results in the correct picture.
5392          */
5393         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5394         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5395
5396         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5397         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5398
5399         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5400         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5401
5402         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5403         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5404         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5405
5406         if (INTEL_INFO(dev)->gen > 6) {
5407                 uint16_t postoff = 0;
5408
5409                 if (intel_crtc->config.limited_color_range)
5410                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5411
5412                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5413                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5414                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5415
5416                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5417         } else {
5418                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5419
5420                 if (intel_crtc->config.limited_color_range)
5421                         mode |= CSC_BLACK_SCREEN_OFFSET;
5422
5423                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5424         }
5425 }
5426
5427 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5428 {
5429         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5432         uint32_t val;
5433
5434         val = 0;
5435
5436         if (intel_crtc->config.dither)
5437                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5438
5439         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5440                 val |= PIPECONF_INTERLACED_ILK;
5441         else
5442                 val |= PIPECONF_PROGRESSIVE;
5443
5444         I915_WRITE(PIPECONF(cpu_transcoder), val);
5445         POSTING_READ(PIPECONF(cpu_transcoder));
5446
5447         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5448         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5449 }
5450
5451 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5452                                     intel_clock_t *clock,
5453                                     bool *has_reduced_clock,
5454                                     intel_clock_t *reduced_clock)
5455 {
5456         struct drm_device *dev = crtc->dev;
5457         struct drm_i915_private *dev_priv = dev->dev_private;
5458         struct intel_encoder *intel_encoder;
5459         int refclk;
5460         const intel_limit_t *limit;
5461         bool ret, is_lvds = false;
5462
5463         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5464                 switch (intel_encoder->type) {
5465                 case INTEL_OUTPUT_LVDS:
5466                         is_lvds = true;
5467                         break;
5468                 }
5469         }
5470
5471         refclk = ironlake_get_refclk(crtc);
5472
5473         /*
5474          * Returns a set of divisors for the desired target clock with the given
5475          * refclk, or FALSE.  The returned values represent the clock equation:
5476          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5477          */
5478         limit = intel_limit(crtc, refclk);
5479         ret = dev_priv->display.find_dpll(limit, crtc,
5480                                           to_intel_crtc(crtc)->config.port_clock,
5481                                           refclk, NULL, clock);
5482         if (!ret)
5483                 return false;
5484
5485         if (is_lvds && dev_priv->lvds_downclock_avail) {
5486                 /*
5487                  * Ensure we match the reduced clock's P to the target clock.
5488                  * If the clocks don't match, we can't switch the display clock
5489                  * by using the FP0/FP1. In such case we will disable the LVDS
5490                  * downclock feature.
5491                 */
5492                 *has_reduced_clock =
5493                         dev_priv->display.find_dpll(limit, crtc,
5494                                                     dev_priv->lvds_downclock,
5495                                                     refclk, clock,
5496                                                     reduced_clock);
5497         }
5498
5499         return true;
5500 }
5501
5502 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5503 {
5504         struct drm_i915_private *dev_priv = dev->dev_private;
5505         uint32_t temp;
5506
5507         temp = I915_READ(SOUTH_CHICKEN1);
5508         if (temp & FDI_BC_BIFURCATION_SELECT)
5509                 return;
5510
5511         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5512         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5513
5514         temp |= FDI_BC_BIFURCATION_SELECT;
5515         DRM_DEBUG_KMS("enabling fdi C rx\n");
5516         I915_WRITE(SOUTH_CHICKEN1, temp);
5517         POSTING_READ(SOUTH_CHICKEN1);
5518 }
5519
5520 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5521 {
5522         struct drm_device *dev = intel_crtc->base.dev;
5523         struct drm_i915_private *dev_priv = dev->dev_private;
5524
5525         switch (intel_crtc->pipe) {
5526         case PIPE_A:
5527                 break;
5528         case PIPE_B:
5529                 if (intel_crtc->config.fdi_lanes > 2)
5530                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5531                 else
5532                         cpt_enable_fdi_bc_bifurcation(dev);
5533
5534                 break;
5535         case PIPE_C:
5536                 cpt_enable_fdi_bc_bifurcation(dev);
5537
5538                 break;
5539         default:
5540                 BUG();
5541         }
5542 }
5543
5544 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5545 {
5546         /*
5547          * Account for spread spectrum to avoid
5548          * oversubscribing the link. Max center spread
5549          * is 2.5%; use 5% for safety's sake.
5550          */
5551         u32 bps = target_clock * bpp * 21 / 20;
5552         return bps / (link_bw * 8) + 1;
5553 }
5554
5555 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5556 {
5557         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5558 }
5559
5560 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5561                                       u32 *fp,
5562                                       intel_clock_t *reduced_clock, u32 *fp2)
5563 {
5564         struct drm_crtc *crtc = &intel_crtc->base;
5565         struct drm_device *dev = crtc->dev;
5566         struct drm_i915_private *dev_priv = dev->dev_private;
5567         struct intel_encoder *intel_encoder;
5568         uint32_t dpll;
5569         int factor, num_connectors = 0;
5570         bool is_lvds = false, is_sdvo = false;
5571
5572         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5573                 switch (intel_encoder->type) {
5574                 case INTEL_OUTPUT_LVDS:
5575                         is_lvds = true;
5576                         break;
5577                 case INTEL_OUTPUT_SDVO:
5578                 case INTEL_OUTPUT_HDMI:
5579                         is_sdvo = true;
5580                         break;
5581                 }
5582
5583                 num_connectors++;
5584         }
5585
5586         /* Enable autotuning of the PLL clock (if permissible) */
5587         factor = 21;
5588         if (is_lvds) {
5589                 if ((intel_panel_use_ssc(dev_priv) &&
5590                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5591                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5592                         factor = 25;
5593         } else if (intel_crtc->config.sdvo_tv_clock)
5594                 factor = 20;
5595
5596         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5597                 *fp |= FP_CB_TUNE;
5598
5599         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5600                 *fp2 |= FP_CB_TUNE;
5601
5602         dpll = 0;
5603
5604         if (is_lvds)
5605                 dpll |= DPLLB_MODE_LVDS;
5606         else
5607                 dpll |= DPLLB_MODE_DAC_SERIAL;
5608
5609         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5610                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5611
5612         if (is_sdvo)
5613                 dpll |= DPLL_DVO_HIGH_SPEED;
5614         if (intel_crtc->config.has_dp_encoder)
5615                 dpll |= DPLL_DVO_HIGH_SPEED;
5616
5617         /* compute bitmask from p1 value */
5618         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5619         /* also FPA1 */
5620         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5621
5622         switch (intel_crtc->config.dpll.p2) {
5623         case 5:
5624                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5625                 break;
5626         case 7:
5627                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5628                 break;
5629         case 10:
5630                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5631                 break;
5632         case 14:
5633                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5634                 break;
5635         }
5636
5637         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5638                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5639         else
5640                 dpll |= PLL_REF_INPUT_DREFCLK;
5641
5642         return dpll | DPLL_VCO_ENABLE;
5643 }
5644
5645 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5646                                   int x, int y,
5647                                   struct drm_framebuffer *fb)
5648 {
5649         struct drm_device *dev = crtc->dev;
5650         struct drm_i915_private *dev_priv = dev->dev_private;
5651         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5652         int pipe = intel_crtc->pipe;
5653         int plane = intel_crtc->plane;
5654         int num_connectors = 0;
5655         intel_clock_t clock, reduced_clock;
5656         u32 dpll = 0, fp = 0, fp2 = 0;
5657         bool ok, has_reduced_clock = false;
5658         bool is_lvds = false;
5659         struct intel_encoder *encoder;
5660         struct intel_shared_dpll *pll;
5661         int ret;
5662
5663         for_each_encoder_on_crtc(dev, crtc, encoder) {
5664                 switch (encoder->type) {
5665                 case INTEL_OUTPUT_LVDS:
5666                         is_lvds = true;
5667                         break;
5668                 }
5669
5670                 num_connectors++;
5671         }
5672
5673         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5674              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5675
5676         ok = ironlake_compute_clocks(crtc, &clock,
5677                                      &has_reduced_clock, &reduced_clock);
5678         if (!ok && !intel_crtc->config.clock_set) {
5679                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5680                 return -EINVAL;
5681         }
5682         /* Compat-code for transition, will disappear. */
5683         if (!intel_crtc->config.clock_set) {
5684                 intel_crtc->config.dpll.n = clock.n;
5685                 intel_crtc->config.dpll.m1 = clock.m1;
5686                 intel_crtc->config.dpll.m2 = clock.m2;
5687                 intel_crtc->config.dpll.p1 = clock.p1;
5688                 intel_crtc->config.dpll.p2 = clock.p2;
5689         }
5690
5691         /* Ensure that the cursor is valid for the new mode before changing... */
5692         intel_crtc_update_cursor(crtc, true);
5693
5694         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5695         if (intel_crtc->config.has_pch_encoder) {
5696                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5697                 if (has_reduced_clock)
5698                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5699
5700                 dpll = ironlake_compute_dpll(intel_crtc,
5701                                              &fp, &reduced_clock,
5702                                              has_reduced_clock ? &fp2 : NULL);
5703
5704                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5705                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5706                 if (has_reduced_clock)
5707                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5708                 else
5709                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5710
5711                 pll = intel_get_shared_dpll(intel_crtc);
5712                 if (pll == NULL) {
5713                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5714                                          pipe_name(pipe));
5715                         return -EINVAL;
5716                 }
5717         } else
5718                 intel_put_shared_dpll(intel_crtc);
5719
5720         if (intel_crtc->config.has_dp_encoder)
5721                 intel_dp_set_m_n(intel_crtc);
5722
5723         if (is_lvds && has_reduced_clock && i915_powersave)
5724                 intel_crtc->lowfreq_avail = true;
5725         else
5726                 intel_crtc->lowfreq_avail = false;
5727
5728         if (intel_crtc->config.has_pch_encoder) {
5729                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5730
5731         }
5732
5733         intel_set_pipe_timings(intel_crtc);
5734
5735         if (intel_crtc->config.has_pch_encoder) {
5736                 intel_cpu_transcoder_set_m_n(intel_crtc,
5737                                              &intel_crtc->config.fdi_m_n);
5738         }
5739
5740         if (IS_IVYBRIDGE(dev))
5741                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5742
5743         ironlake_set_pipeconf(crtc);
5744
5745         /* Set up the display plane register */
5746         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5747         POSTING_READ(DSPCNTR(plane));
5748
5749         ret = intel_pipe_set_base(crtc, x, y, fb);
5750
5751         intel_update_watermarks(dev);
5752
5753         return ret;
5754 }
5755
5756 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5757                                         struct intel_crtc_config *pipe_config)
5758 {
5759         struct drm_device *dev = crtc->base.dev;
5760         struct drm_i915_private *dev_priv = dev->dev_private;
5761         enum transcoder transcoder = pipe_config->cpu_transcoder;
5762
5763         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5764         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5765         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5766                                         & ~TU_SIZE_MASK;
5767         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5768         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5769                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5770 }
5771
5772 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5773                                      struct intel_crtc_config *pipe_config)
5774 {
5775         struct drm_device *dev = crtc->base.dev;
5776         struct drm_i915_private *dev_priv = dev->dev_private;
5777         uint32_t tmp;
5778
5779         tmp = I915_READ(PF_CTL(crtc->pipe));
5780
5781         if (tmp & PF_ENABLE) {
5782                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5783                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5784
5785                 /* We currently do not free assignements of panel fitters on
5786                  * ivb/hsw (since we don't use the higher upscaling modes which
5787                  * differentiates them) so just WARN about this case for now. */
5788                 if (IS_GEN7(dev)) {
5789                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5790                                 PF_PIPE_SEL_IVB(crtc->pipe));
5791                 }
5792         }
5793 }
5794
5795 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5796                                      struct intel_crtc_config *pipe_config)
5797 {
5798         struct drm_device *dev = crtc->base.dev;
5799         struct drm_i915_private *dev_priv = dev->dev_private;
5800         uint32_t tmp;
5801
5802         pipe_config->cpu_transcoder = crtc->pipe;
5803         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5804
5805         tmp = I915_READ(PIPECONF(crtc->pipe));
5806         if (!(tmp & PIPECONF_ENABLE))
5807                 return false;
5808
5809         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5810                 struct intel_shared_dpll *pll;
5811
5812                 pipe_config->has_pch_encoder = true;
5813
5814                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5815                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5816                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5817
5818                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5819
5820                 /* XXX: Can't properly read out the pch dpll pixel multiplier
5821                  * since we don't have state tracking for pch clocks yet. */
5822                 pipe_config->pixel_multiplier = 1;
5823
5824                 if (HAS_PCH_IBX(dev_priv->dev)) {
5825                         pipe_config->shared_dpll = crtc->pipe;
5826                 } else {
5827                         tmp = I915_READ(PCH_DPLL_SEL);
5828                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5829                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5830                         else
5831                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5832                 }
5833
5834                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5835
5836                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5837                                            &pipe_config->dpll_hw_state));
5838         } else {
5839                 pipe_config->pixel_multiplier = 1;
5840         }
5841
5842         intel_get_pipe_timings(crtc, pipe_config);
5843
5844         ironlake_get_pfit_config(crtc, pipe_config);
5845
5846         return true;
5847 }
5848
5849 static void haswell_modeset_global_resources(struct drm_device *dev)
5850 {
5851         bool enable = false;
5852         struct intel_crtc *crtc;
5853
5854         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5855                 if (!crtc->base.enabled)
5856                         continue;
5857
5858                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5859                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
5860                         enable = true;
5861         }
5862
5863         intel_set_power_well(dev, enable);
5864 }
5865
5866 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5867                                  int x, int y,
5868                                  struct drm_framebuffer *fb)
5869 {
5870         struct drm_device *dev = crtc->dev;
5871         struct drm_i915_private *dev_priv = dev->dev_private;
5872         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5873         int plane = intel_crtc->plane;
5874         int ret;
5875
5876         if (!intel_ddi_pll_mode_set(crtc))
5877                 return -EINVAL;
5878
5879         /* Ensure that the cursor is valid for the new mode before changing... */
5880         intel_crtc_update_cursor(crtc, true);
5881
5882         if (intel_crtc->config.has_dp_encoder)
5883                 intel_dp_set_m_n(intel_crtc);
5884
5885         intel_crtc->lowfreq_avail = false;
5886
5887         intel_set_pipe_timings(intel_crtc);
5888
5889         if (intel_crtc->config.has_pch_encoder) {
5890                 intel_cpu_transcoder_set_m_n(intel_crtc,
5891                                              &intel_crtc->config.fdi_m_n);
5892         }
5893
5894         haswell_set_pipeconf(crtc);
5895
5896         intel_set_pipe_csc(crtc);
5897
5898         /* Set up the display plane register */
5899         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5900         POSTING_READ(DSPCNTR(plane));
5901
5902         ret = intel_pipe_set_base(crtc, x, y, fb);
5903
5904         intel_update_watermarks(dev);
5905
5906         return ret;
5907 }
5908
5909 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5910                                     struct intel_crtc_config *pipe_config)
5911 {
5912         struct drm_device *dev = crtc->base.dev;
5913         struct drm_i915_private *dev_priv = dev->dev_private;
5914         enum intel_display_power_domain pfit_domain;
5915         uint32_t tmp;
5916
5917         pipe_config->cpu_transcoder = crtc->pipe;
5918         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5919
5920         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5921         if (tmp & TRANS_DDI_FUNC_ENABLE) {
5922                 enum pipe trans_edp_pipe;
5923                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5924                 default:
5925                         WARN(1, "unknown pipe linked to edp transcoder\n");
5926                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5927                 case TRANS_DDI_EDP_INPUT_A_ON:
5928                         trans_edp_pipe = PIPE_A;
5929                         break;
5930                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5931                         trans_edp_pipe = PIPE_B;
5932                         break;
5933                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5934                         trans_edp_pipe = PIPE_C;
5935                         break;
5936                 }
5937
5938                 if (trans_edp_pipe == crtc->pipe)
5939                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
5940         }
5941
5942         if (!intel_display_power_enabled(dev,
5943                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
5944                 return false;
5945
5946         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
5947         if (!(tmp & PIPECONF_ENABLE))
5948                 return false;
5949
5950         /*
5951          * Haswell has only FDI/PCH transcoder A. It is which is connected to
5952          * DDI E. So just check whether this pipe is wired to DDI E and whether
5953          * the PCH transcoder is on.
5954          */
5955         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
5956         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5957             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
5958                 pipe_config->has_pch_encoder = true;
5959
5960                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5961                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5962                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5963
5964                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5965         }
5966
5967         intel_get_pipe_timings(crtc, pipe_config);
5968
5969         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5970         if (intel_display_power_enabled(dev, pfit_domain))
5971                 ironlake_get_pfit_config(crtc, pipe_config);
5972
5973         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5974                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
5975
5976         pipe_config->pixel_multiplier = 1;
5977
5978         return true;
5979 }
5980
5981 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5982                                int x, int y,
5983                                struct drm_framebuffer *fb)
5984 {
5985         struct drm_device *dev = crtc->dev;
5986         struct drm_i915_private *dev_priv = dev->dev_private;
5987         struct drm_encoder_helper_funcs *encoder_funcs;
5988         struct intel_encoder *encoder;
5989         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5990         struct drm_display_mode *adjusted_mode =
5991                 &intel_crtc->config.adjusted_mode;
5992         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5993         int pipe = intel_crtc->pipe;
5994         int ret;
5995
5996         drm_vblank_pre_modeset(dev, pipe);
5997
5998         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5999
6000         drm_vblank_post_modeset(dev, pipe);
6001
6002         if (ret != 0)
6003                 return ret;
6004
6005         for_each_encoder_on_crtc(dev, crtc, encoder) {
6006                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6007                         encoder->base.base.id,
6008                         drm_get_encoder_name(&encoder->base),
6009                         mode->base.id, mode->name);
6010                 if (encoder->mode_set) {
6011                         encoder->mode_set(encoder);
6012                 } else {
6013                         encoder_funcs = encoder->base.helper_private;
6014                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6015                 }
6016         }
6017
6018         return 0;
6019 }
6020
6021 static bool intel_eld_uptodate(struct drm_connector *connector,
6022                                int reg_eldv, uint32_t bits_eldv,
6023                                int reg_elda, uint32_t bits_elda,
6024                                int reg_edid)
6025 {
6026         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6027         uint8_t *eld = connector->eld;
6028         uint32_t i;
6029
6030         i = I915_READ(reg_eldv);
6031         i &= bits_eldv;
6032
6033         if (!eld[0])
6034                 return !i;
6035
6036         if (!i)
6037                 return false;
6038
6039         i = I915_READ(reg_elda);
6040         i &= ~bits_elda;
6041         I915_WRITE(reg_elda, i);
6042
6043         for (i = 0; i < eld[2]; i++)
6044                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6045                         return false;
6046
6047         return true;
6048 }
6049
6050 static void g4x_write_eld(struct drm_connector *connector,
6051                           struct drm_crtc *crtc)
6052 {
6053         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6054         uint8_t *eld = connector->eld;
6055         uint32_t eldv;
6056         uint32_t len;
6057         uint32_t i;
6058
6059         i = I915_READ(G4X_AUD_VID_DID);
6060
6061         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6062                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6063         else
6064                 eldv = G4X_ELDV_DEVCTG;
6065
6066         if (intel_eld_uptodate(connector,
6067                                G4X_AUD_CNTL_ST, eldv,
6068                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6069                                G4X_HDMIW_HDMIEDID))
6070                 return;
6071
6072         i = I915_READ(G4X_AUD_CNTL_ST);
6073         i &= ~(eldv | G4X_ELD_ADDR);
6074         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6075         I915_WRITE(G4X_AUD_CNTL_ST, i);
6076
6077         if (!eld[0])
6078                 return;
6079
6080         len = min_t(uint8_t, eld[2], len);
6081         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6082         for (i = 0; i < len; i++)
6083                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6084
6085         i = I915_READ(G4X_AUD_CNTL_ST);
6086         i |= eldv;
6087         I915_WRITE(G4X_AUD_CNTL_ST, i);
6088 }
6089
6090 static void haswell_write_eld(struct drm_connector *connector,
6091                                      struct drm_crtc *crtc)
6092 {
6093         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6094         uint8_t *eld = connector->eld;
6095         struct drm_device *dev = crtc->dev;
6096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6097         uint32_t eldv;
6098         uint32_t i;
6099         int len;
6100         int pipe = to_intel_crtc(crtc)->pipe;
6101         int tmp;
6102
6103         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6104         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6105         int aud_config = HSW_AUD_CFG(pipe);
6106         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6107
6108
6109         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6110
6111         /* Audio output enable */
6112         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6113         tmp = I915_READ(aud_cntrl_st2);
6114         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6115         I915_WRITE(aud_cntrl_st2, tmp);
6116
6117         /* Wait for 1 vertical blank */
6118         intel_wait_for_vblank(dev, pipe);
6119
6120         /* Set ELD valid state */
6121         tmp = I915_READ(aud_cntrl_st2);
6122         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6123         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6124         I915_WRITE(aud_cntrl_st2, tmp);
6125         tmp = I915_READ(aud_cntrl_st2);
6126         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6127
6128         /* Enable HDMI mode */
6129         tmp = I915_READ(aud_config);
6130         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6131         /* clear N_programing_enable and N_value_index */
6132         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6133         I915_WRITE(aud_config, tmp);
6134
6135         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6136
6137         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6138         intel_crtc->eld_vld = true;
6139
6140         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6141                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6142                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6143                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6144         } else
6145                 I915_WRITE(aud_config, 0);
6146
6147         if (intel_eld_uptodate(connector,
6148                                aud_cntrl_st2, eldv,
6149                                aud_cntl_st, IBX_ELD_ADDRESS,
6150                                hdmiw_hdmiedid))
6151                 return;
6152
6153         i = I915_READ(aud_cntrl_st2);
6154         i &= ~eldv;
6155         I915_WRITE(aud_cntrl_st2, i);
6156
6157         if (!eld[0])
6158                 return;
6159
6160         i = I915_READ(aud_cntl_st);
6161         i &= ~IBX_ELD_ADDRESS;
6162         I915_WRITE(aud_cntl_st, i);
6163         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6164         DRM_DEBUG_DRIVER("port num:%d\n", i);
6165
6166         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6167         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6168         for (i = 0; i < len; i++)
6169                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6170
6171         i = I915_READ(aud_cntrl_st2);
6172         i |= eldv;
6173         I915_WRITE(aud_cntrl_st2, i);
6174
6175 }
6176
6177 static void ironlake_write_eld(struct drm_connector *connector,
6178                                      struct drm_crtc *crtc)
6179 {
6180         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6181         uint8_t *eld = connector->eld;
6182         uint32_t eldv;
6183         uint32_t i;
6184         int len;
6185         int hdmiw_hdmiedid;
6186         int aud_config;
6187         int aud_cntl_st;
6188         int aud_cntrl_st2;
6189         int pipe = to_intel_crtc(crtc)->pipe;
6190
6191         if (HAS_PCH_IBX(connector->dev)) {
6192                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6193                 aud_config = IBX_AUD_CFG(pipe);
6194                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6195                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6196         } else {
6197                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6198                 aud_config = CPT_AUD_CFG(pipe);
6199                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6200                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6201         }
6202
6203         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6204
6205         i = I915_READ(aud_cntl_st);
6206         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6207         if (!i) {
6208                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6209                 /* operate blindly on all ports */
6210                 eldv = IBX_ELD_VALIDB;
6211                 eldv |= IBX_ELD_VALIDB << 4;
6212                 eldv |= IBX_ELD_VALIDB << 8;
6213         } else {
6214                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6215                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6216         }
6217
6218         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6219                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6220                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6221                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6222         } else
6223                 I915_WRITE(aud_config, 0);
6224
6225         if (intel_eld_uptodate(connector,
6226                                aud_cntrl_st2, eldv,
6227                                aud_cntl_st, IBX_ELD_ADDRESS,
6228                                hdmiw_hdmiedid))
6229                 return;
6230
6231         i = I915_READ(aud_cntrl_st2);
6232         i &= ~eldv;
6233         I915_WRITE(aud_cntrl_st2, i);
6234
6235         if (!eld[0])
6236                 return;
6237
6238         i = I915_READ(aud_cntl_st);
6239         i &= ~IBX_ELD_ADDRESS;
6240         I915_WRITE(aud_cntl_st, i);
6241
6242         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6243         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6244         for (i = 0; i < len; i++)
6245                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6246
6247         i = I915_READ(aud_cntrl_st2);
6248         i |= eldv;
6249         I915_WRITE(aud_cntrl_st2, i);
6250 }
6251
6252 void intel_write_eld(struct drm_encoder *encoder,
6253                      struct drm_display_mode *mode)
6254 {
6255         struct drm_crtc *crtc = encoder->crtc;
6256         struct drm_connector *connector;
6257         struct drm_device *dev = encoder->dev;
6258         struct drm_i915_private *dev_priv = dev->dev_private;
6259
6260         connector = drm_select_eld(encoder, mode);
6261         if (!connector)
6262                 return;
6263
6264         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6265                          connector->base.id,
6266                          drm_get_connector_name(connector),
6267                          connector->encoder->base.id,
6268                          drm_get_encoder_name(connector->encoder));
6269
6270         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6271
6272         if (dev_priv->display.write_eld)
6273                 dev_priv->display.write_eld(connector, crtc);
6274 }
6275
6276 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6277 void intel_crtc_load_lut(struct drm_crtc *crtc)
6278 {
6279         struct drm_device *dev = crtc->dev;
6280         struct drm_i915_private *dev_priv = dev->dev_private;
6281         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6282         enum pipe pipe = intel_crtc->pipe;
6283         int palreg = PALETTE(pipe);
6284         int i;
6285         bool reenable_ips = false;
6286
6287         /* The clocks have to be on to load the palette. */
6288         if (!crtc->enabled || !intel_crtc->active)
6289                 return;
6290
6291         if (!HAS_PCH_SPLIT(dev_priv->dev))
6292                 assert_pll_enabled(dev_priv, pipe);
6293
6294         /* use legacy palette for Ironlake */
6295         if (HAS_PCH_SPLIT(dev))
6296                 palreg = LGC_PALETTE(pipe);
6297
6298         /* Workaround : Do not read or write the pipe palette/gamma data while
6299          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6300          */
6301         if (intel_crtc->config.ips_enabled &&
6302             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6303              GAMMA_MODE_MODE_SPLIT)) {
6304                 hsw_disable_ips(intel_crtc);
6305                 reenable_ips = true;
6306         }
6307
6308         for (i = 0; i < 256; i++) {
6309                 I915_WRITE(palreg + 4 * i,
6310                            (intel_crtc->lut_r[i] << 16) |
6311                            (intel_crtc->lut_g[i] << 8) |
6312                            intel_crtc->lut_b[i]);
6313         }
6314
6315         if (reenable_ips)
6316                 hsw_enable_ips(intel_crtc);
6317 }
6318
6319 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6320 {
6321         struct drm_device *dev = crtc->dev;
6322         struct drm_i915_private *dev_priv = dev->dev_private;
6323         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6324         bool visible = base != 0;
6325         u32 cntl;
6326
6327         if (intel_crtc->cursor_visible == visible)
6328                 return;
6329
6330         cntl = I915_READ(_CURACNTR);
6331         if (visible) {
6332                 /* On these chipsets we can only modify the base whilst
6333                  * the cursor is disabled.
6334                  */
6335                 I915_WRITE(_CURABASE, base);
6336
6337                 cntl &= ~(CURSOR_FORMAT_MASK);
6338                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6339                 cntl |= CURSOR_ENABLE |
6340                         CURSOR_GAMMA_ENABLE |
6341                         CURSOR_FORMAT_ARGB;
6342         } else
6343                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6344         I915_WRITE(_CURACNTR, cntl);
6345
6346         intel_crtc->cursor_visible = visible;
6347 }
6348
6349 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6350 {
6351         struct drm_device *dev = crtc->dev;
6352         struct drm_i915_private *dev_priv = dev->dev_private;
6353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6354         int pipe = intel_crtc->pipe;
6355         bool visible = base != 0;
6356
6357         if (intel_crtc->cursor_visible != visible) {
6358                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6359                 if (base) {
6360                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6361                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6362                         cntl |= pipe << 28; /* Connect to correct pipe */
6363                 } else {
6364                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6365                         cntl |= CURSOR_MODE_DISABLE;
6366                 }
6367                 I915_WRITE(CURCNTR(pipe), cntl);
6368
6369                 intel_crtc->cursor_visible = visible;
6370         }
6371         /* and commit changes on next vblank */
6372         I915_WRITE(CURBASE(pipe), base);
6373 }
6374
6375 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6376 {
6377         struct drm_device *dev = crtc->dev;
6378         struct drm_i915_private *dev_priv = dev->dev_private;
6379         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6380         int pipe = intel_crtc->pipe;
6381         bool visible = base != 0;
6382
6383         if (intel_crtc->cursor_visible != visible) {
6384                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6385                 if (base) {
6386                         cntl &= ~CURSOR_MODE;
6387                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6388                 } else {
6389                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6390                         cntl |= CURSOR_MODE_DISABLE;
6391                 }
6392                 if (IS_HASWELL(dev))
6393                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6394                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6395
6396                 intel_crtc->cursor_visible = visible;
6397         }
6398         /* and commit changes on next vblank */
6399         I915_WRITE(CURBASE_IVB(pipe), base);
6400 }
6401
6402 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6403 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6404                                      bool on)
6405 {
6406         struct drm_device *dev = crtc->dev;
6407         struct drm_i915_private *dev_priv = dev->dev_private;
6408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6409         int pipe = intel_crtc->pipe;
6410         int x = intel_crtc->cursor_x;
6411         int y = intel_crtc->cursor_y;
6412         u32 base, pos;
6413         bool visible;
6414
6415         pos = 0;
6416
6417         if (on && crtc->enabled && crtc->fb) {
6418                 base = intel_crtc->cursor_addr;
6419                 if (x > (int) crtc->fb->width)
6420                         base = 0;
6421
6422                 if (y > (int) crtc->fb->height)
6423                         base = 0;
6424         } else
6425                 base = 0;
6426
6427         if (x < 0) {
6428                 if (x + intel_crtc->cursor_width < 0)
6429                         base = 0;
6430
6431                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6432                 x = -x;
6433         }
6434         pos |= x << CURSOR_X_SHIFT;
6435
6436         if (y < 0) {
6437                 if (y + intel_crtc->cursor_height < 0)
6438                         base = 0;
6439
6440                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6441                 y = -y;
6442         }
6443         pos |= y << CURSOR_Y_SHIFT;
6444
6445         visible = base != 0;
6446         if (!visible && !intel_crtc->cursor_visible)
6447                 return;
6448
6449         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6450                 I915_WRITE(CURPOS_IVB(pipe), pos);
6451                 ivb_update_cursor(crtc, base);
6452         } else {
6453                 I915_WRITE(CURPOS(pipe), pos);
6454                 if (IS_845G(dev) || IS_I865G(dev))
6455                         i845_update_cursor(crtc, base);
6456                 else
6457                         i9xx_update_cursor(crtc, base);
6458         }
6459 }
6460
6461 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6462                                  struct drm_file *file,
6463                                  uint32_t handle,
6464                                  uint32_t width, uint32_t height)
6465 {
6466         struct drm_device *dev = crtc->dev;
6467         struct drm_i915_private *dev_priv = dev->dev_private;
6468         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6469         struct drm_i915_gem_object *obj;
6470         uint32_t addr;
6471         int ret;
6472
6473         /* if we want to turn off the cursor ignore width and height */
6474         if (!handle) {
6475                 DRM_DEBUG_KMS("cursor off\n");
6476                 addr = 0;
6477                 obj = NULL;
6478                 mutex_lock(&dev->struct_mutex);
6479                 goto finish;
6480         }
6481
6482         /* Currently we only support 64x64 cursors */
6483         if (width != 64 || height != 64) {
6484                 DRM_ERROR("we currently only support 64x64 cursors\n");
6485                 return -EINVAL;
6486         }
6487
6488         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6489         if (&obj->base == NULL)
6490                 return -ENOENT;
6491
6492         if (obj->base.size < width * height * 4) {
6493                 DRM_ERROR("buffer is to small\n");
6494                 ret = -ENOMEM;
6495                 goto fail;
6496         }
6497
6498         /* we only need to pin inside GTT if cursor is non-phy */
6499         mutex_lock(&dev->struct_mutex);
6500         if (!dev_priv->info->cursor_needs_physical) {
6501                 unsigned alignment;
6502
6503                 if (obj->tiling_mode) {
6504                         DRM_ERROR("cursor cannot be tiled\n");
6505                         ret = -EINVAL;
6506                         goto fail_locked;
6507                 }
6508
6509                 /* Note that the w/a also requires 2 PTE of padding following
6510                  * the bo. We currently fill all unused PTE with the shadow
6511                  * page and so we should always have valid PTE following the
6512                  * cursor preventing the VT-d warning.
6513                  */
6514                 alignment = 0;
6515                 if (need_vtd_wa(dev))
6516                         alignment = 64*1024;
6517
6518                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6519                 if (ret) {
6520                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6521                         goto fail_locked;
6522                 }
6523
6524                 ret = i915_gem_object_put_fence(obj);
6525                 if (ret) {
6526                         DRM_ERROR("failed to release fence for cursor");
6527                         goto fail_unpin;
6528                 }
6529
6530                 addr = obj->gtt_offset;
6531         } else {
6532                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6533                 ret = i915_gem_attach_phys_object(dev, obj,
6534                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6535                                                   align);
6536                 if (ret) {
6537                         DRM_ERROR("failed to attach phys object\n");
6538                         goto fail_locked;
6539                 }
6540                 addr = obj->phys_obj->handle->busaddr;
6541         }
6542
6543         if (IS_GEN2(dev))
6544                 I915_WRITE(CURSIZE, (height << 12) | width);
6545
6546  finish:
6547         if (intel_crtc->cursor_bo) {
6548                 if (dev_priv->info->cursor_needs_physical) {
6549                         if (intel_crtc->cursor_bo != obj)
6550                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6551                 } else
6552                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6553                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6554         }
6555
6556         mutex_unlock(&dev->struct_mutex);
6557
6558         intel_crtc->cursor_addr = addr;
6559         intel_crtc->cursor_bo = obj;
6560         intel_crtc->cursor_width = width;
6561         intel_crtc->cursor_height = height;
6562
6563         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6564
6565         return 0;
6566 fail_unpin:
6567         i915_gem_object_unpin(obj);
6568 fail_locked:
6569         mutex_unlock(&dev->struct_mutex);
6570 fail:
6571         drm_gem_object_unreference_unlocked(&obj->base);
6572         return ret;
6573 }
6574
6575 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6576 {
6577         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6578
6579         intel_crtc->cursor_x = x;
6580         intel_crtc->cursor_y = y;
6581
6582         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6583
6584         return 0;
6585 }
6586
6587 /** Sets the color ramps on behalf of RandR */
6588 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6589                                  u16 blue, int regno)
6590 {
6591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6592
6593         intel_crtc->lut_r[regno] = red >> 8;
6594         intel_crtc->lut_g[regno] = green >> 8;
6595         intel_crtc->lut_b[regno] = blue >> 8;
6596 }
6597
6598 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6599                              u16 *blue, int regno)
6600 {
6601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602
6603         *red = intel_crtc->lut_r[regno] << 8;
6604         *green = intel_crtc->lut_g[regno] << 8;
6605         *blue = intel_crtc->lut_b[regno] << 8;
6606 }
6607
6608 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6609                                  u16 *blue, uint32_t start, uint32_t size)
6610 {
6611         int end = (start + size > 256) ? 256 : start + size, i;
6612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6613
6614         for (i = start; i < end; i++) {
6615                 intel_crtc->lut_r[i] = red[i] >> 8;
6616                 intel_crtc->lut_g[i] = green[i] >> 8;
6617                 intel_crtc->lut_b[i] = blue[i] >> 8;
6618         }
6619
6620         intel_crtc_load_lut(crtc);
6621 }
6622
6623 /* VESA 640x480x72Hz mode to set on the pipe */
6624 static struct drm_display_mode load_detect_mode = {
6625         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6626                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6627 };
6628
6629 static struct drm_framebuffer *
6630 intel_framebuffer_create(struct drm_device *dev,
6631                          struct drm_mode_fb_cmd2 *mode_cmd,
6632                          struct drm_i915_gem_object *obj)
6633 {
6634         struct intel_framebuffer *intel_fb;
6635         int ret;
6636
6637         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6638         if (!intel_fb) {
6639                 drm_gem_object_unreference_unlocked(&obj->base);
6640                 return ERR_PTR(-ENOMEM);
6641         }
6642
6643         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6644         if (ret) {
6645                 drm_gem_object_unreference_unlocked(&obj->base);
6646                 kfree(intel_fb);
6647                 return ERR_PTR(ret);
6648         }
6649
6650         return &intel_fb->base;
6651 }
6652
6653 static u32
6654 intel_framebuffer_pitch_for_width(int width, int bpp)
6655 {
6656         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6657         return ALIGN(pitch, 64);
6658 }
6659
6660 static u32
6661 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6662 {
6663         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6664         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6665 }
6666
6667 static struct drm_framebuffer *
6668 intel_framebuffer_create_for_mode(struct drm_device *dev,
6669                                   struct drm_display_mode *mode,
6670                                   int depth, int bpp)
6671 {
6672         struct drm_i915_gem_object *obj;
6673         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6674
6675         obj = i915_gem_alloc_object(dev,
6676                                     intel_framebuffer_size_for_mode(mode, bpp));
6677         if (obj == NULL)
6678                 return ERR_PTR(-ENOMEM);
6679
6680         mode_cmd.width = mode->hdisplay;
6681         mode_cmd.height = mode->vdisplay;
6682         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6683                                                                 bpp);
6684         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6685
6686         return intel_framebuffer_create(dev, &mode_cmd, obj);
6687 }
6688
6689 static struct drm_framebuffer *
6690 mode_fits_in_fbdev(struct drm_device *dev,
6691                    struct drm_display_mode *mode)
6692 {
6693         struct drm_i915_private *dev_priv = dev->dev_private;
6694         struct drm_i915_gem_object *obj;
6695         struct drm_framebuffer *fb;
6696
6697         if (dev_priv->fbdev == NULL)
6698                 return NULL;
6699
6700         obj = dev_priv->fbdev->ifb.obj;
6701         if (obj == NULL)
6702                 return NULL;
6703
6704         fb = &dev_priv->fbdev->ifb.base;
6705         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6706                                                                fb->bits_per_pixel))
6707                 return NULL;
6708
6709         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6710                 return NULL;
6711
6712         return fb;
6713 }
6714
6715 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6716                                 struct drm_display_mode *mode,
6717                                 struct intel_load_detect_pipe *old)
6718 {
6719         struct intel_crtc *intel_crtc;
6720         struct intel_encoder *intel_encoder =
6721                 intel_attached_encoder(connector);
6722         struct drm_crtc *possible_crtc;
6723         struct drm_encoder *encoder = &intel_encoder->base;
6724         struct drm_crtc *crtc = NULL;
6725         struct drm_device *dev = encoder->dev;
6726         struct drm_framebuffer *fb;
6727         int i = -1;
6728
6729         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6730                       connector->base.id, drm_get_connector_name(connector),
6731                       encoder->base.id, drm_get_encoder_name(encoder));
6732
6733         /*
6734          * Algorithm gets a little messy:
6735          *
6736          *   - if the connector already has an assigned crtc, use it (but make
6737          *     sure it's on first)
6738          *
6739          *   - try to find the first unused crtc that can drive this connector,
6740          *     and use that if we find one
6741          */
6742
6743         /* See if we already have a CRTC for this connector */
6744         if (encoder->crtc) {
6745                 crtc = encoder->crtc;
6746
6747                 mutex_lock(&crtc->mutex);
6748
6749                 old->dpms_mode = connector->dpms;
6750                 old->load_detect_temp = false;
6751
6752                 /* Make sure the crtc and connector are running */
6753                 if (connector->dpms != DRM_MODE_DPMS_ON)
6754                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6755
6756                 return true;
6757         }
6758
6759         /* Find an unused one (if possible) */
6760         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6761                 i++;
6762                 if (!(encoder->possible_crtcs & (1 << i)))
6763                         continue;
6764                 if (!possible_crtc->enabled) {
6765                         crtc = possible_crtc;
6766                         break;
6767                 }
6768         }
6769
6770         /*
6771          * If we didn't find an unused CRTC, don't use any.
6772          */
6773         if (!crtc) {
6774                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6775                 return false;
6776         }
6777
6778         mutex_lock(&crtc->mutex);
6779         intel_encoder->new_crtc = to_intel_crtc(crtc);
6780         to_intel_connector(connector)->new_encoder = intel_encoder;
6781
6782         intel_crtc = to_intel_crtc(crtc);
6783         old->dpms_mode = connector->dpms;
6784         old->load_detect_temp = true;
6785         old->release_fb = NULL;
6786
6787         if (!mode)
6788                 mode = &load_detect_mode;
6789
6790         /* We need a framebuffer large enough to accommodate all accesses
6791          * that the plane may generate whilst we perform load detection.
6792          * We can not rely on the fbcon either being present (we get called
6793          * during its initialisation to detect all boot displays, or it may
6794          * not even exist) or that it is large enough to satisfy the
6795          * requested mode.
6796          */
6797         fb = mode_fits_in_fbdev(dev, mode);
6798         if (fb == NULL) {
6799                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6800                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6801                 old->release_fb = fb;
6802         } else
6803                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6804         if (IS_ERR(fb)) {
6805                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6806                 mutex_unlock(&crtc->mutex);
6807                 return false;
6808         }
6809
6810         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6811                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6812                 if (old->release_fb)
6813                         old->release_fb->funcs->destroy(old->release_fb);
6814                 mutex_unlock(&crtc->mutex);
6815                 return false;
6816         }
6817
6818         /* let the connector get through one full cycle before testing */
6819         intel_wait_for_vblank(dev, intel_crtc->pipe);
6820         return true;
6821 }
6822
6823 void intel_release_load_detect_pipe(struct drm_connector *connector,
6824                                     struct intel_load_detect_pipe *old)
6825 {
6826         struct intel_encoder *intel_encoder =
6827                 intel_attached_encoder(connector);
6828         struct drm_encoder *encoder = &intel_encoder->base;
6829         struct drm_crtc *crtc = encoder->crtc;
6830
6831         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6832                       connector->base.id, drm_get_connector_name(connector),
6833                       encoder->base.id, drm_get_encoder_name(encoder));
6834
6835         if (old->load_detect_temp) {
6836                 to_intel_connector(connector)->new_encoder = NULL;
6837                 intel_encoder->new_crtc = NULL;
6838                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6839
6840                 if (old->release_fb) {
6841                         drm_framebuffer_unregister_private(old->release_fb);
6842                         drm_framebuffer_unreference(old->release_fb);
6843                 }
6844
6845                 mutex_unlock(&crtc->mutex);
6846                 return;
6847         }
6848
6849         /* Switch crtc and encoder back off if necessary */
6850         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6851                 connector->funcs->dpms(connector, old->dpms_mode);
6852
6853         mutex_unlock(&crtc->mutex);
6854 }
6855
6856 /* Returns the clock of the currently programmed mode of the given pipe. */
6857 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6858 {
6859         struct drm_i915_private *dev_priv = dev->dev_private;
6860         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6861         int pipe = intel_crtc->pipe;
6862         u32 dpll = I915_READ(DPLL(pipe));
6863         u32 fp;
6864         intel_clock_t clock;
6865
6866         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6867                 fp = I915_READ(FP0(pipe));
6868         else
6869                 fp = I915_READ(FP1(pipe));
6870
6871         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6872         if (IS_PINEVIEW(dev)) {
6873                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6874                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6875         } else {
6876                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6877                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6878         }
6879
6880         if (!IS_GEN2(dev)) {
6881                 if (IS_PINEVIEW(dev))
6882                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6883                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6884                 else
6885                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6886                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6887
6888                 switch (dpll & DPLL_MODE_MASK) {
6889                 case DPLLB_MODE_DAC_SERIAL:
6890                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6891                                 5 : 10;
6892                         break;
6893                 case DPLLB_MODE_LVDS:
6894                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6895                                 7 : 14;
6896                         break;
6897                 default:
6898                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6899                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6900                         return 0;
6901                 }
6902
6903                 if (IS_PINEVIEW(dev))
6904                         pineview_clock(96000, &clock);
6905                 else
6906                         i9xx_clock(96000, &clock);
6907         } else {
6908                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6909
6910                 if (is_lvds) {
6911                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6912                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6913                         clock.p2 = 14;
6914
6915                         if ((dpll & PLL_REF_INPUT_MASK) ==
6916                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6917                                 /* XXX: might not be 66MHz */
6918                                 i9xx_clock(66000, &clock);
6919                         } else
6920                                 i9xx_clock(48000, &clock);
6921                 } else {
6922                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6923                                 clock.p1 = 2;
6924                         else {
6925                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6926                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6927                         }
6928                         if (dpll & PLL_P2_DIVIDE_BY_4)
6929                                 clock.p2 = 4;
6930                         else
6931                                 clock.p2 = 2;
6932
6933                         i9xx_clock(48000, &clock);
6934                 }
6935         }
6936
6937         /* XXX: It would be nice to validate the clocks, but we can't reuse
6938          * i830PllIsValid() because it relies on the xf86_config connector
6939          * configuration being accurate, which it isn't necessarily.
6940          */
6941
6942         return clock.dot;
6943 }
6944
6945 /** Returns the currently programmed mode of the given pipe. */
6946 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6947                                              struct drm_crtc *crtc)
6948 {
6949         struct drm_i915_private *dev_priv = dev->dev_private;
6950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6951         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6952         struct drm_display_mode *mode;
6953         int htot = I915_READ(HTOTAL(cpu_transcoder));
6954         int hsync = I915_READ(HSYNC(cpu_transcoder));
6955         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6956         int vsync = I915_READ(VSYNC(cpu_transcoder));
6957
6958         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6959         if (!mode)
6960                 return NULL;
6961
6962         mode->clock = intel_crtc_clock_get(dev, crtc);
6963         mode->hdisplay = (htot & 0xffff) + 1;
6964         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6965         mode->hsync_start = (hsync & 0xffff) + 1;
6966         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6967         mode->vdisplay = (vtot & 0xffff) + 1;
6968         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6969         mode->vsync_start = (vsync & 0xffff) + 1;
6970         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6971
6972         drm_mode_set_name(mode);
6973
6974         return mode;
6975 }
6976
6977 static void intel_increase_pllclock(struct drm_crtc *crtc)
6978 {
6979         struct drm_device *dev = crtc->dev;
6980         drm_i915_private_t *dev_priv = dev->dev_private;
6981         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6982         int pipe = intel_crtc->pipe;
6983         int dpll_reg = DPLL(pipe);
6984         int dpll;
6985
6986         if (HAS_PCH_SPLIT(dev))
6987                 return;
6988
6989         if (!dev_priv->lvds_downclock_avail)
6990                 return;
6991
6992         dpll = I915_READ(dpll_reg);
6993         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6994                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6995
6996                 assert_panel_unlocked(dev_priv, pipe);
6997
6998                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6999                 I915_WRITE(dpll_reg, dpll);
7000                 intel_wait_for_vblank(dev, pipe);
7001
7002                 dpll = I915_READ(dpll_reg);
7003                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7004                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7005         }
7006 }
7007
7008 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7009 {
7010         struct drm_device *dev = crtc->dev;
7011         drm_i915_private_t *dev_priv = dev->dev_private;
7012         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7013
7014         if (HAS_PCH_SPLIT(dev))
7015                 return;
7016
7017         if (!dev_priv->lvds_downclock_avail)
7018                 return;
7019
7020         /*
7021          * Since this is called by a timer, we should never get here in
7022          * the manual case.
7023          */
7024         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7025                 int pipe = intel_crtc->pipe;
7026                 int dpll_reg = DPLL(pipe);
7027                 int dpll;
7028
7029                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7030
7031                 assert_panel_unlocked(dev_priv, pipe);
7032
7033                 dpll = I915_READ(dpll_reg);
7034                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7035                 I915_WRITE(dpll_reg, dpll);
7036                 intel_wait_for_vblank(dev, pipe);
7037                 dpll = I915_READ(dpll_reg);
7038                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7039                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7040         }
7041
7042 }
7043
7044 void intel_mark_busy(struct drm_device *dev)
7045 {
7046         i915_update_gfx_val(dev->dev_private);
7047 }
7048
7049 void intel_mark_idle(struct drm_device *dev)
7050 {
7051         struct drm_crtc *crtc;
7052
7053         if (!i915_powersave)
7054                 return;
7055
7056         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7057                 if (!crtc->fb)
7058                         continue;
7059
7060                 intel_decrease_pllclock(crtc);
7061         }
7062 }
7063
7064 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7065                         struct intel_ring_buffer *ring)
7066 {
7067         struct drm_device *dev = obj->base.dev;
7068         struct drm_crtc *crtc;
7069
7070         if (!i915_powersave)
7071                 return;
7072
7073         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7074                 if (!crtc->fb)
7075                         continue;
7076
7077                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7078                         continue;
7079
7080                 intel_increase_pllclock(crtc);
7081                 if (ring && intel_fbc_enabled(dev))
7082                         ring->fbc_dirty = true;
7083         }
7084 }
7085
7086 static void intel_crtc_destroy(struct drm_crtc *crtc)
7087 {
7088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7089         struct drm_device *dev = crtc->dev;
7090         struct intel_unpin_work *work;
7091         unsigned long flags;
7092
7093         spin_lock_irqsave(&dev->event_lock, flags);
7094         work = intel_crtc->unpin_work;
7095         intel_crtc->unpin_work = NULL;
7096         spin_unlock_irqrestore(&dev->event_lock, flags);
7097
7098         if (work) {
7099                 cancel_work_sync(&work->work);
7100                 kfree(work);
7101         }
7102
7103         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7104
7105         drm_crtc_cleanup(crtc);
7106
7107         kfree(intel_crtc);
7108 }
7109
7110 static void intel_unpin_work_fn(struct work_struct *__work)
7111 {
7112         struct intel_unpin_work *work =
7113                 container_of(__work, struct intel_unpin_work, work);
7114         struct drm_device *dev = work->crtc->dev;
7115
7116         mutex_lock(&dev->struct_mutex);
7117         intel_unpin_fb_obj(work->old_fb_obj);
7118         drm_gem_object_unreference(&work->pending_flip_obj->base);
7119         drm_gem_object_unreference(&work->old_fb_obj->base);
7120
7121         intel_update_fbc(dev);
7122         mutex_unlock(&dev->struct_mutex);
7123
7124         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7125         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7126
7127         kfree(work);
7128 }
7129
7130 static void do_intel_finish_page_flip(struct drm_device *dev,
7131                                       struct drm_crtc *crtc)
7132 {
7133         drm_i915_private_t *dev_priv = dev->dev_private;
7134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7135         struct intel_unpin_work *work;
7136         unsigned long flags;
7137
7138         /* Ignore early vblank irqs */
7139         if (intel_crtc == NULL)
7140                 return;
7141
7142         spin_lock_irqsave(&dev->event_lock, flags);
7143         work = intel_crtc->unpin_work;
7144
7145         /* Ensure we don't miss a work->pending update ... */
7146         smp_rmb();
7147
7148         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7149                 spin_unlock_irqrestore(&dev->event_lock, flags);
7150                 return;
7151         }
7152
7153         /* and that the unpin work is consistent wrt ->pending. */
7154         smp_rmb();
7155
7156         intel_crtc->unpin_work = NULL;
7157
7158         if (work->event)
7159                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7160
7161         drm_vblank_put(dev, intel_crtc->pipe);
7162
7163         spin_unlock_irqrestore(&dev->event_lock, flags);
7164
7165         wake_up_all(&dev_priv->pending_flip_queue);
7166
7167         queue_work(dev_priv->wq, &work->work);
7168
7169         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7170 }
7171
7172 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7173 {
7174         drm_i915_private_t *dev_priv = dev->dev_private;
7175         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7176
7177         do_intel_finish_page_flip(dev, crtc);
7178 }
7179
7180 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7181 {
7182         drm_i915_private_t *dev_priv = dev->dev_private;
7183         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7184
7185         do_intel_finish_page_flip(dev, crtc);
7186 }
7187
7188 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7189 {
7190         drm_i915_private_t *dev_priv = dev->dev_private;
7191         struct intel_crtc *intel_crtc =
7192                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7193         unsigned long flags;
7194
7195         /* NB: An MMIO update of the plane base pointer will also
7196          * generate a page-flip completion irq, i.e. every modeset
7197          * is also accompanied by a spurious intel_prepare_page_flip().
7198          */
7199         spin_lock_irqsave(&dev->event_lock, flags);
7200         if (intel_crtc->unpin_work)
7201                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7202         spin_unlock_irqrestore(&dev->event_lock, flags);
7203 }
7204
7205 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7206 {
7207         /* Ensure that the work item is consistent when activating it ... */
7208         smp_wmb();
7209         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7210         /* and that it is marked active as soon as the irq could fire. */
7211         smp_wmb();
7212 }
7213
7214 static int intel_gen2_queue_flip(struct drm_device *dev,
7215                                  struct drm_crtc *crtc,
7216                                  struct drm_framebuffer *fb,
7217                                  struct drm_i915_gem_object *obj)
7218 {
7219         struct drm_i915_private *dev_priv = dev->dev_private;
7220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7221         u32 flip_mask;
7222         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7223         int ret;
7224
7225         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7226         if (ret)
7227                 goto err;
7228
7229         ret = intel_ring_begin(ring, 6);
7230         if (ret)
7231                 goto err_unpin;
7232
7233         /* Can't queue multiple flips, so wait for the previous
7234          * one to finish before executing the next.
7235          */
7236         if (intel_crtc->plane)
7237                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7238         else
7239                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7240         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7241         intel_ring_emit(ring, MI_NOOP);
7242         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7243                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7244         intel_ring_emit(ring, fb->pitches[0]);
7245         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7246         intel_ring_emit(ring, 0); /* aux display base address, unused */
7247
7248         intel_mark_page_flip_active(intel_crtc);
7249         intel_ring_advance(ring);
7250         return 0;
7251
7252 err_unpin:
7253         intel_unpin_fb_obj(obj);
7254 err:
7255         return ret;
7256 }
7257
7258 static int intel_gen3_queue_flip(struct drm_device *dev,
7259                                  struct drm_crtc *crtc,
7260                                  struct drm_framebuffer *fb,
7261                                  struct drm_i915_gem_object *obj)
7262 {
7263         struct drm_i915_private *dev_priv = dev->dev_private;
7264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7265         u32 flip_mask;
7266         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7267         int ret;
7268
7269         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7270         if (ret)
7271                 goto err;
7272
7273         ret = intel_ring_begin(ring, 6);
7274         if (ret)
7275                 goto err_unpin;
7276
7277         if (intel_crtc->plane)
7278                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7279         else
7280                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7281         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7282         intel_ring_emit(ring, MI_NOOP);
7283         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7284                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7285         intel_ring_emit(ring, fb->pitches[0]);
7286         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7287         intel_ring_emit(ring, MI_NOOP);
7288
7289         intel_mark_page_flip_active(intel_crtc);
7290         intel_ring_advance(ring);
7291         return 0;
7292
7293 err_unpin:
7294         intel_unpin_fb_obj(obj);
7295 err:
7296         return ret;
7297 }
7298
7299 static int intel_gen4_queue_flip(struct drm_device *dev,
7300                                  struct drm_crtc *crtc,
7301                                  struct drm_framebuffer *fb,
7302                                  struct drm_i915_gem_object *obj)
7303 {
7304         struct drm_i915_private *dev_priv = dev->dev_private;
7305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7306         uint32_t pf, pipesrc;
7307         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7308         int ret;
7309
7310         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7311         if (ret)
7312                 goto err;
7313
7314         ret = intel_ring_begin(ring, 4);
7315         if (ret)
7316                 goto err_unpin;
7317
7318         /* i965+ uses the linear or tiled offsets from the
7319          * Display Registers (which do not change across a page-flip)
7320          * so we need only reprogram the base address.
7321          */
7322         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7323                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7324         intel_ring_emit(ring, fb->pitches[0]);
7325         intel_ring_emit(ring,
7326                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7327                         obj->tiling_mode);
7328
7329         /* XXX Enabling the panel-fitter across page-flip is so far
7330          * untested on non-native modes, so ignore it for now.
7331          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7332          */
7333         pf = 0;
7334         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7335         intel_ring_emit(ring, pf | pipesrc);
7336
7337         intel_mark_page_flip_active(intel_crtc);
7338         intel_ring_advance(ring);
7339         return 0;
7340
7341 err_unpin:
7342         intel_unpin_fb_obj(obj);
7343 err:
7344         return ret;
7345 }
7346
7347 static int intel_gen6_queue_flip(struct drm_device *dev,
7348                                  struct drm_crtc *crtc,
7349                                  struct drm_framebuffer *fb,
7350                                  struct drm_i915_gem_object *obj)
7351 {
7352         struct drm_i915_private *dev_priv = dev->dev_private;
7353         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7354         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7355         uint32_t pf, pipesrc;
7356         int ret;
7357
7358         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7359         if (ret)
7360                 goto err;
7361
7362         ret = intel_ring_begin(ring, 4);
7363         if (ret)
7364                 goto err_unpin;
7365
7366         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7367                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7368         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7369         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7370
7371         /* Contrary to the suggestions in the documentation,
7372          * "Enable Panel Fitter" does not seem to be required when page
7373          * flipping with a non-native mode, and worse causes a normal
7374          * modeset to fail.
7375          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7376          */
7377         pf = 0;
7378         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7379         intel_ring_emit(ring, pf | pipesrc);
7380
7381         intel_mark_page_flip_active(intel_crtc);
7382         intel_ring_advance(ring);
7383         return 0;
7384
7385 err_unpin:
7386         intel_unpin_fb_obj(obj);
7387 err:
7388         return ret;
7389 }
7390
7391 /*
7392  * On gen7 we currently use the blit ring because (in early silicon at least)
7393  * the render ring doesn't give us interrpts for page flip completion, which
7394  * means clients will hang after the first flip is queued.  Fortunately the
7395  * blit ring generates interrupts properly, so use it instead.
7396  */
7397 static int intel_gen7_queue_flip(struct drm_device *dev,
7398                                  struct drm_crtc *crtc,
7399                                  struct drm_framebuffer *fb,
7400                                  struct drm_i915_gem_object *obj)
7401 {
7402         struct drm_i915_private *dev_priv = dev->dev_private;
7403         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7404         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7405         uint32_t plane_bit = 0;
7406         int ret;
7407
7408         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7409         if (ret)
7410                 goto err;
7411
7412         switch(intel_crtc->plane) {
7413         case PLANE_A:
7414                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7415                 break;
7416         case PLANE_B:
7417                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7418                 break;
7419         case PLANE_C:
7420                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7421                 break;
7422         default:
7423                 WARN_ONCE(1, "unknown plane in flip command\n");
7424                 ret = -ENODEV;
7425                 goto err_unpin;
7426         }
7427
7428         ret = intel_ring_begin(ring, 4);
7429         if (ret)
7430                 goto err_unpin;
7431
7432         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7433         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7434         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7435         intel_ring_emit(ring, (MI_NOOP));
7436
7437         intel_mark_page_flip_active(intel_crtc);
7438         intel_ring_advance(ring);
7439         return 0;
7440
7441 err_unpin:
7442         intel_unpin_fb_obj(obj);
7443 err:
7444         return ret;
7445 }
7446
7447 static int intel_default_queue_flip(struct drm_device *dev,
7448                                     struct drm_crtc *crtc,
7449                                     struct drm_framebuffer *fb,
7450                                     struct drm_i915_gem_object *obj)
7451 {
7452         return -ENODEV;
7453 }
7454
7455 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7456                                 struct drm_framebuffer *fb,
7457                                 struct drm_pending_vblank_event *event)
7458 {
7459         struct drm_device *dev = crtc->dev;
7460         struct drm_i915_private *dev_priv = dev->dev_private;
7461         struct drm_framebuffer *old_fb = crtc->fb;
7462         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7464         struct intel_unpin_work *work;
7465         unsigned long flags;
7466         int ret;
7467
7468         /* Can't change pixel format via MI display flips. */
7469         if (fb->pixel_format != crtc->fb->pixel_format)
7470                 return -EINVAL;
7471
7472         /*
7473          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7474          * Note that pitch changes could also affect these register.
7475          */
7476         if (INTEL_INFO(dev)->gen > 3 &&
7477             (fb->offsets[0] != crtc->fb->offsets[0] ||
7478              fb->pitches[0] != crtc->fb->pitches[0]))
7479                 return -EINVAL;
7480
7481         work = kzalloc(sizeof *work, GFP_KERNEL);
7482         if (work == NULL)
7483                 return -ENOMEM;
7484
7485         work->event = event;
7486         work->crtc = crtc;
7487         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7488         INIT_WORK(&work->work, intel_unpin_work_fn);
7489
7490         ret = drm_vblank_get(dev, intel_crtc->pipe);
7491         if (ret)
7492                 goto free_work;
7493
7494         /* We borrow the event spin lock for protecting unpin_work */
7495         spin_lock_irqsave(&dev->event_lock, flags);
7496         if (intel_crtc->unpin_work) {
7497                 spin_unlock_irqrestore(&dev->event_lock, flags);
7498                 kfree(work);
7499                 drm_vblank_put(dev, intel_crtc->pipe);
7500
7501                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7502                 return -EBUSY;
7503         }
7504         intel_crtc->unpin_work = work;
7505         spin_unlock_irqrestore(&dev->event_lock, flags);
7506
7507         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7508                 flush_workqueue(dev_priv->wq);
7509
7510         ret = i915_mutex_lock_interruptible(dev);
7511         if (ret)
7512                 goto cleanup;
7513
7514         /* Reference the objects for the scheduled work. */
7515         drm_gem_object_reference(&work->old_fb_obj->base);
7516         drm_gem_object_reference(&obj->base);
7517
7518         crtc->fb = fb;
7519
7520         work->pending_flip_obj = obj;
7521
7522         work->enable_stall_check = true;
7523
7524         atomic_inc(&intel_crtc->unpin_work_count);
7525         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7526
7527         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7528         if (ret)
7529                 goto cleanup_pending;
7530
7531         intel_disable_fbc(dev);
7532         intel_mark_fb_busy(obj, NULL);
7533         mutex_unlock(&dev->struct_mutex);
7534
7535         trace_i915_flip_request(intel_crtc->plane, obj);
7536
7537         return 0;
7538
7539 cleanup_pending:
7540         atomic_dec(&intel_crtc->unpin_work_count);
7541         crtc->fb = old_fb;
7542         drm_gem_object_unreference(&work->old_fb_obj->base);
7543         drm_gem_object_unreference(&obj->base);
7544         mutex_unlock(&dev->struct_mutex);
7545
7546 cleanup:
7547         spin_lock_irqsave(&dev->event_lock, flags);
7548         intel_crtc->unpin_work = NULL;
7549         spin_unlock_irqrestore(&dev->event_lock, flags);
7550
7551         drm_vblank_put(dev, intel_crtc->pipe);
7552 free_work:
7553         kfree(work);
7554
7555         return ret;
7556 }
7557
7558 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7559         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7560         .load_lut = intel_crtc_load_lut,
7561 };
7562
7563 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7564                                   struct drm_crtc *crtc)
7565 {
7566         struct drm_device *dev;
7567         struct drm_crtc *tmp;
7568         int crtc_mask = 1;
7569
7570         WARN(!crtc, "checking null crtc?\n");
7571
7572         dev = crtc->dev;
7573
7574         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7575                 if (tmp == crtc)
7576                         break;
7577                 crtc_mask <<= 1;
7578         }
7579
7580         if (encoder->possible_crtcs & crtc_mask)
7581                 return true;
7582         return false;
7583 }
7584
7585 /**
7586  * intel_modeset_update_staged_output_state
7587  *
7588  * Updates the staged output configuration state, e.g. after we've read out the
7589  * current hw state.
7590  */
7591 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7592 {
7593         struct intel_encoder *encoder;
7594         struct intel_connector *connector;
7595
7596         list_for_each_entry(connector, &dev->mode_config.connector_list,
7597                             base.head) {
7598                 connector->new_encoder =
7599                         to_intel_encoder(connector->base.encoder);
7600         }
7601
7602         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7603                             base.head) {
7604                 encoder->new_crtc =
7605                         to_intel_crtc(encoder->base.crtc);
7606         }
7607 }
7608
7609 /**
7610  * intel_modeset_commit_output_state
7611  *
7612  * This function copies the stage display pipe configuration to the real one.
7613  */
7614 static void intel_modeset_commit_output_state(struct drm_device *dev)
7615 {
7616         struct intel_encoder *encoder;
7617         struct intel_connector *connector;
7618
7619         list_for_each_entry(connector, &dev->mode_config.connector_list,
7620                             base.head) {
7621                 connector->base.encoder = &connector->new_encoder->base;
7622         }
7623
7624         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7625                             base.head) {
7626                 encoder->base.crtc = &encoder->new_crtc->base;
7627         }
7628 }
7629
7630 static void
7631 connected_sink_compute_bpp(struct intel_connector * connector,
7632                            struct intel_crtc_config *pipe_config)
7633 {
7634         int bpp = pipe_config->pipe_bpp;
7635
7636         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7637                 connector->base.base.id,
7638                 drm_get_connector_name(&connector->base));
7639
7640         /* Don't use an invalid EDID bpc value */
7641         if (connector->base.display_info.bpc &&
7642             connector->base.display_info.bpc * 3 < bpp) {
7643                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7644                               bpp, connector->base.display_info.bpc*3);
7645                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7646         }
7647
7648         /* Clamp bpp to 8 on screens without EDID 1.4 */
7649         if (connector->base.display_info.bpc == 0 && bpp > 24) {
7650                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7651                               bpp);
7652                 pipe_config->pipe_bpp = 24;
7653         }
7654 }
7655
7656 static int
7657 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7658                           struct drm_framebuffer *fb,
7659                           struct intel_crtc_config *pipe_config)
7660 {
7661         struct drm_device *dev = crtc->base.dev;
7662         struct intel_connector *connector;
7663         int bpp;
7664
7665         switch (fb->pixel_format) {
7666         case DRM_FORMAT_C8:
7667                 bpp = 8*3; /* since we go through a colormap */
7668                 break;
7669         case DRM_FORMAT_XRGB1555:
7670         case DRM_FORMAT_ARGB1555:
7671                 /* checked in intel_framebuffer_init already */
7672                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7673                         return -EINVAL;
7674         case DRM_FORMAT_RGB565:
7675                 bpp = 6*3; /* min is 18bpp */
7676                 break;
7677         case DRM_FORMAT_XBGR8888:
7678         case DRM_FORMAT_ABGR8888:
7679                 /* checked in intel_framebuffer_init already */
7680                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7681                         return -EINVAL;
7682         case DRM_FORMAT_XRGB8888:
7683         case DRM_FORMAT_ARGB8888:
7684                 bpp = 8*3;
7685                 break;
7686         case DRM_FORMAT_XRGB2101010:
7687         case DRM_FORMAT_ARGB2101010:
7688         case DRM_FORMAT_XBGR2101010:
7689         case DRM_FORMAT_ABGR2101010:
7690                 /* checked in intel_framebuffer_init already */
7691                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7692                         return -EINVAL;
7693                 bpp = 10*3;
7694                 break;
7695         /* TODO: gen4+ supports 16 bpc floating point, too. */
7696         default:
7697                 DRM_DEBUG_KMS("unsupported depth\n");
7698                 return -EINVAL;
7699         }
7700
7701         pipe_config->pipe_bpp = bpp;
7702
7703         /* Clamp display bpp to EDID value */
7704         list_for_each_entry(connector, &dev->mode_config.connector_list,
7705                             base.head) {
7706                 if (!connector->new_encoder ||
7707                     connector->new_encoder->new_crtc != crtc)
7708                         continue;
7709
7710                 connected_sink_compute_bpp(connector, pipe_config);
7711         }
7712
7713         return bpp;
7714 }
7715
7716 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7717                                    struct intel_crtc_config *pipe_config,
7718                                    const char *context)
7719 {
7720         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7721                       context, pipe_name(crtc->pipe));
7722
7723         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7724         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7725                       pipe_config->pipe_bpp, pipe_config->dither);
7726         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7727                       pipe_config->has_pch_encoder,
7728                       pipe_config->fdi_lanes,
7729                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7730                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7731                       pipe_config->fdi_m_n.tu);
7732         DRM_DEBUG_KMS("requested mode:\n");
7733         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7734         DRM_DEBUG_KMS("adjusted mode:\n");
7735         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7736         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7737                       pipe_config->gmch_pfit.control,
7738                       pipe_config->gmch_pfit.pgm_ratios,
7739                       pipe_config->gmch_pfit.lvds_border_bits);
7740         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7741                       pipe_config->pch_pfit.pos,
7742                       pipe_config->pch_pfit.size);
7743         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7744 }
7745
7746 static bool check_encoder_cloning(struct drm_crtc *crtc)
7747 {
7748         int num_encoders = 0;
7749         bool uncloneable_encoders = false;
7750         struct intel_encoder *encoder;
7751
7752         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7753                             base.head) {
7754                 if (&encoder->new_crtc->base != crtc)
7755                         continue;
7756
7757                 num_encoders++;
7758                 if (!encoder->cloneable)
7759                         uncloneable_encoders = true;
7760         }
7761
7762         return !(num_encoders > 1 && uncloneable_encoders);
7763 }
7764
7765 static struct intel_crtc_config *
7766 intel_modeset_pipe_config(struct drm_crtc *crtc,
7767                           struct drm_framebuffer *fb,
7768                           struct drm_display_mode *mode)
7769 {
7770         struct drm_device *dev = crtc->dev;
7771         struct drm_encoder_helper_funcs *encoder_funcs;
7772         struct intel_encoder *encoder;
7773         struct intel_crtc_config *pipe_config;
7774         int plane_bpp, ret = -EINVAL;
7775         bool retry = true;
7776
7777         if (!check_encoder_cloning(crtc)) {
7778                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7779                 return ERR_PTR(-EINVAL);
7780         }
7781
7782         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7783         if (!pipe_config)
7784                 return ERR_PTR(-ENOMEM);
7785
7786         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7787         drm_mode_copy(&pipe_config->requested_mode, mode);
7788         pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
7789         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7790
7791         /* Compute a starting value for pipe_config->pipe_bpp taking the source
7792          * plane pixel format and any sink constraints into account. Returns the
7793          * source plane bpp so that dithering can be selected on mismatches
7794          * after encoders and crtc also have had their say. */
7795         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7796                                               fb, pipe_config);
7797         if (plane_bpp < 0)
7798                 goto fail;
7799
7800 encoder_retry:
7801         /* Ensure the port clock defaults are reset when retrying. */
7802         pipe_config->port_clock = 0;
7803         pipe_config->pixel_multiplier = 1;
7804
7805         /* Pass our mode to the connectors and the CRTC to give them a chance to
7806          * adjust it according to limitations or connector properties, and also
7807          * a chance to reject the mode entirely.
7808          */
7809         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7810                             base.head) {
7811
7812                 if (&encoder->new_crtc->base != crtc)
7813                         continue;
7814
7815                 if (encoder->compute_config) {
7816                         if (!(encoder->compute_config(encoder, pipe_config))) {
7817                                 DRM_DEBUG_KMS("Encoder config failure\n");
7818                                 goto fail;
7819                         }
7820
7821                         continue;
7822                 }
7823
7824                 encoder_funcs = encoder->base.helper_private;
7825                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7826                                                 &pipe_config->requested_mode,
7827                                                 &pipe_config->adjusted_mode))) {
7828                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7829                         goto fail;
7830                 }
7831         }
7832
7833         /* Set default port clock if not overwritten by the encoder. Needs to be
7834          * done afterwards in case the encoder adjusts the mode. */
7835         if (!pipe_config->port_clock)
7836                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7837
7838         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7839         if (ret < 0) {
7840                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7841                 goto fail;
7842         }
7843
7844         if (ret == RETRY) {
7845                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7846                         ret = -EINVAL;
7847                         goto fail;
7848                 }
7849
7850                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7851                 retry = false;
7852                 goto encoder_retry;
7853         }
7854
7855         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7856         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7857                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7858
7859         return pipe_config;
7860 fail:
7861         kfree(pipe_config);
7862         return ERR_PTR(ret);
7863 }
7864
7865 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7866  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7867 static void
7868 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7869                              unsigned *prepare_pipes, unsigned *disable_pipes)
7870 {
7871         struct intel_crtc *intel_crtc;
7872         struct drm_device *dev = crtc->dev;
7873         struct intel_encoder *encoder;
7874         struct intel_connector *connector;
7875         struct drm_crtc *tmp_crtc;
7876
7877         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7878
7879         /* Check which crtcs have changed outputs connected to them, these need
7880          * to be part of the prepare_pipes mask. We don't (yet) support global
7881          * modeset across multiple crtcs, so modeset_pipes will only have one
7882          * bit set at most. */
7883         list_for_each_entry(connector, &dev->mode_config.connector_list,
7884                             base.head) {
7885                 if (connector->base.encoder == &connector->new_encoder->base)
7886                         continue;
7887
7888                 if (connector->base.encoder) {
7889                         tmp_crtc = connector->base.encoder->crtc;
7890
7891                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7892                 }
7893
7894                 if (connector->new_encoder)
7895                         *prepare_pipes |=
7896                                 1 << connector->new_encoder->new_crtc->pipe;
7897         }
7898
7899         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7900                             base.head) {
7901                 if (encoder->base.crtc == &encoder->new_crtc->base)
7902                         continue;
7903
7904                 if (encoder->base.crtc) {
7905                         tmp_crtc = encoder->base.crtc;
7906
7907                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7908                 }
7909
7910                 if (encoder->new_crtc)
7911                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7912         }
7913
7914         /* Check for any pipes that will be fully disabled ... */
7915         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7916                             base.head) {
7917                 bool used = false;
7918
7919                 /* Don't try to disable disabled crtcs. */
7920                 if (!intel_crtc->base.enabled)
7921                         continue;
7922
7923                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7924                                     base.head) {
7925                         if (encoder->new_crtc == intel_crtc)
7926                                 used = true;
7927                 }
7928
7929                 if (!used)
7930                         *disable_pipes |= 1 << intel_crtc->pipe;
7931         }
7932
7933
7934         /* set_mode is also used to update properties on life display pipes. */
7935         intel_crtc = to_intel_crtc(crtc);
7936         if (crtc->enabled)
7937                 *prepare_pipes |= 1 << intel_crtc->pipe;
7938
7939         /*
7940          * For simplicity do a full modeset on any pipe where the output routing
7941          * changed. We could be more clever, but that would require us to be
7942          * more careful with calling the relevant encoder->mode_set functions.
7943          */
7944         if (*prepare_pipes)
7945                 *modeset_pipes = *prepare_pipes;
7946
7947         /* ... and mask these out. */
7948         *modeset_pipes &= ~(*disable_pipes);
7949         *prepare_pipes &= ~(*disable_pipes);
7950
7951         /*
7952          * HACK: We don't (yet) fully support global modesets. intel_set_config
7953          * obies this rule, but the modeset restore mode of
7954          * intel_modeset_setup_hw_state does not.
7955          */
7956         *modeset_pipes &= 1 << intel_crtc->pipe;
7957         *prepare_pipes &= 1 << intel_crtc->pipe;
7958
7959         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7960                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7961 }
7962
7963 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7964 {
7965         struct drm_encoder *encoder;
7966         struct drm_device *dev = crtc->dev;
7967
7968         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7969                 if (encoder->crtc == crtc)
7970                         return true;
7971
7972         return false;
7973 }
7974
7975 static void
7976 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7977 {
7978         struct intel_encoder *intel_encoder;
7979         struct intel_crtc *intel_crtc;
7980         struct drm_connector *connector;
7981
7982         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7983                             base.head) {
7984                 if (!intel_encoder->base.crtc)
7985                         continue;
7986
7987                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7988
7989                 if (prepare_pipes & (1 << intel_crtc->pipe))
7990                         intel_encoder->connectors_active = false;
7991         }
7992
7993         intel_modeset_commit_output_state(dev);
7994
7995         /* Update computed state. */
7996         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7997                             base.head) {
7998                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7999         }
8000
8001         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8002                 if (!connector->encoder || !connector->encoder->crtc)
8003                         continue;
8004
8005                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8006
8007                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8008                         struct drm_property *dpms_property =
8009                                 dev->mode_config.dpms_property;
8010
8011                         connector->dpms = DRM_MODE_DPMS_ON;
8012                         drm_object_property_set_value(&connector->base,
8013                                                          dpms_property,
8014                                                          DRM_MODE_DPMS_ON);
8015
8016                         intel_encoder = to_intel_encoder(connector->encoder);
8017                         intel_encoder->connectors_active = true;
8018                 }
8019         }
8020
8021 }
8022
8023 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8024         list_for_each_entry((intel_crtc), \
8025                             &(dev)->mode_config.crtc_list, \
8026                             base.head) \
8027                 if (mask & (1 <<(intel_crtc)->pipe))
8028
8029 static bool
8030 intel_pipe_config_compare(struct drm_device *dev,
8031                           struct intel_crtc_config *current_config,
8032                           struct intel_crtc_config *pipe_config)
8033 {
8034 #define PIPE_CONF_CHECK_X(name) \
8035         if (current_config->name != pipe_config->name) { \
8036                 DRM_ERROR("mismatch in " #name " " \
8037                           "(expected 0x%08x, found 0x%08x)\n", \
8038                           current_config->name, \
8039                           pipe_config->name); \
8040                 return false; \
8041         }
8042
8043 #define PIPE_CONF_CHECK_I(name) \
8044         if (current_config->name != pipe_config->name) { \
8045                 DRM_ERROR("mismatch in " #name " " \
8046                           "(expected %i, found %i)\n", \
8047                           current_config->name, \
8048                           pipe_config->name); \
8049                 return false; \
8050         }
8051
8052 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8053         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8054                 DRM_ERROR("mismatch in " #name " " \
8055                           "(expected %i, found %i)\n", \
8056                           current_config->name & (mask), \
8057                           pipe_config->name & (mask)); \
8058                 return false; \
8059         }
8060
8061 #define PIPE_CONF_QUIRK(quirk)  \
8062         ((current_config->quirks | pipe_config->quirks) & (quirk))
8063
8064         PIPE_CONF_CHECK_I(cpu_transcoder);
8065
8066         PIPE_CONF_CHECK_I(has_pch_encoder);
8067         PIPE_CONF_CHECK_I(fdi_lanes);
8068         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8069         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8070         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8071         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8072         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8073
8074         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8075         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8076         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8077         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8078         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8079         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8080
8081         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8082         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8083         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8084         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8085         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8086         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8087
8088         if (!HAS_PCH_SPLIT(dev))
8089                 PIPE_CONF_CHECK_I(pixel_multiplier);
8090
8091         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8092                               DRM_MODE_FLAG_INTERLACE);
8093
8094         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8095                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8096                                       DRM_MODE_FLAG_PHSYNC);
8097                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8098                                       DRM_MODE_FLAG_NHSYNC);
8099                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8100                                       DRM_MODE_FLAG_PVSYNC);
8101                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8102                                       DRM_MODE_FLAG_NVSYNC);
8103         }
8104
8105         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8106         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8107
8108         PIPE_CONF_CHECK_I(gmch_pfit.control);
8109         /* pfit ratios are autocomputed by the hw on gen4+ */
8110         if (INTEL_INFO(dev)->gen < 4)
8111                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8112         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8113         PIPE_CONF_CHECK_I(pch_pfit.pos);
8114         PIPE_CONF_CHECK_I(pch_pfit.size);
8115
8116         PIPE_CONF_CHECK_I(ips_enabled);
8117
8118         PIPE_CONF_CHECK_I(shared_dpll);
8119         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8120         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8121         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8122         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8123
8124 #undef PIPE_CONF_CHECK_X
8125 #undef PIPE_CONF_CHECK_I
8126 #undef PIPE_CONF_CHECK_FLAGS
8127 #undef PIPE_CONF_QUIRK
8128
8129         return true;
8130 }
8131
8132 static void
8133 check_connector_state(struct drm_device *dev)
8134 {
8135         struct intel_connector *connector;
8136
8137         list_for_each_entry(connector, &dev->mode_config.connector_list,
8138                             base.head) {
8139                 /* This also checks the encoder/connector hw state with the
8140                  * ->get_hw_state callbacks. */
8141                 intel_connector_check_state(connector);
8142
8143                 WARN(&connector->new_encoder->base != connector->base.encoder,
8144                      "connector's staged encoder doesn't match current encoder\n");
8145         }
8146 }
8147
8148 static void
8149 check_encoder_state(struct drm_device *dev)
8150 {
8151         struct intel_encoder *encoder;
8152         struct intel_connector *connector;
8153
8154         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8155                             base.head) {
8156                 bool enabled = false;
8157                 bool active = false;
8158                 enum pipe pipe, tracked_pipe;
8159
8160                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8161                               encoder->base.base.id,
8162                               drm_get_encoder_name(&encoder->base));
8163
8164                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8165                      "encoder's stage crtc doesn't match current crtc\n");
8166                 WARN(encoder->connectors_active && !encoder->base.crtc,
8167                      "encoder's active_connectors set, but no crtc\n");
8168
8169                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8170                                     base.head) {
8171                         if (connector->base.encoder != &encoder->base)
8172                                 continue;
8173                         enabled = true;
8174                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8175                                 active = true;
8176                 }
8177                 WARN(!!encoder->base.crtc != enabled,
8178                      "encoder's enabled state mismatch "
8179                      "(expected %i, found %i)\n",
8180                      !!encoder->base.crtc, enabled);
8181                 WARN(active && !encoder->base.crtc,
8182                      "active encoder with no crtc\n");
8183
8184                 WARN(encoder->connectors_active != active,
8185                      "encoder's computed active state doesn't match tracked active state "
8186                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8187
8188                 active = encoder->get_hw_state(encoder, &pipe);
8189                 WARN(active != encoder->connectors_active,
8190                      "encoder's hw state doesn't match sw tracking "
8191                      "(expected %i, found %i)\n",
8192                      encoder->connectors_active, active);
8193
8194                 if (!encoder->base.crtc)
8195                         continue;
8196
8197                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8198                 WARN(active && pipe != tracked_pipe,
8199                      "active encoder's pipe doesn't match"
8200                      "(expected %i, found %i)\n",
8201                      tracked_pipe, pipe);
8202
8203         }
8204 }
8205
8206 static void
8207 check_crtc_state(struct drm_device *dev)
8208 {
8209         drm_i915_private_t *dev_priv = dev->dev_private;
8210         struct intel_crtc *crtc;
8211         struct intel_encoder *encoder;
8212         struct intel_crtc_config pipe_config;
8213
8214         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8215                             base.head) {
8216                 bool enabled = false;
8217                 bool active = false;
8218
8219                 memset(&pipe_config, 0, sizeof(pipe_config));
8220
8221                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8222                               crtc->base.base.id);
8223
8224                 WARN(crtc->active && !crtc->base.enabled,
8225                      "active crtc, but not enabled in sw tracking\n");
8226
8227                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8228                                     base.head) {
8229                         if (encoder->base.crtc != &crtc->base)
8230                                 continue;
8231                         enabled = true;
8232                         if (encoder->connectors_active)
8233                                 active = true;
8234                 }
8235
8236                 WARN(active != crtc->active,
8237                      "crtc's computed active state doesn't match tracked active state "
8238                      "(expected %i, found %i)\n", active, crtc->active);
8239                 WARN(enabled != crtc->base.enabled,
8240                      "crtc's computed enabled state doesn't match tracked enabled state "
8241                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8242
8243                 active = dev_priv->display.get_pipe_config(crtc,
8244                                                            &pipe_config);
8245
8246                 /* hw state is inconsistent with the pipe A quirk */
8247                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8248                         active = crtc->active;
8249
8250                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8251                                     base.head) {
8252                         if (encoder->base.crtc != &crtc->base)
8253                                 continue;
8254                         if (encoder->get_config)
8255                                 encoder->get_config(encoder, &pipe_config);
8256                 }
8257
8258                 WARN(crtc->active != active,
8259                      "crtc active state doesn't match with hw state "
8260                      "(expected %i, found %i)\n", crtc->active, active);
8261
8262                 if (active &&
8263                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8264                         WARN(1, "pipe state doesn't match!\n");
8265                         intel_dump_pipe_config(crtc, &pipe_config,
8266                                                "[hw state]");
8267                         intel_dump_pipe_config(crtc, &crtc->config,
8268                                                "[sw state]");
8269                 }
8270         }
8271 }
8272
8273 static void
8274 check_shared_dpll_state(struct drm_device *dev)
8275 {
8276         drm_i915_private_t *dev_priv = dev->dev_private;
8277         struct intel_crtc *crtc;
8278         struct intel_dpll_hw_state dpll_hw_state;
8279         int i;
8280
8281         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8282                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8283                 int enabled_crtcs = 0, active_crtcs = 0;
8284                 bool active;
8285
8286                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8287
8288                 DRM_DEBUG_KMS("%s\n", pll->name);
8289
8290                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8291
8292                 WARN(pll->active > pll->refcount,
8293                      "more active pll users than references: %i vs %i\n",
8294                      pll->active, pll->refcount);
8295                 WARN(pll->active && !pll->on,
8296                      "pll in active use but not on in sw tracking\n");
8297                 WARN(pll->on != active,
8298                      "pll on state mismatch (expected %i, found %i)\n",
8299                      pll->on, active);
8300
8301                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8302                                     base.head) {
8303                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8304                                 enabled_crtcs++;
8305                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8306                                 active_crtcs++;
8307                 }
8308                 WARN(pll->active != active_crtcs,
8309                      "pll active crtcs mismatch (expected %i, found %i)\n",
8310                      pll->active, active_crtcs);
8311                 WARN(pll->refcount != enabled_crtcs,
8312                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8313                      pll->refcount, enabled_crtcs);
8314
8315                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8316                                        sizeof(dpll_hw_state)),
8317                      "pll hw state mismatch\n");
8318         }
8319 }
8320
8321 void
8322 intel_modeset_check_state(struct drm_device *dev)
8323 {
8324         check_connector_state(dev);
8325         check_encoder_state(dev);
8326         check_crtc_state(dev);
8327         check_shared_dpll_state(dev);
8328 }
8329
8330 static int __intel_set_mode(struct drm_crtc *crtc,
8331                             struct drm_display_mode *mode,
8332                             int x, int y, struct drm_framebuffer *fb)
8333 {
8334         struct drm_device *dev = crtc->dev;
8335         drm_i915_private_t *dev_priv = dev->dev_private;
8336         struct drm_display_mode *saved_mode, *saved_hwmode;
8337         struct intel_crtc_config *pipe_config = NULL;
8338         struct intel_crtc *intel_crtc;
8339         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8340         int ret = 0;
8341
8342         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8343         if (!saved_mode)
8344                 return -ENOMEM;
8345         saved_hwmode = saved_mode + 1;
8346
8347         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8348                                      &prepare_pipes, &disable_pipes);
8349
8350         *saved_hwmode = crtc->hwmode;
8351         *saved_mode = crtc->mode;
8352
8353         /* Hack: Because we don't (yet) support global modeset on multiple
8354          * crtcs, we don't keep track of the new mode for more than one crtc.
8355          * Hence simply check whether any bit is set in modeset_pipes in all the
8356          * pieces of code that are not yet converted to deal with mutliple crtcs
8357          * changing their mode at the same time. */
8358         if (modeset_pipes) {
8359                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8360                 if (IS_ERR(pipe_config)) {
8361                         ret = PTR_ERR(pipe_config);
8362                         pipe_config = NULL;
8363
8364                         goto out;
8365                 }
8366                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8367                                        "[modeset]");
8368         }
8369
8370         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8371                 intel_crtc_disable(&intel_crtc->base);
8372
8373         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8374                 if (intel_crtc->base.enabled)
8375                         dev_priv->display.crtc_disable(&intel_crtc->base);
8376         }
8377
8378         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8379          * to set it here already despite that we pass it down the callchain.
8380          */
8381         if (modeset_pipes) {
8382                 crtc->mode = *mode;
8383                 /* mode_set/enable/disable functions rely on a correct pipe
8384                  * config. */
8385                 to_intel_crtc(crtc)->config = *pipe_config;
8386         }
8387
8388         /* Only after disabling all output pipelines that will be changed can we
8389          * update the the output configuration. */
8390         intel_modeset_update_state(dev, prepare_pipes);
8391
8392         if (dev_priv->display.modeset_global_resources)
8393                 dev_priv->display.modeset_global_resources(dev);
8394
8395         /* Set up the DPLL and any encoders state that needs to adjust or depend
8396          * on the DPLL.
8397          */
8398         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8399                 ret = intel_crtc_mode_set(&intel_crtc->base,
8400                                           x, y, fb);
8401                 if (ret)
8402                         goto done;
8403         }
8404
8405         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8406         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8407                 dev_priv->display.crtc_enable(&intel_crtc->base);
8408
8409         if (modeset_pipes) {
8410                 /* Store real post-adjustment hardware mode. */
8411                 crtc->hwmode = pipe_config->adjusted_mode;
8412
8413                 /* Calculate and store various constants which
8414                  * are later needed by vblank and swap-completion
8415                  * timestamping. They are derived from true hwmode.
8416                  */
8417                 drm_calc_timestamping_constants(crtc);
8418         }
8419
8420         /* FIXME: add subpixel order */
8421 done:
8422         if (ret && crtc->enabled) {
8423                 crtc->hwmode = *saved_hwmode;
8424                 crtc->mode = *saved_mode;
8425         }
8426
8427 out:
8428         kfree(pipe_config);
8429         kfree(saved_mode);
8430         return ret;
8431 }
8432
8433 int intel_set_mode(struct drm_crtc *crtc,
8434                      struct drm_display_mode *mode,
8435                      int x, int y, struct drm_framebuffer *fb)
8436 {
8437         int ret;
8438
8439         ret = __intel_set_mode(crtc, mode, x, y, fb);
8440
8441         if (ret == 0)
8442                 intel_modeset_check_state(crtc->dev);
8443
8444         return ret;
8445 }
8446
8447 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8448 {
8449         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8450 }
8451
8452 #undef for_each_intel_crtc_masked
8453
8454 static void intel_set_config_free(struct intel_set_config *config)
8455 {
8456         if (!config)
8457                 return;
8458
8459         kfree(config->save_connector_encoders);
8460         kfree(config->save_encoder_crtcs);
8461         kfree(config);
8462 }
8463
8464 static int intel_set_config_save_state(struct drm_device *dev,
8465                                        struct intel_set_config *config)
8466 {
8467         struct drm_encoder *encoder;
8468         struct drm_connector *connector;
8469         int count;
8470
8471         config->save_encoder_crtcs =
8472                 kcalloc(dev->mode_config.num_encoder,
8473                         sizeof(struct drm_crtc *), GFP_KERNEL);
8474         if (!config->save_encoder_crtcs)
8475                 return -ENOMEM;
8476
8477         config->save_connector_encoders =
8478                 kcalloc(dev->mode_config.num_connector,
8479                         sizeof(struct drm_encoder *), GFP_KERNEL);
8480         if (!config->save_connector_encoders)
8481                 return -ENOMEM;
8482
8483         /* Copy data. Note that driver private data is not affected.
8484          * Should anything bad happen only the expected state is
8485          * restored, not the drivers personal bookkeeping.
8486          */
8487         count = 0;
8488         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8489                 config->save_encoder_crtcs[count++] = encoder->crtc;
8490         }
8491
8492         count = 0;
8493         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8494                 config->save_connector_encoders[count++] = connector->encoder;
8495         }
8496
8497         return 0;
8498 }
8499
8500 static void intel_set_config_restore_state(struct drm_device *dev,
8501                                            struct intel_set_config *config)
8502 {
8503         struct intel_encoder *encoder;
8504         struct intel_connector *connector;
8505         int count;
8506
8507         count = 0;
8508         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8509                 encoder->new_crtc =
8510                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8511         }
8512
8513         count = 0;
8514         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8515                 connector->new_encoder =
8516                         to_intel_encoder(config->save_connector_encoders[count++]);
8517         }
8518 }
8519
8520 static bool
8521 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8522                       int num_connectors)
8523 {
8524         int i;
8525
8526         for (i = 0; i < num_connectors; i++)
8527                 if (connectors[i].encoder &&
8528                     connectors[i].encoder->crtc == crtc &&
8529                     connectors[i].dpms != DRM_MODE_DPMS_ON)
8530                         return true;
8531
8532         return false;
8533 }
8534
8535 static void
8536 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8537                                       struct intel_set_config *config)
8538 {
8539
8540         /* We should be able to check here if the fb has the same properties
8541          * and then just flip_or_move it */
8542         if (set->connectors != NULL &&
8543             is_crtc_connector_off(set->crtc, *set->connectors,
8544                                   set->num_connectors)) {
8545                         config->mode_changed = true;
8546         } else if (set->crtc->fb != set->fb) {
8547                 /* If we have no fb then treat it as a full mode set */
8548                 if (set->crtc->fb == NULL) {
8549                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8550                         config->mode_changed = true;
8551                 } else if (set->fb == NULL) {
8552                         config->mode_changed = true;
8553                 } else if (set->fb->pixel_format !=
8554                            set->crtc->fb->pixel_format) {
8555                         config->mode_changed = true;
8556                 } else {
8557                         config->fb_changed = true;
8558                 }
8559         }
8560
8561         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8562                 config->fb_changed = true;
8563
8564         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8565                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8566                 drm_mode_debug_printmodeline(&set->crtc->mode);
8567                 drm_mode_debug_printmodeline(set->mode);
8568                 config->mode_changed = true;
8569         }
8570 }
8571
8572 static int
8573 intel_modeset_stage_output_state(struct drm_device *dev,
8574                                  struct drm_mode_set *set,
8575                                  struct intel_set_config *config)
8576 {
8577         struct drm_crtc *new_crtc;
8578         struct intel_connector *connector;
8579         struct intel_encoder *encoder;
8580         int count, ro;
8581
8582         /* The upper layers ensure that we either disable a crtc or have a list
8583          * of connectors. For paranoia, double-check this. */
8584         WARN_ON(!set->fb && (set->num_connectors != 0));
8585         WARN_ON(set->fb && (set->num_connectors == 0));
8586
8587         count = 0;
8588         list_for_each_entry(connector, &dev->mode_config.connector_list,
8589                             base.head) {
8590                 /* Otherwise traverse passed in connector list and get encoders
8591                  * for them. */
8592                 for (ro = 0; ro < set->num_connectors; ro++) {
8593                         if (set->connectors[ro] == &connector->base) {
8594                                 connector->new_encoder = connector->encoder;
8595                                 break;
8596                         }
8597                 }
8598
8599                 /* If we disable the crtc, disable all its connectors. Also, if
8600                  * the connector is on the changing crtc but not on the new
8601                  * connector list, disable it. */
8602                 if ((!set->fb || ro == set->num_connectors) &&
8603                     connector->base.encoder &&
8604                     connector->base.encoder->crtc == set->crtc) {
8605                         connector->new_encoder = NULL;
8606
8607                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8608                                 connector->base.base.id,
8609                                 drm_get_connector_name(&connector->base));
8610                 }
8611
8612
8613                 if (&connector->new_encoder->base != connector->base.encoder) {
8614                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8615                         config->mode_changed = true;
8616                 }
8617         }
8618         /* connector->new_encoder is now updated for all connectors. */
8619
8620         /* Update crtc of enabled connectors. */
8621         count = 0;
8622         list_for_each_entry(connector, &dev->mode_config.connector_list,
8623                             base.head) {
8624                 if (!connector->new_encoder)
8625                         continue;
8626
8627                 new_crtc = connector->new_encoder->base.crtc;
8628
8629                 for (ro = 0; ro < set->num_connectors; ro++) {
8630                         if (set->connectors[ro] == &connector->base)
8631                                 new_crtc = set->crtc;
8632                 }
8633
8634                 /* Make sure the new CRTC will work with the encoder */
8635                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8636                                            new_crtc)) {
8637                         return -EINVAL;
8638                 }
8639                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8640
8641                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8642                         connector->base.base.id,
8643                         drm_get_connector_name(&connector->base),
8644                         new_crtc->base.id);
8645         }
8646
8647         /* Check for any encoders that needs to be disabled. */
8648         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8649                             base.head) {
8650                 list_for_each_entry(connector,
8651                                     &dev->mode_config.connector_list,
8652                                     base.head) {
8653                         if (connector->new_encoder == encoder) {
8654                                 WARN_ON(!connector->new_encoder->new_crtc);
8655
8656                                 goto next_encoder;
8657                         }
8658                 }
8659                 encoder->new_crtc = NULL;
8660 next_encoder:
8661                 /* Only now check for crtc changes so we don't miss encoders
8662                  * that will be disabled. */
8663                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8664                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8665                         config->mode_changed = true;
8666                 }
8667         }
8668         /* Now we've also updated encoder->new_crtc for all encoders. */
8669
8670         return 0;
8671 }
8672
8673 static int intel_crtc_set_config(struct drm_mode_set *set)
8674 {
8675         struct drm_device *dev;
8676         struct drm_mode_set save_set;
8677         struct intel_set_config *config;
8678         int ret;
8679
8680         BUG_ON(!set);
8681         BUG_ON(!set->crtc);
8682         BUG_ON(!set->crtc->helper_private);
8683
8684         /* Enforce sane interface api - has been abused by the fb helper. */
8685         BUG_ON(!set->mode && set->fb);
8686         BUG_ON(set->fb && set->num_connectors == 0);
8687
8688         if (set->fb) {
8689                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8690                                 set->crtc->base.id, set->fb->base.id,
8691                                 (int)set->num_connectors, set->x, set->y);
8692         } else {
8693                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8694         }
8695
8696         dev = set->crtc->dev;
8697
8698         ret = -ENOMEM;
8699         config = kzalloc(sizeof(*config), GFP_KERNEL);
8700         if (!config)
8701                 goto out_config;
8702
8703         ret = intel_set_config_save_state(dev, config);
8704         if (ret)
8705                 goto out_config;
8706
8707         save_set.crtc = set->crtc;
8708         save_set.mode = &set->crtc->mode;
8709         save_set.x = set->crtc->x;
8710         save_set.y = set->crtc->y;
8711         save_set.fb = set->crtc->fb;
8712
8713         /* Compute whether we need a full modeset, only an fb base update or no
8714          * change at all. In the future we might also check whether only the
8715          * mode changed, e.g. for LVDS where we only change the panel fitter in
8716          * such cases. */
8717         intel_set_config_compute_mode_changes(set, config);
8718
8719         ret = intel_modeset_stage_output_state(dev, set, config);
8720         if (ret)
8721                 goto fail;
8722
8723         if (config->mode_changed) {
8724                 ret = intel_set_mode(set->crtc, set->mode,
8725                                      set->x, set->y, set->fb);
8726         } else if (config->fb_changed) {
8727                 intel_crtc_wait_for_pending_flips(set->crtc);
8728
8729                 ret = intel_pipe_set_base(set->crtc,
8730                                           set->x, set->y, set->fb);
8731         }
8732
8733         if (ret) {
8734                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8735                               set->crtc->base.id, ret);
8736 fail:
8737                 intel_set_config_restore_state(dev, config);
8738
8739                 /* Try to restore the config */
8740                 if (config->mode_changed &&
8741                     intel_set_mode(save_set.crtc, save_set.mode,
8742                                    save_set.x, save_set.y, save_set.fb))
8743                         DRM_ERROR("failed to restore config after modeset failure\n");
8744         }
8745
8746 out_config:
8747         intel_set_config_free(config);
8748         return ret;
8749 }
8750
8751 static const struct drm_crtc_funcs intel_crtc_funcs = {
8752         .cursor_set = intel_crtc_cursor_set,
8753         .cursor_move = intel_crtc_cursor_move,
8754         .gamma_set = intel_crtc_gamma_set,
8755         .set_config = intel_crtc_set_config,
8756         .destroy = intel_crtc_destroy,
8757         .page_flip = intel_crtc_page_flip,
8758 };
8759
8760 static void intel_cpu_pll_init(struct drm_device *dev)
8761 {
8762         if (HAS_DDI(dev))
8763                 intel_ddi_pll_init(dev);
8764 }
8765
8766 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8767                                       struct intel_shared_dpll *pll,
8768                                       struct intel_dpll_hw_state *hw_state)
8769 {
8770         uint32_t val;
8771
8772         val = I915_READ(PCH_DPLL(pll->id));
8773         hw_state->dpll = val;
8774         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8775         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8776
8777         return val & DPLL_VCO_ENABLE;
8778 }
8779
8780 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8781                                   struct intel_shared_dpll *pll)
8782 {
8783         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8784         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8785 }
8786
8787 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8788                                 struct intel_shared_dpll *pll)
8789 {
8790         /* PCH refclock must be enabled first */
8791         assert_pch_refclk_enabled(dev_priv);
8792
8793         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8794
8795         /* Wait for the clocks to stabilize. */
8796         POSTING_READ(PCH_DPLL(pll->id));
8797         udelay(150);
8798
8799         /* The pixel multiplier can only be updated once the
8800          * DPLL is enabled and the clocks are stable.
8801          *
8802          * So write it again.
8803          */
8804         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8805         POSTING_READ(PCH_DPLL(pll->id));
8806         udelay(200);
8807 }
8808
8809 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8810                                  struct intel_shared_dpll *pll)
8811 {
8812         struct drm_device *dev = dev_priv->dev;
8813         struct intel_crtc *crtc;
8814
8815         /* Make sure no transcoder isn't still depending on us. */
8816         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8817                 if (intel_crtc_to_shared_dpll(crtc) == pll)
8818                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8819         }
8820
8821         I915_WRITE(PCH_DPLL(pll->id), 0);
8822         POSTING_READ(PCH_DPLL(pll->id));
8823         udelay(200);
8824 }
8825
8826 static char *ibx_pch_dpll_names[] = {
8827         "PCH DPLL A",
8828         "PCH DPLL B",
8829 };
8830
8831 static void ibx_pch_dpll_init(struct drm_device *dev)
8832 {
8833         struct drm_i915_private *dev_priv = dev->dev_private;
8834         int i;
8835
8836         dev_priv->num_shared_dpll = 2;
8837
8838         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8839                 dev_priv->shared_dplls[i].id = i;
8840                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8841                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
8842                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8843                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8844                 dev_priv->shared_dplls[i].get_hw_state =
8845                         ibx_pch_dpll_get_hw_state;
8846         }
8847 }
8848
8849 static void intel_shared_dpll_init(struct drm_device *dev)
8850 {
8851         struct drm_i915_private *dev_priv = dev->dev_private;
8852
8853         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8854                 ibx_pch_dpll_init(dev);
8855         else
8856                 dev_priv->num_shared_dpll = 0;
8857
8858         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8859         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8860                       dev_priv->num_shared_dpll);
8861 }
8862
8863 static void intel_crtc_init(struct drm_device *dev, int pipe)
8864 {
8865         drm_i915_private_t *dev_priv = dev->dev_private;
8866         struct intel_crtc *intel_crtc;
8867         int i;
8868
8869         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8870         if (intel_crtc == NULL)
8871                 return;
8872
8873         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8874
8875         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8876         for (i = 0; i < 256; i++) {
8877                 intel_crtc->lut_r[i] = i;
8878                 intel_crtc->lut_g[i] = i;
8879                 intel_crtc->lut_b[i] = i;
8880         }
8881
8882         /* Swap pipes & planes for FBC on pre-965 */
8883         intel_crtc->pipe = pipe;
8884         intel_crtc->plane = pipe;
8885         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8886                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8887                 intel_crtc->plane = !pipe;
8888         }
8889
8890         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8891                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8892         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8893         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8894
8895         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8896 }
8897
8898 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8899                                 struct drm_file *file)
8900 {
8901         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8902         struct drm_mode_object *drmmode_obj;
8903         struct intel_crtc *crtc;
8904
8905         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8906                 return -ENODEV;
8907
8908         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8909                         DRM_MODE_OBJECT_CRTC);
8910
8911         if (!drmmode_obj) {
8912                 DRM_ERROR("no such CRTC id\n");
8913                 return -EINVAL;
8914         }
8915
8916         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8917         pipe_from_crtc_id->pipe = crtc->pipe;
8918
8919         return 0;
8920 }
8921
8922 static int intel_encoder_clones(struct intel_encoder *encoder)
8923 {
8924         struct drm_device *dev = encoder->base.dev;
8925         struct intel_encoder *source_encoder;
8926         int index_mask = 0;
8927         int entry = 0;
8928
8929         list_for_each_entry(source_encoder,
8930                             &dev->mode_config.encoder_list, base.head) {
8931
8932                 if (encoder == source_encoder)
8933                         index_mask |= (1 << entry);
8934
8935                 /* Intel hw has only one MUX where enocoders could be cloned. */
8936                 if (encoder->cloneable && source_encoder->cloneable)
8937                         index_mask |= (1 << entry);
8938
8939                 entry++;
8940         }
8941
8942         return index_mask;
8943 }
8944
8945 static bool has_edp_a(struct drm_device *dev)
8946 {
8947         struct drm_i915_private *dev_priv = dev->dev_private;
8948
8949         if (!IS_MOBILE(dev))
8950                 return false;
8951
8952         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8953                 return false;
8954
8955         if (IS_GEN5(dev) &&
8956             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8957                 return false;
8958
8959         return true;
8960 }
8961
8962 static void intel_setup_outputs(struct drm_device *dev)
8963 {
8964         struct drm_i915_private *dev_priv = dev->dev_private;
8965         struct intel_encoder *encoder;
8966         bool dpd_is_edp = false;
8967
8968         intel_lvds_init(dev);
8969
8970         if (!IS_ULT(dev))
8971                 intel_crt_init(dev);
8972
8973         if (HAS_DDI(dev)) {
8974                 int found;
8975
8976                 /* Haswell uses DDI functions to detect digital outputs */
8977                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8978                 /* DDI A only supports eDP */
8979                 if (found)
8980                         intel_ddi_init(dev, PORT_A);
8981
8982                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8983                  * register */
8984                 found = I915_READ(SFUSE_STRAP);
8985
8986                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8987                         intel_ddi_init(dev, PORT_B);
8988                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8989                         intel_ddi_init(dev, PORT_C);
8990                 if (found & SFUSE_STRAP_DDID_DETECTED)
8991                         intel_ddi_init(dev, PORT_D);
8992         } else if (HAS_PCH_SPLIT(dev)) {
8993                 int found;
8994                 dpd_is_edp = intel_dpd_is_edp(dev);
8995
8996                 if (has_edp_a(dev))
8997                         intel_dp_init(dev, DP_A, PORT_A);
8998
8999                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9000                         /* PCH SDVOB multiplex with HDMIB */
9001                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9002                         if (!found)
9003                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9004                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9005                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9006                 }
9007
9008                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9009                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9010
9011                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9012                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9013
9014                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9015                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9016
9017                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9018                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9019         } else if (IS_VALLEYVIEW(dev)) {
9020                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9021                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9022                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9023
9024                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9025                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9026                                         PORT_B);
9027                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9028                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9029                 }
9030         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9031                 bool found = false;
9032
9033                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9034                         DRM_DEBUG_KMS("probing SDVOB\n");
9035                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9036                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9037                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9038                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9039                         }
9040
9041                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9042                                 intel_dp_init(dev, DP_B, PORT_B);
9043                 }
9044
9045                 /* Before G4X SDVOC doesn't have its own detect register */
9046
9047                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9048                         DRM_DEBUG_KMS("probing SDVOC\n");
9049                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9050                 }
9051
9052                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9053
9054                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9055                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9056                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9057                         }
9058                         if (SUPPORTS_INTEGRATED_DP(dev))
9059                                 intel_dp_init(dev, DP_C, PORT_C);
9060                 }
9061
9062                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9063                     (I915_READ(DP_D) & DP_DETECTED))
9064                         intel_dp_init(dev, DP_D, PORT_D);
9065         } else if (IS_GEN2(dev))
9066                 intel_dvo_init(dev);
9067
9068         if (SUPPORTS_TV(dev))
9069                 intel_tv_init(dev);
9070
9071         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9072                 encoder->base.possible_crtcs = encoder->crtc_mask;
9073                 encoder->base.possible_clones =
9074                         intel_encoder_clones(encoder);
9075         }
9076
9077         intel_init_pch_refclk(dev);
9078
9079         drm_helper_move_panel_connectors_to_head(dev);
9080 }
9081
9082 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9083 {
9084         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9085
9086         drm_framebuffer_cleanup(fb);
9087         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9088
9089         kfree(intel_fb);
9090 }
9091
9092 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9093                                                 struct drm_file *file,
9094                                                 unsigned int *handle)
9095 {
9096         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9097         struct drm_i915_gem_object *obj = intel_fb->obj;
9098
9099         return drm_gem_handle_create(file, &obj->base, handle);
9100 }
9101
9102 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9103         .destroy = intel_user_framebuffer_destroy,
9104         .create_handle = intel_user_framebuffer_create_handle,
9105 };
9106
9107 int intel_framebuffer_init(struct drm_device *dev,
9108                            struct intel_framebuffer *intel_fb,
9109                            struct drm_mode_fb_cmd2 *mode_cmd,
9110                            struct drm_i915_gem_object *obj)
9111 {
9112         int pitch_limit;
9113         int ret;
9114
9115         if (obj->tiling_mode == I915_TILING_Y) {
9116                 DRM_DEBUG("hardware does not support tiling Y\n");
9117                 return -EINVAL;
9118         }
9119
9120         if (mode_cmd->pitches[0] & 63) {
9121                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9122                           mode_cmd->pitches[0]);
9123                 return -EINVAL;
9124         }
9125
9126         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9127                 pitch_limit = 32*1024;
9128         } else if (INTEL_INFO(dev)->gen >= 4) {
9129                 if (obj->tiling_mode)
9130                         pitch_limit = 16*1024;
9131                 else
9132                         pitch_limit = 32*1024;
9133         } else if (INTEL_INFO(dev)->gen >= 3) {
9134                 if (obj->tiling_mode)
9135                         pitch_limit = 8*1024;
9136                 else
9137                         pitch_limit = 16*1024;
9138         } else
9139                 /* XXX DSPC is limited to 4k tiled */
9140                 pitch_limit = 8*1024;
9141
9142         if (mode_cmd->pitches[0] > pitch_limit) {
9143                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9144                           obj->tiling_mode ? "tiled" : "linear",
9145                           mode_cmd->pitches[0], pitch_limit);
9146                 return -EINVAL;
9147         }
9148
9149         if (obj->tiling_mode != I915_TILING_NONE &&
9150             mode_cmd->pitches[0] != obj->stride) {
9151                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9152                           mode_cmd->pitches[0], obj->stride);
9153                 return -EINVAL;
9154         }
9155
9156         /* Reject formats not supported by any plane early. */
9157         switch (mode_cmd->pixel_format) {
9158         case DRM_FORMAT_C8:
9159         case DRM_FORMAT_RGB565:
9160         case DRM_FORMAT_XRGB8888:
9161         case DRM_FORMAT_ARGB8888:
9162                 break;
9163         case DRM_FORMAT_XRGB1555:
9164         case DRM_FORMAT_ARGB1555:
9165                 if (INTEL_INFO(dev)->gen > 3) {
9166                         DRM_DEBUG("unsupported pixel format: %s\n",
9167                                   drm_get_format_name(mode_cmd->pixel_format));
9168                         return -EINVAL;
9169                 }
9170                 break;
9171         case DRM_FORMAT_XBGR8888:
9172         case DRM_FORMAT_ABGR8888:
9173         case DRM_FORMAT_XRGB2101010:
9174         case DRM_FORMAT_ARGB2101010:
9175         case DRM_FORMAT_XBGR2101010:
9176         case DRM_FORMAT_ABGR2101010:
9177                 if (INTEL_INFO(dev)->gen < 4) {
9178                         DRM_DEBUG("unsupported pixel format: %s\n",
9179                                   drm_get_format_name(mode_cmd->pixel_format));
9180                         return -EINVAL;
9181                 }
9182                 break;
9183         case DRM_FORMAT_YUYV:
9184         case DRM_FORMAT_UYVY:
9185         case DRM_FORMAT_YVYU:
9186         case DRM_FORMAT_VYUY:
9187                 if (INTEL_INFO(dev)->gen < 5) {
9188                         DRM_DEBUG("unsupported pixel format: %s\n",
9189                                   drm_get_format_name(mode_cmd->pixel_format));
9190                         return -EINVAL;
9191                 }
9192                 break;
9193         default:
9194                 DRM_DEBUG("unsupported pixel format: %s\n",
9195                           drm_get_format_name(mode_cmd->pixel_format));
9196                 return -EINVAL;
9197         }
9198
9199         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9200         if (mode_cmd->offsets[0] != 0)
9201                 return -EINVAL;
9202
9203         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9204         intel_fb->obj = obj;
9205
9206         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9207         if (ret) {
9208                 DRM_ERROR("framebuffer init failed %d\n", ret);
9209                 return ret;
9210         }
9211
9212         return 0;
9213 }
9214
9215 static struct drm_framebuffer *
9216 intel_user_framebuffer_create(struct drm_device *dev,
9217                               struct drm_file *filp,
9218                               struct drm_mode_fb_cmd2 *mode_cmd)
9219 {
9220         struct drm_i915_gem_object *obj;
9221
9222         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9223                                                 mode_cmd->handles[0]));
9224         if (&obj->base == NULL)
9225                 return ERR_PTR(-ENOENT);
9226
9227         return intel_framebuffer_create(dev, mode_cmd, obj);
9228 }
9229
9230 static const struct drm_mode_config_funcs intel_mode_funcs = {
9231         .fb_create = intel_user_framebuffer_create,
9232         .output_poll_changed = intel_fb_output_poll_changed,
9233 };
9234
9235 /* Set up chip specific display functions */
9236 static void intel_init_display(struct drm_device *dev)
9237 {
9238         struct drm_i915_private *dev_priv = dev->dev_private;
9239
9240         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9241                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9242         else if (IS_VALLEYVIEW(dev))
9243                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9244         else if (IS_PINEVIEW(dev))
9245                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9246         else
9247                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9248
9249         if (HAS_DDI(dev)) {
9250                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9251                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9252                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9253                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9254                 dev_priv->display.off = haswell_crtc_off;
9255                 dev_priv->display.update_plane = ironlake_update_plane;
9256         } else if (HAS_PCH_SPLIT(dev)) {
9257                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9258                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9259                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9260                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9261                 dev_priv->display.off = ironlake_crtc_off;
9262                 dev_priv->display.update_plane = ironlake_update_plane;
9263         } else if (IS_VALLEYVIEW(dev)) {
9264                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9265                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9266                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9267                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9268                 dev_priv->display.off = i9xx_crtc_off;
9269                 dev_priv->display.update_plane = i9xx_update_plane;
9270         } else {
9271                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9272                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9273                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9274                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9275                 dev_priv->display.off = i9xx_crtc_off;
9276                 dev_priv->display.update_plane = i9xx_update_plane;
9277         }
9278
9279         /* Returns the core display clock speed */
9280         if (IS_VALLEYVIEW(dev))
9281                 dev_priv->display.get_display_clock_speed =
9282                         valleyview_get_display_clock_speed;
9283         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9284                 dev_priv->display.get_display_clock_speed =
9285                         i945_get_display_clock_speed;
9286         else if (IS_I915G(dev))
9287                 dev_priv->display.get_display_clock_speed =
9288                         i915_get_display_clock_speed;
9289         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9290                 dev_priv->display.get_display_clock_speed =
9291                         i9xx_misc_get_display_clock_speed;
9292         else if (IS_I915GM(dev))
9293                 dev_priv->display.get_display_clock_speed =
9294                         i915gm_get_display_clock_speed;
9295         else if (IS_I865G(dev))
9296                 dev_priv->display.get_display_clock_speed =
9297                         i865_get_display_clock_speed;
9298         else if (IS_I85X(dev))
9299                 dev_priv->display.get_display_clock_speed =
9300                         i855_get_display_clock_speed;
9301         else /* 852, 830 */
9302                 dev_priv->display.get_display_clock_speed =
9303                         i830_get_display_clock_speed;
9304
9305         if (HAS_PCH_SPLIT(dev)) {
9306                 if (IS_GEN5(dev)) {
9307                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9308                         dev_priv->display.write_eld = ironlake_write_eld;
9309                 } else if (IS_GEN6(dev)) {
9310                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9311                         dev_priv->display.write_eld = ironlake_write_eld;
9312                 } else if (IS_IVYBRIDGE(dev)) {
9313                         /* FIXME: detect B0+ stepping and use auto training */
9314                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9315                         dev_priv->display.write_eld = ironlake_write_eld;
9316                         dev_priv->display.modeset_global_resources =
9317                                 ivb_modeset_global_resources;
9318                 } else if (IS_HASWELL(dev)) {
9319                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9320                         dev_priv->display.write_eld = haswell_write_eld;
9321                         dev_priv->display.modeset_global_resources =
9322                                 haswell_modeset_global_resources;
9323                 }
9324         } else if (IS_G4X(dev)) {
9325                 dev_priv->display.write_eld = g4x_write_eld;
9326         }
9327
9328         /* Default just returns -ENODEV to indicate unsupported */
9329         dev_priv->display.queue_flip = intel_default_queue_flip;
9330
9331         switch (INTEL_INFO(dev)->gen) {
9332         case 2:
9333                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9334                 break;
9335
9336         case 3:
9337                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9338                 break;
9339
9340         case 4:
9341         case 5:
9342                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9343                 break;
9344
9345         case 6:
9346                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9347                 break;
9348         case 7:
9349                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9350                 break;
9351         }
9352 }
9353
9354 /*
9355  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9356  * resume, or other times.  This quirk makes sure that's the case for
9357  * affected systems.
9358  */
9359 static void quirk_pipea_force(struct drm_device *dev)
9360 {
9361         struct drm_i915_private *dev_priv = dev->dev_private;
9362
9363         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9364         DRM_INFO("applying pipe a force quirk\n");
9365 }
9366
9367 /*
9368  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9369  */
9370 static void quirk_ssc_force_disable(struct drm_device *dev)
9371 {
9372         struct drm_i915_private *dev_priv = dev->dev_private;
9373         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9374         DRM_INFO("applying lvds SSC disable quirk\n");
9375 }
9376
9377 /*
9378  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9379  * brightness value
9380  */
9381 static void quirk_invert_brightness(struct drm_device *dev)
9382 {
9383         struct drm_i915_private *dev_priv = dev->dev_private;
9384         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9385         DRM_INFO("applying inverted panel brightness quirk\n");
9386 }
9387
9388 struct intel_quirk {
9389         int device;
9390         int subsystem_vendor;
9391         int subsystem_device;
9392         void (*hook)(struct drm_device *dev);
9393 };
9394
9395 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9396 struct intel_dmi_quirk {
9397         void (*hook)(struct drm_device *dev);
9398         const struct dmi_system_id (*dmi_id_list)[];
9399 };
9400
9401 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9402 {
9403         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9404         return 1;
9405 }
9406
9407 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9408         {
9409                 .dmi_id_list = &(const struct dmi_system_id[]) {
9410                         {
9411                                 .callback = intel_dmi_reverse_brightness,
9412                                 .ident = "NCR Corporation",
9413                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9414                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9415                                 },
9416                         },
9417                         { }  /* terminating entry */
9418                 },
9419                 .hook = quirk_invert_brightness,
9420         },
9421 };
9422
9423 static struct intel_quirk intel_quirks[] = {
9424         /* HP Mini needs pipe A force quirk (LP: #322104) */
9425         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9426
9427         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9428         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9429
9430         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9431         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9432
9433         /* 830/845 need to leave pipe A & dpll A up */
9434         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9435         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9436
9437         /* Lenovo U160 cannot use SSC on LVDS */
9438         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9439
9440         /* Sony Vaio Y cannot use SSC on LVDS */
9441         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9442
9443         /* Acer Aspire 5734Z must invert backlight brightness */
9444         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9445
9446         /* Acer/eMachines G725 */
9447         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9448
9449         /* Acer/eMachines e725 */
9450         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9451
9452         /* Acer/Packard Bell NCL20 */
9453         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9454
9455         /* Acer Aspire 4736Z */
9456         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9457 };
9458
9459 static void intel_init_quirks(struct drm_device *dev)
9460 {
9461         struct pci_dev *d = dev->pdev;
9462         int i;
9463
9464         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9465                 struct intel_quirk *q = &intel_quirks[i];
9466
9467                 if (d->device == q->device &&
9468                     (d->subsystem_vendor == q->subsystem_vendor ||
9469                      q->subsystem_vendor == PCI_ANY_ID) &&
9470                     (d->subsystem_device == q->subsystem_device ||
9471                      q->subsystem_device == PCI_ANY_ID))
9472                         q->hook(dev);
9473         }
9474         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9475                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9476                         intel_dmi_quirks[i].hook(dev);
9477         }
9478 }
9479
9480 /* Disable the VGA plane that we never use */
9481 static void i915_disable_vga(struct drm_device *dev)
9482 {
9483         struct drm_i915_private *dev_priv = dev->dev_private;
9484         u8 sr1;
9485         u32 vga_reg = i915_vgacntrl_reg(dev);
9486
9487         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9488         outb(SR01, VGA_SR_INDEX);
9489         sr1 = inb(VGA_SR_DATA);
9490         outb(sr1 | 1<<5, VGA_SR_DATA);
9491         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9492         udelay(300);
9493
9494         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9495         POSTING_READ(vga_reg);
9496 }
9497
9498 void intel_modeset_init_hw(struct drm_device *dev)
9499 {
9500         intel_init_power_well(dev);
9501
9502         intel_prepare_ddi(dev);
9503
9504         intel_init_clock_gating(dev);
9505
9506         mutex_lock(&dev->struct_mutex);
9507         intel_enable_gt_powersave(dev);
9508         mutex_unlock(&dev->struct_mutex);
9509 }
9510
9511 void intel_modeset_suspend_hw(struct drm_device *dev)
9512 {
9513         intel_suspend_hw(dev);
9514 }
9515
9516 void intel_modeset_init(struct drm_device *dev)
9517 {
9518         struct drm_i915_private *dev_priv = dev->dev_private;
9519         int i, j, ret;
9520
9521         drm_mode_config_init(dev);
9522
9523         dev->mode_config.min_width = 0;
9524         dev->mode_config.min_height = 0;
9525
9526         dev->mode_config.preferred_depth = 24;
9527         dev->mode_config.prefer_shadow = 1;
9528
9529         dev->mode_config.funcs = &intel_mode_funcs;
9530
9531         intel_init_quirks(dev);
9532
9533         intel_init_pm(dev);
9534
9535         if (INTEL_INFO(dev)->num_pipes == 0)
9536                 return;
9537
9538         intel_init_display(dev);
9539
9540         if (IS_GEN2(dev)) {
9541                 dev->mode_config.max_width = 2048;
9542                 dev->mode_config.max_height = 2048;
9543         } else if (IS_GEN3(dev)) {
9544                 dev->mode_config.max_width = 4096;
9545                 dev->mode_config.max_height = 4096;
9546         } else {
9547                 dev->mode_config.max_width = 8192;
9548                 dev->mode_config.max_height = 8192;
9549         }
9550         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9551
9552         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9553                       INTEL_INFO(dev)->num_pipes,
9554                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9555
9556         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9557                 intel_crtc_init(dev, i);
9558                 for (j = 0; j < dev_priv->num_plane; j++) {
9559                         ret = intel_plane_init(dev, i, j);
9560                         if (ret)
9561                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9562                                               pipe_name(i), sprite_name(i, j), ret);
9563                 }
9564         }
9565
9566         intel_cpu_pll_init(dev);
9567         intel_shared_dpll_init(dev);
9568
9569         /* Just disable it once at startup */
9570         i915_disable_vga(dev);
9571         intel_setup_outputs(dev);
9572
9573         /* Just in case the BIOS is doing something questionable. */
9574         intel_disable_fbc(dev);
9575 }
9576
9577 static void
9578 intel_connector_break_all_links(struct intel_connector *connector)
9579 {
9580         connector->base.dpms = DRM_MODE_DPMS_OFF;
9581         connector->base.encoder = NULL;
9582         connector->encoder->connectors_active = false;
9583         connector->encoder->base.crtc = NULL;
9584 }
9585
9586 static void intel_enable_pipe_a(struct drm_device *dev)
9587 {
9588         struct intel_connector *connector;
9589         struct drm_connector *crt = NULL;
9590         struct intel_load_detect_pipe load_detect_temp;
9591
9592         /* We can't just switch on the pipe A, we need to set things up with a
9593          * proper mode and output configuration. As a gross hack, enable pipe A
9594          * by enabling the load detect pipe once. */
9595         list_for_each_entry(connector,
9596                             &dev->mode_config.connector_list,
9597                             base.head) {
9598                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9599                         crt = &connector->base;
9600                         break;
9601                 }
9602         }
9603
9604         if (!crt)
9605                 return;
9606
9607         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9608                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9609
9610
9611 }
9612
9613 static bool
9614 intel_check_plane_mapping(struct intel_crtc *crtc)
9615 {
9616         struct drm_device *dev = crtc->base.dev;
9617         struct drm_i915_private *dev_priv = dev->dev_private;
9618         u32 reg, val;
9619
9620         if (INTEL_INFO(dev)->num_pipes == 1)
9621                 return true;
9622
9623         reg = DSPCNTR(!crtc->plane);
9624         val = I915_READ(reg);
9625
9626         if ((val & DISPLAY_PLANE_ENABLE) &&
9627             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9628                 return false;
9629
9630         return true;
9631 }
9632
9633 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9634 {
9635         struct drm_device *dev = crtc->base.dev;
9636         struct drm_i915_private *dev_priv = dev->dev_private;
9637         u32 reg;
9638
9639         /* Clear any frame start delays used for debugging left by the BIOS */
9640         reg = PIPECONF(crtc->config.cpu_transcoder);
9641         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9642
9643         /* We need to sanitize the plane -> pipe mapping first because this will
9644          * disable the crtc (and hence change the state) if it is wrong. Note
9645          * that gen4+ has a fixed plane -> pipe mapping.  */
9646         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9647                 struct intel_connector *connector;
9648                 bool plane;
9649
9650                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9651                               crtc->base.base.id);
9652
9653                 /* Pipe has the wrong plane attached and the plane is active.
9654                  * Temporarily change the plane mapping and disable everything
9655                  * ...  */
9656                 plane = crtc->plane;
9657                 crtc->plane = !plane;
9658                 dev_priv->display.crtc_disable(&crtc->base);
9659                 crtc->plane = plane;
9660
9661                 /* ... and break all links. */
9662                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9663                                     base.head) {
9664                         if (connector->encoder->base.crtc != &crtc->base)
9665                                 continue;
9666
9667                         intel_connector_break_all_links(connector);
9668                 }
9669
9670                 WARN_ON(crtc->active);
9671                 crtc->base.enabled = false;
9672         }
9673
9674         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9675             crtc->pipe == PIPE_A && !crtc->active) {
9676                 /* BIOS forgot to enable pipe A, this mostly happens after
9677                  * resume. Force-enable the pipe to fix this, the update_dpms
9678                  * call below we restore the pipe to the right state, but leave
9679                  * the required bits on. */
9680                 intel_enable_pipe_a(dev);
9681         }
9682
9683         /* Adjust the state of the output pipe according to whether we
9684          * have active connectors/encoders. */
9685         intel_crtc_update_dpms(&crtc->base);
9686
9687         if (crtc->active != crtc->base.enabled) {
9688                 struct intel_encoder *encoder;
9689
9690                 /* This can happen either due to bugs in the get_hw_state
9691                  * functions or because the pipe is force-enabled due to the
9692                  * pipe A quirk. */
9693                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9694                               crtc->base.base.id,
9695                               crtc->base.enabled ? "enabled" : "disabled",
9696                               crtc->active ? "enabled" : "disabled");
9697
9698                 crtc->base.enabled = crtc->active;
9699
9700                 /* Because we only establish the connector -> encoder ->
9701                  * crtc links if something is active, this means the
9702                  * crtc is now deactivated. Break the links. connector
9703                  * -> encoder links are only establish when things are
9704                  *  actually up, hence no need to break them. */
9705                 WARN_ON(crtc->active);
9706
9707                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9708                         WARN_ON(encoder->connectors_active);
9709                         encoder->base.crtc = NULL;
9710                 }
9711         }
9712 }
9713
9714 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9715 {
9716         struct intel_connector *connector;
9717         struct drm_device *dev = encoder->base.dev;
9718
9719         /* We need to check both for a crtc link (meaning that the
9720          * encoder is active and trying to read from a pipe) and the
9721          * pipe itself being active. */
9722         bool has_active_crtc = encoder->base.crtc &&
9723                 to_intel_crtc(encoder->base.crtc)->active;
9724
9725         if (encoder->connectors_active && !has_active_crtc) {
9726                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9727                               encoder->base.base.id,
9728                               drm_get_encoder_name(&encoder->base));
9729
9730                 /* Connector is active, but has no active pipe. This is
9731                  * fallout from our resume register restoring. Disable
9732                  * the encoder manually again. */
9733                 if (encoder->base.crtc) {
9734                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9735                                       encoder->base.base.id,
9736                                       drm_get_encoder_name(&encoder->base));
9737                         encoder->disable(encoder);
9738                 }
9739
9740                 /* Inconsistent output/port/pipe state happens presumably due to
9741                  * a bug in one of the get_hw_state functions. Or someplace else
9742                  * in our code, like the register restore mess on resume. Clamp
9743                  * things to off as a safer default. */
9744                 list_for_each_entry(connector,
9745                                     &dev->mode_config.connector_list,
9746                                     base.head) {
9747                         if (connector->encoder != encoder)
9748                                 continue;
9749
9750                         intel_connector_break_all_links(connector);
9751                 }
9752         }
9753         /* Enabled encoders without active connectors will be fixed in
9754          * the crtc fixup. */
9755 }
9756
9757 void i915_redisable_vga(struct drm_device *dev)
9758 {
9759         struct drm_i915_private *dev_priv = dev->dev_private;
9760         u32 vga_reg = i915_vgacntrl_reg(dev);
9761
9762         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9763                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9764                 i915_disable_vga(dev);
9765         }
9766 }
9767
9768 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9769 {
9770         struct drm_i915_private *dev_priv = dev->dev_private;
9771         enum pipe pipe;
9772         struct intel_crtc *crtc;
9773         struct intel_encoder *encoder;
9774         struct intel_connector *connector;
9775         int i;
9776
9777         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9778                             base.head) {
9779                 memset(&crtc->config, 0, sizeof(crtc->config));
9780
9781                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9782                                                                  &crtc->config);
9783
9784                 crtc->base.enabled = crtc->active;
9785
9786                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9787                               crtc->base.base.id,
9788                               crtc->active ? "enabled" : "disabled");
9789         }
9790
9791         /* FIXME: Smash this into the new shared dpll infrastructure. */
9792         if (HAS_DDI(dev))
9793                 intel_ddi_setup_hw_pll_state(dev);
9794
9795         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9796                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9797
9798                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9799                 pll->active = 0;
9800                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9801                                     base.head) {
9802                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9803                                 pll->active++;
9804                 }
9805                 pll->refcount = pll->active;
9806
9807                 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9808                               pll->name, pll->refcount);
9809         }
9810
9811         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9812                             base.head) {
9813                 pipe = 0;
9814
9815                 if (encoder->get_hw_state(encoder, &pipe)) {
9816                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9817                         encoder->base.crtc = &crtc->base;
9818                         if (encoder->get_config)
9819                                 encoder->get_config(encoder, &crtc->config);
9820                 } else {
9821                         encoder->base.crtc = NULL;
9822                 }
9823
9824                 encoder->connectors_active = false;
9825                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9826                               encoder->base.base.id,
9827                               drm_get_encoder_name(&encoder->base),
9828                               encoder->base.crtc ? "enabled" : "disabled",
9829                               pipe);
9830         }
9831
9832         list_for_each_entry(connector, &dev->mode_config.connector_list,
9833                             base.head) {
9834                 if (connector->get_hw_state(connector)) {
9835                         connector->base.dpms = DRM_MODE_DPMS_ON;
9836                         connector->encoder->connectors_active = true;
9837                         connector->base.encoder = &connector->encoder->base;
9838                 } else {
9839                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9840                         connector->base.encoder = NULL;
9841                 }
9842                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9843                               connector->base.base.id,
9844                               drm_get_connector_name(&connector->base),
9845                               connector->base.encoder ? "enabled" : "disabled");
9846         }
9847 }
9848
9849 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9850  * and i915 state tracking structures. */
9851 void intel_modeset_setup_hw_state(struct drm_device *dev,
9852                                   bool force_restore)
9853 {
9854         struct drm_i915_private *dev_priv = dev->dev_private;
9855         enum pipe pipe;
9856         struct drm_plane *plane;
9857         struct intel_crtc *crtc;
9858         struct intel_encoder *encoder;
9859
9860         intel_modeset_readout_hw_state(dev);
9861
9862         /* HW state is read out, now we need to sanitize this mess. */
9863         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9864                             base.head) {
9865                 intel_sanitize_encoder(encoder);
9866         }
9867
9868         for_each_pipe(pipe) {
9869                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9870                 intel_sanitize_crtc(crtc);
9871                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9872         }
9873
9874         if (force_restore) {
9875                 /*
9876                  * We need to use raw interfaces for restoring state to avoid
9877                  * checking (bogus) intermediate states.
9878                  */
9879                 for_each_pipe(pipe) {
9880                         struct drm_crtc *crtc =
9881                                 dev_priv->pipe_to_crtc_mapping[pipe];
9882
9883                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9884                                          crtc->fb);
9885                 }
9886                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9887                         intel_plane_restore(plane);
9888
9889                 i915_redisable_vga(dev);
9890         } else {
9891                 intel_modeset_update_staged_output_state(dev);
9892         }
9893
9894         intel_modeset_check_state(dev);
9895
9896         drm_mode_config_reset(dev);
9897 }
9898
9899 void intel_modeset_gem_init(struct drm_device *dev)
9900 {
9901         intel_modeset_init_hw(dev);
9902
9903         intel_setup_overlay(dev);
9904
9905         intel_modeset_setup_hw_state(dev, false);
9906 }
9907
9908 void intel_modeset_cleanup(struct drm_device *dev)
9909 {
9910         struct drm_i915_private *dev_priv = dev->dev_private;
9911         struct drm_crtc *crtc;
9912         struct intel_crtc *intel_crtc;
9913
9914         /*
9915          * Interrupts and polling as the first thing to avoid creating havoc.
9916          * Too much stuff here (turning of rps, connectors, ...) would
9917          * experience fancy races otherwise.
9918          */
9919         drm_irq_uninstall(dev);
9920         cancel_work_sync(&dev_priv->hotplug_work);
9921         /*
9922          * Due to the hpd irq storm handling the hotplug work can re-arm the
9923          * poll handlers. Hence disable polling after hpd handling is shut down.
9924          */
9925         drm_kms_helper_poll_fini(dev);
9926
9927         mutex_lock(&dev->struct_mutex);
9928
9929         intel_unregister_dsm_handler();
9930
9931         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9932                 /* Skip inactive CRTCs */
9933                 if (!crtc->fb)
9934                         continue;
9935
9936                 intel_crtc = to_intel_crtc(crtc);
9937                 intel_increase_pllclock(crtc);
9938         }
9939
9940         intel_disable_fbc(dev);
9941
9942         intel_disable_gt_powersave(dev);
9943
9944         ironlake_teardown_rc6(dev);
9945
9946         mutex_unlock(&dev->struct_mutex);
9947
9948         /* flush any delayed tasks or pending work */
9949         flush_scheduled_work();
9950
9951         /* destroy backlight, if any, before the connectors */
9952         intel_panel_destroy_backlight(dev);
9953
9954         drm_mode_config_cleanup(dev);
9955
9956         intel_cleanup_overlay(dev);
9957 }
9958
9959 /*
9960  * Return which encoder is currently attached for connector.
9961  */
9962 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9963 {
9964         return &intel_attached_encoder(connector)->base;
9965 }
9966
9967 void intel_connector_attach_encoder(struct intel_connector *connector,
9968                                     struct intel_encoder *encoder)
9969 {
9970         connector->encoder = encoder;
9971         drm_mode_connector_attach_encoder(&connector->base,
9972                                           &encoder->base);
9973 }
9974
9975 /*
9976  * set vga decode state - true == enable VGA decode
9977  */
9978 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9979 {
9980         struct drm_i915_private *dev_priv = dev->dev_private;
9981         u16 gmch_ctrl;
9982
9983         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9984         if (state)
9985                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9986         else
9987                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9988         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9989         return 0;
9990 }
9991
9992 #ifdef CONFIG_DEBUG_FS
9993 #include <linux/seq_file.h>
9994
9995 struct intel_display_error_state {
9996
9997         u32 power_well_driver;
9998
9999         struct intel_cursor_error_state {
10000                 u32 control;
10001                 u32 position;
10002                 u32 base;
10003                 u32 size;
10004         } cursor[I915_MAX_PIPES];
10005
10006         struct intel_pipe_error_state {
10007                 enum transcoder cpu_transcoder;
10008                 u32 conf;
10009                 u32 source;
10010
10011                 u32 htotal;
10012                 u32 hblank;
10013                 u32 hsync;
10014                 u32 vtotal;
10015                 u32 vblank;
10016                 u32 vsync;
10017         } pipe[I915_MAX_PIPES];
10018
10019         struct intel_plane_error_state {
10020                 u32 control;
10021                 u32 stride;
10022                 u32 size;
10023                 u32 pos;
10024                 u32 addr;
10025                 u32 surface;
10026                 u32 tile_offset;
10027         } plane[I915_MAX_PIPES];
10028 };
10029
10030 struct intel_display_error_state *
10031 intel_display_capture_error_state(struct drm_device *dev)
10032 {
10033         drm_i915_private_t *dev_priv = dev->dev_private;
10034         struct intel_display_error_state *error;
10035         enum transcoder cpu_transcoder;
10036         int i;
10037
10038         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10039         if (error == NULL)
10040                 return NULL;
10041
10042         if (HAS_POWER_WELL(dev))
10043                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10044
10045         for_each_pipe(i) {
10046                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
10047                 error->pipe[i].cpu_transcoder = cpu_transcoder;
10048
10049                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10050                         error->cursor[i].control = I915_READ(CURCNTR(i));
10051                         error->cursor[i].position = I915_READ(CURPOS(i));
10052                         error->cursor[i].base = I915_READ(CURBASE(i));
10053                 } else {
10054                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10055                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10056                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10057                 }
10058
10059                 error->plane[i].control = I915_READ(DSPCNTR(i));
10060                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10061                 if (INTEL_INFO(dev)->gen <= 3) {
10062                         error->plane[i].size = I915_READ(DSPSIZE(i));
10063                         error->plane[i].pos = I915_READ(DSPPOS(i));
10064                 }
10065                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10066                         error->plane[i].addr = I915_READ(DSPADDR(i));
10067                 if (INTEL_INFO(dev)->gen >= 4) {
10068                         error->plane[i].surface = I915_READ(DSPSURF(i));
10069                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10070                 }
10071
10072                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10073                 error->pipe[i].source = I915_READ(PIPESRC(i));
10074                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10075                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10076                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10077                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10078                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10079                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10080         }
10081
10082         /* In the code above we read the registers without checking if the power
10083          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10084          * prevent the next I915_WRITE from detecting it and printing an error
10085          * message. */
10086         if (HAS_POWER_WELL(dev))
10087                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10088
10089         return error;
10090 }
10091
10092 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10093
10094 void
10095 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10096                                 struct drm_device *dev,
10097                                 struct intel_display_error_state *error)
10098 {
10099         int i;
10100
10101         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10102         if (HAS_POWER_WELL(dev))
10103                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10104                            error->power_well_driver);
10105         for_each_pipe(i) {
10106                 err_printf(m, "Pipe [%d]:\n", i);
10107                 err_printf(m, "  CPU transcoder: %c\n",
10108                            transcoder_name(error->pipe[i].cpu_transcoder));
10109                 err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10110                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10111                 err_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
10112                 err_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
10113                 err_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
10114                 err_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
10115                 err_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
10116                 err_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
10117
10118                 err_printf(m, "Plane [%d]:\n", i);
10119                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10120                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10121                 if (INTEL_INFO(dev)->gen <= 3) {
10122                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10123                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10124                 }
10125                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10126                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10127                 if (INTEL_INFO(dev)->gen >= 4) {
10128                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10129                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10130                 }
10131
10132                 err_printf(m, "Cursor [%d]:\n", i);
10133                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10134                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10135                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10136         }
10137 }
10138 #endif