Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  49                                 struct intel_crtc_config *pipe_config);
  50 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  51                                     struct intel_crtc_config *pipe_config);
  52
  53 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  54                           int x, int y, struct drm_framebuffer *old_fb);
  55
  56
  57 typedef struct {
  58         int     min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62         int     dot_limit;
  63         int     p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 typedef struct intel_limit intel_limit_t;
  67 struct intel_limit {
  68         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  69         intel_p2_t          p2;
  70 };
  71
  72 /* FDI */
  73 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  74
  75 int
  76 intel_pch_rawclk(struct drm_device *dev)
  77 {
  78         struct drm_i915_private *dev_priv = dev->dev_private;
  79
  80         WARN_ON(!HAS_PCH_SPLIT(dev));
  81
  82         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  83 }
  84
  85 static inline u32 /* units of 100MHz */
  86 intel_fdi_link_freq(struct drm_device *dev)
  87 {
  88         if (IS_GEN5(dev)) {
  89                 struct drm_i915_private *dev_priv = dev->dev_private;
  90                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  91         } else
  92                 return 27;
  93 }
  94
  95 static const intel_limit_t intel_limits_i8xx_dac = {
  96         .dot = { .min = 25000, .max = 350000 },
  97         .vco = { .min = 930000, .max = 1400000 },
  98         .n = { .min = 3, .max = 16 },
  99         .m = { .min = 96, .max = 140 },
 100         .m1 = { .min = 18, .max = 26 },
 101         .m2 = { .min = 6, .max = 16 },
 102         .p = { .min = 4, .max = 128 },
 103         .p1 = { .min = 2, .max = 33 },
 104         .p2 = { .dot_limit = 165000,
 105                 .p2_slow = 4, .p2_fast = 2 },
 106 };
 107
 108 static const intel_limit_t intel_limits_i8xx_dvo = {
 109         .dot = { .min = 25000, .max = 350000 },
 110         .vco = { .min = 930000, .max = 1400000 },
 111         .n = { .min = 3, .max = 16 },
 112         .m = { .min = 96, .max = 140 },
 113         .m1 = { .min = 18, .max = 26 },
 114         .m2 = { .min = 6, .max = 16 },
 115         .p = { .min = 4, .max = 128 },
 116         .p1 = { .min = 2, .max = 33 },
 117         .p2 = { .dot_limit = 165000,
 118                 .p2_slow = 4, .p2_fast = 4 },
 119 };
 120
 121 static const intel_limit_t intel_limits_i8xx_lvds = {
 122         .dot = { .min = 25000, .max = 350000 },
 123         .vco = { .min = 930000, .max = 1400000 },
 124         .n = { .min = 3, .max = 16 },
 125         .m = { .min = 96, .max = 140 },
 126         .m1 = { .min = 18, .max = 26 },
 127         .m2 = { .min = 6, .max = 16 },
 128         .p = { .min = 4, .max = 128 },
 129         .p1 = { .min = 1, .max = 6 },
 130         .p2 = { .dot_limit = 165000,
 131                 .p2_slow = 14, .p2_fast = 7 },
 132 };
 133
 134 static const intel_limit_t intel_limits_i9xx_sdvo = {
 135         .dot = { .min = 20000, .max = 400000 },
 136         .vco = { .min = 1400000, .max = 2800000 },
 137         .n = { .min = 1, .max = 6 },
 138         .m = { .min = 70, .max = 120 },
 139         .m1 = { .min = 8, .max = 18 },
 140         .m2 = { .min = 3, .max = 7 },
 141         .p = { .min = 5, .max = 80 },
 142         .p1 = { .min = 1, .max = 8 },
 143         .p2 = { .dot_limit = 200000,
 144                 .p2_slow = 10, .p2_fast = 5 },
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_lvds = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 7, .max = 98 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 112000,
 157                 .p2_slow = 14, .p2_fast = 7 },
 158 };
 159
 160
 161 static const intel_limit_t intel_limits_g4x_sdvo = {
 162         .dot = { .min = 25000, .max = 270000 },
 163         .vco = { .min = 1750000, .max = 3500000},
 164         .n = { .min = 1, .max = 4 },
 165         .m = { .min = 104, .max = 138 },
 166         .m1 = { .min = 17, .max = 23 },
 167         .m2 = { .min = 5, .max = 11 },
 168         .p = { .min = 10, .max = 30 },
 169         .p1 = { .min = 1, .max = 3},
 170         .p2 = { .dot_limit = 270000,
 171                 .p2_slow = 10,
 172                 .p2_fast = 10
 173         },
 174 };
 175
 176 static const intel_limit_t intel_limits_g4x_hdmi = {
 177         .dot = { .min = 22000, .max = 400000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 16, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 5, .max = 80 },
 184         .p1 = { .min = 1, .max = 8},
 185         .p2 = { .dot_limit = 165000,
 186                 .p2_slow = 10, .p2_fast = 5 },
 187 };
 188
 189 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 190         .dot = { .min = 20000, .max = 115000 },
 191         .vco = { .min = 1750000, .max = 3500000 },
 192         .n = { .min = 1, .max = 3 },
 193         .m = { .min = 104, .max = 138 },
 194         .m1 = { .min = 17, .max = 23 },
 195         .m2 = { .min = 5, .max = 11 },
 196         .p = { .min = 28, .max = 112 },
 197         .p1 = { .min = 2, .max = 8 },
 198         .p2 = { .dot_limit = 0,
 199                 .p2_slow = 14, .p2_fast = 14
 200         },
 201 };
 202
 203 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 204         .dot = { .min = 80000, .max = 224000 },
 205         .vco = { .min = 1750000, .max = 3500000 },
 206         .n = { .min = 1, .max = 3 },
 207         .m = { .min = 104, .max = 138 },
 208         .m1 = { .min = 17, .max = 23 },
 209         .m2 = { .min = 5, .max = 11 },
 210         .p = { .min = 14, .max = 42 },
 211         .p1 = { .min = 2, .max = 6 },
 212         .p2 = { .dot_limit = 0,
 213                 .p2_slow = 7, .p2_fast = 7
 214         },
 215 };
 216
 217 static const intel_limit_t intel_limits_pineview_sdvo = {
 218         .dot = { .min = 20000, .max = 400000},
 219         .vco = { .min = 1700000, .max = 3500000 },
 220         /* Pineview's Ncounter is a ring counter */
 221         .n = { .min = 3, .max = 6 },
 222         .m = { .min = 2, .max = 256 },
 223         /* Pineview only has one combined m divider, which we treat as m2. */
 224         .m1 = { .min = 0, .max = 0 },
 225         .m2 = { .min = 0, .max = 254 },
 226         .p = { .min = 5, .max = 80 },
 227         .p1 = { .min = 1, .max = 8 },
 228         .p2 = { .dot_limit = 200000,
 229                 .p2_slow = 10, .p2_fast = 5 },
 230 };
 231
 232 static const intel_limit_t intel_limits_pineview_lvds = {
 233         .dot = { .min = 20000, .max = 400000 },
 234         .vco = { .min = 1700000, .max = 3500000 },
 235         .n = { .min = 3, .max = 6 },
 236         .m = { .min = 2, .max = 256 },
 237         .m1 = { .min = 0, .max = 0 },
 238         .m2 = { .min = 0, .max = 254 },
 239         .p = { .min = 7, .max = 112 },
 240         .p1 = { .min = 1, .max = 8 },
 241         .p2 = { .dot_limit = 112000,
 242                 .p2_slow = 14, .p2_fast = 14 },
 243 };
 244
 245 /* Ironlake / Sandybridge
 246  *
 247  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 248  * the range value for them is (actual_value - 2).
 249  */
 250 static const intel_limit_t intel_limits_ironlake_dac = {
 251         .dot = { .min = 25000, .max = 350000 },
 252         .vco = { .min = 1760000, .max = 3510000 },
 253         .n = { .min = 1, .max = 5 },
 254         .m = { .min = 79, .max = 127 },
 255         .m1 = { .min = 12, .max = 22 },
 256         .m2 = { .min = 5, .max = 9 },
 257         .p = { .min = 5, .max = 80 },
 258         .p1 = { .min = 1, .max = 8 },
 259         .p2 = { .dot_limit = 225000,
 260                 .p2_slow = 10, .p2_fast = 5 },
 261 };
 262
 263 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 264         .dot = { .min = 25000, .max = 350000 },
 265         .vco = { .min = 1760000, .max = 3510000 },
 266         .n = { .min = 1, .max = 3 },
 267         .m = { .min = 79, .max = 118 },
 268         .m1 = { .min = 12, .max = 22 },
 269         .m2 = { .min = 5, .max = 9 },
 270         .p = { .min = 28, .max = 112 },
 271         .p1 = { .min = 2, .max = 8 },
 272         .p2 = { .dot_limit = 225000,
 273                 .p2_slow = 14, .p2_fast = 14 },
 274 };
 275
 276 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 277         .dot = { .min = 25000, .max = 350000 },
 278         .vco = { .min = 1760000, .max = 3510000 },
 279         .n = { .min = 1, .max = 3 },
 280         .m = { .min = 79, .max = 127 },
 281         .m1 = { .min = 12, .max = 22 },
 282         .m2 = { .min = 5, .max = 9 },
 283         .p = { .min = 14, .max = 56 },
 284         .p1 = { .min = 2, .max = 8 },
 285         .p2 = { .dot_limit = 225000,
 286                 .p2_slow = 7, .p2_fast = 7 },
 287 };
 288
 289 /* LVDS 100mhz refclk limits. */
 290 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 2 },
 294         .m = { .min = 79, .max = 126 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 28, .max = 112 },
 298         .p1 = { .min = 2, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 14, .p2_fast = 14 },
 301 };
 302
 303 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 304         .dot = { .min = 25000, .max = 350000 },
 305         .vco = { .min = 1760000, .max = 3510000 },
 306         .n = { .min = 1, .max = 3 },
 307         .m = { .min = 79, .max = 126 },
 308         .m1 = { .min = 12, .max = 22 },
 309         .m2 = { .min = 5, .max = 9 },
 310         .p = { .min = 14, .max = 42 },
 311         .p1 = { .min = 2, .max = 6 },
 312         .p2 = { .dot_limit = 225000,
 313                 .p2_slow = 7, .p2_fast = 7 },
 314 };
 315
 316 static const intel_limit_t intel_limits_vlv_dac = {
 317         .dot = { .min = 25000, .max = 270000 },
 318         .vco = { .min = 4000000, .max = 6000000 },
 319         .n = { .min = 1, .max = 7 },
 320         .m = { .min = 22, .max = 450 }, /* guess */
 321         .m1 = { .min = 2, .max = 3 },
 322         .m2 = { .min = 11, .max = 156 },
 323         .p = { .min = 10, .max = 30 },
 324         .p1 = { .min = 1, .max = 3 },
 325         .p2 = { .dot_limit = 270000,
 326                 .p2_slow = 2, .p2_fast = 20 },
 327 };
 328
 329 static const intel_limit_t intel_limits_vlv_hdmi = {
 330         .dot = { .min = 25000, .max = 270000 },
 331         .vco = { .min = 4000000, .max = 6000000 },
 332         .n = { .min = 1, .max = 7 },
 333         .m = { .min = 60, .max = 300 }, /* guess */
 334         .m1 = { .min = 2, .max = 3 },
 335         .m2 = { .min = 11, .max = 156 },
 336         .p = { .min = 10, .max = 30 },
 337         .p1 = { .min = 2, .max = 3 },
 338         .p2 = { .dot_limit = 270000,
 339                 .p2_slow = 2, .p2_fast = 20 },
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dp = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 },
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353 };
 354
 355 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 356                                                 int refclk)
 357 {
 358         struct drm_device *dev = crtc->dev;
 359         const intel_limit_t *limit;
 360
 361         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 362                 if (intel_is_dual_link_lvds(dev)) {
 363                         if (refclk == 100000)
 364                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 365                         else
 366                                 limit = &intel_limits_ironlake_dual_lvds;
 367                 } else {
 368                         if (refclk == 100000)
 369                                 limit = &intel_limits_ironlake_single_lvds_100m;
 370                         else
 371                                 limit = &intel_limits_ironlake_single_lvds;
 372                 }
 373         } else
 374                 limit = &intel_limits_ironlake_dac;
 375
 376         return limit;
 377 }
 378
 379 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 380 {
 381         struct drm_device *dev = crtc->dev;
 382         const intel_limit_t *limit;
 383
 384         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 385                 if (intel_is_dual_link_lvds(dev))
 386                         limit = &intel_limits_g4x_dual_channel_lvds;
 387                 else
 388                         limit = &intel_limits_g4x_single_channel_lvds;
 389         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 390                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 391                 limit = &intel_limits_g4x_hdmi;
 392         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 393                 limit = &intel_limits_g4x_sdvo;
 394         } else /* The option is for other outputs */
 395                 limit = &intel_limits_i9xx_sdvo;
 396
 397         return limit;
 398 }
 399
 400 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 401 {
 402         struct drm_device *dev = crtc->dev;
 403         const intel_limit_t *limit;
 404
 405         if (HAS_PCH_SPLIT(dev))
 406                 limit = intel_ironlake_limit(crtc, refclk);
 407         else if (IS_G4X(dev)) {
 408                 limit = intel_g4x_limit(crtc);
 409         } else if (IS_PINEVIEW(dev)) {
 410                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 411                         limit = &intel_limits_pineview_lvds;
 412                 else
 413                         limit = &intel_limits_pineview_sdvo;
 414         } else if (IS_VALLEYVIEW(dev)) {
 415                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 416                         limit = &intel_limits_vlv_dac;
 417                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 418                         limit = &intel_limits_vlv_hdmi;
 419                 else
 420                         limit = &intel_limits_vlv_dp;
 421         } else if (!IS_GEN2(dev)) {
 422                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 423                         limit = &intel_limits_i9xx_lvds;
 424                 else
 425                         limit = &intel_limits_i9xx_sdvo;
 426         } else {
 427                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 428                         limit = &intel_limits_i8xx_lvds;
 429                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 430                         limit = &intel_limits_i8xx_dvo;
 431                 else
 432                         limit = &intel_limits_i8xx_dac;
 433         }
 434         return limit;
 435 }
 436
 437 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 438 static void pineview_clock(int refclk, intel_clock_t *clock)
 439 {
 440         clock->m = clock->m2 + 2;
 441         clock->p = clock->p1 * clock->p2;
 442         clock->vco = refclk * clock->m / clock->n;
 443         clock->dot = clock->vco / clock->p;
 444 }
 445
 446 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 447 {
 448         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 449 }
 450
 451 static void i9xx_clock(int refclk, intel_clock_t *clock)
 452 {
 453         clock->m = i9xx_dpll_compute_m(clock);
 454         clock->p = clock->p1 * clock->p2;
 455         clock->vco = refclk * clock->m / (clock->n + 2);
 456         clock->dot = clock->vco / clock->p;
 457 }
 458
 459 /**
 460  * Returns whether any output on the specified pipe is of the specified type
 461  */
 462 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 463 {
 464         struct drm_device *dev = crtc->dev;
 465         struct intel_encoder *encoder;
 466
 467         for_each_encoder_on_crtc(dev, crtc, encoder)
 468                 if (encoder->type == type)
 469                         return true;
 470
 471         return false;
 472 }
 473
 474 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 475 /**
 476  * Returns whether the given set of divisors are valid for a given refclk with
 477  * the given connectors.
 478  */
 479
 480 static bool intel_PLL_is_valid(struct drm_device *dev,
 481                                const intel_limit_t *limit,
 482                                const intel_clock_t *clock)
 483 {
 484         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 485                 INTELPllInvalid("p1 out of range\n");
 486         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 487                 INTELPllInvalid("p out of range\n");
 488         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 489                 INTELPllInvalid("m2 out of range\n");
 490         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 491                 INTELPllInvalid("m1 out of range\n");
 492         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 493                 INTELPllInvalid("m1 <= m2\n");
 494         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 495                 INTELPllInvalid("m out of range\n");
 496         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 497                 INTELPllInvalid("n out of range\n");
 498         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 499                 INTELPllInvalid("vco out of range\n");
 500         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 501          * connector, etc., rather than just a single range.
 502          */
 503         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 504                 INTELPllInvalid("dot out of range\n");
 505
 506         return true;
 507 }
 508
 509 static bool
 510 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 511                     int target, int refclk, intel_clock_t *match_clock,
 512                     intel_clock_t *best_clock)
 513 {
 514         struct drm_device *dev = crtc->dev;
 515         intel_clock_t clock;
 516         int err = target;
 517
 518         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 519                 /*
 520                  * For LVDS just rely on its current settings for dual-channel.
 521                  * We haven't figured out how to reliably set up different
 522                  * single/dual channel state, if we even can.
 523                  */
 524                 if (intel_is_dual_link_lvds(dev))
 525                         clock.p2 = limit->p2.p2_fast;
 526                 else
 527                         clock.p2 = limit->p2.p2_slow;
 528         } else {
 529                 if (target < limit->p2.dot_limit)
 530                         clock.p2 = limit->p2.p2_slow;
 531                 else
 532                         clock.p2 = limit->p2.p2_fast;
 533         }
 534
 535         memset(best_clock, 0, sizeof(*best_clock));
 536
 537         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 538              clock.m1++) {
 539                 for (clock.m2 = limit->m2.min;
 540                      clock.m2 <= limit->m2.max; clock.m2++) {
 541                         if (clock.m2 >= clock.m1)
 542                                 break;
 543                         for (clock.n = limit->n.min;
 544                              clock.n <= limit->n.max; clock.n++) {
 545                                 for (clock.p1 = limit->p1.min;
 546                                         clock.p1 <= limit->p1.max; clock.p1++) {
 547                                         int this_err;
 548
 549                                         i9xx_clock(refclk, &clock);
 550                                         if (!intel_PLL_is_valid(dev, limit,
 551                                                                 &clock))
 552                                                 continue;
 553                                         if (match_clock &&
 554                                             clock.p != match_clock->p)
 555                                                 continue;
 556
 557                                         this_err = abs(clock.dot - target);
 558                                         if (this_err < err) {
 559                                                 *best_clock = clock;
 560                                                 err = this_err;
 561                                         }
 562                                 }
 563                         }
 564                 }
 565         }
 566
 567         return (err != target);
 568 }
 569
 570 static bool
 571 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 572                    int target, int refclk, intel_clock_t *match_clock,
 573                    intel_clock_t *best_clock)
 574 {
 575         struct drm_device *dev = crtc->dev;
 576         intel_clock_t clock;
 577         int err = target;
 578
 579         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 580                 /*
 581                  * For LVDS just rely on its current settings for dual-channel.
 582                  * We haven't figured out how to reliably set up different
 583                  * single/dual channel state, if we even can.
 584                  */
 585                 if (intel_is_dual_link_lvds(dev))
 586                         clock.p2 = limit->p2.p2_fast;
 587                 else
 588                         clock.p2 = limit->p2.p2_slow;
 589         } else {
 590                 if (target < limit->p2.dot_limit)
 591                         clock.p2 = limit->p2.p2_slow;
 592                 else
 593                         clock.p2 = limit->p2.p2_fast;
 594         }
 595
 596         memset(best_clock, 0, sizeof(*best_clock));
 597
 598         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 599              clock.m1++) {
 600                 for (clock.m2 = limit->m2.min;
 601                      clock.m2 <= limit->m2.max; clock.m2++) {
 602                         for (clock.n = limit->n.min;
 603                              clock.n <= limit->n.max; clock.n++) {
 604                                 for (clock.p1 = limit->p1.min;
 605                                         clock.p1 <= limit->p1.max; clock.p1++) {
 606                                         int this_err;
 607
 608                                         pineview_clock(refclk, &clock);
 609                                         if (!intel_PLL_is_valid(dev, limit,
 610                                                                 &clock))
 611                                                 continue;
 612                                         if (match_clock &&
 613                                             clock.p != match_clock->p)
 614                                                 continue;
 615
 616                                         this_err = abs(clock.dot - target);
 617                                         if (this_err < err) {
 618                                                 *best_clock = clock;
 619                                                 err = this_err;
 620                                         }
 621                                 }
 622                         }
 623                 }
 624         }
 625
 626         return (err != target);
 627 }
 628
 629 static bool
 630 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 631                    int target, int refclk, intel_clock_t *match_clock,
 632                    intel_clock_t *best_clock)
 633 {
 634         struct drm_device *dev = crtc->dev;
 635         intel_clock_t clock;
 636         int max_n;
 637         bool found;
 638         /* approximately equals target * 0.00585 */
 639         int err_most = (target >> 8) + (target >> 9);
 640         found = false;
 641
 642         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 643                 if (intel_is_dual_link_lvds(dev))
 644                         clock.p2 = limit->p2.p2_fast;
 645                 else
 646                         clock.p2 = limit->p2.p2_slow;
 647         } else {
 648                 if (target < limit->p2.dot_limit)
 649                         clock.p2 = limit->p2.p2_slow;
 650                 else
 651                         clock.p2 = limit->p2.p2_fast;
 652         }
 653
 654         memset(best_clock, 0, sizeof(*best_clock));
 655         max_n = limit->n.max;
 656         /* based on hardware requirement, prefer smaller n to precision */
 657         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 658                 /* based on hardware requirement, prefere larger m1,m2 */
 659                 for (clock.m1 = limit->m1.max;
 660                      clock.m1 >= limit->m1.min; clock.m1--) {
 661                         for (clock.m2 = limit->m2.max;
 662                              clock.m2 >= limit->m2.min; clock.m2--) {
 663                                 for (clock.p1 = limit->p1.max;
 664                                      clock.p1 >= limit->p1.min; clock.p1--) {
 665                                         int this_err;
 666
 667                                         i9xx_clock(refclk, &clock);
 668                                         if (!intel_PLL_is_valid(dev, limit,
 669                                                                 &clock))
 670                                                 continue;
 671
 672                                         this_err = abs(clock.dot - target);
 673                                         if (this_err < err_most) {
 674                                                 *best_clock = clock;
 675                                                 err_most = this_err;
 676                                                 max_n = clock.n;
 677                                                 found = true;
 678                                         }
 679                                 }
 680                         }
 681                 }
 682         }
 683         return found;
 684 }
 685
 686 static bool
 687 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 688                    int target, int refclk, intel_clock_t *match_clock,
 689                    intel_clock_t *best_clock)
 690 {
 691         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 692         u32 m, n, fastclk;
 693         u32 updrate, minupdate, p;
 694         unsigned long bestppm, ppm, absppm;
 695         int dotclk, flag;
 696
 697         flag = 0;
 698         dotclk = target * 1000;
 699         bestppm = 1000000;
 700         ppm = absppm = 0;
 701         fastclk = dotclk / (2*100);
 702         updrate = 0;
 703         minupdate = 19200;
 704         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 705         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 706
 707         /* based on hardware requirement, prefer smaller n to precision */
 708         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 709                 updrate = refclk / n;
 710                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 711                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 712                                 if (p2 > 10)
 713                                         p2 = p2 - 1;
 714                                 p = p1 * p2;
 715                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 716                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 717                                         m2 = (((2*(fastclk * p * n / m1 )) +
 718                                                refclk) / (2*refclk));
 719                                         m = m1 * m2;
 720                                         vco = updrate * m;
 721                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 722                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 723                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 724                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 725                                                         bestppm = 0;
 726                                                         flag = 1;
 727                                                 }
 728                                                 if (absppm < bestppm - 10) {
 729                                                         bestppm = absppm;
 730                                                         flag = 1;
 731                                                 }
 732                                                 if (flag) {
 733                                                         bestn = n;
 734                                                         bestm1 = m1;
 735                                                         bestm2 = m2;
 736                                                         bestp1 = p1;
 737                                                         bestp2 = p2;
 738                                                         flag = 0;
 739                                                 }
 740                                         }
 741                                 }
 742                         }
 743                 }
 744         }
 745         best_clock->n = bestn;
 746         best_clock->m1 = bestm1;
 747         best_clock->m2 = bestm2;
 748         best_clock->p1 = bestp1;
 749         best_clock->p2 = bestp2;
 750
 751         return true;
 752 }
 753
 754 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 755                                              enum pipe pipe)
 756 {
 757         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 759
 760         return intel_crtc->config.cpu_transcoder;
 761 }
 762
 763 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 764 {
 765         struct drm_i915_private *dev_priv = dev->dev_private;
 766         u32 frame, frame_reg = PIPEFRAME(pipe);
 767
 768         frame = I915_READ(frame_reg);
 769
 770         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 771                 DRM_DEBUG_KMS("vblank wait timed out\n");
 772 }
 773
 774 /**
 775  * intel_wait_for_vblank - wait for vblank on a given pipe
 776  * @dev: drm device
 777  * @pipe: pipe to wait for
 778  *
 779  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 780  * mode setting code.
 781  */
 782 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 783 {
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         int pipestat_reg = PIPESTAT(pipe);
 786
 787         if (INTEL_INFO(dev)->gen >= 5) {
 788                 ironlake_wait_for_vblank(dev, pipe);
 789                 return;
 790         }
 791
 792         /* Clear existing vblank status. Note this will clear any other
 793          * sticky status fields as well.
 794          *
 795          * This races with i915_driver_irq_handler() with the result
 796          * that either function could miss a vblank event.  Here it is not
 797          * fatal, as we will either wait upon the next vblank interrupt or
 798          * timeout.  Generally speaking intel_wait_for_vblank() is only
 799          * called during modeset at which time the GPU should be idle and
 800          * should *not* be performing page flips and thus not waiting on
 801          * vblanks...
 802          * Currently, the result of us stealing a vblank from the irq
 803          * handler is that a single frame will be skipped during swapbuffers.
 804          */
 805         I915_WRITE(pipestat_reg,
 806                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 807
 808         /* Wait for vblank interrupt bit to set */
 809         if (wait_for(I915_READ(pipestat_reg) &
 810                      PIPE_VBLANK_INTERRUPT_STATUS,
 811                      50))
 812                 DRM_DEBUG_KMS("vblank wait timed out\n");
 813 }
 814
 815 /*
 816  * intel_wait_for_pipe_off - wait for pipe to turn off
 817  * @dev: drm device
 818  * @pipe: pipe to wait for
 819  *
 820  * After disabling a pipe, we can't wait for vblank in the usual way,
 821  * spinning on the vblank interrupt status bit, since we won't actually
 822  * see an interrupt when the pipe is disabled.
 823  *
 824  * On Gen4 and above:
 825  *   wait for the pipe register state bit to turn off
 826  *
 827  * Otherwise:
 828  *   wait for the display line value to settle (it usually
 829  *   ends up stopping at the start of the next frame).
 830  *
 831  */
 832 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 833 {
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 836                                                                       pipe);
 837
 838         if (INTEL_INFO(dev)->gen >= 4) {
 839                 int reg = PIPECONF(cpu_transcoder);
 840
 841                 /* Wait for the Pipe State to go off */
 842                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 843                              100))
 844                         WARN(1, "pipe_off wait timed out\n");
 845         } else {
 846                 u32 last_line, line_mask;
 847                 int reg = PIPEDSL(pipe);
 848                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 849
 850                 if (IS_GEN2(dev))
 851                         line_mask = DSL_LINEMASK_GEN2;
 852                 else
 853                         line_mask = DSL_LINEMASK_GEN3;
 854
 855                 /* Wait for the display line to settle */
 856                 do {
 857                         last_line = I915_READ(reg) & line_mask;
 858                         mdelay(5);
 859                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 860                          time_after(timeout, jiffies));
 861                 if (time_after(jiffies, timeout))
 862                         WARN(1, "pipe_off wait timed out\n");
 863         }
 864 }
 865
 866 /*
 867  * ibx_digital_port_connected - is the specified port connected?
 868  * @dev_priv: i915 private structure
 869  * @port: the port to test
 870  *
 871  * Returns true if @port is connected, false otherwise.
 872  */
 873 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 874                                 struct intel_digital_port *port)
 875 {
 876         u32 bit;
 877
 878         if (HAS_PCH_IBX(dev_priv->dev)) {
 879                 switch(port->port) {
 880                 case PORT_B:
 881                         bit = SDE_PORTB_HOTPLUG;
 882                         break;
 883                 case PORT_C:
 884                         bit = SDE_PORTC_HOTPLUG;
 885                         break;
 886                 case PORT_D:
 887                         bit = SDE_PORTD_HOTPLUG;
 888                         break;
 889                 default:
 890                         return true;
 891                 }
 892         } else {
 893                 switch(port->port) {
 894                 case PORT_B:
 895                         bit = SDE_PORTB_HOTPLUG_CPT;
 896                         break;
 897                 case PORT_C:
 898                         bit = SDE_PORTC_HOTPLUG_CPT;
 899                         break;
 900                 case PORT_D:
 901                         bit = SDE_PORTD_HOTPLUG_CPT;
 902                         break;
 903                 default:
 904                         return true;
 905                 }
 906         }
 907
 908         return I915_READ(SDEISR) & bit;
 909 }
 910
 911 static const char *state_string(bool enabled)
 912 {
 913         return enabled ? "on" : "off";
 914 }
 915
 916 /* Only for pre-ILK configs */
 917 void assert_pll(struct drm_i915_private *dev_priv,
 918                 enum pipe pipe, bool state)
 919 {
 920         int reg;
 921         u32 val;
 922         bool cur_state;
 923
 924         reg = DPLL(pipe);
 925         val = I915_READ(reg);
 926         cur_state = !!(val & DPLL_VCO_ENABLE);
 927         WARN(cur_state != state,
 928              "PLL state assertion failure (expected %s, current %s)\n",
 929              state_string(state), state_string(cur_state));
 930 }
 931
 932 /* XXX: the dsi pll is shared between MIPI DSI ports */
 933 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 934 {
 935         u32 val;
 936         bool cur_state;
 937
 938         mutex_lock(&dev_priv->dpio_lock);
 939         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 940         mutex_unlock(&dev_priv->dpio_lock);
 941
 942         cur_state = val & DSI_PLL_VCO_EN;
 943         WARN(cur_state != state,
 944              "DSI PLL state assertion failure (expected %s, current %s)\n",
 945              state_string(state), state_string(cur_state));
 946 }
 947 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 948 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 949
 950 struct intel_shared_dpll *
 951 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 952 {
 953         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 954
 955         if (crtc->config.shared_dpll < 0)
 956                 return NULL;
 957
 958         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 959 }
 960
 961 /* For ILK+ */
 962 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 963                         struct intel_shared_dpll *pll,
 964                         bool state)
 965 {
 966         bool cur_state;
 967         struct intel_dpll_hw_state hw_state;
 968
 969         if (HAS_PCH_LPT(dev_priv->dev)) {
 970                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 971                 return;
 972         }
 973
 974         if (WARN (!pll,
 975                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 976                 return;
 977
 978         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 979         WARN(cur_state != state,
 980              "%s assertion failure (expected %s, current %s)\n",
 981              pll->name, state_string(state), state_string(cur_state));
 982 }
 983
 984 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 985                           enum pipe pipe, bool state)
 986 {
 987         int reg;
 988         u32 val;
 989         bool cur_state;
 990         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 991                                                                       pipe);
 992
 993         if (HAS_DDI(dev_priv->dev)) {
 994                 /* DDI does not have a specific FDI_TX register */
 995                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 996                 val = I915_READ(reg);
 997                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 998         } else {
 999                 reg = FDI_TX_CTL(pipe);
1000                 val = I915_READ(reg);
1001                 cur_state = !!(val & FDI_TX_ENABLE);
1002         }
1003         WARN(cur_state != state,
1004              "FDI TX state assertion failure (expected %s, current %s)\n",
1005              state_string(state), state_string(cur_state));
1006 }
1007 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1008 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009
1010 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1011                           enum pipe pipe, bool state)
1012 {
1013         int reg;
1014         u32 val;
1015         bool cur_state;
1016
1017         reg = FDI_RX_CTL(pipe);
1018         val = I915_READ(reg);
1019         cur_state = !!(val & FDI_RX_ENABLE);
1020         WARN(cur_state != state,
1021              "FDI RX state assertion failure (expected %s, current %s)\n",
1022              state_string(state), state_string(cur_state));
1023 }
1024 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1025 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026
1027 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1028                                       enum pipe pipe)
1029 {
1030         int reg;
1031         u32 val;
1032
1033         /* ILK FDI PLL is always enabled */
1034         if (dev_priv->info->gen == 5)
1035                 return;
1036
1037         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1038         if (HAS_DDI(dev_priv->dev))
1039                 return;
1040
1041         reg = FDI_TX_CTL(pipe);
1042         val = I915_READ(reg);
1043         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1044 }
1045
1046 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1047                        enum pipe pipe, bool state)
1048 {
1049         int reg;
1050         u32 val;
1051         bool cur_state;
1052
1053         reg = FDI_RX_CTL(pipe);
1054         val = I915_READ(reg);
1055         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1056         WARN(cur_state != state,
1057              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1058              state_string(state), state_string(cur_state));
1059 }
1060
1061 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1062                                   enum pipe pipe)
1063 {
1064         int pp_reg, lvds_reg;
1065         u32 val;
1066         enum pipe panel_pipe = PIPE_A;
1067         bool locked = true;
1068
1069         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1070                 pp_reg = PCH_PP_CONTROL;
1071                 lvds_reg = PCH_LVDS;
1072         } else {
1073                 pp_reg = PP_CONTROL;
1074                 lvds_reg = LVDS;
1075         }
1076
1077         val = I915_READ(pp_reg);
1078         if (!(val & PANEL_POWER_ON) ||
1079             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1080                 locked = false;
1081
1082         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1083                 panel_pipe = PIPE_B;
1084
1085         WARN(panel_pipe == pipe && locked,
1086              "panel assertion failure, pipe %c regs locked\n",
1087              pipe_name(pipe));
1088 }
1089
1090 void assert_pipe(struct drm_i915_private *dev_priv,
1091                  enum pipe pipe, bool state)
1092 {
1093         int reg;
1094         u32 val;
1095         bool cur_state;
1096         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1097                                                                       pipe);
1098
1099         /* if we need the pipe A quirk it must be always on */
1100         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1101                 state = true;
1102
1103         if (!intel_display_power_enabled(dev_priv->dev,
1104                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1105                 cur_state = false;
1106         } else {
1107                 reg = PIPECONF(cpu_transcoder);
1108                 val = I915_READ(reg);
1109                 cur_state = !!(val & PIPECONF_ENABLE);
1110         }
1111
1112         WARN(cur_state != state,
1113              "pipe %c assertion failure (expected %s, current %s)\n",
1114              pipe_name(pipe), state_string(state), state_string(cur_state));
1115 }
1116
1117 static void assert_plane(struct drm_i915_private *dev_priv,
1118                          enum plane plane, bool state)
1119 {
1120         int reg;
1121         u32 val;
1122         bool cur_state;
1123
1124         reg = DSPCNTR(plane);
1125         val = I915_READ(reg);
1126         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1127         WARN(cur_state != state,
1128              "plane %c assertion failure (expected %s, current %s)\n",
1129              plane_name(plane), state_string(state), state_string(cur_state));
1130 }
1131
1132 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1133 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1134
1135 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1136                                    enum pipe pipe)
1137 {
1138         struct drm_device *dev = dev_priv->dev;
1139         int reg, i;
1140         u32 val;
1141         int cur_pipe;
1142
1143         /* Primary planes are fixed to pipes on gen4+ */
1144         if (INTEL_INFO(dev)->gen >= 4) {
1145                 reg = DSPCNTR(pipe);
1146                 val = I915_READ(reg);
1147                 WARN((val & DISPLAY_PLANE_ENABLE),
1148                      "plane %c assertion failure, should be disabled but not\n",
1149                      plane_name(pipe));
1150                 return;
1151         }
1152
1153         /* Need to check both planes against the pipe */
1154         for_each_pipe(i) {
1155                 reg = DSPCNTR(i);
1156                 val = I915_READ(reg);
1157                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1158                         DISPPLANE_SEL_PIPE_SHIFT;
1159                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1160                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1161                      plane_name(i), pipe_name(pipe));
1162         }
1163 }
1164
1165 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1166                                     enum pipe pipe)
1167 {
1168         struct drm_device *dev = dev_priv->dev;
1169         int reg, i;
1170         u32 val;
1171
1172         if (IS_VALLEYVIEW(dev)) {
1173                 for (i = 0; i < dev_priv->num_plane; i++) {
1174                         reg = SPCNTR(pipe, i);
1175                         val = I915_READ(reg);
1176                         WARN((val & SP_ENABLE),
1177                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1178                              sprite_name(pipe, i), pipe_name(pipe));
1179                 }
1180         } else if (INTEL_INFO(dev)->gen >= 7) {
1181                 reg = SPRCTL(pipe);
1182                 val = I915_READ(reg);
1183                 WARN((val & SPRITE_ENABLE),
1184                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1185                      plane_name(pipe), pipe_name(pipe));
1186         } else if (INTEL_INFO(dev)->gen >= 5) {
1187                 reg = DVSCNTR(pipe);
1188                 val = I915_READ(reg);
1189                 WARN((val & DVS_ENABLE),
1190                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191                      plane_name(pipe), pipe_name(pipe));
1192         }
1193 }
1194
1195 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1196 {
1197         u32 val;
1198         bool enabled;
1199
1200         if (HAS_PCH_LPT(dev_priv->dev)) {
1201                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1202                 return;
1203         }
1204
1205         val = I915_READ(PCH_DREF_CONTROL);
1206         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1207                             DREF_SUPERSPREAD_SOURCE_MASK));
1208         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1209 }
1210
1211 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1212                                            enum pipe pipe)
1213 {
1214         int reg;
1215         u32 val;
1216         bool enabled;
1217
1218         reg = PCH_TRANSCONF(pipe);
1219         val = I915_READ(reg);
1220         enabled = !!(val & TRANS_ENABLE);
1221         WARN(enabled,
1222              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1223              pipe_name(pipe));
1224 }
1225
1226 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1227                             enum pipe pipe, u32 port_sel, u32 val)
1228 {
1229         if ((val & DP_PORT_EN) == 0)
1230                 return false;
1231
1232         if (HAS_PCH_CPT(dev_priv->dev)) {
1233                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1234                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1235                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1236                         return false;
1237         } else {
1238                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1239                         return false;
1240         }
1241         return true;
1242 }
1243
1244 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1245                               enum pipe pipe, u32 val)
1246 {
1247         if ((val & SDVO_ENABLE) == 0)
1248                 return false;
1249
1250         if (HAS_PCH_CPT(dev_priv->dev)) {
1251                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1252                         return false;
1253         } else {
1254                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1255                         return false;
1256         }
1257         return true;
1258 }
1259
1260 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1261                               enum pipe pipe, u32 val)
1262 {
1263         if ((val & LVDS_PORT_EN) == 0)
1264                 return false;
1265
1266         if (HAS_PCH_CPT(dev_priv->dev)) {
1267                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1268                         return false;
1269         } else {
1270                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1271                         return false;
1272         }
1273         return true;
1274 }
1275
1276 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1277                               enum pipe pipe, u32 val)
1278 {
1279         if ((val & ADPA_DAC_ENABLE) == 0)
1280                 return false;
1281         if (HAS_PCH_CPT(dev_priv->dev)) {
1282                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1283                         return false;
1284         } else {
1285                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1286                         return false;
1287         }
1288         return true;
1289 }
1290
1291 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1292                                    enum pipe pipe, int reg, u32 port_sel)
1293 {
1294         u32 val = I915_READ(reg);
1295         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1296              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1297              reg, pipe_name(pipe));
1298
1299         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1300              && (val & DP_PIPEB_SELECT),
1301              "IBX PCH dp port still using transcoder B\n");
1302 }
1303
1304 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1305                                      enum pipe pipe, int reg)
1306 {
1307         u32 val = I915_READ(reg);
1308         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1309              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1310              reg, pipe_name(pipe));
1311
1312         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1313              && (val & SDVO_PIPE_B_SELECT),
1314              "IBX PCH hdmi port still using transcoder B\n");
1315 }
1316
1317 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1318                                       enum pipe pipe)
1319 {
1320         int reg;
1321         u32 val;
1322
1323         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1324         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1325         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1326
1327         reg = PCH_ADPA;
1328         val = I915_READ(reg);
1329         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1330              "PCH VGA enabled on transcoder %c, should be disabled\n",
1331              pipe_name(pipe));
1332
1333         reg = PCH_LVDS;
1334         val = I915_READ(reg);
1335         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1336              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1337              pipe_name(pipe));
1338
1339         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1340         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1341         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1342 }
1343
1344 static void vlv_enable_pll(struct intel_crtc *crtc)
1345 {
1346         struct drm_device *dev = crtc->base.dev;
1347         struct drm_i915_private *dev_priv = dev->dev_private;
1348         int reg = DPLL(crtc->pipe);
1349         u32 dpll = crtc->config.dpll_hw_state.dpll;
1350
1351         assert_pipe_disabled(dev_priv, crtc->pipe);
1352
1353         /* No really, not for ILK+ */
1354         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1355
1356         /* PLL is protected by panel, make sure we can write it */
1357         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1358                 assert_panel_unlocked(dev_priv, crtc->pipe);
1359
1360         I915_WRITE(reg, dpll);
1361         POSTING_READ(reg);
1362         udelay(150);
1363
1364         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1365                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1366
1367         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1368         POSTING_READ(DPLL_MD(crtc->pipe));
1369
1370         /* We do this three times for luck */
1371         I915_WRITE(reg, dpll);
1372         POSTING_READ(reg);
1373         udelay(150); /* wait for warmup */
1374         I915_WRITE(reg, dpll);
1375         POSTING_READ(reg);
1376         udelay(150); /* wait for warmup */
1377         I915_WRITE(reg, dpll);
1378         POSTING_READ(reg);
1379         udelay(150); /* wait for warmup */
1380 }
1381
1382 static void i9xx_enable_pll(struct intel_crtc *crtc)
1383 {
1384         struct drm_device *dev = crtc->base.dev;
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386         int reg = DPLL(crtc->pipe);
1387         u32 dpll = crtc->config.dpll_hw_state.dpll;
1388
1389         assert_pipe_disabled(dev_priv, crtc->pipe);
1390
1391         /* No really, not for ILK+ */
1392         BUG_ON(dev_priv->info->gen >= 5);
1393
1394         /* PLL is protected by panel, make sure we can write it */
1395         if (IS_MOBILE(dev) && !IS_I830(dev))
1396                 assert_panel_unlocked(dev_priv, crtc->pipe);
1397
1398         I915_WRITE(reg, dpll);
1399
1400         /* Wait for the clocks to stabilize. */
1401         POSTING_READ(reg);
1402         udelay(150);
1403
1404         if (INTEL_INFO(dev)->gen >= 4) {
1405                 I915_WRITE(DPLL_MD(crtc->pipe),
1406                            crtc->config.dpll_hw_state.dpll_md);
1407         } else {
1408                 /* The pixel multiplier can only be updated once the
1409                  * DPLL is enabled and the clocks are stable.
1410                  *
1411                  * So write it again.
1412                  */
1413                 I915_WRITE(reg, dpll);
1414         }
1415
1416         /* We do this three times for luck */
1417         I915_WRITE(reg, dpll);
1418         POSTING_READ(reg);
1419         udelay(150); /* wait for warmup */
1420         I915_WRITE(reg, dpll);
1421         POSTING_READ(reg);
1422         udelay(150); /* wait for warmup */
1423         I915_WRITE(reg, dpll);
1424         POSTING_READ(reg);
1425         udelay(150); /* wait for warmup */
1426 }
1427
1428 /**
1429  * i9xx_disable_pll - disable a PLL
1430  * @dev_priv: i915 private structure
1431  * @pipe: pipe PLL to disable
1432  *
1433  * Disable the PLL for @pipe, making sure the pipe is off first.
1434  *
1435  * Note!  This is for pre-ILK only.
1436  */
1437 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1438 {
1439         /* Don't disable pipe A or pipe A PLLs if needed */
1440         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1441                 return;
1442
1443         /* Make sure the pipe isn't still relying on us */
1444         assert_pipe_disabled(dev_priv, pipe);
1445
1446         I915_WRITE(DPLL(pipe), 0);
1447         POSTING_READ(DPLL(pipe));
1448 }
1449
1450 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1451 {
1452         u32 port_mask;
1453
1454         if (!port)
1455                 port_mask = DPLL_PORTB_READY_MASK;
1456         else
1457                 port_mask = DPLL_PORTC_READY_MASK;
1458
1459         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1460                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1461                      'B' + port, I915_READ(DPLL(0)));
1462 }
1463
1464 /**
1465  * ironlake_enable_shared_dpll - enable PCH PLL
1466  * @dev_priv: i915 private structure
1467  * @pipe: pipe PLL to enable
1468  *
1469  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1470  * drives the transcoder clock.
1471  */
1472 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1473 {
1474         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1475         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1476
1477         /* PCH PLLs only available on ILK, SNB and IVB */
1478         BUG_ON(dev_priv->info->gen < 5);
1479         if (WARN_ON(pll == NULL))
1480                 return;
1481
1482         if (WARN_ON(pll->refcount == 0))
1483                 return;
1484
1485         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1486                       pll->name, pll->active, pll->on,
1487                       crtc->base.base.id);
1488
1489         if (pll->active++) {
1490                 WARN_ON(!pll->on);
1491                 assert_shared_dpll_enabled(dev_priv, pll);
1492                 return;
1493         }
1494         WARN_ON(pll->on);
1495
1496         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1497         pll->enable(dev_priv, pll);
1498         pll->on = true;
1499 }
1500
1501 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1502 {
1503         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1504         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1505
1506         /* PCH only available on ILK+ */
1507         BUG_ON(dev_priv->info->gen < 5);
1508         if (WARN_ON(pll == NULL))
1509                return;
1510
1511         if (WARN_ON(pll->refcount == 0))
1512                 return;
1513
1514         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1515                       pll->name, pll->active, pll->on,
1516                       crtc->base.base.id);
1517
1518         if (WARN_ON(pll->active == 0)) {
1519                 assert_shared_dpll_disabled(dev_priv, pll);
1520                 return;
1521         }
1522
1523         assert_shared_dpll_enabled(dev_priv, pll);
1524         WARN_ON(!pll->on);
1525         if (--pll->active)
1526                 return;
1527
1528         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1529         pll->disable(dev_priv, pll);
1530         pll->on = false;
1531 }
1532
1533 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1534                                            enum pipe pipe)
1535 {
1536         struct drm_device *dev = dev_priv->dev;
1537         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1539         uint32_t reg, val, pipeconf_val;
1540
1541         /* PCH only available on ILK+ */
1542         BUG_ON(dev_priv->info->gen < 5);
1543
1544         /* Make sure PCH DPLL is enabled */
1545         assert_shared_dpll_enabled(dev_priv,
1546                                    intel_crtc_to_shared_dpll(intel_crtc));
1547
1548         /* FDI must be feeding us bits for PCH ports */
1549         assert_fdi_tx_enabled(dev_priv, pipe);
1550         assert_fdi_rx_enabled(dev_priv, pipe);
1551
1552         if (HAS_PCH_CPT(dev)) {
1553                 /* Workaround: Set the timing override bit before enabling the
1554                  * pch transcoder. */
1555                 reg = TRANS_CHICKEN2(pipe);
1556                 val = I915_READ(reg);
1557                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1558                 I915_WRITE(reg, val);
1559         }
1560
1561         reg = PCH_TRANSCONF(pipe);
1562         val = I915_READ(reg);
1563         pipeconf_val = I915_READ(PIPECONF(pipe));
1564
1565         if (HAS_PCH_IBX(dev_priv->dev)) {
1566                 /*
1567                  * make the BPC in transcoder be consistent with
1568                  * that in pipeconf reg.
1569                  */
1570                 val &= ~PIPECONF_BPC_MASK;
1571                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1572         }
1573
1574         val &= ~TRANS_INTERLACE_MASK;
1575         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1576                 if (HAS_PCH_IBX(dev_priv->dev) &&
1577                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1578                         val |= TRANS_LEGACY_INTERLACED_ILK;
1579                 else
1580                         val |= TRANS_INTERLACED;
1581         else
1582                 val |= TRANS_PROGRESSIVE;
1583
1584         I915_WRITE(reg, val | TRANS_ENABLE);
1585         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1586                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1587 }
1588
1589 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1590                                       enum transcoder cpu_transcoder)
1591 {
1592         u32 val, pipeconf_val;
1593
1594         /* PCH only available on ILK+ */
1595         BUG_ON(dev_priv->info->gen < 5);
1596
1597         /* FDI must be feeding us bits for PCH ports */
1598         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1599         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1600
1601         /* Workaround: set timing override bit. */
1602         val = I915_READ(_TRANSA_CHICKEN2);
1603         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1604         I915_WRITE(_TRANSA_CHICKEN2, val);
1605
1606         val = TRANS_ENABLE;
1607         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1608
1609         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1610             PIPECONF_INTERLACED_ILK)
1611                 val |= TRANS_INTERLACED;
1612         else
1613                 val |= TRANS_PROGRESSIVE;
1614
1615         I915_WRITE(LPT_TRANSCONF, val);
1616         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1617                 DRM_ERROR("Failed to enable PCH transcoder\n");
1618 }
1619
1620 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1621                                             enum pipe pipe)
1622 {
1623         struct drm_device *dev = dev_priv->dev;
1624         uint32_t reg, val;
1625
1626         /* FDI relies on the transcoder */
1627         assert_fdi_tx_disabled(dev_priv, pipe);
1628         assert_fdi_rx_disabled(dev_priv, pipe);
1629
1630         /* Ports must be off as well */
1631         assert_pch_ports_disabled(dev_priv, pipe);
1632
1633         reg = PCH_TRANSCONF(pipe);
1634         val = I915_READ(reg);
1635         val &= ~TRANS_ENABLE;
1636         I915_WRITE(reg, val);
1637         /* wait for PCH transcoder off, transcoder state */
1638         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1639                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1640
1641         if (!HAS_PCH_IBX(dev)) {
1642                 /* Workaround: Clear the timing override chicken bit again. */
1643                 reg = TRANS_CHICKEN2(pipe);
1644                 val = I915_READ(reg);
1645                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1646                 I915_WRITE(reg, val);
1647         }
1648 }
1649
1650 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1651 {
1652         u32 val;
1653
1654         val = I915_READ(LPT_TRANSCONF);
1655         val &= ~TRANS_ENABLE;
1656         I915_WRITE(LPT_TRANSCONF, val);
1657         /* wait for PCH transcoder off, transcoder state */
1658         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1659                 DRM_ERROR("Failed to disable PCH transcoder\n");
1660
1661         /* Workaround: clear timing override bit. */
1662         val = I915_READ(_TRANSA_CHICKEN2);
1663         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1664         I915_WRITE(_TRANSA_CHICKEN2, val);
1665 }
1666
1667 /**
1668  * intel_enable_pipe - enable a pipe, asserting requirements
1669  * @dev_priv: i915 private structure
1670  * @pipe: pipe to enable
1671  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1672  *
1673  * Enable @pipe, making sure that various hardware specific requirements
1674  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1675  *
1676  * @pipe should be %PIPE_A or %PIPE_B.
1677  *
1678  * Will wait until the pipe is actually running (i.e. first vblank) before
1679  * returning.
1680  */
1681 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1682                               bool pch_port, bool dsi)
1683 {
1684         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1685                                                                       pipe);
1686         enum pipe pch_transcoder;
1687         int reg;
1688         u32 val;
1689
1690         assert_planes_disabled(dev_priv, pipe);
1691         assert_sprites_disabled(dev_priv, pipe);
1692
1693         if (HAS_PCH_LPT(dev_priv->dev))
1694                 pch_transcoder = TRANSCODER_A;
1695         else
1696                 pch_transcoder = pipe;
1697
1698         /*
1699          * A pipe without a PLL won't actually be able to drive bits from
1700          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1701          * need the check.
1702          */
1703         if (!HAS_PCH_SPLIT(dev_priv->dev))
1704                 if (dsi)
1705                         assert_dsi_pll_enabled(dev_priv);
1706                 else
1707                         assert_pll_enabled(dev_priv, pipe);
1708         else {
1709                 if (pch_port) {
1710                         /* if driving the PCH, we need FDI enabled */
1711                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1712                         assert_fdi_tx_pll_enabled(dev_priv,
1713                                                   (enum pipe) cpu_transcoder);
1714                 }
1715                 /* FIXME: assert CPU port conditions for SNB+ */
1716         }
1717
1718         reg = PIPECONF(cpu_transcoder);
1719         val = I915_READ(reg);
1720         if (val & PIPECONF_ENABLE)
1721                 return;
1722
1723         I915_WRITE(reg, val | PIPECONF_ENABLE);
1724         intel_wait_for_vblank(dev_priv->dev, pipe);
1725 }
1726
1727 /**
1728  * intel_disable_pipe - disable a pipe, asserting requirements
1729  * @dev_priv: i915 private structure
1730  * @pipe: pipe to disable
1731  *
1732  * Disable @pipe, making sure that various hardware specific requirements
1733  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1734  *
1735  * @pipe should be %PIPE_A or %PIPE_B.
1736  *
1737  * Will wait until the pipe has shut down before returning.
1738  */
1739 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1740                                enum pipe pipe)
1741 {
1742         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1743                                                                       pipe);
1744         int reg;
1745         u32 val;
1746
1747         /*
1748          * Make sure planes won't keep trying to pump pixels to us,
1749          * or we might hang the display.
1750          */
1751         assert_planes_disabled(dev_priv, pipe);
1752         assert_sprites_disabled(dev_priv, pipe);
1753
1754         /* Don't disable pipe A or pipe A PLLs if needed */
1755         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1756                 return;
1757
1758         reg = PIPECONF(cpu_transcoder);
1759         val = I915_READ(reg);
1760         if ((val & PIPECONF_ENABLE) == 0)
1761                 return;
1762
1763         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1764         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1765 }
1766
1767 /*
1768  * Plane regs are double buffered, going from enabled->disabled needs a
1769  * trigger in order to latch.  The display address reg provides this.
1770  */
1771 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1772                                       enum plane plane)
1773 {
1774         if (dev_priv->info->gen >= 4)
1775                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1776         else
1777                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1778 }
1779
1780 /**
1781  * intel_enable_plane - enable a display plane on a given pipe
1782  * @dev_priv: i915 private structure
1783  * @plane: plane to enable
1784  * @pipe: pipe being fed
1785  *
1786  * Enable @plane on @pipe, making sure that @pipe is running first.
1787  */
1788 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1789                                enum plane plane, enum pipe pipe)
1790 {
1791         int reg;
1792         u32 val;
1793
1794         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1795         assert_pipe_enabled(dev_priv, pipe);
1796
1797         reg = DSPCNTR(plane);
1798         val = I915_READ(reg);
1799         if (val & DISPLAY_PLANE_ENABLE)
1800                 return;
1801
1802         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1803         intel_flush_display_plane(dev_priv, plane);
1804         intel_wait_for_vblank(dev_priv->dev, pipe);
1805 }
1806
1807 /**
1808  * intel_disable_plane - disable a display plane
1809  * @dev_priv: i915 private structure
1810  * @plane: plane to disable
1811  * @pipe: pipe consuming the data
1812  *
1813  * Disable @plane; should be an independent operation.
1814  */
1815 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1816                                 enum plane plane, enum pipe pipe)
1817 {
1818         int reg;
1819         u32 val;
1820
1821         reg = DSPCNTR(plane);
1822         val = I915_READ(reg);
1823         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1824                 return;
1825
1826         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1827         intel_flush_display_plane(dev_priv, plane);
1828         intel_wait_for_vblank(dev_priv->dev, pipe);
1829 }
1830
1831 static bool need_vtd_wa(struct drm_device *dev)
1832 {
1833 #ifdef CONFIG_INTEL_IOMMU
1834         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1835                 return true;
1836 #endif
1837         return false;
1838 }
1839
1840 int
1841 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1842                            struct drm_i915_gem_object *obj,
1843                            struct intel_ring_buffer *pipelined)
1844 {
1845         struct drm_i915_private *dev_priv = dev->dev_private;
1846         u32 alignment;
1847         int ret;
1848
1849         switch (obj->tiling_mode) {
1850         case I915_TILING_NONE:
1851                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1852                         alignment = 128 * 1024;
1853                 else if (INTEL_INFO(dev)->gen >= 4)
1854                         alignment = 4 * 1024;
1855                 else
1856                         alignment = 64 * 1024;
1857                 break;
1858         case I915_TILING_X:
1859                 /* pin() will align the object as required by fence */
1860                 alignment = 0;
1861                 break;
1862         case I915_TILING_Y:
1863                 /* Despite that we check this in framebuffer_init userspace can
1864                  * screw us over and change the tiling after the fact. Only
1865                  * pinned buffers can't change their tiling. */
1866                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1867                 return -EINVAL;
1868         default:
1869                 BUG();
1870         }
1871
1872         /* Note that the w/a also requires 64 PTE of padding following the
1873          * bo. We currently fill all unused PTE with the shadow page and so
1874          * we should always have valid PTE following the scanout preventing
1875          * the VT-d warning.
1876          */
1877         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1878                 alignment = 256 * 1024;
1879
1880         dev_priv->mm.interruptible = false;
1881         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1882         if (ret)
1883                 goto err_interruptible;
1884
1885         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1886          * fence, whereas 965+ only requires a fence if using
1887          * framebuffer compression.  For simplicity, we always install
1888          * a fence as the cost is not that onerous.
1889          */
1890         ret = i915_gem_object_get_fence(obj);
1891         if (ret)
1892                 goto err_unpin;
1893
1894         i915_gem_object_pin_fence(obj);
1895
1896         dev_priv->mm.interruptible = true;
1897         return 0;
1898
1899 err_unpin:
1900         i915_gem_object_unpin_from_display_plane(obj);
1901 err_interruptible:
1902         dev_priv->mm.interruptible = true;
1903         return ret;
1904 }
1905
1906 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1907 {
1908         i915_gem_object_unpin_fence(obj);
1909         i915_gem_object_unpin_from_display_plane(obj);
1910 }
1911
1912 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1913  * is assumed to be a power-of-two. */
1914 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1915                                              unsigned int tiling_mode,
1916                                              unsigned int cpp,
1917                                              unsigned int pitch)
1918 {
1919         if (tiling_mode != I915_TILING_NONE) {
1920                 unsigned int tile_rows, tiles;
1921
1922                 tile_rows = *y / 8;
1923                 *y %= 8;
1924
1925                 tiles = *x / (512/cpp);
1926                 *x %= 512/cpp;
1927
1928                 return tile_rows * pitch * 8 + tiles * 4096;
1929         } else {
1930                 unsigned int offset;
1931
1932                 offset = *y * pitch + *x * cpp;
1933                 *y = 0;
1934                 *x = (offset & 4095) / cpp;
1935                 return offset & -4096;
1936         }
1937 }
1938
1939 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1940                              int x, int y)
1941 {
1942         struct drm_device *dev = crtc->dev;
1943         struct drm_i915_private *dev_priv = dev->dev_private;
1944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1945         struct intel_framebuffer *intel_fb;
1946         struct drm_i915_gem_object *obj;
1947         int plane = intel_crtc->plane;
1948         unsigned long linear_offset;
1949         u32 dspcntr;
1950         u32 reg;
1951
1952         switch (plane) {
1953         case 0:
1954         case 1:
1955                 break;
1956         default:
1957                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1958                 return -EINVAL;
1959         }
1960
1961         intel_fb = to_intel_framebuffer(fb);
1962         obj = intel_fb->obj;
1963
1964         reg = DSPCNTR(plane);
1965         dspcntr = I915_READ(reg);
1966         /* Mask out pixel format bits in case we change it */
1967         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1968         switch (fb->pixel_format) {
1969         case DRM_FORMAT_C8:
1970                 dspcntr |= DISPPLANE_8BPP;
1971                 break;
1972         case DRM_FORMAT_XRGB1555:
1973         case DRM_FORMAT_ARGB1555:
1974                 dspcntr |= DISPPLANE_BGRX555;
1975                 break;
1976         case DRM_FORMAT_RGB565:
1977                 dspcntr |= DISPPLANE_BGRX565;
1978                 break;
1979         case DRM_FORMAT_XRGB8888:
1980         case DRM_FORMAT_ARGB8888:
1981                 dspcntr |= DISPPLANE_BGRX888;
1982                 break;
1983         case DRM_FORMAT_XBGR8888:
1984         case DRM_FORMAT_ABGR8888:
1985                 dspcntr |= DISPPLANE_RGBX888;
1986                 break;
1987         case DRM_FORMAT_XRGB2101010:
1988         case DRM_FORMAT_ARGB2101010:
1989                 dspcntr |= DISPPLANE_BGRX101010;
1990                 break;
1991         case DRM_FORMAT_XBGR2101010:
1992         case DRM_FORMAT_ABGR2101010:
1993                 dspcntr |= DISPPLANE_RGBX101010;
1994                 break;
1995         default:
1996                 BUG();
1997         }
1998
1999         if (INTEL_INFO(dev)->gen >= 4) {
2000                 if (obj->tiling_mode != I915_TILING_NONE)
2001                         dspcntr |= DISPPLANE_TILED;
2002                 else
2003                         dspcntr &= ~DISPPLANE_TILED;
2004         }
2005
2006         if (IS_G4X(dev))
2007                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2008
2009         I915_WRITE(reg, dspcntr);
2010
2011         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2012
2013         if (INTEL_INFO(dev)->gen >= 4) {
2014                 intel_crtc->dspaddr_offset =
2015                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2016                                                        fb->bits_per_pixel / 8,
2017                                                        fb->pitches[0]);
2018                 linear_offset -= intel_crtc->dspaddr_offset;
2019         } else {
2020                 intel_crtc->dspaddr_offset = linear_offset;
2021         }
2022
2023         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2024                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2025                       fb->pitches[0]);
2026         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2027         if (INTEL_INFO(dev)->gen >= 4) {
2028                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2029                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2030                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2031                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2032         } else
2033                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2034         POSTING_READ(reg);
2035
2036         return 0;
2037 }
2038
2039 static int ironlake_update_plane(struct drm_crtc *crtc,
2040                                  struct drm_framebuffer *fb, int x, int y)
2041 {
2042         struct drm_device *dev = crtc->dev;
2043         struct drm_i915_private *dev_priv = dev->dev_private;
2044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2045         struct intel_framebuffer *intel_fb;
2046         struct drm_i915_gem_object *obj;
2047         int plane = intel_crtc->plane;
2048         unsigned long linear_offset;
2049         u32 dspcntr;
2050         u32 reg;
2051
2052         switch (plane) {
2053         case 0:
2054         case 1:
2055         case 2:
2056                 break;
2057         default:
2058                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2059                 return -EINVAL;
2060         }
2061
2062         intel_fb = to_intel_framebuffer(fb);
2063         obj = intel_fb->obj;
2064
2065         reg = DSPCNTR(plane);
2066         dspcntr = I915_READ(reg);
2067         /* Mask out pixel format bits in case we change it */
2068         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2069         switch (fb->pixel_format) {
2070         case DRM_FORMAT_C8:
2071                 dspcntr |= DISPPLANE_8BPP;
2072                 break;
2073         case DRM_FORMAT_RGB565:
2074                 dspcntr |= DISPPLANE_BGRX565;
2075                 break;
2076         case DRM_FORMAT_XRGB8888:
2077         case DRM_FORMAT_ARGB8888:
2078                 dspcntr |= DISPPLANE_BGRX888;
2079                 break;
2080         case DRM_FORMAT_XBGR8888:
2081         case DRM_FORMAT_ABGR8888:
2082                 dspcntr |= DISPPLANE_RGBX888;
2083                 break;
2084         case DRM_FORMAT_XRGB2101010:
2085         case DRM_FORMAT_ARGB2101010:
2086                 dspcntr |= DISPPLANE_BGRX101010;
2087                 break;
2088         case DRM_FORMAT_XBGR2101010:
2089         case DRM_FORMAT_ABGR2101010:
2090                 dspcntr |= DISPPLANE_RGBX101010;
2091                 break;
2092         default:
2093                 BUG();
2094         }
2095
2096         if (obj->tiling_mode != I915_TILING_NONE)
2097                 dspcntr |= DISPPLANE_TILED;
2098         else
2099                 dspcntr &= ~DISPPLANE_TILED;
2100
2101         if (IS_HASWELL(dev))
2102                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2103         else
2104                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2105
2106         I915_WRITE(reg, dspcntr);
2107
2108         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2109         intel_crtc->dspaddr_offset =
2110                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2111                                                fb->bits_per_pixel / 8,
2112                                                fb->pitches[0]);
2113         linear_offset -= intel_crtc->dspaddr_offset;
2114
2115         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2116                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2117                       fb->pitches[0]);
2118         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2119         I915_MODIFY_DISPBASE(DSPSURF(plane),
2120                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2121         if (IS_HASWELL(dev)) {
2122                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2123         } else {
2124                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2125                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2126         }
2127         POSTING_READ(reg);
2128
2129         return 0;
2130 }
2131
2132 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2133 static int
2134 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2135                            int x, int y, enum mode_set_atomic state)
2136 {
2137         struct drm_device *dev = crtc->dev;
2138         struct drm_i915_private *dev_priv = dev->dev_private;
2139
2140         if (dev_priv->display.disable_fbc)
2141                 dev_priv->display.disable_fbc(dev);
2142         intel_increase_pllclock(crtc);
2143
2144         return dev_priv->display.update_plane(crtc, fb, x, y);
2145 }
2146
2147 void intel_display_handle_reset(struct drm_device *dev)
2148 {
2149         struct drm_i915_private *dev_priv = dev->dev_private;
2150         struct drm_crtc *crtc;
2151
2152         /*
2153          * Flips in the rings have been nuked by the reset,
2154          * so complete all pending flips so that user space
2155          * will get its events and not get stuck.
2156          *
2157          * Also update the base address of all primary
2158          * planes to the the last fb to make sure we're
2159          * showing the correct fb after a reset.
2160          *
2161          * Need to make two loops over the crtcs so that we
2162          * don't try to grab a crtc mutex before the
2163          * pending_flip_queue really got woken up.
2164          */
2165
2166         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2167                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2168                 enum plane plane = intel_crtc->plane;
2169
2170                 intel_prepare_page_flip(dev, plane);
2171                 intel_finish_page_flip_plane(dev, plane);
2172         }
2173
2174         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2175                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176
2177                 mutex_lock(&crtc->mutex);
2178                 if (intel_crtc->active)
2179                         dev_priv->display.update_plane(crtc, crtc->fb,
2180                                                        crtc->x, crtc->y);
2181                 mutex_unlock(&crtc->mutex);
2182         }
2183 }
2184
2185 static int
2186 intel_finish_fb(struct drm_framebuffer *old_fb)
2187 {
2188         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2189         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2190         bool was_interruptible = dev_priv->mm.interruptible;
2191         int ret;
2192
2193         /* Big Hammer, we also need to ensure that any pending
2194          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2195          * current scanout is retired before unpinning the old
2196          * framebuffer.
2197          *
2198          * This should only fail upon a hung GPU, in which case we
2199          * can safely continue.
2200          */
2201         dev_priv->mm.interruptible = false;
2202         ret = i915_gem_object_finish_gpu(obj);
2203         dev_priv->mm.interruptible = was_interruptible;
2204
2205         return ret;
2206 }
2207
2208 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2209 {
2210         struct drm_device *dev = crtc->dev;
2211         struct drm_i915_master_private *master_priv;
2212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214         if (!dev->primary->master)
2215                 return;
2216
2217         master_priv = dev->primary->master->driver_priv;
2218         if (!master_priv->sarea_priv)
2219                 return;
2220
2221         switch (intel_crtc->pipe) {
2222         case 0:
2223                 master_priv->sarea_priv->pipeA_x = x;
2224                 master_priv->sarea_priv->pipeA_y = y;
2225                 break;
2226         case 1:
2227                 master_priv->sarea_priv->pipeB_x = x;
2228                 master_priv->sarea_priv->pipeB_y = y;
2229                 break;
2230         default:
2231                 break;
2232         }
2233 }
2234
2235 static int
2236 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2237                     struct drm_framebuffer *fb)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2242         struct drm_framebuffer *old_fb;
2243         int ret;
2244
2245         /* no fb bound */
2246         if (!fb) {
2247                 DRM_ERROR("No FB bound\n");
2248                 return 0;
2249         }
2250
2251         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2252                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2253                           plane_name(intel_crtc->plane),
2254                           INTEL_INFO(dev)->num_pipes);
2255                 return -EINVAL;
2256         }
2257
2258         mutex_lock(&dev->struct_mutex);
2259         ret = intel_pin_and_fence_fb_obj(dev,
2260                                          to_intel_framebuffer(fb)->obj,
2261                                          NULL);
2262         if (ret != 0) {
2263                 mutex_unlock(&dev->struct_mutex);
2264                 DRM_ERROR("pin & fence failed\n");
2265                 return ret;
2266         }
2267
2268         /* Update pipe size and adjust fitter if needed */
2269         if (i915_fastboot) {
2270                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2271                            ((crtc->mode.hdisplay - 1) << 16) |
2272                            (crtc->mode.vdisplay - 1));
2273                 if (!intel_crtc->config.pch_pfit.size &&
2274                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2275                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2276                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2277                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2278                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2279                 }
2280         }
2281
2282         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2283         if (ret) {
2284                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2285                 mutex_unlock(&dev->struct_mutex);
2286                 DRM_ERROR("failed to update base address\n");
2287                 return ret;
2288         }
2289
2290         old_fb = crtc->fb;
2291         crtc->fb = fb;
2292         crtc->x = x;
2293         crtc->y = y;
2294
2295         if (old_fb) {
2296                 if (intel_crtc->active && old_fb != fb)
2297                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2298                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2299         }
2300
2301         intel_update_fbc(dev);
2302         intel_edp_psr_update(dev);
2303         mutex_unlock(&dev->struct_mutex);
2304
2305         intel_crtc_update_sarea_pos(crtc, x, y);
2306
2307         return 0;
2308 }
2309
2310 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2311 {
2312         struct drm_device *dev = crtc->dev;
2313         struct drm_i915_private *dev_priv = dev->dev_private;
2314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2315         int pipe = intel_crtc->pipe;
2316         u32 reg, temp;
2317
2318         /* enable normal train */
2319         reg = FDI_TX_CTL(pipe);
2320         temp = I915_READ(reg);
2321         if (IS_IVYBRIDGE(dev)) {
2322                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2323                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2324         } else {
2325                 temp &= ~FDI_LINK_TRAIN_NONE;
2326                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2327         }
2328         I915_WRITE(reg, temp);
2329
2330         reg = FDI_RX_CTL(pipe);
2331         temp = I915_READ(reg);
2332         if (HAS_PCH_CPT(dev)) {
2333                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2334                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2335         } else {
2336                 temp &= ~FDI_LINK_TRAIN_NONE;
2337                 temp |= FDI_LINK_TRAIN_NONE;
2338         }
2339         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2340
2341         /* wait one idle pattern time */
2342         POSTING_READ(reg);
2343         udelay(1000);
2344
2345         /* IVB wants error correction enabled */
2346         if (IS_IVYBRIDGE(dev))
2347                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2348                            FDI_FE_ERRC_ENABLE);
2349 }
2350
2351 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2352 {
2353         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2354 }
2355
2356 static void ivb_modeset_global_resources(struct drm_device *dev)
2357 {
2358         struct drm_i915_private *dev_priv = dev->dev_private;
2359         struct intel_crtc *pipe_B_crtc =
2360                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2361         struct intel_crtc *pipe_C_crtc =
2362                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2363         uint32_t temp;
2364
2365         /*
2366          * When everything is off disable fdi C so that we could enable fdi B
2367          * with all lanes. Note that we don't care about enabled pipes without
2368          * an enabled pch encoder.
2369          */
2370         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2371             !pipe_has_enabled_pch(pipe_C_crtc)) {
2372                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2373                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2374
2375                 temp = I915_READ(SOUTH_CHICKEN1);
2376                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2377                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2378                 I915_WRITE(SOUTH_CHICKEN1, temp);
2379         }
2380 }
2381
2382 /* The FDI link training functions for ILK/Ibexpeak. */
2383 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2384 {
2385         struct drm_device *dev = crtc->dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388         int pipe = intel_crtc->pipe;
2389         int plane = intel_crtc->plane;
2390         u32 reg, temp, tries;
2391
2392         /* FDI needs bits from pipe & plane first */
2393         assert_pipe_enabled(dev_priv, pipe);
2394         assert_plane_enabled(dev_priv, plane);
2395
2396         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397            for train result */
2398         reg = FDI_RX_IMR(pipe);
2399         temp = I915_READ(reg);
2400         temp &= ~FDI_RX_SYMBOL_LOCK;
2401         temp &= ~FDI_RX_BIT_LOCK;
2402         I915_WRITE(reg, temp);
2403         I915_READ(reg);
2404         udelay(150);
2405
2406         /* enable CPU FDI TX and PCH FDI RX */
2407         reg = FDI_TX_CTL(pipe);
2408         temp = I915_READ(reg);
2409         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2410         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2411         temp &= ~FDI_LINK_TRAIN_NONE;
2412         temp |= FDI_LINK_TRAIN_PATTERN_1;
2413         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2414
2415         reg = FDI_RX_CTL(pipe);
2416         temp = I915_READ(reg);
2417         temp &= ~FDI_LINK_TRAIN_NONE;
2418         temp |= FDI_LINK_TRAIN_PATTERN_1;
2419         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2420
2421         POSTING_READ(reg);
2422         udelay(150);
2423
2424         /* Ironlake workaround, enable clock pointer after FDI enable*/
2425         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2426         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2427                    FDI_RX_PHASE_SYNC_POINTER_EN);
2428
2429         reg = FDI_RX_IIR(pipe);
2430         for (tries = 0; tries < 5; tries++) {
2431                 temp = I915_READ(reg);
2432                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2433
2434                 if ((temp & FDI_RX_BIT_LOCK)) {
2435                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2436                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2437                         break;
2438                 }
2439         }
2440         if (tries == 5)
2441                 DRM_ERROR("FDI train 1 fail!\n");
2442
2443         /* Train 2 */
2444         reg = FDI_TX_CTL(pipe);
2445         temp = I915_READ(reg);
2446         temp &= ~FDI_LINK_TRAIN_NONE;
2447         temp |= FDI_LINK_TRAIN_PATTERN_2;
2448         I915_WRITE(reg, temp);
2449
2450         reg = FDI_RX_CTL(pipe);
2451         temp = I915_READ(reg);
2452         temp &= ~FDI_LINK_TRAIN_NONE;
2453         temp |= FDI_LINK_TRAIN_PATTERN_2;
2454         I915_WRITE(reg, temp);
2455
2456         POSTING_READ(reg);
2457         udelay(150);
2458
2459         reg = FDI_RX_IIR(pipe);
2460         for (tries = 0; tries < 5; tries++) {
2461                 temp = I915_READ(reg);
2462                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2463
2464                 if (temp & FDI_RX_SYMBOL_LOCK) {
2465                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2466                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2467                         break;
2468                 }
2469         }
2470         if (tries == 5)
2471                 DRM_ERROR("FDI train 2 fail!\n");
2472
2473         DRM_DEBUG_KMS("FDI train done\n");
2474
2475 }
2476
2477 static const int snb_b_fdi_train_param[] = {
2478         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2479         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2480         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2481         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2482 };
2483
2484 /* The FDI link training functions for SNB/Cougarpoint. */
2485 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2486 {
2487         struct drm_device *dev = crtc->dev;
2488         struct drm_i915_private *dev_priv = dev->dev_private;
2489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490         int pipe = intel_crtc->pipe;
2491         u32 reg, temp, i, retry;
2492
2493         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2494            for train result */
2495         reg = FDI_RX_IMR(pipe);
2496         temp = I915_READ(reg);
2497         temp &= ~FDI_RX_SYMBOL_LOCK;
2498         temp &= ~FDI_RX_BIT_LOCK;
2499         I915_WRITE(reg, temp);
2500
2501         POSTING_READ(reg);
2502         udelay(150);
2503
2504         /* enable CPU FDI TX and PCH FDI RX */
2505         reg = FDI_TX_CTL(pipe);
2506         temp = I915_READ(reg);
2507         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2508         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2509         temp &= ~FDI_LINK_TRAIN_NONE;
2510         temp |= FDI_LINK_TRAIN_PATTERN_1;
2511         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512         /* SNB-B */
2513         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2514         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2515
2516         I915_WRITE(FDI_RX_MISC(pipe),
2517                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2518
2519         reg = FDI_RX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         if (HAS_PCH_CPT(dev)) {
2522                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2523                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2524         } else {
2525                 temp &= ~FDI_LINK_TRAIN_NONE;
2526                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2527         }
2528         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530         POSTING_READ(reg);
2531         udelay(150);
2532
2533         for (i = 0; i < 4; i++) {
2534                 reg = FDI_TX_CTL(pipe);
2535                 temp = I915_READ(reg);
2536                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537                 temp |= snb_b_fdi_train_param[i];
2538                 I915_WRITE(reg, temp);
2539
2540                 POSTING_READ(reg);
2541                 udelay(500);
2542
2543                 for (retry = 0; retry < 5; retry++) {
2544                         reg = FDI_RX_IIR(pipe);
2545                         temp = I915_READ(reg);
2546                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547                         if (temp & FDI_RX_BIT_LOCK) {
2548                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2549                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2550                                 break;
2551                         }
2552                         udelay(50);
2553                 }
2554                 if (retry < 5)
2555                         break;
2556         }
2557         if (i == 4)
2558                 DRM_ERROR("FDI train 1 fail!\n");
2559
2560         /* Train 2 */
2561         reg = FDI_TX_CTL(pipe);
2562         temp = I915_READ(reg);
2563         temp &= ~FDI_LINK_TRAIN_NONE;
2564         temp |= FDI_LINK_TRAIN_PATTERN_2;
2565         if (IS_GEN6(dev)) {
2566                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2567                 /* SNB-B */
2568                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2569         }
2570         I915_WRITE(reg, temp);
2571
2572         reg = FDI_RX_CTL(pipe);
2573         temp = I915_READ(reg);
2574         if (HAS_PCH_CPT(dev)) {
2575                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2576                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2577         } else {
2578                 temp &= ~FDI_LINK_TRAIN_NONE;
2579                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580         }
2581         I915_WRITE(reg, temp);
2582
2583         POSTING_READ(reg);
2584         udelay(150);
2585
2586         for (i = 0; i < 4; i++) {
2587                 reg = FDI_TX_CTL(pipe);
2588                 temp = I915_READ(reg);
2589                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590                 temp |= snb_b_fdi_train_param[i];
2591                 I915_WRITE(reg, temp);
2592
2593                 POSTING_READ(reg);
2594                 udelay(500);
2595
2596                 for (retry = 0; retry < 5; retry++) {
2597                         reg = FDI_RX_IIR(pipe);
2598                         temp = I915_READ(reg);
2599                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2600                         if (temp & FDI_RX_SYMBOL_LOCK) {
2601                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2602                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2603                                 break;
2604                         }
2605                         udelay(50);
2606                 }
2607                 if (retry < 5)
2608                         break;
2609         }
2610         if (i == 4)
2611                 DRM_ERROR("FDI train 2 fail!\n");
2612
2613         DRM_DEBUG_KMS("FDI train done.\n");
2614 }
2615
2616 /* Manual link training for Ivy Bridge A0 parts */
2617 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2618 {
2619         struct drm_device *dev = crtc->dev;
2620         struct drm_i915_private *dev_priv = dev->dev_private;
2621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622         int pipe = intel_crtc->pipe;
2623         u32 reg, temp, i, j;
2624
2625         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2626            for train result */
2627         reg = FDI_RX_IMR(pipe);
2628         temp = I915_READ(reg);
2629         temp &= ~FDI_RX_SYMBOL_LOCK;
2630         temp &= ~FDI_RX_BIT_LOCK;
2631         I915_WRITE(reg, temp);
2632
2633         POSTING_READ(reg);
2634         udelay(150);
2635
2636         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2637                       I915_READ(FDI_RX_IIR(pipe)));
2638
2639         /* Try each vswing and preemphasis setting twice before moving on */
2640         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2641                 /* disable first in case we need to retry */
2642                 reg = FDI_TX_CTL(pipe);
2643                 temp = I915_READ(reg);
2644                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2645                 temp &= ~FDI_TX_ENABLE;
2646                 I915_WRITE(reg, temp);
2647
2648                 reg = FDI_RX_CTL(pipe);
2649                 temp = I915_READ(reg);
2650                 temp &= ~FDI_LINK_TRAIN_AUTO;
2651                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2652                 temp &= ~FDI_RX_ENABLE;
2653                 I915_WRITE(reg, temp);
2654
2655                 /* enable CPU FDI TX and PCH FDI RX */
2656                 reg = FDI_TX_CTL(pipe);
2657                 temp = I915_READ(reg);
2658                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2659                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2660                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662                 temp |= snb_b_fdi_train_param[j/2];
2663                 temp |= FDI_COMPOSITE_SYNC;
2664                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
2666                 I915_WRITE(FDI_RX_MISC(pipe),
2667                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
2669                 reg = FDI_RX_CTL(pipe);
2670                 temp = I915_READ(reg);
2671                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2672                 temp |= FDI_COMPOSITE_SYNC;
2673                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2674
2675                 POSTING_READ(reg);
2676                 udelay(1); /* should be 0.5us */
2677
2678                 for (i = 0; i < 4; i++) {
2679                         reg = FDI_RX_IIR(pipe);
2680                         temp = I915_READ(reg);
2681                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2682
2683                         if (temp & FDI_RX_BIT_LOCK ||
2684                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2685                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2686                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2687                                               i);
2688                                 break;
2689                         }
2690                         udelay(1); /* should be 0.5us */
2691                 }
2692                 if (i == 4) {
2693                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2694                         continue;
2695                 }
2696
2697                 /* Train 2 */
2698                 reg = FDI_TX_CTL(pipe);
2699                 temp = I915_READ(reg);
2700                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2701                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2702                 I915_WRITE(reg, temp);
2703
2704                 reg = FDI_RX_CTL(pipe);
2705                 temp = I915_READ(reg);
2706                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2707                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2708                 I915_WRITE(reg, temp);
2709
2710                 POSTING_READ(reg);
2711                 udelay(2); /* should be 1.5us */
2712
2713                 for (i = 0; i < 4; i++) {
2714                         reg = FDI_RX_IIR(pipe);
2715                         temp = I915_READ(reg);
2716                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2717
2718                         if (temp & FDI_RX_SYMBOL_LOCK ||
2719                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2720                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2721                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2722                                               i);
2723                                 goto train_done;
2724                         }
2725                         udelay(2); /* should be 1.5us */
2726                 }
2727                 if (i == 4)
2728                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2729         }
2730
2731 train_done:
2732         DRM_DEBUG_KMS("FDI train done.\n");
2733 }
2734
2735 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2736 {
2737         struct drm_device *dev = intel_crtc->base.dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         int pipe = intel_crtc->pipe;
2740         u32 reg, temp;
2741
2742
2743         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2744         reg = FDI_RX_CTL(pipe);
2745         temp = I915_READ(reg);
2746         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2747         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2748         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2749         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2750
2751         POSTING_READ(reg);
2752         udelay(200);
2753
2754         /* Switch from Rawclk to PCDclk */
2755         temp = I915_READ(reg);
2756         I915_WRITE(reg, temp | FDI_PCDCLK);
2757
2758         POSTING_READ(reg);
2759         udelay(200);
2760
2761         /* Enable CPU FDI TX PLL, always on for Ironlake */
2762         reg = FDI_TX_CTL(pipe);
2763         temp = I915_READ(reg);
2764         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2765                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2766
2767                 POSTING_READ(reg);
2768                 udelay(100);
2769         }
2770 }
2771
2772 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2773 {
2774         struct drm_device *dev = intel_crtc->base.dev;
2775         struct drm_i915_private *dev_priv = dev->dev_private;
2776         int pipe = intel_crtc->pipe;
2777         u32 reg, temp;
2778
2779         /* Switch from PCDclk to Rawclk */
2780         reg = FDI_RX_CTL(pipe);
2781         temp = I915_READ(reg);
2782         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2783
2784         /* Disable CPU FDI TX PLL */
2785         reg = FDI_TX_CTL(pipe);
2786         temp = I915_READ(reg);
2787         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2788
2789         POSTING_READ(reg);
2790         udelay(100);
2791
2792         reg = FDI_RX_CTL(pipe);
2793         temp = I915_READ(reg);
2794         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2795
2796         /* Wait for the clocks to turn off. */
2797         POSTING_READ(reg);
2798         udelay(100);
2799 }
2800
2801 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2802 {
2803         struct drm_device *dev = crtc->dev;
2804         struct drm_i915_private *dev_priv = dev->dev_private;
2805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2806         int pipe = intel_crtc->pipe;
2807         u32 reg, temp;
2808
2809         /* disable CPU FDI tx and PCH FDI rx */
2810         reg = FDI_TX_CTL(pipe);
2811         temp = I915_READ(reg);
2812         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2813         POSTING_READ(reg);
2814
2815         reg = FDI_RX_CTL(pipe);
2816         temp = I915_READ(reg);
2817         temp &= ~(0x7 << 16);
2818         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2819         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2820
2821         POSTING_READ(reg);
2822         udelay(100);
2823
2824         /* Ironlake workaround, disable clock pointer after downing FDI */
2825         if (HAS_PCH_IBX(dev)) {
2826                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2827         }
2828
2829         /* still set train pattern 1 */
2830         reg = FDI_TX_CTL(pipe);
2831         temp = I915_READ(reg);
2832         temp &= ~FDI_LINK_TRAIN_NONE;
2833         temp |= FDI_LINK_TRAIN_PATTERN_1;
2834         I915_WRITE(reg, temp);
2835
2836         reg = FDI_RX_CTL(pipe);
2837         temp = I915_READ(reg);
2838         if (HAS_PCH_CPT(dev)) {
2839                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841         } else {
2842                 temp &= ~FDI_LINK_TRAIN_NONE;
2843                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844         }
2845         /* BPC in FDI rx is consistent with that in PIPECONF */
2846         temp &= ~(0x07 << 16);
2847         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2848         I915_WRITE(reg, temp);
2849
2850         POSTING_READ(reg);
2851         udelay(100);
2852 }
2853
2854 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2855 {
2856         struct drm_device *dev = crtc->dev;
2857         struct drm_i915_private *dev_priv = dev->dev_private;
2858         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2859         unsigned long flags;
2860         bool pending;
2861
2862         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2863             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2864                 return false;
2865
2866         spin_lock_irqsave(&dev->event_lock, flags);
2867         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2868         spin_unlock_irqrestore(&dev->event_lock, flags);
2869
2870         return pending;
2871 }
2872
2873 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2874 {
2875         struct drm_device *dev = crtc->dev;
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877
2878         if (crtc->fb == NULL)
2879                 return;
2880
2881         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2882
2883         wait_event(dev_priv->pending_flip_queue,
2884                    !intel_crtc_has_pending_flip(crtc));
2885
2886         mutex_lock(&dev->struct_mutex);
2887         intel_finish_fb(crtc->fb);
2888         mutex_unlock(&dev->struct_mutex);
2889 }
2890
2891 /* Program iCLKIP clock to the desired frequency */
2892 static void lpt_program_iclkip(struct drm_crtc *crtc)
2893 {
2894         struct drm_device *dev = crtc->dev;
2895         struct drm_i915_private *dev_priv = dev->dev_private;
2896         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2897         u32 temp;
2898
2899         mutex_lock(&dev_priv->dpio_lock);
2900
2901         /* It is necessary to ungate the pixclk gate prior to programming
2902          * the divisors, and gate it back when it is done.
2903          */
2904         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2905
2906         /* Disable SSCCTL */
2907         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2908                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2909                                 SBI_SSCCTL_DISABLE,
2910                         SBI_ICLK);
2911
2912         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2913         if (crtc->mode.clock == 20000) {
2914                 auxdiv = 1;
2915                 divsel = 0x41;
2916                 phaseinc = 0x20;
2917         } else {
2918                 /* The iCLK virtual clock root frequency is in MHz,
2919                  * but the crtc->mode.clock in in KHz. To get the divisors,
2920                  * it is necessary to divide one by another, so we
2921                  * convert the virtual clock precision to KHz here for higher
2922                  * precision.
2923                  */
2924                 u32 iclk_virtual_root_freq = 172800 * 1000;
2925                 u32 iclk_pi_range = 64;
2926                 u32 desired_divisor, msb_divisor_value, pi_value;
2927
2928                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2929                 msb_divisor_value = desired_divisor / iclk_pi_range;
2930                 pi_value = desired_divisor % iclk_pi_range;
2931
2932                 auxdiv = 0;
2933                 divsel = msb_divisor_value - 2;
2934                 phaseinc = pi_value;
2935         }
2936
2937         /* This should not happen with any sane values */
2938         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2939                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2940         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2941                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2942
2943         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2944                         crtc->mode.clock,
2945                         auxdiv,
2946                         divsel,
2947                         phasedir,
2948                         phaseinc);
2949
2950         /* Program SSCDIVINTPHASE6 */
2951         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2952         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2953         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2954         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2955         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2956         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2957         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2958         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2959
2960         /* Program SSCAUXDIV */
2961         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2962         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2963         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2964         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2965
2966         /* Enable modulator and associated divider */
2967         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2968         temp &= ~SBI_SSCCTL_DISABLE;
2969         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2970
2971         /* Wait for initialization time */
2972         udelay(24);
2973
2974         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2975
2976         mutex_unlock(&dev_priv->dpio_lock);
2977 }
2978
2979 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2980                                                 enum pipe pch_transcoder)
2981 {
2982         struct drm_device *dev = crtc->base.dev;
2983         struct drm_i915_private *dev_priv = dev->dev_private;
2984         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2985
2986         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2987                    I915_READ(HTOTAL(cpu_transcoder)));
2988         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2989                    I915_READ(HBLANK(cpu_transcoder)));
2990         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2991                    I915_READ(HSYNC(cpu_transcoder)));
2992
2993         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2994                    I915_READ(VTOTAL(cpu_transcoder)));
2995         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2996                    I915_READ(VBLANK(cpu_transcoder)));
2997         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2998                    I915_READ(VSYNC(cpu_transcoder)));
2999         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3000                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3001 }
3002
3003 /*
3004  * Enable PCH resources required for PCH ports:
3005  *   - PCH PLLs
3006  *   - FDI training & RX/TX
3007  *   - update transcoder timings
3008  *   - DP transcoding bits
3009  *   - transcoder
3010  */
3011 static void ironlake_pch_enable(struct drm_crtc *crtc)
3012 {
3013         struct drm_device *dev = crtc->dev;
3014         struct drm_i915_private *dev_priv = dev->dev_private;
3015         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3016         int pipe = intel_crtc->pipe;
3017         u32 reg, temp;
3018
3019         assert_pch_transcoder_disabled(dev_priv, pipe);
3020
3021         /* Write the TU size bits before fdi link training, so that error
3022          * detection works. */
3023         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3024                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3025
3026         /* For PCH output, training FDI link */
3027         dev_priv->display.fdi_link_train(crtc);
3028
3029         /* We need to program the right clock selection before writing the pixel
3030          * mutliplier into the DPLL. */
3031         if (HAS_PCH_CPT(dev)) {
3032                 u32 sel;
3033
3034                 temp = I915_READ(PCH_DPLL_SEL);
3035                 temp |= TRANS_DPLL_ENABLE(pipe);
3036                 sel = TRANS_DPLLB_SEL(pipe);
3037                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3038                         temp |= sel;
3039                 else
3040                         temp &= ~sel;
3041                 I915_WRITE(PCH_DPLL_SEL, temp);
3042         }
3043
3044         /* XXX: pch pll's can be enabled any time before we enable the PCH
3045          * transcoder, and we actually should do this to not upset any PCH
3046          * transcoder that already use the clock when we share it.
3047          *
3048          * Note that enable_shared_dpll tries to do the right thing, but
3049          * get_shared_dpll unconditionally resets the pll - we need that to have
3050          * the right LVDS enable sequence. */
3051         ironlake_enable_shared_dpll(intel_crtc);
3052
3053         /* set transcoder timing, panel must allow it */
3054         assert_panel_unlocked(dev_priv, pipe);
3055         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3056
3057         intel_fdi_normal_train(crtc);
3058
3059         /* For PCH DP, enable TRANS_DP_CTL */
3060         if (HAS_PCH_CPT(dev) &&
3061             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3062              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3063                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3064                 reg = TRANS_DP_CTL(pipe);
3065                 temp = I915_READ(reg);
3066                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3067                           TRANS_DP_SYNC_MASK |
3068                           TRANS_DP_BPC_MASK);
3069                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3070                          TRANS_DP_ENH_FRAMING);
3071                 temp |= bpc << 9; /* same format but at 11:9 */
3072
3073                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3074                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3075                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3076                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3077
3078                 switch (intel_trans_dp_port_sel(crtc)) {
3079                 case PCH_DP_B:
3080                         temp |= TRANS_DP_PORT_SEL_B;
3081                         break;
3082                 case PCH_DP_C:
3083                         temp |= TRANS_DP_PORT_SEL_C;
3084                         break;
3085                 case PCH_DP_D:
3086                         temp |= TRANS_DP_PORT_SEL_D;
3087                         break;
3088                 default:
3089                         BUG();
3090                 }
3091
3092                 I915_WRITE(reg, temp);
3093         }
3094
3095         ironlake_enable_pch_transcoder(dev_priv, pipe);
3096 }
3097
3098 static void lpt_pch_enable(struct drm_crtc *crtc)
3099 {
3100         struct drm_device *dev = crtc->dev;
3101         struct drm_i915_private *dev_priv = dev->dev_private;
3102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3103         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3104
3105         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3106
3107         lpt_program_iclkip(crtc);
3108
3109         /* Set transcoder timing. */
3110         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3111
3112         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3113 }
3114
3115 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3116 {
3117         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3118
3119         if (pll == NULL)
3120                 return;
3121
3122         if (pll->refcount == 0) {
3123                 WARN(1, "bad %s refcount\n", pll->name);
3124                 return;
3125         }
3126
3127         if (--pll->refcount == 0) {
3128                 WARN_ON(pll->on);
3129                 WARN_ON(pll->active);
3130         }
3131
3132         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3133 }
3134
3135 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3136 {
3137         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3138         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3139         enum intel_dpll_id i;
3140
3141         if (pll) {
3142                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3143                               crtc->base.base.id, pll->name);
3144                 intel_put_shared_dpll(crtc);
3145         }
3146
3147         if (HAS_PCH_IBX(dev_priv->dev)) {
3148                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3149                 i = (enum intel_dpll_id) crtc->pipe;
3150                 pll = &dev_priv->shared_dplls[i];
3151
3152                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3153                               crtc->base.base.id, pll->name);
3154
3155                 goto found;
3156         }
3157
3158         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3159                 pll = &dev_priv->shared_dplls[i];
3160
3161                 /* Only want to check enabled timings first */
3162                 if (pll->refcount == 0)
3163                         continue;
3164
3165                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3166                            sizeof(pll->hw_state)) == 0) {
3167                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3168                                       crtc->base.base.id,
3169                                       pll->name, pll->refcount, pll->active);
3170
3171                         goto found;
3172                 }
3173         }
3174
3175         /* Ok no matching timings, maybe there's a free one? */
3176         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3177                 pll = &dev_priv->shared_dplls[i];
3178                 if (pll->refcount == 0) {
3179                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3180                                       crtc->base.base.id, pll->name);
3181                         goto found;
3182                 }
3183         }
3184
3185         return NULL;
3186
3187 found:
3188         crtc->config.shared_dpll = i;
3189         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3190                          pipe_name(crtc->pipe));
3191
3192         if (pll->active == 0) {
3193                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3194                        sizeof(pll->hw_state));
3195
3196                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3197                 WARN_ON(pll->on);
3198                 assert_shared_dpll_disabled(dev_priv, pll);
3199
3200                 pll->mode_set(dev_priv, pll);
3201         }
3202         pll->refcount++;
3203
3204         return pll;
3205 }
3206
3207 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3208 {
3209         struct drm_i915_private *dev_priv = dev->dev_private;
3210         int dslreg = PIPEDSL(pipe);
3211         u32 temp;
3212
3213         temp = I915_READ(dslreg);
3214         udelay(500);
3215         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3216                 if (wait_for(I915_READ(dslreg) != temp, 5))
3217                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3218         }
3219 }
3220
3221 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3222 {
3223         struct drm_device *dev = crtc->base.dev;
3224         struct drm_i915_private *dev_priv = dev->dev_private;
3225         int pipe = crtc->pipe;
3226
3227         if (crtc->config.pch_pfit.size) {
3228                 /* Force use of hard-coded filter coefficients
3229                  * as some pre-programmed values are broken,
3230                  * e.g. x201.
3231                  */
3232                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3233                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3234                                                  PF_PIPE_SEL_IVB(pipe));
3235                 else
3236                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3237                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3238                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3239         }
3240 }
3241
3242 static void intel_enable_planes(struct drm_crtc *crtc)
3243 {
3244         struct drm_device *dev = crtc->dev;
3245         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3246         struct intel_plane *intel_plane;
3247
3248         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3249                 if (intel_plane->pipe == pipe)
3250                         intel_plane_restore(&intel_plane->base);
3251 }
3252
3253 static void intel_disable_planes(struct drm_crtc *crtc)
3254 {
3255         struct drm_device *dev = crtc->dev;
3256         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3257         struct intel_plane *intel_plane;
3258
3259         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3260                 if (intel_plane->pipe == pipe)
3261                         intel_plane_disable(&intel_plane->base);
3262 }
3263
3264 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3265 {
3266         struct drm_device *dev = crtc->dev;
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269         struct intel_encoder *encoder;
3270         int pipe = intel_crtc->pipe;
3271         int plane = intel_crtc->plane;
3272
3273         WARN_ON(!crtc->enabled);
3274
3275         if (intel_crtc->active)
3276                 return;
3277
3278         intel_crtc->active = true;
3279
3280         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3281         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3282
3283         intel_update_watermarks(dev);
3284
3285         for_each_encoder_on_crtc(dev, crtc, encoder)
3286                 if (encoder->pre_enable)
3287                         encoder->pre_enable(encoder);
3288
3289         if (intel_crtc->config.has_pch_encoder) {
3290                 /* Note: FDI PLL enabling _must_ be done before we enable the
3291                  * cpu pipes, hence this is separate from all the other fdi/pch
3292                  * enabling. */
3293                 ironlake_fdi_pll_enable(intel_crtc);
3294         } else {
3295                 assert_fdi_tx_disabled(dev_priv, pipe);
3296                 assert_fdi_rx_disabled(dev_priv, pipe);
3297         }
3298
3299         ironlake_pfit_enable(intel_crtc);
3300
3301         /*
3302          * On ILK+ LUT must be loaded before the pipe is running but with
3303          * clocks enabled
3304          */
3305         intel_crtc_load_lut(crtc);
3306
3307         intel_enable_pipe(dev_priv, pipe,
3308                           intel_crtc->config.has_pch_encoder, false);
3309         intel_enable_plane(dev_priv, plane, pipe);
3310         intel_enable_planes(crtc);
3311         intel_crtc_update_cursor(crtc, true);
3312
3313         if (intel_crtc->config.has_pch_encoder)
3314                 ironlake_pch_enable(crtc);
3315
3316         mutex_lock(&dev->struct_mutex);
3317         intel_update_fbc(dev);
3318         mutex_unlock(&dev->struct_mutex);
3319
3320         for_each_encoder_on_crtc(dev, crtc, encoder)
3321                 encoder->enable(encoder);
3322
3323         if (HAS_PCH_CPT(dev))
3324                 cpt_verify_modeset(dev, intel_crtc->pipe);
3325
3326         /*
3327          * There seems to be a race in PCH platform hw (at least on some
3328          * outputs) where an enabled pipe still completes any pageflip right
3329          * away (as if the pipe is off) instead of waiting for vblank. As soon
3330          * as the first vblank happend, everything works as expected. Hence just
3331          * wait for one vblank before returning to avoid strange things
3332          * happening.
3333          */
3334         intel_wait_for_vblank(dev, intel_crtc->pipe);
3335 }
3336
3337 /* IPS only exists on ULT machines and is tied to pipe A. */
3338 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3339 {
3340         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3341 }
3342
3343 static void hsw_enable_ips(struct intel_crtc *crtc)
3344 {
3345         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3346
3347         if (!crtc->config.ips_enabled)
3348                 return;
3349
3350         /* We can only enable IPS after we enable a plane and wait for a vblank.
3351          * We guarantee that the plane is enabled by calling intel_enable_ips
3352          * only after intel_enable_plane. And intel_enable_plane already waits
3353          * for a vblank, so all we need to do here is to enable the IPS bit. */
3354         assert_plane_enabled(dev_priv, crtc->plane);
3355         I915_WRITE(IPS_CTL, IPS_ENABLE);
3356 }
3357
3358 static void hsw_disable_ips(struct intel_crtc *crtc)
3359 {
3360         struct drm_device *dev = crtc->base.dev;
3361         struct drm_i915_private *dev_priv = dev->dev_private;
3362
3363         if (!crtc->config.ips_enabled)
3364                 return;
3365
3366         assert_plane_enabled(dev_priv, crtc->plane);
3367         I915_WRITE(IPS_CTL, 0);
3368
3369         /* We need to wait for a vblank before we can disable the plane. */
3370         intel_wait_for_vblank(dev, crtc->pipe);
3371 }
3372
3373 static void haswell_crtc_enable(struct drm_crtc *crtc)
3374 {
3375         struct drm_device *dev = crtc->dev;
3376         struct drm_i915_private *dev_priv = dev->dev_private;
3377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3378         struct intel_encoder *encoder;
3379         int pipe = intel_crtc->pipe;
3380         int plane = intel_crtc->plane;
3381
3382         WARN_ON(!crtc->enabled);
3383
3384         if (intel_crtc->active)
3385                 return;
3386
3387         intel_crtc->active = true;
3388
3389         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3390         if (intel_crtc->config.has_pch_encoder)
3391                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3392
3393         intel_update_watermarks(dev);
3394
3395         if (intel_crtc->config.has_pch_encoder)
3396                 dev_priv->display.fdi_link_train(crtc);
3397
3398         for_each_encoder_on_crtc(dev, crtc, encoder)
3399                 if (encoder->pre_enable)
3400                         encoder->pre_enable(encoder);
3401
3402         intel_ddi_enable_pipe_clock(intel_crtc);
3403
3404         ironlake_pfit_enable(intel_crtc);
3405
3406         /*
3407          * On ILK+ LUT must be loaded before the pipe is running but with
3408          * clocks enabled
3409          */
3410         intel_crtc_load_lut(crtc);
3411
3412         intel_ddi_set_pipe_settings(crtc);
3413         intel_ddi_enable_transcoder_func(crtc);
3414
3415         intel_enable_pipe(dev_priv, pipe,
3416                           intel_crtc->config.has_pch_encoder, false);
3417         intel_enable_plane(dev_priv, plane, pipe);
3418         intel_enable_planes(crtc);
3419         intel_crtc_update_cursor(crtc, true);
3420
3421         hsw_enable_ips(intel_crtc);
3422
3423         if (intel_crtc->config.has_pch_encoder)
3424                 lpt_pch_enable(crtc);
3425
3426         mutex_lock(&dev->struct_mutex);
3427         intel_update_fbc(dev);
3428         mutex_unlock(&dev->struct_mutex);
3429
3430         for_each_encoder_on_crtc(dev, crtc, encoder)
3431                 encoder->enable(encoder);
3432
3433         /*
3434          * There seems to be a race in PCH platform hw (at least on some
3435          * outputs) where an enabled pipe still completes any pageflip right
3436          * away (as if the pipe is off) instead of waiting for vblank. As soon
3437          * as the first vblank happend, everything works as expected. Hence just
3438          * wait for one vblank before returning to avoid strange things
3439          * happening.
3440          */
3441         intel_wait_for_vblank(dev, intel_crtc->pipe);
3442 }
3443
3444 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3445 {
3446         struct drm_device *dev = crtc->base.dev;
3447         struct drm_i915_private *dev_priv = dev->dev_private;
3448         int pipe = crtc->pipe;
3449
3450         /* To avoid upsetting the power well on haswell only disable the pfit if
3451          * it's in use. The hw state code will make sure we get this right. */
3452         if (crtc->config.pch_pfit.size) {
3453                 I915_WRITE(PF_CTL(pipe), 0);
3454                 I915_WRITE(PF_WIN_POS(pipe), 0);
3455                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3456         }
3457 }
3458
3459 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3460 {
3461         struct drm_device *dev = crtc->dev;
3462         struct drm_i915_private *dev_priv = dev->dev_private;
3463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3464         struct intel_encoder *encoder;
3465         int pipe = intel_crtc->pipe;
3466         int plane = intel_crtc->plane;
3467         u32 reg, temp;
3468
3469
3470         if (!intel_crtc->active)
3471                 return;
3472
3473         for_each_encoder_on_crtc(dev, crtc, encoder)
3474                 encoder->disable(encoder);
3475
3476         intel_crtc_wait_for_pending_flips(crtc);
3477         drm_vblank_off(dev, pipe);
3478
3479         if (dev_priv->fbc.plane == plane)
3480                 intel_disable_fbc(dev);
3481
3482         intel_crtc_update_cursor(crtc, false);
3483         intel_disable_planes(crtc);
3484         intel_disable_plane(dev_priv, plane, pipe);
3485
3486         if (intel_crtc->config.has_pch_encoder)
3487                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3488
3489         intel_disable_pipe(dev_priv, pipe);
3490
3491         ironlake_pfit_disable(intel_crtc);
3492
3493         for_each_encoder_on_crtc(dev, crtc, encoder)
3494                 if (encoder->post_disable)
3495                         encoder->post_disable(encoder);
3496
3497         if (intel_crtc->config.has_pch_encoder) {
3498                 ironlake_fdi_disable(crtc);
3499
3500                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3501                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3502
3503                 if (HAS_PCH_CPT(dev)) {
3504                         /* disable TRANS_DP_CTL */
3505                         reg = TRANS_DP_CTL(pipe);
3506                         temp = I915_READ(reg);
3507                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3508                                   TRANS_DP_PORT_SEL_MASK);
3509                         temp |= TRANS_DP_PORT_SEL_NONE;
3510                         I915_WRITE(reg, temp);
3511
3512                         /* disable DPLL_SEL */
3513                         temp = I915_READ(PCH_DPLL_SEL);
3514                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3515                         I915_WRITE(PCH_DPLL_SEL, temp);
3516                 }
3517
3518                 /* disable PCH DPLL */
3519                 intel_disable_shared_dpll(intel_crtc);
3520
3521                 ironlake_fdi_pll_disable(intel_crtc);
3522         }
3523
3524         intel_crtc->active = false;
3525         intel_update_watermarks(dev);
3526
3527         mutex_lock(&dev->struct_mutex);
3528         intel_update_fbc(dev);
3529         mutex_unlock(&dev->struct_mutex);
3530 }
3531
3532 static void haswell_crtc_disable(struct drm_crtc *crtc)
3533 {
3534         struct drm_device *dev = crtc->dev;
3535         struct drm_i915_private *dev_priv = dev->dev_private;
3536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3537         struct intel_encoder *encoder;
3538         int pipe = intel_crtc->pipe;
3539         int plane = intel_crtc->plane;
3540         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3541
3542         if (!intel_crtc->active)
3543                 return;
3544
3545         for_each_encoder_on_crtc(dev, crtc, encoder)
3546                 encoder->disable(encoder);
3547
3548         intel_crtc_wait_for_pending_flips(crtc);
3549         drm_vblank_off(dev, pipe);
3550
3551         /* FBC must be disabled before disabling the plane on HSW. */
3552         if (dev_priv->fbc.plane == plane)
3553                 intel_disable_fbc(dev);
3554
3555         hsw_disable_ips(intel_crtc);
3556
3557         intel_crtc_update_cursor(crtc, false);
3558         intel_disable_planes(crtc);
3559         intel_disable_plane(dev_priv, plane, pipe);
3560
3561         if (intel_crtc->config.has_pch_encoder)
3562                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3563         intel_disable_pipe(dev_priv, pipe);
3564
3565         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3566
3567         ironlake_pfit_disable(intel_crtc);
3568
3569         intel_ddi_disable_pipe_clock(intel_crtc);
3570
3571         for_each_encoder_on_crtc(dev, crtc, encoder)
3572                 if (encoder->post_disable)
3573                         encoder->post_disable(encoder);
3574
3575         if (intel_crtc->config.has_pch_encoder) {
3576                 lpt_disable_pch_transcoder(dev_priv);
3577                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3578                 intel_ddi_fdi_disable(crtc);
3579         }
3580
3581         intel_crtc->active = false;
3582         intel_update_watermarks(dev);
3583
3584         mutex_lock(&dev->struct_mutex);
3585         intel_update_fbc(dev);
3586         mutex_unlock(&dev->struct_mutex);
3587 }
3588
3589 static void ironlake_crtc_off(struct drm_crtc *crtc)
3590 {
3591         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592         intel_put_shared_dpll(intel_crtc);
3593 }
3594
3595 static void haswell_crtc_off(struct drm_crtc *crtc)
3596 {
3597         intel_ddi_put_crtc_pll(crtc);
3598 }
3599
3600 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3601 {
3602         if (!enable && intel_crtc->overlay) {
3603                 struct drm_device *dev = intel_crtc->base.dev;
3604                 struct drm_i915_private *dev_priv = dev->dev_private;
3605
3606                 mutex_lock(&dev->struct_mutex);
3607                 dev_priv->mm.interruptible = false;
3608                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3609                 dev_priv->mm.interruptible = true;
3610                 mutex_unlock(&dev->struct_mutex);
3611         }
3612
3613         /* Let userspace switch the overlay on again. In most cases userspace
3614          * has to recompute where to put it anyway.
3615          */
3616 }
3617
3618 /**
3619  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3620  * cursor plane briefly if not already running after enabling the display
3621  * plane.
3622  * This workaround avoids occasional blank screens when self refresh is
3623  * enabled.
3624  */
3625 static void
3626 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3627 {
3628         u32 cntl = I915_READ(CURCNTR(pipe));
3629
3630         if ((cntl & CURSOR_MODE) == 0) {
3631                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3632
3633                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3634                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3635                 intel_wait_for_vblank(dev_priv->dev, pipe);
3636                 I915_WRITE(CURCNTR(pipe), cntl);
3637                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3638                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3639         }
3640 }
3641
3642 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3643 {
3644         struct drm_device *dev = crtc->base.dev;
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         struct intel_crtc_config *pipe_config = &crtc->config;
3647
3648         if (!crtc->config.gmch_pfit.control)
3649                 return;
3650
3651         /*
3652          * The panel fitter should only be adjusted whilst the pipe is disabled,
3653          * according to register description and PRM.
3654          */
3655         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3656         assert_pipe_disabled(dev_priv, crtc->pipe);
3657
3658         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3659         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3660
3661         /* Border color in case we don't scale up to the full screen. Black by
3662          * default, change to something else for debugging. */
3663         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3664 }
3665
3666 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3667 {
3668         struct drm_device *dev = crtc->dev;
3669         struct drm_i915_private *dev_priv = dev->dev_private;
3670         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671         struct intel_encoder *encoder;
3672         int pipe = intel_crtc->pipe;
3673         int plane = intel_crtc->plane;
3674         bool is_dsi;
3675
3676         WARN_ON(!crtc->enabled);
3677
3678         if (intel_crtc->active)
3679                 return;
3680
3681         intel_crtc->active = true;
3682         intel_update_watermarks(dev);
3683
3684         for_each_encoder_on_crtc(dev, crtc, encoder)
3685                 if (encoder->pre_pll_enable)
3686                         encoder->pre_pll_enable(encoder);
3687
3688         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3689
3690         if (!is_dsi)
3691                 vlv_enable_pll(intel_crtc);
3692
3693         for_each_encoder_on_crtc(dev, crtc, encoder)
3694                 if (encoder->pre_enable)
3695                         encoder->pre_enable(encoder);
3696
3697         i9xx_pfit_enable(intel_crtc);
3698
3699         intel_crtc_load_lut(crtc);
3700
3701         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3702         intel_enable_plane(dev_priv, plane, pipe);
3703         intel_enable_planes(crtc);
3704         intel_crtc_update_cursor(crtc, true);
3705
3706         intel_update_fbc(dev);
3707
3708         for_each_encoder_on_crtc(dev, crtc, encoder)
3709                 encoder->enable(encoder);
3710 }
3711
3712 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3713 {
3714         struct drm_device *dev = crtc->dev;
3715         struct drm_i915_private *dev_priv = dev->dev_private;
3716         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3717         struct intel_encoder *encoder;
3718         int pipe = intel_crtc->pipe;
3719         int plane = intel_crtc->plane;
3720
3721         WARN_ON(!crtc->enabled);
3722
3723         if (intel_crtc->active)
3724                 return;
3725
3726         intel_crtc->active = true;
3727         intel_update_watermarks(dev);
3728
3729         for_each_encoder_on_crtc(dev, crtc, encoder)
3730                 if (encoder->pre_enable)
3731                         encoder->pre_enable(encoder);
3732
3733         i9xx_enable_pll(intel_crtc);
3734
3735         i9xx_pfit_enable(intel_crtc);
3736
3737         intel_crtc_load_lut(crtc);
3738
3739         intel_enable_pipe(dev_priv, pipe, false, false);
3740         intel_enable_plane(dev_priv, plane, pipe);
3741         intel_enable_planes(crtc);
3742         /* The fixup needs to happen before cursor is enabled */
3743         if (IS_G4X(dev))
3744                 g4x_fixup_plane(dev_priv, pipe);
3745         intel_crtc_update_cursor(crtc, true);
3746
3747         /* Give the overlay scaler a chance to enable if it's on this pipe */
3748         intel_crtc_dpms_overlay(intel_crtc, true);
3749
3750         intel_update_fbc(dev);
3751
3752         for_each_encoder_on_crtc(dev, crtc, encoder)
3753                 encoder->enable(encoder);
3754 }
3755
3756 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3757 {
3758         struct drm_device *dev = crtc->base.dev;
3759         struct drm_i915_private *dev_priv = dev->dev_private;
3760
3761         if (!crtc->config.gmch_pfit.control)
3762                 return;
3763
3764         assert_pipe_disabled(dev_priv, crtc->pipe);
3765
3766         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3767                          I915_READ(PFIT_CONTROL));
3768         I915_WRITE(PFIT_CONTROL, 0);
3769 }
3770
3771 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3772 {
3773         struct drm_device *dev = crtc->dev;
3774         struct drm_i915_private *dev_priv = dev->dev_private;
3775         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3776         struct intel_encoder *encoder;
3777         int pipe = intel_crtc->pipe;
3778         int plane = intel_crtc->plane;
3779
3780         if (!intel_crtc->active)
3781                 return;
3782
3783         for_each_encoder_on_crtc(dev, crtc, encoder)
3784                 encoder->disable(encoder);
3785
3786         /* Give the overlay scaler a chance to disable if it's on this pipe */
3787         intel_crtc_wait_for_pending_flips(crtc);
3788         drm_vblank_off(dev, pipe);
3789
3790         if (dev_priv->fbc.plane == plane)
3791                 intel_disable_fbc(dev);
3792
3793         intel_crtc_dpms_overlay(intel_crtc, false);
3794         intel_crtc_update_cursor(crtc, false);
3795         intel_disable_planes(crtc);
3796         intel_disable_plane(dev_priv, plane, pipe);
3797
3798         intel_disable_pipe(dev_priv, pipe);
3799
3800         i9xx_pfit_disable(intel_crtc);
3801
3802         for_each_encoder_on_crtc(dev, crtc, encoder)
3803                 if (encoder->post_disable)
3804                         encoder->post_disable(encoder);
3805
3806         if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3807                 i9xx_disable_pll(dev_priv, pipe);
3808
3809         intel_crtc->active = false;
3810         intel_update_fbc(dev);
3811         intel_update_watermarks(dev);
3812 }
3813
3814 static void i9xx_crtc_off(struct drm_crtc *crtc)
3815 {
3816 }
3817
3818 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3819                                     bool enabled)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_master_private *master_priv;
3823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3824         int pipe = intel_crtc->pipe;
3825
3826         if (!dev->primary->master)
3827                 return;
3828
3829         master_priv = dev->primary->master->driver_priv;
3830         if (!master_priv->sarea_priv)
3831                 return;
3832
3833         switch (pipe) {
3834         case 0:
3835                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3836                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3837                 break;
3838         case 1:
3839                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3840                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3841                 break;
3842         default:
3843                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3844                 break;
3845         }
3846 }
3847
3848 /**
3849  * Sets the power management mode of the pipe and plane.
3850  */
3851 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3852 {
3853         struct drm_device *dev = crtc->dev;
3854         struct drm_i915_private *dev_priv = dev->dev_private;
3855         struct intel_encoder *intel_encoder;
3856         bool enable = false;
3857
3858         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3859                 enable |= intel_encoder->connectors_active;
3860
3861         if (enable)
3862                 dev_priv->display.crtc_enable(crtc);
3863         else
3864                 dev_priv->display.crtc_disable(crtc);
3865
3866         intel_crtc_update_sarea(crtc, enable);
3867 }
3868
3869 static void intel_crtc_disable(struct drm_crtc *crtc)
3870 {
3871         struct drm_device *dev = crtc->dev;
3872         struct drm_connector *connector;
3873         struct drm_i915_private *dev_priv = dev->dev_private;
3874         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875
3876         /* crtc should still be enabled when we disable it. */
3877         WARN_ON(!crtc->enabled);
3878
3879         dev_priv->display.crtc_disable(crtc);
3880         intel_crtc->eld_vld = false;
3881         intel_crtc_update_sarea(crtc, false);
3882         dev_priv->display.off(crtc);
3883
3884         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3885         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3886
3887         if (crtc->fb) {
3888                 mutex_lock(&dev->struct_mutex);
3889                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3890                 mutex_unlock(&dev->struct_mutex);
3891                 crtc->fb = NULL;
3892         }
3893
3894         /* Update computed state. */
3895         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3896                 if (!connector->encoder || !connector->encoder->crtc)
3897                         continue;
3898
3899                 if (connector->encoder->crtc != crtc)
3900                         continue;
3901
3902                 connector->dpms = DRM_MODE_DPMS_OFF;
3903                 to_intel_encoder(connector->encoder)->connectors_active = false;
3904         }
3905 }
3906
3907 void intel_encoder_destroy(struct drm_encoder *encoder)
3908 {
3909         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3910
3911         drm_encoder_cleanup(encoder);
3912         kfree(intel_encoder);
3913 }
3914
3915 /* Simple dpms helper for encoders with just one connector, no cloning and only
3916  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3917  * state of the entire output pipe. */
3918 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3919 {
3920         if (mode == DRM_MODE_DPMS_ON) {
3921                 encoder->connectors_active = true;
3922
3923                 intel_crtc_update_dpms(encoder->base.crtc);
3924         } else {
3925                 encoder->connectors_active = false;
3926
3927                 intel_crtc_update_dpms(encoder->base.crtc);
3928         }
3929 }
3930
3931 /* Cross check the actual hw state with our own modeset state tracking (and it's
3932  * internal consistency). */
3933 static void intel_connector_check_state(struct intel_connector *connector)
3934 {
3935         if (connector->get_hw_state(connector)) {
3936                 struct intel_encoder *encoder = connector->encoder;
3937                 struct drm_crtc *crtc;
3938                 bool encoder_enabled;
3939                 enum pipe pipe;
3940
3941                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3942                               connector->base.base.id,
3943                               drm_get_connector_name(&connector->base));
3944
3945                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3946                      "wrong connector dpms state\n");
3947                 WARN(connector->base.encoder != &encoder->base,
3948                      "active connector not linked to encoder\n");
3949                 WARN(!encoder->connectors_active,
3950                      "encoder->connectors_active not set\n");
3951
3952                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3953                 WARN(!encoder_enabled, "encoder not enabled\n");
3954                 if (WARN_ON(!encoder->base.crtc))
3955                         return;
3956
3957                 crtc = encoder->base.crtc;
3958
3959                 WARN(!crtc->enabled, "crtc not enabled\n");
3960                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3961                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3962                      "encoder active on the wrong pipe\n");
3963         }
3964 }
3965
3966 /* Even simpler default implementation, if there's really no special case to
3967  * consider. */
3968 void intel_connector_dpms(struct drm_connector *connector, int mode)
3969 {
3970         struct intel_encoder *encoder = intel_attached_encoder(connector);
3971
3972         /* All the simple cases only support two dpms states. */
3973         if (mode != DRM_MODE_DPMS_ON)
3974                 mode = DRM_MODE_DPMS_OFF;
3975
3976         if (mode == connector->dpms)
3977                 return;
3978
3979         connector->dpms = mode;
3980
3981         /* Only need to change hw state when actually enabled */
3982         if (encoder->base.crtc)
3983                 intel_encoder_dpms(encoder, mode);
3984         else
3985                 WARN_ON(encoder->connectors_active != false);
3986
3987         intel_modeset_check_state(connector->dev);
3988 }
3989
3990 /* Simple connector->get_hw_state implementation for encoders that support only
3991  * one connector and no cloning and hence the encoder state determines the state
3992  * of the connector. */
3993 bool intel_connector_get_hw_state(struct intel_connector *connector)
3994 {
3995         enum pipe pipe = 0;
3996         struct intel_encoder *encoder = connector->encoder;
3997
3998         return encoder->get_hw_state(encoder, &pipe);
3999 }
4000
4001 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4002                                      struct intel_crtc_config *pipe_config)
4003 {
4004         struct drm_i915_private *dev_priv = dev->dev_private;
4005         struct intel_crtc *pipe_B_crtc =
4006                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4007
4008         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4009                       pipe_name(pipe), pipe_config->fdi_lanes);
4010         if (pipe_config->fdi_lanes > 4) {
4011                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4012                               pipe_name(pipe), pipe_config->fdi_lanes);
4013                 return false;
4014         }
4015
4016         if (IS_HASWELL(dev)) {
4017                 if (pipe_config->fdi_lanes > 2) {
4018                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4019                                       pipe_config->fdi_lanes);
4020                         return false;
4021                 } else {
4022                         return true;
4023                 }
4024         }
4025
4026         if (INTEL_INFO(dev)->num_pipes == 2)
4027                 return true;
4028
4029         /* Ivybridge 3 pipe is really complicated */
4030         switch (pipe) {
4031         case PIPE_A:
4032                 return true;
4033         case PIPE_B:
4034                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4035                     pipe_config->fdi_lanes > 2) {
4036                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4037                                       pipe_name(pipe), pipe_config->fdi_lanes);
4038                         return false;
4039                 }
4040                 return true;
4041         case PIPE_C:
4042                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4043                     pipe_B_crtc->config.fdi_lanes <= 2) {
4044                         if (pipe_config->fdi_lanes > 2) {
4045                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4046                                               pipe_name(pipe), pipe_config->fdi_lanes);
4047                                 return false;
4048                         }
4049                 } else {
4050                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4051                         return false;
4052                 }
4053                 return true;
4054         default:
4055                 BUG();
4056         }
4057 }
4058
4059 #define RETRY 1
4060 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4061                                        struct intel_crtc_config *pipe_config)
4062 {
4063         struct drm_device *dev = intel_crtc->base.dev;
4064         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4065         int lane, link_bw, fdi_dotclock;
4066         bool setup_ok, needs_recompute = false;
4067
4068 retry:
4069         /* FDI is a binary signal running at ~2.7GHz, encoding
4070          * each output octet as 10 bits. The actual frequency
4071          * is stored as a divider into a 100MHz clock, and the
4072          * mode pixel clock is stored in units of 1KHz.
4073          * Hence the bw of each lane in terms of the mode signal
4074          * is:
4075          */
4076         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4077
4078         fdi_dotclock = adjusted_mode->clock;
4079         fdi_dotclock /= pipe_config->pixel_multiplier;
4080
4081         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4082                                            pipe_config->pipe_bpp);
4083
4084         pipe_config->fdi_lanes = lane;
4085
4086         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4087                                link_bw, &pipe_config->fdi_m_n);
4088
4089         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4090                                             intel_crtc->pipe, pipe_config);
4091         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4092                 pipe_config->pipe_bpp -= 2*3;
4093                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4094                               pipe_config->pipe_bpp);
4095                 needs_recompute = true;
4096                 pipe_config->bw_constrained = true;
4097
4098                 goto retry;
4099         }
4100
4101         if (needs_recompute)
4102                 return RETRY;
4103
4104         return setup_ok ? 0 : -EINVAL;
4105 }
4106
4107 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4108                                    struct intel_crtc_config *pipe_config)
4109 {
4110         pipe_config->ips_enabled = i915_enable_ips &&
4111                                    hsw_crtc_supports_ips(crtc) &&
4112                                    pipe_config->pipe_bpp <= 24;
4113 }
4114
4115 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4116                                      struct intel_crtc_config *pipe_config)
4117 {
4118         struct drm_device *dev = crtc->base.dev;
4119         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4120
4121         if (HAS_PCH_SPLIT(dev)) {
4122                 /* FDI link clock is fixed at 2.7G */
4123                 if (pipe_config->requested_mode.clock * 3
4124                     > IRONLAKE_FDI_FREQ * 4)
4125                         return -EINVAL;
4126         }
4127
4128         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4130          */
4131         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4133                 return -EINVAL;
4134
4135         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4136                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4137         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4138                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139                  * for lvds. */
4140                 pipe_config->pipe_bpp = 8*3;
4141         }
4142
4143         if (HAS_IPS(dev))
4144                 hsw_compute_ips_config(crtc, pipe_config);
4145
4146         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4147          * clock survives for now. */
4148         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4149                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4150
4151         if (pipe_config->has_pch_encoder)
4152                 return ironlake_fdi_compute_config(crtc, pipe_config);
4153
4154         return 0;
4155 }
4156
4157 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4158 {
4159         return 400000; /* FIXME */
4160 }
4161
4162 static int i945_get_display_clock_speed(struct drm_device *dev)
4163 {
4164         return 400000;
4165 }
4166
4167 static int i915_get_display_clock_speed(struct drm_device *dev)
4168 {
4169         return 333000;
4170 }
4171
4172 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4173 {
4174         return 200000;
4175 }
4176
4177 static int pnv_get_display_clock_speed(struct drm_device *dev)
4178 {
4179         u16 gcfgc = 0;
4180
4181         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4182
4183         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4184         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4185                 return 267000;
4186         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4187                 return 333000;
4188         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4189                 return 444000;
4190         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4191                 return 200000;
4192         default:
4193                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4194         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4195                 return 133000;
4196         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4197                 return 167000;
4198         }
4199 }
4200
4201 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4202 {
4203         u16 gcfgc = 0;
4204
4205         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4206
4207         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4208                 return 133000;
4209         else {
4210                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4211                 case GC_DISPLAY_CLOCK_333_MHZ:
4212                         return 333000;
4213                 default:
4214                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4215                         return 190000;
4216                 }
4217         }
4218 }
4219
4220 static int i865_get_display_clock_speed(struct drm_device *dev)
4221 {
4222         return 266000;
4223 }
4224
4225 static int i855_get_display_clock_speed(struct drm_device *dev)
4226 {
4227         u16 hpllcc = 0;
4228         /* Assume that the hardware is in the high speed state.  This
4229          * should be the default.
4230          */
4231         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4232         case GC_CLOCK_133_200:
4233         case GC_CLOCK_100_200:
4234                 return 200000;
4235         case GC_CLOCK_166_250:
4236                 return 250000;
4237         case GC_CLOCK_100_133:
4238                 return 133000;
4239         }
4240
4241         /* Shouldn't happen */
4242         return 0;
4243 }
4244
4245 static int i830_get_display_clock_speed(struct drm_device *dev)
4246 {
4247         return 133000;
4248 }
4249
4250 static void
4251 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4252 {
4253         while (*num > DATA_LINK_M_N_MASK ||
4254                *den > DATA_LINK_M_N_MASK) {
4255                 *num >>= 1;
4256                 *den >>= 1;
4257         }
4258 }
4259
4260 static void compute_m_n(unsigned int m, unsigned int n,
4261                         uint32_t *ret_m, uint32_t *ret_n)
4262 {
4263         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4264         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4265         intel_reduce_m_n_ratio(ret_m, ret_n);
4266 }
4267
4268 void
4269 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4270                        int pixel_clock, int link_clock,
4271                        struct intel_link_m_n *m_n)
4272 {
4273         m_n->tu = 64;
4274
4275         compute_m_n(bits_per_pixel * pixel_clock,
4276                     link_clock * nlanes * 8,
4277                     &m_n->gmch_m, &m_n->gmch_n);
4278
4279         compute_m_n(pixel_clock, link_clock,
4280                     &m_n->link_m, &m_n->link_n);
4281 }
4282
4283 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4284 {
4285         if (i915_panel_use_ssc >= 0)
4286                 return i915_panel_use_ssc != 0;
4287         return dev_priv->vbt.lvds_use_ssc
4288                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4289 }
4290
4291 static int vlv_get_refclk(struct drm_crtc *crtc)
4292 {
4293         struct drm_device *dev = crtc->dev;
4294         struct drm_i915_private *dev_priv = dev->dev_private;
4295         int refclk = 27000; /* for DP & HDMI */
4296
4297         return 100000; /* only one validated so far */
4298
4299         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4300                 refclk = 96000;
4301         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4302                 if (intel_panel_use_ssc(dev_priv))
4303                         refclk = 100000;
4304                 else
4305                         refclk = 96000;
4306         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4307                 refclk = 100000;
4308         }
4309
4310         return refclk;
4311 }
4312
4313 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4314 {
4315         struct drm_device *dev = crtc->dev;
4316         struct drm_i915_private *dev_priv = dev->dev_private;
4317         int refclk;
4318
4319         if (IS_VALLEYVIEW(dev)) {
4320                 refclk = vlv_get_refclk(crtc);
4321         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4322             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4323                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4324                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4325                               refclk / 1000);
4326         } else if (!IS_GEN2(dev)) {
4327                 refclk = 96000;
4328         } else {
4329                 refclk = 48000;
4330         }
4331
4332         return refclk;
4333 }
4334
4335 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4336 {
4337         return (1 << dpll->n) << 16 | dpll->m2;
4338 }
4339
4340 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4341 {
4342         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4343 }
4344
4345 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4346                                      intel_clock_t *reduced_clock)
4347 {
4348         struct drm_device *dev = crtc->base.dev;
4349         struct drm_i915_private *dev_priv = dev->dev_private;
4350         int pipe = crtc->pipe;
4351         u32 fp, fp2 = 0;
4352
4353         if (IS_PINEVIEW(dev)) {
4354                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4355                 if (reduced_clock)
4356                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4357         } else {
4358                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4359                 if (reduced_clock)
4360                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4361         }
4362
4363         I915_WRITE(FP0(pipe), fp);
4364         crtc->config.dpll_hw_state.fp0 = fp;
4365
4366         crtc->lowfreq_avail = false;
4367         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4368             reduced_clock && i915_powersave) {
4369                 I915_WRITE(FP1(pipe), fp2);
4370                 crtc->config.dpll_hw_state.fp1 = fp2;
4371                 crtc->lowfreq_avail = true;
4372         } else {
4373                 I915_WRITE(FP1(pipe), fp);
4374                 crtc->config.dpll_hw_state.fp1 = fp;
4375         }
4376 }
4377
4378 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4379 {
4380         u32 reg_val;
4381
4382         /*
4383          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4384          * and set it to a reasonable value instead.
4385          */
4386         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4387         reg_val &= 0xffffff00;
4388         reg_val |= 0x00000030;
4389         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4390
4391         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4392         reg_val &= 0x8cffffff;
4393         reg_val = 0x8c000000;
4394         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4395
4396         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4397         reg_val &= 0xffffff00;
4398         vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4399
4400         reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4401         reg_val &= 0x00ffffff;
4402         reg_val |= 0xb0000000;
4403         vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4404 }
4405
4406 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4407                                          struct intel_link_m_n *m_n)
4408 {
4409         struct drm_device *dev = crtc->base.dev;
4410         struct drm_i915_private *dev_priv = dev->dev_private;
4411         int pipe = crtc->pipe;
4412
4413         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4414         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4415         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4416         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4417 }
4418
4419 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4420                                          struct intel_link_m_n *m_n)
4421 {
4422         struct drm_device *dev = crtc->base.dev;
4423         struct drm_i915_private *dev_priv = dev->dev_private;
4424         int pipe = crtc->pipe;
4425         enum transcoder transcoder = crtc->config.cpu_transcoder;
4426
4427         if (INTEL_INFO(dev)->gen >= 5) {
4428                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4429                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4430                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4431                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4432         } else {
4433                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4434                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4435                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4436                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4437         }
4438 }
4439
4440 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4441 {
4442         if (crtc->config.has_pch_encoder)
4443                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4444         else
4445                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4446 }
4447
4448 static void vlv_update_pll(struct intel_crtc *crtc)
4449 {
4450         struct drm_device *dev = crtc->base.dev;
4451         struct drm_i915_private *dev_priv = dev->dev_private;
4452         int pipe = crtc->pipe;
4453         u32 dpll, mdiv;
4454         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4455         u32 coreclk, reg_val, dpll_md;
4456
4457         mutex_lock(&dev_priv->dpio_lock);
4458
4459         bestn = crtc->config.dpll.n;
4460         bestm1 = crtc->config.dpll.m1;
4461         bestm2 = crtc->config.dpll.m2;
4462         bestp1 = crtc->config.dpll.p1;
4463         bestp2 = crtc->config.dpll.p2;
4464
4465         /* See eDP HDMI DPIO driver vbios notes doc */
4466
4467         /* PLL B needs special handling */
4468         if (pipe)
4469                 vlv_pllb_recal_opamp(dev_priv);
4470
4471         /* Set up Tx target for periodic Rcomp update */
4472         vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4473
4474         /* Disable target IRef on PLL */
4475         reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4476         reg_val &= 0x00ffffff;
4477         vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4478
4479         /* Disable fast lock */
4480         vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4481
4482         /* Set idtafcrecal before PLL is enabled */
4483         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4484         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4485         mdiv |= ((bestn << DPIO_N_SHIFT));
4486         mdiv |= (1 << DPIO_K_SHIFT);
4487
4488         /*
4489          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4490          * but we don't support that).
4491          * Note: don't use the DAC post divider as it seems unstable.
4492          */
4493         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4494         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4495
4496         mdiv |= DPIO_ENABLE_CALIBRATION;
4497         vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4498
4499         /* Set HBR and RBR LPF coefficients */
4500         if (crtc->config.port_clock == 162000 ||
4501             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4502             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4503                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4504                                  0x009f0003);
4505         else
4506                 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4507                                  0x00d0000f);
4508
4509         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4510             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4511                 /* Use SSC source */
4512                 if (!pipe)
4513                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4514                                          0x0df40000);
4515                 else
4516                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4517                                          0x0df70000);
4518         } else { /* HDMI or VGA */
4519                 /* Use bend source */
4520                 if (!pipe)
4521                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4522                                          0x0df70000);
4523                 else
4524                         vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4525                                          0x0df40000);
4526         }
4527
4528         coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4529         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4530         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4531             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4532                 coreclk |= 0x01000000;
4533         vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4534
4535         vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4536
4537         /* Enable DPIO clock input */
4538         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4539                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4540         if (pipe)
4541                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4542
4543         dpll |= DPLL_VCO_ENABLE;
4544         crtc->config.dpll_hw_state.dpll = dpll;
4545
4546         dpll_md = (crtc->config.pixel_multiplier - 1)
4547                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4548         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4549
4550         if (crtc->config.has_dp_encoder)
4551                 intel_dp_set_m_n(crtc);
4552
4553         mutex_unlock(&dev_priv->dpio_lock);
4554 }
4555
4556 static void i9xx_update_pll(struct intel_crtc *crtc,
4557                             intel_clock_t *reduced_clock,
4558                             int num_connectors)
4559 {
4560         struct drm_device *dev = crtc->base.dev;
4561         struct drm_i915_private *dev_priv = dev->dev_private;
4562         u32 dpll;
4563         bool is_sdvo;
4564         struct dpll *clock = &crtc->config.dpll;
4565
4566         i9xx_update_pll_dividers(crtc, reduced_clock);
4567
4568         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4569                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4570
4571         dpll = DPLL_VGA_MODE_DIS;
4572
4573         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4574                 dpll |= DPLLB_MODE_LVDS;
4575         else
4576                 dpll |= DPLLB_MODE_DAC_SERIAL;
4577
4578         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4579                 dpll |= (crtc->config.pixel_multiplier - 1)
4580                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4581         }
4582
4583         if (is_sdvo)
4584                 dpll |= DPLL_SDVO_HIGH_SPEED;
4585
4586         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4587                 dpll |= DPLL_SDVO_HIGH_SPEED;
4588
4589         /* compute bitmask from p1 value */
4590         if (IS_PINEVIEW(dev))
4591                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4592         else {
4593                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594                 if (IS_G4X(dev) && reduced_clock)
4595                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4596         }
4597         switch (clock->p2) {
4598         case 5:
4599                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4600                 break;
4601         case 7:
4602                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4603                 break;
4604         case 10:
4605                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4606                 break;
4607         case 14:
4608                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4609                 break;
4610         }
4611         if (INTEL_INFO(dev)->gen >= 4)
4612                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4613
4614         if (crtc->config.sdvo_tv_clock)
4615                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4616         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4617                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4618                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4619         else
4620                 dpll |= PLL_REF_INPUT_DREFCLK;
4621
4622         dpll |= DPLL_VCO_ENABLE;
4623         crtc->config.dpll_hw_state.dpll = dpll;
4624
4625         if (INTEL_INFO(dev)->gen >= 4) {
4626                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4627                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4628                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4629         }
4630
4631         if (crtc->config.has_dp_encoder)
4632                 intel_dp_set_m_n(crtc);
4633 }
4634
4635 static void i8xx_update_pll(struct intel_crtc *crtc,
4636                             intel_clock_t *reduced_clock,
4637                             int num_connectors)
4638 {
4639         struct drm_device *dev = crtc->base.dev;
4640         struct drm_i915_private *dev_priv = dev->dev_private;
4641         u32 dpll;
4642         struct dpll *clock = &crtc->config.dpll;
4643
4644         i9xx_update_pll_dividers(crtc, reduced_clock);
4645
4646         dpll = DPLL_VGA_MODE_DIS;
4647
4648         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4649                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4650         } else {
4651                 if (clock->p1 == 2)
4652                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4653                 else
4654                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4655                 if (clock->p2 == 4)
4656                         dpll |= PLL_P2_DIVIDE_BY_4;
4657         }
4658
4659         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4660                 dpll |= DPLL_DVO_2X_MODE;
4661
4662         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4663                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4664                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4665         else
4666                 dpll |= PLL_REF_INPUT_DREFCLK;
4667
4668         dpll |= DPLL_VCO_ENABLE;
4669         crtc->config.dpll_hw_state.dpll = dpll;
4670 }
4671
4672 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4673 {
4674         struct drm_device *dev = intel_crtc->base.dev;
4675         struct drm_i915_private *dev_priv = dev->dev_private;
4676         enum pipe pipe = intel_crtc->pipe;
4677         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4678         struct drm_display_mode *adjusted_mode =
4679                 &intel_crtc->config.adjusted_mode;
4680         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4681         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4682
4683         /* We need to be careful not to changed the adjusted mode, for otherwise
4684          * the hw state checker will get angry at the mismatch. */
4685         crtc_vtotal = adjusted_mode->crtc_vtotal;
4686         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4687
4688         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4689                 /* the chip adds 2 halflines automatically */
4690                 crtc_vtotal -= 1;
4691                 crtc_vblank_end -= 1;
4692                 vsyncshift = adjusted_mode->crtc_hsync_start
4693                              - adjusted_mode->crtc_htotal / 2;
4694         } else {
4695                 vsyncshift = 0;
4696         }
4697
4698         if (INTEL_INFO(dev)->gen > 3)
4699                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4700
4701         I915_WRITE(HTOTAL(cpu_transcoder),
4702                    (adjusted_mode->crtc_hdisplay - 1) |
4703                    ((adjusted_mode->crtc_htotal - 1) << 16));
4704         I915_WRITE(HBLANK(cpu_transcoder),
4705                    (adjusted_mode->crtc_hblank_start - 1) |
4706                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4707         I915_WRITE(HSYNC(cpu_transcoder),
4708                    (adjusted_mode->crtc_hsync_start - 1) |
4709                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4710
4711         I915_WRITE(VTOTAL(cpu_transcoder),
4712                    (adjusted_mode->crtc_vdisplay - 1) |
4713                    ((crtc_vtotal - 1) << 16));
4714         I915_WRITE(VBLANK(cpu_transcoder),
4715                    (adjusted_mode->crtc_vblank_start - 1) |
4716                    ((crtc_vblank_end - 1) << 16));
4717         I915_WRITE(VSYNC(cpu_transcoder),
4718                    (adjusted_mode->crtc_vsync_start - 1) |
4719                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4720
4721         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4722          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4723          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4724          * bits. */
4725         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4726             (pipe == PIPE_B || pipe == PIPE_C))
4727                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4728
4729         /* pipesrc controls the size that is scaled from, which should
4730          * always be the user's requested size.
4731          */
4732         I915_WRITE(PIPESRC(pipe),
4733                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4734 }
4735
4736 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4737                                    struct intel_crtc_config *pipe_config)
4738 {
4739         struct drm_device *dev = crtc->base.dev;
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4742         uint32_t tmp;
4743
4744         tmp = I915_READ(HTOTAL(cpu_transcoder));
4745         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4746         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4747         tmp = I915_READ(HBLANK(cpu_transcoder));
4748         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4749         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4750         tmp = I915_READ(HSYNC(cpu_transcoder));
4751         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4752         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4753
4754         tmp = I915_READ(VTOTAL(cpu_transcoder));
4755         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4756         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4757         tmp = I915_READ(VBLANK(cpu_transcoder));
4758         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4759         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4760         tmp = I915_READ(VSYNC(cpu_transcoder));
4761         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4762         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4763
4764         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4765                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4766                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4767                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4768         }
4769
4770         tmp = I915_READ(PIPESRC(crtc->pipe));
4771         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4772         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4773 }
4774
4775 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4776                                              struct intel_crtc_config *pipe_config)
4777 {
4778         struct drm_crtc *crtc = &intel_crtc->base;
4779
4780         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4781         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4782         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4783         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4784
4785         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4786         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4787         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4788         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4789
4790         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4791
4792         crtc->mode.clock = pipe_config->adjusted_mode.clock;
4793         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4794 }
4795
4796 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4797 {
4798         struct drm_device *dev = intel_crtc->base.dev;
4799         struct drm_i915_private *dev_priv = dev->dev_private;
4800         uint32_t pipeconf;
4801
4802         pipeconf = 0;
4803
4804         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4805                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4806                  * core speed.
4807                  *
4808                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4809                  * pipe == 0 check?
4810                  */
4811                 if (intel_crtc->config.requested_mode.clock >
4812                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4813                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4814         }
4815
4816         /* only g4x and later have fancy bpc/dither controls */
4817         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4818                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4819                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4820                         pipeconf |= PIPECONF_DITHER_EN |
4821                                     PIPECONF_DITHER_TYPE_SP;
4822
4823                 switch (intel_crtc->config.pipe_bpp) {
4824                 case 18:
4825                         pipeconf |= PIPECONF_6BPC;
4826                         break;
4827                 case 24:
4828                         pipeconf |= PIPECONF_8BPC;
4829                         break;
4830                 case 30:
4831                         pipeconf |= PIPECONF_10BPC;
4832                         break;
4833                 default:
4834                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4835                         BUG();
4836                 }
4837         }
4838
4839         if (HAS_PIPE_CXSR(dev)) {
4840                 if (intel_crtc->lowfreq_avail) {
4841                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4842                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4843                 } else {
4844                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4845                 }
4846         }
4847
4848         if (!IS_GEN2(dev) &&
4849             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4850                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4851         else
4852                 pipeconf |= PIPECONF_PROGRESSIVE;
4853
4854         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4855                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4856
4857         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4858         POSTING_READ(PIPECONF(intel_crtc->pipe));
4859 }
4860
4861 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4862                               int x, int y,
4863                               struct drm_framebuffer *fb)
4864 {
4865         struct drm_device *dev = crtc->dev;
4866         struct drm_i915_private *dev_priv = dev->dev_private;
4867         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4868         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4869         int pipe = intel_crtc->pipe;
4870         int plane = intel_crtc->plane;
4871         int refclk, num_connectors = 0;
4872         intel_clock_t clock, reduced_clock;
4873         u32 dspcntr;
4874         bool ok, has_reduced_clock = false;
4875         bool is_lvds = false, is_dsi = false;
4876         struct intel_encoder *encoder;
4877         const intel_limit_t *limit;
4878         int ret;
4879
4880         for_each_encoder_on_crtc(dev, crtc, encoder) {
4881                 switch (encoder->type) {
4882                 case INTEL_OUTPUT_LVDS:
4883                         is_lvds = true;
4884                         break;
4885                 case INTEL_OUTPUT_DSI:
4886                         is_dsi = true;
4887                         break;
4888                 }
4889
4890                 num_connectors++;
4891         }
4892
4893         refclk = i9xx_get_refclk(crtc, num_connectors);
4894
4895         if (!is_dsi) {
4896                 /*
4897                  * Returns a set of divisors for the desired target clock with
4898                  * the given refclk, or FALSE.  The returned values represent
4899                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4900                  * 2) / p1 / p2.
4901                  */
4902                 limit = intel_limit(crtc, refclk);
4903                 ok = dev_priv->display.find_dpll(limit, crtc,
4904                                                  intel_crtc->config.port_clock,
4905                                                  refclk, NULL, &clock);
4906                 if (!ok && !intel_crtc->config.clock_set) {
4907                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
4908                         return -EINVAL;
4909                 }
4910         }
4911
4912         /* Ensure that the cursor is valid for the new mode before changing... */
4913         intel_crtc_update_cursor(crtc, true);
4914
4915         if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
4916                 /*
4917                  * Ensure we match the reduced clock's P to the target clock.
4918                  * If the clocks don't match, we can't switch the display clock
4919                  * by using the FP0/FP1. In such case we will disable the LVDS
4920                  * downclock feature.
4921                 */
4922                 has_reduced_clock =
4923                         dev_priv->display.find_dpll(limit, crtc,
4924                                                     dev_priv->lvds_downclock,
4925                                                     refclk, &clock,
4926                                                     &reduced_clock);
4927         }
4928         /* Compat-code for transition, will disappear. */
4929         if (!intel_crtc->config.clock_set) {
4930                 intel_crtc->config.dpll.n = clock.n;
4931                 intel_crtc->config.dpll.m1 = clock.m1;
4932                 intel_crtc->config.dpll.m2 = clock.m2;
4933                 intel_crtc->config.dpll.p1 = clock.p1;
4934                 intel_crtc->config.dpll.p2 = clock.p2;
4935         }
4936
4937         if (IS_GEN2(dev)) {
4938                 i8xx_update_pll(intel_crtc,
4939                                 has_reduced_clock ? &reduced_clock : NULL,
4940                                 num_connectors);
4941         } else if (IS_VALLEYVIEW(dev)) {
4942                 if (!is_dsi)
4943                         vlv_update_pll(intel_crtc);
4944         } else {
4945                 i9xx_update_pll(intel_crtc,
4946                                 has_reduced_clock ? &reduced_clock : NULL,
4947                                 num_connectors);
4948         }
4949
4950         /* Set up the display plane register */
4951         dspcntr = DISPPLANE_GAMMA_ENABLE;
4952
4953         if (!IS_VALLEYVIEW(dev)) {
4954                 if (pipe == 0)
4955                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4956                 else
4957                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4958         }
4959
4960         intel_set_pipe_timings(intel_crtc);
4961
4962         /* pipesrc and dspsize control the size that is scaled from,
4963          * which should always be the user's requested size.
4964          */
4965         I915_WRITE(DSPSIZE(plane),
4966                    ((mode->vdisplay - 1) << 16) |
4967                    (mode->hdisplay - 1));
4968         I915_WRITE(DSPPOS(plane), 0);
4969
4970         i9xx_set_pipeconf(intel_crtc);
4971
4972         I915_WRITE(DSPCNTR(plane), dspcntr);
4973         POSTING_READ(DSPCNTR(plane));
4974
4975         ret = intel_pipe_set_base(crtc, x, y, fb);
4976
4977         intel_update_watermarks(dev);
4978
4979         return ret;
4980 }
4981
4982 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4983                                  struct intel_crtc_config *pipe_config)
4984 {
4985         struct drm_device *dev = crtc->base.dev;
4986         struct drm_i915_private *dev_priv = dev->dev_private;
4987         uint32_t tmp;
4988
4989         tmp = I915_READ(PFIT_CONTROL);
4990         if (!(tmp & PFIT_ENABLE))
4991                 return;
4992
4993         /* Check whether the pfit is attached to our pipe. */
4994         if (INTEL_INFO(dev)->gen < 4) {
4995                 if (crtc->pipe != PIPE_B)
4996                         return;
4997         } else {
4998                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4999                         return;
5000         }
5001
5002         pipe_config->gmch_pfit.control = tmp;
5003         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5004         if (INTEL_INFO(dev)->gen < 5)
5005                 pipe_config->gmch_pfit.lvds_border_bits =
5006                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5007 }
5008
5009 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5010                                  struct intel_crtc_config *pipe_config)
5011 {
5012         struct drm_device *dev = crtc->base.dev;
5013         struct drm_i915_private *dev_priv = dev->dev_private;
5014         uint32_t tmp;
5015
5016         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5017         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5018
5019         tmp = I915_READ(PIPECONF(crtc->pipe));
5020         if (!(tmp & PIPECONF_ENABLE))
5021                 return false;
5022
5023         intel_get_pipe_timings(crtc, pipe_config);
5024
5025         i9xx_get_pfit_config(crtc, pipe_config);
5026
5027         if (INTEL_INFO(dev)->gen >= 4) {
5028                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5029                 pipe_config->pixel_multiplier =
5030                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5031                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5032                 pipe_config->dpll_hw_state.dpll_md = tmp;
5033         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5034                 tmp = I915_READ(DPLL(crtc->pipe));
5035                 pipe_config->pixel_multiplier =
5036                         ((tmp & SDVO_MULTIPLIER_MASK)
5037                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5038         } else {
5039                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5040                  * port and will be fixed up in the encoder->get_config
5041                  * function. */
5042                 pipe_config->pixel_multiplier = 1;
5043         }
5044         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5045         if (!IS_VALLEYVIEW(dev)) {
5046                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5047                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5048         } else {
5049                 /* Mask out read-only status bits. */
5050                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5051                                                      DPLL_PORTC_READY_MASK |
5052                                                      DPLL_PORTB_READY_MASK);
5053         }
5054
5055         return true;
5056 }
5057
5058 static void ironlake_init_pch_refclk(struct drm_device *dev)
5059 {
5060         struct drm_i915_private *dev_priv = dev->dev_private;
5061         struct drm_mode_config *mode_config = &dev->mode_config;
5062         struct intel_encoder *encoder;
5063         u32 val, final;
5064         bool has_lvds = false;
5065         bool has_cpu_edp = false;
5066         bool has_panel = false;
5067         bool has_ck505 = false;
5068         bool can_ssc = false;
5069
5070         /* We need to take the global config into account */
5071         list_for_each_entry(encoder, &mode_config->encoder_list,
5072                             base.head) {
5073                 switch (encoder->type) {
5074                 case INTEL_OUTPUT_LVDS:
5075                         has_panel = true;
5076                         has_lvds = true;
5077                         break;
5078                 case INTEL_OUTPUT_EDP:
5079                         has_panel = true;
5080                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5081                                 has_cpu_edp = true;
5082                         break;
5083                 }
5084         }
5085
5086         if (HAS_PCH_IBX(dev)) {
5087                 has_ck505 = dev_priv->vbt.display_clock_mode;
5088                 can_ssc = has_ck505;
5089         } else {
5090                 has_ck505 = false;
5091                 can_ssc = true;
5092         }
5093
5094         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5095                       has_panel, has_lvds, has_ck505);
5096
5097         /* Ironlake: try to setup display ref clock before DPLL
5098          * enabling. This is only under driver's control after
5099          * PCH B stepping, previous chipset stepping should be
5100          * ignoring this setting.
5101          */
5102         val = I915_READ(PCH_DREF_CONTROL);
5103
5104         /* As we must carefully and slowly disable/enable each source in turn,
5105          * compute the final state we want first and check if we need to
5106          * make any changes at all.
5107          */
5108         final = val;
5109         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5110         if (has_ck505)
5111                 final |= DREF_NONSPREAD_CK505_ENABLE;
5112         else
5113                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5114
5115         final &= ~DREF_SSC_SOURCE_MASK;
5116         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5117         final &= ~DREF_SSC1_ENABLE;
5118
5119         if (has_panel) {
5120                 final |= DREF_SSC_SOURCE_ENABLE;
5121
5122                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5123                         final |= DREF_SSC1_ENABLE;
5124
5125                 if (has_cpu_edp) {
5126                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5127                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5128                         else
5129                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5130                 } else
5131                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5132         } else {
5133                 final |= DREF_SSC_SOURCE_DISABLE;
5134                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5135         }
5136
5137         if (final == val)
5138                 return;
5139
5140         /* Always enable nonspread source */
5141         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5142
5143         if (has_ck505)
5144                 val |= DREF_NONSPREAD_CK505_ENABLE;
5145         else
5146                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5147
5148         if (has_panel) {
5149                 val &= ~DREF_SSC_SOURCE_MASK;
5150                 val |= DREF_SSC_SOURCE_ENABLE;
5151
5152                 /* SSC must be turned on before enabling the CPU output  */
5153                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5154                         DRM_DEBUG_KMS("Using SSC on panel\n");
5155                         val |= DREF_SSC1_ENABLE;
5156                 } else
5157                         val &= ~DREF_SSC1_ENABLE;
5158
5159                 /* Get SSC going before enabling the outputs */
5160                 I915_WRITE(PCH_DREF_CONTROL, val);
5161                 POSTING_READ(PCH_DREF_CONTROL);
5162                 udelay(200);
5163
5164                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5165
5166                 /* Enable CPU source on CPU attached eDP */
5167                 if (has_cpu_edp) {
5168                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5169                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5170                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5171                         }
5172                         else
5173                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5174                 } else
5175                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5176
5177                 I915_WRITE(PCH_DREF_CONTROL, val);
5178                 POSTING_READ(PCH_DREF_CONTROL);
5179                 udelay(200);
5180         } else {
5181                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5182
5183                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5184
5185                 /* Turn off CPU output */
5186                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5187
5188                 I915_WRITE(PCH_DREF_CONTROL, val);
5189                 POSTING_READ(PCH_DREF_CONTROL);
5190                 udelay(200);
5191
5192                 /* Turn off the SSC source */
5193                 val &= ~DREF_SSC_SOURCE_MASK;
5194                 val |= DREF_SSC_SOURCE_DISABLE;
5195
5196                 /* Turn off SSC1 */
5197                 val &= ~DREF_SSC1_ENABLE;
5198
5199                 I915_WRITE(PCH_DREF_CONTROL, val);
5200                 POSTING_READ(PCH_DREF_CONTROL);
5201                 udelay(200);
5202         }
5203
5204         BUG_ON(val != final);
5205 }
5206
5207 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5208 {
5209         uint32_t tmp;
5210
5211         tmp = I915_READ(SOUTH_CHICKEN2);
5212         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5213         I915_WRITE(SOUTH_CHICKEN2, tmp);
5214
5215         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5216                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5217                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5218
5219         tmp = I915_READ(SOUTH_CHICKEN2);
5220         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5221         I915_WRITE(SOUTH_CHICKEN2, tmp);
5222
5223         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5224                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5225                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5226 }
5227
5228 /* WaMPhyProgramming:hsw */
5229 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5230 {
5231         uint32_t tmp;
5232
5233         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5234         tmp &= ~(0xFF << 24);
5235         tmp |= (0x12 << 24);
5236         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5237
5238         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5239         tmp |= (1 << 11);
5240         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5241
5242         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5243         tmp |= (1 << 11);
5244         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5245
5246         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5247         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5248         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5249
5250         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5251         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5252         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5253
5254         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5255         tmp &= ~(7 << 13);
5256         tmp |= (5 << 13);
5257         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5258
5259         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5260         tmp &= ~(7 << 13);
5261         tmp |= (5 << 13);
5262         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5263
5264         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5265         tmp &= ~0xFF;
5266         tmp |= 0x1C;
5267         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5268
5269         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5270         tmp &= ~0xFF;
5271         tmp |= 0x1C;
5272         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5273
5274         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5275         tmp &= ~(0xFF << 16);
5276         tmp |= (0x1C << 16);
5277         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5278
5279         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5280         tmp &= ~(0xFF << 16);
5281         tmp |= (0x1C << 16);
5282         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5283
5284         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5285         tmp |= (1 << 27);
5286         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5287
5288         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5289         tmp |= (1 << 27);
5290         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5291
5292         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5293         tmp &= ~(0xF << 28);
5294         tmp |= (4 << 28);
5295         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5296
5297         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5298         tmp &= ~(0xF << 28);
5299         tmp |= (4 << 28);
5300         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5301 }
5302
5303 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5304  * Programming" based on the parameters passed:
5305  * - Sequence to enable CLKOUT_DP
5306  * - Sequence to enable CLKOUT_DP without spread
5307  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5308  */
5309 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5310                                  bool with_fdi)
5311 {
5312         struct drm_i915_private *dev_priv = dev->dev_private;
5313         uint32_t reg, tmp;
5314
5315         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5316                 with_spread = true;
5317         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5318                  with_fdi, "LP PCH doesn't have FDI\n"))
5319                 with_fdi = false;
5320
5321         mutex_lock(&dev_priv->dpio_lock);
5322
5323         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5324         tmp &= ~SBI_SSCCTL_DISABLE;
5325         tmp |= SBI_SSCCTL_PATHALT;
5326         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5327
5328         udelay(24);
5329
5330         if (with_spread) {
5331                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5332                 tmp &= ~SBI_SSCCTL_PATHALT;
5333                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5334
5335                 if (with_fdi) {
5336                         lpt_reset_fdi_mphy(dev_priv);
5337                         lpt_program_fdi_mphy(dev_priv);
5338                 }
5339         }
5340
5341         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5342                SBI_GEN0 : SBI_DBUFF0;
5343         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5344         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5345         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5346
5347         mutex_unlock(&dev_priv->dpio_lock);
5348 }
5349
5350 /* Sequence to disable CLKOUT_DP */
5351 static void lpt_disable_clkout_dp(struct drm_device *dev)
5352 {
5353         struct drm_i915_private *dev_priv = dev->dev_private;
5354         uint32_t reg, tmp;
5355
5356         mutex_lock(&dev_priv->dpio_lock);
5357
5358         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5359                SBI_GEN0 : SBI_DBUFF0;
5360         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5361         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5362         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5363
5364         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5365         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5366                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5367                         tmp |= SBI_SSCCTL_PATHALT;
5368                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5369                         udelay(32);
5370                 }
5371                 tmp |= SBI_SSCCTL_DISABLE;
5372                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5373         }
5374
5375         mutex_unlock(&dev_priv->dpio_lock);
5376 }
5377
5378 static void lpt_init_pch_refclk(struct drm_device *dev)
5379 {
5380         struct drm_mode_config *mode_config = &dev->mode_config;
5381         struct intel_encoder *encoder;
5382         bool has_vga = false;
5383
5384         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5385                 switch (encoder->type) {
5386                 case INTEL_OUTPUT_ANALOG:
5387                         has_vga = true;
5388                         break;
5389                 }
5390         }
5391
5392         if (has_vga)
5393                 lpt_enable_clkout_dp(dev, true, true);
5394         else
5395                 lpt_disable_clkout_dp(dev);
5396 }
5397
5398 /*
5399  * Initialize reference clocks when the driver loads
5400  */
5401 void intel_init_pch_refclk(struct drm_device *dev)
5402 {
5403         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5404                 ironlake_init_pch_refclk(dev);
5405         else if (HAS_PCH_LPT(dev))
5406                 lpt_init_pch_refclk(dev);
5407 }
5408
5409 static int ironlake_get_refclk(struct drm_crtc *crtc)
5410 {
5411         struct drm_device *dev = crtc->dev;
5412         struct drm_i915_private *dev_priv = dev->dev_private;
5413         struct intel_encoder *encoder;
5414         int num_connectors = 0;
5415         bool is_lvds = false;
5416
5417         for_each_encoder_on_crtc(dev, crtc, encoder) {
5418                 switch (encoder->type) {
5419                 case INTEL_OUTPUT_LVDS:
5420                         is_lvds = true;
5421                         break;
5422                 }
5423                 num_connectors++;
5424         }
5425
5426         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5427                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5428                               dev_priv->vbt.lvds_ssc_freq);
5429                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5430         }
5431
5432         return 120000;
5433 }
5434
5435 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5436 {
5437         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5438         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5439         int pipe = intel_crtc->pipe;
5440         uint32_t val;
5441
5442         val = 0;
5443
5444         switch (intel_crtc->config.pipe_bpp) {
5445         case 18:
5446                 val |= PIPECONF_6BPC;
5447                 break;
5448         case 24:
5449                 val |= PIPECONF_8BPC;
5450                 break;
5451         case 30:
5452                 val |= PIPECONF_10BPC;
5453                 break;
5454         case 36:
5455                 val |= PIPECONF_12BPC;
5456                 break;
5457         default:
5458                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5459                 BUG();
5460         }
5461
5462         if (intel_crtc->config.dither)
5463                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5464
5465         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5466                 val |= PIPECONF_INTERLACED_ILK;
5467         else
5468                 val |= PIPECONF_PROGRESSIVE;
5469
5470         if (intel_crtc->config.limited_color_range)
5471                 val |= PIPECONF_COLOR_RANGE_SELECT;
5472
5473         I915_WRITE(PIPECONF(pipe), val);
5474         POSTING_READ(PIPECONF(pipe));
5475 }
5476
5477 /*
5478  * Set up the pipe CSC unit.
5479  *
5480  * Currently only full range RGB to limited range RGB conversion
5481  * is supported, but eventually this should handle various
5482  * RGB<->YCbCr scenarios as well.
5483  */
5484 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5485 {
5486         struct drm_device *dev = crtc->dev;
5487         struct drm_i915_private *dev_priv = dev->dev_private;
5488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5489         int pipe = intel_crtc->pipe;
5490         uint16_t coeff = 0x7800; /* 1.0 */
5491
5492         /*
5493          * TODO: Check what kind of values actually come out of the pipe
5494          * with these coeff/postoff values and adjust to get the best
5495          * accuracy. Perhaps we even need to take the bpc value into
5496          * consideration.
5497          */
5498
5499         if (intel_crtc->config.limited_color_range)
5500                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5501
5502         /*
5503          * GY/GU and RY/RU should be the other way around according
5504          * to BSpec, but reality doesn't agree. Just set them up in
5505          * a way that results in the correct picture.
5506          */
5507         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5508         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5509
5510         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5511         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5512
5513         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5514         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5515
5516         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5517         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5518         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5519
5520         if (INTEL_INFO(dev)->gen > 6) {
5521                 uint16_t postoff = 0;
5522
5523                 if (intel_crtc->config.limited_color_range)
5524                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5525
5526                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5527                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5528                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5529
5530                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5531         } else {
5532                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5533
5534                 if (intel_crtc->config.limited_color_range)
5535                         mode |= CSC_BLACK_SCREEN_OFFSET;
5536
5537                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5538         }
5539 }
5540
5541 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5542 {
5543         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5544         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5545         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5546         uint32_t val;
5547
5548         val = 0;
5549
5550         if (intel_crtc->config.dither)
5551                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5552
5553         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5554                 val |= PIPECONF_INTERLACED_ILK;
5555         else
5556                 val |= PIPECONF_PROGRESSIVE;
5557
5558         I915_WRITE(PIPECONF(cpu_transcoder), val);
5559         POSTING_READ(PIPECONF(cpu_transcoder));
5560
5561         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5562         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5563 }
5564
5565 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5566                                     intel_clock_t *clock,
5567                                     bool *has_reduced_clock,
5568                                     intel_clock_t *reduced_clock)
5569 {
5570         struct drm_device *dev = crtc->dev;
5571         struct drm_i915_private *dev_priv = dev->dev_private;
5572         struct intel_encoder *intel_encoder;
5573         int refclk;
5574         const intel_limit_t *limit;
5575         bool ret, is_lvds = false;
5576
5577         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5578                 switch (intel_encoder->type) {
5579                 case INTEL_OUTPUT_LVDS:
5580                         is_lvds = true;
5581                         break;
5582                 }
5583         }
5584
5585         refclk = ironlake_get_refclk(crtc);
5586
5587         /*
5588          * Returns a set of divisors for the desired target clock with the given
5589          * refclk, or FALSE.  The returned values represent the clock equation:
5590          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5591          */
5592         limit = intel_limit(crtc, refclk);
5593         ret = dev_priv->display.find_dpll(limit, crtc,
5594                                           to_intel_crtc(crtc)->config.port_clock,
5595                                           refclk, NULL, clock);
5596         if (!ret)
5597                 return false;
5598
5599         if (is_lvds && dev_priv->lvds_downclock_avail) {
5600                 /*
5601                  * Ensure we match the reduced clock's P to the target clock.
5602                  * If the clocks don't match, we can't switch the display clock
5603                  * by using the FP0/FP1. In such case we will disable the LVDS
5604                  * downclock feature.
5605                 */
5606                 *has_reduced_clock =
5607                         dev_priv->display.find_dpll(limit, crtc,
5608                                                     dev_priv->lvds_downclock,
5609                                                     refclk, clock,
5610                                                     reduced_clock);
5611         }
5612
5613         return true;
5614 }
5615
5616 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5617 {
5618         struct drm_i915_private *dev_priv = dev->dev_private;
5619         uint32_t temp;
5620
5621         temp = I915_READ(SOUTH_CHICKEN1);
5622         if (temp & FDI_BC_BIFURCATION_SELECT)
5623                 return;
5624
5625         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5626         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5627
5628         temp |= FDI_BC_BIFURCATION_SELECT;
5629         DRM_DEBUG_KMS("enabling fdi C rx\n");
5630         I915_WRITE(SOUTH_CHICKEN1, temp);
5631         POSTING_READ(SOUTH_CHICKEN1);
5632 }
5633
5634 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5635 {
5636         struct drm_device *dev = intel_crtc->base.dev;
5637         struct drm_i915_private *dev_priv = dev->dev_private;
5638
5639         switch (intel_crtc->pipe) {
5640         case PIPE_A:
5641                 break;
5642         case PIPE_B:
5643                 if (intel_crtc->config.fdi_lanes > 2)
5644                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5645                 else
5646                         cpt_enable_fdi_bc_bifurcation(dev);
5647
5648                 break;
5649         case PIPE_C:
5650                 cpt_enable_fdi_bc_bifurcation(dev);
5651
5652                 break;
5653         default:
5654                 BUG();
5655         }
5656 }
5657
5658 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5659 {
5660         /*
5661          * Account for spread spectrum to avoid
5662          * oversubscribing the link. Max center spread
5663          * is 2.5%; use 5% for safety's sake.
5664          */
5665         u32 bps = target_clock * bpp * 21 / 20;
5666         return bps / (link_bw * 8) + 1;
5667 }
5668
5669 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5670 {
5671         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5672 }
5673
5674 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5675                                       u32 *fp,
5676                                       intel_clock_t *reduced_clock, u32 *fp2)
5677 {
5678         struct drm_crtc *crtc = &intel_crtc->base;
5679         struct drm_device *dev = crtc->dev;
5680         struct drm_i915_private *dev_priv = dev->dev_private;
5681         struct intel_encoder *intel_encoder;
5682         uint32_t dpll;
5683         int factor, num_connectors = 0;
5684         bool is_lvds = false, is_sdvo = false;
5685
5686         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5687                 switch (intel_encoder->type) {
5688                 case INTEL_OUTPUT_LVDS:
5689                         is_lvds = true;
5690                         break;
5691                 case INTEL_OUTPUT_SDVO:
5692                 case INTEL_OUTPUT_HDMI:
5693                         is_sdvo = true;
5694                         break;
5695                 }
5696
5697                 num_connectors++;
5698         }
5699
5700         /* Enable autotuning of the PLL clock (if permissible) */
5701         factor = 21;
5702         if (is_lvds) {
5703                 if ((intel_panel_use_ssc(dev_priv) &&
5704                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5705                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5706                         factor = 25;
5707         } else if (intel_crtc->config.sdvo_tv_clock)
5708                 factor = 20;
5709
5710         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5711                 *fp |= FP_CB_TUNE;
5712
5713         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5714                 *fp2 |= FP_CB_TUNE;
5715
5716         dpll = 0;
5717
5718         if (is_lvds)
5719                 dpll |= DPLLB_MODE_LVDS;
5720         else
5721                 dpll |= DPLLB_MODE_DAC_SERIAL;
5722
5723         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5724                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5725
5726         if (is_sdvo)
5727                 dpll |= DPLL_SDVO_HIGH_SPEED;
5728         if (intel_crtc->config.has_dp_encoder)
5729                 dpll |= DPLL_SDVO_HIGH_SPEED;
5730
5731         /* compute bitmask from p1 value */
5732         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5733         /* also FPA1 */
5734         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5735
5736         switch (intel_crtc->config.dpll.p2) {
5737         case 5:
5738                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5739                 break;
5740         case 7:
5741                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5742                 break;
5743         case 10:
5744                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5745                 break;
5746         case 14:
5747                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5748                 break;
5749         }
5750
5751         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5752                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5753         else
5754                 dpll |= PLL_REF_INPUT_DREFCLK;
5755
5756         return dpll | DPLL_VCO_ENABLE;
5757 }
5758
5759 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5760                                   int x, int y,
5761                                   struct drm_framebuffer *fb)
5762 {
5763         struct drm_device *dev = crtc->dev;
5764         struct drm_i915_private *dev_priv = dev->dev_private;
5765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5766         int pipe = intel_crtc->pipe;
5767         int plane = intel_crtc->plane;
5768         int num_connectors = 0;
5769         intel_clock_t clock, reduced_clock;
5770         u32 dpll = 0, fp = 0, fp2 = 0;
5771         bool ok, has_reduced_clock = false;
5772         bool is_lvds = false;
5773         struct intel_encoder *encoder;
5774         struct intel_shared_dpll *pll;
5775         int ret;
5776
5777         for_each_encoder_on_crtc(dev, crtc, encoder) {
5778                 switch (encoder->type) {
5779                 case INTEL_OUTPUT_LVDS:
5780                         is_lvds = true;
5781                         break;
5782                 }
5783
5784                 num_connectors++;
5785         }
5786
5787         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5788              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5789
5790         ok = ironlake_compute_clocks(crtc, &clock,
5791                                      &has_reduced_clock, &reduced_clock);
5792         if (!ok && !intel_crtc->config.clock_set) {
5793                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5794                 return -EINVAL;
5795         }
5796         /* Compat-code for transition, will disappear. */
5797         if (!intel_crtc->config.clock_set) {
5798                 intel_crtc->config.dpll.n = clock.n;
5799                 intel_crtc->config.dpll.m1 = clock.m1;
5800                 intel_crtc->config.dpll.m2 = clock.m2;
5801                 intel_crtc->config.dpll.p1 = clock.p1;
5802                 intel_crtc->config.dpll.p2 = clock.p2;
5803         }
5804
5805         /* Ensure that the cursor is valid for the new mode before changing... */
5806         intel_crtc_update_cursor(crtc, true);
5807
5808         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5809         if (intel_crtc->config.has_pch_encoder) {
5810                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5811                 if (has_reduced_clock)
5812                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5813
5814                 dpll = ironlake_compute_dpll(intel_crtc,
5815                                              &fp, &reduced_clock,
5816                                              has_reduced_clock ? &fp2 : NULL);
5817
5818                 intel_crtc->config.dpll_hw_state.dpll = dpll;
5819                 intel_crtc->config.dpll_hw_state.fp0 = fp;
5820                 if (has_reduced_clock)
5821                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
5822                 else
5823                         intel_crtc->config.dpll_hw_state.fp1 = fp;
5824
5825                 pll = intel_get_shared_dpll(intel_crtc);
5826                 if (pll == NULL) {
5827                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5828                                          pipe_name(pipe));
5829                         return -EINVAL;
5830                 }
5831         } else
5832                 intel_put_shared_dpll(intel_crtc);
5833
5834         if (intel_crtc->config.has_dp_encoder)
5835                 intel_dp_set_m_n(intel_crtc);
5836
5837         if (is_lvds && has_reduced_clock && i915_powersave)
5838                 intel_crtc->lowfreq_avail = true;
5839         else
5840                 intel_crtc->lowfreq_avail = false;
5841
5842         if (intel_crtc->config.has_pch_encoder) {
5843                 pll = intel_crtc_to_shared_dpll(intel_crtc);
5844
5845         }
5846
5847         intel_set_pipe_timings(intel_crtc);
5848
5849         if (intel_crtc->config.has_pch_encoder) {
5850                 intel_cpu_transcoder_set_m_n(intel_crtc,
5851                                              &intel_crtc->config.fdi_m_n);
5852         }
5853
5854         if (IS_IVYBRIDGE(dev))
5855                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5856
5857         ironlake_set_pipeconf(crtc);
5858
5859         /* Set up the display plane register */
5860         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5861         POSTING_READ(DSPCNTR(plane));
5862
5863         ret = intel_pipe_set_base(crtc, x, y, fb);
5864
5865         intel_update_watermarks(dev);
5866
5867         return ret;
5868 }
5869
5870 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5871                                         struct intel_crtc_config *pipe_config)
5872 {
5873         struct drm_device *dev = crtc->base.dev;
5874         struct drm_i915_private *dev_priv = dev->dev_private;
5875         enum transcoder transcoder = pipe_config->cpu_transcoder;
5876
5877         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5878         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5879         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5880                                         & ~TU_SIZE_MASK;
5881         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5882         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5883                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5884 }
5885
5886 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5887                                      struct intel_crtc_config *pipe_config)
5888 {
5889         struct drm_device *dev = crtc->base.dev;
5890         struct drm_i915_private *dev_priv = dev->dev_private;
5891         uint32_t tmp;
5892
5893         tmp = I915_READ(PF_CTL(crtc->pipe));
5894
5895         if (tmp & PF_ENABLE) {
5896                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5897                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5898
5899                 /* We currently do not free assignements of panel fitters on
5900                  * ivb/hsw (since we don't use the higher upscaling modes which
5901                  * differentiates them) so just WARN about this case for now. */
5902                 if (IS_GEN7(dev)) {
5903                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5904                                 PF_PIPE_SEL_IVB(crtc->pipe));
5905                 }
5906         }
5907 }
5908
5909 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5910                                      struct intel_crtc_config *pipe_config)
5911 {
5912         struct drm_device *dev = crtc->base.dev;
5913         struct drm_i915_private *dev_priv = dev->dev_private;
5914         uint32_t tmp;
5915
5916         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5917         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5918
5919         tmp = I915_READ(PIPECONF(crtc->pipe));
5920         if (!(tmp & PIPECONF_ENABLE))
5921                 return false;
5922
5923         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5924                 struct intel_shared_dpll *pll;
5925
5926                 pipe_config->has_pch_encoder = true;
5927
5928                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5929                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5930                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5931
5932                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5933
5934                 if (HAS_PCH_IBX(dev_priv->dev)) {
5935                         pipe_config->shared_dpll =
5936                                 (enum intel_dpll_id) crtc->pipe;
5937                 } else {
5938                         tmp = I915_READ(PCH_DPLL_SEL);
5939                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5940                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5941                         else
5942                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5943                 }
5944
5945                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5946
5947                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5948                                            &pipe_config->dpll_hw_state));
5949
5950                 tmp = pipe_config->dpll_hw_state.dpll;
5951                 pipe_config->pixel_multiplier =
5952                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5953                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
5954         } else {
5955                 pipe_config->pixel_multiplier = 1;
5956         }
5957
5958         intel_get_pipe_timings(crtc, pipe_config);
5959
5960         ironlake_get_pfit_config(crtc, pipe_config);
5961
5962         return true;
5963 }
5964
5965 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5966 {
5967         struct drm_device *dev = dev_priv->dev;
5968         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5969         struct intel_crtc *crtc;
5970         unsigned long irqflags;
5971         uint32_t val;
5972
5973         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5974                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5975                      pipe_name(crtc->pipe));
5976
5977         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5978         WARN(plls->spll_refcount, "SPLL enabled\n");
5979         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5980         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5981         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5982         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5983              "CPU PWM1 enabled\n");
5984         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5985              "CPU PWM2 enabled\n");
5986         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5987              "PCH PWM1 enabled\n");
5988         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5989              "Utility pin enabled\n");
5990         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5991
5992         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5993         val = I915_READ(DEIMR);
5994         WARN((val & ~DE_PCH_EVENT_IVB) != val,
5995              "Unexpected DEIMR bits enabled: 0x%x\n", val);
5996         val = I915_READ(SDEIMR);
5997         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
5998              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5999         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6000 }
6001
6002 /*
6003  * This function implements pieces of two sequences from BSpec:
6004  * - Sequence for display software to disable LCPLL
6005  * - Sequence for display software to allow package C8+
6006  * The steps implemented here are just the steps that actually touch the LCPLL
6007  * register. Callers should take care of disabling all the display engine
6008  * functions, doing the mode unset, fixing interrupts, etc.
6009  */
6010 void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6011                        bool switch_to_fclk, bool allow_power_down)
6012 {
6013         uint32_t val;
6014
6015         assert_can_disable_lcpll(dev_priv);
6016
6017         val = I915_READ(LCPLL_CTL);
6018
6019         if (switch_to_fclk) {
6020                 val |= LCPLL_CD_SOURCE_FCLK;
6021                 I915_WRITE(LCPLL_CTL, val);
6022
6023                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6024                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6025                         DRM_ERROR("Switching to FCLK failed\n");
6026
6027                 val = I915_READ(LCPLL_CTL);
6028         }
6029
6030         val |= LCPLL_PLL_DISABLE;
6031         I915_WRITE(LCPLL_CTL, val);
6032         POSTING_READ(LCPLL_CTL);
6033
6034         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6035                 DRM_ERROR("LCPLL still locked\n");
6036
6037         val = I915_READ(D_COMP);
6038         val |= D_COMP_COMP_DISABLE;
6039         I915_WRITE(D_COMP, val);
6040         POSTING_READ(D_COMP);
6041         ndelay(100);
6042
6043         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6044                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6045
6046         if (allow_power_down) {
6047                 val = I915_READ(LCPLL_CTL);
6048                 val |= LCPLL_POWER_DOWN_ALLOW;
6049                 I915_WRITE(LCPLL_CTL, val);
6050                 POSTING_READ(LCPLL_CTL);
6051         }
6052 }
6053
6054 /*
6055  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6056  * source.
6057  */
6058 void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6059 {
6060         uint32_t val;
6061
6062         val = I915_READ(LCPLL_CTL);
6063
6064         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6065                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6066                 return;
6067
6068         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6069          * we'll hang the machine! */
6070         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6071
6072         if (val & LCPLL_POWER_DOWN_ALLOW) {
6073                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6074                 I915_WRITE(LCPLL_CTL, val);
6075                 POSTING_READ(LCPLL_CTL);
6076         }
6077
6078         val = I915_READ(D_COMP);
6079         val |= D_COMP_COMP_FORCE;
6080         val &= ~D_COMP_COMP_DISABLE;
6081         I915_WRITE(D_COMP, val);
6082         POSTING_READ(D_COMP);
6083
6084         val = I915_READ(LCPLL_CTL);
6085         val &= ~LCPLL_PLL_DISABLE;
6086         I915_WRITE(LCPLL_CTL, val);
6087
6088         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6089                 DRM_ERROR("LCPLL not locked yet\n");
6090
6091         if (val & LCPLL_CD_SOURCE_FCLK) {
6092                 val = I915_READ(LCPLL_CTL);
6093                 val &= ~LCPLL_CD_SOURCE_FCLK;
6094                 I915_WRITE(LCPLL_CTL, val);
6095
6096                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6097                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6098                         DRM_ERROR("Switching back to LCPLL failed\n");
6099         }
6100
6101         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6102 }
6103
6104 void hsw_enable_pc8_work(struct work_struct *__work)
6105 {
6106         struct drm_i915_private *dev_priv =
6107                 container_of(to_delayed_work(__work), struct drm_i915_private,
6108                              pc8.enable_work);
6109         struct drm_device *dev = dev_priv->dev;
6110         uint32_t val;
6111
6112         if (dev_priv->pc8.enabled)
6113                 return;
6114
6115         DRM_DEBUG_KMS("Enabling package C8+\n");
6116
6117         dev_priv->pc8.enabled = true;
6118
6119         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6120                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6121                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6122                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6123         }
6124
6125         lpt_disable_clkout_dp(dev);
6126         hsw_pc8_disable_interrupts(dev);
6127         hsw_disable_lcpll(dev_priv, true, true);
6128 }
6129
6130 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6131 {
6132         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6133         WARN(dev_priv->pc8.disable_count < 1,
6134              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6135
6136         dev_priv->pc8.disable_count--;
6137         if (dev_priv->pc8.disable_count != 0)
6138                 return;
6139
6140         schedule_delayed_work(&dev_priv->pc8.enable_work,
6141                               msecs_to_jiffies(i915_pc8_timeout));
6142 }
6143
6144 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6145 {
6146         struct drm_device *dev = dev_priv->dev;
6147         uint32_t val;
6148
6149         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6150         WARN(dev_priv->pc8.disable_count < 0,
6151              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6152
6153         dev_priv->pc8.disable_count++;
6154         if (dev_priv->pc8.disable_count != 1)
6155                 return;
6156
6157         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6158         if (!dev_priv->pc8.enabled)
6159                 return;
6160
6161         DRM_DEBUG_KMS("Disabling package C8+\n");
6162
6163         hsw_restore_lcpll(dev_priv);
6164         hsw_pc8_restore_interrupts(dev);
6165         lpt_init_pch_refclk(dev);
6166
6167         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6168                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6169                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6170                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6171         }
6172
6173         intel_prepare_ddi(dev);
6174         i915_gem_init_swizzling(dev);
6175         mutex_lock(&dev_priv->rps.hw_lock);
6176         gen6_update_ring_freq(dev);
6177         mutex_unlock(&dev_priv->rps.hw_lock);
6178         dev_priv->pc8.enabled = false;
6179 }
6180
6181 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6182 {
6183         mutex_lock(&dev_priv->pc8.lock);
6184         __hsw_enable_package_c8(dev_priv);
6185         mutex_unlock(&dev_priv->pc8.lock);
6186 }
6187
6188 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6189 {
6190         mutex_lock(&dev_priv->pc8.lock);
6191         __hsw_disable_package_c8(dev_priv);
6192         mutex_unlock(&dev_priv->pc8.lock);
6193 }
6194
6195 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6196 {
6197         struct drm_device *dev = dev_priv->dev;
6198         struct intel_crtc *crtc;
6199         uint32_t val;
6200
6201         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6202                 if (crtc->base.enabled)
6203                         return false;
6204
6205         /* This case is still possible since we have the i915.disable_power_well
6206          * parameter and also the KVMr or something else might be requesting the
6207          * power well. */
6208         val = I915_READ(HSW_PWR_WELL_DRIVER);
6209         if (val != 0) {
6210                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6211                 return false;
6212         }
6213
6214         return true;
6215 }
6216
6217 /* Since we're called from modeset_global_resources there's no way to
6218  * symmetrically increase and decrease the refcount, so we use
6219  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6220  * or not.
6221  */
6222 static void hsw_update_package_c8(struct drm_device *dev)
6223 {
6224         struct drm_i915_private *dev_priv = dev->dev_private;
6225         bool allow;
6226
6227         if (!i915_enable_pc8)
6228                 return;
6229
6230         mutex_lock(&dev_priv->pc8.lock);
6231
6232         allow = hsw_can_enable_package_c8(dev_priv);
6233
6234         if (allow == dev_priv->pc8.requirements_met)
6235                 goto done;
6236
6237         dev_priv->pc8.requirements_met = allow;
6238
6239         if (allow)
6240                 __hsw_enable_package_c8(dev_priv);
6241         else
6242                 __hsw_disable_package_c8(dev_priv);
6243
6244 done:
6245         mutex_unlock(&dev_priv->pc8.lock);
6246 }
6247
6248 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6249 {
6250         if (!dev_priv->pc8.gpu_idle) {
6251                 dev_priv->pc8.gpu_idle = true;
6252                 hsw_enable_package_c8(dev_priv);
6253         }
6254 }
6255
6256 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6257 {
6258         if (dev_priv->pc8.gpu_idle) {
6259                 dev_priv->pc8.gpu_idle = false;
6260                 hsw_disable_package_c8(dev_priv);
6261         }
6262 }
6263
6264 static void haswell_modeset_global_resources(struct drm_device *dev)
6265 {
6266         bool enable = false;
6267         struct intel_crtc *crtc;
6268
6269         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6270                 if (!crtc->base.enabled)
6271                         continue;
6272
6273                 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6274                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
6275                         enable = true;
6276         }
6277
6278         intel_set_power_well(dev, enable);
6279
6280         hsw_update_package_c8(dev);
6281 }
6282
6283 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6284                                  int x, int y,
6285                                  struct drm_framebuffer *fb)
6286 {
6287         struct drm_device *dev = crtc->dev;
6288         struct drm_i915_private *dev_priv = dev->dev_private;
6289         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6290         int plane = intel_crtc->plane;
6291         int ret;
6292
6293         if (!intel_ddi_pll_mode_set(crtc))
6294                 return -EINVAL;
6295
6296         /* Ensure that the cursor is valid for the new mode before changing... */
6297         intel_crtc_update_cursor(crtc, true);
6298
6299         if (intel_crtc->config.has_dp_encoder)
6300                 intel_dp_set_m_n(intel_crtc);
6301
6302         intel_crtc->lowfreq_avail = false;
6303
6304         intel_set_pipe_timings(intel_crtc);
6305
6306         if (intel_crtc->config.has_pch_encoder) {
6307                 intel_cpu_transcoder_set_m_n(intel_crtc,
6308                                              &intel_crtc->config.fdi_m_n);
6309         }
6310
6311         haswell_set_pipeconf(crtc);
6312
6313         intel_set_pipe_csc(crtc);
6314
6315         /* Set up the display plane register */
6316         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6317         POSTING_READ(DSPCNTR(plane));
6318
6319         ret = intel_pipe_set_base(crtc, x, y, fb);
6320
6321         intel_update_watermarks(dev);
6322
6323         return ret;
6324 }
6325
6326 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6327                                     struct intel_crtc_config *pipe_config)
6328 {
6329         struct drm_device *dev = crtc->base.dev;
6330         struct drm_i915_private *dev_priv = dev->dev_private;
6331         enum intel_display_power_domain pfit_domain;
6332         uint32_t tmp;
6333
6334         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6335         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6336
6337         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6338         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6339                 enum pipe trans_edp_pipe;
6340                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6341                 default:
6342                         WARN(1, "unknown pipe linked to edp transcoder\n");
6343                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6344                 case TRANS_DDI_EDP_INPUT_A_ON:
6345                         trans_edp_pipe = PIPE_A;
6346                         break;
6347                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6348                         trans_edp_pipe = PIPE_B;
6349                         break;
6350                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6351                         trans_edp_pipe = PIPE_C;
6352                         break;
6353                 }
6354
6355                 if (trans_edp_pipe == crtc->pipe)
6356                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6357         }
6358
6359         if (!intel_display_power_enabled(dev,
6360                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6361                 return false;
6362
6363         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6364         if (!(tmp & PIPECONF_ENABLE))
6365                 return false;
6366
6367         /*
6368          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6369          * DDI E. So just check whether this pipe is wired to DDI E and whether
6370          * the PCH transcoder is on.
6371          */
6372         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6373         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6374             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6375                 pipe_config->has_pch_encoder = true;
6376
6377                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6378                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6379                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6380
6381                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6382         }
6383
6384         intel_get_pipe_timings(crtc, pipe_config);
6385
6386         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6387         if (intel_display_power_enabled(dev, pfit_domain))
6388                 ironlake_get_pfit_config(crtc, pipe_config);
6389
6390         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6391                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6392
6393         pipe_config->pixel_multiplier = 1;
6394
6395         return true;
6396 }
6397
6398 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6399                                int x, int y,
6400                                struct drm_framebuffer *fb)
6401 {
6402         struct drm_device *dev = crtc->dev;
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         struct intel_encoder *encoder;
6405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6407         int pipe = intel_crtc->pipe;
6408         int ret;
6409
6410         drm_vblank_pre_modeset(dev, pipe);
6411
6412         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6413
6414         drm_vblank_post_modeset(dev, pipe);
6415
6416         if (ret != 0)
6417                 return ret;
6418
6419         for_each_encoder_on_crtc(dev, crtc, encoder) {
6420                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6421                         encoder->base.base.id,
6422                         drm_get_encoder_name(&encoder->base),
6423                         mode->base.id, mode->name);
6424                 encoder->mode_set(encoder);
6425         }
6426
6427         return 0;
6428 }
6429
6430 static bool intel_eld_uptodate(struct drm_connector *connector,
6431                                int reg_eldv, uint32_t bits_eldv,
6432                                int reg_elda, uint32_t bits_elda,
6433                                int reg_edid)
6434 {
6435         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6436         uint8_t *eld = connector->eld;
6437         uint32_t i;
6438
6439         i = I915_READ(reg_eldv);
6440         i &= bits_eldv;
6441
6442         if (!eld[0])
6443                 return !i;
6444
6445         if (!i)
6446                 return false;
6447
6448         i = I915_READ(reg_elda);
6449         i &= ~bits_elda;
6450         I915_WRITE(reg_elda, i);
6451
6452         for (i = 0; i < eld[2]; i++)
6453                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6454                         return false;
6455
6456         return true;
6457 }
6458
6459 static void g4x_write_eld(struct drm_connector *connector,
6460                           struct drm_crtc *crtc)
6461 {
6462         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6463         uint8_t *eld = connector->eld;
6464         uint32_t eldv;
6465         uint32_t len;
6466         uint32_t i;
6467
6468         i = I915_READ(G4X_AUD_VID_DID);
6469
6470         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6471                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6472         else
6473                 eldv = G4X_ELDV_DEVCTG;
6474
6475         if (intel_eld_uptodate(connector,
6476                                G4X_AUD_CNTL_ST, eldv,
6477                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6478                                G4X_HDMIW_HDMIEDID))
6479                 return;
6480
6481         i = I915_READ(G4X_AUD_CNTL_ST);
6482         i &= ~(eldv | G4X_ELD_ADDR);
6483         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6484         I915_WRITE(G4X_AUD_CNTL_ST, i);
6485
6486         if (!eld[0])
6487                 return;
6488
6489         len = min_t(uint8_t, eld[2], len);
6490         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6491         for (i = 0; i < len; i++)
6492                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6493
6494         i = I915_READ(G4X_AUD_CNTL_ST);
6495         i |= eldv;
6496         I915_WRITE(G4X_AUD_CNTL_ST, i);
6497 }
6498
6499 static void haswell_write_eld(struct drm_connector *connector,
6500                                      struct drm_crtc *crtc)
6501 {
6502         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6503         uint8_t *eld = connector->eld;
6504         struct drm_device *dev = crtc->dev;
6505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6506         uint32_t eldv;
6507         uint32_t i;
6508         int len;
6509         int pipe = to_intel_crtc(crtc)->pipe;
6510         int tmp;
6511
6512         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6513         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6514         int aud_config = HSW_AUD_CFG(pipe);
6515         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6516
6517
6518         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6519
6520         /* Audio output enable */
6521         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6522         tmp = I915_READ(aud_cntrl_st2);
6523         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6524         I915_WRITE(aud_cntrl_st2, tmp);
6525
6526         /* Wait for 1 vertical blank */
6527         intel_wait_for_vblank(dev, pipe);
6528
6529         /* Set ELD valid state */
6530         tmp = I915_READ(aud_cntrl_st2);
6531         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6532         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6533         I915_WRITE(aud_cntrl_st2, tmp);
6534         tmp = I915_READ(aud_cntrl_st2);
6535         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6536
6537         /* Enable HDMI mode */
6538         tmp = I915_READ(aud_config);
6539         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6540         /* clear N_programing_enable and N_value_index */
6541         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6542         I915_WRITE(aud_config, tmp);
6543
6544         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6545
6546         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6547         intel_crtc->eld_vld = true;
6548
6549         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6550                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6551                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6552                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6553         } else
6554                 I915_WRITE(aud_config, 0);
6555
6556         if (intel_eld_uptodate(connector,
6557                                aud_cntrl_st2, eldv,
6558                                aud_cntl_st, IBX_ELD_ADDRESS,
6559                                hdmiw_hdmiedid))
6560                 return;
6561
6562         i = I915_READ(aud_cntrl_st2);
6563         i &= ~eldv;
6564         I915_WRITE(aud_cntrl_st2, i);
6565
6566         if (!eld[0])
6567                 return;
6568
6569         i = I915_READ(aud_cntl_st);
6570         i &= ~IBX_ELD_ADDRESS;
6571         I915_WRITE(aud_cntl_st, i);
6572         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6573         DRM_DEBUG_DRIVER("port num:%d\n", i);
6574
6575         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6576         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6577         for (i = 0; i < len; i++)
6578                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6579
6580         i = I915_READ(aud_cntrl_st2);
6581         i |= eldv;
6582         I915_WRITE(aud_cntrl_st2, i);
6583
6584 }
6585
6586 static void ironlake_write_eld(struct drm_connector *connector,
6587                                      struct drm_crtc *crtc)
6588 {
6589         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6590         uint8_t *eld = connector->eld;
6591         uint32_t eldv;
6592         uint32_t i;
6593         int len;
6594         int hdmiw_hdmiedid;
6595         int aud_config;
6596         int aud_cntl_st;
6597         int aud_cntrl_st2;
6598         int pipe = to_intel_crtc(crtc)->pipe;
6599
6600         if (HAS_PCH_IBX(connector->dev)) {
6601                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6602                 aud_config = IBX_AUD_CFG(pipe);
6603                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6604                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6605         } else {
6606                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6607                 aud_config = CPT_AUD_CFG(pipe);
6608                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6609                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6610         }
6611
6612         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6613
6614         i = I915_READ(aud_cntl_st);
6615         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6616         if (!i) {
6617                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6618                 /* operate blindly on all ports */
6619                 eldv = IBX_ELD_VALIDB;
6620                 eldv |= IBX_ELD_VALIDB << 4;
6621                 eldv |= IBX_ELD_VALIDB << 8;
6622         } else {
6623                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6624                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6625         }
6626
6627         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6628                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6629                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6630                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6631         } else
6632                 I915_WRITE(aud_config, 0);
6633
6634         if (intel_eld_uptodate(connector,
6635                                aud_cntrl_st2, eldv,
6636                                aud_cntl_st, IBX_ELD_ADDRESS,
6637                                hdmiw_hdmiedid))
6638                 return;
6639
6640         i = I915_READ(aud_cntrl_st2);
6641         i &= ~eldv;
6642         I915_WRITE(aud_cntrl_st2, i);
6643
6644         if (!eld[0])
6645                 return;
6646
6647         i = I915_READ(aud_cntl_st);
6648         i &= ~IBX_ELD_ADDRESS;
6649         I915_WRITE(aud_cntl_st, i);
6650
6651         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6652         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6653         for (i = 0; i < len; i++)
6654                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6655
6656         i = I915_READ(aud_cntrl_st2);
6657         i |= eldv;
6658         I915_WRITE(aud_cntrl_st2, i);
6659 }
6660
6661 void intel_write_eld(struct drm_encoder *encoder,
6662                      struct drm_display_mode *mode)
6663 {
6664         struct drm_crtc *crtc = encoder->crtc;
6665         struct drm_connector *connector;
6666         struct drm_device *dev = encoder->dev;
6667         struct drm_i915_private *dev_priv = dev->dev_private;
6668
6669         connector = drm_select_eld(encoder, mode);
6670         if (!connector)
6671                 return;
6672
6673         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6674                          connector->base.id,
6675                          drm_get_connector_name(connector),
6676                          connector->encoder->base.id,
6677                          drm_get_encoder_name(connector->encoder));
6678
6679         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6680
6681         if (dev_priv->display.write_eld)
6682                 dev_priv->display.write_eld(connector, crtc);
6683 }
6684
6685 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6686 void intel_crtc_load_lut(struct drm_crtc *crtc)
6687 {
6688         struct drm_device *dev = crtc->dev;
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6691         enum pipe pipe = intel_crtc->pipe;
6692         int palreg = PALETTE(pipe);
6693         int i;
6694         bool reenable_ips = false;
6695
6696         /* The clocks have to be on to load the palette. */
6697         if (!crtc->enabled || !intel_crtc->active)
6698                 return;
6699
6700         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6701                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6702                         assert_dsi_pll_enabled(dev_priv);
6703                 else
6704                         assert_pll_enabled(dev_priv, pipe);
6705         }
6706
6707         /* use legacy palette for Ironlake */
6708         if (HAS_PCH_SPLIT(dev))
6709                 palreg = LGC_PALETTE(pipe);
6710
6711         /* Workaround : Do not read or write the pipe palette/gamma data while
6712          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6713          */
6714         if (intel_crtc->config.ips_enabled &&
6715             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6716              GAMMA_MODE_MODE_SPLIT)) {
6717                 hsw_disable_ips(intel_crtc);
6718                 reenable_ips = true;
6719         }
6720
6721         for (i = 0; i < 256; i++) {
6722                 I915_WRITE(palreg + 4 * i,
6723                            (intel_crtc->lut_r[i] << 16) |
6724                            (intel_crtc->lut_g[i] << 8) |
6725                            intel_crtc->lut_b[i]);
6726         }
6727
6728         if (reenable_ips)
6729                 hsw_enable_ips(intel_crtc);
6730 }
6731
6732 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6733 {
6734         struct drm_device *dev = crtc->dev;
6735         struct drm_i915_private *dev_priv = dev->dev_private;
6736         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737         bool visible = base != 0;
6738         u32 cntl;
6739
6740         if (intel_crtc->cursor_visible == visible)
6741                 return;
6742
6743         cntl = I915_READ(_CURACNTR);
6744         if (visible) {
6745                 /* On these chipsets we can only modify the base whilst
6746                  * the cursor is disabled.
6747                  */
6748                 I915_WRITE(_CURABASE, base);
6749
6750                 cntl &= ~(CURSOR_FORMAT_MASK);
6751                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6752                 cntl |= CURSOR_ENABLE |
6753                         CURSOR_GAMMA_ENABLE |
6754                         CURSOR_FORMAT_ARGB;
6755         } else
6756                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6757         I915_WRITE(_CURACNTR, cntl);
6758
6759         intel_crtc->cursor_visible = visible;
6760 }
6761
6762 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6763 {
6764         struct drm_device *dev = crtc->dev;
6765         struct drm_i915_private *dev_priv = dev->dev_private;
6766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6767         int pipe = intel_crtc->pipe;
6768         bool visible = base != 0;
6769
6770         if (intel_crtc->cursor_visible != visible) {
6771                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6772                 if (base) {
6773                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6774                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6775                         cntl |= pipe << 28; /* Connect to correct pipe */
6776                 } else {
6777                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6778                         cntl |= CURSOR_MODE_DISABLE;
6779                 }
6780                 I915_WRITE(CURCNTR(pipe), cntl);
6781
6782                 intel_crtc->cursor_visible = visible;
6783         }
6784         /* and commit changes on next vblank */
6785         I915_WRITE(CURBASE(pipe), base);
6786 }
6787
6788 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6789 {
6790         struct drm_device *dev = crtc->dev;
6791         struct drm_i915_private *dev_priv = dev->dev_private;
6792         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6793         int pipe = intel_crtc->pipe;
6794         bool visible = base != 0;
6795
6796         if (intel_crtc->cursor_visible != visible) {
6797                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6798                 if (base) {
6799                         cntl &= ~CURSOR_MODE;
6800                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6801                 } else {
6802                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6803                         cntl |= CURSOR_MODE_DISABLE;
6804                 }
6805                 if (IS_HASWELL(dev)) {
6806                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6807                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6808                 }
6809                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6810
6811                 intel_crtc->cursor_visible = visible;
6812         }
6813         /* and commit changes on next vblank */
6814         I915_WRITE(CURBASE_IVB(pipe), base);
6815 }
6816
6817 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6818 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6819                                      bool on)
6820 {
6821         struct drm_device *dev = crtc->dev;
6822         struct drm_i915_private *dev_priv = dev->dev_private;
6823         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6824         int pipe = intel_crtc->pipe;
6825         int x = intel_crtc->cursor_x;
6826         int y = intel_crtc->cursor_y;
6827         u32 base, pos;
6828         bool visible;
6829
6830         pos = 0;
6831
6832         if (on && crtc->enabled && crtc->fb) {
6833                 base = intel_crtc->cursor_addr;
6834                 if (x > (int) crtc->fb->width)
6835                         base = 0;
6836
6837                 if (y > (int) crtc->fb->height)
6838                         base = 0;
6839         } else
6840                 base = 0;
6841
6842         if (x < 0) {
6843                 if (x + intel_crtc->cursor_width < 0)
6844                         base = 0;
6845
6846                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6847                 x = -x;
6848         }
6849         pos |= x << CURSOR_X_SHIFT;
6850
6851         if (y < 0) {
6852                 if (y + intel_crtc->cursor_height < 0)
6853                         base = 0;
6854
6855                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6856                 y = -y;
6857         }
6858         pos |= y << CURSOR_Y_SHIFT;
6859
6860         visible = base != 0;
6861         if (!visible && !intel_crtc->cursor_visible)
6862                 return;
6863
6864         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6865                 I915_WRITE(CURPOS_IVB(pipe), pos);
6866                 ivb_update_cursor(crtc, base);
6867         } else {
6868                 I915_WRITE(CURPOS(pipe), pos);
6869                 if (IS_845G(dev) || IS_I865G(dev))
6870                         i845_update_cursor(crtc, base);
6871                 else
6872                         i9xx_update_cursor(crtc, base);
6873         }
6874 }
6875
6876 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6877                                  struct drm_file *file,
6878                                  uint32_t handle,
6879                                  uint32_t width, uint32_t height)
6880 {
6881         struct drm_device *dev = crtc->dev;
6882         struct drm_i915_private *dev_priv = dev->dev_private;
6883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6884         struct drm_i915_gem_object *obj;
6885         uint32_t addr;
6886         int ret;
6887
6888         /* if we want to turn off the cursor ignore width and height */
6889         if (!handle) {
6890                 DRM_DEBUG_KMS("cursor off\n");
6891                 addr = 0;
6892                 obj = NULL;
6893                 mutex_lock(&dev->struct_mutex);
6894                 goto finish;
6895         }
6896
6897         /* Currently we only support 64x64 cursors */
6898         if (width != 64 || height != 64) {
6899                 DRM_ERROR("we currently only support 64x64 cursors\n");
6900                 return -EINVAL;
6901         }
6902
6903         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6904         if (&obj->base == NULL)
6905                 return -ENOENT;
6906
6907         if (obj->base.size < width * height * 4) {
6908                 DRM_ERROR("buffer is to small\n");
6909                 ret = -ENOMEM;
6910                 goto fail;
6911         }
6912
6913         /* we only need to pin inside GTT if cursor is non-phy */
6914         mutex_lock(&dev->struct_mutex);
6915         if (!dev_priv->info->cursor_needs_physical) {
6916                 unsigned alignment;
6917
6918                 if (obj->tiling_mode) {
6919                         DRM_ERROR("cursor cannot be tiled\n");
6920                         ret = -EINVAL;
6921                         goto fail_locked;
6922                 }
6923
6924                 /* Note that the w/a also requires 2 PTE of padding following
6925                  * the bo. We currently fill all unused PTE with the shadow
6926                  * page and so we should always have valid PTE following the
6927                  * cursor preventing the VT-d warning.
6928                  */
6929                 alignment = 0;
6930                 if (need_vtd_wa(dev))
6931                         alignment = 64*1024;
6932
6933                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6934                 if (ret) {
6935                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6936                         goto fail_locked;
6937                 }
6938
6939                 ret = i915_gem_object_put_fence(obj);
6940                 if (ret) {
6941                         DRM_ERROR("failed to release fence for cursor");
6942                         goto fail_unpin;
6943                 }
6944
6945                 addr = i915_gem_obj_ggtt_offset(obj);
6946         } else {
6947                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6948                 ret = i915_gem_attach_phys_object(dev, obj,
6949                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6950                                                   align);
6951                 if (ret) {
6952                         DRM_ERROR("failed to attach phys object\n");
6953                         goto fail_locked;
6954                 }
6955                 addr = obj->phys_obj->handle->busaddr;
6956         }
6957
6958         if (IS_GEN2(dev))
6959                 I915_WRITE(CURSIZE, (height << 12) | width);
6960
6961  finish:
6962         if (intel_crtc->cursor_bo) {
6963                 if (dev_priv->info->cursor_needs_physical) {
6964                         if (intel_crtc->cursor_bo != obj)
6965                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6966                 } else
6967                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
6968                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6969         }
6970
6971         mutex_unlock(&dev->struct_mutex);
6972
6973         intel_crtc->cursor_addr = addr;
6974         intel_crtc->cursor_bo = obj;
6975         intel_crtc->cursor_width = width;
6976         intel_crtc->cursor_height = height;
6977
6978         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6979
6980         return 0;
6981 fail_unpin:
6982         i915_gem_object_unpin_from_display_plane(obj);
6983 fail_locked:
6984         mutex_unlock(&dev->struct_mutex);
6985 fail:
6986         drm_gem_object_unreference_unlocked(&obj->base);
6987         return ret;
6988 }
6989
6990 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6991 {
6992         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6993
6994         intel_crtc->cursor_x = x;
6995         intel_crtc->cursor_y = y;
6996
6997         intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6998
6999         return 0;
7000 }
7001
7002 /** Sets the color ramps on behalf of RandR */
7003 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7004                                  u16 blue, int regno)
7005 {
7006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007
7008         intel_crtc->lut_r[regno] = red >> 8;
7009         intel_crtc->lut_g[regno] = green >> 8;
7010         intel_crtc->lut_b[regno] = blue >> 8;
7011 }
7012
7013 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7014                              u16 *blue, int regno)
7015 {
7016         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7017
7018         *red = intel_crtc->lut_r[regno] << 8;
7019         *green = intel_crtc->lut_g[regno] << 8;
7020         *blue = intel_crtc->lut_b[regno] << 8;
7021 }
7022
7023 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7024                                  u16 *blue, uint32_t start, uint32_t size)
7025 {
7026         int end = (start + size > 256) ? 256 : start + size, i;
7027         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7028
7029         for (i = start; i < end; i++) {
7030                 intel_crtc->lut_r[i] = red[i] >> 8;
7031                 intel_crtc->lut_g[i] = green[i] >> 8;
7032                 intel_crtc->lut_b[i] = blue[i] >> 8;
7033         }
7034
7035         intel_crtc_load_lut(crtc);
7036 }
7037
7038 /* VESA 640x480x72Hz mode to set on the pipe */
7039 static struct drm_display_mode load_detect_mode = {
7040         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7041                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7042 };
7043
7044 static struct drm_framebuffer *
7045 intel_framebuffer_create(struct drm_device *dev,
7046                          struct drm_mode_fb_cmd2 *mode_cmd,
7047                          struct drm_i915_gem_object *obj)
7048 {
7049         struct intel_framebuffer *intel_fb;
7050         int ret;
7051
7052         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7053         if (!intel_fb) {
7054                 drm_gem_object_unreference_unlocked(&obj->base);
7055                 return ERR_PTR(-ENOMEM);
7056         }
7057
7058         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7059         if (ret) {
7060                 drm_gem_object_unreference_unlocked(&obj->base);
7061                 kfree(intel_fb);
7062                 return ERR_PTR(ret);
7063         }
7064
7065         return &intel_fb->base;
7066 }
7067
7068 static u32
7069 intel_framebuffer_pitch_for_width(int width, int bpp)
7070 {
7071         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7072         return ALIGN(pitch, 64);
7073 }
7074
7075 static u32
7076 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7077 {
7078         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7079         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7080 }
7081
7082 static struct drm_framebuffer *
7083 intel_framebuffer_create_for_mode(struct drm_device *dev,
7084                                   struct drm_display_mode *mode,
7085                                   int depth, int bpp)
7086 {
7087         struct drm_i915_gem_object *obj;
7088         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7089
7090         obj = i915_gem_alloc_object(dev,
7091                                     intel_framebuffer_size_for_mode(mode, bpp));
7092         if (obj == NULL)
7093                 return ERR_PTR(-ENOMEM);
7094
7095         mode_cmd.width = mode->hdisplay;
7096         mode_cmd.height = mode->vdisplay;
7097         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7098                                                                 bpp);
7099         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7100
7101         return intel_framebuffer_create(dev, &mode_cmd, obj);
7102 }
7103
7104 static struct drm_framebuffer *
7105 mode_fits_in_fbdev(struct drm_device *dev,
7106                    struct drm_display_mode *mode)
7107 {
7108         struct drm_i915_private *dev_priv = dev->dev_private;
7109         struct drm_i915_gem_object *obj;
7110         struct drm_framebuffer *fb;
7111
7112         if (dev_priv->fbdev == NULL)
7113                 return NULL;
7114
7115         obj = dev_priv->fbdev->ifb.obj;
7116         if (obj == NULL)
7117                 return NULL;
7118
7119         fb = &dev_priv->fbdev->ifb.base;
7120         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7121                                                                fb->bits_per_pixel))
7122                 return NULL;
7123
7124         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7125                 return NULL;
7126
7127         return fb;
7128 }
7129
7130 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7131                                 struct drm_display_mode *mode,
7132                                 struct intel_load_detect_pipe *old)
7133 {
7134         struct intel_crtc *intel_crtc;
7135         struct intel_encoder *intel_encoder =
7136                 intel_attached_encoder(connector);
7137         struct drm_crtc *possible_crtc;
7138         struct drm_encoder *encoder = &intel_encoder->base;
7139         struct drm_crtc *crtc = NULL;
7140         struct drm_device *dev = encoder->dev;
7141         struct drm_framebuffer *fb;
7142         int i = -1;
7143
7144         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7145                       connector->base.id, drm_get_connector_name(connector),
7146                       encoder->base.id, drm_get_encoder_name(encoder));
7147
7148         /*
7149          * Algorithm gets a little messy:
7150          *
7151          *   - if the connector already has an assigned crtc, use it (but make
7152          *     sure it's on first)
7153          *
7154          *   - try to find the first unused crtc that can drive this connector,
7155          *     and use that if we find one
7156          */
7157
7158         /* See if we already have a CRTC for this connector */
7159         if (encoder->crtc) {
7160                 crtc = encoder->crtc;
7161
7162                 mutex_lock(&crtc->mutex);
7163
7164                 old->dpms_mode = connector->dpms;
7165                 old->load_detect_temp = false;
7166
7167                 /* Make sure the crtc and connector are running */
7168                 if (connector->dpms != DRM_MODE_DPMS_ON)
7169                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7170
7171                 return true;
7172         }
7173
7174         /* Find an unused one (if possible) */
7175         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7176                 i++;
7177                 if (!(encoder->possible_crtcs & (1 << i)))
7178                         continue;
7179                 if (!possible_crtc->enabled) {
7180                         crtc = possible_crtc;
7181                         break;
7182                 }
7183         }
7184
7185         /*
7186          * If we didn't find an unused CRTC, don't use any.
7187          */
7188         if (!crtc) {
7189                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7190                 return false;
7191         }
7192
7193         mutex_lock(&crtc->mutex);
7194         intel_encoder->new_crtc = to_intel_crtc(crtc);
7195         to_intel_connector(connector)->new_encoder = intel_encoder;
7196
7197         intel_crtc = to_intel_crtc(crtc);
7198         old->dpms_mode = connector->dpms;
7199         old->load_detect_temp = true;
7200         old->release_fb = NULL;
7201
7202         if (!mode)
7203                 mode = &load_detect_mode;
7204
7205         /* We need a framebuffer large enough to accommodate all accesses
7206          * that the plane may generate whilst we perform load detection.
7207          * We can not rely on the fbcon either being present (we get called
7208          * during its initialisation to detect all boot displays, or it may
7209          * not even exist) or that it is large enough to satisfy the
7210          * requested mode.
7211          */
7212         fb = mode_fits_in_fbdev(dev, mode);
7213         if (fb == NULL) {
7214                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7215                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7216                 old->release_fb = fb;
7217         } else
7218                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7219         if (IS_ERR(fb)) {
7220                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7221                 mutex_unlock(&crtc->mutex);
7222                 return false;
7223         }
7224
7225         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7226                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7227                 if (old->release_fb)
7228                         old->release_fb->funcs->destroy(old->release_fb);
7229                 mutex_unlock(&crtc->mutex);
7230                 return false;
7231         }
7232
7233         /* let the connector get through one full cycle before testing */
7234         intel_wait_for_vblank(dev, intel_crtc->pipe);
7235         return true;
7236 }
7237
7238 void intel_release_load_detect_pipe(struct drm_connector *connector,
7239                                     struct intel_load_detect_pipe *old)
7240 {
7241         struct intel_encoder *intel_encoder =
7242                 intel_attached_encoder(connector);
7243         struct drm_encoder *encoder = &intel_encoder->base;
7244         struct drm_crtc *crtc = encoder->crtc;
7245
7246         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7247                       connector->base.id, drm_get_connector_name(connector),
7248                       encoder->base.id, drm_get_encoder_name(encoder));
7249
7250         if (old->load_detect_temp) {
7251                 to_intel_connector(connector)->new_encoder = NULL;
7252                 intel_encoder->new_crtc = NULL;
7253                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7254
7255                 if (old->release_fb) {
7256                         drm_framebuffer_unregister_private(old->release_fb);
7257                         drm_framebuffer_unreference(old->release_fb);
7258                 }
7259
7260                 mutex_unlock(&crtc->mutex);
7261                 return;
7262         }
7263
7264         /* Switch crtc and encoder back off if necessary */
7265         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7266                 connector->funcs->dpms(connector, old->dpms_mode);
7267
7268         mutex_unlock(&crtc->mutex);
7269 }
7270
7271 /* Returns the clock of the currently programmed mode of the given pipe. */
7272 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7273                                 struct intel_crtc_config *pipe_config)
7274 {
7275         struct drm_device *dev = crtc->base.dev;
7276         struct drm_i915_private *dev_priv = dev->dev_private;
7277         int pipe = pipe_config->cpu_transcoder;
7278         u32 dpll = I915_READ(DPLL(pipe));
7279         u32 fp;
7280         intel_clock_t clock;
7281
7282         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7283                 fp = I915_READ(FP0(pipe));
7284         else
7285                 fp = I915_READ(FP1(pipe));
7286
7287         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7288         if (IS_PINEVIEW(dev)) {
7289                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7290                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7291         } else {
7292                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7293                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7294         }
7295
7296         if (!IS_GEN2(dev)) {
7297                 if (IS_PINEVIEW(dev))
7298                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7299                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7300                 else
7301                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7302                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7303
7304                 switch (dpll & DPLL_MODE_MASK) {
7305                 case DPLLB_MODE_DAC_SERIAL:
7306                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7307                                 5 : 10;
7308                         break;
7309                 case DPLLB_MODE_LVDS:
7310                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7311                                 7 : 14;
7312                         break;
7313                 default:
7314                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7315                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7316                         pipe_config->adjusted_mode.clock = 0;
7317                         return;
7318                 }
7319
7320                 if (IS_PINEVIEW(dev))
7321                         pineview_clock(96000, &clock);
7322                 else
7323                         i9xx_clock(96000, &clock);
7324         } else {
7325                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7326
7327                 if (is_lvds) {
7328                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7329                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7330                         clock.p2 = 14;
7331
7332                         if ((dpll & PLL_REF_INPUT_MASK) ==
7333                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7334                                 /* XXX: might not be 66MHz */
7335                                 i9xx_clock(66000, &clock);
7336                         } else
7337                                 i9xx_clock(48000, &clock);
7338                 } else {
7339                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7340                                 clock.p1 = 2;
7341                         else {
7342                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7343                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7344                         }
7345                         if (dpll & PLL_P2_DIVIDE_BY_4)
7346                                 clock.p2 = 4;
7347                         else
7348                                 clock.p2 = 2;
7349
7350                         i9xx_clock(48000, &clock);
7351                 }
7352         }
7353
7354         pipe_config->adjusted_mode.clock = clock.dot;
7355 }
7356
7357 static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7358                                     struct intel_crtc_config *pipe_config)
7359 {
7360         struct drm_device *dev = crtc->base.dev;
7361         struct drm_i915_private *dev_priv = dev->dev_private;
7362         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7363         int link_freq, repeat;
7364         u64 clock;
7365         u32 link_m, link_n;
7366
7367         repeat = pipe_config->pixel_multiplier;
7368
7369         /*
7370          * The calculation for the data clock is:
7371          * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7372          * But we want to avoid losing precison if possible, so:
7373          * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7374          *
7375          * and the link clock is simpler:
7376          * link_clock = (m * link_clock * repeat) / n
7377          */
7378
7379         /*
7380          * We need to get the FDI or DP link clock here to derive
7381          * the M/N dividers.
7382          *
7383          * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7384          * For DP, it's either 1.62GHz or 2.7GHz.
7385          * We do our calculations in 10*MHz since we don't need much precison.
7386          */
7387         if (pipe_config->has_pch_encoder)
7388                 link_freq = intel_fdi_link_freq(dev) * 10000;
7389         else
7390                 link_freq = pipe_config->port_clock;
7391
7392         link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7393         link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7394
7395         if (!link_m || !link_n)
7396                 return;
7397
7398         clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7399         do_div(clock, link_n);
7400
7401         pipe_config->adjusted_mode.clock = clock;
7402 }
7403
7404 /** Returns the currently programmed mode of the given pipe. */
7405 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7406                                              struct drm_crtc *crtc)
7407 {
7408         struct drm_i915_private *dev_priv = dev->dev_private;
7409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7410         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7411         struct drm_display_mode *mode;
7412         struct intel_crtc_config pipe_config;
7413         int htot = I915_READ(HTOTAL(cpu_transcoder));
7414         int hsync = I915_READ(HSYNC(cpu_transcoder));
7415         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7416         int vsync = I915_READ(VSYNC(cpu_transcoder));
7417
7418         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7419         if (!mode)
7420                 return NULL;
7421
7422         /*
7423          * Construct a pipe_config sufficient for getting the clock info
7424          * back out of crtc_clock_get.
7425          *
7426          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7427          * to use a real value here instead.
7428          */
7429         pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
7430         pipe_config.pixel_multiplier = 1;
7431         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7432
7433         mode->clock = pipe_config.adjusted_mode.clock;
7434         mode->hdisplay = (htot & 0xffff) + 1;
7435         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7436         mode->hsync_start = (hsync & 0xffff) + 1;
7437         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7438         mode->vdisplay = (vtot & 0xffff) + 1;
7439         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7440         mode->vsync_start = (vsync & 0xffff) + 1;
7441         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7442
7443         drm_mode_set_name(mode);
7444
7445         return mode;
7446 }
7447
7448 static void intel_increase_pllclock(struct drm_crtc *crtc)
7449 {
7450         struct drm_device *dev = crtc->dev;
7451         drm_i915_private_t *dev_priv = dev->dev_private;
7452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7453         int pipe = intel_crtc->pipe;
7454         int dpll_reg = DPLL(pipe);
7455         int dpll;
7456
7457         if (HAS_PCH_SPLIT(dev))
7458                 return;
7459
7460         if (!dev_priv->lvds_downclock_avail)
7461                 return;
7462
7463         dpll = I915_READ(dpll_reg);
7464         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7465                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7466
7467                 assert_panel_unlocked(dev_priv, pipe);
7468
7469                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7470                 I915_WRITE(dpll_reg, dpll);
7471                 intel_wait_for_vblank(dev, pipe);
7472
7473                 dpll = I915_READ(dpll_reg);
7474                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7475                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7476         }
7477 }
7478
7479 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7480 {
7481         struct drm_device *dev = crtc->dev;
7482         drm_i915_private_t *dev_priv = dev->dev_private;
7483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7484
7485         if (HAS_PCH_SPLIT(dev))
7486                 return;
7487
7488         if (!dev_priv->lvds_downclock_avail)
7489                 return;
7490
7491         /*
7492          * Since this is called by a timer, we should never get here in
7493          * the manual case.
7494          */
7495         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7496                 int pipe = intel_crtc->pipe;
7497                 int dpll_reg = DPLL(pipe);
7498                 int dpll;
7499
7500                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7501
7502                 assert_panel_unlocked(dev_priv, pipe);
7503
7504                 dpll = I915_READ(dpll_reg);
7505                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7506                 I915_WRITE(dpll_reg, dpll);
7507                 intel_wait_for_vblank(dev, pipe);
7508                 dpll = I915_READ(dpll_reg);
7509                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7510                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7511         }
7512
7513 }
7514
7515 void intel_mark_busy(struct drm_device *dev)
7516 {
7517         struct drm_i915_private *dev_priv = dev->dev_private;
7518
7519         hsw_package_c8_gpu_busy(dev_priv);
7520         i915_update_gfx_val(dev_priv);
7521 }
7522
7523 void intel_mark_idle(struct drm_device *dev)
7524 {
7525         struct drm_i915_private *dev_priv = dev->dev_private;
7526         struct drm_crtc *crtc;
7527
7528         hsw_package_c8_gpu_idle(dev_priv);
7529
7530         if (!i915_powersave)
7531                 return;
7532
7533         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7534                 if (!crtc->fb)
7535                         continue;
7536
7537                 intel_decrease_pllclock(crtc);
7538         }
7539 }
7540
7541 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7542                         struct intel_ring_buffer *ring)
7543 {
7544         struct drm_device *dev = obj->base.dev;
7545         struct drm_crtc *crtc;
7546
7547         if (!i915_powersave)
7548                 return;
7549
7550         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7551                 if (!crtc->fb)
7552                         continue;
7553
7554                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7555                         continue;
7556
7557                 intel_increase_pllclock(crtc);
7558                 if (ring && intel_fbc_enabled(dev))
7559                         ring->fbc_dirty = true;
7560         }
7561 }
7562
7563 static void intel_crtc_destroy(struct drm_crtc *crtc)
7564 {
7565         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7566         struct drm_device *dev = crtc->dev;
7567         struct intel_unpin_work *work;
7568         unsigned long flags;
7569
7570         spin_lock_irqsave(&dev->event_lock, flags);
7571         work = intel_crtc->unpin_work;
7572         intel_crtc->unpin_work = NULL;
7573         spin_unlock_irqrestore(&dev->event_lock, flags);
7574
7575         if (work) {
7576                 cancel_work_sync(&work->work);
7577                 kfree(work);
7578         }
7579
7580         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7581
7582         drm_crtc_cleanup(crtc);
7583
7584         kfree(intel_crtc);
7585 }
7586
7587 static void intel_unpin_work_fn(struct work_struct *__work)
7588 {
7589         struct intel_unpin_work *work =
7590                 container_of(__work, struct intel_unpin_work, work);
7591         struct drm_device *dev = work->crtc->dev;
7592
7593         mutex_lock(&dev->struct_mutex);
7594         intel_unpin_fb_obj(work->old_fb_obj);
7595         drm_gem_object_unreference(&work->pending_flip_obj->base);
7596         drm_gem_object_unreference(&work->old_fb_obj->base);
7597
7598         intel_update_fbc(dev);
7599         mutex_unlock(&dev->struct_mutex);
7600
7601         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7602         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7603
7604         kfree(work);
7605 }
7606
7607 static void do_intel_finish_page_flip(struct drm_device *dev,
7608                                       struct drm_crtc *crtc)
7609 {
7610         drm_i915_private_t *dev_priv = dev->dev_private;
7611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7612         struct intel_unpin_work *work;
7613         unsigned long flags;
7614
7615         /* Ignore early vblank irqs */
7616         if (intel_crtc == NULL)
7617                 return;
7618
7619         spin_lock_irqsave(&dev->event_lock, flags);
7620         work = intel_crtc->unpin_work;
7621
7622         /* Ensure we don't miss a work->pending update ... */
7623         smp_rmb();
7624
7625         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7626                 spin_unlock_irqrestore(&dev->event_lock, flags);
7627                 return;
7628         }
7629
7630         /* and that the unpin work is consistent wrt ->pending. */
7631         smp_rmb();
7632
7633         intel_crtc->unpin_work = NULL;
7634
7635         if (work->event)
7636                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7637
7638         drm_vblank_put(dev, intel_crtc->pipe);
7639
7640         spin_unlock_irqrestore(&dev->event_lock, flags);
7641
7642         wake_up_all(&dev_priv->pending_flip_queue);
7643
7644         queue_work(dev_priv->wq, &work->work);
7645
7646         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7647 }
7648
7649 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7650 {
7651         drm_i915_private_t *dev_priv = dev->dev_private;
7652         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7653
7654         do_intel_finish_page_flip(dev, crtc);
7655 }
7656
7657 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7658 {
7659         drm_i915_private_t *dev_priv = dev->dev_private;
7660         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7661
7662         do_intel_finish_page_flip(dev, crtc);
7663 }
7664
7665 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7666 {
7667         drm_i915_private_t *dev_priv = dev->dev_private;
7668         struct intel_crtc *intel_crtc =
7669                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7670         unsigned long flags;
7671
7672         /* NB: An MMIO update of the plane base pointer will also
7673          * generate a page-flip completion irq, i.e. every modeset
7674          * is also accompanied by a spurious intel_prepare_page_flip().
7675          */
7676         spin_lock_irqsave(&dev->event_lock, flags);
7677         if (intel_crtc->unpin_work)
7678                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7679         spin_unlock_irqrestore(&dev->event_lock, flags);
7680 }
7681
7682 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7683 {
7684         /* Ensure that the work item is consistent when activating it ... */
7685         smp_wmb();
7686         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7687         /* and that it is marked active as soon as the irq could fire. */
7688         smp_wmb();
7689 }
7690
7691 static int intel_gen2_queue_flip(struct drm_device *dev,
7692                                  struct drm_crtc *crtc,
7693                                  struct drm_framebuffer *fb,
7694                                  struct drm_i915_gem_object *obj,
7695                                  uint32_t flags)
7696 {
7697         struct drm_i915_private *dev_priv = dev->dev_private;
7698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7699         u32 flip_mask;
7700         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7701         int ret;
7702
7703         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7704         if (ret)
7705                 goto err;
7706
7707         ret = intel_ring_begin(ring, 6);
7708         if (ret)
7709                 goto err_unpin;
7710
7711         /* Can't queue multiple flips, so wait for the previous
7712          * one to finish before executing the next.
7713          */
7714         if (intel_crtc->plane)
7715                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7716         else
7717                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7718         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7719         intel_ring_emit(ring, MI_NOOP);
7720         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7721                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7722         intel_ring_emit(ring, fb->pitches[0]);
7723         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7724         intel_ring_emit(ring, 0); /* aux display base address, unused */
7725
7726         intel_mark_page_flip_active(intel_crtc);
7727         intel_ring_advance(ring);
7728         return 0;
7729
7730 err_unpin:
7731         intel_unpin_fb_obj(obj);
7732 err:
7733         return ret;
7734 }
7735
7736 static int intel_gen3_queue_flip(struct drm_device *dev,
7737                                  struct drm_crtc *crtc,
7738                                  struct drm_framebuffer *fb,
7739                                  struct drm_i915_gem_object *obj,
7740                                  uint32_t flags)
7741 {
7742         struct drm_i915_private *dev_priv = dev->dev_private;
7743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7744         u32 flip_mask;
7745         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7746         int ret;
7747
7748         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7749         if (ret)
7750                 goto err;
7751
7752         ret = intel_ring_begin(ring, 6);
7753         if (ret)
7754                 goto err_unpin;
7755
7756         if (intel_crtc->plane)
7757                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7758         else
7759                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7760         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7761         intel_ring_emit(ring, MI_NOOP);
7762         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7763                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7764         intel_ring_emit(ring, fb->pitches[0]);
7765         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7766         intel_ring_emit(ring, MI_NOOP);
7767
7768         intel_mark_page_flip_active(intel_crtc);
7769         intel_ring_advance(ring);
7770         return 0;
7771
7772 err_unpin:
7773         intel_unpin_fb_obj(obj);
7774 err:
7775         return ret;
7776 }
7777
7778 static int intel_gen4_queue_flip(struct drm_device *dev,
7779                                  struct drm_crtc *crtc,
7780                                  struct drm_framebuffer *fb,
7781                                  struct drm_i915_gem_object *obj,
7782                                  uint32_t flags)
7783 {
7784         struct drm_i915_private *dev_priv = dev->dev_private;
7785         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7786         uint32_t pf, pipesrc;
7787         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7788         int ret;
7789
7790         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7791         if (ret)
7792                 goto err;
7793
7794         ret = intel_ring_begin(ring, 4);
7795         if (ret)
7796                 goto err_unpin;
7797
7798         /* i965+ uses the linear or tiled offsets from the
7799          * Display Registers (which do not change across a page-flip)
7800          * so we need only reprogram the base address.
7801          */
7802         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7803                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7804         intel_ring_emit(ring, fb->pitches[0]);
7805         intel_ring_emit(ring,
7806                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
7807                         obj->tiling_mode);
7808
7809         /* XXX Enabling the panel-fitter across page-flip is so far
7810          * untested on non-native modes, so ignore it for now.
7811          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7812          */
7813         pf = 0;
7814         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7815         intel_ring_emit(ring, pf | pipesrc);
7816
7817         intel_mark_page_flip_active(intel_crtc);
7818         intel_ring_advance(ring);
7819         return 0;
7820
7821 err_unpin:
7822         intel_unpin_fb_obj(obj);
7823 err:
7824         return ret;
7825 }
7826
7827 static int intel_gen6_queue_flip(struct drm_device *dev,
7828                                  struct drm_crtc *crtc,
7829                                  struct drm_framebuffer *fb,
7830                                  struct drm_i915_gem_object *obj,
7831                                  uint32_t flags)
7832 {
7833         struct drm_i915_private *dev_priv = dev->dev_private;
7834         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7835         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7836         uint32_t pf, pipesrc;
7837         int ret;
7838
7839         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7840         if (ret)
7841                 goto err;
7842
7843         ret = intel_ring_begin(ring, 4);
7844         if (ret)
7845                 goto err_unpin;
7846
7847         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7848                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7849         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7850         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7851
7852         /* Contrary to the suggestions in the documentation,
7853          * "Enable Panel Fitter" does not seem to be required when page
7854          * flipping with a non-native mode, and worse causes a normal
7855          * modeset to fail.
7856          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7857          */
7858         pf = 0;
7859         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7860         intel_ring_emit(ring, pf | pipesrc);
7861
7862         intel_mark_page_flip_active(intel_crtc);
7863         intel_ring_advance(ring);
7864         return 0;
7865
7866 err_unpin:
7867         intel_unpin_fb_obj(obj);
7868 err:
7869         return ret;
7870 }
7871
7872 static int intel_gen7_queue_flip(struct drm_device *dev,
7873                                  struct drm_crtc *crtc,
7874                                  struct drm_framebuffer *fb,
7875                                  struct drm_i915_gem_object *obj,
7876                                  uint32_t flags)
7877 {
7878         struct drm_i915_private *dev_priv = dev->dev_private;
7879         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7880         struct intel_ring_buffer *ring;
7881         uint32_t plane_bit = 0;
7882         int len, ret;
7883
7884         ring = obj->ring;
7885         if (ring == NULL || ring->id != RCS)
7886                 ring = &dev_priv->ring[BCS];
7887
7888         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7889         if (ret)
7890                 goto err;
7891
7892         switch(intel_crtc->plane) {
7893         case PLANE_A:
7894                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7895                 break;
7896         case PLANE_B:
7897                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7898                 break;
7899         case PLANE_C:
7900                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7901                 break;
7902         default:
7903                 WARN_ONCE(1, "unknown plane in flip command\n");
7904                 ret = -ENODEV;
7905                 goto err_unpin;
7906         }
7907
7908         len = 4;
7909         if (ring->id == RCS)
7910                 len += 6;
7911
7912         ret = intel_ring_begin(ring, len);
7913         if (ret)
7914                 goto err_unpin;
7915
7916         /* Unmask the flip-done completion message. Note that the bspec says that
7917          * we should do this for both the BCS and RCS, and that we must not unmask
7918          * more than one flip event at any time (or ensure that one flip message
7919          * can be sent by waiting for flip-done prior to queueing new flips).
7920          * Experimentation says that BCS works despite DERRMR masking all
7921          * flip-done completion events and that unmasking all planes at once
7922          * for the RCS also doesn't appear to drop events. Setting the DERRMR
7923          * to zero does lead to lockups within MI_DISPLAY_FLIP.
7924          */
7925         if (ring->id == RCS) {
7926                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7927                 intel_ring_emit(ring, DERRMR);
7928                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7929                                         DERRMR_PIPEB_PRI_FLIP_DONE |
7930                                         DERRMR_PIPEC_PRI_FLIP_DONE));
7931                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7932                 intel_ring_emit(ring, DERRMR);
7933                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7934         }
7935
7936         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7937         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7938         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7939         intel_ring_emit(ring, (MI_NOOP));
7940
7941         intel_mark_page_flip_active(intel_crtc);
7942         intel_ring_advance(ring);
7943         return 0;
7944
7945 err_unpin:
7946         intel_unpin_fb_obj(obj);
7947 err:
7948         return ret;
7949 }
7950
7951 static int intel_default_queue_flip(struct drm_device *dev,
7952                                     struct drm_crtc *crtc,
7953                                     struct drm_framebuffer *fb,
7954                                     struct drm_i915_gem_object *obj,
7955                                     uint32_t flags)
7956 {
7957         return -ENODEV;
7958 }
7959
7960 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7961                                 struct drm_framebuffer *fb,
7962                                 struct drm_pending_vblank_event *event,
7963                                 uint32_t page_flip_flags)
7964 {
7965         struct drm_device *dev = crtc->dev;
7966         struct drm_i915_private *dev_priv = dev->dev_private;
7967         struct drm_framebuffer *old_fb = crtc->fb;
7968         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7970         struct intel_unpin_work *work;
7971         unsigned long flags;
7972         int ret;
7973
7974         /* Can't change pixel format via MI display flips. */
7975         if (fb->pixel_format != crtc->fb->pixel_format)
7976                 return -EINVAL;
7977
7978         /*
7979          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7980          * Note that pitch changes could also affect these register.
7981          */
7982         if (INTEL_INFO(dev)->gen > 3 &&
7983             (fb->offsets[0] != crtc->fb->offsets[0] ||
7984              fb->pitches[0] != crtc->fb->pitches[0]))
7985                 return -EINVAL;
7986
7987         work = kzalloc(sizeof *work, GFP_KERNEL);
7988         if (work == NULL)
7989                 return -ENOMEM;
7990
7991         work->event = event;
7992         work->crtc = crtc;
7993         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7994         INIT_WORK(&work->work, intel_unpin_work_fn);
7995
7996         ret = drm_vblank_get(dev, intel_crtc->pipe);
7997         if (ret)
7998                 goto free_work;
7999
8000         /* We borrow the event spin lock for protecting unpin_work */
8001         spin_lock_irqsave(&dev->event_lock, flags);
8002         if (intel_crtc->unpin_work) {
8003                 spin_unlock_irqrestore(&dev->event_lock, flags);
8004                 kfree(work);
8005                 drm_vblank_put(dev, intel_crtc->pipe);
8006
8007                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8008                 return -EBUSY;
8009         }
8010         intel_crtc->unpin_work = work;
8011         spin_unlock_irqrestore(&dev->event_lock, flags);
8012
8013         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8014                 flush_workqueue(dev_priv->wq);
8015
8016         ret = i915_mutex_lock_interruptible(dev);
8017         if (ret)
8018                 goto cleanup;
8019
8020         /* Reference the objects for the scheduled work. */
8021         drm_gem_object_reference(&work->old_fb_obj->base);
8022         drm_gem_object_reference(&obj->base);
8023
8024         crtc->fb = fb;
8025
8026         work->pending_flip_obj = obj;
8027
8028         work->enable_stall_check = true;
8029
8030         atomic_inc(&intel_crtc->unpin_work_count);
8031         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8032
8033         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8034         if (ret)
8035                 goto cleanup_pending;
8036
8037         intel_disable_fbc(dev);
8038         intel_mark_fb_busy(obj, NULL);
8039         mutex_unlock(&dev->struct_mutex);
8040
8041         trace_i915_flip_request(intel_crtc->plane, obj);
8042
8043         return 0;
8044
8045 cleanup_pending:
8046         atomic_dec(&intel_crtc->unpin_work_count);
8047         crtc->fb = old_fb;
8048         drm_gem_object_unreference(&work->old_fb_obj->base);
8049         drm_gem_object_unreference(&obj->base);
8050         mutex_unlock(&dev->struct_mutex);
8051
8052 cleanup:
8053         spin_lock_irqsave(&dev->event_lock, flags);
8054         intel_crtc->unpin_work = NULL;
8055         spin_unlock_irqrestore(&dev->event_lock, flags);
8056
8057         drm_vblank_put(dev, intel_crtc->pipe);
8058 free_work:
8059         kfree(work);
8060
8061         return ret;
8062 }
8063
8064 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8065         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8066         .load_lut = intel_crtc_load_lut,
8067 };
8068
8069 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8070                                   struct drm_crtc *crtc)
8071 {
8072         struct drm_device *dev;
8073         struct drm_crtc *tmp;
8074         int crtc_mask = 1;
8075
8076         WARN(!crtc, "checking null crtc?\n");
8077
8078         dev = crtc->dev;
8079
8080         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8081                 if (tmp == crtc)
8082                         break;
8083                 crtc_mask <<= 1;
8084         }
8085
8086         if (encoder->possible_crtcs & crtc_mask)
8087                 return true;
8088         return false;
8089 }
8090
8091 /**
8092  * intel_modeset_update_staged_output_state
8093  *
8094  * Updates the staged output configuration state, e.g. after we've read out the
8095  * current hw state.
8096  */
8097 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8098 {
8099         struct intel_encoder *encoder;
8100         struct intel_connector *connector;
8101
8102         list_for_each_entry(connector, &dev->mode_config.connector_list,
8103                             base.head) {
8104                 connector->new_encoder =
8105                         to_intel_encoder(connector->base.encoder);
8106         }
8107
8108         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8109                             base.head) {
8110                 encoder->new_crtc =
8111                         to_intel_crtc(encoder->base.crtc);
8112         }
8113 }
8114
8115 /**
8116  * intel_modeset_commit_output_state
8117  *
8118  * This function copies the stage display pipe configuration to the real one.
8119  */
8120 static void intel_modeset_commit_output_state(struct drm_device *dev)
8121 {
8122         struct intel_encoder *encoder;
8123         struct intel_connector *connector;
8124
8125         list_for_each_entry(connector, &dev->mode_config.connector_list,
8126                             base.head) {
8127                 connector->base.encoder = &connector->new_encoder->base;
8128         }
8129
8130         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8131                             base.head) {
8132                 encoder->base.crtc = &encoder->new_crtc->base;
8133         }
8134 }
8135
8136 static void
8137 connected_sink_compute_bpp(struct intel_connector * connector,
8138                            struct intel_crtc_config *pipe_config)
8139 {
8140         int bpp = pipe_config->pipe_bpp;
8141
8142         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8143                 connector->base.base.id,
8144                 drm_get_connector_name(&connector->base));
8145
8146         /* Don't use an invalid EDID bpc value */
8147         if (connector->base.display_info.bpc &&
8148             connector->base.display_info.bpc * 3 < bpp) {
8149                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8150                               bpp, connector->base.display_info.bpc*3);
8151                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8152         }
8153
8154         /* Clamp bpp to 8 on screens without EDID 1.4 */
8155         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8156                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8157                               bpp);
8158                 pipe_config->pipe_bpp = 24;
8159         }
8160 }
8161
8162 static int
8163 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8164                           struct drm_framebuffer *fb,
8165                           struct intel_crtc_config *pipe_config)
8166 {
8167         struct drm_device *dev = crtc->base.dev;
8168         struct intel_connector *connector;
8169         int bpp;
8170
8171         switch (fb->pixel_format) {
8172         case DRM_FORMAT_C8:
8173                 bpp = 8*3; /* since we go through a colormap */
8174                 break;
8175         case DRM_FORMAT_XRGB1555:
8176         case DRM_FORMAT_ARGB1555:
8177                 /* checked in intel_framebuffer_init already */
8178                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8179                         return -EINVAL;
8180         case DRM_FORMAT_RGB565:
8181                 bpp = 6*3; /* min is 18bpp */
8182                 break;
8183         case DRM_FORMAT_XBGR8888:
8184         case DRM_FORMAT_ABGR8888:
8185                 /* checked in intel_framebuffer_init already */
8186                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8187                         return -EINVAL;
8188         case DRM_FORMAT_XRGB8888:
8189         case DRM_FORMAT_ARGB8888:
8190                 bpp = 8*3;
8191                 break;
8192         case DRM_FORMAT_XRGB2101010:
8193         case DRM_FORMAT_ARGB2101010:
8194         case DRM_FORMAT_XBGR2101010:
8195         case DRM_FORMAT_ABGR2101010:
8196                 /* checked in intel_framebuffer_init already */
8197                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8198                         return -EINVAL;
8199                 bpp = 10*3;
8200                 break;
8201         /* TODO: gen4+ supports 16 bpc floating point, too. */
8202         default:
8203                 DRM_DEBUG_KMS("unsupported depth\n");
8204                 return -EINVAL;
8205         }
8206
8207         pipe_config->pipe_bpp = bpp;
8208
8209         /* Clamp display bpp to EDID value */
8210         list_for_each_entry(connector, &dev->mode_config.connector_list,
8211                             base.head) {
8212                 if (!connector->new_encoder ||
8213                     connector->new_encoder->new_crtc != crtc)
8214                         continue;
8215
8216                 connected_sink_compute_bpp(connector, pipe_config);
8217         }
8218
8219         return bpp;
8220 }
8221
8222 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8223                                    struct intel_crtc_config *pipe_config,
8224                                    const char *context)
8225 {
8226         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8227                       context, pipe_name(crtc->pipe));
8228
8229         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8230         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8231                       pipe_config->pipe_bpp, pipe_config->dither);
8232         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8233                       pipe_config->has_pch_encoder,
8234                       pipe_config->fdi_lanes,
8235                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8236                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8237                       pipe_config->fdi_m_n.tu);
8238         DRM_DEBUG_KMS("requested mode:\n");
8239         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8240         DRM_DEBUG_KMS("adjusted mode:\n");
8241         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8242         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8243                       pipe_config->gmch_pfit.control,
8244                       pipe_config->gmch_pfit.pgm_ratios,
8245                       pipe_config->gmch_pfit.lvds_border_bits);
8246         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8247                       pipe_config->pch_pfit.pos,
8248                       pipe_config->pch_pfit.size);
8249         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8250 }
8251
8252 static bool check_encoder_cloning(struct drm_crtc *crtc)
8253 {
8254         int num_encoders = 0;
8255         bool uncloneable_encoders = false;
8256         struct intel_encoder *encoder;
8257
8258         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8259                             base.head) {
8260                 if (&encoder->new_crtc->base != crtc)
8261                         continue;
8262
8263                 num_encoders++;
8264                 if (!encoder->cloneable)
8265                         uncloneable_encoders = true;
8266         }
8267
8268         return !(num_encoders > 1 && uncloneable_encoders);
8269 }
8270
8271 static struct intel_crtc_config *
8272 intel_modeset_pipe_config(struct drm_crtc *crtc,
8273                           struct drm_framebuffer *fb,
8274                           struct drm_display_mode *mode)
8275 {
8276         struct drm_device *dev = crtc->dev;
8277         struct intel_encoder *encoder;
8278         struct intel_crtc_config *pipe_config;
8279         int plane_bpp, ret = -EINVAL;
8280         bool retry = true;
8281
8282         if (!check_encoder_cloning(crtc)) {
8283                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8284                 return ERR_PTR(-EINVAL);
8285         }
8286
8287         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8288         if (!pipe_config)
8289                 return ERR_PTR(-ENOMEM);
8290
8291         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8292         drm_mode_copy(&pipe_config->requested_mode, mode);
8293         pipe_config->cpu_transcoder =
8294                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8295         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8296
8297         /*
8298          * Sanitize sync polarity flags based on requested ones. If neither
8299          * positive or negative polarity is requested, treat this as meaning
8300          * negative polarity.
8301          */
8302         if (!(pipe_config->adjusted_mode.flags &
8303               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8304                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8305
8306         if (!(pipe_config->adjusted_mode.flags &
8307               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8308                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8309
8310         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8311          * plane pixel format and any sink constraints into account. Returns the
8312          * source plane bpp so that dithering can be selected on mismatches
8313          * after encoders and crtc also have had their say. */
8314         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8315                                               fb, pipe_config);
8316         if (plane_bpp < 0)
8317                 goto fail;
8318
8319 encoder_retry:
8320         /* Ensure the port clock defaults are reset when retrying. */
8321         pipe_config->port_clock = 0;
8322         pipe_config->pixel_multiplier = 1;
8323
8324         /* Fill in default crtc timings, allow encoders to overwrite them. */
8325         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8326
8327         /* Pass our mode to the connectors and the CRTC to give them a chance to
8328          * adjust it according to limitations or connector properties, and also
8329          * a chance to reject the mode entirely.
8330          */
8331         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8332                             base.head) {
8333
8334                 if (&encoder->new_crtc->base != crtc)
8335                         continue;
8336
8337                 if (!(encoder->compute_config(encoder, pipe_config))) {
8338                         DRM_DEBUG_KMS("Encoder config failure\n");
8339                         goto fail;
8340                 }
8341         }
8342
8343         /* Set default port clock if not overwritten by the encoder. Needs to be
8344          * done afterwards in case the encoder adjusts the mode. */
8345         if (!pipe_config->port_clock)
8346                 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8347
8348         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8349         if (ret < 0) {
8350                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8351                 goto fail;
8352         }
8353
8354         if (ret == RETRY) {
8355                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8356                         ret = -EINVAL;
8357                         goto fail;
8358                 }
8359
8360                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8361                 retry = false;
8362                 goto encoder_retry;
8363         }
8364
8365         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8366         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8367                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8368
8369         return pipe_config;
8370 fail:
8371         kfree(pipe_config);
8372         return ERR_PTR(ret);
8373 }
8374
8375 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8376  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8377 static void
8378 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8379                              unsigned *prepare_pipes, unsigned *disable_pipes)
8380 {
8381         struct intel_crtc *intel_crtc;
8382         struct drm_device *dev = crtc->dev;
8383         struct intel_encoder *encoder;
8384         struct intel_connector *connector;
8385         struct drm_crtc *tmp_crtc;
8386
8387         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8388
8389         /* Check which crtcs have changed outputs connected to them, these need
8390          * to be part of the prepare_pipes mask. We don't (yet) support global
8391          * modeset across multiple crtcs, so modeset_pipes will only have one
8392          * bit set at most. */
8393         list_for_each_entry(connector, &dev->mode_config.connector_list,
8394                             base.head) {
8395                 if (connector->base.encoder == &connector->new_encoder->base)
8396                         continue;
8397
8398                 if (connector->base.encoder) {
8399                         tmp_crtc = connector->base.encoder->crtc;
8400
8401                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8402                 }
8403
8404                 if (connector->new_encoder)
8405                         *prepare_pipes |=
8406                                 1 << connector->new_encoder->new_crtc->pipe;
8407         }
8408
8409         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8410                             base.head) {
8411                 if (encoder->base.crtc == &encoder->new_crtc->base)
8412                         continue;
8413
8414                 if (encoder->base.crtc) {
8415                         tmp_crtc = encoder->base.crtc;
8416
8417                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8418                 }
8419
8420                 if (encoder->new_crtc)
8421                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8422         }
8423
8424         /* Check for any pipes that will be fully disabled ... */
8425         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8426                             base.head) {
8427                 bool used = false;
8428
8429                 /* Don't try to disable disabled crtcs. */
8430                 if (!intel_crtc->base.enabled)
8431                         continue;
8432
8433                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8434                                     base.head) {
8435                         if (encoder->new_crtc == intel_crtc)
8436                                 used = true;
8437                 }
8438
8439                 if (!used)
8440                         *disable_pipes |= 1 << intel_crtc->pipe;
8441         }
8442
8443
8444         /* set_mode is also used to update properties on life display pipes. */
8445         intel_crtc = to_intel_crtc(crtc);
8446         if (crtc->enabled)
8447                 *prepare_pipes |= 1 << intel_crtc->pipe;
8448
8449         /*
8450          * For simplicity do a full modeset on any pipe where the output routing
8451          * changed. We could be more clever, but that would require us to be
8452          * more careful with calling the relevant encoder->mode_set functions.
8453          */
8454         if (*prepare_pipes)
8455                 *modeset_pipes = *prepare_pipes;
8456
8457         /* ... and mask these out. */
8458         *modeset_pipes &= ~(*disable_pipes);
8459         *prepare_pipes &= ~(*disable_pipes);
8460
8461         /*
8462          * HACK: We don't (yet) fully support global modesets. intel_set_config
8463          * obies this rule, but the modeset restore mode of
8464          * intel_modeset_setup_hw_state does not.
8465          */
8466         *modeset_pipes &= 1 << intel_crtc->pipe;
8467         *prepare_pipes &= 1 << intel_crtc->pipe;
8468
8469         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8470                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8471 }
8472
8473 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8474 {
8475         struct drm_encoder *encoder;
8476         struct drm_device *dev = crtc->dev;
8477
8478         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8479                 if (encoder->crtc == crtc)
8480                         return true;
8481
8482         return false;
8483 }
8484
8485 static void
8486 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8487 {
8488         struct intel_encoder *intel_encoder;
8489         struct intel_crtc *intel_crtc;
8490         struct drm_connector *connector;
8491
8492         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8493                             base.head) {
8494                 if (!intel_encoder->base.crtc)
8495                         continue;
8496
8497                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8498
8499                 if (prepare_pipes & (1 << intel_crtc->pipe))
8500                         intel_encoder->connectors_active = false;
8501         }
8502
8503         intel_modeset_commit_output_state(dev);
8504
8505         /* Update computed state. */
8506         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8507                             base.head) {
8508                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8509         }
8510
8511         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8512                 if (!connector->encoder || !connector->encoder->crtc)
8513                         continue;
8514
8515                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8516
8517                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8518                         struct drm_property *dpms_property =
8519                                 dev->mode_config.dpms_property;
8520
8521                         connector->dpms = DRM_MODE_DPMS_ON;
8522                         drm_object_property_set_value(&connector->base,
8523                                                          dpms_property,
8524                                                          DRM_MODE_DPMS_ON);
8525
8526                         intel_encoder = to_intel_encoder(connector->encoder);
8527                         intel_encoder->connectors_active = true;
8528                 }
8529         }
8530
8531 }
8532
8533 static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8534                                     struct intel_crtc_config *new)
8535 {
8536         int clock1, clock2, diff;
8537
8538         clock1 = cur->adjusted_mode.clock;
8539         clock2 = new->adjusted_mode.clock;
8540
8541         if (clock1 == clock2)
8542                 return true;
8543
8544         if (!clock1 || !clock2)
8545                 return false;
8546
8547         diff = abs(clock1 - clock2);
8548
8549         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8550                 return true;
8551
8552         return false;
8553 }
8554
8555 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8556         list_for_each_entry((intel_crtc), \
8557                             &(dev)->mode_config.crtc_list, \
8558                             base.head) \
8559                 if (mask & (1 <<(intel_crtc)->pipe))
8560
8561 static bool
8562 intel_pipe_config_compare(struct drm_device *dev,
8563                           struct intel_crtc_config *current_config,
8564                           struct intel_crtc_config *pipe_config)
8565 {
8566 #define PIPE_CONF_CHECK_X(name) \
8567         if (current_config->name != pipe_config->name) { \
8568                 DRM_ERROR("mismatch in " #name " " \
8569                           "(expected 0x%08x, found 0x%08x)\n", \
8570                           current_config->name, \
8571                           pipe_config->name); \
8572                 return false; \
8573         }
8574
8575 #define PIPE_CONF_CHECK_I(name) \
8576         if (current_config->name != pipe_config->name) { \
8577                 DRM_ERROR("mismatch in " #name " " \
8578                           "(expected %i, found %i)\n", \
8579                           current_config->name, \
8580                           pipe_config->name); \
8581                 return false; \
8582         }
8583
8584 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8585         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8586                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8587                           "(expected %i, found %i)\n", \
8588                           current_config->name & (mask), \
8589                           pipe_config->name & (mask)); \
8590                 return false; \
8591         }
8592
8593 #define PIPE_CONF_QUIRK(quirk)  \
8594         ((current_config->quirks | pipe_config->quirks) & (quirk))
8595
8596         PIPE_CONF_CHECK_I(cpu_transcoder);
8597
8598         PIPE_CONF_CHECK_I(has_pch_encoder);
8599         PIPE_CONF_CHECK_I(fdi_lanes);
8600         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8601         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8602         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8603         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8604         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8605
8606         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8607         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8608         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8609         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8610         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8611         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8612
8613         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8614         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8615         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8616         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8617         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8618         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8619
8620         PIPE_CONF_CHECK_I(pixel_multiplier);
8621
8622         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8623                               DRM_MODE_FLAG_INTERLACE);
8624
8625         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8626                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8627                                       DRM_MODE_FLAG_PHSYNC);
8628                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8629                                       DRM_MODE_FLAG_NHSYNC);
8630                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8631                                       DRM_MODE_FLAG_PVSYNC);
8632                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8633                                       DRM_MODE_FLAG_NVSYNC);
8634         }
8635
8636         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8637         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8638
8639         PIPE_CONF_CHECK_I(gmch_pfit.control);
8640         /* pfit ratios are autocomputed by the hw on gen4+ */
8641         if (INTEL_INFO(dev)->gen < 4)
8642                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8643         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8644         PIPE_CONF_CHECK_I(pch_pfit.pos);
8645         PIPE_CONF_CHECK_I(pch_pfit.size);
8646
8647         PIPE_CONF_CHECK_I(ips_enabled);
8648
8649         PIPE_CONF_CHECK_I(shared_dpll);
8650         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8651         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
8652         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8653         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8654
8655 #undef PIPE_CONF_CHECK_X
8656 #undef PIPE_CONF_CHECK_I
8657 #undef PIPE_CONF_CHECK_FLAGS
8658 #undef PIPE_CONF_QUIRK
8659
8660         if (!IS_HASWELL(dev)) {
8661                 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8662                         DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
8663                                   current_config->adjusted_mode.clock,
8664                                   pipe_config->adjusted_mode.clock);
8665                         return false;
8666                 }
8667         }
8668
8669         return true;
8670 }
8671
8672 static void
8673 check_connector_state(struct drm_device *dev)
8674 {
8675         struct intel_connector *connector;
8676
8677         list_for_each_entry(connector, &dev->mode_config.connector_list,
8678                             base.head) {
8679                 /* This also checks the encoder/connector hw state with the
8680                  * ->get_hw_state callbacks. */
8681                 intel_connector_check_state(connector);
8682
8683                 WARN(&connector->new_encoder->base != connector->base.encoder,
8684                      "connector's staged encoder doesn't match current encoder\n");
8685         }
8686 }
8687
8688 static void
8689 check_encoder_state(struct drm_device *dev)
8690 {
8691         struct intel_encoder *encoder;
8692         struct intel_connector *connector;
8693
8694         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8695                             base.head) {
8696                 bool enabled = false;
8697                 bool active = false;
8698                 enum pipe pipe, tracked_pipe;
8699
8700                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8701                               encoder->base.base.id,
8702                               drm_get_encoder_name(&encoder->base));
8703
8704                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8705                      "encoder's stage crtc doesn't match current crtc\n");
8706                 WARN(encoder->connectors_active && !encoder->base.crtc,
8707                      "encoder's active_connectors set, but no crtc\n");
8708
8709                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8710                                     base.head) {
8711                         if (connector->base.encoder != &encoder->base)
8712                                 continue;
8713                         enabled = true;
8714                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8715                                 active = true;
8716                 }
8717                 WARN(!!encoder->base.crtc != enabled,
8718                      "encoder's enabled state mismatch "
8719                      "(expected %i, found %i)\n",
8720                      !!encoder->base.crtc, enabled);
8721                 WARN(active && !encoder->base.crtc,
8722                      "active encoder with no crtc\n");
8723
8724                 WARN(encoder->connectors_active != active,
8725                      "encoder's computed active state doesn't match tracked active state "
8726                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8727
8728                 active = encoder->get_hw_state(encoder, &pipe);
8729                 WARN(active != encoder->connectors_active,
8730                      "encoder's hw state doesn't match sw tracking "
8731                      "(expected %i, found %i)\n",
8732                      encoder->connectors_active, active);
8733
8734                 if (!encoder->base.crtc)
8735                         continue;
8736
8737                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8738                 WARN(active && pipe != tracked_pipe,
8739                      "active encoder's pipe doesn't match"
8740                      "(expected %i, found %i)\n",
8741                      tracked_pipe, pipe);
8742
8743         }
8744 }
8745
8746 static void
8747 check_crtc_state(struct drm_device *dev)
8748 {
8749         drm_i915_private_t *dev_priv = dev->dev_private;
8750         struct intel_crtc *crtc;
8751         struct intel_encoder *encoder;
8752         struct intel_crtc_config pipe_config;
8753
8754         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8755                             base.head) {
8756                 bool enabled = false;
8757                 bool active = false;
8758
8759                 memset(&pipe_config, 0, sizeof(pipe_config));
8760
8761                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8762                               crtc->base.base.id);
8763
8764                 WARN(crtc->active && !crtc->base.enabled,
8765                      "active crtc, but not enabled in sw tracking\n");
8766
8767                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8768                                     base.head) {
8769                         if (encoder->base.crtc != &crtc->base)
8770                                 continue;
8771                         enabled = true;
8772                         if (encoder->connectors_active)
8773                                 active = true;
8774                 }
8775
8776                 WARN(active != crtc->active,
8777                      "crtc's computed active state doesn't match tracked active state "
8778                      "(expected %i, found %i)\n", active, crtc->active);
8779                 WARN(enabled != crtc->base.enabled,
8780                      "crtc's computed enabled state doesn't match tracked enabled state "
8781                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8782
8783                 active = dev_priv->display.get_pipe_config(crtc,
8784                                                            &pipe_config);
8785
8786                 /* hw state is inconsistent with the pipe A quirk */
8787                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8788                         active = crtc->active;
8789
8790                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8791                                     base.head) {
8792                         enum pipe pipe;
8793                         if (encoder->base.crtc != &crtc->base)
8794                                 continue;
8795                         if (encoder->get_config &&
8796                             encoder->get_hw_state(encoder, &pipe))
8797                                 encoder->get_config(encoder, &pipe_config);
8798                 }
8799
8800                 if (dev_priv->display.get_clock)
8801                         dev_priv->display.get_clock(crtc, &pipe_config);
8802
8803                 WARN(crtc->active != active,
8804                      "crtc active state doesn't match with hw state "
8805                      "(expected %i, found %i)\n", crtc->active, active);
8806
8807                 if (active &&
8808                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8809                         WARN(1, "pipe state doesn't match!\n");
8810                         intel_dump_pipe_config(crtc, &pipe_config,
8811                                                "[hw state]");
8812                         intel_dump_pipe_config(crtc, &crtc->config,
8813                                                "[sw state]");
8814                 }
8815         }
8816 }
8817
8818 static void
8819 check_shared_dpll_state(struct drm_device *dev)
8820 {
8821         drm_i915_private_t *dev_priv = dev->dev_private;
8822         struct intel_crtc *crtc;
8823         struct intel_dpll_hw_state dpll_hw_state;
8824         int i;
8825
8826         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8827                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8828                 int enabled_crtcs = 0, active_crtcs = 0;
8829                 bool active;
8830
8831                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8832
8833                 DRM_DEBUG_KMS("%s\n", pll->name);
8834
8835                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8836
8837                 WARN(pll->active > pll->refcount,
8838                      "more active pll users than references: %i vs %i\n",
8839                      pll->active, pll->refcount);
8840                 WARN(pll->active && !pll->on,
8841                      "pll in active use but not on in sw tracking\n");
8842                 WARN(pll->on && !pll->active,
8843                      "pll in on but not on in use in sw tracking\n");
8844                 WARN(pll->on != active,
8845                      "pll on state mismatch (expected %i, found %i)\n",
8846                      pll->on, active);
8847
8848                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8849                                     base.head) {
8850                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8851                                 enabled_crtcs++;
8852                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8853                                 active_crtcs++;
8854                 }
8855                 WARN(pll->active != active_crtcs,
8856                      "pll active crtcs mismatch (expected %i, found %i)\n",
8857                      pll->active, active_crtcs);
8858                 WARN(pll->refcount != enabled_crtcs,
8859                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
8860                      pll->refcount, enabled_crtcs);
8861
8862                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8863                                        sizeof(dpll_hw_state)),
8864                      "pll hw state mismatch\n");
8865         }
8866 }
8867
8868 void
8869 intel_modeset_check_state(struct drm_device *dev)
8870 {
8871         check_connector_state(dev);
8872         check_encoder_state(dev);
8873         check_crtc_state(dev);
8874         check_shared_dpll_state(dev);
8875 }
8876
8877 static int __intel_set_mode(struct drm_crtc *crtc,
8878                             struct drm_display_mode *mode,
8879                             int x, int y, struct drm_framebuffer *fb)
8880 {
8881         struct drm_device *dev = crtc->dev;
8882         drm_i915_private_t *dev_priv = dev->dev_private;
8883         struct drm_display_mode *saved_mode, *saved_hwmode;
8884         struct intel_crtc_config *pipe_config = NULL;
8885         struct intel_crtc *intel_crtc;
8886         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8887         int ret = 0;
8888
8889         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8890         if (!saved_mode)
8891                 return -ENOMEM;
8892         saved_hwmode = saved_mode + 1;
8893
8894         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8895                                      &prepare_pipes, &disable_pipes);
8896
8897         *saved_hwmode = crtc->hwmode;
8898         *saved_mode = crtc->mode;
8899
8900         /* Hack: Because we don't (yet) support global modeset on multiple
8901          * crtcs, we don't keep track of the new mode for more than one crtc.
8902          * Hence simply check whether any bit is set in modeset_pipes in all the
8903          * pieces of code that are not yet converted to deal with mutliple crtcs
8904          * changing their mode at the same time. */
8905         if (modeset_pipes) {
8906                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8907                 if (IS_ERR(pipe_config)) {
8908                         ret = PTR_ERR(pipe_config);
8909                         pipe_config = NULL;
8910
8911                         goto out;
8912                 }
8913                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8914                                        "[modeset]");
8915         }
8916
8917         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8918                 intel_crtc_disable(&intel_crtc->base);
8919
8920         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8921                 if (intel_crtc->base.enabled)
8922                         dev_priv->display.crtc_disable(&intel_crtc->base);
8923         }
8924
8925         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8926          * to set it here already despite that we pass it down the callchain.
8927          */
8928         if (modeset_pipes) {
8929                 crtc->mode = *mode;
8930                 /* mode_set/enable/disable functions rely on a correct pipe
8931                  * config. */
8932                 to_intel_crtc(crtc)->config = *pipe_config;
8933         }
8934
8935         /* Only after disabling all output pipelines that will be changed can we
8936          * update the the output configuration. */
8937         intel_modeset_update_state(dev, prepare_pipes);
8938
8939         if (dev_priv->display.modeset_global_resources)
8940                 dev_priv->display.modeset_global_resources(dev);
8941
8942         /* Set up the DPLL and any encoders state that needs to adjust or depend
8943          * on the DPLL.
8944          */
8945         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8946                 ret = intel_crtc_mode_set(&intel_crtc->base,
8947                                           x, y, fb);
8948                 if (ret)
8949                         goto done;
8950         }
8951
8952         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8953         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8954                 dev_priv->display.crtc_enable(&intel_crtc->base);
8955
8956         if (modeset_pipes) {
8957                 /* Store real post-adjustment hardware mode. */
8958                 crtc->hwmode = pipe_config->adjusted_mode;
8959
8960                 /* Calculate and store various constants which
8961                  * are later needed by vblank and swap-completion
8962                  * timestamping. They are derived from true hwmode.
8963                  */
8964                 drm_calc_timestamping_constants(crtc);
8965         }
8966
8967         /* FIXME: add subpixel order */
8968 done:
8969         if (ret && crtc->enabled) {
8970                 crtc->hwmode = *saved_hwmode;
8971                 crtc->mode = *saved_mode;
8972         }
8973
8974 out:
8975         kfree(pipe_config);
8976         kfree(saved_mode);
8977         return ret;
8978 }
8979
8980 static int intel_set_mode(struct drm_crtc *crtc,
8981                           struct drm_display_mode *mode,
8982                           int x, int y, struct drm_framebuffer *fb)
8983 {
8984         int ret;
8985
8986         ret = __intel_set_mode(crtc, mode, x, y, fb);
8987
8988         if (ret == 0)
8989                 intel_modeset_check_state(crtc->dev);
8990
8991         return ret;
8992 }
8993
8994 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8995 {
8996         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8997 }
8998
8999 #undef for_each_intel_crtc_masked
9000
9001 static void intel_set_config_free(struct intel_set_config *config)
9002 {
9003         if (!config)
9004                 return;
9005
9006         kfree(config->save_connector_encoders);
9007         kfree(config->save_encoder_crtcs);
9008         kfree(config);
9009 }
9010
9011 static int intel_set_config_save_state(struct drm_device *dev,
9012                                        struct intel_set_config *config)
9013 {
9014         struct drm_encoder *encoder;
9015         struct drm_connector *connector;
9016         int count;
9017
9018         config->save_encoder_crtcs =
9019                 kcalloc(dev->mode_config.num_encoder,
9020                         sizeof(struct drm_crtc *), GFP_KERNEL);
9021         if (!config->save_encoder_crtcs)
9022                 return -ENOMEM;
9023
9024         config->save_connector_encoders =
9025                 kcalloc(dev->mode_config.num_connector,
9026                         sizeof(struct drm_encoder *), GFP_KERNEL);
9027         if (!config->save_connector_encoders)
9028                 return -ENOMEM;
9029
9030         /* Copy data. Note that driver private data is not affected.
9031          * Should anything bad happen only the expected state is
9032          * restored, not the drivers personal bookkeeping.
9033          */
9034         count = 0;
9035         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9036                 config->save_encoder_crtcs[count++] = encoder->crtc;
9037         }
9038
9039         count = 0;
9040         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9041                 config->save_connector_encoders[count++] = connector->encoder;
9042         }
9043
9044         return 0;
9045 }
9046
9047 static void intel_set_config_restore_state(struct drm_device *dev,
9048                                            struct intel_set_config *config)
9049 {
9050         struct intel_encoder *encoder;
9051         struct intel_connector *connector;
9052         int count;
9053
9054         count = 0;
9055         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9056                 encoder->new_crtc =
9057                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9058         }
9059
9060         count = 0;
9061         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9062                 connector->new_encoder =
9063                         to_intel_encoder(config->save_connector_encoders[count++]);
9064         }
9065 }
9066
9067 static bool
9068 is_crtc_connector_off(struct drm_mode_set *set)
9069 {
9070         int i;
9071
9072         if (set->num_connectors == 0)
9073                 return false;
9074
9075         if (WARN_ON(set->connectors == NULL))
9076                 return false;
9077
9078         for (i = 0; i < set->num_connectors; i++)
9079                 if (set->connectors[i]->encoder &&
9080                     set->connectors[i]->encoder->crtc == set->crtc &&
9081                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9082                         return true;
9083
9084         return false;
9085 }
9086
9087 static void
9088 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9089                                       struct intel_set_config *config)
9090 {
9091
9092         /* We should be able to check here if the fb has the same properties
9093          * and then just flip_or_move it */
9094         if (is_crtc_connector_off(set)) {
9095                 config->mode_changed = true;
9096         } else if (set->crtc->fb != set->fb) {
9097                 /* If we have no fb then treat it as a full mode set */
9098                 if (set->crtc->fb == NULL) {
9099                         struct intel_crtc *intel_crtc =
9100                                 to_intel_crtc(set->crtc);
9101
9102                         if (intel_crtc->active && i915_fastboot) {
9103                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9104                                 config->fb_changed = true;
9105                         } else {
9106                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9107                                 config->mode_changed = true;
9108                         }
9109                 } else if (set->fb == NULL) {
9110                         config->mode_changed = true;
9111                 } else if (set->fb->pixel_format !=
9112                            set->crtc->fb->pixel_format) {
9113                         config->mode_changed = true;
9114                 } else {
9115                         config->fb_changed = true;
9116                 }
9117         }
9118
9119         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9120                 config->fb_changed = true;
9121
9122         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9123                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9124                 drm_mode_debug_printmodeline(&set->crtc->mode);
9125                 drm_mode_debug_printmodeline(set->mode);
9126                 config->mode_changed = true;
9127         }
9128
9129         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9130                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9131 }
9132
9133 static int
9134 intel_modeset_stage_output_state(struct drm_device *dev,
9135                                  struct drm_mode_set *set,
9136                                  struct intel_set_config *config)
9137 {
9138         struct drm_crtc *new_crtc;
9139         struct intel_connector *connector;
9140         struct intel_encoder *encoder;
9141         int ro;
9142
9143         /* The upper layers ensure that we either disable a crtc or have a list
9144          * of connectors. For paranoia, double-check this. */
9145         WARN_ON(!set->fb && (set->num_connectors != 0));
9146         WARN_ON(set->fb && (set->num_connectors == 0));
9147
9148         list_for_each_entry(connector, &dev->mode_config.connector_list,
9149                             base.head) {
9150                 /* Otherwise traverse passed in connector list and get encoders
9151                  * for them. */
9152                 for (ro = 0; ro < set->num_connectors; ro++) {
9153                         if (set->connectors[ro] == &connector->base) {
9154                                 connector->new_encoder = connector->encoder;
9155                                 break;
9156                         }
9157                 }
9158
9159                 /* If we disable the crtc, disable all its connectors. Also, if
9160                  * the connector is on the changing crtc but not on the new
9161                  * connector list, disable it. */
9162                 if ((!set->fb || ro == set->num_connectors) &&
9163                     connector->base.encoder &&
9164                     connector->base.encoder->crtc == set->crtc) {
9165                         connector->new_encoder = NULL;
9166
9167                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9168                                 connector->base.base.id,
9169                                 drm_get_connector_name(&connector->base));
9170                 }
9171
9172
9173                 if (&connector->new_encoder->base != connector->base.encoder) {
9174                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9175                         config->mode_changed = true;
9176                 }
9177         }
9178         /* connector->new_encoder is now updated for all connectors. */
9179
9180         /* Update crtc of enabled connectors. */
9181         list_for_each_entry(connector, &dev->mode_config.connector_list,
9182                             base.head) {
9183                 if (!connector->new_encoder)
9184                         continue;
9185
9186                 new_crtc = connector->new_encoder->base.crtc;
9187
9188                 for (ro = 0; ro < set->num_connectors; ro++) {
9189                         if (set->connectors[ro] == &connector->base)
9190                                 new_crtc = set->crtc;
9191                 }
9192
9193                 /* Make sure the new CRTC will work with the encoder */
9194                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9195                                            new_crtc)) {
9196                         return -EINVAL;
9197                 }
9198                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9199
9200                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9201                         connector->base.base.id,
9202                         drm_get_connector_name(&connector->base),
9203                         new_crtc->base.id);
9204         }
9205
9206         /* Check for any encoders that needs to be disabled. */
9207         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9208                             base.head) {
9209                 list_for_each_entry(connector,
9210                                     &dev->mode_config.connector_list,
9211                                     base.head) {
9212                         if (connector->new_encoder == encoder) {
9213                                 WARN_ON(!connector->new_encoder->new_crtc);
9214
9215                                 goto next_encoder;
9216                         }
9217                 }
9218                 encoder->new_crtc = NULL;
9219 next_encoder:
9220                 /* Only now check for crtc changes so we don't miss encoders
9221                  * that will be disabled. */
9222                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9223                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9224                         config->mode_changed = true;
9225                 }
9226         }
9227         /* Now we've also updated encoder->new_crtc for all encoders. */
9228
9229         return 0;
9230 }
9231
9232 static int intel_crtc_set_config(struct drm_mode_set *set)
9233 {
9234         struct drm_device *dev;
9235         struct drm_mode_set save_set;
9236         struct intel_set_config *config;
9237         int ret;
9238
9239         BUG_ON(!set);
9240         BUG_ON(!set->crtc);
9241         BUG_ON(!set->crtc->helper_private);
9242
9243         /* Enforce sane interface api - has been abused by the fb helper. */
9244         BUG_ON(!set->mode && set->fb);
9245         BUG_ON(set->fb && set->num_connectors == 0);
9246
9247         if (set->fb) {
9248                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9249                                 set->crtc->base.id, set->fb->base.id,
9250                                 (int)set->num_connectors, set->x, set->y);
9251         } else {
9252                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9253         }
9254
9255         dev = set->crtc->dev;
9256
9257         ret = -ENOMEM;
9258         config = kzalloc(sizeof(*config), GFP_KERNEL);
9259         if (!config)
9260                 goto out_config;
9261
9262         ret = intel_set_config_save_state(dev, config);
9263         if (ret)
9264                 goto out_config;
9265
9266         save_set.crtc = set->crtc;
9267         save_set.mode = &set->crtc->mode;
9268         save_set.x = set->crtc->x;
9269         save_set.y = set->crtc->y;
9270         save_set.fb = set->crtc->fb;
9271
9272         /* Compute whether we need a full modeset, only an fb base update or no
9273          * change at all. In the future we might also check whether only the
9274          * mode changed, e.g. for LVDS where we only change the panel fitter in
9275          * such cases. */
9276         intel_set_config_compute_mode_changes(set, config);
9277
9278         ret = intel_modeset_stage_output_state(dev, set, config);
9279         if (ret)
9280                 goto fail;
9281
9282         if (config->mode_changed) {
9283                 ret = intel_set_mode(set->crtc, set->mode,
9284                                      set->x, set->y, set->fb);
9285         } else if (config->fb_changed) {
9286                 intel_crtc_wait_for_pending_flips(set->crtc);
9287
9288                 ret = intel_pipe_set_base(set->crtc,
9289                                           set->x, set->y, set->fb);
9290         }
9291
9292         if (ret) {
9293                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9294                               set->crtc->base.id, ret);
9295 fail:
9296                 intel_set_config_restore_state(dev, config);
9297
9298                 /* Try to restore the config */
9299                 if (config->mode_changed &&
9300                     intel_set_mode(save_set.crtc, save_set.mode,
9301                                    save_set.x, save_set.y, save_set.fb))
9302                         DRM_ERROR("failed to restore config after modeset failure\n");
9303         }
9304
9305 out_config:
9306         intel_set_config_free(config);
9307         return ret;
9308 }
9309
9310 static const struct drm_crtc_funcs intel_crtc_funcs = {
9311         .cursor_set = intel_crtc_cursor_set,
9312         .cursor_move = intel_crtc_cursor_move,
9313         .gamma_set = intel_crtc_gamma_set,
9314         .set_config = intel_crtc_set_config,
9315         .destroy = intel_crtc_destroy,
9316         .page_flip = intel_crtc_page_flip,
9317 };
9318
9319 static void intel_cpu_pll_init(struct drm_device *dev)
9320 {
9321         if (HAS_DDI(dev))
9322                 intel_ddi_pll_init(dev);
9323 }
9324
9325 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9326                                       struct intel_shared_dpll *pll,
9327                                       struct intel_dpll_hw_state *hw_state)
9328 {
9329         uint32_t val;
9330
9331         val = I915_READ(PCH_DPLL(pll->id));
9332         hw_state->dpll = val;
9333         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9334         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9335
9336         return val & DPLL_VCO_ENABLE;
9337 }
9338
9339 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9340                                   struct intel_shared_dpll *pll)
9341 {
9342         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9343         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9344 }
9345
9346 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9347                                 struct intel_shared_dpll *pll)
9348 {
9349         /* PCH refclock must be enabled first */
9350         assert_pch_refclk_enabled(dev_priv);
9351
9352         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9353
9354         /* Wait for the clocks to stabilize. */
9355         POSTING_READ(PCH_DPLL(pll->id));
9356         udelay(150);
9357
9358         /* The pixel multiplier can only be updated once the
9359          * DPLL is enabled and the clocks are stable.
9360          *
9361          * So write it again.
9362          */
9363         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9364         POSTING_READ(PCH_DPLL(pll->id));
9365         udelay(200);
9366 }
9367
9368 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9369                                  struct intel_shared_dpll *pll)
9370 {
9371         struct drm_device *dev = dev_priv->dev;
9372         struct intel_crtc *crtc;
9373
9374         /* Make sure no transcoder isn't still depending on us. */
9375         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9376                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9377                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9378         }
9379
9380         I915_WRITE(PCH_DPLL(pll->id), 0);
9381         POSTING_READ(PCH_DPLL(pll->id));
9382         udelay(200);
9383 }
9384
9385 static char *ibx_pch_dpll_names[] = {
9386         "PCH DPLL A",
9387         "PCH DPLL B",
9388 };
9389
9390 static void ibx_pch_dpll_init(struct drm_device *dev)
9391 {
9392         struct drm_i915_private *dev_priv = dev->dev_private;
9393         int i;
9394
9395         dev_priv->num_shared_dpll = 2;
9396
9397         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9398                 dev_priv->shared_dplls[i].id = i;
9399                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9400                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9401                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9402                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9403                 dev_priv->shared_dplls[i].get_hw_state =
9404                         ibx_pch_dpll_get_hw_state;
9405         }
9406 }
9407
9408 static void intel_shared_dpll_init(struct drm_device *dev)
9409 {
9410         struct drm_i915_private *dev_priv = dev->dev_private;
9411
9412         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9413                 ibx_pch_dpll_init(dev);
9414         else
9415                 dev_priv->num_shared_dpll = 0;
9416
9417         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9418         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9419                       dev_priv->num_shared_dpll);
9420 }
9421
9422 static void intel_crtc_init(struct drm_device *dev, int pipe)
9423 {
9424         drm_i915_private_t *dev_priv = dev->dev_private;
9425         struct intel_crtc *intel_crtc;
9426         int i;
9427
9428         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9429         if (intel_crtc == NULL)
9430                 return;
9431
9432         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9433
9434         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9435         for (i = 0; i < 256; i++) {
9436                 intel_crtc->lut_r[i] = i;
9437                 intel_crtc->lut_g[i] = i;
9438                 intel_crtc->lut_b[i] = i;
9439         }
9440
9441         /* Swap pipes & planes for FBC on pre-965 */
9442         intel_crtc->pipe = pipe;
9443         intel_crtc->plane = pipe;
9444         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9445                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9446                 intel_crtc->plane = !pipe;
9447         }
9448
9449         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9450                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9451         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9452         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9453
9454         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9455 }
9456
9457 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9458                                 struct drm_file *file)
9459 {
9460         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9461         struct drm_mode_object *drmmode_obj;
9462         struct intel_crtc *crtc;
9463
9464         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9465                 return -ENODEV;
9466
9467         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9468                         DRM_MODE_OBJECT_CRTC);
9469
9470         if (!drmmode_obj) {
9471                 DRM_ERROR("no such CRTC id\n");
9472                 return -EINVAL;
9473         }
9474
9475         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9476         pipe_from_crtc_id->pipe = crtc->pipe;
9477
9478         return 0;
9479 }
9480
9481 static int intel_encoder_clones(struct intel_encoder *encoder)
9482 {
9483         struct drm_device *dev = encoder->base.dev;
9484         struct intel_encoder *source_encoder;
9485         int index_mask = 0;
9486         int entry = 0;
9487
9488         list_for_each_entry(source_encoder,
9489                             &dev->mode_config.encoder_list, base.head) {
9490
9491                 if (encoder == source_encoder)
9492                         index_mask |= (1 << entry);
9493
9494                 /* Intel hw has only one MUX where enocoders could be cloned. */
9495                 if (encoder->cloneable && source_encoder->cloneable)
9496                         index_mask |= (1 << entry);
9497
9498                 entry++;
9499         }
9500
9501         return index_mask;
9502 }
9503
9504 static bool has_edp_a(struct drm_device *dev)
9505 {
9506         struct drm_i915_private *dev_priv = dev->dev_private;
9507
9508         if (!IS_MOBILE(dev))
9509                 return false;
9510
9511         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9512                 return false;
9513
9514         if (IS_GEN5(dev) &&
9515             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9516                 return false;
9517
9518         return true;
9519 }
9520
9521 static void intel_setup_outputs(struct drm_device *dev)
9522 {
9523         struct drm_i915_private *dev_priv = dev->dev_private;
9524         struct intel_encoder *encoder;
9525         bool dpd_is_edp = false;
9526
9527         intel_lvds_init(dev);
9528
9529         if (!IS_ULT(dev))
9530                 intel_crt_init(dev);
9531
9532         if (HAS_DDI(dev)) {
9533                 int found;
9534
9535                 /* Haswell uses DDI functions to detect digital outputs */
9536                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9537                 /* DDI A only supports eDP */
9538                 if (found)
9539                         intel_ddi_init(dev, PORT_A);
9540
9541                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9542                  * register */
9543                 found = I915_READ(SFUSE_STRAP);
9544
9545                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9546                         intel_ddi_init(dev, PORT_B);
9547                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9548                         intel_ddi_init(dev, PORT_C);
9549                 if (found & SFUSE_STRAP_DDID_DETECTED)
9550                         intel_ddi_init(dev, PORT_D);
9551         } else if (HAS_PCH_SPLIT(dev)) {
9552                 int found;
9553                 dpd_is_edp = intel_dpd_is_edp(dev);
9554
9555                 if (has_edp_a(dev))
9556                         intel_dp_init(dev, DP_A, PORT_A);
9557
9558                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9559                         /* PCH SDVOB multiplex with HDMIB */
9560                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9561                         if (!found)
9562                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9563                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9564                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9565                 }
9566
9567                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9568                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9569
9570                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9571                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9572
9573                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9574                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9575
9576                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9577                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9578         } else if (IS_VALLEYVIEW(dev)) {
9579                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9580                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9581                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9582                                         PORT_C);
9583                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9584                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9585                                               PORT_C);
9586                 }
9587
9588                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9589                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9590                                         PORT_B);
9591                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9592                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9593                 }
9594         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9595                 bool found = false;
9596
9597                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9598                         DRM_DEBUG_KMS("probing SDVOB\n");
9599                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9600                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9601                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9602                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9603                         }
9604
9605                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
9606                                 intel_dp_init(dev, DP_B, PORT_B);
9607                 }
9608
9609                 /* Before G4X SDVOC doesn't have its own detect register */
9610
9611                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9612                         DRM_DEBUG_KMS("probing SDVOC\n");
9613                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9614                 }
9615
9616                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9617
9618                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9619                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9620                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9621                         }
9622                         if (SUPPORTS_INTEGRATED_DP(dev))
9623                                 intel_dp_init(dev, DP_C, PORT_C);
9624                 }
9625
9626                 if (SUPPORTS_INTEGRATED_DP(dev) &&
9627                     (I915_READ(DP_D) & DP_DETECTED))
9628                         intel_dp_init(dev, DP_D, PORT_D);
9629         } else if (IS_GEN2(dev))
9630                 intel_dvo_init(dev);
9631
9632         if (SUPPORTS_TV(dev))
9633                 intel_tv_init(dev);
9634
9635         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9636                 encoder->base.possible_crtcs = encoder->crtc_mask;
9637                 encoder->base.possible_clones =
9638                         intel_encoder_clones(encoder);
9639         }
9640
9641         intel_init_pch_refclk(dev);
9642
9643         drm_helper_move_panel_connectors_to_head(dev);
9644 }
9645
9646 void intel_framebuffer_fini(struct intel_framebuffer *fb)
9647 {
9648         drm_framebuffer_cleanup(&fb->base);
9649         drm_gem_object_unreference_unlocked(&fb->obj->base);
9650 }
9651
9652 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9653 {
9654         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9655
9656         intel_framebuffer_fini(intel_fb);
9657         kfree(intel_fb);
9658 }
9659
9660 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9661                                                 struct drm_file *file,
9662                                                 unsigned int *handle)
9663 {
9664         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9665         struct drm_i915_gem_object *obj = intel_fb->obj;
9666
9667         return drm_gem_handle_create(file, &obj->base, handle);
9668 }
9669
9670 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9671         .destroy = intel_user_framebuffer_destroy,
9672         .create_handle = intel_user_framebuffer_create_handle,
9673 };
9674
9675 int intel_framebuffer_init(struct drm_device *dev,
9676                            struct intel_framebuffer *intel_fb,
9677                            struct drm_mode_fb_cmd2 *mode_cmd,
9678                            struct drm_i915_gem_object *obj)
9679 {
9680         int pitch_limit;
9681         int ret;
9682
9683         if (obj->tiling_mode == I915_TILING_Y) {
9684                 DRM_DEBUG("hardware does not support tiling Y\n");
9685                 return -EINVAL;
9686         }
9687
9688         if (mode_cmd->pitches[0] & 63) {
9689                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9690                           mode_cmd->pitches[0]);
9691                 return -EINVAL;
9692         }
9693
9694         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9695                 pitch_limit = 32*1024;
9696         } else if (INTEL_INFO(dev)->gen >= 4) {
9697                 if (obj->tiling_mode)
9698                         pitch_limit = 16*1024;
9699                 else
9700                         pitch_limit = 32*1024;
9701         } else if (INTEL_INFO(dev)->gen >= 3) {
9702                 if (obj->tiling_mode)
9703                         pitch_limit = 8*1024;
9704                 else
9705                         pitch_limit = 16*1024;
9706         } else
9707                 /* XXX DSPC is limited to 4k tiled */
9708                 pitch_limit = 8*1024;
9709
9710         if (mode_cmd->pitches[0] > pitch_limit) {
9711                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9712                           obj->tiling_mode ? "tiled" : "linear",
9713                           mode_cmd->pitches[0], pitch_limit);
9714                 return -EINVAL;
9715         }
9716
9717         if (obj->tiling_mode != I915_TILING_NONE &&
9718             mode_cmd->pitches[0] != obj->stride) {
9719                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9720                           mode_cmd->pitches[0], obj->stride);
9721                 return -EINVAL;
9722         }
9723
9724         /* Reject formats not supported by any plane early. */
9725         switch (mode_cmd->pixel_format) {
9726         case DRM_FORMAT_C8:
9727         case DRM_FORMAT_RGB565:
9728         case DRM_FORMAT_XRGB8888:
9729         case DRM_FORMAT_ARGB8888:
9730                 break;
9731         case DRM_FORMAT_XRGB1555:
9732         case DRM_FORMAT_ARGB1555:
9733                 if (INTEL_INFO(dev)->gen > 3) {
9734                         DRM_DEBUG("unsupported pixel format: %s\n",
9735                                   drm_get_format_name(mode_cmd->pixel_format));
9736                         return -EINVAL;
9737                 }
9738                 break;
9739         case DRM_FORMAT_XBGR8888:
9740         case DRM_FORMAT_ABGR8888:
9741         case DRM_FORMAT_XRGB2101010:
9742         case DRM_FORMAT_ARGB2101010:
9743         case DRM_FORMAT_XBGR2101010:
9744         case DRM_FORMAT_ABGR2101010:
9745                 if (INTEL_INFO(dev)->gen < 4) {
9746                         DRM_DEBUG("unsupported pixel format: %s\n",
9747                                   drm_get_format_name(mode_cmd->pixel_format));
9748                         return -EINVAL;
9749                 }
9750                 break;
9751         case DRM_FORMAT_YUYV:
9752         case DRM_FORMAT_UYVY:
9753         case DRM_FORMAT_YVYU:
9754         case DRM_FORMAT_VYUY:
9755                 if (INTEL_INFO(dev)->gen < 5) {
9756                         DRM_DEBUG("unsupported pixel format: %s\n",
9757                                   drm_get_format_name(mode_cmd->pixel_format));
9758                         return -EINVAL;
9759                 }
9760                 break;
9761         default:
9762                 DRM_DEBUG("unsupported pixel format: %s\n",
9763                           drm_get_format_name(mode_cmd->pixel_format));
9764                 return -EINVAL;
9765         }
9766
9767         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9768         if (mode_cmd->offsets[0] != 0)
9769                 return -EINVAL;
9770
9771         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9772         intel_fb->obj = obj;
9773
9774         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9775         if (ret) {
9776                 DRM_ERROR("framebuffer init failed %d\n", ret);
9777                 return ret;
9778         }
9779
9780         return 0;
9781 }
9782
9783 static struct drm_framebuffer *
9784 intel_user_framebuffer_create(struct drm_device *dev,
9785                               struct drm_file *filp,
9786                               struct drm_mode_fb_cmd2 *mode_cmd)
9787 {
9788         struct drm_i915_gem_object *obj;
9789
9790         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9791                                                 mode_cmd->handles[0]));
9792         if (&obj->base == NULL)
9793                 return ERR_PTR(-ENOENT);
9794
9795         return intel_framebuffer_create(dev, mode_cmd, obj);
9796 }
9797
9798 static const struct drm_mode_config_funcs intel_mode_funcs = {
9799         .fb_create = intel_user_framebuffer_create,
9800         .output_poll_changed = intel_fb_output_poll_changed,
9801 };
9802
9803 /* Set up chip specific display functions */
9804 static void intel_init_display(struct drm_device *dev)
9805 {
9806         struct drm_i915_private *dev_priv = dev->dev_private;
9807
9808         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9809                 dev_priv->display.find_dpll = g4x_find_best_dpll;
9810         else if (IS_VALLEYVIEW(dev))
9811                 dev_priv->display.find_dpll = vlv_find_best_dpll;
9812         else if (IS_PINEVIEW(dev))
9813                 dev_priv->display.find_dpll = pnv_find_best_dpll;
9814         else
9815                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9816
9817         if (HAS_DDI(dev)) {
9818                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9819                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9820                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9821                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9822                 dev_priv->display.off = haswell_crtc_off;
9823                 dev_priv->display.update_plane = ironlake_update_plane;
9824         } else if (HAS_PCH_SPLIT(dev)) {
9825                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9826                 dev_priv->display.get_clock = ironlake_crtc_clock_get;
9827                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9828                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9829                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9830                 dev_priv->display.off = ironlake_crtc_off;
9831                 dev_priv->display.update_plane = ironlake_update_plane;
9832         } else if (IS_VALLEYVIEW(dev)) {
9833                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9834                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9835                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9836                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9837                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9838                 dev_priv->display.off = i9xx_crtc_off;
9839                 dev_priv->display.update_plane = i9xx_update_plane;
9840         } else {
9841                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9842                 dev_priv->display.get_clock = i9xx_crtc_clock_get;
9843                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9844                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9845                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9846                 dev_priv->display.off = i9xx_crtc_off;
9847                 dev_priv->display.update_plane = i9xx_update_plane;
9848         }
9849
9850         /* Returns the core display clock speed */
9851         if (IS_VALLEYVIEW(dev))
9852                 dev_priv->display.get_display_clock_speed =
9853                         valleyview_get_display_clock_speed;
9854         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9855                 dev_priv->display.get_display_clock_speed =
9856                         i945_get_display_clock_speed;
9857         else if (IS_I915G(dev))
9858                 dev_priv->display.get_display_clock_speed =
9859                         i915_get_display_clock_speed;
9860         else if (IS_I945GM(dev) || IS_845G(dev))
9861                 dev_priv->display.get_display_clock_speed =
9862                         i9xx_misc_get_display_clock_speed;
9863         else if (IS_PINEVIEW(dev))
9864                 dev_priv->display.get_display_clock_speed =
9865                         pnv_get_display_clock_speed;
9866         else if (IS_I915GM(dev))
9867                 dev_priv->display.get_display_clock_speed =
9868                         i915gm_get_display_clock_speed;
9869         else if (IS_I865G(dev))
9870                 dev_priv->display.get_display_clock_speed =
9871                         i865_get_display_clock_speed;
9872         else if (IS_I85X(dev))
9873                 dev_priv->display.get_display_clock_speed =
9874                         i855_get_display_clock_speed;
9875         else /* 852, 830 */
9876                 dev_priv->display.get_display_clock_speed =
9877                         i830_get_display_clock_speed;
9878
9879         if (HAS_PCH_SPLIT(dev)) {
9880                 if (IS_GEN5(dev)) {
9881                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9882                         dev_priv->display.write_eld = ironlake_write_eld;
9883                 } else if (IS_GEN6(dev)) {
9884                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9885                         dev_priv->display.write_eld = ironlake_write_eld;
9886                 } else if (IS_IVYBRIDGE(dev)) {
9887                         /* FIXME: detect B0+ stepping and use auto training */
9888                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9889                         dev_priv->display.write_eld = ironlake_write_eld;
9890                         dev_priv->display.modeset_global_resources =
9891                                 ivb_modeset_global_resources;
9892                 } else if (IS_HASWELL(dev)) {
9893                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9894                         dev_priv->display.write_eld = haswell_write_eld;
9895                         dev_priv->display.modeset_global_resources =
9896                                 haswell_modeset_global_resources;
9897                 }
9898         } else if (IS_G4X(dev)) {
9899                 dev_priv->display.write_eld = g4x_write_eld;
9900         }
9901
9902         /* Default just returns -ENODEV to indicate unsupported */
9903         dev_priv->display.queue_flip = intel_default_queue_flip;
9904
9905         switch (INTEL_INFO(dev)->gen) {
9906         case 2:
9907                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9908                 break;
9909
9910         case 3:
9911                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9912                 break;
9913
9914         case 4:
9915         case 5:
9916                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9917                 break;
9918
9919         case 6:
9920                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9921                 break;
9922         case 7:
9923                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9924                 break;
9925         }
9926 }
9927
9928 /*
9929  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9930  * resume, or other times.  This quirk makes sure that's the case for
9931  * affected systems.
9932  */
9933 static void quirk_pipea_force(struct drm_device *dev)
9934 {
9935         struct drm_i915_private *dev_priv = dev->dev_private;
9936
9937         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9938         DRM_INFO("applying pipe a force quirk\n");
9939 }
9940
9941 /*
9942  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9943  */
9944 static void quirk_ssc_force_disable(struct drm_device *dev)
9945 {
9946         struct drm_i915_private *dev_priv = dev->dev_private;
9947         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9948         DRM_INFO("applying lvds SSC disable quirk\n");
9949 }
9950
9951 /*
9952  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9953  * brightness value
9954  */
9955 static void quirk_invert_brightness(struct drm_device *dev)
9956 {
9957         struct drm_i915_private *dev_priv = dev->dev_private;
9958         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9959         DRM_INFO("applying inverted panel brightness quirk\n");
9960 }
9961
9962 /*
9963  * Some machines (Dell XPS13) suffer broken backlight controls if
9964  * BLM_PCH_PWM_ENABLE is set.
9965  */
9966 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9967 {
9968         struct drm_i915_private *dev_priv = dev->dev_private;
9969         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9970         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9971 }
9972
9973 struct intel_quirk {
9974         int device;
9975         int subsystem_vendor;
9976         int subsystem_device;
9977         void (*hook)(struct drm_device *dev);
9978 };
9979
9980 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9981 struct intel_dmi_quirk {
9982         void (*hook)(struct drm_device *dev);
9983         const struct dmi_system_id (*dmi_id_list)[];
9984 };
9985
9986 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9987 {
9988         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9989         return 1;
9990 }
9991
9992 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9993         {
9994                 .dmi_id_list = &(const struct dmi_system_id[]) {
9995                         {
9996                                 .callback = intel_dmi_reverse_brightness,
9997                                 .ident = "NCR Corporation",
9998                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9999                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10000                                 },
10001                         },
10002                         { }  /* terminating entry */
10003                 },
10004                 .hook = quirk_invert_brightness,
10005         },
10006 };
10007
10008 static struct intel_quirk intel_quirks[] = {
10009         /* HP Mini needs pipe A force quirk (LP: #322104) */
10010         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10011
10012         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10013         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10014
10015         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10016         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10017
10018         /* 830/845 need to leave pipe A & dpll A up */
10019         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10020         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10021
10022         /* Lenovo U160 cannot use SSC on LVDS */
10023         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10024
10025         /* Sony Vaio Y cannot use SSC on LVDS */
10026         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10027
10028         /* Acer Aspire 5734Z must invert backlight brightness */
10029         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
10030
10031         /* Acer/eMachines G725 */
10032         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
10033
10034         /* Acer/eMachines e725 */
10035         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
10036
10037         /* Acer/Packard Bell NCL20 */
10038         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
10039
10040         /* Acer Aspire 4736Z */
10041         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
10042
10043         /* Dell XPS13 HD Sandy Bridge */
10044         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10045         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10046         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10047 };
10048
10049 static void intel_init_quirks(struct drm_device *dev)
10050 {
10051         struct pci_dev *d = dev->pdev;
10052         int i;
10053
10054         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10055                 struct intel_quirk *q = &intel_quirks[i];
10056
10057                 if (d->device == q->device &&
10058                     (d->subsystem_vendor == q->subsystem_vendor ||
10059                      q->subsystem_vendor == PCI_ANY_ID) &&
10060                     (d->subsystem_device == q->subsystem_device ||
10061                      q->subsystem_device == PCI_ANY_ID))
10062                         q->hook(dev);
10063         }
10064         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10065                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10066                         intel_dmi_quirks[i].hook(dev);
10067         }
10068 }
10069
10070 /* Disable the VGA plane that we never use */
10071 static void i915_disable_vga(struct drm_device *dev)
10072 {
10073         struct drm_i915_private *dev_priv = dev->dev_private;
10074         u8 sr1;
10075         u32 vga_reg = i915_vgacntrl_reg(dev);
10076
10077         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10078         outb(SR01, VGA_SR_INDEX);
10079         sr1 = inb(VGA_SR_DATA);
10080         outb(sr1 | 1<<5, VGA_SR_DATA);
10081
10082         /* Disable VGA memory on Intel HD */
10083         if (HAS_PCH_SPLIT(dev)) {
10084                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10085                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10086                                                    VGA_RSRC_NORMAL_IO |
10087                                                    VGA_RSRC_NORMAL_MEM);
10088         }
10089
10090         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10091         udelay(300);
10092
10093         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10094         POSTING_READ(vga_reg);
10095 }
10096
10097 static void i915_enable_vga(struct drm_device *dev)
10098 {
10099         /* Enable VGA memory on Intel HD */
10100         if (HAS_PCH_SPLIT(dev)) {
10101                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10102                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10103                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10104                                                    VGA_RSRC_LEGACY_MEM |
10105                                                    VGA_RSRC_NORMAL_IO |
10106                                                    VGA_RSRC_NORMAL_MEM);
10107                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10108         }
10109 }
10110
10111 void intel_modeset_init_hw(struct drm_device *dev)
10112 {
10113         intel_init_power_well(dev);
10114
10115         intel_prepare_ddi(dev);
10116
10117         intel_init_clock_gating(dev);
10118
10119         mutex_lock(&dev->struct_mutex);
10120         intel_enable_gt_powersave(dev);
10121         mutex_unlock(&dev->struct_mutex);
10122 }
10123
10124 void intel_modeset_suspend_hw(struct drm_device *dev)
10125 {
10126         intel_suspend_hw(dev);
10127 }
10128
10129 void intel_modeset_init(struct drm_device *dev)
10130 {
10131         struct drm_i915_private *dev_priv = dev->dev_private;
10132         int i, j, ret;
10133
10134         drm_mode_config_init(dev);
10135
10136         dev->mode_config.min_width = 0;
10137         dev->mode_config.min_height = 0;
10138
10139         dev->mode_config.preferred_depth = 24;
10140         dev->mode_config.prefer_shadow = 1;
10141
10142         dev->mode_config.funcs = &intel_mode_funcs;
10143
10144         intel_init_quirks(dev);
10145
10146         intel_init_pm(dev);
10147
10148         if (INTEL_INFO(dev)->num_pipes == 0)
10149                 return;
10150
10151         intel_init_display(dev);
10152
10153         if (IS_GEN2(dev)) {
10154                 dev->mode_config.max_width = 2048;
10155                 dev->mode_config.max_height = 2048;
10156         } else if (IS_GEN3(dev)) {
10157                 dev->mode_config.max_width = 4096;
10158                 dev->mode_config.max_height = 4096;
10159         } else {
10160                 dev->mode_config.max_width = 8192;
10161                 dev->mode_config.max_height = 8192;
10162         }
10163         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10164
10165         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10166                       INTEL_INFO(dev)->num_pipes,
10167                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10168
10169         for_each_pipe(i) {
10170                 intel_crtc_init(dev, i);
10171                 for (j = 0; j < dev_priv->num_plane; j++) {
10172                         ret = intel_plane_init(dev, i, j);
10173                         if (ret)
10174                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10175                                               pipe_name(i), sprite_name(i, j), ret);
10176                 }
10177         }
10178
10179         intel_cpu_pll_init(dev);
10180         intel_shared_dpll_init(dev);
10181
10182         /* Just disable it once at startup */
10183         i915_disable_vga(dev);
10184         intel_setup_outputs(dev);
10185
10186         /* Just in case the BIOS is doing something questionable. */
10187         intel_disable_fbc(dev);
10188 }
10189
10190 static void
10191 intel_connector_break_all_links(struct intel_connector *connector)
10192 {
10193         connector->base.dpms = DRM_MODE_DPMS_OFF;
10194         connector->base.encoder = NULL;
10195         connector->encoder->connectors_active = false;
10196         connector->encoder->base.crtc = NULL;
10197 }
10198
10199 static void intel_enable_pipe_a(struct drm_device *dev)
10200 {
10201         struct intel_connector *connector;
10202         struct drm_connector *crt = NULL;
10203         struct intel_load_detect_pipe load_detect_temp;
10204
10205         /* We can't just switch on the pipe A, we need to set things up with a
10206          * proper mode and output configuration. As a gross hack, enable pipe A
10207          * by enabling the load detect pipe once. */
10208         list_for_each_entry(connector,
10209                             &dev->mode_config.connector_list,
10210                             base.head) {
10211                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10212                         crt = &connector->base;
10213                         break;
10214                 }
10215         }
10216
10217         if (!crt)
10218                 return;
10219
10220         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10221                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10222
10223
10224 }
10225
10226 static bool
10227 intel_check_plane_mapping(struct intel_crtc *crtc)
10228 {
10229         struct drm_device *dev = crtc->base.dev;
10230         struct drm_i915_private *dev_priv = dev->dev_private;
10231         u32 reg, val;
10232
10233         if (INTEL_INFO(dev)->num_pipes == 1)
10234                 return true;
10235
10236         reg = DSPCNTR(!crtc->plane);
10237         val = I915_READ(reg);
10238
10239         if ((val & DISPLAY_PLANE_ENABLE) &&
10240             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10241                 return false;
10242
10243         return true;
10244 }
10245
10246 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10247 {
10248         struct drm_device *dev = crtc->base.dev;
10249         struct drm_i915_private *dev_priv = dev->dev_private;
10250         u32 reg;
10251
10252         /* Clear any frame start delays used for debugging left by the BIOS */
10253         reg = PIPECONF(crtc->config.cpu_transcoder);
10254         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10255
10256         /* We need to sanitize the plane -> pipe mapping first because this will
10257          * disable the crtc (and hence change the state) if it is wrong. Note
10258          * that gen4+ has a fixed plane -> pipe mapping.  */
10259         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10260                 struct intel_connector *connector;
10261                 bool plane;
10262
10263                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10264                               crtc->base.base.id);
10265
10266                 /* Pipe has the wrong plane attached and the plane is active.
10267                  * Temporarily change the plane mapping and disable everything
10268                  * ...  */
10269                 plane = crtc->plane;
10270                 crtc->plane = !plane;
10271                 dev_priv->display.crtc_disable(&crtc->base);
10272                 crtc->plane = plane;
10273
10274                 /* ... and break all links. */
10275                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10276                                     base.head) {
10277                         if (connector->encoder->base.crtc != &crtc->base)
10278                                 continue;
10279
10280                         intel_connector_break_all_links(connector);
10281                 }
10282
10283                 WARN_ON(crtc->active);
10284                 crtc->base.enabled = false;
10285         }
10286
10287         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10288             crtc->pipe == PIPE_A && !crtc->active) {
10289                 /* BIOS forgot to enable pipe A, this mostly happens after
10290                  * resume. Force-enable the pipe to fix this, the update_dpms
10291                  * call below we restore the pipe to the right state, but leave
10292                  * the required bits on. */
10293                 intel_enable_pipe_a(dev);
10294         }
10295
10296         /* Adjust the state of the output pipe according to whether we
10297          * have active connectors/encoders. */
10298         intel_crtc_update_dpms(&crtc->base);
10299
10300         if (crtc->active != crtc->base.enabled) {
10301                 struct intel_encoder *encoder;
10302
10303                 /* This can happen either due to bugs in the get_hw_state
10304                  * functions or because the pipe is force-enabled due to the
10305                  * pipe A quirk. */
10306                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10307                               crtc->base.base.id,
10308                               crtc->base.enabled ? "enabled" : "disabled",
10309                               crtc->active ? "enabled" : "disabled");
10310
10311                 crtc->base.enabled = crtc->active;
10312
10313                 /* Because we only establish the connector -> encoder ->
10314                  * crtc links if something is active, this means the
10315                  * crtc is now deactivated. Break the links. connector
10316                  * -> encoder links are only establish when things are
10317                  *  actually up, hence no need to break them. */
10318                 WARN_ON(crtc->active);
10319
10320                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10321                         WARN_ON(encoder->connectors_active);
10322                         encoder->base.crtc = NULL;
10323                 }
10324         }
10325 }
10326
10327 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10328 {
10329         struct intel_connector *connector;
10330         struct drm_device *dev = encoder->base.dev;
10331
10332         /* We need to check both for a crtc link (meaning that the
10333          * encoder is active and trying to read from a pipe) and the
10334          * pipe itself being active. */
10335         bool has_active_crtc = encoder->base.crtc &&
10336                 to_intel_crtc(encoder->base.crtc)->active;
10337
10338         if (encoder->connectors_active && !has_active_crtc) {
10339                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10340                               encoder->base.base.id,
10341                               drm_get_encoder_name(&encoder->base));
10342
10343                 /* Connector is active, but has no active pipe. This is
10344                  * fallout from our resume register restoring. Disable
10345                  * the encoder manually again. */
10346                 if (encoder->base.crtc) {
10347                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10348                                       encoder->base.base.id,
10349                                       drm_get_encoder_name(&encoder->base));
10350                         encoder->disable(encoder);
10351                 }
10352
10353                 /* Inconsistent output/port/pipe state happens presumably due to
10354                  * a bug in one of the get_hw_state functions. Or someplace else
10355                  * in our code, like the register restore mess on resume. Clamp
10356                  * things to off as a safer default. */
10357                 list_for_each_entry(connector,
10358                                     &dev->mode_config.connector_list,
10359                                     base.head) {
10360                         if (connector->encoder != encoder)
10361                                 continue;
10362
10363                         intel_connector_break_all_links(connector);
10364                 }
10365         }
10366         /* Enabled encoders without active connectors will be fixed in
10367          * the crtc fixup. */
10368 }
10369
10370 void i915_redisable_vga(struct drm_device *dev)
10371 {
10372         struct drm_i915_private *dev_priv = dev->dev_private;
10373         u32 vga_reg = i915_vgacntrl_reg(dev);
10374
10375         /* This function can be called both from intel_modeset_setup_hw_state or
10376          * at a very early point in our resume sequence, where the power well
10377          * structures are not yet restored. Since this function is at a very
10378          * paranoid "someone might have enabled VGA while we were not looking"
10379          * level, just check if the power well is enabled instead of trying to
10380          * follow the "don't touch the power well if we don't need it" policy
10381          * the rest of the driver uses. */
10382         if (HAS_POWER_WELL(dev) &&
10383             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10384                 return;
10385
10386         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10387                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10388                 i915_disable_vga(dev);
10389         }
10390 }
10391
10392 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10393 {
10394         struct drm_i915_private *dev_priv = dev->dev_private;
10395         enum pipe pipe;
10396         struct intel_crtc *crtc;
10397         struct intel_encoder *encoder;
10398         struct intel_connector *connector;
10399         int i;
10400
10401         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10402                             base.head) {
10403                 memset(&crtc->config, 0, sizeof(crtc->config));
10404
10405                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10406                                                                  &crtc->config);
10407
10408                 crtc->base.enabled = crtc->active;
10409
10410                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10411                               crtc->base.base.id,
10412                               crtc->active ? "enabled" : "disabled");
10413         }
10414
10415         /* FIXME: Smash this into the new shared dpll infrastructure. */
10416         if (HAS_DDI(dev))
10417                 intel_ddi_setup_hw_pll_state(dev);
10418
10419         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10420                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10421
10422                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10423                 pll->active = 0;
10424                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10425                                     base.head) {
10426                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10427                                 pll->active++;
10428                 }
10429                 pll->refcount = pll->active;
10430
10431                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10432                               pll->name, pll->refcount, pll->on);
10433         }
10434
10435         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10436                             base.head) {
10437                 pipe = 0;
10438
10439                 if (encoder->get_hw_state(encoder, &pipe)) {
10440                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10441                         encoder->base.crtc = &crtc->base;
10442                         if (encoder->get_config)
10443                                 encoder->get_config(encoder, &crtc->config);
10444                 } else {
10445                         encoder->base.crtc = NULL;
10446                 }
10447
10448                 encoder->connectors_active = false;
10449                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10450                               encoder->base.base.id,
10451                               drm_get_encoder_name(&encoder->base),
10452                               encoder->base.crtc ? "enabled" : "disabled",
10453                               pipe);
10454         }
10455
10456         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10457                             base.head) {
10458                 if (!crtc->active)
10459                         continue;
10460                 if (dev_priv->display.get_clock)
10461                         dev_priv->display.get_clock(crtc,
10462                                                     &crtc->config);
10463         }
10464
10465         list_for_each_entry(connector, &dev->mode_config.connector_list,
10466                             base.head) {
10467                 if (connector->get_hw_state(connector)) {
10468                         connector->base.dpms = DRM_MODE_DPMS_ON;
10469                         connector->encoder->connectors_active = true;
10470                         connector->base.encoder = &connector->encoder->base;
10471                 } else {
10472                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10473                         connector->base.encoder = NULL;
10474                 }
10475                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10476                               connector->base.base.id,
10477                               drm_get_connector_name(&connector->base),
10478                               connector->base.encoder ? "enabled" : "disabled");
10479         }
10480 }
10481
10482 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10483  * and i915 state tracking structures. */
10484 void intel_modeset_setup_hw_state(struct drm_device *dev,
10485                                   bool force_restore)
10486 {
10487         struct drm_i915_private *dev_priv = dev->dev_private;
10488         enum pipe pipe;
10489         struct drm_plane *plane;
10490         struct intel_crtc *crtc;
10491         struct intel_encoder *encoder;
10492         int i;
10493
10494         intel_modeset_readout_hw_state(dev);
10495
10496         /*
10497          * Now that we have the config, copy it to each CRTC struct
10498          * Note that this could go away if we move to using crtc_config
10499          * checking everywhere.
10500          */
10501         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10502                             base.head) {
10503                 if (crtc->active && i915_fastboot) {
10504                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10505
10506                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10507                                       crtc->base.base.id);
10508                         drm_mode_debug_printmodeline(&crtc->base.mode);
10509                 }
10510         }
10511
10512         /* HW state is read out, now we need to sanitize this mess. */
10513         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10514                             base.head) {
10515                 intel_sanitize_encoder(encoder);
10516         }
10517
10518         for_each_pipe(pipe) {
10519                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10520                 intel_sanitize_crtc(crtc);
10521                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10522         }
10523
10524         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10525                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10526
10527                 if (!pll->on || pll->active)
10528                         continue;
10529
10530                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10531
10532                 pll->disable(dev_priv, pll);
10533                 pll->on = false;
10534         }
10535
10536         if (force_restore) {
10537                 /*
10538                  * We need to use raw interfaces for restoring state to avoid
10539                  * checking (bogus) intermediate states.
10540                  */
10541                 for_each_pipe(pipe) {
10542                         struct drm_crtc *crtc =
10543                                 dev_priv->pipe_to_crtc_mapping[pipe];
10544
10545                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10546                                          crtc->fb);
10547                 }
10548                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10549                         intel_plane_restore(plane);
10550
10551                 i915_redisable_vga(dev);
10552         } else {
10553                 intel_modeset_update_staged_output_state(dev);
10554         }
10555
10556         intel_modeset_check_state(dev);
10557
10558         drm_mode_config_reset(dev);
10559 }
10560
10561 void intel_modeset_gem_init(struct drm_device *dev)
10562 {
10563         intel_modeset_init_hw(dev);
10564
10565         intel_setup_overlay(dev);
10566
10567         intel_modeset_setup_hw_state(dev, false);
10568 }
10569
10570 void intel_modeset_cleanup(struct drm_device *dev)
10571 {
10572         struct drm_i915_private *dev_priv = dev->dev_private;
10573         struct drm_crtc *crtc;
10574
10575         /*
10576          * Interrupts and polling as the first thing to avoid creating havoc.
10577          * Too much stuff here (turning of rps, connectors, ...) would
10578          * experience fancy races otherwise.
10579          */
10580         drm_irq_uninstall(dev);
10581         cancel_work_sync(&dev_priv->hotplug_work);
10582         /*
10583          * Due to the hpd irq storm handling the hotplug work can re-arm the
10584          * poll handlers. Hence disable polling after hpd handling is shut down.
10585          */
10586         drm_kms_helper_poll_fini(dev);
10587
10588         mutex_lock(&dev->struct_mutex);
10589
10590         intel_unregister_dsm_handler();
10591
10592         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10593                 /* Skip inactive CRTCs */
10594                 if (!crtc->fb)
10595                         continue;
10596
10597                 intel_increase_pllclock(crtc);
10598         }
10599
10600         intel_disable_fbc(dev);
10601
10602         i915_enable_vga(dev);
10603
10604         intel_disable_gt_powersave(dev);
10605
10606         ironlake_teardown_rc6(dev);
10607
10608         mutex_unlock(&dev->struct_mutex);
10609
10610         /* flush any delayed tasks or pending work */
10611         flush_scheduled_work();
10612
10613         /* destroy backlight, if any, before the connectors */
10614         intel_panel_destroy_backlight(dev);
10615
10616         drm_mode_config_cleanup(dev);
10617
10618         intel_cleanup_overlay(dev);
10619 }
10620
10621 /*
10622  * Return which encoder is currently attached for connector.
10623  */
10624 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10625 {
10626         return &intel_attached_encoder(connector)->base;
10627 }
10628
10629 void intel_connector_attach_encoder(struct intel_connector *connector,
10630                                     struct intel_encoder *encoder)
10631 {
10632         connector->encoder = encoder;
10633         drm_mode_connector_attach_encoder(&connector->base,
10634                                           &encoder->base);
10635 }
10636
10637 /*
10638  * set vga decode state - true == enable VGA decode
10639  */
10640 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10641 {
10642         struct drm_i915_private *dev_priv = dev->dev_private;
10643         u16 gmch_ctrl;
10644
10645         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10646         if (state)
10647                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10648         else
10649                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10650         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10651         return 0;
10652 }
10653
10654 struct intel_display_error_state {
10655
10656         u32 power_well_driver;
10657
10658         int num_transcoders;
10659
10660         struct intel_cursor_error_state {
10661                 u32 control;
10662                 u32 position;
10663                 u32 base;
10664                 u32 size;
10665         } cursor[I915_MAX_PIPES];
10666
10667         struct intel_pipe_error_state {
10668                 u32 source;
10669         } pipe[I915_MAX_PIPES];
10670
10671         struct intel_plane_error_state {
10672                 u32 control;
10673                 u32 stride;
10674                 u32 size;
10675                 u32 pos;
10676                 u32 addr;
10677                 u32 surface;
10678                 u32 tile_offset;
10679         } plane[I915_MAX_PIPES];
10680
10681         struct intel_transcoder_error_state {
10682                 enum transcoder cpu_transcoder;
10683
10684                 u32 conf;
10685
10686                 u32 htotal;
10687                 u32 hblank;
10688                 u32 hsync;
10689                 u32 vtotal;
10690                 u32 vblank;
10691                 u32 vsync;
10692         } transcoder[4];
10693 };
10694
10695 struct intel_display_error_state *
10696 intel_display_capture_error_state(struct drm_device *dev)
10697 {
10698         drm_i915_private_t *dev_priv = dev->dev_private;
10699         struct intel_display_error_state *error;
10700         int transcoders[] = {
10701                 TRANSCODER_A,
10702                 TRANSCODER_B,
10703                 TRANSCODER_C,
10704                 TRANSCODER_EDP,
10705         };
10706         int i;
10707
10708         if (INTEL_INFO(dev)->num_pipes == 0)
10709                 return NULL;
10710
10711         error = kmalloc(sizeof(*error), GFP_ATOMIC);
10712         if (error == NULL)
10713                 return NULL;
10714
10715         if (HAS_POWER_WELL(dev))
10716                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10717
10718         for_each_pipe(i) {
10719                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10720                         error->cursor[i].control = I915_READ(CURCNTR(i));
10721                         error->cursor[i].position = I915_READ(CURPOS(i));
10722                         error->cursor[i].base = I915_READ(CURBASE(i));
10723                 } else {
10724                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10725                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10726                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10727                 }
10728
10729                 error->plane[i].control = I915_READ(DSPCNTR(i));
10730                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10731                 if (INTEL_INFO(dev)->gen <= 3) {
10732                         error->plane[i].size = I915_READ(DSPSIZE(i));
10733                         error->plane[i].pos = I915_READ(DSPPOS(i));
10734                 }
10735                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10736                         error->plane[i].addr = I915_READ(DSPADDR(i));
10737                 if (INTEL_INFO(dev)->gen >= 4) {
10738                         error->plane[i].surface = I915_READ(DSPSURF(i));
10739                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10740                 }
10741
10742                 error->pipe[i].source = I915_READ(PIPESRC(i));
10743         }
10744
10745         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10746         if (HAS_DDI(dev_priv->dev))
10747                 error->num_transcoders++; /* Account for eDP. */
10748
10749         for (i = 0; i < error->num_transcoders; i++) {
10750                 enum transcoder cpu_transcoder = transcoders[i];
10751
10752                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10753
10754                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10755                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10756                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10757                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10758                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10759                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10760                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10761         }
10762
10763         /* In the code above we read the registers without checking if the power
10764          * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10765          * prevent the next I915_WRITE from detecting it and printing an error
10766          * message. */
10767         intel_uncore_clear_errors(dev);
10768
10769         return error;
10770 }
10771
10772 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10773
10774 void
10775 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10776                                 struct drm_device *dev,
10777                                 struct intel_display_error_state *error)
10778 {
10779         int i;
10780
10781         if (!error)
10782                 return;
10783
10784         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10785         if (HAS_POWER_WELL(dev))
10786                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10787                            error->power_well_driver);
10788         for_each_pipe(i) {
10789                 err_printf(m, "Pipe [%d]:\n", i);
10790                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
10791
10792                 err_printf(m, "Plane [%d]:\n", i);
10793                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10794                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10795                 if (INTEL_INFO(dev)->gen <= 3) {
10796                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10797                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10798                 }
10799                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10800                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10801                 if (INTEL_INFO(dev)->gen >= 4) {
10802                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10803                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10804                 }
10805
10806                 err_printf(m, "Cursor [%d]:\n", i);
10807                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10808                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10809                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10810         }
10811
10812         for (i = 0; i < error->num_transcoders; i++) {
10813                 err_printf(m, "  CPU transcoder: %c\n",
10814                            transcoder_name(error->transcoder[i].cpu_transcoder));
10815                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10816                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10817                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10818                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10819                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10820                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10821                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
10822         }
10823 }