2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
63 struct drm_encoder *encoder = &intel_encoder->base;
64 int type = intel_encoder->type;
66 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
67 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
68 struct intel_digital_port *intel_dig_port =
69 enc_to_dig_port(encoder);
70 return intel_dig_port->port;
72 } else if (type == INTEL_OUTPUT_ANALOG) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
90 struct drm_i915_private *dev_priv = dev->dev_private;
93 const u32 *ddi_translations = ((use_fdi_mode) ?
94 hsw_ddi_translations_fdi :
95 hsw_ddi_translations_dp);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode ? "FDI" : "DP");
101 WARN((use_fdi_mode && (port != PORT_E)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
106 I915_WRITE(reg, ddi_translations[i]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device *dev)
121 for (port = PORT_A; port < PORT_E; port++)
122 intel_prepare_ddi_buffers(dev, port, false);
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
128 intel_prepare_ddi_buffers(dev, PORT_E, true);
131 static const long hsw_ddi_buf_ctl_values[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW,
133 DDI_BUF_EMP_400MV_3_5DB_HSW,
134 DDI_BUF_EMP_400MV_6DB_HSW,
135 DDI_BUF_EMP_400MV_9_5DB_HSW,
136 DDI_BUF_EMP_600MV_0DB_HSW,
137 DDI_BUF_EMP_600MV_3_5DB_HSW,
138 DDI_BUF_EMP_600MV_6DB_HSW,
139 DDI_BUF_EMP_800MV_0DB_HSW,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
146 uint32_t reg = DDI_BUF_CTL(port);
149 for (i = 0; i < 8; i++) {
151 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc *crtc)
168 struct drm_device *dev = crtc->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
171 u32 temp, i, rx_ctl_val;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
179 FDI_RX_PWRDN_LANE0_VAL(2) |
180 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
182 /* Enable the PCH Receiver FDI PLL */
183 rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
184 ((intel_crtc->fdi_lanes - 1) << 19);
185 if (dev_priv->fdi_rx_polarity_reversed)
186 rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT;
187 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
188 POSTING_READ(_FDI_RXA_CTL);
191 /* Switch from Rawclk to PCDclk */
192 rx_ctl_val |= FDI_PCDCLK;
193 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
195 /* Configure Port Clock Select */
196 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
198 /* Start the training iterating through available voltages and emphasis,
199 * testing each value twice. */
200 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
201 /* Configure DP_TP_CTL with auto-training */
202 I915_WRITE(DP_TP_CTL(PORT_E),
203 DP_TP_CTL_FDI_AUTOTRAIN |
204 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
205 DP_TP_CTL_LINK_TRAIN_PAT1 |
208 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
209 I915_WRITE(DDI_BUF_CTL(PORT_E),
211 ((intel_crtc->fdi_lanes - 1) << 1) |
212 hsw_ddi_buf_ctl_values[i / 2]);
213 POSTING_READ(DDI_BUF_CTL(PORT_E));
217 /* Program PCH FDI Receiver TU */
218 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
220 /* Enable PCH FDI Receiver with auto-training */
221 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
222 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
223 POSTING_READ(_FDI_RXA_CTL);
225 /* Wait for FDI receiver lane calibration */
228 /* Unset FDI_RX_MISC pwrdn lanes */
229 temp = I915_READ(_FDI_RXA_MISC);
230 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
231 I915_WRITE(_FDI_RXA_MISC, temp);
232 POSTING_READ(_FDI_RXA_MISC);
234 /* Wait for FDI auto training time */
237 temp = I915_READ(DP_TP_STATUS(PORT_E));
238 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
239 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
241 /* Enable normal pixel sending for FDI */
242 I915_WRITE(DP_TP_CTL(PORT_E),
243 DP_TP_CTL_FDI_AUTOTRAIN |
244 DP_TP_CTL_LINK_TRAIN_NORMAL |
245 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
251 temp = I915_READ(DDI_BUF_CTL(PORT_E));
252 temp &= ~DDI_BUF_CTL_ENABLE;
253 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
254 POSTING_READ(DDI_BUF_CTL(PORT_E));
256 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
257 temp = I915_READ(DP_TP_CTL(PORT_E));
258 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
259 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
260 I915_WRITE(DP_TP_CTL(PORT_E), temp);
261 POSTING_READ(DP_TP_CTL(PORT_E));
263 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
265 rx_ctl_val &= ~FDI_RX_ENABLE;
266 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
267 POSTING_READ(_FDI_RXA_CTL);
269 /* Reset FDI_RX_MISC pwrdn lanes */
270 temp = I915_READ(_FDI_RXA_MISC);
271 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
272 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
273 I915_WRITE(_FDI_RXA_MISC, temp);
274 POSTING_READ(_FDI_RXA_MISC);
277 DRM_ERROR("FDI link training failed!\n");
280 /* WRPLL clock dividers */
281 struct wrpll_tmds_clock {
283 u16 p; /* Post divider */
284 u16 n2; /* Feedback divider */
285 u16 r2; /* Reference divider */
288 /* Table of matching values for WRPLL clocks programming for each frequency.
289 * The code assumes this table is sorted. */
290 static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
305 {27027, 18, 100, 111},
333 {40541, 22, 147, 89},
343 {44900, 20, 108, 65},
359 {54054, 16, 173, 108},
411 {81081, 6, 100, 111},
456 {108108, 8, 173, 108},
463 {111264, 8, 150, 91},
507 {135250, 6, 167, 111},
530 {148352, 4, 100, 91},
552 {162162, 4, 131, 109},
560 {169000, 4, 104, 83},
607 {202000, 4, 112, 75},
609 {203000, 4, 146, 97},
666 static void intel_ddi_mode_set(struct drm_encoder *encoder,
667 struct drm_display_mode *mode,
668 struct drm_display_mode *adjusted_mode)
670 struct drm_crtc *crtc = encoder->crtc;
671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
672 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
673 int port = intel_ddi_get_encoder_port(intel_encoder);
674 int pipe = intel_crtc->pipe;
675 int type = intel_encoder->type;
677 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
678 port_name(port), pipe_name(pipe));
680 intel_crtc->eld_vld = false;
681 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
682 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
684 intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
685 switch (intel_dp->lane_count) {
687 intel_dp->DP |= DDI_PORT_WIDTH_X1;
690 intel_dp->DP |= DDI_PORT_WIDTH_X2;
693 intel_dp->DP |= DDI_PORT_WIDTH_X4;
696 intel_dp->DP |= DDI_PORT_WIDTH_X4;
697 WARN(1, "Unexpected DP lane count %d\n",
698 intel_dp->lane_count);
702 if (intel_dp->has_audio) {
703 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
704 pipe_name(intel_crtc->pipe));
707 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
708 intel_write_eld(encoder, adjusted_mode);
711 intel_dp_init_link_config(intel_dp);
713 } else if (type == INTEL_OUTPUT_HDMI) {
714 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
716 if (intel_hdmi->has_audio) {
717 /* Proper support for digital audio needs a new logic
718 * and a new set of registers, so we leave it for future
721 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
722 pipe_name(intel_crtc->pipe));
725 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
726 intel_write_eld(encoder, adjusted_mode);
729 intel_hdmi->set_infoframes(encoder, adjusted_mode);
733 static struct intel_encoder *
734 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
736 struct drm_device *dev = crtc->dev;
737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
738 struct intel_encoder *intel_encoder, *ret = NULL;
739 int num_encoders = 0;
741 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
746 if (num_encoders != 1)
747 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
754 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
756 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
757 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
761 switch (intel_crtc->ddi_pll_sel) {
762 case PORT_CLK_SEL_SPLL:
763 plls->spll_refcount--;
764 if (plls->spll_refcount == 0) {
765 DRM_DEBUG_KMS("Disabling SPLL\n");
766 val = I915_READ(SPLL_CTL);
767 WARN_ON(!(val & SPLL_PLL_ENABLE));
768 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
769 POSTING_READ(SPLL_CTL);
772 case PORT_CLK_SEL_WRPLL1:
773 plls->wrpll1_refcount--;
774 if (plls->wrpll1_refcount == 0) {
775 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
776 val = I915_READ(WRPLL_CTL1);
777 WARN_ON(!(val & WRPLL_PLL_ENABLE));
778 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
779 POSTING_READ(WRPLL_CTL1);
782 case PORT_CLK_SEL_WRPLL2:
783 plls->wrpll2_refcount--;
784 if (plls->wrpll2_refcount == 0) {
785 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
786 val = I915_READ(WRPLL_CTL2);
787 WARN_ON(!(val & WRPLL_PLL_ENABLE));
788 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
789 POSTING_READ(WRPLL_CTL2);
794 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
795 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
796 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
798 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
801 static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
805 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
806 if (clock <= wrpll_tmds_clock_table[i].clock)
809 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
812 *p = wrpll_tmds_clock_table[i].p;
813 *n2 = wrpll_tmds_clock_table[i].n2;
814 *r2 = wrpll_tmds_clock_table[i].r2;
816 if (wrpll_tmds_clock_table[i].clock != clock)
817 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
818 wrpll_tmds_clock_table[i].clock, clock);
820 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
821 clock, *p, *n2, *r2);
824 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
827 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
828 struct drm_encoder *encoder = &intel_encoder->base;
829 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
830 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
831 int type = intel_encoder->type;
832 enum pipe pipe = intel_crtc->pipe;
835 /* TODO: reuse PLLs when possible (compare values) */
837 intel_ddi_put_crtc_pll(crtc);
839 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
840 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
842 switch (intel_dp->link_bw) {
843 case DP_LINK_BW_1_62:
844 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
847 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
850 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
853 DRM_ERROR("Link bandwidth %d unsupported\n",
858 /* We don't need to turn any PLL on because we'll use LCPLL. */
861 } else if (type == INTEL_OUTPUT_HDMI) {
864 if (plls->wrpll1_refcount == 0) {
865 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
867 plls->wrpll1_refcount++;
869 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
870 } else if (plls->wrpll2_refcount == 0) {
871 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
873 plls->wrpll2_refcount++;
875 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
877 DRM_ERROR("No WRPLLs available!\n");
881 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
882 "WRPLL already enabled\n");
884 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
886 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
887 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
888 WRPLL_DIVIDER_POST(p);
890 } else if (type == INTEL_OUTPUT_ANALOG) {
891 if (plls->spll_refcount == 0) {
892 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
894 plls->spll_refcount++;
896 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
899 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
900 "SPLL already enabled\n");
902 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
905 WARN(1, "Invalid DDI encoder type %d\n", type);
909 I915_WRITE(reg, val);
915 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
917 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
919 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
920 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
921 int type = intel_encoder->type;
924 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
926 temp = TRANS_MSA_SYNC_CLK;
927 switch (intel_crtc->bpp) {
929 temp |= TRANS_MSA_6_BPC;
932 temp |= TRANS_MSA_8_BPC;
935 temp |= TRANS_MSA_10_BPC;
938 temp |= TRANS_MSA_12_BPC;
941 temp |= TRANS_MSA_8_BPC;
942 WARN(1, "%d bpp unsupported by DDI function\n",
945 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
949 void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
952 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
953 struct drm_encoder *encoder = &intel_encoder->base;
954 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
955 enum pipe pipe = intel_crtc->pipe;
956 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
957 enum port port = intel_ddi_get_encoder_port(intel_encoder);
958 int type = intel_encoder->type;
961 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
962 temp = TRANS_DDI_FUNC_ENABLE;
963 temp |= TRANS_DDI_SELECT_PORT(port);
965 switch (intel_crtc->bpp) {
967 temp |= TRANS_DDI_BPC_6;
970 temp |= TRANS_DDI_BPC_8;
973 temp |= TRANS_DDI_BPC_10;
976 temp |= TRANS_DDI_BPC_12;
979 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
983 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
984 temp |= TRANS_DDI_PVSYNC;
985 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
986 temp |= TRANS_DDI_PHSYNC;
988 if (cpu_transcoder == TRANSCODER_EDP) {
991 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
994 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
997 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1005 if (type == INTEL_OUTPUT_HDMI) {
1006 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1008 if (intel_hdmi->has_hdmi_sink)
1009 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1011 temp |= TRANS_DDI_MODE_SELECT_DVI;
1013 } else if (type == INTEL_OUTPUT_ANALOG) {
1014 temp |= TRANS_DDI_MODE_SELECT_FDI;
1015 temp |= (intel_crtc->fdi_lanes - 1) << 1;
1017 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1018 type == INTEL_OUTPUT_EDP) {
1019 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1021 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1023 switch (intel_dp->lane_count) {
1025 temp |= TRANS_DDI_PORT_WIDTH_X1;
1028 temp |= TRANS_DDI_PORT_WIDTH_X2;
1031 temp |= TRANS_DDI_PORT_WIDTH_X4;
1034 temp |= TRANS_DDI_PORT_WIDTH_X4;
1035 WARN(1, "Unsupported lane count %d\n",
1036 intel_dp->lane_count);
1040 WARN(1, "Invalid encoder type %d for pipe %d\n",
1041 intel_encoder->type, pipe);
1044 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1047 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1048 enum transcoder cpu_transcoder)
1050 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1051 uint32_t val = I915_READ(reg);
1053 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1054 val |= TRANS_DDI_PORT_NONE;
1055 I915_WRITE(reg, val);
1058 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1060 struct drm_device *dev = intel_connector->base.dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 struct intel_encoder *intel_encoder = intel_connector->encoder;
1063 int type = intel_connector->base.connector_type;
1064 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1066 enum transcoder cpu_transcoder;
1069 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1073 cpu_transcoder = TRANSCODER_EDP;
1075 cpu_transcoder = (enum transcoder) pipe;
1077 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1079 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1080 case TRANS_DDI_MODE_SELECT_HDMI:
1081 case TRANS_DDI_MODE_SELECT_DVI:
1082 return (type == DRM_MODE_CONNECTOR_HDMIA);
1084 case TRANS_DDI_MODE_SELECT_DP_SST:
1085 if (type == DRM_MODE_CONNECTOR_eDP)
1087 case TRANS_DDI_MODE_SELECT_DP_MST:
1088 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1090 case TRANS_DDI_MODE_SELECT_FDI:
1091 return (type == DRM_MODE_CONNECTOR_VGA);
1098 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1101 struct drm_device *dev = encoder->base.dev;
1102 struct drm_i915_private *dev_priv = dev->dev_private;
1103 enum port port = intel_ddi_get_encoder_port(encoder);
1107 tmp = I915_READ(DDI_BUF_CTL(port));
1109 if (!(tmp & DDI_BUF_CTL_ENABLE))
1112 if (port == PORT_A) {
1113 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1115 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1116 case TRANS_DDI_EDP_INPUT_A_ON:
1117 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1120 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1123 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1130 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1131 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1133 if ((tmp & TRANS_DDI_PORT_MASK)
1134 == TRANS_DDI_SELECT_PORT(port)) {
1141 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
1146 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1151 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1155 if (cpu_transcoder == TRANSCODER_EDP) {
1158 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1159 temp &= TRANS_DDI_PORT_MASK;
1161 for (i = PORT_B; i <= PORT_E; i++)
1162 if (temp == TRANS_DDI_SELECT_PORT(i))
1166 ret = I915_READ(PORT_CLK_SEL(port));
1168 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1169 pipe_name(pipe), port_name(port), ret);
1174 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1178 struct intel_crtc *intel_crtc;
1180 for_each_pipe(pipe) {
1182 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1184 if (!intel_crtc->active)
1187 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1190 switch (intel_crtc->ddi_pll_sel) {
1191 case PORT_CLK_SEL_SPLL:
1192 dev_priv->ddi_plls.spll_refcount++;
1194 case PORT_CLK_SEL_WRPLL1:
1195 dev_priv->ddi_plls.wrpll1_refcount++;
1197 case PORT_CLK_SEL_WRPLL2:
1198 dev_priv->ddi_plls.wrpll2_refcount++;
1204 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1206 struct drm_crtc *crtc = &intel_crtc->base;
1207 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1208 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1209 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1210 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1212 if (cpu_transcoder != TRANSCODER_EDP)
1213 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1214 TRANS_CLK_SEL_PORT(port));
1217 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1219 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1220 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1222 if (cpu_transcoder != TRANSCODER_EDP)
1223 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1224 TRANS_CLK_SEL_DISABLED);
1227 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1229 struct drm_encoder *encoder = &intel_encoder->base;
1230 struct drm_crtc *crtc = encoder->crtc;
1231 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1233 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1234 int type = intel_encoder->type;
1236 if (type == INTEL_OUTPUT_EDP) {
1237 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1238 ironlake_edp_panel_vdd_on(intel_dp);
1239 ironlake_edp_panel_on(intel_dp);
1240 ironlake_edp_panel_vdd_off(intel_dp, true);
1243 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1244 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1246 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1247 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1249 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1250 intel_dp_start_link_train(intel_dp);
1251 intel_dp_complete_link_train(intel_dp);
1255 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1257 struct drm_encoder *encoder = &intel_encoder->base;
1258 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1259 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1260 int type = intel_encoder->type;
1264 val = I915_READ(DDI_BUF_CTL(port));
1265 if (val & DDI_BUF_CTL_ENABLE) {
1266 val &= ~DDI_BUF_CTL_ENABLE;
1267 I915_WRITE(DDI_BUF_CTL(port), val);
1271 val = I915_READ(DP_TP_CTL(port));
1272 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1273 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1274 I915_WRITE(DP_TP_CTL(port), val);
1277 intel_wait_ddi_buf_idle(dev_priv, port);
1279 if (type == INTEL_OUTPUT_EDP) {
1280 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1281 ironlake_edp_panel_vdd_on(intel_dp);
1282 ironlake_edp_panel_off(intel_dp);
1285 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1288 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1290 struct drm_encoder *encoder = &intel_encoder->base;
1291 struct drm_crtc *crtc = encoder->crtc;
1292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1293 int pipe = intel_crtc->pipe;
1294 struct drm_device *dev = encoder->dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1297 int type = intel_encoder->type;
1300 if (type == INTEL_OUTPUT_HDMI) {
1301 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1302 * are ignored so nothing special needs to be done besides
1303 * enabling the port.
1305 I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE);
1306 } else if (type == INTEL_OUTPUT_EDP) {
1307 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1309 ironlake_edp_backlight_on(intel_dp);
1312 if (intel_crtc->eld_vld) {
1313 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1314 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1315 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1319 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1321 struct drm_encoder *encoder = &intel_encoder->base;
1322 struct drm_crtc *crtc = encoder->crtc;
1323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1324 int pipe = intel_crtc->pipe;
1325 int type = intel_encoder->type;
1326 struct drm_device *dev = encoder->dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1330 if (type == INTEL_OUTPUT_EDP) {
1331 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1333 ironlake_edp_backlight_off(intel_dp);
1336 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1337 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1338 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1341 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1343 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1345 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1348 else if (IS_ULT(dev_priv->dev))
1354 void intel_ddi_pll_init(struct drm_device *dev)
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 uint32_t val = I915_READ(LCPLL_CTL);
1359 /* The LCPLL register should be turned on by the BIOS. For now let's
1360 * just check its state and print errors in case something is wrong.
1361 * Don't even try to turn it on.
1364 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1365 intel_ddi_get_cdclk_freq(dev_priv));
1367 if (val & LCPLL_CD_SOURCE_FCLK)
1368 DRM_ERROR("CDCLK source is not LCPLL\n");
1370 if (val & LCPLL_PLL_DISABLE)
1371 DRM_ERROR("LCPLL is disabled\n");
1374 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1376 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1377 struct intel_dp *intel_dp = &intel_dig_port->dp;
1378 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1379 enum port port = intel_dig_port->port;
1383 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1384 val = I915_READ(DDI_BUF_CTL(port));
1385 if (val & DDI_BUF_CTL_ENABLE) {
1386 val &= ~DDI_BUF_CTL_ENABLE;
1387 I915_WRITE(DDI_BUF_CTL(port), val);
1391 val = I915_READ(DP_TP_CTL(port));
1392 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1393 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1394 I915_WRITE(DP_TP_CTL(port), val);
1395 POSTING_READ(DP_TP_CTL(port));
1398 intel_wait_ddi_buf_idle(dev_priv, port);
1401 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1402 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1403 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1404 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1405 I915_WRITE(DP_TP_CTL(port), val);
1406 POSTING_READ(DP_TP_CTL(port));
1408 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1409 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1410 POSTING_READ(DDI_BUF_CTL(port));
1415 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1417 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1418 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1421 intel_ddi_post_disable(intel_encoder);
1423 val = I915_READ(_FDI_RXA_CTL);
1424 val &= ~FDI_RX_ENABLE;
1425 I915_WRITE(_FDI_RXA_CTL, val);
1427 val = I915_READ(_FDI_RXA_MISC);
1428 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1429 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1430 I915_WRITE(_FDI_RXA_MISC, val);
1432 val = I915_READ(_FDI_RXA_CTL);
1434 I915_WRITE(_FDI_RXA_CTL, val);
1436 val = I915_READ(_FDI_RXA_CTL);
1437 val &= ~FDI_RX_PLL_ENABLE;
1438 I915_WRITE(_FDI_RXA_CTL, val);
1441 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1443 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1444 int type = intel_encoder->type;
1446 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1447 intel_dp_check_link_status(intel_dp);
1450 static void intel_ddi_destroy(struct drm_encoder *encoder)
1452 /* HDMI has nothing special to destroy, so we can go with this. */
1453 intel_dp_encoder_destroy(encoder);
1456 static bool intel_ddi_mode_fixup(struct drm_encoder *encoder,
1457 const struct drm_display_mode *mode,
1458 struct drm_display_mode *adjusted_mode)
1460 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1461 int type = intel_encoder->type;
1463 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n");
1465 if (type == INTEL_OUTPUT_HDMI)
1466 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode);
1468 return intel_dp_mode_fixup(encoder, mode, adjusted_mode);
1471 static const struct drm_encoder_funcs intel_ddi_funcs = {
1472 .destroy = intel_ddi_destroy,
1475 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1476 .mode_fixup = intel_ddi_mode_fixup,
1477 .mode_set = intel_ddi_mode_set,
1478 .disable = intel_encoder_noop,
1481 void intel_ddi_init(struct drm_device *dev, enum port port)
1483 struct intel_digital_port *intel_dig_port;
1484 struct intel_encoder *intel_encoder;
1485 struct drm_encoder *encoder;
1486 struct intel_connector *hdmi_connector = NULL;
1487 struct intel_connector *dp_connector = NULL;
1489 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1490 if (!intel_dig_port)
1493 dp_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1494 if (!dp_connector) {
1495 kfree(intel_dig_port);
1499 if (port != PORT_A) {
1500 hdmi_connector = kzalloc(sizeof(struct intel_connector),
1502 if (!hdmi_connector) {
1503 kfree(dp_connector);
1504 kfree(intel_dig_port);
1509 intel_encoder = &intel_dig_port->base;
1510 encoder = &intel_encoder->base;
1512 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1513 DRM_MODE_ENCODER_TMDS);
1514 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1516 intel_encoder->enable = intel_enable_ddi;
1517 intel_encoder->pre_enable = intel_ddi_pre_enable;
1518 intel_encoder->disable = intel_disable_ddi;
1519 intel_encoder->post_disable = intel_ddi_post_disable;
1520 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1522 intel_dig_port->port = port;
1524 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port);
1526 intel_dig_port->hdmi.sdvox_reg = 0;
1527 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1529 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1530 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1531 intel_encoder->cloneable = false;
1532 intel_encoder->hot_plug = intel_ddi_hot_plug;
1535 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1536 intel_dp_init_connector(intel_dig_port, dp_connector);