2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
36 static u32 calc_residency(struct drm_device *dev, const u32 reg)
38 struct drm_i915_private *dev_priv = dev->dev_private;
39 u64 raw_time; /* 32b value may overflow during fixed point math */
41 if (!intel_enable_rc6(dev))
44 raw_time = I915_READ(reg) * 128ULL;
45 return DIV_ROUND_UP_ULL(raw_time, 100000);
49 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
51 struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
52 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
56 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
58 struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
59 u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
60 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
64 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
66 struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
67 u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
68 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
72 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
74 struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
75 u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
76 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
79 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
80 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
81 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
82 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
84 static struct attribute *rc6_attrs[] = {
85 &dev_attr_rc6_enable.attr,
86 &dev_attr_rc6_residency_ms.attr,
87 &dev_attr_rc6p_residency_ms.attr,
88 &dev_attr_rc6pp_residency_ms.attr,
92 static struct attribute_group rc6_attr_group = {
93 .name = power_group_name,
98 static int l3_access_valid(struct drm_device *dev, loff_t offset)
100 if (!HAS_L3_GPU_CACHE(dev))
106 if (offset >= GEN7_L3LOG_SIZE)
113 i915_l3_read(struct file *filp, struct kobject *kobj,
114 struct bin_attribute *attr, char *buf,
115 loff_t offset, size_t count)
117 struct device *dev = container_of(kobj, struct device, kobj);
118 struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
119 struct drm_device *drm_dev = dminor->dev;
120 struct drm_i915_private *dev_priv = drm_dev->dev_private;
121 int slice = (int)(uintptr_t)attr->private;
124 count = round_down(count, 4);
126 ret = l3_access_valid(drm_dev, offset);
130 count = min_t(int, GEN7_L3LOG_SIZE-offset, count);
132 ret = i915_mutex_lock_interruptible(drm_dev);
136 if (dev_priv->l3_parity.remap_info[slice])
138 dev_priv->l3_parity.remap_info[slice] + (offset/4),
141 memset(buf, 0, count);
143 mutex_unlock(&drm_dev->struct_mutex);
149 i915_l3_write(struct file *filp, struct kobject *kobj,
150 struct bin_attribute *attr, char *buf,
151 loff_t offset, size_t count)
153 struct device *dev = container_of(kobj, struct device, kobj);
154 struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
155 struct drm_device *drm_dev = dminor->dev;
156 struct drm_i915_private *dev_priv = drm_dev->dev_private;
157 struct i915_hw_context *ctx;
158 u32 *temp = NULL; /* Just here to make handling failures easy */
159 int slice = (int)(uintptr_t)attr->private;
162 ret = l3_access_valid(drm_dev, offset);
166 if (dev_priv->hw_contexts_disabled)
169 ret = i915_mutex_lock_interruptible(drm_dev);
173 if (!dev_priv->l3_parity.remap_info[slice]) {
174 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
176 mutex_unlock(&drm_dev->struct_mutex);
181 ret = i915_gpu_idle(drm_dev);
184 mutex_unlock(&drm_dev->struct_mutex);
188 /* TODO: Ideally we really want a GPU reset here to make sure errors
189 * aren't propagated. Since I cannot find a stable way to reset the GPU
190 * at this point it is left as a TODO.
193 dev_priv->l3_parity.remap_info[slice] = temp;
195 memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
197 /* NB: We defer the remapping until we switch to the context */
198 list_for_each_entry(ctx, &dev_priv->context_list, link)
199 ctx->remap_slice |= (1<<slice);
201 mutex_unlock(&drm_dev->struct_mutex);
206 static struct bin_attribute dpf_attrs = {
207 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
208 .size = GEN7_L3LOG_SIZE,
209 .read = i915_l3_read,
210 .write = i915_l3_write,
215 static struct bin_attribute dpf_attrs_1 = {
216 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
217 .size = GEN7_L3LOG_SIZE,
218 .read = i915_l3_read,
219 .write = i915_l3_write,
224 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
225 struct device_attribute *attr, char *buf)
227 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
228 struct drm_device *dev = minor->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
232 mutex_lock(&dev_priv->rps.hw_lock);
233 if (IS_VALLEYVIEW(dev_priv->dev)) {
235 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
236 ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
238 ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
240 mutex_unlock(&dev_priv->rps.hw_lock);
242 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
245 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
246 struct device_attribute *attr, char *buf)
248 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
249 struct drm_device *dev = minor->dev;
250 struct drm_i915_private *dev_priv = dev->dev_private;
252 return snprintf(buf, PAGE_SIZE, "%d\n",
253 vlv_gpu_freq(dev_priv->mem_freq,
254 dev_priv->rps.rpe_delay));
257 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
259 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
260 struct drm_device *dev = minor->dev;
261 struct drm_i915_private *dev_priv = dev->dev_private;
264 mutex_lock(&dev_priv->rps.hw_lock);
265 if (IS_VALLEYVIEW(dev_priv->dev))
266 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
268 ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
269 mutex_unlock(&dev_priv->rps.hw_lock);
271 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
274 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
275 struct device_attribute *attr,
276 const char *buf, size_t count)
278 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
279 struct drm_device *dev = minor->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
284 ret = kstrtou32(buf, 0, &val);
288 mutex_lock(&dev_priv->rps.hw_lock);
290 if (IS_VALLEYVIEW(dev_priv->dev)) {
291 val = vlv_freq_opcode(dev_priv->mem_freq, val);
293 hw_max = valleyview_rps_max_freq(dev_priv);
294 hw_min = valleyview_rps_min_freq(dev_priv);
297 val /= GT_FREQUENCY_MULTIPLIER;
299 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
300 hw_max = dev_priv->rps.hw_max;
301 non_oc_max = (rp_state_cap & 0xff);
302 hw_min = ((rp_state_cap & 0xff0000) >> 16);
305 if (val < hw_min || val > hw_max ||
306 val < dev_priv->rps.min_delay) {
307 mutex_unlock(&dev_priv->rps.hw_lock);
311 if (val > non_oc_max)
312 DRM_DEBUG("User requested overclocking to %d\n",
313 val * GT_FREQUENCY_MULTIPLIER);
315 if (dev_priv->rps.cur_delay > val) {
316 if (IS_VALLEYVIEW(dev_priv->dev))
317 valleyview_set_rps(dev_priv->dev, val);
319 gen6_set_rps(dev_priv->dev, val);
322 dev_priv->rps.max_delay = val;
324 mutex_unlock(&dev_priv->rps.hw_lock);
329 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
331 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
332 struct drm_device *dev = minor->dev;
333 struct drm_i915_private *dev_priv = dev->dev_private;
336 mutex_lock(&dev_priv->rps.hw_lock);
337 if (IS_VALLEYVIEW(dev_priv->dev))
338 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
340 ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
341 mutex_unlock(&dev_priv->rps.hw_lock);
343 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
346 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
347 struct device_attribute *attr,
348 const char *buf, size_t count)
350 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
351 struct drm_device *dev = minor->dev;
352 struct drm_i915_private *dev_priv = dev->dev_private;
353 u32 val, rp_state_cap, hw_max, hw_min;
356 ret = kstrtou32(buf, 0, &val);
360 mutex_lock(&dev_priv->rps.hw_lock);
362 if (IS_VALLEYVIEW(dev)) {
363 val = vlv_freq_opcode(dev_priv->mem_freq, val);
365 hw_max = valleyview_rps_max_freq(dev_priv);
366 hw_min = valleyview_rps_min_freq(dev_priv);
368 val /= GT_FREQUENCY_MULTIPLIER;
370 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
371 hw_max = dev_priv->rps.hw_max;
372 hw_min = ((rp_state_cap & 0xff0000) >> 16);
375 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
376 mutex_unlock(&dev_priv->rps.hw_lock);
380 if (dev_priv->rps.cur_delay < val) {
381 if (IS_VALLEYVIEW(dev))
382 valleyview_set_rps(dev, val);
384 gen6_set_rps(dev_priv->dev, val);
387 dev_priv->rps.min_delay = val;
389 mutex_unlock(&dev_priv->rps.hw_lock);
395 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
396 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
397 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
399 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
401 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
402 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
403 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
404 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
406 /* For now we have a static number of RP states */
407 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
409 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
410 struct drm_device *dev = minor->dev;
411 struct drm_i915_private *dev_priv = dev->dev_private;
412 u32 val, rp_state_cap;
415 ret = mutex_lock_interruptible(&dev->struct_mutex);
418 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
419 mutex_unlock(&dev->struct_mutex);
421 if (attr == &dev_attr_gt_RP0_freq_mhz) {
422 val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
423 } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
424 val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
425 } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
426 val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
430 return snprintf(buf, PAGE_SIZE, "%d\n", val);
433 static const struct attribute *gen6_attrs[] = {
434 &dev_attr_gt_cur_freq_mhz.attr,
435 &dev_attr_gt_max_freq_mhz.attr,
436 &dev_attr_gt_min_freq_mhz.attr,
437 &dev_attr_gt_RP0_freq_mhz.attr,
438 &dev_attr_gt_RP1_freq_mhz.attr,
439 &dev_attr_gt_RPn_freq_mhz.attr,
443 static const struct attribute *vlv_attrs[] = {
444 &dev_attr_gt_cur_freq_mhz.attr,
445 &dev_attr_gt_max_freq_mhz.attr,
446 &dev_attr_gt_min_freq_mhz.attr,
447 &dev_attr_vlv_rpe_freq_mhz.attr,
451 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
452 struct bin_attribute *attr, char *buf,
453 loff_t off, size_t count)
456 struct device *kdev = container_of(kobj, struct device, kobj);
457 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
458 struct drm_device *dev = minor->dev;
459 struct i915_error_state_file_priv error_priv;
460 struct drm_i915_error_state_buf error_str;
461 ssize_t ret_count = 0;
464 memset(&error_priv, 0, sizeof(error_priv));
466 ret = i915_error_state_buf_init(&error_str, count, off);
470 error_priv.dev = dev;
471 i915_error_state_get(dev, &error_priv);
473 ret = i915_error_state_to_str(&error_str, &error_priv);
477 ret_count = count < error_str.bytes ? count : error_str.bytes;
479 memcpy(buf, error_str.buf, ret_count);
481 i915_error_state_put(&error_priv);
482 i915_error_state_buf_release(&error_str);
484 return ret ?: ret_count;
487 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
488 struct bin_attribute *attr, char *buf,
489 loff_t off, size_t count)
491 struct device *kdev = container_of(kobj, struct device, kobj);
492 struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
493 struct drm_device *dev = minor->dev;
496 DRM_DEBUG_DRIVER("Resetting error state\n");
498 ret = mutex_lock_interruptible(&dev->struct_mutex);
502 i915_destroy_error_state(dev);
503 mutex_unlock(&dev->struct_mutex);
508 static struct bin_attribute error_state_attr = {
509 .attr.name = "error",
510 .attr.mode = S_IRUSR | S_IWUSR,
512 .read = error_state_read,
513 .write = error_state_write,
516 void i915_setup_sysfs(struct drm_device *dev)
521 if (INTEL_INFO(dev)->gen >= 6) {
522 ret = sysfs_merge_group(&dev->primary->kdev.kobj,
525 DRM_ERROR("RC6 residency sysfs setup failed\n");
528 if (HAS_L3_GPU_CACHE(dev)) {
529 ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
531 DRM_ERROR("l3 parity sysfs setup failed\n");
533 if (NUM_L3_SLICES(dev) > 1) {
534 ret = device_create_bin_file(&dev->primary->kdev,
537 DRM_ERROR("l3 parity slice 1 setup failed\n");
542 if (IS_VALLEYVIEW(dev))
543 ret = sysfs_create_files(&dev->primary->kdev.kobj, vlv_attrs);
544 else if (INTEL_INFO(dev)->gen >= 6)
545 ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
547 DRM_ERROR("RPS sysfs setup failed\n");
549 ret = sysfs_create_bin_file(&dev->primary->kdev.kobj,
552 DRM_ERROR("error_state sysfs setup failed\n");
555 void i915_teardown_sysfs(struct drm_device *dev)
557 sysfs_remove_bin_file(&dev->primary->kdev.kobj, &error_state_attr);
558 if (IS_VALLEYVIEW(dev))
559 sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
561 sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
562 device_remove_bin_file(&dev->primary->kdev, &dpf_attrs_1);
563 device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
565 sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);