Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_sysfs.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *
  26  */
  27
  28 #include <linux/device.h>
  29 #include <linux/module.h>
  30 #include <linux/stat.h>
  31 #include <linux/sysfs.h>
  32 #include "intel_drv.h"
  33 #include "i915_drv.h"
  34
  35 #ifdef CONFIG_PM
  36 static u32 calc_residency(struct drm_device *dev, const u32 reg)
  37 {
  38         struct drm_i915_private *dev_priv = dev->dev_private;
  39         u64 raw_time; /* 32b value may overflow during fixed point math */
  40
  41         if (!intel_enable_rc6(dev))
  42                 return 0;
  43
  44         raw_time = I915_READ(reg) * 128ULL;
  45         return DIV_ROUND_UP_ULL(raw_time, 100000);
  46 }
  47
  48 static ssize_t
  49 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
  50 {
  51         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  52         return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
  53 }
  54
  55 static ssize_t
  56 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  57 {
  58         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  59         u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
  60         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
  61 }
  62
  63 static ssize_t
  64 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  65 {
  66         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  67         u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
  68         return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
  69 }
  70
  71 static ssize_t
  72 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  73 {
  74         struct drm_minor *dminor = container_of(kdev, struct drm_minor, kdev);
  75         u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
  76         return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
  77 }
  78
  79 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
  80 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
  81 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
  82 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
  83
  84 static struct attribute *rc6_attrs[] = {
  85         &dev_attr_rc6_enable.attr,
  86         &dev_attr_rc6_residency_ms.attr,
  87         &dev_attr_rc6p_residency_ms.attr,
  88         &dev_attr_rc6pp_residency_ms.attr,
  89         NULL
  90 };
  91
  92 static struct attribute_group rc6_attr_group = {
  93         .name = power_group_name,
  94         .attrs =  rc6_attrs
  95 };
  96 #endif
  97
  98 static int l3_access_valid(struct drm_device *dev, loff_t offset)
  99 {
 100         if (!HAS_L3_GPU_CACHE(dev))
 101                 return -EPERM;
 102
 103         if (offset % 4 != 0)
 104                 return -EINVAL;
 105
 106         if (offset >= GEN7_L3LOG_SIZE)
 107                 return -ENXIO;
 108
 109         return 0;
 110 }
 111
 112 static ssize_t
 113 i915_l3_read(struct file *filp, struct kobject *kobj,
 114              struct bin_attribute *attr, char *buf,
 115              loff_t offset, size_t count)
 116 {
 117         struct device *dev = container_of(kobj, struct device, kobj);
 118         struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
 119         struct drm_device *drm_dev = dminor->dev;
 120         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 121         uint32_t misccpctl;
 122         int i, ret;
 123
 124         count = round_down(count, 4);
 125
 126         ret = l3_access_valid(drm_dev, offset);
 127         if (ret)
 128                 return ret;
 129
 130         ret = i915_mutex_lock_interruptible(drm_dev);
 131         if (ret)
 132                 return ret;
 133
 134         misccpctl = I915_READ(GEN7_MISCCPCTL);
 135         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 136
 137         for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
 138                 *((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);
 139
 140         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 141
 142         mutex_unlock(&drm_dev->struct_mutex);
 143
 144         return i - offset;
 145 }
 146
 147 static ssize_t
 148 i915_l3_write(struct file *filp, struct kobject *kobj,
 149               struct bin_attribute *attr, char *buf,
 150               loff_t offset, size_t count)
 151 {
 152         struct device *dev = container_of(kobj, struct device, kobj);
 153         struct drm_minor *dminor = container_of(dev, struct drm_minor, kdev);
 154         struct drm_device *drm_dev = dminor->dev;
 155         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 156         u32 *temp = NULL; /* Just here to make handling failures easy */
 157         int ret;
 158
 159         ret = l3_access_valid(drm_dev, offset);
 160         if (ret)
 161                 return ret;
 162
 163         ret = i915_mutex_lock_interruptible(drm_dev);
 164         if (ret)
 165                 return ret;
 166
 167         if (!dev_priv->l3_parity.remap_info) {
 168                 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
 169                 if (!temp) {
 170                         mutex_unlock(&drm_dev->struct_mutex);
 171                         return -ENOMEM;
 172                 }
 173         }
 174
 175         ret = i915_gpu_idle(drm_dev);
 176         if (ret) {
 177                 kfree(temp);
 178                 mutex_unlock(&drm_dev->struct_mutex);
 179                 return ret;
 180         }
 181
 182         /* TODO: Ideally we really want a GPU reset here to make sure errors
 183          * aren't propagated. Since I cannot find a stable way to reset the GPU
 184          * at this point it is left as a TODO.
 185         */
 186         if (temp)
 187                 dev_priv->l3_parity.remap_info = temp;
 188
 189         memcpy(dev_priv->l3_parity.remap_info + (offset/4),
 190                buf + (offset/4),
 191                count);
 192
 193         i915_gem_l3_remap(drm_dev);
 194
 195         mutex_unlock(&drm_dev->struct_mutex);
 196
 197         return count;
 198 }
 199
 200 static struct bin_attribute dpf_attrs = {
 201         .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
 202         .size = GEN7_L3LOG_SIZE,
 203         .read = i915_l3_read,
 204         .write = i915_l3_write,
 205         .mmap = NULL
 206 };
 207
 208 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 209                                     struct device_attribute *attr, char *buf)
 210 {
 211         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 212         struct drm_device *dev = minor->dev;
 213         struct drm_i915_private *dev_priv = dev->dev_private;
 214         int ret;
 215
 216         mutex_lock(&dev_priv->rps.hw_lock);
 217         if (IS_VALLEYVIEW(dev_priv->dev)) {
 218                 u32 freq;
 219                 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 220                 ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
 221         } else {
 222                 ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
 223         }
 224         mutex_unlock(&dev_priv->rps.hw_lock);
 225
 226         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 227 }
 228
 229 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 230                                      struct device_attribute *attr, char *buf)
 231 {
 232         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 233         struct drm_device *dev = minor->dev;
 234         struct drm_i915_private *dev_priv = dev->dev_private;
 235
 236         return snprintf(buf, PAGE_SIZE, "%d\n",
 237                         vlv_gpu_freq(dev_priv->mem_freq,
 238                                      dev_priv->rps.rpe_delay));
 239 }
 240
 241 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 242 {
 243         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 244         struct drm_device *dev = minor->dev;
 245         struct drm_i915_private *dev_priv = dev->dev_private;
 246         int ret;
 247
 248         mutex_lock(&dev_priv->rps.hw_lock);
 249         if (IS_VALLEYVIEW(dev_priv->dev))
 250                 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
 251         else
 252                 ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
 253         mutex_unlock(&dev_priv->rps.hw_lock);
 254
 255         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 256 }
 257
 258 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 259                                      struct device_attribute *attr,
 260                                      const char *buf, size_t count)
 261 {
 262         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 263         struct drm_device *dev = minor->dev;
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
 266         ssize_t ret;
 267
 268         ret = kstrtou32(buf, 0, &val);
 269         if (ret)
 270                 return ret;
 271
 272         mutex_lock(&dev_priv->rps.hw_lock);
 273
 274         if (IS_VALLEYVIEW(dev_priv->dev)) {
 275                 val = vlv_freq_opcode(dev_priv->mem_freq, val);
 276
 277                 hw_max = valleyview_rps_max_freq(dev_priv);
 278                 hw_min = valleyview_rps_min_freq(dev_priv);
 279                 non_oc_max = hw_max;
 280         } else {
 281                 val /= GT_FREQUENCY_MULTIPLIER;
 282
 283                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 284                 hw_max = dev_priv->rps.hw_max;
 285                 non_oc_max = (rp_state_cap & 0xff);
 286                 hw_min = ((rp_state_cap & 0xff0000) >> 16);
 287         }
 288
 289         if (val < hw_min || val > hw_max ||
 290             val < dev_priv->rps.min_delay) {
 291                 mutex_unlock(&dev_priv->rps.hw_lock);
 292                 return -EINVAL;
 293         }
 294
 295         if (val > non_oc_max)
 296                 DRM_DEBUG("User requested overclocking to %d\n",
 297                           val * GT_FREQUENCY_MULTIPLIER);
 298
 299         if (dev_priv->rps.cur_delay > val) {
 300                 if (IS_VALLEYVIEW(dev_priv->dev))
 301                         valleyview_set_rps(dev_priv->dev, val);
 302                 else
 303                         gen6_set_rps(dev_priv->dev, val);
 304         }
 305
 306         dev_priv->rps.max_delay = val;
 307
 308         mutex_unlock(&dev_priv->rps.hw_lock);
 309
 310         return count;
 311 }
 312
 313 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 314 {
 315         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 316         struct drm_device *dev = minor->dev;
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318         int ret;
 319
 320         mutex_lock(&dev_priv->rps.hw_lock);
 321         if (IS_VALLEYVIEW(dev_priv->dev))
 322                 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
 323         else
 324                 ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
 325         mutex_unlock(&dev_priv->rps.hw_lock);
 326
 327         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 328 }
 329
 330 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 331                                      struct device_attribute *attr,
 332                                      const char *buf, size_t count)
 333 {
 334         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 335         struct drm_device *dev = minor->dev;
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         u32 val, rp_state_cap, hw_max, hw_min;
 338         ssize_t ret;
 339
 340         ret = kstrtou32(buf, 0, &val);
 341         if (ret)
 342                 return ret;
 343
 344         mutex_lock(&dev_priv->rps.hw_lock);
 345
 346         if (IS_VALLEYVIEW(dev)) {
 347                 val = vlv_freq_opcode(dev_priv->mem_freq, val);
 348
 349                 hw_max = valleyview_rps_max_freq(dev_priv);
 350                 hw_min = valleyview_rps_min_freq(dev_priv);
 351         } else {
 352                 val /= GT_FREQUENCY_MULTIPLIER;
 353
 354                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 355                 hw_max = dev_priv->rps.hw_max;
 356                 hw_min = ((rp_state_cap & 0xff0000) >> 16);
 357         }
 358
 359         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
 360                 mutex_unlock(&dev_priv->rps.hw_lock);
 361                 return -EINVAL;
 362         }
 363
 364         if (dev_priv->rps.cur_delay < val) {
 365                 if (IS_VALLEYVIEW(dev))
 366                         valleyview_set_rps(dev, val);
 367                 else
 368                         gen6_set_rps(dev_priv->dev, val);
 369         }
 370
 371         dev_priv->rps.min_delay = val;
 372
 373         mutex_unlock(&dev_priv->rps.hw_lock);
 374
 375         return count;
 376
 377 }
 378
 379 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
 380 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
 381 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
 382
 383 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
 384
 385 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
 386 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 387 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 388 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 389
 390 /* For now we have a static number of RP states */
 391 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 392 {
 393         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 394         struct drm_device *dev = minor->dev;
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396         u32 val, rp_state_cap;
 397         ssize_t ret;
 398
 399         ret = mutex_lock_interruptible(&dev->struct_mutex);
 400         if (ret)
 401                 return ret;
 402         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 403         mutex_unlock(&dev->struct_mutex);
 404
 405         if (attr == &dev_attr_gt_RP0_freq_mhz) {
 406                 val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
 407         } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
 408                 val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
 409         } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
 410                 val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
 411         } else {
 412                 BUG();
 413         }
 414         return snprintf(buf, PAGE_SIZE, "%d\n", val);
 415 }
 416
 417 static const struct attribute *gen6_attrs[] = {
 418         &dev_attr_gt_cur_freq_mhz.attr,
 419         &dev_attr_gt_max_freq_mhz.attr,
 420         &dev_attr_gt_min_freq_mhz.attr,
 421         &dev_attr_gt_RP0_freq_mhz.attr,
 422         &dev_attr_gt_RP1_freq_mhz.attr,
 423         &dev_attr_gt_RPn_freq_mhz.attr,
 424         NULL,
 425 };
 426
 427 static const struct attribute *vlv_attrs[] = {
 428         &dev_attr_gt_cur_freq_mhz.attr,
 429         &dev_attr_gt_max_freq_mhz.attr,
 430         &dev_attr_gt_min_freq_mhz.attr,
 431         &dev_attr_vlv_rpe_freq_mhz.attr,
 432         NULL,
 433 };
 434
 435 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 436                                 struct bin_attribute *attr, char *buf,
 437                                 loff_t off, size_t count)
 438 {
 439
 440         struct device *kdev = container_of(kobj, struct device, kobj);
 441         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 442         struct drm_device *dev = minor->dev;
 443         struct i915_error_state_file_priv error_priv;
 444         struct drm_i915_error_state_buf error_str;
 445         ssize_t ret_count = 0;
 446         int ret;
 447
 448         memset(&error_priv, 0, sizeof(error_priv));
 449
 450         ret = i915_error_state_buf_init(&error_str, count, off);
 451         if (ret)
 452                 return ret;
 453
 454         error_priv.dev = dev;
 455         i915_error_state_get(dev, &error_priv);
 456
 457         ret = i915_error_state_to_str(&error_str, &error_priv);
 458         if (ret)
 459                 goto out;
 460
 461         ret_count = count < error_str.bytes ? count : error_str.bytes;
 462
 463         memcpy(buf, error_str.buf, ret_count);
 464 out:
 465         i915_error_state_put(&error_priv);
 466         i915_error_state_buf_release(&error_str);
 467
 468         return ret ?: ret_count;
 469 }
 470
 471 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
 472                                  struct bin_attribute *attr, char *buf,
 473                                  loff_t off, size_t count)
 474 {
 475         struct device *kdev = container_of(kobj, struct device, kobj);
 476         struct drm_minor *minor = container_of(kdev, struct drm_minor, kdev);
 477         struct drm_device *dev = minor->dev;
 478         int ret;
 479
 480         DRM_DEBUG_DRIVER("Resetting error state\n");
 481
 482         ret = mutex_lock_interruptible(&dev->struct_mutex);
 483         if (ret)
 484                 return ret;
 485
 486         i915_destroy_error_state(dev);
 487         mutex_unlock(&dev->struct_mutex);
 488
 489         return count;
 490 }
 491
 492 static struct bin_attribute error_state_attr = {
 493         .attr.name = "error",
 494         .attr.mode = S_IRUSR | S_IWUSR,
 495         .size = 0,
 496         .read = error_state_read,
 497         .write = error_state_write,
 498 };
 499
 500 void i915_setup_sysfs(struct drm_device *dev)
 501 {
 502         int ret;
 503
 504 #ifdef CONFIG_PM
 505         if (INTEL_INFO(dev)->gen >= 6) {
 506                 ret = sysfs_merge_group(&dev->primary->kdev.kobj,
 507                                         &rc6_attr_group);
 508                 if (ret)
 509                         DRM_ERROR("RC6 residency sysfs setup failed\n");
 510         }
 511 #endif
 512         if (HAS_L3_GPU_CACHE(dev)) {
 513                 ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
 514                 if (ret)
 515                         DRM_ERROR("l3 parity sysfs setup failed\n");
 516         }
 517
 518         ret = 0;
 519         if (IS_VALLEYVIEW(dev))
 520                 ret = sysfs_create_files(&dev->primary->kdev.kobj, vlv_attrs);
 521         else if (INTEL_INFO(dev)->gen >= 6)
 522                 ret = sysfs_create_files(&dev->primary->kdev.kobj, gen6_attrs);
 523         if (ret)
 524                 DRM_ERROR("RPS sysfs setup failed\n");
 525
 526         ret = sysfs_create_bin_file(&dev->primary->kdev.kobj,
 527                                     &error_state_attr);
 528         if (ret)
 529                 DRM_ERROR("error_state sysfs setup failed\n");
 530 }
 531
 532 void i915_teardown_sysfs(struct drm_device *dev)
 533 {
 534         sysfs_remove_bin_file(&dev->primary->kdev.kobj, &error_state_attr);
 535         if (IS_VALLEYVIEW(dev))
 536                 sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
 537         else
 538                 sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
 539         device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
 540 #ifdef CONFIG_PM
 541         sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
 542 #endif
 543 }