2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
28 #include <linux/device.h>
29 #include <linux/module.h>
30 #include <linux/stat.h>
31 #include <linux/sysfs.h>
32 #include "intel_drv.h"
35 #define dev_to_drm_minor(d) dev_get_drvdata((d))
38 static u32 calc_residency(struct drm_device *dev, const u32 reg)
40 struct drm_i915_private *dev_priv = dev->dev_private;
41 u64 raw_time; /* 32b value may overflow during fixed point math */
42 u64 units = 128ULL, div = 100000ULL, bias = 100ULL;
44 if (!intel_enable_rc6(dev))
47 /* On VLV, residency time is in CZ units rather than 1.28us */
48 if (IS_VALLEYVIEW(dev)) {
51 clkctl2 = I915_READ(VLV_CLK_CTL2) >>
52 CLK_CTL2_CZCOUNT_30NS_SHIFT;
54 WARN(!clkctl2, "bogus CZ count value");
57 units = DIV_ROUND_UP_ULL(30ULL * bias, (u64)clkctl2);
58 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
61 div = 1000000ULL * bias;
64 raw_time = I915_READ(reg) * units;
65 return DIV_ROUND_UP_ULL(raw_time, div);
69 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
71 struct drm_minor *dminor = dev_to_drm_minor(kdev);
72 return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6(dminor->dev));
76 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
78 struct drm_minor *dminor = dev_get_drvdata(kdev);
79 u32 rc6_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6);
80 return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
84 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
86 struct drm_minor *dminor = dev_to_drm_minor(kdev);
87 u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
88 if (IS_VALLEYVIEW(dminor->dev))
90 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
94 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
96 struct drm_minor *dminor = dev_to_drm_minor(kdev);
97 u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
98 if (IS_VALLEYVIEW(dminor->dev))
100 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
103 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
104 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
105 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
106 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
108 static struct attribute *rc6_attrs[] = {
109 &dev_attr_rc6_enable.attr,
110 &dev_attr_rc6_residency_ms.attr,
111 &dev_attr_rc6p_residency_ms.attr,
112 &dev_attr_rc6pp_residency_ms.attr,
116 static struct attribute_group rc6_attr_group = {
117 .name = power_group_name,
122 static int l3_access_valid(struct drm_device *dev, loff_t offset)
124 if (!HAS_L3_DPF(dev))
130 if (offset >= GEN7_L3LOG_SIZE)
137 i915_l3_read(struct file *filp, struct kobject *kobj,
138 struct bin_attribute *attr, char *buf,
139 loff_t offset, size_t count)
141 struct device *dev = container_of(kobj, struct device, kobj);
142 struct drm_minor *dminor = dev_to_drm_minor(dev);
143 struct drm_device *drm_dev = dminor->dev;
144 struct drm_i915_private *dev_priv = drm_dev->dev_private;
145 int slice = (int)(uintptr_t)attr->private;
148 count = round_down(count, 4);
150 ret = l3_access_valid(drm_dev, offset);
154 count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
156 ret = i915_mutex_lock_interruptible(drm_dev);
160 if (dev_priv->l3_parity.remap_info[slice])
162 dev_priv->l3_parity.remap_info[slice] + (offset/4),
165 memset(buf, 0, count);
167 mutex_unlock(&drm_dev->struct_mutex);
173 i915_l3_write(struct file *filp, struct kobject *kobj,
174 struct bin_attribute *attr, char *buf,
175 loff_t offset, size_t count)
177 struct device *dev = container_of(kobj, struct device, kobj);
178 struct drm_minor *dminor = dev_to_drm_minor(dev);
179 struct drm_device *drm_dev = dminor->dev;
180 struct drm_i915_private *dev_priv = drm_dev->dev_private;
181 struct i915_hw_context *ctx;
182 u32 *temp = NULL; /* Just here to make handling failures easy */
183 int slice = (int)(uintptr_t)attr->private;
186 ret = l3_access_valid(drm_dev, offset);
190 if (dev_priv->hw_contexts_disabled)
193 ret = i915_mutex_lock_interruptible(drm_dev);
197 if (!dev_priv->l3_parity.remap_info[slice]) {
198 temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
200 mutex_unlock(&drm_dev->struct_mutex);
205 ret = i915_gpu_idle(drm_dev);
208 mutex_unlock(&drm_dev->struct_mutex);
212 /* TODO: Ideally we really want a GPU reset here to make sure errors
213 * aren't propagated. Since I cannot find a stable way to reset the GPU
214 * at this point it is left as a TODO.
217 dev_priv->l3_parity.remap_info[slice] = temp;
219 memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
221 /* NB: We defer the remapping until we switch to the context */
222 list_for_each_entry(ctx, &dev_priv->context_list, link)
223 ctx->remap_slice |= (1<<slice);
225 mutex_unlock(&drm_dev->struct_mutex);
230 static struct bin_attribute dpf_attrs = {
231 .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
232 .size = GEN7_L3LOG_SIZE,
233 .read = i915_l3_read,
234 .write = i915_l3_write,
239 static struct bin_attribute dpf_attrs_1 = {
240 .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
241 .size = GEN7_L3LOG_SIZE,
242 .read = i915_l3_read,
243 .write = i915_l3_write,
248 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
249 struct device_attribute *attr, char *buf)
251 struct drm_minor *minor = dev_to_drm_minor(kdev);
252 struct drm_device *dev = minor->dev;
253 struct drm_i915_private *dev_priv = dev->dev_private;
256 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
258 mutex_lock(&dev_priv->rps.hw_lock);
259 if (IS_VALLEYVIEW(dev_priv->dev)) {
261 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
262 ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
264 ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
266 mutex_unlock(&dev_priv->rps.hw_lock);
268 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
271 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
272 struct device_attribute *attr, char *buf)
274 struct drm_minor *minor = dev_to_drm_minor(kdev);
275 struct drm_device *dev = minor->dev;
276 struct drm_i915_private *dev_priv = dev->dev_private;
278 return snprintf(buf, PAGE_SIZE, "%d\n",
279 vlv_gpu_freq(dev_priv->mem_freq,
280 dev_priv->rps.rpe_delay));
283 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
285 struct drm_minor *minor = dev_to_drm_minor(kdev);
286 struct drm_device *dev = minor->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
290 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
292 mutex_lock(&dev_priv->rps.hw_lock);
293 if (IS_VALLEYVIEW(dev_priv->dev))
294 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
296 ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
297 mutex_unlock(&dev_priv->rps.hw_lock);
299 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
302 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
303 struct device_attribute *attr,
304 const char *buf, size_t count)
306 struct drm_minor *minor = dev_to_drm_minor(kdev);
307 struct drm_device *dev = minor->dev;
308 struct drm_i915_private *dev_priv = dev->dev_private;
309 u32 val, rp_state_cap, hw_max, hw_min, non_oc_max;
312 ret = kstrtou32(buf, 0, &val);
316 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
318 mutex_lock(&dev_priv->rps.hw_lock);
320 if (IS_VALLEYVIEW(dev_priv->dev)) {
321 val = vlv_freq_opcode(dev_priv->mem_freq, val);
323 hw_max = valleyview_rps_max_freq(dev_priv);
324 hw_min = valleyview_rps_min_freq(dev_priv);
327 val /= GT_FREQUENCY_MULTIPLIER;
329 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
330 hw_max = dev_priv->rps.hw_max;
331 non_oc_max = (rp_state_cap & 0xff);
332 hw_min = ((rp_state_cap & 0xff0000) >> 16);
335 if (val < hw_min || val > hw_max ||
336 val < dev_priv->rps.min_delay) {
337 mutex_unlock(&dev_priv->rps.hw_lock);
341 if (val > non_oc_max)
342 DRM_DEBUG("User requested overclocking to %d\n",
343 val * GT_FREQUENCY_MULTIPLIER);
345 if (dev_priv->rps.cur_delay > val) {
346 if (IS_VALLEYVIEW(dev_priv->dev))
347 valleyview_set_rps(dev_priv->dev, val);
349 gen6_set_rps(dev_priv->dev, val);
352 dev_priv->rps.max_delay = val;
354 mutex_unlock(&dev_priv->rps.hw_lock);
359 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
361 struct drm_minor *minor = dev_to_drm_minor(kdev);
362 struct drm_device *dev = minor->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
366 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
368 mutex_lock(&dev_priv->rps.hw_lock);
369 if (IS_VALLEYVIEW(dev_priv->dev))
370 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
372 ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
373 mutex_unlock(&dev_priv->rps.hw_lock);
375 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
378 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
379 struct device_attribute *attr,
380 const char *buf, size_t count)
382 struct drm_minor *minor = dev_to_drm_minor(kdev);
383 struct drm_device *dev = minor->dev;
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 u32 val, rp_state_cap, hw_max, hw_min;
388 ret = kstrtou32(buf, 0, &val);
392 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
394 mutex_lock(&dev_priv->rps.hw_lock);
396 if (IS_VALLEYVIEW(dev)) {
397 val = vlv_freq_opcode(dev_priv->mem_freq, val);
399 hw_max = valleyview_rps_max_freq(dev_priv);
400 hw_min = valleyview_rps_min_freq(dev_priv);
402 val /= GT_FREQUENCY_MULTIPLIER;
404 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
405 hw_max = dev_priv->rps.hw_max;
406 hw_min = ((rp_state_cap & 0xff0000) >> 16);
409 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
410 mutex_unlock(&dev_priv->rps.hw_lock);
414 if (dev_priv->rps.cur_delay < val) {
415 if (IS_VALLEYVIEW(dev))
416 valleyview_set_rps(dev, val);
418 gen6_set_rps(dev_priv->dev, val);
421 dev_priv->rps.min_delay = val;
423 mutex_unlock(&dev_priv->rps.hw_lock);
429 static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
430 static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
431 static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
433 static DEVICE_ATTR(vlv_rpe_freq_mhz, S_IRUGO, vlv_rpe_freq_mhz_show, NULL);
435 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
436 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
437 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
438 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
440 /* For now we have a static number of RP states */
441 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
443 struct drm_minor *minor = dev_to_drm_minor(kdev);
444 struct drm_device *dev = minor->dev;
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 u32 val, rp_state_cap;
449 ret = mutex_lock_interruptible(&dev->struct_mutex);
452 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
453 mutex_unlock(&dev->struct_mutex);
455 if (attr == &dev_attr_gt_RP0_freq_mhz) {
456 val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
457 } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
458 val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
459 } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
460 val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
464 return snprintf(buf, PAGE_SIZE, "%d\n", val);
467 static const struct attribute *gen6_attrs[] = {
468 &dev_attr_gt_cur_freq_mhz.attr,
469 &dev_attr_gt_max_freq_mhz.attr,
470 &dev_attr_gt_min_freq_mhz.attr,
471 &dev_attr_gt_RP0_freq_mhz.attr,
472 &dev_attr_gt_RP1_freq_mhz.attr,
473 &dev_attr_gt_RPn_freq_mhz.attr,
477 static const struct attribute *vlv_attrs[] = {
478 &dev_attr_gt_cur_freq_mhz.attr,
479 &dev_attr_gt_max_freq_mhz.attr,
480 &dev_attr_gt_min_freq_mhz.attr,
481 &dev_attr_vlv_rpe_freq_mhz.attr,
485 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
486 struct bin_attribute *attr, char *buf,
487 loff_t off, size_t count)
490 struct device *kdev = container_of(kobj, struct device, kobj);
491 struct drm_minor *minor = dev_to_drm_minor(kdev);
492 struct drm_device *dev = minor->dev;
493 struct i915_error_state_file_priv error_priv;
494 struct drm_i915_error_state_buf error_str;
495 ssize_t ret_count = 0;
498 memset(&error_priv, 0, sizeof(error_priv));
500 ret = i915_error_state_buf_init(&error_str, count, off);
504 error_priv.dev = dev;
505 i915_error_state_get(dev, &error_priv);
507 ret = i915_error_state_to_str(&error_str, &error_priv);
511 ret_count = count < error_str.bytes ? count : error_str.bytes;
513 memcpy(buf, error_str.buf, ret_count);
515 i915_error_state_put(&error_priv);
516 i915_error_state_buf_release(&error_str);
518 return ret ?: ret_count;
521 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
522 struct bin_attribute *attr, char *buf,
523 loff_t off, size_t count)
525 struct device *kdev = container_of(kobj, struct device, kobj);
526 struct drm_minor *minor = dev_to_drm_minor(kdev);
527 struct drm_device *dev = minor->dev;
530 DRM_DEBUG_DRIVER("Resetting error state\n");
532 ret = mutex_lock_interruptible(&dev->struct_mutex);
536 i915_destroy_error_state(dev);
537 mutex_unlock(&dev->struct_mutex);
542 static struct bin_attribute error_state_attr = {
543 .attr.name = "error",
544 .attr.mode = S_IRUSR | S_IWUSR,
546 .read = error_state_read,
547 .write = error_state_write,
550 void i915_setup_sysfs(struct drm_device *dev)
555 if (INTEL_INFO(dev)->gen >= 6) {
556 ret = sysfs_merge_group(&dev->primary->kdev->kobj,
559 DRM_ERROR("RC6 residency sysfs setup failed\n");
562 if (HAS_L3_DPF(dev)) {
563 ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
565 DRM_ERROR("l3 parity sysfs setup failed\n");
567 if (NUM_L3_SLICES(dev) > 1) {
568 ret = device_create_bin_file(dev->primary->kdev,
571 DRM_ERROR("l3 parity slice 1 setup failed\n");
576 if (IS_VALLEYVIEW(dev))
577 ret = sysfs_create_files(&dev->primary->kdev->kobj, vlv_attrs);
578 else if (INTEL_INFO(dev)->gen >= 6)
579 ret = sysfs_create_files(&dev->primary->kdev->kobj, gen6_attrs);
581 DRM_ERROR("RPS sysfs setup failed\n");
583 ret = sysfs_create_bin_file(&dev->primary->kdev->kobj,
586 DRM_ERROR("error_state sysfs setup failed\n");
589 void i915_teardown_sysfs(struct drm_device *dev)
591 sysfs_remove_bin_file(&dev->primary->kdev->kobj, &error_state_attr);
592 if (IS_VALLEYVIEW(dev))
593 sysfs_remove_files(&dev->primary->kdev->kobj, vlv_attrs);
595 sysfs_remove_files(&dev->primary->kdev->kobj, gen6_attrs);
596 device_remove_bin_file(dev->primary->kdev, &dpf_attrs_1);
597 device_remove_bin_file(dev->primary->kdev, &dpf_attrs);
599 sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group);