Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pc8.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pc8.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pc8.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pc8.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pc8.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pc8.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 236                                                  enum pipe pipe, bool enable)
 237 {
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 240                                           DE_PIPEB_FIFO_UNDERRUN;
 241
 242         if (enable)
 243                 ironlake_enable_display_irq(dev_priv, bit);
 244         else
 245                 ironlake_disable_display_irq(dev_priv, bit);
 246 }
 247
 248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 249                                                   enum pipe pipe, bool enable)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         if (enable) {
 253                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 254
 255                 if (!ivb_can_enable_err_int(dev))
 256                         return;
 257
 258                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 259         } else {
 260                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 261
 262                 /* Change the state _after_ we've read out the current one. */
 263                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 264
 265                 if (!was_enabled &&
 266                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 267                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 268                                       pipe_name(pipe));
 269                 }
 270         }
 271 }
 272
 273 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 274                                                   enum pipe pipe, bool enable)
 275 {
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277
 278         assert_spin_locked(&dev_priv->irq_lock);
 279
 280         if (enable)
 281                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 282         else
 283                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 284         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 285         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 286 }
 287
 288 /**
 289  * ibx_display_interrupt_update - update SDEIMR
 290  * @dev_priv: driver private
 291  * @interrupt_mask: mask of interrupt bits to update
 292  * @enabled_irq_mask: mask of interrupt bits to enable
 293  */
 294 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 295                                          uint32_t interrupt_mask,
 296                                          uint32_t enabled_irq_mask)
 297 {
 298         uint32_t sdeimr = I915_READ(SDEIMR);
 299         sdeimr &= ~interrupt_mask;
 300         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 301
 302         assert_spin_locked(&dev_priv->irq_lock);
 303
 304         if (dev_priv->pc8.irqs_disabled &&
 305             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 306                 WARN(1, "IRQs disabled\n");
 307                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 308                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 309                                                  interrupt_mask);
 310                 return;
 311         }
 312
 313         I915_WRITE(SDEIMR, sdeimr);
 314         POSTING_READ(SDEIMR);
 315 }
 316 #define ibx_enable_display_interrupt(dev_priv, bits) \
 317         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 318 #define ibx_disable_display_interrupt(dev_priv, bits) \
 319         ibx_display_interrupt_update((dev_priv), (bits), 0)
 320
 321 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 322                                             enum transcoder pch_transcoder,
 323                                             bool enable)
 324 {
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 327                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 328
 329         if (enable)
 330                 ibx_enable_display_interrupt(dev_priv, bit);
 331         else
 332                 ibx_disable_display_interrupt(dev_priv, bit);
 333 }
 334
 335 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 336                                             enum transcoder pch_transcoder,
 337                                             bool enable)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340
 341         if (enable) {
 342                 I915_WRITE(SERR_INT,
 343                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 344
 345                 if (!cpt_can_enable_serr_int(dev))
 346                         return;
 347
 348                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 349         } else {
 350                 uint32_t tmp = I915_READ(SERR_INT);
 351                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 352
 353                 /* Change the state _after_ we've read out the current one. */
 354                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 355
 356                 if (!was_enabled &&
 357                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 358                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 359                                       transcoder_name(pch_transcoder));
 360                 }
 361         }
 362 }
 363
 364 /**
 365  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 366  * @dev: drm device
 367  * @pipe: pipe
 368  * @enable: true if we want to report FIFO underrun errors, false otherwise
 369  *
 370  * This function makes us disable or enable CPU fifo underruns for a specific
 371  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 372  * reporting for one pipe may also disable all the other CPU error interruts for
 373  * the other pipes, due to the fact that there's just one interrupt mask/enable
 374  * bit for all the pipes.
 375  *
 376  * Returns the previous state of underrun reporting.
 377  */
 378 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 379                                            enum pipe pipe, bool enable)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 383         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 384         unsigned long flags;
 385         bool ret;
 386
 387         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 388
 389         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 390
 391         if (enable == ret)
 392                 goto done;
 393
 394         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 395
 396         if (IS_GEN5(dev) || IS_GEN6(dev))
 397                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 398         else if (IS_GEN7(dev))
 399                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 400         else if (IS_GEN8(dev))
 401                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 402
 403 done:
 404         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 405         return ret;
 406 }
 407
 408 /**
 409  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 410  * @dev: drm device
 411  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 412  * @enable: true if we want to report FIFO underrun errors, false otherwise
 413  *
 414  * This function makes us disable or enable PCH fifo underruns for a specific
 415  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 416  * underrun reporting for one transcoder may also disable all the other PCH
 417  * error interruts for the other transcoders, due to the fact that there's just
 418  * one interrupt mask/enable bit for all the transcoders.
 419  *
 420  * Returns the previous state of underrun reporting.
 421  */
 422 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 423                                            enum transcoder pch_transcoder,
 424                                            bool enable)
 425 {
 426         struct drm_i915_private *dev_priv = dev->dev_private;
 427         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 429         unsigned long flags;
 430         bool ret;
 431
 432         /*
 433          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 434          * has only one pch transcoder A that all pipes can use. To avoid racy
 435          * pch transcoder -> pipe lookups from interrupt code simply store the
 436          * underrun statistics in crtc A. Since we never expose this anywhere
 437          * nor use it outside of the fifo underrun code here using the "wrong"
 438          * crtc on LPT won't cause issues.
 439          */
 440
 441         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 442
 443         ret = !intel_crtc->pch_fifo_underrun_disabled;
 444
 445         if (enable == ret)
 446                 goto done;
 447
 448         intel_crtc->pch_fifo_underrun_disabled = !enable;
 449
 450         if (HAS_PCH_IBX(dev))
 451                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 452         else
 453                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 454
 455 done:
 456         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 457         return ret;
 458 }
 459
 460
 461 void
 462 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 463 {
 464         u32 reg = PIPESTAT(pipe);
 465         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 466
 467         assert_spin_locked(&dev_priv->irq_lock);
 468
 469         if ((pipestat & mask) == mask)
 470                 return;
 471
 472         /* Enable the interrupt, clear any pending status */
 473         pipestat |= mask | (mask >> 16);
 474         I915_WRITE(reg, pipestat);
 475         POSTING_READ(reg);
 476 }
 477
 478 void
 479 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
 480 {
 481         u32 reg = PIPESTAT(pipe);
 482         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 483
 484         assert_spin_locked(&dev_priv->irq_lock);
 485
 486         if ((pipestat & mask) == 0)
 487                 return;
 488
 489         pipestat &= ~mask;
 490         I915_WRITE(reg, pipestat);
 491         POSTING_READ(reg);
 492 }
 493
 494 /**
 495  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 496  */
 497 static void i915_enable_asle_pipestat(struct drm_device *dev)
 498 {
 499         drm_i915_private_t *dev_priv = dev->dev_private;
 500         unsigned long irqflags;
 501
 502         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 503                 return;
 504
 505         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 506
 507         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
 508         if (INTEL_INFO(dev)->gen >= 4)
 509                 i915_enable_pipestat(dev_priv, PIPE_A,
 510                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 511
 512         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 513 }
 514
 515 /**
 516  * i915_pipe_enabled - check if a pipe is enabled
 517  * @dev: DRM device
 518  * @pipe: pipe to check
 519  *
 520  * Reading certain registers when the pipe is disabled can hang the chip.
 521  * Use this routine to make sure the PLL is running and the pipe is active
 522  * before reading such registers if unsure.
 523  */
 524 static int
 525 i915_pipe_enabled(struct drm_device *dev, int pipe)
 526 {
 527         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 528
 529         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 530                 /* Locking is horribly broken here, but whatever. */
 531                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 532                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 533
 534                 return intel_crtc->active;
 535         } else {
 536                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 537         }
 538 }
 539
 540 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 541 {
 542         /* Gen2 doesn't have a hardware frame counter */
 543         return 0;
 544 }
 545
 546 /* Called from drm generic code, passed a 'crtc', which
 547  * we use as a pipe index
 548  */
 549 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 550 {
 551         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 552         unsigned long high_frame;
 553         unsigned long low_frame;
 554         u32 high1, high2, low, pixel, vbl_start;
 555
 556         if (!i915_pipe_enabled(dev, pipe)) {
 557                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 558                                 "pipe %c\n", pipe_name(pipe));
 559                 return 0;
 560         }
 561
 562         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 563                 struct intel_crtc *intel_crtc =
 564                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 565                 const struct drm_display_mode *mode =
 566                         &intel_crtc->config.adjusted_mode;
 567
 568                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 569         } else {
 570                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 571                 u32 htotal;
 572
 573                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 574                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 575
 576                 vbl_start *= htotal;
 577         }
 578
 579         high_frame = PIPEFRAME(pipe);
 580         low_frame = PIPEFRAMEPIXEL(pipe);
 581
 582         /*
 583          * High & low register fields aren't synchronized, so make sure
 584          * we get a low value that's stable across two reads of the high
 585          * register.
 586          */
 587         do {
 588                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 589                 low   = I915_READ(low_frame);
 590                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 591         } while (high1 != high2);
 592
 593         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 594         pixel = low & PIPE_PIXEL_MASK;
 595         low >>= PIPE_FRAME_LOW_SHIFT;
 596
 597         /*
 598          * The frame counter increments at beginning of active.
 599          * Cook up a vblank counter by also checking the pixel
 600          * counter against vblank start.
 601          */
 602         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 603 }
 604
 605 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 606 {
 607         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 608         int reg = PIPE_FRMCOUNT_GM45(pipe);
 609
 610         if (!i915_pipe_enabled(dev, pipe)) {
 611                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 612                                  "pipe %c\n", pipe_name(pipe));
 613                 return 0;
 614         }
 615
 616         return I915_READ(reg);
 617 }
 618
 619 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 620 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 621 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
 622
 623 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 624 {
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626         uint32_t status;
 627
 628         if (INTEL_INFO(dev)->gen < 7) {
 629                 status = pipe == PIPE_A ?
 630                         DE_PIPEA_VBLANK :
 631                         DE_PIPEB_VBLANK;
 632         } else {
 633                 switch (pipe) {
 634                 default:
 635                 case PIPE_A:
 636                         status = DE_PIPEA_VBLANK_IVB;
 637                         break;
 638                 case PIPE_B:
 639                         status = DE_PIPEB_VBLANK_IVB;
 640                         break;
 641                 case PIPE_C:
 642                         status = DE_PIPEC_VBLANK_IVB;
 643                         break;
 644                 }
 645         }
 646
 647         return __raw_i915_read32(dev_priv, DEISR) & status;
 648 }
 649
 650 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 651                                     unsigned int flags, int *vpos, int *hpos,
 652                                     ktime_t *stime, ktime_t *etime)
 653 {
 654         struct drm_i915_private *dev_priv = dev->dev_private;
 655         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 657         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 658         int position;
 659         int vbl_start, vbl_end, htotal, vtotal;
 660         bool in_vbl = true;
 661         int ret = 0;
 662         unsigned long irqflags;
 663
 664         if (!intel_crtc->active) {
 665                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 666                                  "pipe %c\n", pipe_name(pipe));
 667                 return 0;
 668         }
 669
 670         htotal = mode->crtc_htotal;
 671         vtotal = mode->crtc_vtotal;
 672         vbl_start = mode->crtc_vblank_start;
 673         vbl_end = mode->crtc_vblank_end;
 674
 675         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 676                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 677                 vbl_end /= 2;
 678                 vtotal /= 2;
 679         }
 680
 681         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 682
 683         /*
 684          * Lock uncore.lock, as we will do multiple timing critical raw
 685          * register reads, potentially with preemption disabled, so the
 686          * following code must not block on uncore.lock.
 687          */
 688         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 689
 690         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 691
 692         /* Get optional system timestamp before query. */
 693         if (stime)
 694                 *stime = ktime_get();
 695
 696         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 697                 /* No obvious pixelcount register. Only query vertical
 698                  * scanout position from Display scan line register.
 699                  */
 700                 if (IS_GEN2(dev))
 701                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 702                 else
 703                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 704
 705                 if (HAS_DDI(dev)) {
 706                         /*
 707                          * On HSW HDMI outputs there seems to be a 2 line
 708                          * difference, whereas eDP has the normal 1 line
 709                          * difference that earlier platforms have. External
 710                          * DP is unknown. For now just check for the 2 line
 711                          * difference case on all output types on HSW+.
 712                          *
 713                          * This might misinterpret the scanline counter being
 714                          * one line too far along on eDP, but that's less
 715                          * dangerous than the alternative since that would lead
 716                          * the vblank timestamp code astray when it sees a
 717                          * scanline count before vblank_start during a vblank
 718                          * interrupt.
 719                          */
 720                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 721                         if ((in_vbl && (position == vbl_start - 2 ||
 722                                         position == vbl_start - 1)) ||
 723                             (!in_vbl && (position == vbl_end - 2 ||
 724                                          position == vbl_end - 1)))
 725                                 position = (position + 2) % vtotal;
 726                 } else if (HAS_PCH_SPLIT(dev)) {
 727                         /*
 728                          * The scanline counter increments at the leading edge
 729                          * of hsync, ie. it completely misses the active portion
 730                          * of the line. Fix up the counter at both edges of vblank
 731                          * to get a more accurate picture whether we're in vblank
 732                          * or not.
 733                          */
 734                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 735                         if ((in_vbl && position == vbl_start - 1) ||
 736                             (!in_vbl && position == vbl_end - 1))
 737                                 position = (position + 1) % vtotal;
 738                 } else {
 739                         /*
 740                          * ISR vblank status bits don't work the way we'd want
 741                          * them to work on non-PCH platforms (for
 742                          * ilk_pipe_in_vblank_locked()), and there doesn't
 743                          * appear any other way to determine if we're currently
 744                          * in vblank.
 745                          *
 746                          * Instead let's assume that we're already in vblank if
 747                          * we got called from the vblank interrupt and the
 748                          * scanline counter value indicates that we're on the
 749                          * line just prior to vblank start. This should result
 750                          * in the correct answer, unless the vblank interrupt
 751                          * delivery really got delayed for almost exactly one
 752                          * full frame/field.
 753                          */
 754                         if (flags & DRM_CALLED_FROM_VBLIRQ &&
 755                             position == vbl_start - 1) {
 756                                 position = (position + 1) % vtotal;
 757
 758                                 /* Signal this correction as "applied". */
 759                                 ret |= 0x8;
 760                         }
 761                 }
 762         } else {
 763                 /* Have access to pixelcount since start of frame.
 764                  * We can split this into vertical and horizontal
 765                  * scanout position.
 766                  */
 767                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 768
 769                 /* convert to pixel counts */
 770                 vbl_start *= htotal;
 771                 vbl_end *= htotal;
 772                 vtotal *= htotal;
 773         }
 774
 775         /* Get optional system timestamp after query. */
 776         if (etime)
 777                 *etime = ktime_get();
 778
 779         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 780
 781         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 782
 783         in_vbl = position >= vbl_start && position < vbl_end;
 784
 785         /*
 786          * While in vblank, position will be negative
 787          * counting up towards 0 at vbl_end. And outside
 788          * vblank, position will be positive counting
 789          * up since vbl_end.
 790          */
 791         if (position >= vbl_start)
 792                 position -= vbl_end;
 793         else
 794                 position += vtotal - vbl_end;
 795
 796         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 797                 *vpos = position;
 798                 *hpos = 0;
 799         } else {
 800                 *vpos = position / htotal;
 801                 *hpos = position - (*vpos * htotal);
 802         }
 803
 804         /* In vblank? */
 805         if (in_vbl)
 806                 ret |= DRM_SCANOUTPOS_INVBL;
 807
 808         return ret;
 809 }
 810
 811 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 812                               int *max_error,
 813                               struct timeval *vblank_time,
 814                               unsigned flags)
 815 {
 816         struct drm_crtc *crtc;
 817
 818         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 819                 DRM_ERROR("Invalid crtc %d\n", pipe);
 820                 return -EINVAL;
 821         }
 822
 823         /* Get drm_crtc to timestamp: */
 824         crtc = intel_get_crtc_for_pipe(dev, pipe);
 825         if (crtc == NULL) {
 826                 DRM_ERROR("Invalid crtc %d\n", pipe);
 827                 return -EINVAL;
 828         }
 829
 830         if (!crtc->enabled) {
 831                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 832                 return -EBUSY;
 833         }
 834
 835         /* Helper routine in DRM core does all the work: */
 836         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 837                                                      vblank_time, flags,
 838                                                      crtc,
 839                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 840 }
 841
 842 static bool intel_hpd_irq_event(struct drm_device *dev,
 843                                 struct drm_connector *connector)
 844 {
 845         enum drm_connector_status old_status;
 846
 847         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 848         old_status = connector->status;
 849
 850         connector->status = connector->funcs->detect(connector, false);
 851         if (old_status == connector->status)
 852                 return false;
 853
 854         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 855                       connector->base.id,
 856                       drm_get_connector_name(connector),
 857                       drm_get_connector_status_name(old_status),
 858                       drm_get_connector_status_name(connector->status));
 859
 860         return true;
 861 }
 862
 863 /*
 864  * Handle hotplug events outside the interrupt handler proper.
 865  */
 866 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 867
 868 static void i915_hotplug_work_func(struct work_struct *work)
 869 {
 870         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 871                                                     hotplug_work);
 872         struct drm_device *dev = dev_priv->dev;
 873         struct drm_mode_config *mode_config = &dev->mode_config;
 874         struct intel_connector *intel_connector;
 875         struct intel_encoder *intel_encoder;
 876         struct drm_connector *connector;
 877         unsigned long irqflags;
 878         bool hpd_disabled = false;
 879         bool changed = false;
 880         u32 hpd_event_bits;
 881
 882         /* HPD irq before everything is fully set up. */
 883         if (!dev_priv->enable_hotplug_processing)
 884                 return;
 885
 886         mutex_lock(&mode_config->mutex);
 887         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 888
 889         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 890
 891         hpd_event_bits = dev_priv->hpd_event_bits;
 892         dev_priv->hpd_event_bits = 0;
 893         list_for_each_entry(connector, &mode_config->connector_list, head) {
 894                 intel_connector = to_intel_connector(connector);
 895                 intel_encoder = intel_connector->encoder;
 896                 if (intel_encoder->hpd_pin > HPD_NONE &&
 897                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 898                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 899                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 900                                  "switching from hotplug detection to polling\n",
 901                                 drm_get_connector_name(connector));
 902                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 903                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 904                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 905                         hpd_disabled = true;
 906                 }
 907                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 908                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 909                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 910                 }
 911         }
 912          /* if there were no outputs to poll, poll was disabled,
 913           * therefore make sure it's enabled when disabling HPD on
 914           * some connectors */
 915         if (hpd_disabled) {
 916                 drm_kms_helper_poll_enable(dev);
 917                 mod_timer(&dev_priv->hotplug_reenable_timer,
 918                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 919         }
 920
 921         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 922
 923         list_for_each_entry(connector, &mode_config->connector_list, head) {
 924                 intel_connector = to_intel_connector(connector);
 925                 intel_encoder = intel_connector->encoder;
 926                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 927                         if (intel_encoder->hot_plug)
 928                                 intel_encoder->hot_plug(intel_encoder);
 929                         if (intel_hpd_irq_event(dev, connector))
 930                                 changed = true;
 931                 }
 932         }
 933         mutex_unlock(&mode_config->mutex);
 934
 935         if (changed)
 936                 drm_kms_helper_hotplug_event(dev);
 937 }
 938
 939 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 940 {
 941         drm_i915_private_t *dev_priv = dev->dev_private;
 942         u32 busy_up, busy_down, max_avg, min_avg;
 943         u8 new_delay;
 944
 945         spin_lock(&mchdev_lock);
 946
 947         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 948
 949         new_delay = dev_priv->ips.cur_delay;
 950
 951         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 952         busy_up = I915_READ(RCPREVBSYTUPAVG);
 953         busy_down = I915_READ(RCPREVBSYTDNAVG);
 954         max_avg = I915_READ(RCBMAXAVG);
 955         min_avg = I915_READ(RCBMINAVG);
 956
 957         /* Handle RCS change request from hw */
 958         if (busy_up > max_avg) {
 959                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 960                         new_delay = dev_priv->ips.cur_delay - 1;
 961                 if (new_delay < dev_priv->ips.max_delay)
 962                         new_delay = dev_priv->ips.max_delay;
 963         } else if (busy_down < min_avg) {
 964                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 965                         new_delay = dev_priv->ips.cur_delay + 1;
 966                 if (new_delay > dev_priv->ips.min_delay)
 967                         new_delay = dev_priv->ips.min_delay;
 968         }
 969
 970         if (ironlake_set_drps(dev, new_delay))
 971                 dev_priv->ips.cur_delay = new_delay;
 972
 973         spin_unlock(&mchdev_lock);
 974
 975         return;
 976 }
 977
 978 static void notify_ring(struct drm_device *dev,
 979                         struct intel_ring_buffer *ring)
 980 {
 981         if (ring->obj == NULL)
 982                 return;
 983
 984         trace_i915_gem_request_complete(ring);
 985
 986         wake_up_all(&ring->irq_queue);
 987         i915_queue_hangcheck(dev);
 988 }
 989
 990 static void gen6_pm_rps_work(struct work_struct *work)
 991 {
 992         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 993                                                     rps.work);
 994         u32 pm_iir;
 995         int new_delay, adj;
 996
 997         spin_lock_irq(&dev_priv->irq_lock);
 998         pm_iir = dev_priv->rps.pm_iir;
 999         dev_priv->rps.pm_iir = 0;
1000         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1001         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
1002         spin_unlock_irq(&dev_priv->irq_lock);
1003
1004         /* Make sure we didn't queue anything we're not going to process. */
1005         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1006
1007         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1008                 return;
1009
1010         mutex_lock(&dev_priv->rps.hw_lock);
1011
1012         adj = dev_priv->rps.last_adj;
1013         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1014                 if (adj > 0)
1015                         adj *= 2;
1016                 else
1017                         adj = 1;
1018                 new_delay = dev_priv->rps.cur_delay + adj;
1019
1020                 /*
1021                  * For better performance, jump directly
1022                  * to RPe if we're below it.
1023                  */
1024                 if (new_delay < dev_priv->rps.rpe_delay)
1025                         new_delay = dev_priv->rps.rpe_delay;
1026         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1027                 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1028                         new_delay = dev_priv->rps.rpe_delay;
1029                 else
1030                         new_delay = dev_priv->rps.min_delay;
1031                 adj = 0;
1032         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1033                 if (adj < 0)
1034                         adj *= 2;
1035                 else
1036                         adj = -1;
1037                 new_delay = dev_priv->rps.cur_delay + adj;
1038         } else { /* unknown event */
1039                 new_delay = dev_priv->rps.cur_delay;
1040         }
1041
1042         /* sysfs frequency interfaces may have snuck in while servicing the
1043          * interrupt
1044          */
1045         new_delay = clamp_t(int, new_delay,
1046                             dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1047         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1048
1049         if (IS_VALLEYVIEW(dev_priv->dev))
1050                 valleyview_set_rps(dev_priv->dev, new_delay);
1051         else
1052                 gen6_set_rps(dev_priv->dev, new_delay);
1053
1054         mutex_unlock(&dev_priv->rps.hw_lock);
1055 }
1056
1057
1058 /**
1059  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1060  * occurred.
1061  * @work: workqueue struct
1062  *
1063  * Doesn't actually do anything except notify userspace. As a consequence of
1064  * this event, userspace should try to remap the bad rows since statistically
1065  * it is likely the same row is more likely to go bad again.
1066  */
1067 static void ivybridge_parity_work(struct work_struct *work)
1068 {
1069         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1070                                                     l3_parity.error_work);
1071         u32 error_status, row, bank, subbank;
1072         char *parity_event[6];
1073         uint32_t misccpctl;
1074         unsigned long flags;
1075         uint8_t slice = 0;
1076
1077         /* We must turn off DOP level clock gating to access the L3 registers.
1078          * In order to prevent a get/put style interface, acquire struct mutex
1079          * any time we access those registers.
1080          */
1081         mutex_lock(&dev_priv->dev->struct_mutex);
1082
1083         /* If we've screwed up tracking, just let the interrupt fire again */
1084         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1085                 goto out;
1086
1087         misccpctl = I915_READ(GEN7_MISCCPCTL);
1088         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1089         POSTING_READ(GEN7_MISCCPCTL);
1090
1091         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1092                 u32 reg;
1093
1094                 slice--;
1095                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1096                         break;
1097
1098                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1099
1100                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1101
1102                 error_status = I915_READ(reg);
1103                 row = GEN7_PARITY_ERROR_ROW(error_status);
1104                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1105                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1106
1107                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1108                 POSTING_READ(reg);
1109
1110                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1111                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1112                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1113                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1114                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1115                 parity_event[5] = NULL;
1116
1117                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1118                                    KOBJ_CHANGE, parity_event);
1119
1120                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1121                           slice, row, bank, subbank);
1122
1123                 kfree(parity_event[4]);
1124                 kfree(parity_event[3]);
1125                 kfree(parity_event[2]);
1126                 kfree(parity_event[1]);
1127         }
1128
1129         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1130
1131 out:
1132         WARN_ON(dev_priv->l3_parity.which_slice);
1133         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1134         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1135         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1136
1137         mutex_unlock(&dev_priv->dev->struct_mutex);
1138 }
1139
1140 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1141 {
1142         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1143
1144         if (!HAS_L3_DPF(dev))
1145                 return;
1146
1147         spin_lock(&dev_priv->irq_lock);
1148         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1149         spin_unlock(&dev_priv->irq_lock);
1150
1151         iir &= GT_PARITY_ERROR(dev);
1152         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1153                 dev_priv->l3_parity.which_slice |= 1 << 1;
1154
1155         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1156                 dev_priv->l3_parity.which_slice |= 1 << 0;
1157
1158         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1159 }
1160
1161 static void ilk_gt_irq_handler(struct drm_device *dev,
1162                                struct drm_i915_private *dev_priv,
1163                                u32 gt_iir)
1164 {
1165         if (gt_iir &
1166             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1167                 notify_ring(dev, &dev_priv->ring[RCS]);
1168         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1169                 notify_ring(dev, &dev_priv->ring[VCS]);
1170 }
1171
1172 static void snb_gt_irq_handler(struct drm_device *dev,
1173                                struct drm_i915_private *dev_priv,
1174                                u32 gt_iir)
1175 {
1176
1177         if (gt_iir &
1178             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1179                 notify_ring(dev, &dev_priv->ring[RCS]);
1180         if (gt_iir & GT_BSD_USER_INTERRUPT)
1181                 notify_ring(dev, &dev_priv->ring[VCS]);
1182         if (gt_iir & GT_BLT_USER_INTERRUPT)
1183                 notify_ring(dev, &dev_priv->ring[BCS]);
1184
1185         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1186                       GT_BSD_CS_ERROR_INTERRUPT |
1187                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1188                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1189                 i915_handle_error(dev, false);
1190         }
1191
1192         if (gt_iir & GT_PARITY_ERROR(dev))
1193                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1194 }
1195
1196 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1197                                        struct drm_i915_private *dev_priv,
1198                                        u32 master_ctl)
1199 {
1200         u32 rcs, bcs, vcs;
1201         uint32_t tmp = 0;
1202         irqreturn_t ret = IRQ_NONE;
1203
1204         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1205                 tmp = I915_READ(GEN8_GT_IIR(0));
1206                 if (tmp) {
1207                         ret = IRQ_HANDLED;
1208                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1209                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1210                         if (rcs & GT_RENDER_USER_INTERRUPT)
1211                                 notify_ring(dev, &dev_priv->ring[RCS]);
1212                         if (bcs & GT_RENDER_USER_INTERRUPT)
1213                                 notify_ring(dev, &dev_priv->ring[BCS]);
1214                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1215                 } else
1216                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1217         }
1218
1219         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1220                 tmp = I915_READ(GEN8_GT_IIR(1));
1221                 if (tmp) {
1222                         ret = IRQ_HANDLED;
1223                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1224                         if (vcs & GT_RENDER_USER_INTERRUPT)
1225                                 notify_ring(dev, &dev_priv->ring[VCS]);
1226                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1227                 } else
1228                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1229         }
1230
1231         if (master_ctl & GEN8_GT_VECS_IRQ) {
1232                 tmp = I915_READ(GEN8_GT_IIR(3));
1233                 if (tmp) {
1234                         ret = IRQ_HANDLED;
1235                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1236                         if (vcs & GT_RENDER_USER_INTERRUPT)
1237                                 notify_ring(dev, &dev_priv->ring[VECS]);
1238                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1239                 } else
1240                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1241         }
1242
1243         return ret;
1244 }
1245
1246 #define HPD_STORM_DETECT_PERIOD 1000
1247 #define HPD_STORM_THRESHOLD 5
1248
1249 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1250                                          u32 hotplug_trigger,
1251                                          const u32 *hpd)
1252 {
1253         drm_i915_private_t *dev_priv = dev->dev_private;
1254         int i;
1255         bool storm_detected = false;
1256
1257         if (!hotplug_trigger)
1258                 return;
1259
1260         spin_lock(&dev_priv->irq_lock);
1261         for (i = 1; i < HPD_NUM_PINS; i++) {
1262
1263                 WARN_ONCE(hpd[i] & hotplug_trigger &&
1264                           dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1265                           "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1266                           hotplug_trigger, i, hpd[i]);
1267
1268                 if (!(hpd[i] & hotplug_trigger) ||
1269                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1270                         continue;
1271
1272                 dev_priv->hpd_event_bits |= (1 << i);
1273                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1274                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1275                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1276                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1277                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1278                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1279                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1280                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1281                         dev_priv->hpd_event_bits &= ~(1 << i);
1282                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1283                         storm_detected = true;
1284                 } else {
1285                         dev_priv->hpd_stats[i].hpd_cnt++;
1286                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1287                                       dev_priv->hpd_stats[i].hpd_cnt);
1288                 }
1289         }
1290
1291         if (storm_detected)
1292                 dev_priv->display.hpd_irq_setup(dev);
1293         spin_unlock(&dev_priv->irq_lock);
1294
1295         /*
1296          * Our hotplug handler can grab modeset locks (by calling down into the
1297          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1298          * queue for otherwise the flush_work in the pageflip code will
1299          * deadlock.
1300          */
1301         schedule_work(&dev_priv->hotplug_work);
1302 }
1303
1304 static void gmbus_irq_handler(struct drm_device *dev)
1305 {
1306         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1307
1308         wake_up_all(&dev_priv->gmbus_wait_queue);
1309 }
1310
1311 static void dp_aux_irq_handler(struct drm_device *dev)
1312 {
1313         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1314
1315         wake_up_all(&dev_priv->gmbus_wait_queue);
1316 }
1317
1318 #if defined(CONFIG_DEBUG_FS)
1319 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1320                                          uint32_t crc0, uint32_t crc1,
1321                                          uint32_t crc2, uint32_t crc3,
1322                                          uint32_t crc4)
1323 {
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1326         struct intel_pipe_crc_entry *entry;
1327         int head, tail;
1328
1329         spin_lock(&pipe_crc->lock);
1330
1331         if (!pipe_crc->entries) {
1332                 spin_unlock(&pipe_crc->lock);
1333                 DRM_ERROR("spurious interrupt\n");
1334                 return;
1335         }
1336
1337         head = pipe_crc->head;
1338         tail = pipe_crc->tail;
1339
1340         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1341                 spin_unlock(&pipe_crc->lock);
1342                 DRM_ERROR("CRC buffer overflowing\n");
1343                 return;
1344         }
1345
1346         entry = &pipe_crc->entries[head];
1347
1348         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1349         entry->crc[0] = crc0;
1350         entry->crc[1] = crc1;
1351         entry->crc[2] = crc2;
1352         entry->crc[3] = crc3;
1353         entry->crc[4] = crc4;
1354
1355         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1356         pipe_crc->head = head;
1357
1358         spin_unlock(&pipe_crc->lock);
1359
1360         wake_up_interruptible(&pipe_crc->wq);
1361 }
1362 #else
1363 static inline void
1364 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1365                              uint32_t crc0, uint32_t crc1,
1366                              uint32_t crc2, uint32_t crc3,
1367                              uint32_t crc4) {}
1368 #endif
1369
1370
1371 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1372 {
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374
1375         display_pipe_crc_irq_handler(dev, pipe,
1376                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1377                                      0, 0, 0, 0);
1378 }
1379
1380 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1381 {
1382         struct drm_i915_private *dev_priv = dev->dev_private;
1383
1384         display_pipe_crc_irq_handler(dev, pipe,
1385                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1386                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1387                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1388                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1389                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1390 }
1391
1392 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1393 {
1394         struct drm_i915_private *dev_priv = dev->dev_private;
1395         uint32_t res1, res2;
1396
1397         if (INTEL_INFO(dev)->gen >= 3)
1398                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1399         else
1400                 res1 = 0;
1401
1402         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1403                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1404         else
1405                 res2 = 0;
1406
1407         display_pipe_crc_irq_handler(dev, pipe,
1408                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1409                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1410                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1411                                      res1, res2);
1412 }
1413
1414 /* The RPS events need forcewake, so we add them to a work queue and mask their
1415  * IMR bits until the work is done. Other interrupts can be processed without
1416  * the work queue. */
1417 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1418 {
1419         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1420                 spin_lock(&dev_priv->irq_lock);
1421                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1422                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1423                 spin_unlock(&dev_priv->irq_lock);
1424
1425                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1426         }
1427
1428         if (HAS_VEBOX(dev_priv->dev)) {
1429                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1430                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1431
1432                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1433                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1434                         i915_handle_error(dev_priv->dev, false);
1435                 }
1436         }
1437 }
1438
1439 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1440 {
1441         struct drm_device *dev = (struct drm_device *) arg;
1442         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1443         u32 iir, gt_iir, pm_iir;
1444         irqreturn_t ret = IRQ_NONE;
1445         unsigned long irqflags;
1446         int pipe;
1447         u32 pipe_stats[I915_MAX_PIPES];
1448
1449         atomic_inc(&dev_priv->irq_received);
1450
1451         while (true) {
1452                 iir = I915_READ(VLV_IIR);
1453                 gt_iir = I915_READ(GTIIR);
1454                 pm_iir = I915_READ(GEN6_PMIIR);
1455
1456                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1457                         goto out;
1458
1459                 ret = IRQ_HANDLED;
1460
1461                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1462
1463                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1464                 for_each_pipe(pipe) {
1465                         int reg = PIPESTAT(pipe);
1466                         pipe_stats[pipe] = I915_READ(reg);
1467
1468                         /*
1469                          * Clear the PIPE*STAT regs before the IIR
1470                          */
1471                         if (pipe_stats[pipe] & 0x8000ffff) {
1472                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1473                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1474                                                          pipe_name(pipe));
1475                                 I915_WRITE(reg, pipe_stats[pipe]);
1476                         }
1477                 }
1478                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1479
1480                 for_each_pipe(pipe) {
1481                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1482                                 drm_handle_vblank(dev, pipe);
1483
1484                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1485                                 intel_prepare_page_flip(dev, pipe);
1486                                 intel_finish_page_flip(dev, pipe);
1487                         }
1488
1489                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1490                                 i9xx_pipe_crc_irq_handler(dev, pipe);
1491                 }
1492
1493                 /* Consume port.  Then clear IIR or we'll miss events */
1494                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1495                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1496                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1497
1498                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1499                                          hotplug_status);
1500
1501                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1502
1503                         if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1504                                 dp_aux_irq_handler(dev);
1505
1506                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1507                         I915_READ(PORT_HOTPLUG_STAT);
1508                 }
1509
1510                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1511                         gmbus_irq_handler(dev);
1512
1513                 if (pm_iir)
1514                         gen6_rps_irq_handler(dev_priv, pm_iir);
1515
1516                 I915_WRITE(GTIIR, gt_iir);
1517                 I915_WRITE(GEN6_PMIIR, pm_iir);
1518                 I915_WRITE(VLV_IIR, iir);
1519         }
1520
1521 out:
1522         return ret;
1523 }
1524
1525 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1526 {
1527         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1528         int pipe;
1529         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1530
1531         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1532
1533         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1534                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1535                                SDE_AUDIO_POWER_SHIFT);
1536                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1537                                  port_name(port));
1538         }
1539
1540         if (pch_iir & SDE_AUX_MASK)
1541                 dp_aux_irq_handler(dev);
1542
1543         if (pch_iir & SDE_GMBUS)
1544                 gmbus_irq_handler(dev);
1545
1546         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1547                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1548
1549         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1550                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1551
1552         if (pch_iir & SDE_POISON)
1553                 DRM_ERROR("PCH poison interrupt\n");
1554
1555         if (pch_iir & SDE_FDI_MASK)
1556                 for_each_pipe(pipe)
1557                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1558                                          pipe_name(pipe),
1559                                          I915_READ(FDI_RX_IIR(pipe)));
1560
1561         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1562                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1563
1564         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1565                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1566
1567         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1568                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1569                                                           false))
1570                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1571
1572         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1573                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1574                                                           false))
1575                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1576 }
1577
1578 static void ivb_err_int_handler(struct drm_device *dev)
1579 {
1580         struct drm_i915_private *dev_priv = dev->dev_private;
1581         u32 err_int = I915_READ(GEN7_ERR_INT);
1582         enum pipe pipe;
1583
1584         if (err_int & ERR_INT_POISON)
1585                 DRM_ERROR("Poison interrupt\n");
1586
1587         for_each_pipe(pipe) {
1588                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1589                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1590                                                                   false))
1591                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1592                                                  pipe_name(pipe));
1593                 }
1594
1595                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1596                         if (IS_IVYBRIDGE(dev))
1597                                 ivb_pipe_crc_irq_handler(dev, pipe);
1598                         else
1599                                 hsw_pipe_crc_irq_handler(dev, pipe);
1600                 }
1601         }
1602
1603         I915_WRITE(GEN7_ERR_INT, err_int);
1604 }
1605
1606 static void cpt_serr_int_handler(struct drm_device *dev)
1607 {
1608         struct drm_i915_private *dev_priv = dev->dev_private;
1609         u32 serr_int = I915_READ(SERR_INT);
1610
1611         if (serr_int & SERR_INT_POISON)
1612                 DRM_ERROR("PCH poison interrupt\n");
1613
1614         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1615                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1616                                                           false))
1617                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1618
1619         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1620                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1621                                                           false))
1622                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1623
1624         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1625                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1626                                                           false))
1627                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1628
1629         I915_WRITE(SERR_INT, serr_int);
1630 }
1631
1632 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1633 {
1634         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1635         int pipe;
1636         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1637
1638         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1639
1640         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1641                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1642                                SDE_AUDIO_POWER_SHIFT_CPT);
1643                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1644                                  port_name(port));
1645         }
1646
1647         if (pch_iir & SDE_AUX_MASK_CPT)
1648                 dp_aux_irq_handler(dev);
1649
1650         if (pch_iir & SDE_GMBUS_CPT)
1651                 gmbus_irq_handler(dev);
1652
1653         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1654                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1655
1656         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1657                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1658
1659         if (pch_iir & SDE_FDI_MASK_CPT)
1660                 for_each_pipe(pipe)
1661                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1662                                          pipe_name(pipe),
1663                                          I915_READ(FDI_RX_IIR(pipe)));
1664
1665         if (pch_iir & SDE_ERROR_CPT)
1666                 cpt_serr_int_handler(dev);
1667 }
1668
1669 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1670 {
1671         struct drm_i915_private *dev_priv = dev->dev_private;
1672         enum pipe pipe;
1673
1674         if (de_iir & DE_AUX_CHANNEL_A)
1675                 dp_aux_irq_handler(dev);
1676
1677         if (de_iir & DE_GSE)
1678                 intel_opregion_asle_intr(dev);
1679
1680         if (de_iir & DE_POISON)
1681                 DRM_ERROR("Poison interrupt\n");
1682
1683         for_each_pipe(pipe) {
1684                 if (de_iir & DE_PIPE_VBLANK(pipe))
1685                         drm_handle_vblank(dev, pipe);
1686
1687                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1688                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1689                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1690                                                  pipe_name(pipe));
1691
1692                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1693                         i9xx_pipe_crc_irq_handler(dev, pipe);
1694
1695                 /* plane/pipes map 1:1 on ilk+ */
1696                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1697                         intel_prepare_page_flip(dev, pipe);
1698                         intel_finish_page_flip_plane(dev, pipe);
1699                 }
1700         }
1701
1702         /* check event from PCH */
1703         if (de_iir & DE_PCH_EVENT) {
1704                 u32 pch_iir = I915_READ(SDEIIR);
1705
1706                 if (HAS_PCH_CPT(dev))
1707                         cpt_irq_handler(dev, pch_iir);
1708                 else
1709                         ibx_irq_handler(dev, pch_iir);
1710
1711                 /* should clear PCH hotplug event before clear CPU irq */
1712                 I915_WRITE(SDEIIR, pch_iir);
1713         }
1714
1715         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1716                 ironlake_rps_change_irq_handler(dev);
1717 }
1718
1719 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1720 {
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722         enum pipe i;
1723
1724         if (de_iir & DE_ERR_INT_IVB)
1725                 ivb_err_int_handler(dev);
1726
1727         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1728                 dp_aux_irq_handler(dev);
1729
1730         if (de_iir & DE_GSE_IVB)
1731                 intel_opregion_asle_intr(dev);
1732
1733         for_each_pipe(i) {
1734                 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1735                         drm_handle_vblank(dev, i);
1736
1737                 /* plane/pipes map 1:1 on ilk+ */
1738                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1739                         intel_prepare_page_flip(dev, i);
1740                         intel_finish_page_flip_plane(dev, i);
1741                 }
1742         }
1743
1744         /* check event from PCH */
1745         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1746                 u32 pch_iir = I915_READ(SDEIIR);
1747
1748                 cpt_irq_handler(dev, pch_iir);
1749
1750                 /* clear PCH hotplug event before clear CPU irq */
1751                 I915_WRITE(SDEIIR, pch_iir);
1752         }
1753 }
1754
1755 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1756 {
1757         struct drm_device *dev = (struct drm_device *) arg;
1758         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1759         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1760         irqreturn_t ret = IRQ_NONE;
1761
1762         atomic_inc(&dev_priv->irq_received);
1763
1764         /* We get interrupts on unclaimed registers, so check for this before we
1765          * do any I915_{READ,WRITE}. */
1766         intel_uncore_check_errors(dev);
1767
1768         /* disable master interrupt before clearing iir  */
1769         de_ier = I915_READ(DEIER);
1770         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1771         POSTING_READ(DEIER);
1772
1773         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1774          * interrupts will will be stored on its back queue, and then we'll be
1775          * able to process them after we restore SDEIER (as soon as we restore
1776          * it, we'll get an interrupt if SDEIIR still has something to process
1777          * due to its back queue). */
1778         if (!HAS_PCH_NOP(dev)) {
1779                 sde_ier = I915_READ(SDEIER);
1780                 I915_WRITE(SDEIER, 0);
1781                 POSTING_READ(SDEIER);
1782         }
1783
1784         gt_iir = I915_READ(GTIIR);
1785         if (gt_iir) {
1786                 if (INTEL_INFO(dev)->gen >= 6)
1787                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1788                 else
1789                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1790                 I915_WRITE(GTIIR, gt_iir);
1791                 ret = IRQ_HANDLED;
1792         }
1793
1794         de_iir = I915_READ(DEIIR);
1795         if (de_iir) {
1796                 if (INTEL_INFO(dev)->gen >= 7)
1797                         ivb_display_irq_handler(dev, de_iir);
1798                 else
1799                         ilk_display_irq_handler(dev, de_iir);
1800                 I915_WRITE(DEIIR, de_iir);
1801                 ret = IRQ_HANDLED;
1802         }
1803
1804         if (INTEL_INFO(dev)->gen >= 6) {
1805                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1806                 if (pm_iir) {
1807                         gen6_rps_irq_handler(dev_priv, pm_iir);
1808                         I915_WRITE(GEN6_PMIIR, pm_iir);
1809                         ret = IRQ_HANDLED;
1810                 }
1811         }
1812
1813         I915_WRITE(DEIER, de_ier);
1814         POSTING_READ(DEIER);
1815         if (!HAS_PCH_NOP(dev)) {
1816                 I915_WRITE(SDEIER, sde_ier);
1817                 POSTING_READ(SDEIER);
1818         }
1819
1820         return ret;
1821 }
1822
1823 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1824 {
1825         struct drm_device *dev = arg;
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827         u32 master_ctl;
1828         irqreturn_t ret = IRQ_NONE;
1829         uint32_t tmp = 0;
1830         enum pipe pipe;
1831
1832         atomic_inc(&dev_priv->irq_received);
1833
1834         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1835         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1836         if (!master_ctl)
1837                 return IRQ_NONE;
1838
1839         I915_WRITE(GEN8_MASTER_IRQ, 0);
1840         POSTING_READ(GEN8_MASTER_IRQ);
1841
1842         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1843
1844         if (master_ctl & GEN8_DE_MISC_IRQ) {
1845                 tmp = I915_READ(GEN8_DE_MISC_IIR);
1846                 if (tmp & GEN8_DE_MISC_GSE)
1847                         intel_opregion_asle_intr(dev);
1848                 else if (tmp)
1849                         DRM_ERROR("Unexpected DE Misc interrupt\n");
1850                 else
1851                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1852
1853                 if (tmp) {
1854                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1855                         ret = IRQ_HANDLED;
1856                 }
1857         }
1858
1859         if (master_ctl & GEN8_DE_PORT_IRQ) {
1860                 tmp = I915_READ(GEN8_DE_PORT_IIR);
1861                 if (tmp & GEN8_AUX_CHANNEL_A)
1862                         dp_aux_irq_handler(dev);
1863                 else if (tmp)
1864                         DRM_ERROR("Unexpected DE Port interrupt\n");
1865                 else
1866                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1867
1868                 if (tmp) {
1869                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1870                         ret = IRQ_HANDLED;
1871                 }
1872         }
1873
1874         for_each_pipe(pipe) {
1875                 uint32_t pipe_iir;
1876
1877                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1878                         continue;
1879
1880                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1881                 if (pipe_iir & GEN8_PIPE_VBLANK)
1882                         drm_handle_vblank(dev, pipe);
1883
1884                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1885                         intel_prepare_page_flip(dev, pipe);
1886                         intel_finish_page_flip_plane(dev, pipe);
1887                 }
1888
1889                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1890                         hsw_pipe_crc_irq_handler(dev, pipe);
1891
1892                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1893                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1894                                                                   false))
1895                                 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1896                                                  pipe_name(pipe));
1897                 }
1898
1899                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1900                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1901                                   pipe_name(pipe),
1902                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1903                 }
1904
1905                 if (pipe_iir) {
1906                         ret = IRQ_HANDLED;
1907                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1908                 } else
1909                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1910         }
1911
1912         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1913                 /*
1914                  * FIXME(BDW): Assume for now that the new interrupt handling
1915                  * scheme also closed the SDE interrupt handling race we've seen
1916                  * on older pch-split platforms. But this needs testing.
1917                  */
1918                 u32 pch_iir = I915_READ(SDEIIR);
1919
1920                 cpt_irq_handler(dev, pch_iir);
1921
1922                 if (pch_iir) {
1923                         I915_WRITE(SDEIIR, pch_iir);
1924                         ret = IRQ_HANDLED;
1925                 }
1926         }
1927
1928         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1929         POSTING_READ(GEN8_MASTER_IRQ);
1930
1931         return ret;
1932 }
1933
1934 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1935                                bool reset_completed)
1936 {
1937         struct intel_ring_buffer *ring;
1938         int i;
1939
1940         /*
1941          * Notify all waiters for GPU completion events that reset state has
1942          * been changed, and that they need to restart their wait after
1943          * checking for potential errors (and bail out to drop locks if there is
1944          * a gpu reset pending so that i915_error_work_func can acquire them).
1945          */
1946
1947         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1948         for_each_ring(ring, dev_priv, i)
1949                 wake_up_all(&ring->irq_queue);
1950
1951         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1952         wake_up_all(&dev_priv->pending_flip_queue);
1953
1954         /*
1955          * Signal tasks blocked in i915_gem_wait_for_error that the pending
1956          * reset state is cleared.
1957          */
1958         if (reset_completed)
1959                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1960 }
1961
1962 /**
1963  * i915_error_work_func - do process context error handling work
1964  * @work: work struct
1965  *
1966  * Fire an error uevent so userspace can see that a hang or error
1967  * was detected.
1968  */
1969 static void i915_error_work_func(struct work_struct *work)
1970 {
1971         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1972                                                     work);
1973         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1974                                                     gpu_error);
1975         struct drm_device *dev = dev_priv->dev;
1976         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1977         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1978         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1979         int ret;
1980
1981         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
1982
1983         /*
1984          * Note that there's only one work item which does gpu resets, so we
1985          * need not worry about concurrent gpu resets potentially incrementing
1986          * error->reset_counter twice. We only need to take care of another
1987          * racing irq/hangcheck declaring the gpu dead for a second time. A
1988          * quick check for that is good enough: schedule_work ensures the
1989          * correct ordering between hang detection and this work item, and since
1990          * the reset in-progress bit is only ever set by code outside of this
1991          * work we don't need to worry about any other races.
1992          */
1993         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1994                 DRM_DEBUG_DRIVER("resetting chip\n");
1995                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
1996                                    reset_event);
1997
1998                 /*
1999                  * All state reset _must_ be completed before we update the
2000                  * reset counter, for otherwise waiters might miss the reset
2001                  * pending state and not properly drop locks, resulting in
2002                  * deadlocks with the reset work.
2003                  */
2004                 ret = i915_reset(dev);
2005
2006                 intel_display_handle_reset(dev);
2007
2008                 if (ret == 0) {
2009                         /*
2010                          * After all the gem state is reset, increment the reset
2011                          * counter and wake up everyone waiting for the reset to
2012                          * complete.
2013                          *
2014                          * Since unlock operations are a one-sided barrier only,
2015                          * we need to insert a barrier here to order any seqno
2016                          * updates before
2017                          * the counter increment.
2018                          */
2019                         smp_mb__before_atomic_inc();
2020                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2021
2022                         kobject_uevent_env(&dev->primary->kdev->kobj,
2023                                            KOBJ_CHANGE, reset_done_event);
2024                 } else {
2025                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2026                 }
2027
2028                 /*
2029                  * Note: The wake_up also serves as a memory barrier so that
2030                  * waiters see the update value of the reset counter atomic_t.
2031                  */
2032                 i915_error_wake_up(dev_priv, true);
2033         }
2034 }
2035
2036 static void i915_report_and_clear_eir(struct drm_device *dev)
2037 {
2038         struct drm_i915_private *dev_priv = dev->dev_private;
2039         uint32_t instdone[I915_NUM_INSTDONE_REG];
2040         u32 eir = I915_READ(EIR);
2041         int pipe, i;
2042
2043         if (!eir)
2044                 return;
2045
2046         pr_err("render error detected, EIR: 0x%08x\n", eir);
2047
2048         i915_get_extra_instdone(dev, instdone);
2049
2050         if (IS_G4X(dev)) {
2051                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2052                         u32 ipeir = I915_READ(IPEIR_I965);
2053
2054                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2055                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2056                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2057                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2058                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2059                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2060                         I915_WRITE(IPEIR_I965, ipeir);
2061                         POSTING_READ(IPEIR_I965);
2062                 }
2063                 if (eir & GM45_ERROR_PAGE_TABLE) {
2064                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2065                         pr_err("page table error\n");
2066                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2067                         I915_WRITE(PGTBL_ER, pgtbl_err);
2068                         POSTING_READ(PGTBL_ER);
2069                 }
2070         }
2071
2072         if (!IS_GEN2(dev)) {
2073                 if (eir & I915_ERROR_PAGE_TABLE) {
2074                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2075                         pr_err("page table error\n");
2076                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2077                         I915_WRITE(PGTBL_ER, pgtbl_err);
2078                         POSTING_READ(PGTBL_ER);
2079                 }
2080         }
2081
2082         if (eir & I915_ERROR_MEMORY_REFRESH) {
2083                 pr_err("memory refresh error:\n");
2084                 for_each_pipe(pipe)
2085                         pr_err("pipe %c stat: 0x%08x\n",
2086                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2087                 /* pipestat has already been acked */
2088         }
2089         if (eir & I915_ERROR_INSTRUCTION) {
2090                 pr_err("instruction error\n");
2091                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2092                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2093                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2094                 if (INTEL_INFO(dev)->gen < 4) {
2095                         u32 ipeir = I915_READ(IPEIR);
2096
2097                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2098                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2099                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2100                         I915_WRITE(IPEIR, ipeir);
2101                         POSTING_READ(IPEIR);
2102                 } else {
2103                         u32 ipeir = I915_READ(IPEIR_I965);
2104
2105                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2106                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2107                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2108                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2109                         I915_WRITE(IPEIR_I965, ipeir);
2110                         POSTING_READ(IPEIR_I965);
2111                 }
2112         }
2113
2114         I915_WRITE(EIR, eir);
2115         POSTING_READ(EIR);
2116         eir = I915_READ(EIR);
2117         if (eir) {
2118                 /*
2119                  * some errors might have become stuck,
2120                  * mask them.
2121                  */
2122                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2123                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2124                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2125         }
2126 }
2127
2128 /**
2129  * i915_handle_error - handle an error interrupt
2130  * @dev: drm device
2131  *
2132  * Do some basic checking of regsiter state at error interrupt time and
2133  * dump it to the syslog.  Also call i915_capture_error_state() to make
2134  * sure we get a record and make it available in debugfs.  Fire a uevent
2135  * so userspace knows something bad happened (should trigger collection
2136  * of a ring dump etc.).
2137  */
2138 void i915_handle_error(struct drm_device *dev, bool wedged)
2139 {
2140         struct drm_i915_private *dev_priv = dev->dev_private;
2141
2142         i915_capture_error_state(dev);
2143         i915_report_and_clear_eir(dev);
2144
2145         if (wedged) {
2146                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2147                                 &dev_priv->gpu_error.reset_counter);
2148
2149                 /*
2150                  * Wakeup waiting processes so that the reset work function
2151                  * i915_error_work_func doesn't deadlock trying to grab various
2152                  * locks. By bumping the reset counter first, the woken
2153                  * processes will see a reset in progress and back off,
2154                  * releasing their locks and then wait for the reset completion.
2155                  * We must do this for _all_ gpu waiters that might hold locks
2156                  * that the reset work needs to acquire.
2157                  *
2158                  * Note: The wake_up serves as the required memory barrier to
2159                  * ensure that the waiters see the updated value of the reset
2160                  * counter atomic_t.
2161                  */
2162                 i915_error_wake_up(dev_priv, false);
2163         }
2164
2165         /*
2166          * Our reset work can grab modeset locks (since it needs to reset the
2167          * state of outstanding pagelips). Hence it must not be run on our own
2168          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2169          * code will deadlock.
2170          */
2171         schedule_work(&dev_priv->gpu_error.work);
2172 }
2173
2174 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2175 {
2176         drm_i915_private_t *dev_priv = dev->dev_private;
2177         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2178         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2179         struct drm_i915_gem_object *obj;
2180         struct intel_unpin_work *work;
2181         unsigned long flags;
2182         bool stall_detected;
2183
2184         /* Ignore early vblank irqs */
2185         if (intel_crtc == NULL)
2186                 return;
2187
2188         spin_lock_irqsave(&dev->event_lock, flags);
2189         work = intel_crtc->unpin_work;
2190
2191         if (work == NULL ||
2192             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2193             !work->enable_stall_check) {
2194                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2195                 spin_unlock_irqrestore(&dev->event_lock, flags);
2196                 return;
2197         }
2198
2199         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2200         obj = work->pending_flip_obj;
2201         if (INTEL_INFO(dev)->gen >= 4) {
2202                 int dspsurf = DSPSURF(intel_crtc->plane);
2203                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2204                                         i915_gem_obj_ggtt_offset(obj);
2205         } else {
2206                 int dspaddr = DSPADDR(intel_crtc->plane);
2207                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2208                                                         crtc->y * crtc->fb->pitches[0] +
2209                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2210         }
2211
2212         spin_unlock_irqrestore(&dev->event_lock, flags);
2213
2214         if (stall_detected) {
2215                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2216                 intel_prepare_page_flip(dev, intel_crtc->plane);
2217         }
2218 }
2219
2220 /* Called from drm generic code, passed 'crtc' which
2221  * we use as a pipe index
2222  */
2223 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2224 {
2225         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2226         unsigned long irqflags;
2227
2228         if (!i915_pipe_enabled(dev, pipe))
2229                 return -EINVAL;
2230
2231         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2232         if (INTEL_INFO(dev)->gen >= 4)
2233                 i915_enable_pipestat(dev_priv, pipe,
2234                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
2235         else
2236                 i915_enable_pipestat(dev_priv, pipe,
2237                                      PIPE_VBLANK_INTERRUPT_ENABLE);
2238
2239         /* maintain vblank delivery even in deep C-states */
2240         if (dev_priv->info->gen == 3)
2241                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2242         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2243
2244         return 0;
2245 }
2246
2247 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2248 {
2249         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2250         unsigned long irqflags;
2251         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2252                                                      DE_PIPE_VBLANK(pipe);
2253
2254         if (!i915_pipe_enabled(dev, pipe))
2255                 return -EINVAL;
2256
2257         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2258         ironlake_enable_display_irq(dev_priv, bit);
2259         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2260
2261         return 0;
2262 }
2263
2264 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2265 {
2266         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2267         unsigned long irqflags;
2268         u32 imr;
2269
2270         if (!i915_pipe_enabled(dev, pipe))
2271                 return -EINVAL;
2272
2273         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2274         imr = I915_READ(VLV_IMR);
2275         if (pipe == PIPE_A)
2276                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2277         else
2278                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2279         I915_WRITE(VLV_IMR, imr);
2280         i915_enable_pipestat(dev_priv, pipe,
2281                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
2282         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2283
2284         return 0;
2285 }
2286
2287 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2288 {
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         unsigned long irqflags;
2291
2292         if (!i915_pipe_enabled(dev, pipe))
2293                 return -EINVAL;
2294
2295         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2296         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2297         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2298         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2299         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2300         return 0;
2301 }
2302
2303 /* Called from drm generic code, passed 'crtc' which
2304  * we use as a pipe index
2305  */
2306 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2307 {
2308         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2309         unsigned long irqflags;
2310
2311         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2312         if (dev_priv->info->gen == 3)
2313                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2314
2315         i915_disable_pipestat(dev_priv, pipe,
2316                               PIPE_VBLANK_INTERRUPT_ENABLE |
2317                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2318         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2319 }
2320
2321 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2322 {
2323         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2324         unsigned long irqflags;
2325         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2326                                                      DE_PIPE_VBLANK(pipe);
2327
2328         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2329         ironlake_disable_display_irq(dev_priv, bit);
2330         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2331 }
2332
2333 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2334 {
2335         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2336         unsigned long irqflags;
2337         u32 imr;
2338
2339         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2340         i915_disable_pipestat(dev_priv, pipe,
2341                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
2342         imr = I915_READ(VLV_IMR);
2343         if (pipe == PIPE_A)
2344                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2345         else
2346                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2347         I915_WRITE(VLV_IMR, imr);
2348         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2349 }
2350
2351 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2352 {
2353         struct drm_i915_private *dev_priv = dev->dev_private;
2354         unsigned long irqflags;
2355
2356         if (!i915_pipe_enabled(dev, pipe))
2357                 return;
2358
2359         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2360         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2361         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2362         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2363         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2364 }
2365
2366 static u32
2367 ring_last_seqno(struct intel_ring_buffer *ring)
2368 {
2369         return list_entry(ring->request_list.prev,
2370                           struct drm_i915_gem_request, list)->seqno;
2371 }
2372
2373 static bool
2374 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2375 {
2376         return (list_empty(&ring->request_list) ||
2377                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2378 }
2379
2380 static struct intel_ring_buffer *
2381 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2382 {
2383         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2384         u32 cmd, ipehr, acthd, acthd_min;
2385
2386         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2387         if ((ipehr & ~(0x3 << 16)) !=
2388             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2389                 return NULL;
2390
2391         /* ACTHD is likely pointing to the dword after the actual command,
2392          * so scan backwards until we find the MBOX.
2393          */
2394         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2395         acthd_min = max((int)acthd - 3 * 4, 0);
2396         do {
2397                 cmd = ioread32(ring->virtual_start + acthd);
2398                 if (cmd == ipehr)
2399                         break;
2400
2401                 acthd -= 4;
2402                 if (acthd < acthd_min)
2403                         return NULL;
2404         } while (1);
2405
2406         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2407         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2408 }
2409
2410 static int semaphore_passed(struct intel_ring_buffer *ring)
2411 {
2412         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2413         struct intel_ring_buffer *signaller;
2414         u32 seqno, ctl;
2415
2416         ring->hangcheck.deadlock = true;
2417
2418         signaller = semaphore_waits_for(ring, &seqno);
2419         if (signaller == NULL || signaller->hangcheck.deadlock)
2420                 return -1;
2421
2422         /* cursory check for an unkickable deadlock */
2423         ctl = I915_READ_CTL(signaller);
2424         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2425                 return -1;
2426
2427         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2428 }
2429
2430 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2431 {
2432         struct intel_ring_buffer *ring;
2433         int i;
2434
2435         for_each_ring(ring, dev_priv, i)
2436                 ring->hangcheck.deadlock = false;
2437 }
2438
2439 static enum intel_ring_hangcheck_action
2440 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2441 {
2442         struct drm_device *dev = ring->dev;
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444         u32 tmp;
2445
2446         if (ring->hangcheck.acthd != acthd)
2447                 return HANGCHECK_ACTIVE;
2448
2449         if (IS_GEN2(dev))
2450                 return HANGCHECK_HUNG;
2451
2452         /* Is the chip hanging on a WAIT_FOR_EVENT?
2453          * If so we can simply poke the RB_WAIT bit
2454          * and break the hang. This should work on
2455          * all but the second generation chipsets.
2456          */
2457         tmp = I915_READ_CTL(ring);
2458         if (tmp & RING_WAIT) {
2459                 DRM_ERROR("Kicking stuck wait on %s\n",
2460                           ring->name);
2461                 i915_handle_error(dev, false);
2462                 I915_WRITE_CTL(ring, tmp);
2463                 return HANGCHECK_KICK;
2464         }
2465
2466         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2467                 switch (semaphore_passed(ring)) {
2468                 default:
2469                         return HANGCHECK_HUNG;
2470                 case 1:
2471                         DRM_ERROR("Kicking stuck semaphore on %s\n",
2472                                   ring->name);
2473                         i915_handle_error(dev, false);
2474                         I915_WRITE_CTL(ring, tmp);
2475                         return HANGCHECK_KICK;
2476                 case 0:
2477                         return HANGCHECK_WAIT;
2478                 }
2479         }
2480
2481         return HANGCHECK_HUNG;
2482 }
2483
2484 /**
2485  * This is called when the chip hasn't reported back with completed
2486  * batchbuffers in a long time. We keep track per ring seqno progress and
2487  * if there are no progress, hangcheck score for that ring is increased.
2488  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2489  * we kick the ring. If we see no progress on three subsequent calls
2490  * we assume chip is wedged and try to fix it by resetting the chip.
2491  */
2492 static void i915_hangcheck_elapsed(unsigned long data)
2493 {
2494         struct drm_device *dev = (struct drm_device *)data;
2495         drm_i915_private_t *dev_priv = dev->dev_private;
2496         struct intel_ring_buffer *ring;
2497         int i;
2498         int busy_count = 0, rings_hung = 0;
2499         bool stuck[I915_NUM_RINGS] = { 0 };
2500 #define BUSY 1
2501 #define KICK 5
2502 #define HUNG 20
2503 #define FIRE 30
2504
2505         if (!i915_enable_hangcheck)
2506                 return;
2507
2508         for_each_ring(ring, dev_priv, i) {
2509                 u32 seqno, acthd;
2510                 bool busy = true;
2511
2512                 semaphore_clear_deadlocks(dev_priv);
2513
2514                 seqno = ring->get_seqno(ring, false);
2515                 acthd = intel_ring_get_active_head(ring);
2516
2517                 if (ring->hangcheck.seqno == seqno) {
2518                         if (ring_idle(ring, seqno)) {
2519                                 ring->hangcheck.action = HANGCHECK_IDLE;
2520
2521                                 if (waitqueue_active(&ring->irq_queue)) {
2522                                         /* Issue a wake-up to catch stuck h/w. */
2523                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2524                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2525                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2526                                                                   ring->name);
2527                                                 else
2528                                                         DRM_INFO("Fake missed irq on %s\n",
2529                                                                  ring->name);
2530                                                 wake_up_all(&ring->irq_queue);
2531                                         }
2532                                         /* Safeguard against driver failure */
2533                                         ring->hangcheck.score += BUSY;
2534                                 } else
2535                                         busy = false;
2536                         } else {
2537                                 /* We always increment the hangcheck score
2538                                  * if the ring is busy and still processing
2539                                  * the same request, so that no single request
2540                                  * can run indefinitely (such as a chain of
2541                                  * batches). The only time we do not increment
2542                                  * the hangcheck score on this ring, if this
2543                                  * ring is in a legitimate wait for another
2544                                  * ring. In that case the waiting ring is a
2545                                  * victim and we want to be sure we catch the
2546                                  * right culprit. Then every time we do kick
2547                                  * the ring, add a small increment to the
2548                                  * score so that we can catch a batch that is
2549                                  * being repeatedly kicked and so responsible
2550                                  * for stalling the machine.
2551                                  */
2552                                 ring->hangcheck.action = ring_stuck(ring,
2553                                                                     acthd);
2554
2555                                 switch (ring->hangcheck.action) {
2556                                 case HANGCHECK_IDLE:
2557                                 case HANGCHECK_WAIT:
2558                                         break;
2559                                 case HANGCHECK_ACTIVE:
2560                                         ring->hangcheck.score += BUSY;
2561                                         break;
2562                                 case HANGCHECK_KICK:
2563                                         ring->hangcheck.score += KICK;
2564                                         break;
2565                                 case HANGCHECK_HUNG:
2566                                         ring->hangcheck.score += HUNG;
2567                                         stuck[i] = true;
2568                                         break;
2569                                 }
2570                         }
2571                 } else {
2572                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2573
2574                         /* Gradually reduce the count so that we catch DoS
2575                          * attempts across multiple batches.
2576                          */
2577                         if (ring->hangcheck.score > 0)
2578                                 ring->hangcheck.score--;
2579                 }
2580
2581                 ring->hangcheck.seqno = seqno;
2582                 ring->hangcheck.acthd = acthd;
2583                 busy_count += busy;
2584         }
2585
2586         for_each_ring(ring, dev_priv, i) {
2587                 if (ring->hangcheck.score > FIRE) {
2588                         DRM_INFO("%s on %s\n",
2589                                  stuck[i] ? "stuck" : "no progress",
2590                                  ring->name);
2591                         rings_hung++;
2592                 }
2593         }
2594
2595         if (rings_hung)
2596                 return i915_handle_error(dev, true);
2597
2598         if (busy_count)
2599                 /* Reset timer case chip hangs without another request
2600                  * being added */
2601                 i915_queue_hangcheck(dev);
2602 }
2603
2604 void i915_queue_hangcheck(struct drm_device *dev)
2605 {
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         if (!i915_enable_hangcheck)
2608                 return;
2609
2610         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2611                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2612 }
2613
2614 static void ibx_irq_preinstall(struct drm_device *dev)
2615 {
2616         struct drm_i915_private *dev_priv = dev->dev_private;
2617
2618         if (HAS_PCH_NOP(dev))
2619                 return;
2620
2621         /* south display irq */
2622         I915_WRITE(SDEIMR, 0xffffffff);
2623         /*
2624          * SDEIER is also touched by the interrupt handler to work around missed
2625          * PCH interrupts. Hence we can't update it after the interrupt handler
2626          * is enabled - instead we unconditionally enable all PCH interrupt
2627          * sources here, but then only unmask them as needed with SDEIMR.
2628          */
2629         I915_WRITE(SDEIER, 0xffffffff);
2630         POSTING_READ(SDEIER);
2631 }
2632
2633 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2634 {
2635         struct drm_i915_private *dev_priv = dev->dev_private;
2636
2637         /* and GT */
2638         I915_WRITE(GTIMR, 0xffffffff);
2639         I915_WRITE(GTIER, 0x0);
2640         POSTING_READ(GTIER);
2641
2642         if (INTEL_INFO(dev)->gen >= 6) {
2643                 /* and PM */
2644                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2645                 I915_WRITE(GEN6_PMIER, 0x0);
2646                 POSTING_READ(GEN6_PMIER);
2647         }
2648 }
2649
2650 /* drm_dma.h hooks
2651 */
2652 static void ironlake_irq_preinstall(struct drm_device *dev)
2653 {
2654         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2655
2656         atomic_set(&dev_priv->irq_received, 0);
2657
2658         I915_WRITE(HWSTAM, 0xeffe);
2659
2660         I915_WRITE(DEIMR, 0xffffffff);
2661         I915_WRITE(DEIER, 0x0);
2662         POSTING_READ(DEIER);
2663
2664         gen5_gt_irq_preinstall(dev);
2665
2666         ibx_irq_preinstall(dev);
2667 }
2668
2669 static void valleyview_irq_preinstall(struct drm_device *dev)
2670 {
2671         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2672         int pipe;
2673
2674         atomic_set(&dev_priv->irq_received, 0);
2675
2676         /* VLV magic */
2677         I915_WRITE(VLV_IMR, 0);
2678         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2679         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2680         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2681
2682         /* and GT */
2683         I915_WRITE(GTIIR, I915_READ(GTIIR));
2684         I915_WRITE(GTIIR, I915_READ(GTIIR));
2685
2686         gen5_gt_irq_preinstall(dev);
2687
2688         I915_WRITE(DPINVGTT, 0xff);
2689
2690         I915_WRITE(PORT_HOTPLUG_EN, 0);
2691         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2692         for_each_pipe(pipe)
2693                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2694         I915_WRITE(VLV_IIR, 0xffffffff);
2695         I915_WRITE(VLV_IMR, 0xffffffff);
2696         I915_WRITE(VLV_IER, 0x0);
2697         POSTING_READ(VLV_IER);
2698 }
2699
2700 static void gen8_irq_preinstall(struct drm_device *dev)
2701 {
2702         struct drm_i915_private *dev_priv = dev->dev_private;
2703         int pipe;
2704
2705         atomic_set(&dev_priv->irq_received, 0);
2706
2707         I915_WRITE(GEN8_MASTER_IRQ, 0);
2708         POSTING_READ(GEN8_MASTER_IRQ);
2709
2710         /* IIR can theoretically queue up two events. Be paranoid */
2711 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2712                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2713                 POSTING_READ(GEN8_##type##_IMR(which)); \
2714                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2715                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2716                 POSTING_READ(GEN8_##type##_IIR(which)); \
2717                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2718         } while (0)
2719
2720 #define GEN8_IRQ_INIT(type) do { \
2721                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2722                 POSTING_READ(GEN8_##type##_IMR); \
2723                 I915_WRITE(GEN8_##type##_IER, 0); \
2724                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2725                 POSTING_READ(GEN8_##type##_IIR); \
2726                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2727         } while (0)
2728
2729         GEN8_IRQ_INIT_NDX(GT, 0);
2730         GEN8_IRQ_INIT_NDX(GT, 1);
2731         GEN8_IRQ_INIT_NDX(GT, 2);
2732         GEN8_IRQ_INIT_NDX(GT, 3);
2733
2734         for_each_pipe(pipe) {
2735                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2736         }
2737
2738         GEN8_IRQ_INIT(DE_PORT);
2739         GEN8_IRQ_INIT(DE_MISC);
2740         GEN8_IRQ_INIT(PCU);
2741 #undef GEN8_IRQ_INIT
2742 #undef GEN8_IRQ_INIT_NDX
2743
2744         POSTING_READ(GEN8_PCU_IIR);
2745
2746         ibx_irq_preinstall(dev);
2747 }
2748
2749 static void ibx_hpd_irq_setup(struct drm_device *dev)
2750 {
2751         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2752         struct drm_mode_config *mode_config = &dev->mode_config;
2753         struct intel_encoder *intel_encoder;
2754         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2755
2756         if (HAS_PCH_IBX(dev)) {
2757                 hotplug_irqs = SDE_HOTPLUG_MASK;
2758                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2759                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2760                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2761         } else {
2762                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2763                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2764                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2765                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2766         }
2767
2768         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2769
2770         /*
2771          * Enable digital hotplug on the PCH, and configure the DP short pulse
2772          * duration to 2ms (which is the minimum in the Display Port spec)
2773          *
2774          * This register is the same on all known PCH chips.
2775          */
2776         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2777         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2778         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2779         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2780         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2781         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2782 }
2783
2784 static void ibx_irq_postinstall(struct drm_device *dev)
2785 {
2786         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2787         u32 mask;
2788
2789         if (HAS_PCH_NOP(dev))
2790                 return;
2791
2792         if (HAS_PCH_IBX(dev)) {
2793                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2794                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2795         } else {
2796                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2797
2798                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2799         }
2800
2801         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2802         I915_WRITE(SDEIMR, ~mask);
2803 }
2804
2805 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2806 {
2807         struct drm_i915_private *dev_priv = dev->dev_private;
2808         u32 pm_irqs, gt_irqs;
2809
2810         pm_irqs = gt_irqs = 0;
2811
2812         dev_priv->gt_irq_mask = ~0;
2813         if (HAS_L3_DPF(dev)) {
2814                 /* L3 parity interrupt is always unmasked. */
2815                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2816                 gt_irqs |= GT_PARITY_ERROR(dev);
2817         }
2818
2819         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2820         if (IS_GEN5(dev)) {
2821                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2822                            ILK_BSD_USER_INTERRUPT;
2823         } else {
2824                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2825         }
2826
2827         I915_WRITE(GTIIR, I915_READ(GTIIR));
2828         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2829         I915_WRITE(GTIER, gt_irqs);
2830         POSTING_READ(GTIER);
2831
2832         if (INTEL_INFO(dev)->gen >= 6) {
2833                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2834
2835                 if (HAS_VEBOX(dev))
2836                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2837
2838                 dev_priv->pm_irq_mask = 0xffffffff;
2839                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2840                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2841                 I915_WRITE(GEN6_PMIER, pm_irqs);
2842                 POSTING_READ(GEN6_PMIER);
2843         }
2844 }
2845
2846 static int ironlake_irq_postinstall(struct drm_device *dev)
2847 {
2848         unsigned long irqflags;
2849         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2850         u32 display_mask, extra_mask;
2851
2852         if (INTEL_INFO(dev)->gen >= 7) {
2853                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2854                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2855                                 DE_PLANEB_FLIP_DONE_IVB |
2856                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2857                                 DE_ERR_INT_IVB);
2858                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2859                               DE_PIPEA_VBLANK_IVB);
2860
2861                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2862         } else {
2863                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2864                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2865                                 DE_AUX_CHANNEL_A |
2866                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2867                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2868                                 DE_POISON);
2869                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2870         }
2871
2872         dev_priv->irq_mask = ~display_mask;
2873
2874         /* should always can generate irq */
2875         I915_WRITE(DEIIR, I915_READ(DEIIR));
2876         I915_WRITE(DEIMR, dev_priv->irq_mask);
2877         I915_WRITE(DEIER, display_mask | extra_mask);
2878         POSTING_READ(DEIER);
2879
2880         gen5_gt_irq_postinstall(dev);
2881
2882         ibx_irq_postinstall(dev);
2883
2884         if (IS_IRONLAKE_M(dev)) {
2885                 /* Enable PCU event interrupts
2886                  *
2887                  * spinlocking not required here for correctness since interrupt
2888                  * setup is guaranteed to run in single-threaded context. But we
2889                  * need it to make the assert_spin_locked happy. */
2890                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2891                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2892                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2893         }
2894
2895         return 0;
2896 }
2897
2898 static int valleyview_irq_postinstall(struct drm_device *dev)
2899 {
2900         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2901         u32 enable_mask;
2902         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2903                 PIPE_CRC_DONE_ENABLE;
2904         unsigned long irqflags;
2905
2906         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2907         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2908                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2909                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2910                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2911
2912         /*
2913          *Leave vblank interrupts masked initially.  enable/disable will
2914          * toggle them based on usage.
2915          */
2916         dev_priv->irq_mask = (~enable_mask) |
2917                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2918                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2919
2920         I915_WRITE(PORT_HOTPLUG_EN, 0);
2921         POSTING_READ(PORT_HOTPLUG_EN);
2922
2923         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2924         I915_WRITE(VLV_IER, enable_mask);
2925         I915_WRITE(VLV_IIR, 0xffffffff);
2926         I915_WRITE(PIPESTAT(0), 0xffff);
2927         I915_WRITE(PIPESTAT(1), 0xffff);
2928         POSTING_READ(VLV_IER);
2929
2930         /* Interrupt setup is already guaranteed to be single-threaded, this is
2931          * just to make the assert_spin_locked check happy. */
2932         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2933         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2934         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2935         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2936         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2937
2938         I915_WRITE(VLV_IIR, 0xffffffff);
2939         I915_WRITE(VLV_IIR, 0xffffffff);
2940
2941         gen5_gt_irq_postinstall(dev);
2942
2943         /* ack & enable invalid PTE error interrupts */
2944 #if 0 /* FIXME: add support to irq handler for checking these bits */
2945         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2946         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2947 #endif
2948
2949         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2950
2951         return 0;
2952 }
2953
2954 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2955 {
2956         int i;
2957
2958         /* These are interrupts we'll toggle with the ring mask register */
2959         uint32_t gt_interrupts[] = {
2960                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2961                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2962                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2963                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2964                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2965                 0,
2966                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2967                 };
2968
2969         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2970                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2971                 if (tmp)
2972                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2973                                   i, tmp);
2974                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2975                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2976         }
2977         POSTING_READ(GEN8_GT_IER(0));
2978 }
2979
2980 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2981 {
2982         struct drm_device *dev = dev_priv->dev;
2983         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2984                 GEN8_PIPE_CDCLK_CRC_DONE |
2985                 GEN8_PIPE_FIFO_UNDERRUN |
2986                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2987         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
2988         int pipe;
2989         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2990         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2991         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
2992
2993         for_each_pipe(pipe) {
2994                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2995                 if (tmp)
2996                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2997                                   pipe, tmp);
2998                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2999                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3000         }
3001         POSTING_READ(GEN8_DE_PIPE_ISR(0));
3002
3003         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3004         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3005         POSTING_READ(GEN8_DE_PORT_IER);
3006 }
3007
3008 static int gen8_irq_postinstall(struct drm_device *dev)
3009 {
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011
3012         gen8_gt_irq_postinstall(dev_priv);
3013         gen8_de_irq_postinstall(dev_priv);
3014
3015         ibx_irq_postinstall(dev);
3016
3017         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3018         POSTING_READ(GEN8_MASTER_IRQ);
3019
3020         return 0;
3021 }
3022
3023 static void gen8_irq_uninstall(struct drm_device *dev)
3024 {
3025         struct drm_i915_private *dev_priv = dev->dev_private;
3026         int pipe;
3027
3028         if (!dev_priv)
3029                 return;
3030
3031         atomic_set(&dev_priv->irq_received, 0);
3032
3033         I915_WRITE(GEN8_MASTER_IRQ, 0);
3034
3035 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3036                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3037                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3038                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3039         } while (0)
3040
3041 #define GEN8_IRQ_FINI(type) do { \
3042                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3043                 I915_WRITE(GEN8_##type##_IER, 0); \
3044                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3045         } while (0)
3046
3047         GEN8_IRQ_FINI_NDX(GT, 0);
3048         GEN8_IRQ_FINI_NDX(GT, 1);
3049         GEN8_IRQ_FINI_NDX(GT, 2);
3050         GEN8_IRQ_FINI_NDX(GT, 3);
3051
3052         for_each_pipe(pipe) {
3053                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3054         }
3055
3056         GEN8_IRQ_FINI(DE_PORT);
3057         GEN8_IRQ_FINI(DE_MISC);
3058         GEN8_IRQ_FINI(PCU);
3059 #undef GEN8_IRQ_FINI
3060 #undef GEN8_IRQ_FINI_NDX
3061
3062         POSTING_READ(GEN8_PCU_IIR);
3063 }
3064
3065 static void valleyview_irq_uninstall(struct drm_device *dev)
3066 {
3067         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3068         int pipe;
3069
3070         if (!dev_priv)
3071                 return;
3072
3073         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3074
3075         for_each_pipe(pipe)
3076                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3077
3078         I915_WRITE(HWSTAM, 0xffffffff);
3079         I915_WRITE(PORT_HOTPLUG_EN, 0);
3080         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3081         for_each_pipe(pipe)
3082                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3083         I915_WRITE(VLV_IIR, 0xffffffff);
3084         I915_WRITE(VLV_IMR, 0xffffffff);
3085         I915_WRITE(VLV_IER, 0x0);
3086         POSTING_READ(VLV_IER);
3087 }
3088
3089 static void ironlake_irq_uninstall(struct drm_device *dev)
3090 {
3091         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3092
3093         if (!dev_priv)
3094                 return;
3095
3096         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3097
3098         I915_WRITE(HWSTAM, 0xffffffff);
3099
3100         I915_WRITE(DEIMR, 0xffffffff);
3101         I915_WRITE(DEIER, 0x0);
3102         I915_WRITE(DEIIR, I915_READ(DEIIR));
3103         if (IS_GEN7(dev))
3104                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3105
3106         I915_WRITE(GTIMR, 0xffffffff);
3107         I915_WRITE(GTIER, 0x0);
3108         I915_WRITE(GTIIR, I915_READ(GTIIR));
3109
3110         if (HAS_PCH_NOP(dev))
3111                 return;
3112
3113         I915_WRITE(SDEIMR, 0xffffffff);
3114         I915_WRITE(SDEIER, 0x0);
3115         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3116         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3117                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3118 }
3119
3120 static void i8xx_irq_preinstall(struct drm_device * dev)
3121 {
3122         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3123         int pipe;
3124
3125         atomic_set(&dev_priv->irq_received, 0);
3126
3127         for_each_pipe(pipe)
3128                 I915_WRITE(PIPESTAT(pipe), 0);
3129         I915_WRITE16(IMR, 0xffff);
3130         I915_WRITE16(IER, 0x0);
3131         POSTING_READ16(IER);
3132 }
3133
3134 static int i8xx_irq_postinstall(struct drm_device *dev)
3135 {
3136         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3137         unsigned long irqflags;
3138
3139         I915_WRITE16(EMR,
3140                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3141
3142         /* Unmask the interrupts that we always want on. */
3143         dev_priv->irq_mask =
3144                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3145                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3146                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3147                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3148                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3149         I915_WRITE16(IMR, dev_priv->irq_mask);
3150
3151         I915_WRITE16(IER,
3152                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3153                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3154                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3155                      I915_USER_INTERRUPT);
3156         POSTING_READ16(IER);
3157
3158         /* Interrupt setup is already guaranteed to be single-threaded, this is
3159          * just to make the assert_spin_locked check happy. */
3160         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3161         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3162         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3163         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3164
3165         return 0;
3166 }
3167
3168 /*
3169  * Returns true when a page flip has completed.
3170  */
3171 static bool i8xx_handle_vblank(struct drm_device *dev,
3172                                int plane, int pipe, u32 iir)
3173 {
3174         drm_i915_private_t *dev_priv = dev->dev_private;
3175         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3176
3177         if (!drm_handle_vblank(dev, pipe))
3178                 return false;
3179
3180         if ((iir & flip_pending) == 0)
3181                 return false;
3182
3183         intel_prepare_page_flip(dev, plane);
3184
3185         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3186          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3187          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3188          * the flip is completed (no longer pending). Since this doesn't raise
3189          * an interrupt per se, we watch for the change at vblank.
3190          */
3191         if (I915_READ16(ISR) & flip_pending)
3192                 return false;
3193
3194         intel_finish_page_flip(dev, pipe);
3195
3196         return true;
3197 }
3198
3199 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3200 {
3201         struct drm_device *dev = (struct drm_device *) arg;
3202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3203         u16 iir, new_iir;
3204         u32 pipe_stats[2];
3205         unsigned long irqflags;
3206         int pipe;
3207         u16 flip_mask =
3208                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3209                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3210
3211         atomic_inc(&dev_priv->irq_received);
3212
3213         iir = I915_READ16(IIR);
3214         if (iir == 0)
3215                 return IRQ_NONE;
3216
3217         while (iir & ~flip_mask) {
3218                 /* Can't rely on pipestat interrupt bit in iir as it might
3219                  * have been cleared after the pipestat interrupt was received.
3220                  * It doesn't set the bit in iir again, but it still produces
3221                  * interrupts (for non-MSI).
3222                  */
3223                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3224                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3225                         i915_handle_error(dev, false);
3226
3227                 for_each_pipe(pipe) {
3228                         int reg = PIPESTAT(pipe);
3229                         pipe_stats[pipe] = I915_READ(reg);
3230
3231                         /*
3232                          * Clear the PIPE*STAT regs before the IIR
3233                          */
3234                         if (pipe_stats[pipe] & 0x8000ffff) {
3235                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3236                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3237                                                          pipe_name(pipe));
3238                                 I915_WRITE(reg, pipe_stats[pipe]);
3239                         }
3240                 }
3241                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3242
3243                 I915_WRITE16(IIR, iir & ~flip_mask);
3244                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3245
3246                 i915_update_dri1_breadcrumb(dev);
3247
3248                 if (iir & I915_USER_INTERRUPT)
3249                         notify_ring(dev, &dev_priv->ring[RCS]);
3250
3251                 for_each_pipe(pipe) {
3252                         int plane = pipe;
3253                         if (HAS_FBC(dev))
3254                                 plane = !plane;
3255
3256                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3257                             i8xx_handle_vblank(dev, plane, pipe, iir))
3258                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3259
3260                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3261                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3262                 }
3263
3264                 iir = new_iir;
3265         }
3266
3267         return IRQ_HANDLED;
3268 }
3269
3270 static void i8xx_irq_uninstall(struct drm_device * dev)
3271 {
3272         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3273         int pipe;
3274
3275         for_each_pipe(pipe) {
3276                 /* Clear enable bits; then clear status bits */
3277                 I915_WRITE(PIPESTAT(pipe), 0);
3278                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3279         }
3280         I915_WRITE16(IMR, 0xffff);
3281         I915_WRITE16(IER, 0x0);
3282         I915_WRITE16(IIR, I915_READ16(IIR));
3283 }
3284
3285 static void i915_irq_preinstall(struct drm_device * dev)
3286 {
3287         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3288         int pipe;
3289
3290         atomic_set(&dev_priv->irq_received, 0);
3291
3292         if (I915_HAS_HOTPLUG(dev)) {
3293                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3294                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3295         }
3296
3297         I915_WRITE16(HWSTAM, 0xeffe);
3298         for_each_pipe(pipe)
3299                 I915_WRITE(PIPESTAT(pipe), 0);
3300         I915_WRITE(IMR, 0xffffffff);
3301         I915_WRITE(IER, 0x0);
3302         POSTING_READ(IER);
3303 }
3304
3305 static int i915_irq_postinstall(struct drm_device *dev)
3306 {
3307         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3308         u32 enable_mask;
3309         unsigned long irqflags;
3310
3311         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3312
3313         /* Unmask the interrupts that we always want on. */
3314         dev_priv->irq_mask =
3315                 ~(I915_ASLE_INTERRUPT |
3316                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3317                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3318                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3319                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3320                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3321
3322         enable_mask =
3323                 I915_ASLE_INTERRUPT |
3324                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3325                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3326                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3327                 I915_USER_INTERRUPT;
3328
3329         if (I915_HAS_HOTPLUG(dev)) {
3330                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3331                 POSTING_READ(PORT_HOTPLUG_EN);
3332
3333                 /* Enable in IER... */
3334                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3335                 /* and unmask in IMR */
3336                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3337         }
3338
3339         I915_WRITE(IMR, dev_priv->irq_mask);
3340         I915_WRITE(IER, enable_mask);
3341         POSTING_READ(IER);
3342
3343         i915_enable_asle_pipestat(dev);
3344
3345         /* Interrupt setup is already guaranteed to be single-threaded, this is
3346          * just to make the assert_spin_locked check happy. */
3347         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3348         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3349         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3350         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3351
3352         return 0;
3353 }
3354
3355 /*
3356  * Returns true when a page flip has completed.
3357  */
3358 static bool i915_handle_vblank(struct drm_device *dev,
3359                                int plane, int pipe, u32 iir)
3360 {
3361         drm_i915_private_t *dev_priv = dev->dev_private;
3362         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3363
3364         if (!drm_handle_vblank(dev, pipe))
3365                 return false;
3366
3367         if ((iir & flip_pending) == 0)
3368                 return false;
3369
3370         intel_prepare_page_flip(dev, plane);
3371
3372         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3373          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3374          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3375          * the flip is completed (no longer pending). Since this doesn't raise
3376          * an interrupt per se, we watch for the change at vblank.
3377          */
3378         if (I915_READ(ISR) & flip_pending)
3379                 return false;
3380
3381         intel_finish_page_flip(dev, pipe);
3382
3383         return true;
3384 }
3385
3386 static irqreturn_t i915_irq_handler(int irq, void *arg)
3387 {
3388         struct drm_device *dev = (struct drm_device *) arg;
3389         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3390         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3391         unsigned long irqflags;
3392         u32 flip_mask =
3393                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3394                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3395         int pipe, ret = IRQ_NONE;
3396
3397         atomic_inc(&dev_priv->irq_received);
3398
3399         iir = I915_READ(IIR);
3400         do {
3401                 bool irq_received = (iir & ~flip_mask) != 0;
3402                 bool blc_event = false;
3403
3404                 /* Can't rely on pipestat interrupt bit in iir as it might
3405                  * have been cleared after the pipestat interrupt was received.
3406                  * It doesn't set the bit in iir again, but it still produces
3407                  * interrupts (for non-MSI).
3408                  */
3409                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3410                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3411                         i915_handle_error(dev, false);
3412
3413                 for_each_pipe(pipe) {
3414                         int reg = PIPESTAT(pipe);
3415                         pipe_stats[pipe] = I915_READ(reg);
3416
3417                         /* Clear the PIPE*STAT regs before the IIR */
3418                         if (pipe_stats[pipe] & 0x8000ffff) {
3419                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3420                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3421                                                          pipe_name(pipe));
3422                                 I915_WRITE(reg, pipe_stats[pipe]);
3423                                 irq_received = true;
3424                         }
3425                 }
3426                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3427
3428                 if (!irq_received)
3429                         break;
3430
3431                 /* Consume port.  Then clear IIR or we'll miss events */
3432                 if ((I915_HAS_HOTPLUG(dev)) &&
3433                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3434                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3435                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3436
3437                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3438                                   hotplug_status);
3439
3440                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3441
3442                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3443                         POSTING_READ(PORT_HOTPLUG_STAT);
3444                 }
3445
3446                 I915_WRITE(IIR, iir & ~flip_mask);
3447                 new_iir = I915_READ(IIR); /* Flush posted writes */
3448
3449                 if (iir & I915_USER_INTERRUPT)
3450                         notify_ring(dev, &dev_priv->ring[RCS]);
3451
3452                 for_each_pipe(pipe) {
3453                         int plane = pipe;
3454                         if (HAS_FBC(dev))
3455                                 plane = !plane;
3456
3457                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3458                             i915_handle_vblank(dev, plane, pipe, iir))
3459                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3460
3461                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3462                                 blc_event = true;
3463
3464                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3465                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3466                 }
3467
3468                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3469                         intel_opregion_asle_intr(dev);
3470
3471                 /* With MSI, interrupts are only generated when iir
3472                  * transitions from zero to nonzero.  If another bit got
3473                  * set while we were handling the existing iir bits, then
3474                  * we would never get another interrupt.
3475                  *
3476                  * This is fine on non-MSI as well, as if we hit this path
3477                  * we avoid exiting the interrupt handler only to generate
3478                  * another one.
3479                  *
3480                  * Note that for MSI this could cause a stray interrupt report
3481                  * if an interrupt landed in the time between writing IIR and
3482                  * the posting read.  This should be rare enough to never
3483                  * trigger the 99% of 100,000 interrupts test for disabling
3484                  * stray interrupts.
3485                  */
3486                 ret = IRQ_HANDLED;
3487                 iir = new_iir;
3488         } while (iir & ~flip_mask);
3489
3490         i915_update_dri1_breadcrumb(dev);
3491
3492         return ret;
3493 }
3494
3495 static void i915_irq_uninstall(struct drm_device * dev)
3496 {
3497         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3498         int pipe;
3499
3500         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3501
3502         if (I915_HAS_HOTPLUG(dev)) {
3503                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3504                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3505         }
3506
3507         I915_WRITE16(HWSTAM, 0xffff);
3508         for_each_pipe(pipe) {
3509                 /* Clear enable bits; then clear status bits */
3510                 I915_WRITE(PIPESTAT(pipe), 0);
3511                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3512         }
3513         I915_WRITE(IMR, 0xffffffff);
3514         I915_WRITE(IER, 0x0);
3515
3516         I915_WRITE(IIR, I915_READ(IIR));
3517 }
3518
3519 static void i965_irq_preinstall(struct drm_device * dev)
3520 {
3521         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3522         int pipe;
3523
3524         atomic_set(&dev_priv->irq_received, 0);
3525
3526         I915_WRITE(PORT_HOTPLUG_EN, 0);
3527         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3528
3529         I915_WRITE(HWSTAM, 0xeffe);
3530         for_each_pipe(pipe)
3531                 I915_WRITE(PIPESTAT(pipe), 0);
3532         I915_WRITE(IMR, 0xffffffff);
3533         I915_WRITE(IER, 0x0);
3534         POSTING_READ(IER);
3535 }
3536
3537 static int i965_irq_postinstall(struct drm_device *dev)
3538 {
3539         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3540         u32 enable_mask;
3541         u32 error_mask;
3542         unsigned long irqflags;
3543
3544         /* Unmask the interrupts that we always want on. */
3545         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3546                                I915_DISPLAY_PORT_INTERRUPT |
3547                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3548                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3549                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3550                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3551                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3552
3553         enable_mask = ~dev_priv->irq_mask;
3554         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3555                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3556         enable_mask |= I915_USER_INTERRUPT;
3557
3558         if (IS_G4X(dev))
3559                 enable_mask |= I915_BSD_USER_INTERRUPT;
3560
3561         /* Interrupt setup is already guaranteed to be single-threaded, this is
3562          * just to make the assert_spin_locked check happy. */
3563         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3564         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3565         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3566         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3567         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3568
3569         /*
3570          * Enable some error detection, note the instruction error mask
3571          * bit is reserved, so we leave it masked.
3572          */
3573         if (IS_G4X(dev)) {
3574                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3575                                GM45_ERROR_MEM_PRIV |
3576                                GM45_ERROR_CP_PRIV |
3577                                I915_ERROR_MEMORY_REFRESH);
3578         } else {
3579                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3580                                I915_ERROR_MEMORY_REFRESH);
3581         }
3582         I915_WRITE(EMR, error_mask);
3583
3584         I915_WRITE(IMR, dev_priv->irq_mask);
3585         I915_WRITE(IER, enable_mask);
3586         POSTING_READ(IER);
3587
3588         I915_WRITE(PORT_HOTPLUG_EN, 0);
3589         POSTING_READ(PORT_HOTPLUG_EN);
3590
3591         i915_enable_asle_pipestat(dev);
3592
3593         return 0;
3594 }
3595
3596 static void i915_hpd_irq_setup(struct drm_device *dev)
3597 {
3598         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3599         struct drm_mode_config *mode_config = &dev->mode_config;
3600         struct intel_encoder *intel_encoder;
3601         u32 hotplug_en;
3602
3603         assert_spin_locked(&dev_priv->irq_lock);
3604
3605         if (I915_HAS_HOTPLUG(dev)) {
3606                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3607                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3608                 /* Note HDMI and DP share hotplug bits */
3609                 /* enable bits are the same for all generations */
3610                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3611                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3612                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3613                 /* Programming the CRT detection parameters tends
3614                    to generate a spurious hotplug event about three
3615                    seconds later.  So just do it once.
3616                 */
3617                 if (IS_G4X(dev))
3618                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3619                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3620                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3621
3622                 /* Ignore TV since it's buggy */
3623                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3624         }
3625 }
3626
3627 static irqreturn_t i965_irq_handler(int irq, void *arg)
3628 {
3629         struct drm_device *dev = (struct drm_device *) arg;
3630         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3631         u32 iir, new_iir;
3632         u32 pipe_stats[I915_MAX_PIPES];
3633         unsigned long irqflags;
3634         int irq_received;
3635         int ret = IRQ_NONE, pipe;
3636         u32 flip_mask =
3637                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3638                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3639
3640         atomic_inc(&dev_priv->irq_received);
3641
3642         iir = I915_READ(IIR);
3643
3644         for (;;) {
3645                 bool blc_event = false;
3646
3647                 irq_received = (iir & ~flip_mask) != 0;
3648
3649                 /* Can't rely on pipestat interrupt bit in iir as it might
3650                  * have been cleared after the pipestat interrupt was received.
3651                  * It doesn't set the bit in iir again, but it still produces
3652                  * interrupts (for non-MSI).
3653                  */
3654                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3655                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3656                         i915_handle_error(dev, false);
3657
3658                 for_each_pipe(pipe) {
3659                         int reg = PIPESTAT(pipe);
3660                         pipe_stats[pipe] = I915_READ(reg);
3661
3662                         /*
3663                          * Clear the PIPE*STAT regs before the IIR
3664                          */
3665                         if (pipe_stats[pipe] & 0x8000ffff) {
3666                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3667                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3668                                                          pipe_name(pipe));
3669                                 I915_WRITE(reg, pipe_stats[pipe]);
3670                                 irq_received = 1;
3671                         }
3672                 }
3673                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3674
3675                 if (!irq_received)
3676                         break;
3677
3678                 ret = IRQ_HANDLED;
3679
3680                 /* Consume port.  Then clear IIR or we'll miss events */
3681                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3682                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3683                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3684                                                                   HOTPLUG_INT_STATUS_G4X :
3685                                                                   HOTPLUG_INT_STATUS_I915);
3686
3687                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3688                                   hotplug_status);
3689
3690                         intel_hpd_irq_handler(dev, hotplug_trigger,
3691                                               IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3692
3693                         if (IS_G4X(dev) &&
3694                             (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3695                                 dp_aux_irq_handler(dev);
3696
3697                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3698                         I915_READ(PORT_HOTPLUG_STAT);
3699                 }
3700
3701                 I915_WRITE(IIR, iir & ~flip_mask);
3702                 new_iir = I915_READ(IIR); /* Flush posted writes */
3703
3704                 if (iir & I915_USER_INTERRUPT)
3705                         notify_ring(dev, &dev_priv->ring[RCS]);
3706                 if (iir & I915_BSD_USER_INTERRUPT)
3707                         notify_ring(dev, &dev_priv->ring[VCS]);
3708
3709                 for_each_pipe(pipe) {
3710                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3711                             i915_handle_vblank(dev, pipe, pipe, iir))
3712                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3713
3714                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3715                                 blc_event = true;
3716
3717                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3718                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3719                 }
3720
3721
3722                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3723                         intel_opregion_asle_intr(dev);
3724
3725                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3726                         gmbus_irq_handler(dev);
3727
3728                 /* With MSI, interrupts are only generated when iir
3729                  * transitions from zero to nonzero.  If another bit got
3730                  * set while we were handling the existing iir bits, then
3731                  * we would never get another interrupt.
3732                  *
3733                  * This is fine on non-MSI as well, as if we hit this path
3734                  * we avoid exiting the interrupt handler only to generate
3735                  * another one.
3736                  *
3737                  * Note that for MSI this could cause a stray interrupt report
3738                  * if an interrupt landed in the time between writing IIR and
3739                  * the posting read.  This should be rare enough to never
3740                  * trigger the 99% of 100,000 interrupts test for disabling
3741                  * stray interrupts.
3742                  */
3743                 iir = new_iir;
3744         }
3745
3746         i915_update_dri1_breadcrumb(dev);
3747
3748         return ret;
3749 }
3750
3751 static void i965_irq_uninstall(struct drm_device * dev)
3752 {
3753         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3754         int pipe;
3755
3756         if (!dev_priv)
3757                 return;
3758
3759         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3760
3761         I915_WRITE(PORT_HOTPLUG_EN, 0);
3762         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3763
3764         I915_WRITE(HWSTAM, 0xffffffff);
3765         for_each_pipe(pipe)
3766                 I915_WRITE(PIPESTAT(pipe), 0);
3767         I915_WRITE(IMR, 0xffffffff);
3768         I915_WRITE(IER, 0x0);
3769
3770         for_each_pipe(pipe)
3771                 I915_WRITE(PIPESTAT(pipe),
3772                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3773         I915_WRITE(IIR, I915_READ(IIR));
3774 }
3775
3776 static void i915_reenable_hotplug_timer_func(unsigned long data)
3777 {
3778         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3779         struct drm_device *dev = dev_priv->dev;
3780         struct drm_mode_config *mode_config = &dev->mode_config;
3781         unsigned long irqflags;
3782         int i;
3783
3784         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3785         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3786                 struct drm_connector *connector;
3787
3788                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3789                         continue;
3790
3791                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3792
3793                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3794                         struct intel_connector *intel_connector = to_intel_connector(connector);
3795
3796                         if (intel_connector->encoder->hpd_pin == i) {
3797                                 if (connector->polled != intel_connector->polled)
3798                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3799                                                          drm_get_connector_name(connector));
3800                                 connector->polled = intel_connector->polled;
3801                                 if (!connector->polled)
3802                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3803                         }
3804                 }
3805         }
3806         if (dev_priv->display.hpd_irq_setup)
3807                 dev_priv->display.hpd_irq_setup(dev);
3808         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3809 }
3810
3811 void intel_irq_init(struct drm_device *dev)
3812 {
3813         struct drm_i915_private *dev_priv = dev->dev_private;
3814
3815         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3816         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3817         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3818         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3819
3820         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3821                     i915_hangcheck_elapsed,
3822                     (unsigned long) dev);
3823         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3824                     (unsigned long) dev_priv);
3825
3826         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3827
3828         if (IS_GEN2(dev)) {
3829                 dev->max_vblank_count = 0;
3830                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3831         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3832                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3833                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3834         } else {
3835                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3836                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3837         }
3838
3839         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3840                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3841                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3842         }
3843
3844         if (IS_VALLEYVIEW(dev)) {
3845                 dev->driver->irq_handler = valleyview_irq_handler;
3846                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3847                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3848                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3849                 dev->driver->enable_vblank = valleyview_enable_vblank;
3850                 dev->driver->disable_vblank = valleyview_disable_vblank;
3851                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3852         } else if (IS_GEN8(dev)) {
3853                 dev->driver->irq_handler = gen8_irq_handler;
3854                 dev->driver->irq_preinstall = gen8_irq_preinstall;
3855                 dev->driver->irq_postinstall = gen8_irq_postinstall;
3856                 dev->driver->irq_uninstall = gen8_irq_uninstall;
3857                 dev->driver->enable_vblank = gen8_enable_vblank;
3858                 dev->driver->disable_vblank = gen8_disable_vblank;
3859                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3860         } else if (HAS_PCH_SPLIT(dev)) {
3861                 dev->driver->irq_handler = ironlake_irq_handler;
3862                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3863                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3864                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3865                 dev->driver->enable_vblank = ironlake_enable_vblank;
3866                 dev->driver->disable_vblank = ironlake_disable_vblank;
3867                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3868         } else {
3869                 if (INTEL_INFO(dev)->gen == 2) {
3870                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3871                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3872                         dev->driver->irq_handler = i8xx_irq_handler;
3873                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3874                 } else if (INTEL_INFO(dev)->gen == 3) {
3875                         dev->driver->irq_preinstall = i915_irq_preinstall;
3876                         dev->driver->irq_postinstall = i915_irq_postinstall;
3877                         dev->driver->irq_uninstall = i915_irq_uninstall;
3878                         dev->driver->irq_handler = i915_irq_handler;
3879                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3880                 } else {
3881                         dev->driver->irq_preinstall = i965_irq_preinstall;
3882                         dev->driver->irq_postinstall = i965_irq_postinstall;
3883                         dev->driver->irq_uninstall = i965_irq_uninstall;
3884                         dev->driver->irq_handler = i965_irq_handler;
3885                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3886                 }
3887                 dev->driver->enable_vblank = i915_enable_vblank;
3888                 dev->driver->disable_vblank = i915_disable_vblank;
3889         }
3890 }
3891
3892 void intel_hpd_init(struct drm_device *dev)
3893 {
3894         struct drm_i915_private *dev_priv = dev->dev_private;
3895         struct drm_mode_config *mode_config = &dev->mode_config;
3896         struct drm_connector *connector;
3897         unsigned long irqflags;
3898         int i;
3899
3900         for (i = 1; i < HPD_NUM_PINS; i++) {
3901                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3902                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3903         }
3904         list_for_each_entry(connector, &mode_config->connector_list, head) {
3905                 struct intel_connector *intel_connector = to_intel_connector(connector);
3906                 connector->polled = intel_connector->polled;
3907                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3908                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3909         }
3910
3911         /* Interrupt setup is already guaranteed to be single-threaded, this is
3912          * just to make the assert_spin_locked checks happy. */
3913         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3914         if (dev_priv->display.hpd_irq_setup)
3915                 dev_priv->display.hpd_irq_setup(dev);
3916         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3917 }
3918
3919 /* Disable interrupts so we can allow Package C8+. */
3920 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3921 {
3922         struct drm_i915_private *dev_priv = dev->dev_private;
3923         unsigned long irqflags;
3924
3925         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3926
3927         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3928         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3929         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3930         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3931         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3932
3933         ironlake_disable_display_irq(dev_priv, 0xffffffff);
3934         ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3935         ilk_disable_gt_irq(dev_priv, 0xffffffff);
3936         snb_disable_pm_irq(dev_priv, 0xffffffff);
3937
3938         dev_priv->pc8.irqs_disabled = true;
3939
3940         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3941 }
3942
3943 /* Restore interrupts so we can recover from Package C8+. */
3944 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3945 {
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         unsigned long irqflags;
3948         uint32_t val;
3949
3950         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3951
3952         val = I915_READ(DEIMR);
3953         WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3954
3955         val = I915_READ(SDEIMR);
3956         WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3957
3958         val = I915_READ(GTIMR);
3959         WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3960
3961         val = I915_READ(GEN6_PMIMR);
3962         WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3963
3964         dev_priv->pc8.irqs_disabled = false;
3965
3966         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3967         ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3968         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3969         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3970         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3971
3972         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3973 }