1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
40 static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
48 static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
56 static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
65 static const u32 hpd_status_g4x[] = {
66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
83 /* For display hotplug interrupt */
85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
87 assert_spin_locked(&dev_priv->irq_lock);
89 if (dev_priv->pc8.irqs_disabled) {
90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask;
95 if ((dev_priv->irq_mask & mask) != 0) {
96 dev_priv->irq_mask &= ~mask;
97 I915_WRITE(DEIMR, dev_priv->irq_mask);
103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
105 assert_spin_locked(&dev_priv->irq_lock);
107 if (dev_priv->pc8.irqs_disabled) {
108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask;
113 if ((dev_priv->irq_mask & mask) != mask) {
114 dev_priv->irq_mask |= mask;
115 I915_WRITE(DEIMR, dev_priv->irq_mask);
121 * ilk_update_gt_irq - update GTIMR
122 * @dev_priv: driver private
123 * @interrupt_mask: mask of interrupt bits to update
124 * @enabled_irq_mask: mask of interrupt bits to enable
126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
127 uint32_t interrupt_mask,
128 uint32_t enabled_irq_mask)
130 assert_spin_locked(&dev_priv->irq_lock);
132 if (dev_priv->pc8.irqs_disabled) {
133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
140 dev_priv->gt_irq_mask &= ~interrupt_mask;
141 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
142 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
148 ilk_update_gt_irq(dev_priv, mask, mask);
151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
153 ilk_update_gt_irq(dev_priv, mask, 0);
157 * snb_update_pm_irq - update GEN6_PMIMR
158 * @dev_priv: driver private
159 * @interrupt_mask: mask of interrupt bits to update
160 * @enabled_irq_mask: mask of interrupt bits to enable
162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
163 uint32_t interrupt_mask,
164 uint32_t enabled_irq_mask)
168 assert_spin_locked(&dev_priv->irq_lock);
170 if (dev_priv->pc8.irqs_disabled) {
171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
178 new_val = dev_priv->pm_irq_mask;
179 new_val &= ~interrupt_mask;
180 new_val |= (~enabled_irq_mask & interrupt_mask);
182 if (new_val != dev_priv->pm_irq_mask) {
183 dev_priv->pm_irq_mask = new_val;
184 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
185 POSTING_READ(GEN6_PMIMR);
189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
191 snb_update_pm_irq(dev_priv, mask, mask);
194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
196 snb_update_pm_irq(dev_priv, mask, 0);
199 static bool ivb_can_enable_err_int(struct drm_device *dev)
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_crtc *crtc;
205 assert_spin_locked(&dev_priv->irq_lock);
207 for_each_pipe(pipe) {
208 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
210 if (crtc->cpu_fifo_underrun_disabled)
217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
219 struct drm_i915_private *dev_priv = dev->dev_private;
221 struct intel_crtc *crtc;
223 assert_spin_locked(&dev_priv->irq_lock);
225 for_each_pipe(pipe) {
226 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
228 if (crtc->pch_fifo_underrun_disabled)
235 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
236 enum pipe pipe, bool enable)
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
240 DE_PIPEB_FIFO_UNDERRUN;
243 ironlake_enable_display_irq(dev_priv, bit);
245 ironlake_disable_display_irq(dev_priv, bit);
248 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
249 enum pipe pipe, bool enable)
251 struct drm_i915_private *dev_priv = dev->dev_private;
253 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
255 if (!ivb_can_enable_err_int(dev))
258 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
260 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
262 /* Change the state _after_ we've read out the current one. */
263 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
266 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
267 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
273 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
274 enum pipe pipe, bool enable)
276 struct drm_i915_private *dev_priv = dev->dev_private;
278 assert_spin_locked(&dev_priv->irq_lock);
281 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
283 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
284 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
285 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
289 * ibx_display_interrupt_update - update SDEIMR
290 * @dev_priv: driver private
291 * @interrupt_mask: mask of interrupt bits to update
292 * @enabled_irq_mask: mask of interrupt bits to enable
294 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
295 uint32_t interrupt_mask,
296 uint32_t enabled_irq_mask)
298 uint32_t sdeimr = I915_READ(SDEIMR);
299 sdeimr &= ~interrupt_mask;
300 sdeimr |= (~enabled_irq_mask & interrupt_mask);
302 assert_spin_locked(&dev_priv->irq_lock);
304 if (dev_priv->pc8.irqs_disabled &&
305 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
306 WARN(1, "IRQs disabled\n");
307 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
308 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
313 I915_WRITE(SDEIMR, sdeimr);
314 POSTING_READ(SDEIMR);
316 #define ibx_enable_display_interrupt(dev_priv, bits) \
317 ibx_display_interrupt_update((dev_priv), (bits), (bits))
318 #define ibx_disable_display_interrupt(dev_priv, bits) \
319 ibx_display_interrupt_update((dev_priv), (bits), 0)
321 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
322 enum transcoder pch_transcoder,
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
327 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
330 ibx_enable_display_interrupt(dev_priv, bit);
332 ibx_disable_display_interrupt(dev_priv, bit);
335 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
336 enum transcoder pch_transcoder,
339 struct drm_i915_private *dev_priv = dev->dev_private;
343 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
345 if (!cpt_can_enable_serr_int(dev))
348 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
350 uint32_t tmp = I915_READ(SERR_INT);
351 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
353 /* Change the state _after_ we've read out the current one. */
354 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
357 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
358 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
359 transcoder_name(pch_transcoder));
365 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
368 * @enable: true if we want to report FIFO underrun errors, false otherwise
370 * This function makes us disable or enable CPU fifo underruns for a specific
371 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
372 * reporting for one pipe may also disable all the other CPU error interruts for
373 * the other pipes, due to the fact that there's just one interrupt mask/enable
374 * bit for all the pipes.
376 * Returns the previous state of underrun reporting.
378 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
379 enum pipe pipe, bool enable)
381 struct drm_i915_private *dev_priv = dev->dev_private;
382 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
387 spin_lock_irqsave(&dev_priv->irq_lock, flags);
389 ret = !intel_crtc->cpu_fifo_underrun_disabled;
394 intel_crtc->cpu_fifo_underrun_disabled = !enable;
396 if (IS_GEN5(dev) || IS_GEN6(dev))
397 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
398 else if (IS_GEN7(dev))
399 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
400 else if (IS_GEN8(dev))
401 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
404 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
409 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
411 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
412 * @enable: true if we want to report FIFO underrun errors, false otherwise
414 * This function makes us disable or enable PCH fifo underruns for a specific
415 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
416 * underrun reporting for one transcoder may also disable all the other PCH
417 * error interruts for the other transcoders, due to the fact that there's just
418 * one interrupt mask/enable bit for all the transcoders.
420 * Returns the previous state of underrun reporting.
422 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
423 enum transcoder pch_transcoder,
426 struct drm_i915_private *dev_priv = dev->dev_private;
427 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
433 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
434 * has only one pch transcoder A that all pipes can use. To avoid racy
435 * pch transcoder -> pipe lookups from interrupt code simply store the
436 * underrun statistics in crtc A. Since we never expose this anywhere
437 * nor use it outside of the fifo underrun code here using the "wrong"
438 * crtc on LPT won't cause issues.
441 spin_lock_irqsave(&dev_priv->irq_lock, flags);
443 ret = !intel_crtc->pch_fifo_underrun_disabled;
448 intel_crtc->pch_fifo_underrun_disabled = !enable;
450 if (HAS_PCH_IBX(dev))
451 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
453 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
456 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
462 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
464 u32 reg = PIPESTAT(pipe);
465 u32 pipestat = I915_READ(reg) & 0x7fff0000;
467 assert_spin_locked(&dev_priv->irq_lock);
469 if ((pipestat & mask) == mask)
472 /* Enable the interrupt, clear any pending status */
473 pipestat |= mask | (mask >> 16);
474 I915_WRITE(reg, pipestat);
479 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask)
481 u32 reg = PIPESTAT(pipe);
482 u32 pipestat = I915_READ(reg) & 0x7fff0000;
484 assert_spin_locked(&dev_priv->irq_lock);
486 if ((pipestat & mask) == 0)
490 I915_WRITE(reg, pipestat);
495 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
497 static void i915_enable_asle_pipestat(struct drm_device *dev)
499 drm_i915_private_t *dev_priv = dev->dev_private;
500 unsigned long irqflags;
502 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
507 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE);
508 if (INTEL_INFO(dev)->gen >= 4)
509 i915_enable_pipestat(dev_priv, PIPE_A,
510 PIPE_LEGACY_BLC_EVENT_ENABLE);
512 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
516 * i915_pipe_enabled - check if a pipe is enabled
518 * @pipe: pipe to check
520 * Reading certain registers when the pipe is disabled can hang the chip.
521 * Use this routine to make sure the PLL is running and the pipe is active
522 * before reading such registers if unsure.
525 i915_pipe_enabled(struct drm_device *dev, int pipe)
527 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
529 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
530 /* Locking is horribly broken here, but whatever. */
531 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
534 return intel_crtc->active;
536 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
540 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
542 /* Gen2 doesn't have a hardware frame counter */
546 /* Called from drm generic code, passed a 'crtc', which
547 * we use as a pipe index
549 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
551 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
552 unsigned long high_frame;
553 unsigned long low_frame;
554 u32 high1, high2, low, pixel, vbl_start;
556 if (!i915_pipe_enabled(dev, pipe)) {
557 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
558 "pipe %c\n", pipe_name(pipe));
562 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
563 struct intel_crtc *intel_crtc =
564 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
565 const struct drm_display_mode *mode =
566 &intel_crtc->config.adjusted_mode;
568 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
570 enum transcoder cpu_transcoder = (enum transcoder) pipe;
573 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
574 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
579 high_frame = PIPEFRAME(pipe);
580 low_frame = PIPEFRAMEPIXEL(pipe);
583 * High & low register fields aren't synchronized, so make sure
584 * we get a low value that's stable across two reads of the high
588 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
589 low = I915_READ(low_frame);
590 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
591 } while (high1 != high2);
593 high1 >>= PIPE_FRAME_HIGH_SHIFT;
594 pixel = low & PIPE_PIXEL_MASK;
595 low >>= PIPE_FRAME_LOW_SHIFT;
598 * The frame counter increments at beginning of active.
599 * Cook up a vblank counter by also checking the pixel
600 * counter against vblank start.
602 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
605 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
608 int reg = PIPE_FRMCOUNT_GM45(pipe);
610 if (!i915_pipe_enabled(dev, pipe)) {
611 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
612 "pipe %c\n", pipe_name(pipe));
616 return I915_READ(reg);
619 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
620 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
621 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
623 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
625 struct drm_i915_private *dev_priv = dev->dev_private;
628 if (INTEL_INFO(dev)->gen < 7) {
629 status = pipe == PIPE_A ?
636 status = DE_PIPEA_VBLANK_IVB;
639 status = DE_PIPEB_VBLANK_IVB;
642 status = DE_PIPEC_VBLANK_IVB;
647 return __raw_i915_read32(dev_priv, DEISR) & status;
650 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
651 unsigned int flags, int *vpos, int *hpos,
652 ktime_t *stime, ktime_t *etime)
654 struct drm_i915_private *dev_priv = dev->dev_private;
655 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
657 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
659 int vbl_start, vbl_end, htotal, vtotal;
662 unsigned long irqflags;
664 if (!intel_crtc->active) {
665 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
666 "pipe %c\n", pipe_name(pipe));
670 htotal = mode->crtc_htotal;
671 vtotal = mode->crtc_vtotal;
672 vbl_start = mode->crtc_vblank_start;
673 vbl_end = mode->crtc_vblank_end;
675 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
676 vbl_start = DIV_ROUND_UP(vbl_start, 2);
681 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
684 * Lock uncore.lock, as we will do multiple timing critical raw
685 * register reads, potentially with preemption disabled, so the
686 * following code must not block on uncore.lock.
688 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
690 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
692 /* Get optional system timestamp before query. */
694 *stime = ktime_get();
696 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
697 /* No obvious pixelcount register. Only query vertical
698 * scanout position from Display scan line register.
701 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
703 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
705 if (HAS_PCH_SPLIT(dev)) {
707 * The scanline counter increments at the leading edge
708 * of hsync, ie. it completely misses the active portion
709 * of the line. Fix up the counter at both edges of vblank
710 * to get a more accurate picture whether we're in vblank
713 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
714 if ((in_vbl && position == vbl_start - 1) ||
715 (!in_vbl && position == vbl_end - 1))
716 position = (position + 1) % vtotal;
719 * ISR vblank status bits don't work the way we'd want
720 * them to work on non-PCH platforms (for
721 * ilk_pipe_in_vblank_locked()), and there doesn't
722 * appear any other way to determine if we're currently
725 * Instead let's assume that we're already in vblank if
726 * we got called from the vblank interrupt and the
727 * scanline counter value indicates that we're on the
728 * line just prior to vblank start. This should result
729 * in the correct answer, unless the vblank interrupt
730 * delivery really got delayed for almost exactly one
733 if (flags & DRM_CALLED_FROM_VBLIRQ &&
734 position == vbl_start - 1) {
735 position = (position + 1) % vtotal;
737 /* Signal this correction as "applied". */
742 /* Have access to pixelcount since start of frame.
743 * We can split this into vertical and horizontal
746 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
748 /* convert to pixel counts */
754 /* Get optional system timestamp after query. */
756 *etime = ktime_get();
758 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
760 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
762 in_vbl = position >= vbl_start && position < vbl_end;
765 * While in vblank, position will be negative
766 * counting up towards 0 at vbl_end. And outside
767 * vblank, position will be positive counting
770 if (position >= vbl_start)
773 position += vtotal - vbl_end;
775 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
779 *vpos = position / htotal;
780 *hpos = position - (*vpos * htotal);
785 ret |= DRM_SCANOUTPOS_INVBL;
790 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
792 struct timeval *vblank_time,
795 struct drm_crtc *crtc;
797 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
798 DRM_ERROR("Invalid crtc %d\n", pipe);
802 /* Get drm_crtc to timestamp: */
803 crtc = intel_get_crtc_for_pipe(dev, pipe);
805 DRM_ERROR("Invalid crtc %d\n", pipe);
809 if (!crtc->enabled) {
810 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
814 /* Helper routine in DRM core does all the work: */
815 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
818 &to_intel_crtc(crtc)->config.adjusted_mode);
821 static bool intel_hpd_irq_event(struct drm_device *dev,
822 struct drm_connector *connector)
824 enum drm_connector_status old_status;
826 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
827 old_status = connector->status;
829 connector->status = connector->funcs->detect(connector, false);
830 if (old_status == connector->status)
833 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
835 drm_get_connector_name(connector),
836 drm_get_connector_status_name(old_status),
837 drm_get_connector_status_name(connector->status));
843 * Handle hotplug events outside the interrupt handler proper.
845 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
847 static void i915_hotplug_work_func(struct work_struct *work)
849 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
851 struct drm_device *dev = dev_priv->dev;
852 struct drm_mode_config *mode_config = &dev->mode_config;
853 struct intel_connector *intel_connector;
854 struct intel_encoder *intel_encoder;
855 struct drm_connector *connector;
856 unsigned long irqflags;
857 bool hpd_disabled = false;
858 bool changed = false;
861 /* HPD irq before everything is fully set up. */
862 if (!dev_priv->enable_hotplug_processing)
865 mutex_lock(&mode_config->mutex);
866 DRM_DEBUG_KMS("running encoder hotplug functions\n");
868 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
870 hpd_event_bits = dev_priv->hpd_event_bits;
871 dev_priv->hpd_event_bits = 0;
872 list_for_each_entry(connector, &mode_config->connector_list, head) {
873 intel_connector = to_intel_connector(connector);
874 intel_encoder = intel_connector->encoder;
875 if (intel_encoder->hpd_pin > HPD_NONE &&
876 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
877 connector->polled == DRM_CONNECTOR_POLL_HPD) {
878 DRM_INFO("HPD interrupt storm detected on connector %s: "
879 "switching from hotplug detection to polling\n",
880 drm_get_connector_name(connector));
881 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
882 connector->polled = DRM_CONNECTOR_POLL_CONNECT
883 | DRM_CONNECTOR_POLL_DISCONNECT;
886 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
887 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
888 drm_get_connector_name(connector), intel_encoder->hpd_pin);
891 /* if there were no outputs to poll, poll was disabled,
892 * therefore make sure it's enabled when disabling HPD on
895 drm_kms_helper_poll_enable(dev);
896 mod_timer(&dev_priv->hotplug_reenable_timer,
897 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
900 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
902 list_for_each_entry(connector, &mode_config->connector_list, head) {
903 intel_connector = to_intel_connector(connector);
904 intel_encoder = intel_connector->encoder;
905 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
906 if (intel_encoder->hot_plug)
907 intel_encoder->hot_plug(intel_encoder);
908 if (intel_hpd_irq_event(dev, connector))
912 mutex_unlock(&mode_config->mutex);
915 drm_kms_helper_hotplug_event(dev);
918 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
920 drm_i915_private_t *dev_priv = dev->dev_private;
921 u32 busy_up, busy_down, max_avg, min_avg;
924 spin_lock(&mchdev_lock);
926 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
928 new_delay = dev_priv->ips.cur_delay;
930 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
931 busy_up = I915_READ(RCPREVBSYTUPAVG);
932 busy_down = I915_READ(RCPREVBSYTDNAVG);
933 max_avg = I915_READ(RCBMAXAVG);
934 min_avg = I915_READ(RCBMINAVG);
936 /* Handle RCS change request from hw */
937 if (busy_up > max_avg) {
938 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
939 new_delay = dev_priv->ips.cur_delay - 1;
940 if (new_delay < dev_priv->ips.max_delay)
941 new_delay = dev_priv->ips.max_delay;
942 } else if (busy_down < min_avg) {
943 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
944 new_delay = dev_priv->ips.cur_delay + 1;
945 if (new_delay > dev_priv->ips.min_delay)
946 new_delay = dev_priv->ips.min_delay;
949 if (ironlake_set_drps(dev, new_delay))
950 dev_priv->ips.cur_delay = new_delay;
952 spin_unlock(&mchdev_lock);
957 static void notify_ring(struct drm_device *dev,
958 struct intel_ring_buffer *ring)
960 if (ring->obj == NULL)
963 trace_i915_gem_request_complete(ring);
965 wake_up_all(&ring->irq_queue);
966 i915_queue_hangcheck(dev);
969 static void gen6_pm_rps_work(struct work_struct *work)
971 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
976 spin_lock_irq(&dev_priv->irq_lock);
977 pm_iir = dev_priv->rps.pm_iir;
978 dev_priv->rps.pm_iir = 0;
979 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
980 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
981 spin_unlock_irq(&dev_priv->irq_lock);
983 /* Make sure we didn't queue anything we're not going to process. */
984 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
986 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
989 mutex_lock(&dev_priv->rps.hw_lock);
991 adj = dev_priv->rps.last_adj;
992 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
997 new_delay = dev_priv->rps.cur_delay + adj;
1000 * For better performance, jump directly
1001 * to RPe if we're below it.
1003 if (new_delay < dev_priv->rps.rpe_delay)
1004 new_delay = dev_priv->rps.rpe_delay;
1005 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1006 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1007 new_delay = dev_priv->rps.rpe_delay;
1009 new_delay = dev_priv->rps.min_delay;
1011 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1016 new_delay = dev_priv->rps.cur_delay + adj;
1017 } else { /* unknown event */
1018 new_delay = dev_priv->rps.cur_delay;
1021 /* sysfs frequency interfaces may have snuck in while servicing the
1024 new_delay = clamp_t(int, new_delay,
1025 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1026 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1028 if (IS_VALLEYVIEW(dev_priv->dev))
1029 valleyview_set_rps(dev_priv->dev, new_delay);
1031 gen6_set_rps(dev_priv->dev, new_delay);
1033 mutex_unlock(&dev_priv->rps.hw_lock);
1038 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1040 * @work: workqueue struct
1042 * Doesn't actually do anything except notify userspace. As a consequence of
1043 * this event, userspace should try to remap the bad rows since statistically
1044 * it is likely the same row is more likely to go bad again.
1046 static void ivybridge_parity_work(struct work_struct *work)
1048 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1049 l3_parity.error_work);
1050 u32 error_status, row, bank, subbank;
1051 char *parity_event[6];
1053 unsigned long flags;
1056 /* We must turn off DOP level clock gating to access the L3 registers.
1057 * In order to prevent a get/put style interface, acquire struct mutex
1058 * any time we access those registers.
1060 mutex_lock(&dev_priv->dev->struct_mutex);
1062 /* If we've screwed up tracking, just let the interrupt fire again */
1063 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1066 misccpctl = I915_READ(GEN7_MISCCPCTL);
1067 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1068 POSTING_READ(GEN7_MISCCPCTL);
1070 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1074 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1077 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1079 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1081 error_status = I915_READ(reg);
1082 row = GEN7_PARITY_ERROR_ROW(error_status);
1083 bank = GEN7_PARITY_ERROR_BANK(error_status);
1084 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1086 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1089 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1090 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1091 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1092 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1093 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1094 parity_event[5] = NULL;
1096 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1097 KOBJ_CHANGE, parity_event);
1099 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1100 slice, row, bank, subbank);
1102 kfree(parity_event[4]);
1103 kfree(parity_event[3]);
1104 kfree(parity_event[2]);
1105 kfree(parity_event[1]);
1108 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1111 WARN_ON(dev_priv->l3_parity.which_slice);
1112 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1113 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1114 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1116 mutex_unlock(&dev_priv->dev->struct_mutex);
1119 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1121 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1123 if (!HAS_L3_DPF(dev))
1126 spin_lock(&dev_priv->irq_lock);
1127 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1128 spin_unlock(&dev_priv->irq_lock);
1130 iir &= GT_PARITY_ERROR(dev);
1131 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1132 dev_priv->l3_parity.which_slice |= 1 << 1;
1134 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1135 dev_priv->l3_parity.which_slice |= 1 << 0;
1137 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1140 static void ilk_gt_irq_handler(struct drm_device *dev,
1141 struct drm_i915_private *dev_priv,
1145 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1146 notify_ring(dev, &dev_priv->ring[RCS]);
1147 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1148 notify_ring(dev, &dev_priv->ring[VCS]);
1151 static void snb_gt_irq_handler(struct drm_device *dev,
1152 struct drm_i915_private *dev_priv,
1157 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1158 notify_ring(dev, &dev_priv->ring[RCS]);
1159 if (gt_iir & GT_BSD_USER_INTERRUPT)
1160 notify_ring(dev, &dev_priv->ring[VCS]);
1161 if (gt_iir & GT_BLT_USER_INTERRUPT)
1162 notify_ring(dev, &dev_priv->ring[BCS]);
1164 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1165 GT_BSD_CS_ERROR_INTERRUPT |
1166 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1167 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1168 i915_handle_error(dev, false);
1171 if (gt_iir & GT_PARITY_ERROR(dev))
1172 ivybridge_parity_error_irq_handler(dev, gt_iir);
1175 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1176 struct drm_i915_private *dev_priv,
1181 irqreturn_t ret = IRQ_NONE;
1183 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1184 tmp = I915_READ(GEN8_GT_IIR(0));
1187 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1188 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1189 if (rcs & GT_RENDER_USER_INTERRUPT)
1190 notify_ring(dev, &dev_priv->ring[RCS]);
1191 if (bcs & GT_RENDER_USER_INTERRUPT)
1192 notify_ring(dev, &dev_priv->ring[BCS]);
1193 I915_WRITE(GEN8_GT_IIR(0), tmp);
1195 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1198 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1199 tmp = I915_READ(GEN8_GT_IIR(1));
1202 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1203 if (vcs & GT_RENDER_USER_INTERRUPT)
1204 notify_ring(dev, &dev_priv->ring[VCS]);
1205 I915_WRITE(GEN8_GT_IIR(1), tmp);
1207 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1210 if (master_ctl & GEN8_GT_VECS_IRQ) {
1211 tmp = I915_READ(GEN8_GT_IIR(3));
1214 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1215 if (vcs & GT_RENDER_USER_INTERRUPT)
1216 notify_ring(dev, &dev_priv->ring[VECS]);
1217 I915_WRITE(GEN8_GT_IIR(3), tmp);
1219 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1225 #define HPD_STORM_DETECT_PERIOD 1000
1226 #define HPD_STORM_THRESHOLD 5
1228 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1229 u32 hotplug_trigger,
1232 drm_i915_private_t *dev_priv = dev->dev_private;
1234 bool storm_detected = false;
1236 if (!hotplug_trigger)
1239 spin_lock(&dev_priv->irq_lock);
1240 for (i = 1; i < HPD_NUM_PINS; i++) {
1242 WARN_ONCE(hpd[i] & hotplug_trigger &&
1243 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1244 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1245 hotplug_trigger, i, hpd[i]);
1247 if (!(hpd[i] & hotplug_trigger) ||
1248 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1251 dev_priv->hpd_event_bits |= (1 << i);
1252 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1253 dev_priv->hpd_stats[i].hpd_last_jiffies
1254 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1255 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1256 dev_priv->hpd_stats[i].hpd_cnt = 0;
1257 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1258 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1259 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1260 dev_priv->hpd_event_bits &= ~(1 << i);
1261 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1262 storm_detected = true;
1264 dev_priv->hpd_stats[i].hpd_cnt++;
1265 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1266 dev_priv->hpd_stats[i].hpd_cnt);
1271 dev_priv->display.hpd_irq_setup(dev);
1272 spin_unlock(&dev_priv->irq_lock);
1275 * Our hotplug handler can grab modeset locks (by calling down into the
1276 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1277 * queue for otherwise the flush_work in the pageflip code will
1280 schedule_work(&dev_priv->hotplug_work);
1283 static void gmbus_irq_handler(struct drm_device *dev)
1285 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1287 wake_up_all(&dev_priv->gmbus_wait_queue);
1290 static void dp_aux_irq_handler(struct drm_device *dev)
1292 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1294 wake_up_all(&dev_priv->gmbus_wait_queue);
1297 #if defined(CONFIG_DEBUG_FS)
1298 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1299 uint32_t crc0, uint32_t crc1,
1300 uint32_t crc2, uint32_t crc3,
1303 struct drm_i915_private *dev_priv = dev->dev_private;
1304 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1305 struct intel_pipe_crc_entry *entry;
1308 spin_lock(&pipe_crc->lock);
1310 if (!pipe_crc->entries) {
1311 spin_unlock(&pipe_crc->lock);
1312 DRM_ERROR("spurious interrupt\n");
1316 head = pipe_crc->head;
1317 tail = pipe_crc->tail;
1319 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1320 spin_unlock(&pipe_crc->lock);
1321 DRM_ERROR("CRC buffer overflowing\n");
1325 entry = &pipe_crc->entries[head];
1327 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1328 entry->crc[0] = crc0;
1329 entry->crc[1] = crc1;
1330 entry->crc[2] = crc2;
1331 entry->crc[3] = crc3;
1332 entry->crc[4] = crc4;
1334 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1335 pipe_crc->head = head;
1337 spin_unlock(&pipe_crc->lock);
1339 wake_up_interruptible(&pipe_crc->wq);
1343 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1344 uint32_t crc0, uint32_t crc1,
1345 uint32_t crc2, uint32_t crc3,
1350 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1352 struct drm_i915_private *dev_priv = dev->dev_private;
1354 display_pipe_crc_irq_handler(dev, pipe,
1355 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1359 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1361 struct drm_i915_private *dev_priv = dev->dev_private;
1363 display_pipe_crc_irq_handler(dev, pipe,
1364 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1365 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1366 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1367 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1368 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1371 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 uint32_t res1, res2;
1376 if (INTEL_INFO(dev)->gen >= 3)
1377 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1381 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1382 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1386 display_pipe_crc_irq_handler(dev, pipe,
1387 I915_READ(PIPE_CRC_RES_RED(pipe)),
1388 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1389 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1393 /* The RPS events need forcewake, so we add them to a work queue and mask their
1394 * IMR bits until the work is done. Other interrupts can be processed without
1395 * the work queue. */
1396 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1398 if (pm_iir & GEN6_PM_RPS_EVENTS) {
1399 spin_lock(&dev_priv->irq_lock);
1400 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1401 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1402 spin_unlock(&dev_priv->irq_lock);
1404 queue_work(dev_priv->wq, &dev_priv->rps.work);
1407 if (HAS_VEBOX(dev_priv->dev)) {
1408 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1409 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1411 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1412 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1413 i915_handle_error(dev_priv->dev, false);
1418 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1420 struct drm_device *dev = (struct drm_device *) arg;
1421 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1422 u32 iir, gt_iir, pm_iir;
1423 irqreturn_t ret = IRQ_NONE;
1424 unsigned long irqflags;
1426 u32 pipe_stats[I915_MAX_PIPES];
1428 atomic_inc(&dev_priv->irq_received);
1431 iir = I915_READ(VLV_IIR);
1432 gt_iir = I915_READ(GTIIR);
1433 pm_iir = I915_READ(GEN6_PMIIR);
1435 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1440 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1442 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1443 for_each_pipe(pipe) {
1444 int reg = PIPESTAT(pipe);
1445 pipe_stats[pipe] = I915_READ(reg);
1448 * Clear the PIPE*STAT regs before the IIR
1450 if (pipe_stats[pipe] & 0x8000ffff) {
1451 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1452 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1454 I915_WRITE(reg, pipe_stats[pipe]);
1457 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1459 for_each_pipe(pipe) {
1460 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1461 drm_handle_vblank(dev, pipe);
1463 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1464 intel_prepare_page_flip(dev, pipe);
1465 intel_finish_page_flip(dev, pipe);
1468 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1469 i9xx_pipe_crc_irq_handler(dev, pipe);
1472 /* Consume port. Then clear IIR or we'll miss events */
1473 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1474 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1475 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1477 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1480 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1482 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1483 dp_aux_irq_handler(dev);
1485 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1486 I915_READ(PORT_HOTPLUG_STAT);
1489 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1490 gmbus_irq_handler(dev);
1493 gen6_rps_irq_handler(dev_priv, pm_iir);
1495 I915_WRITE(GTIIR, gt_iir);
1496 I915_WRITE(GEN6_PMIIR, pm_iir);
1497 I915_WRITE(VLV_IIR, iir);
1504 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1506 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1508 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1510 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1512 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1513 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1514 SDE_AUDIO_POWER_SHIFT);
1515 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1519 if (pch_iir & SDE_AUX_MASK)
1520 dp_aux_irq_handler(dev);
1522 if (pch_iir & SDE_GMBUS)
1523 gmbus_irq_handler(dev);
1525 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1526 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1528 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1529 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1531 if (pch_iir & SDE_POISON)
1532 DRM_ERROR("PCH poison interrupt\n");
1534 if (pch_iir & SDE_FDI_MASK)
1536 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1538 I915_READ(FDI_RX_IIR(pipe)));
1540 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1541 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1543 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1544 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1546 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1547 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1549 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1551 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1552 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1554 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1557 static void ivb_err_int_handler(struct drm_device *dev)
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 u32 err_int = I915_READ(GEN7_ERR_INT);
1563 if (err_int & ERR_INT_POISON)
1564 DRM_ERROR("Poison interrupt\n");
1566 for_each_pipe(pipe) {
1567 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1568 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1570 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1574 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1575 if (IS_IVYBRIDGE(dev))
1576 ivb_pipe_crc_irq_handler(dev, pipe);
1578 hsw_pipe_crc_irq_handler(dev, pipe);
1582 I915_WRITE(GEN7_ERR_INT, err_int);
1585 static void cpt_serr_int_handler(struct drm_device *dev)
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 u32 serr_int = I915_READ(SERR_INT);
1590 if (serr_int & SERR_INT_POISON)
1591 DRM_ERROR("PCH poison interrupt\n");
1593 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1594 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1596 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1598 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1599 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1601 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1603 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1604 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1606 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1608 I915_WRITE(SERR_INT, serr_int);
1611 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1613 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1615 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1617 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1619 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1620 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1621 SDE_AUDIO_POWER_SHIFT_CPT);
1622 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1626 if (pch_iir & SDE_AUX_MASK_CPT)
1627 dp_aux_irq_handler(dev);
1629 if (pch_iir & SDE_GMBUS_CPT)
1630 gmbus_irq_handler(dev);
1632 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1633 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1635 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1636 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1638 if (pch_iir & SDE_FDI_MASK_CPT)
1640 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1642 I915_READ(FDI_RX_IIR(pipe)));
1644 if (pch_iir & SDE_ERROR_CPT)
1645 cpt_serr_int_handler(dev);
1648 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1653 if (de_iir & DE_AUX_CHANNEL_A)
1654 dp_aux_irq_handler(dev);
1656 if (de_iir & DE_GSE)
1657 intel_opregion_asle_intr(dev);
1659 if (de_iir & DE_POISON)
1660 DRM_ERROR("Poison interrupt\n");
1662 for_each_pipe(pipe) {
1663 if (de_iir & DE_PIPE_VBLANK(pipe))
1664 drm_handle_vblank(dev, pipe);
1666 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1667 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1668 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1671 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1672 i9xx_pipe_crc_irq_handler(dev, pipe);
1674 /* plane/pipes map 1:1 on ilk+ */
1675 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1676 intel_prepare_page_flip(dev, pipe);
1677 intel_finish_page_flip_plane(dev, pipe);
1681 /* check event from PCH */
1682 if (de_iir & DE_PCH_EVENT) {
1683 u32 pch_iir = I915_READ(SDEIIR);
1685 if (HAS_PCH_CPT(dev))
1686 cpt_irq_handler(dev, pch_iir);
1688 ibx_irq_handler(dev, pch_iir);
1690 /* should clear PCH hotplug event before clear CPU irq */
1691 I915_WRITE(SDEIIR, pch_iir);
1694 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1695 ironlake_rps_change_irq_handler(dev);
1698 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1703 if (de_iir & DE_ERR_INT_IVB)
1704 ivb_err_int_handler(dev);
1706 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1707 dp_aux_irq_handler(dev);
1709 if (de_iir & DE_GSE_IVB)
1710 intel_opregion_asle_intr(dev);
1713 if (de_iir & (DE_PIPE_VBLANK_IVB(i)))
1714 drm_handle_vblank(dev, i);
1716 /* plane/pipes map 1:1 on ilk+ */
1717 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) {
1718 intel_prepare_page_flip(dev, i);
1719 intel_finish_page_flip_plane(dev, i);
1723 /* check event from PCH */
1724 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1725 u32 pch_iir = I915_READ(SDEIIR);
1727 cpt_irq_handler(dev, pch_iir);
1729 /* clear PCH hotplug event before clear CPU irq */
1730 I915_WRITE(SDEIIR, pch_iir);
1734 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1736 struct drm_device *dev = (struct drm_device *) arg;
1737 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1738 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1739 irqreturn_t ret = IRQ_NONE;
1741 atomic_inc(&dev_priv->irq_received);
1743 /* We get interrupts on unclaimed registers, so check for this before we
1744 * do any I915_{READ,WRITE}. */
1745 intel_uncore_check_errors(dev);
1747 /* disable master interrupt before clearing iir */
1748 de_ier = I915_READ(DEIER);
1749 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1750 POSTING_READ(DEIER);
1752 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1753 * interrupts will will be stored on its back queue, and then we'll be
1754 * able to process them after we restore SDEIER (as soon as we restore
1755 * it, we'll get an interrupt if SDEIIR still has something to process
1756 * due to its back queue). */
1757 if (!HAS_PCH_NOP(dev)) {
1758 sde_ier = I915_READ(SDEIER);
1759 I915_WRITE(SDEIER, 0);
1760 POSTING_READ(SDEIER);
1763 gt_iir = I915_READ(GTIIR);
1765 if (INTEL_INFO(dev)->gen >= 6)
1766 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1768 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1769 I915_WRITE(GTIIR, gt_iir);
1773 de_iir = I915_READ(DEIIR);
1775 if (INTEL_INFO(dev)->gen >= 7)
1776 ivb_display_irq_handler(dev, de_iir);
1778 ilk_display_irq_handler(dev, de_iir);
1779 I915_WRITE(DEIIR, de_iir);
1783 if (INTEL_INFO(dev)->gen >= 6) {
1784 u32 pm_iir = I915_READ(GEN6_PMIIR);
1786 gen6_rps_irq_handler(dev_priv, pm_iir);
1787 I915_WRITE(GEN6_PMIIR, pm_iir);
1792 I915_WRITE(DEIER, de_ier);
1793 POSTING_READ(DEIER);
1794 if (!HAS_PCH_NOP(dev)) {
1795 I915_WRITE(SDEIER, sde_ier);
1796 POSTING_READ(SDEIER);
1802 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1804 struct drm_device *dev = arg;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1807 irqreturn_t ret = IRQ_NONE;
1811 atomic_inc(&dev_priv->irq_received);
1813 master_ctl = I915_READ(GEN8_MASTER_IRQ);
1814 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1818 I915_WRITE(GEN8_MASTER_IRQ, 0);
1819 POSTING_READ(GEN8_MASTER_IRQ);
1821 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1823 if (master_ctl & GEN8_DE_MISC_IRQ) {
1824 tmp = I915_READ(GEN8_DE_MISC_IIR);
1825 if (tmp & GEN8_DE_MISC_GSE)
1826 intel_opregion_asle_intr(dev);
1828 DRM_ERROR("Unexpected DE Misc interrupt\n");
1830 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
1833 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
1838 if (master_ctl & GEN8_DE_PORT_IRQ) {
1839 tmp = I915_READ(GEN8_DE_PORT_IIR);
1840 if (tmp & GEN8_AUX_CHANNEL_A)
1841 dp_aux_irq_handler(dev);
1843 DRM_ERROR("Unexpected DE Port interrupt\n");
1845 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
1848 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
1853 for_each_pipe(pipe) {
1856 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
1859 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
1860 if (pipe_iir & GEN8_PIPE_VBLANK)
1861 drm_handle_vblank(dev, pipe);
1863 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
1864 intel_prepare_page_flip(dev, pipe);
1865 intel_finish_page_flip_plane(dev, pipe);
1868 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
1869 hsw_pipe_crc_irq_handler(dev, pipe);
1871 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
1872 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1874 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n",
1878 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
1879 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
1881 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
1886 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
1888 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
1891 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
1893 * FIXME(BDW): Assume for now that the new interrupt handling
1894 * scheme also closed the SDE interrupt handling race we've seen
1895 * on older pch-split platforms. But this needs testing.
1897 u32 pch_iir = I915_READ(SDEIIR);
1899 cpt_irq_handler(dev, pch_iir);
1902 I915_WRITE(SDEIIR, pch_iir);
1907 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1908 POSTING_READ(GEN8_MASTER_IRQ);
1913 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1914 bool reset_completed)
1916 struct intel_ring_buffer *ring;
1920 * Notify all waiters for GPU completion events that reset state has
1921 * been changed, and that they need to restart their wait after
1922 * checking for potential errors (and bail out to drop locks if there is
1923 * a gpu reset pending so that i915_error_work_func can acquire them).
1926 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1927 for_each_ring(ring, dev_priv, i)
1928 wake_up_all(&ring->irq_queue);
1930 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1931 wake_up_all(&dev_priv->pending_flip_queue);
1934 * Signal tasks blocked in i915_gem_wait_for_error that the pending
1935 * reset state is cleared.
1937 if (reset_completed)
1938 wake_up_all(&dev_priv->gpu_error.reset_queue);
1942 * i915_error_work_func - do process context error handling work
1943 * @work: work struct
1945 * Fire an error uevent so userspace can see that a hang or error
1948 static void i915_error_work_func(struct work_struct *work)
1950 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1952 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1954 struct drm_device *dev = dev_priv->dev;
1955 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1956 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1957 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1960 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
1963 * Note that there's only one work item which does gpu resets, so we
1964 * need not worry about concurrent gpu resets potentially incrementing
1965 * error->reset_counter twice. We only need to take care of another
1966 * racing irq/hangcheck declaring the gpu dead for a second time. A
1967 * quick check for that is good enough: schedule_work ensures the
1968 * correct ordering between hang detection and this work item, and since
1969 * the reset in-progress bit is only ever set by code outside of this
1970 * work we don't need to worry about any other races.
1972 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1973 DRM_DEBUG_DRIVER("resetting chip\n");
1974 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
1978 * All state reset _must_ be completed before we update the
1979 * reset counter, for otherwise waiters might miss the reset
1980 * pending state and not properly drop locks, resulting in
1981 * deadlocks with the reset work.
1983 ret = i915_reset(dev);
1985 intel_display_handle_reset(dev);
1989 * After all the gem state is reset, increment the reset
1990 * counter and wake up everyone waiting for the reset to
1993 * Since unlock operations are a one-sided barrier only,
1994 * we need to insert a barrier here to order any seqno
1996 * the counter increment.
1998 smp_mb__before_atomic_inc();
1999 atomic_inc(&dev_priv->gpu_error.reset_counter);
2001 kobject_uevent_env(&dev->primary->kdev->kobj,
2002 KOBJ_CHANGE, reset_done_event);
2004 atomic_set_mask(I915_WEDGED, &error->reset_counter);
2008 * Note: The wake_up also serves as a memory barrier so that
2009 * waiters see the update value of the reset counter atomic_t.
2011 i915_error_wake_up(dev_priv, true);
2015 static void i915_report_and_clear_eir(struct drm_device *dev)
2017 struct drm_i915_private *dev_priv = dev->dev_private;
2018 uint32_t instdone[I915_NUM_INSTDONE_REG];
2019 u32 eir = I915_READ(EIR);
2025 pr_err("render error detected, EIR: 0x%08x\n", eir);
2027 i915_get_extra_instdone(dev, instdone);
2030 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2031 u32 ipeir = I915_READ(IPEIR_I965);
2033 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2034 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2035 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2036 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2037 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2038 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2039 I915_WRITE(IPEIR_I965, ipeir);
2040 POSTING_READ(IPEIR_I965);
2042 if (eir & GM45_ERROR_PAGE_TABLE) {
2043 u32 pgtbl_err = I915_READ(PGTBL_ER);
2044 pr_err("page table error\n");
2045 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2046 I915_WRITE(PGTBL_ER, pgtbl_err);
2047 POSTING_READ(PGTBL_ER);
2051 if (!IS_GEN2(dev)) {
2052 if (eir & I915_ERROR_PAGE_TABLE) {
2053 u32 pgtbl_err = I915_READ(PGTBL_ER);
2054 pr_err("page table error\n");
2055 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2056 I915_WRITE(PGTBL_ER, pgtbl_err);
2057 POSTING_READ(PGTBL_ER);
2061 if (eir & I915_ERROR_MEMORY_REFRESH) {
2062 pr_err("memory refresh error:\n");
2064 pr_err("pipe %c stat: 0x%08x\n",
2065 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2066 /* pipestat has already been acked */
2068 if (eir & I915_ERROR_INSTRUCTION) {
2069 pr_err("instruction error\n");
2070 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2071 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2072 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2073 if (INTEL_INFO(dev)->gen < 4) {
2074 u32 ipeir = I915_READ(IPEIR);
2076 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2077 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2078 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2079 I915_WRITE(IPEIR, ipeir);
2080 POSTING_READ(IPEIR);
2082 u32 ipeir = I915_READ(IPEIR_I965);
2084 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2085 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2086 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2087 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2088 I915_WRITE(IPEIR_I965, ipeir);
2089 POSTING_READ(IPEIR_I965);
2093 I915_WRITE(EIR, eir);
2095 eir = I915_READ(EIR);
2098 * some errors might have become stuck,
2101 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2102 I915_WRITE(EMR, I915_READ(EMR) | eir);
2103 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2108 * i915_handle_error - handle an error interrupt
2111 * Do some basic checking of regsiter state at error interrupt time and
2112 * dump it to the syslog. Also call i915_capture_error_state() to make
2113 * sure we get a record and make it available in debugfs. Fire a uevent
2114 * so userspace knows something bad happened (should trigger collection
2115 * of a ring dump etc.).
2117 void i915_handle_error(struct drm_device *dev, bool wedged)
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2121 i915_capture_error_state(dev);
2122 i915_report_and_clear_eir(dev);
2125 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2126 &dev_priv->gpu_error.reset_counter);
2129 * Wakeup waiting processes so that the reset work function
2130 * i915_error_work_func doesn't deadlock trying to grab various
2131 * locks. By bumping the reset counter first, the woken
2132 * processes will see a reset in progress and back off,
2133 * releasing their locks and then wait for the reset completion.
2134 * We must do this for _all_ gpu waiters that might hold locks
2135 * that the reset work needs to acquire.
2137 * Note: The wake_up serves as the required memory barrier to
2138 * ensure that the waiters see the updated value of the reset
2141 i915_error_wake_up(dev_priv, false);
2145 * Our reset work can grab modeset locks (since it needs to reset the
2146 * state of outstanding pagelips). Hence it must not be run on our own
2147 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2148 * code will deadlock.
2150 schedule_work(&dev_priv->gpu_error.work);
2153 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2155 drm_i915_private_t *dev_priv = dev->dev_private;
2156 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2158 struct drm_i915_gem_object *obj;
2159 struct intel_unpin_work *work;
2160 unsigned long flags;
2161 bool stall_detected;
2163 /* Ignore early vblank irqs */
2164 if (intel_crtc == NULL)
2167 spin_lock_irqsave(&dev->event_lock, flags);
2168 work = intel_crtc->unpin_work;
2171 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2172 !work->enable_stall_check) {
2173 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2174 spin_unlock_irqrestore(&dev->event_lock, flags);
2178 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2179 obj = work->pending_flip_obj;
2180 if (INTEL_INFO(dev)->gen >= 4) {
2181 int dspsurf = DSPSURF(intel_crtc->plane);
2182 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2183 i915_gem_obj_ggtt_offset(obj);
2185 int dspaddr = DSPADDR(intel_crtc->plane);
2186 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2187 crtc->y * crtc->fb->pitches[0] +
2188 crtc->x * crtc->fb->bits_per_pixel/8);
2191 spin_unlock_irqrestore(&dev->event_lock, flags);
2193 if (stall_detected) {
2194 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2195 intel_prepare_page_flip(dev, intel_crtc->plane);
2199 /* Called from drm generic code, passed 'crtc' which
2200 * we use as a pipe index
2202 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2205 unsigned long irqflags;
2207 if (!i915_pipe_enabled(dev, pipe))
2210 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2211 if (INTEL_INFO(dev)->gen >= 4)
2212 i915_enable_pipestat(dev_priv, pipe,
2213 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2215 i915_enable_pipestat(dev_priv, pipe,
2216 PIPE_VBLANK_INTERRUPT_ENABLE);
2218 /* maintain vblank delivery even in deep C-states */
2219 if (dev_priv->info->gen == 3)
2220 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2221 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2226 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2228 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2229 unsigned long irqflags;
2230 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2231 DE_PIPE_VBLANK(pipe);
2233 if (!i915_pipe_enabled(dev, pipe))
2236 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2237 ironlake_enable_display_irq(dev_priv, bit);
2238 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2243 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2245 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2246 unsigned long irqflags;
2249 if (!i915_pipe_enabled(dev, pipe))
2252 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2253 imr = I915_READ(VLV_IMR);
2255 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2257 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2258 I915_WRITE(VLV_IMR, imr);
2259 i915_enable_pipestat(dev_priv, pipe,
2260 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2261 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2266 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 unsigned long irqflags;
2271 if (!i915_pipe_enabled(dev, pipe))
2274 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2275 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2276 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2277 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2278 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2282 /* Called from drm generic code, passed 'crtc' which
2283 * we use as a pipe index
2285 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2287 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2288 unsigned long irqflags;
2290 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2291 if (dev_priv->info->gen == 3)
2292 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2294 i915_disable_pipestat(dev_priv, pipe,
2295 PIPE_VBLANK_INTERRUPT_ENABLE |
2296 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2297 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2300 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2303 unsigned long irqflags;
2304 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2305 DE_PIPE_VBLANK(pipe);
2307 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2308 ironlake_disable_display_irq(dev_priv, bit);
2309 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2312 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2314 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2315 unsigned long irqflags;
2318 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2319 i915_disable_pipestat(dev_priv, pipe,
2320 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2321 imr = I915_READ(VLV_IMR);
2323 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
2325 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2326 I915_WRITE(VLV_IMR, imr);
2327 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2330 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2332 struct drm_i915_private *dev_priv = dev->dev_private;
2333 unsigned long irqflags;
2335 if (!i915_pipe_enabled(dev, pipe))
2338 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2339 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2340 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2341 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2342 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2346 ring_last_seqno(struct intel_ring_buffer *ring)
2348 return list_entry(ring->request_list.prev,
2349 struct drm_i915_gem_request, list)->seqno;
2353 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2355 return (list_empty(&ring->request_list) ||
2356 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2359 static struct intel_ring_buffer *
2360 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2362 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2363 u32 cmd, ipehr, acthd, acthd_min;
2365 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2366 if ((ipehr & ~(0x3 << 16)) !=
2367 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2370 /* ACTHD is likely pointing to the dword after the actual command,
2371 * so scan backwards until we find the MBOX.
2373 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2374 acthd_min = max((int)acthd - 3 * 4, 0);
2376 cmd = ioread32(ring->virtual_start + acthd);
2381 if (acthd < acthd_min)
2385 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2386 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2389 static int semaphore_passed(struct intel_ring_buffer *ring)
2391 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2392 struct intel_ring_buffer *signaller;
2395 ring->hangcheck.deadlock = true;
2397 signaller = semaphore_waits_for(ring, &seqno);
2398 if (signaller == NULL || signaller->hangcheck.deadlock)
2401 /* cursory check for an unkickable deadlock */
2402 ctl = I915_READ_CTL(signaller);
2403 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2406 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2409 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2411 struct intel_ring_buffer *ring;
2414 for_each_ring(ring, dev_priv, i)
2415 ring->hangcheck.deadlock = false;
2418 static enum intel_ring_hangcheck_action
2419 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2421 struct drm_device *dev = ring->dev;
2422 struct drm_i915_private *dev_priv = dev->dev_private;
2425 if (ring->hangcheck.acthd != acthd)
2426 return HANGCHECK_ACTIVE;
2429 return HANGCHECK_HUNG;
2431 /* Is the chip hanging on a WAIT_FOR_EVENT?
2432 * If so we can simply poke the RB_WAIT bit
2433 * and break the hang. This should work on
2434 * all but the second generation chipsets.
2436 tmp = I915_READ_CTL(ring);
2437 if (tmp & RING_WAIT) {
2438 DRM_ERROR("Kicking stuck wait on %s\n",
2440 i915_handle_error(dev, false);
2441 I915_WRITE_CTL(ring, tmp);
2442 return HANGCHECK_KICK;
2445 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2446 switch (semaphore_passed(ring)) {
2448 return HANGCHECK_HUNG;
2450 DRM_ERROR("Kicking stuck semaphore on %s\n",
2452 i915_handle_error(dev, false);
2453 I915_WRITE_CTL(ring, tmp);
2454 return HANGCHECK_KICK;
2456 return HANGCHECK_WAIT;
2460 return HANGCHECK_HUNG;
2464 * This is called when the chip hasn't reported back with completed
2465 * batchbuffers in a long time. We keep track per ring seqno progress and
2466 * if there are no progress, hangcheck score for that ring is increased.
2467 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2468 * we kick the ring. If we see no progress on three subsequent calls
2469 * we assume chip is wedged and try to fix it by resetting the chip.
2471 static void i915_hangcheck_elapsed(unsigned long data)
2473 struct drm_device *dev = (struct drm_device *)data;
2474 drm_i915_private_t *dev_priv = dev->dev_private;
2475 struct intel_ring_buffer *ring;
2477 int busy_count = 0, rings_hung = 0;
2478 bool stuck[I915_NUM_RINGS] = { 0 };
2484 if (!i915_enable_hangcheck)
2487 for_each_ring(ring, dev_priv, i) {
2491 semaphore_clear_deadlocks(dev_priv);
2493 seqno = ring->get_seqno(ring, false);
2494 acthd = intel_ring_get_active_head(ring);
2496 if (ring->hangcheck.seqno == seqno) {
2497 if (ring_idle(ring, seqno)) {
2498 ring->hangcheck.action = HANGCHECK_IDLE;
2500 if (waitqueue_active(&ring->irq_queue)) {
2501 /* Issue a wake-up to catch stuck h/w. */
2502 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2503 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2504 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2507 DRM_INFO("Fake missed irq on %s\n",
2509 wake_up_all(&ring->irq_queue);
2511 /* Safeguard against driver failure */
2512 ring->hangcheck.score += BUSY;
2516 /* We always increment the hangcheck score
2517 * if the ring is busy and still processing
2518 * the same request, so that no single request
2519 * can run indefinitely (such as a chain of
2520 * batches). The only time we do not increment
2521 * the hangcheck score on this ring, if this
2522 * ring is in a legitimate wait for another
2523 * ring. In that case the waiting ring is a
2524 * victim and we want to be sure we catch the
2525 * right culprit. Then every time we do kick
2526 * the ring, add a small increment to the
2527 * score so that we can catch a batch that is
2528 * being repeatedly kicked and so responsible
2529 * for stalling the machine.
2531 ring->hangcheck.action = ring_stuck(ring,
2534 switch (ring->hangcheck.action) {
2535 case HANGCHECK_IDLE:
2536 case HANGCHECK_WAIT:
2538 case HANGCHECK_ACTIVE:
2539 ring->hangcheck.score += BUSY;
2541 case HANGCHECK_KICK:
2542 ring->hangcheck.score += KICK;
2544 case HANGCHECK_HUNG:
2545 ring->hangcheck.score += HUNG;
2551 ring->hangcheck.action = HANGCHECK_ACTIVE;
2553 /* Gradually reduce the count so that we catch DoS
2554 * attempts across multiple batches.
2556 if (ring->hangcheck.score > 0)
2557 ring->hangcheck.score--;
2560 ring->hangcheck.seqno = seqno;
2561 ring->hangcheck.acthd = acthd;
2565 for_each_ring(ring, dev_priv, i) {
2566 if (ring->hangcheck.score > FIRE) {
2567 DRM_INFO("%s on %s\n",
2568 stuck[i] ? "stuck" : "no progress",
2575 return i915_handle_error(dev, true);
2578 /* Reset timer case chip hangs without another request
2580 i915_queue_hangcheck(dev);
2583 void i915_queue_hangcheck(struct drm_device *dev)
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 if (!i915_enable_hangcheck)
2589 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2590 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2593 static void ibx_irq_preinstall(struct drm_device *dev)
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2597 if (HAS_PCH_NOP(dev))
2600 /* south display irq */
2601 I915_WRITE(SDEIMR, 0xffffffff);
2603 * SDEIER is also touched by the interrupt handler to work around missed
2604 * PCH interrupts. Hence we can't update it after the interrupt handler
2605 * is enabled - instead we unconditionally enable all PCH interrupt
2606 * sources here, but then only unmask them as needed with SDEIMR.
2608 I915_WRITE(SDEIER, 0xffffffff);
2609 POSTING_READ(SDEIER);
2612 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2617 I915_WRITE(GTIMR, 0xffffffff);
2618 I915_WRITE(GTIER, 0x0);
2619 POSTING_READ(GTIER);
2621 if (INTEL_INFO(dev)->gen >= 6) {
2623 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2624 I915_WRITE(GEN6_PMIER, 0x0);
2625 POSTING_READ(GEN6_PMIER);
2631 static void ironlake_irq_preinstall(struct drm_device *dev)
2633 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2635 atomic_set(&dev_priv->irq_received, 0);
2637 I915_WRITE(HWSTAM, 0xeffe);
2639 I915_WRITE(DEIMR, 0xffffffff);
2640 I915_WRITE(DEIER, 0x0);
2641 POSTING_READ(DEIER);
2643 gen5_gt_irq_preinstall(dev);
2645 ibx_irq_preinstall(dev);
2648 static void valleyview_irq_preinstall(struct drm_device *dev)
2650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2653 atomic_set(&dev_priv->irq_received, 0);
2656 I915_WRITE(VLV_IMR, 0);
2657 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2658 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2659 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2662 I915_WRITE(GTIIR, I915_READ(GTIIR));
2663 I915_WRITE(GTIIR, I915_READ(GTIIR));
2665 gen5_gt_irq_preinstall(dev);
2667 I915_WRITE(DPINVGTT, 0xff);
2669 I915_WRITE(PORT_HOTPLUG_EN, 0);
2670 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2672 I915_WRITE(PIPESTAT(pipe), 0xffff);
2673 I915_WRITE(VLV_IIR, 0xffffffff);
2674 I915_WRITE(VLV_IMR, 0xffffffff);
2675 I915_WRITE(VLV_IER, 0x0);
2676 POSTING_READ(VLV_IER);
2679 static void gen8_irq_preinstall(struct drm_device *dev)
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2684 atomic_set(&dev_priv->irq_received, 0);
2686 I915_WRITE(GEN8_MASTER_IRQ, 0);
2687 POSTING_READ(GEN8_MASTER_IRQ);
2689 /* IIR can theoretically queue up two events. Be paranoid */
2690 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2691 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2692 POSTING_READ(GEN8_##type##_IMR(which)); \
2693 I915_WRITE(GEN8_##type##_IER(which), 0); \
2694 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2695 POSTING_READ(GEN8_##type##_IIR(which)); \
2696 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2699 #define GEN8_IRQ_INIT(type) do { \
2700 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2701 POSTING_READ(GEN8_##type##_IMR); \
2702 I915_WRITE(GEN8_##type##_IER, 0); \
2703 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2704 POSTING_READ(GEN8_##type##_IIR); \
2705 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2708 GEN8_IRQ_INIT_NDX(GT, 0);
2709 GEN8_IRQ_INIT_NDX(GT, 1);
2710 GEN8_IRQ_INIT_NDX(GT, 2);
2711 GEN8_IRQ_INIT_NDX(GT, 3);
2713 for_each_pipe(pipe) {
2714 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2717 GEN8_IRQ_INIT(DE_PORT);
2718 GEN8_IRQ_INIT(DE_MISC);
2720 #undef GEN8_IRQ_INIT
2721 #undef GEN8_IRQ_INIT_NDX
2723 POSTING_READ(GEN8_PCU_IIR);
2725 ibx_irq_preinstall(dev);
2728 static void ibx_hpd_irq_setup(struct drm_device *dev)
2730 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2731 struct drm_mode_config *mode_config = &dev->mode_config;
2732 struct intel_encoder *intel_encoder;
2733 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2735 if (HAS_PCH_IBX(dev)) {
2736 hotplug_irqs = SDE_HOTPLUG_MASK;
2737 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2738 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2739 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2741 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2742 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2743 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2744 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2747 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2750 * Enable digital hotplug on the PCH, and configure the DP short pulse
2751 * duration to 2ms (which is the minimum in the Display Port spec)
2753 * This register is the same on all known PCH chips.
2755 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2756 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2757 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2758 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2759 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2760 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2763 static void ibx_irq_postinstall(struct drm_device *dev)
2765 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2768 if (HAS_PCH_NOP(dev))
2771 if (HAS_PCH_IBX(dev)) {
2772 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2773 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2775 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2777 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2780 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2781 I915_WRITE(SDEIMR, ~mask);
2784 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 u32 pm_irqs, gt_irqs;
2789 pm_irqs = gt_irqs = 0;
2791 dev_priv->gt_irq_mask = ~0;
2792 if (HAS_L3_DPF(dev)) {
2793 /* L3 parity interrupt is always unmasked. */
2794 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2795 gt_irqs |= GT_PARITY_ERROR(dev);
2798 gt_irqs |= GT_RENDER_USER_INTERRUPT;
2800 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2801 ILK_BSD_USER_INTERRUPT;
2803 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2806 I915_WRITE(GTIIR, I915_READ(GTIIR));
2807 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2808 I915_WRITE(GTIER, gt_irqs);
2809 POSTING_READ(GTIER);
2811 if (INTEL_INFO(dev)->gen >= 6) {
2812 pm_irqs |= GEN6_PM_RPS_EVENTS;
2815 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2817 dev_priv->pm_irq_mask = 0xffffffff;
2818 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2819 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2820 I915_WRITE(GEN6_PMIER, pm_irqs);
2821 POSTING_READ(GEN6_PMIER);
2825 static int ironlake_irq_postinstall(struct drm_device *dev)
2827 unsigned long irqflags;
2828 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2829 u32 display_mask, extra_mask;
2831 if (INTEL_INFO(dev)->gen >= 7) {
2832 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2833 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2834 DE_PLANEB_FLIP_DONE_IVB |
2835 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2837 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2838 DE_PIPEA_VBLANK_IVB);
2840 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2842 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2843 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2845 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
2846 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
2848 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2851 dev_priv->irq_mask = ~display_mask;
2853 /* should always can generate irq */
2854 I915_WRITE(DEIIR, I915_READ(DEIIR));
2855 I915_WRITE(DEIMR, dev_priv->irq_mask);
2856 I915_WRITE(DEIER, display_mask | extra_mask);
2857 POSTING_READ(DEIER);
2859 gen5_gt_irq_postinstall(dev);
2861 ibx_irq_postinstall(dev);
2863 if (IS_IRONLAKE_M(dev)) {
2864 /* Enable PCU event interrupts
2866 * spinlocking not required here for correctness since interrupt
2867 * setup is guaranteed to run in single-threaded context. But we
2868 * need it to make the assert_spin_locked happy. */
2869 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2870 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2871 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2877 static int valleyview_irq_postinstall(struct drm_device *dev)
2879 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2881 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV |
2882 PIPE_CRC_DONE_ENABLE;
2883 unsigned long irqflags;
2885 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2886 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2887 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2888 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2889 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2892 *Leave vblank interrupts masked initially. enable/disable will
2893 * toggle them based on usage.
2895 dev_priv->irq_mask = (~enable_mask) |
2896 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2897 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2899 I915_WRITE(PORT_HOTPLUG_EN, 0);
2900 POSTING_READ(PORT_HOTPLUG_EN);
2902 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2903 I915_WRITE(VLV_IER, enable_mask);
2904 I915_WRITE(VLV_IIR, 0xffffffff);
2905 I915_WRITE(PIPESTAT(0), 0xffff);
2906 I915_WRITE(PIPESTAT(1), 0xffff);
2907 POSTING_READ(VLV_IER);
2909 /* Interrupt setup is already guaranteed to be single-threaded, this is
2910 * just to make the assert_spin_locked check happy. */
2911 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2912 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2913 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
2914 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2915 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2917 I915_WRITE(VLV_IIR, 0xffffffff);
2918 I915_WRITE(VLV_IIR, 0xffffffff);
2920 gen5_gt_irq_postinstall(dev);
2922 /* ack & enable invalid PTE error interrupts */
2923 #if 0 /* FIXME: add support to irq handler for checking these bits */
2924 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2925 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2928 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2933 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
2937 /* These are interrupts we'll toggle with the ring mask register */
2938 uint32_t gt_interrupts[] = {
2939 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
2940 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
2941 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
2942 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
2943 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
2945 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
2948 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
2949 u32 tmp = I915_READ(GEN8_GT_IIR(i));
2951 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2953 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
2954 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
2956 POSTING_READ(GEN8_GT_IER(0));
2959 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
2961 struct drm_device *dev = dev_priv->dev;
2962 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
2963 GEN8_PIPE_CDCLK_CRC_DONE |
2964 GEN8_PIPE_FIFO_UNDERRUN |
2965 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2966 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
2968 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
2969 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
2970 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
2972 for_each_pipe(pipe) {
2973 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2975 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
2977 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2978 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
2980 POSTING_READ(GEN8_DE_PIPE_ISR(0));
2982 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
2983 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
2984 POSTING_READ(GEN8_DE_PORT_IER);
2987 static int gen8_irq_postinstall(struct drm_device *dev)
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2991 gen8_gt_irq_postinstall(dev_priv);
2992 gen8_de_irq_postinstall(dev_priv);
2994 ibx_irq_postinstall(dev);
2996 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
2997 POSTING_READ(GEN8_MASTER_IRQ);
3002 static void gen8_irq_uninstall(struct drm_device *dev)
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3010 atomic_set(&dev_priv->irq_received, 0);
3012 I915_WRITE(GEN8_MASTER_IRQ, 0);
3014 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3015 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3016 I915_WRITE(GEN8_##type##_IER(which), 0); \
3017 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3020 #define GEN8_IRQ_FINI(type) do { \
3021 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3022 I915_WRITE(GEN8_##type##_IER, 0); \
3023 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3026 GEN8_IRQ_FINI_NDX(GT, 0);
3027 GEN8_IRQ_FINI_NDX(GT, 1);
3028 GEN8_IRQ_FINI_NDX(GT, 2);
3029 GEN8_IRQ_FINI_NDX(GT, 3);
3031 for_each_pipe(pipe) {
3032 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3035 GEN8_IRQ_FINI(DE_PORT);
3036 GEN8_IRQ_FINI(DE_MISC);
3038 #undef GEN8_IRQ_FINI
3039 #undef GEN8_IRQ_FINI_NDX
3041 POSTING_READ(GEN8_PCU_IIR);
3044 static void valleyview_irq_uninstall(struct drm_device *dev)
3046 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3052 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3055 I915_WRITE(PIPESTAT(pipe), 0xffff);
3057 I915_WRITE(HWSTAM, 0xffffffff);
3058 I915_WRITE(PORT_HOTPLUG_EN, 0);
3059 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3061 I915_WRITE(PIPESTAT(pipe), 0xffff);
3062 I915_WRITE(VLV_IIR, 0xffffffff);
3063 I915_WRITE(VLV_IMR, 0xffffffff);
3064 I915_WRITE(VLV_IER, 0x0);
3065 POSTING_READ(VLV_IER);
3068 static void ironlake_irq_uninstall(struct drm_device *dev)
3070 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3075 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3077 I915_WRITE(HWSTAM, 0xffffffff);
3079 I915_WRITE(DEIMR, 0xffffffff);
3080 I915_WRITE(DEIER, 0x0);
3081 I915_WRITE(DEIIR, I915_READ(DEIIR));
3083 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3085 I915_WRITE(GTIMR, 0xffffffff);
3086 I915_WRITE(GTIER, 0x0);
3087 I915_WRITE(GTIIR, I915_READ(GTIIR));
3089 if (HAS_PCH_NOP(dev))
3092 I915_WRITE(SDEIMR, 0xffffffff);
3093 I915_WRITE(SDEIER, 0x0);
3094 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3095 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3096 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3099 static void i8xx_irq_preinstall(struct drm_device * dev)
3101 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3104 atomic_set(&dev_priv->irq_received, 0);
3107 I915_WRITE(PIPESTAT(pipe), 0);
3108 I915_WRITE16(IMR, 0xffff);
3109 I915_WRITE16(IER, 0x0);
3110 POSTING_READ16(IER);
3113 static int i8xx_irq_postinstall(struct drm_device *dev)
3115 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3116 unsigned long irqflags;
3119 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3121 /* Unmask the interrupts that we always want on. */
3122 dev_priv->irq_mask =
3123 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3124 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3125 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3126 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3127 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3128 I915_WRITE16(IMR, dev_priv->irq_mask);
3131 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3132 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3133 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3134 I915_USER_INTERRUPT);
3135 POSTING_READ16(IER);
3137 /* Interrupt setup is already guaranteed to be single-threaded, this is
3138 * just to make the assert_spin_locked check happy. */
3139 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3140 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3141 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3142 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3148 * Returns true when a page flip has completed.
3150 static bool i8xx_handle_vblank(struct drm_device *dev,
3151 int plane, int pipe, u32 iir)
3153 drm_i915_private_t *dev_priv = dev->dev_private;
3154 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3156 if (!drm_handle_vblank(dev, pipe))
3159 if ((iir & flip_pending) == 0)
3162 intel_prepare_page_flip(dev, plane);
3164 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3165 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3166 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3167 * the flip is completed (no longer pending). Since this doesn't raise
3168 * an interrupt per se, we watch for the change at vblank.
3170 if (I915_READ16(ISR) & flip_pending)
3173 intel_finish_page_flip(dev, pipe);
3178 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3180 struct drm_device *dev = (struct drm_device *) arg;
3181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3184 unsigned long irqflags;
3187 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3188 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3190 atomic_inc(&dev_priv->irq_received);
3192 iir = I915_READ16(IIR);
3196 while (iir & ~flip_mask) {
3197 /* Can't rely on pipestat interrupt bit in iir as it might
3198 * have been cleared after the pipestat interrupt was received.
3199 * It doesn't set the bit in iir again, but it still produces
3200 * interrupts (for non-MSI).
3202 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3203 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3204 i915_handle_error(dev, false);
3206 for_each_pipe(pipe) {
3207 int reg = PIPESTAT(pipe);
3208 pipe_stats[pipe] = I915_READ(reg);
3211 * Clear the PIPE*STAT regs before the IIR
3213 if (pipe_stats[pipe] & 0x8000ffff) {
3214 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3215 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3217 I915_WRITE(reg, pipe_stats[pipe]);
3220 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3222 I915_WRITE16(IIR, iir & ~flip_mask);
3223 new_iir = I915_READ16(IIR); /* Flush posted writes */
3225 i915_update_dri1_breadcrumb(dev);
3227 if (iir & I915_USER_INTERRUPT)
3228 notify_ring(dev, &dev_priv->ring[RCS]);
3230 for_each_pipe(pipe) {
3235 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3236 i8xx_handle_vblank(dev, plane, pipe, iir))
3237 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3239 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3240 i9xx_pipe_crc_irq_handler(dev, pipe);
3249 static void i8xx_irq_uninstall(struct drm_device * dev)
3251 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3254 for_each_pipe(pipe) {
3255 /* Clear enable bits; then clear status bits */
3256 I915_WRITE(PIPESTAT(pipe), 0);
3257 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3259 I915_WRITE16(IMR, 0xffff);
3260 I915_WRITE16(IER, 0x0);
3261 I915_WRITE16(IIR, I915_READ16(IIR));
3264 static void i915_irq_preinstall(struct drm_device * dev)
3266 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3269 atomic_set(&dev_priv->irq_received, 0);
3271 if (I915_HAS_HOTPLUG(dev)) {
3272 I915_WRITE(PORT_HOTPLUG_EN, 0);
3273 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3276 I915_WRITE16(HWSTAM, 0xeffe);
3278 I915_WRITE(PIPESTAT(pipe), 0);
3279 I915_WRITE(IMR, 0xffffffff);
3280 I915_WRITE(IER, 0x0);
3284 static int i915_irq_postinstall(struct drm_device *dev)
3286 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3288 unsigned long irqflags;
3290 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3292 /* Unmask the interrupts that we always want on. */
3293 dev_priv->irq_mask =
3294 ~(I915_ASLE_INTERRUPT |
3295 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3296 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3297 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3298 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3299 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3302 I915_ASLE_INTERRUPT |
3303 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3304 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3305 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3306 I915_USER_INTERRUPT;
3308 if (I915_HAS_HOTPLUG(dev)) {
3309 I915_WRITE(PORT_HOTPLUG_EN, 0);
3310 POSTING_READ(PORT_HOTPLUG_EN);
3312 /* Enable in IER... */
3313 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3314 /* and unmask in IMR */
3315 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3318 I915_WRITE(IMR, dev_priv->irq_mask);
3319 I915_WRITE(IER, enable_mask);
3322 i915_enable_asle_pipestat(dev);
3324 /* Interrupt setup is already guaranteed to be single-threaded, this is
3325 * just to make the assert_spin_locked check happy. */
3326 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3327 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3328 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3329 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3335 * Returns true when a page flip has completed.
3337 static bool i915_handle_vblank(struct drm_device *dev,
3338 int plane, int pipe, u32 iir)
3340 drm_i915_private_t *dev_priv = dev->dev_private;
3341 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3343 if (!drm_handle_vblank(dev, pipe))
3346 if ((iir & flip_pending) == 0)
3349 intel_prepare_page_flip(dev, plane);
3351 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3352 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3353 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3354 * the flip is completed (no longer pending). Since this doesn't raise
3355 * an interrupt per se, we watch for the change at vblank.
3357 if (I915_READ(ISR) & flip_pending)
3360 intel_finish_page_flip(dev, pipe);
3365 static irqreturn_t i915_irq_handler(int irq, void *arg)
3367 struct drm_device *dev = (struct drm_device *) arg;
3368 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3369 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3370 unsigned long irqflags;
3372 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3373 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3374 int pipe, ret = IRQ_NONE;
3376 atomic_inc(&dev_priv->irq_received);
3378 iir = I915_READ(IIR);
3380 bool irq_received = (iir & ~flip_mask) != 0;
3381 bool blc_event = false;
3383 /* Can't rely on pipestat interrupt bit in iir as it might
3384 * have been cleared after the pipestat interrupt was received.
3385 * It doesn't set the bit in iir again, but it still produces
3386 * interrupts (for non-MSI).
3388 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3389 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3390 i915_handle_error(dev, false);
3392 for_each_pipe(pipe) {
3393 int reg = PIPESTAT(pipe);
3394 pipe_stats[pipe] = I915_READ(reg);
3396 /* Clear the PIPE*STAT regs before the IIR */
3397 if (pipe_stats[pipe] & 0x8000ffff) {
3398 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3399 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3401 I915_WRITE(reg, pipe_stats[pipe]);
3402 irq_received = true;
3405 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3410 /* Consume port. Then clear IIR or we'll miss events */
3411 if ((I915_HAS_HOTPLUG(dev)) &&
3412 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3413 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3414 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3416 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3419 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3421 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3422 POSTING_READ(PORT_HOTPLUG_STAT);
3425 I915_WRITE(IIR, iir & ~flip_mask);
3426 new_iir = I915_READ(IIR); /* Flush posted writes */
3428 if (iir & I915_USER_INTERRUPT)
3429 notify_ring(dev, &dev_priv->ring[RCS]);
3431 for_each_pipe(pipe) {
3436 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3437 i915_handle_vblank(dev, plane, pipe, iir))
3438 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3440 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3443 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3444 i9xx_pipe_crc_irq_handler(dev, pipe);
3447 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3448 intel_opregion_asle_intr(dev);
3450 /* With MSI, interrupts are only generated when iir
3451 * transitions from zero to nonzero. If another bit got
3452 * set while we were handling the existing iir bits, then
3453 * we would never get another interrupt.
3455 * This is fine on non-MSI as well, as if we hit this path
3456 * we avoid exiting the interrupt handler only to generate
3459 * Note that for MSI this could cause a stray interrupt report
3460 * if an interrupt landed in the time between writing IIR and
3461 * the posting read. This should be rare enough to never
3462 * trigger the 99% of 100,000 interrupts test for disabling
3467 } while (iir & ~flip_mask);
3469 i915_update_dri1_breadcrumb(dev);
3474 static void i915_irq_uninstall(struct drm_device * dev)
3476 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3479 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3481 if (I915_HAS_HOTPLUG(dev)) {
3482 I915_WRITE(PORT_HOTPLUG_EN, 0);
3483 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3486 I915_WRITE16(HWSTAM, 0xffff);
3487 for_each_pipe(pipe) {
3488 /* Clear enable bits; then clear status bits */
3489 I915_WRITE(PIPESTAT(pipe), 0);
3490 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3492 I915_WRITE(IMR, 0xffffffff);
3493 I915_WRITE(IER, 0x0);
3495 I915_WRITE(IIR, I915_READ(IIR));
3498 static void i965_irq_preinstall(struct drm_device * dev)
3500 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3503 atomic_set(&dev_priv->irq_received, 0);
3505 I915_WRITE(PORT_HOTPLUG_EN, 0);
3506 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3508 I915_WRITE(HWSTAM, 0xeffe);
3510 I915_WRITE(PIPESTAT(pipe), 0);
3511 I915_WRITE(IMR, 0xffffffff);
3512 I915_WRITE(IER, 0x0);
3516 static int i965_irq_postinstall(struct drm_device *dev)
3518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3521 unsigned long irqflags;
3523 /* Unmask the interrupts that we always want on. */
3524 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3525 I915_DISPLAY_PORT_INTERRUPT |
3526 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3527 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3528 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3529 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3530 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3532 enable_mask = ~dev_priv->irq_mask;
3533 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3534 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3535 enable_mask |= I915_USER_INTERRUPT;
3538 enable_mask |= I915_BSD_USER_INTERRUPT;
3540 /* Interrupt setup is already guaranteed to be single-threaded, this is
3541 * just to make the assert_spin_locked check happy. */
3542 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3543 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE);
3544 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE);
3545 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE);
3546 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3549 * Enable some error detection, note the instruction error mask
3550 * bit is reserved, so we leave it masked.
3553 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3554 GM45_ERROR_MEM_PRIV |
3555 GM45_ERROR_CP_PRIV |
3556 I915_ERROR_MEMORY_REFRESH);
3558 error_mask = ~(I915_ERROR_PAGE_TABLE |
3559 I915_ERROR_MEMORY_REFRESH);
3561 I915_WRITE(EMR, error_mask);
3563 I915_WRITE(IMR, dev_priv->irq_mask);
3564 I915_WRITE(IER, enable_mask);
3567 I915_WRITE(PORT_HOTPLUG_EN, 0);
3568 POSTING_READ(PORT_HOTPLUG_EN);
3570 i915_enable_asle_pipestat(dev);
3575 static void i915_hpd_irq_setup(struct drm_device *dev)
3577 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3578 struct drm_mode_config *mode_config = &dev->mode_config;
3579 struct intel_encoder *intel_encoder;
3582 assert_spin_locked(&dev_priv->irq_lock);
3584 if (I915_HAS_HOTPLUG(dev)) {
3585 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3586 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3587 /* Note HDMI and DP share hotplug bits */
3588 /* enable bits are the same for all generations */
3589 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3590 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3591 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3592 /* Programming the CRT detection parameters tends
3593 to generate a spurious hotplug event about three
3594 seconds later. So just do it once.
3597 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3598 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3599 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3601 /* Ignore TV since it's buggy */
3602 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3606 static irqreturn_t i965_irq_handler(int irq, void *arg)
3608 struct drm_device *dev = (struct drm_device *) arg;
3609 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3611 u32 pipe_stats[I915_MAX_PIPES];
3612 unsigned long irqflags;
3614 int ret = IRQ_NONE, pipe;
3616 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3617 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3619 atomic_inc(&dev_priv->irq_received);
3621 iir = I915_READ(IIR);
3624 bool blc_event = false;
3626 irq_received = (iir & ~flip_mask) != 0;
3628 /* Can't rely on pipestat interrupt bit in iir as it might
3629 * have been cleared after the pipestat interrupt was received.
3630 * It doesn't set the bit in iir again, but it still produces
3631 * interrupts (for non-MSI).
3633 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3634 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3635 i915_handle_error(dev, false);
3637 for_each_pipe(pipe) {
3638 int reg = PIPESTAT(pipe);
3639 pipe_stats[pipe] = I915_READ(reg);
3642 * Clear the PIPE*STAT regs before the IIR
3644 if (pipe_stats[pipe] & 0x8000ffff) {
3645 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3646 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3648 I915_WRITE(reg, pipe_stats[pipe]);
3652 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3659 /* Consume port. Then clear IIR or we'll miss events */
3660 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3661 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3662 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3663 HOTPLUG_INT_STATUS_G4X :
3664 HOTPLUG_INT_STATUS_I915);
3666 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3669 intel_hpd_irq_handler(dev, hotplug_trigger,
3670 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3673 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3674 dp_aux_irq_handler(dev);
3676 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3677 I915_READ(PORT_HOTPLUG_STAT);
3680 I915_WRITE(IIR, iir & ~flip_mask);
3681 new_iir = I915_READ(IIR); /* Flush posted writes */
3683 if (iir & I915_USER_INTERRUPT)
3684 notify_ring(dev, &dev_priv->ring[RCS]);
3685 if (iir & I915_BSD_USER_INTERRUPT)
3686 notify_ring(dev, &dev_priv->ring[VCS]);
3688 for_each_pipe(pipe) {
3689 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3690 i915_handle_vblank(dev, pipe, pipe, iir))
3691 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3693 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3696 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3697 i9xx_pipe_crc_irq_handler(dev, pipe);
3701 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3702 intel_opregion_asle_intr(dev);
3704 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3705 gmbus_irq_handler(dev);
3707 /* With MSI, interrupts are only generated when iir
3708 * transitions from zero to nonzero. If another bit got
3709 * set while we were handling the existing iir bits, then
3710 * we would never get another interrupt.
3712 * This is fine on non-MSI as well, as if we hit this path
3713 * we avoid exiting the interrupt handler only to generate
3716 * Note that for MSI this could cause a stray interrupt report
3717 * if an interrupt landed in the time between writing IIR and
3718 * the posting read. This should be rare enough to never
3719 * trigger the 99% of 100,000 interrupts test for disabling
3725 i915_update_dri1_breadcrumb(dev);
3730 static void i965_irq_uninstall(struct drm_device * dev)
3732 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3738 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3740 I915_WRITE(PORT_HOTPLUG_EN, 0);
3741 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3743 I915_WRITE(HWSTAM, 0xffffffff);
3745 I915_WRITE(PIPESTAT(pipe), 0);
3746 I915_WRITE(IMR, 0xffffffff);
3747 I915_WRITE(IER, 0x0);
3750 I915_WRITE(PIPESTAT(pipe),
3751 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3752 I915_WRITE(IIR, I915_READ(IIR));
3755 static void i915_reenable_hotplug_timer_func(unsigned long data)
3757 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3758 struct drm_device *dev = dev_priv->dev;
3759 struct drm_mode_config *mode_config = &dev->mode_config;
3760 unsigned long irqflags;
3763 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3764 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3765 struct drm_connector *connector;
3767 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3770 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3772 list_for_each_entry(connector, &mode_config->connector_list, head) {
3773 struct intel_connector *intel_connector = to_intel_connector(connector);
3775 if (intel_connector->encoder->hpd_pin == i) {
3776 if (connector->polled != intel_connector->polled)
3777 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3778 drm_get_connector_name(connector));
3779 connector->polled = intel_connector->polled;
3780 if (!connector->polled)
3781 connector->polled = DRM_CONNECTOR_POLL_HPD;
3785 if (dev_priv->display.hpd_irq_setup)
3786 dev_priv->display.hpd_irq_setup(dev);
3787 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3790 void intel_irq_init(struct drm_device *dev)
3792 struct drm_i915_private *dev_priv = dev->dev_private;
3794 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3795 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3796 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3797 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3799 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3800 i915_hangcheck_elapsed,
3801 (unsigned long) dev);
3802 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3803 (unsigned long) dev_priv);
3805 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3808 dev->max_vblank_count = 0;
3809 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
3810 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3811 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3812 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3814 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3815 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3818 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3819 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3820 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3823 if (IS_VALLEYVIEW(dev)) {
3824 dev->driver->irq_handler = valleyview_irq_handler;
3825 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3826 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3827 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3828 dev->driver->enable_vblank = valleyview_enable_vblank;
3829 dev->driver->disable_vblank = valleyview_disable_vblank;
3830 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3831 } else if (IS_GEN8(dev)) {
3832 dev->driver->irq_handler = gen8_irq_handler;
3833 dev->driver->irq_preinstall = gen8_irq_preinstall;
3834 dev->driver->irq_postinstall = gen8_irq_postinstall;
3835 dev->driver->irq_uninstall = gen8_irq_uninstall;
3836 dev->driver->enable_vblank = gen8_enable_vblank;
3837 dev->driver->disable_vblank = gen8_disable_vblank;
3838 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3839 } else if (HAS_PCH_SPLIT(dev)) {
3840 dev->driver->irq_handler = ironlake_irq_handler;
3841 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3842 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3843 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3844 dev->driver->enable_vblank = ironlake_enable_vblank;
3845 dev->driver->disable_vblank = ironlake_disable_vblank;
3846 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3848 if (INTEL_INFO(dev)->gen == 2) {
3849 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3850 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3851 dev->driver->irq_handler = i8xx_irq_handler;
3852 dev->driver->irq_uninstall = i8xx_irq_uninstall;
3853 } else if (INTEL_INFO(dev)->gen == 3) {
3854 dev->driver->irq_preinstall = i915_irq_preinstall;
3855 dev->driver->irq_postinstall = i915_irq_postinstall;
3856 dev->driver->irq_uninstall = i915_irq_uninstall;
3857 dev->driver->irq_handler = i915_irq_handler;
3858 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3860 dev->driver->irq_preinstall = i965_irq_preinstall;
3861 dev->driver->irq_postinstall = i965_irq_postinstall;
3862 dev->driver->irq_uninstall = i965_irq_uninstall;
3863 dev->driver->irq_handler = i965_irq_handler;
3864 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3866 dev->driver->enable_vblank = i915_enable_vblank;
3867 dev->driver->disable_vblank = i915_disable_vblank;
3871 void intel_hpd_init(struct drm_device *dev)
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct drm_mode_config *mode_config = &dev->mode_config;
3875 struct drm_connector *connector;
3876 unsigned long irqflags;
3879 for (i = 1; i < HPD_NUM_PINS; i++) {
3880 dev_priv->hpd_stats[i].hpd_cnt = 0;
3881 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3883 list_for_each_entry(connector, &mode_config->connector_list, head) {
3884 struct intel_connector *intel_connector = to_intel_connector(connector);
3885 connector->polled = intel_connector->polled;
3886 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3887 connector->polled = DRM_CONNECTOR_POLL_HPD;
3890 /* Interrupt setup is already guaranteed to be single-threaded, this is
3891 * just to make the assert_spin_locked checks happy. */
3892 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3893 if (dev_priv->display.hpd_irq_setup)
3894 dev_priv->display.hpd_irq_setup(dev);
3895 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3898 /* Disable interrupts so we can allow Package C8+. */
3899 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902 unsigned long irqflags;
3904 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3906 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3907 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3908 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3909 dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3910 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3912 ironlake_disable_display_irq(dev_priv, 0xffffffff);
3913 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
3914 ilk_disable_gt_irq(dev_priv, 0xffffffff);
3915 snb_disable_pm_irq(dev_priv, 0xffffffff);
3917 dev_priv->pc8.irqs_disabled = true;
3919 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3922 /* Restore interrupts so we can recover from Package C8+. */
3923 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 unsigned long irqflags;
3929 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3931 val = I915_READ(DEIMR);
3932 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
3934 val = I915_READ(SDEIMR);
3935 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
3937 val = I915_READ(GTIMR);
3938 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
3940 val = I915_READ(GEN6_PMIMR);
3941 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
3943 dev_priv->pc8.irqs_disabled = false;
3945 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3946 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
3947 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3948 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3949 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3951 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);