Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /* For display hotplug interrupt */
  41 static void
  42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  43 {
  44         if ((dev_priv->irq_mask & mask) != 0) {
  45                 dev_priv->irq_mask &= ~mask;
  46                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  47                 POSTING_READ(DEIMR);
  48         }
  49 }
  50
  51 static inline void
  52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  53 {
  54         if ((dev_priv->irq_mask & mask) != mask) {
  55                 dev_priv->irq_mask |= mask;
  56                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  57                 POSTING_READ(DEIMR);
  58         }
  59 }
  60
  61 void
  62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  63 {
  64         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  65                 u32 reg = PIPESTAT(pipe);
  66
  67                 dev_priv->pipestat[pipe] |= mask;
  68                 /* Enable the interrupt, clear any pending status */
  69                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  70                 POSTING_READ(reg);
  71         }
  72 }
  73
  74 void
  75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  76 {
  77         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  78                 u32 reg = PIPESTAT(pipe);
  79
  80                 dev_priv->pipestat[pipe] &= ~mask;
  81                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  82                 POSTING_READ(reg);
  83         }
  84 }
  85
  86 /**
  87  * intel_enable_asle - enable ASLE interrupt for OpRegion
  88  */
  89 void intel_enable_asle(struct drm_device *dev)
  90 {
  91         drm_i915_private_t *dev_priv = dev->dev_private;
  92         unsigned long irqflags;
  93
  94         /* FIXME: opregion/asle for VLV */
  95         if (IS_VALLEYVIEW(dev))
  96                 return;
  97
  98         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  99
 100         if (HAS_PCH_SPLIT(dev))
 101                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 102         else {
 103                 i915_enable_pipestat(dev_priv, 1,
 104                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 105                 if (INTEL_INFO(dev)->gen >= 4)
 106                         i915_enable_pipestat(dev_priv, 0,
 107                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 108         }
 109
 110         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 111 }
 112
 113 /**
 114  * i915_pipe_enabled - check if a pipe is enabled
 115  * @dev: DRM device
 116  * @pipe: pipe to check
 117  *
 118  * Reading certain registers when the pipe is disabled can hang the chip.
 119  * Use this routine to make sure the PLL is running and the pipe is active
 120  * before reading such registers if unsure.
 121  */
 122 static int
 123 i915_pipe_enabled(struct drm_device *dev, int pipe)
 124 {
 125         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 126         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 127 }
 128
 129 /* Called from drm generic code, passed a 'crtc', which
 130  * we use as a pipe index
 131  */
 132 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 133 {
 134         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 135         unsigned long high_frame;
 136         unsigned long low_frame;
 137         u32 high1, high2, low;
 138
 139         if (!i915_pipe_enabled(dev, pipe)) {
 140                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 141                                 "pipe %c\n", pipe_name(pipe));
 142                 return 0;
 143         }
 144
 145         high_frame = PIPEFRAME(pipe);
 146         low_frame = PIPEFRAMEPIXEL(pipe);
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 155                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 156                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157         } while (high1 != high2);
 158
 159         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 160         low >>= PIPE_FRAME_LOW_SHIFT;
 161         return (high1 << 8) | low;
 162 }
 163
 164 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 165 {
 166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 167         int reg = PIPE_FRMCOUNT_GM45(pipe);
 168
 169         if (!i915_pipe_enabled(dev, pipe)) {
 170                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 171                                  "pipe %c\n", pipe_name(pipe));
 172                 return 0;
 173         }
 174
 175         return I915_READ(reg);
 176 }
 177
 178 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 179                              int *vpos, int *hpos)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         u32 vbl = 0, position = 0;
 183         int vbl_start, vbl_end, htotal, vtotal;
 184         bool in_vbl = true;
 185         int ret = 0;
 186
 187         if (!i915_pipe_enabled(dev, pipe)) {
 188                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 189                                  "pipe %c\n", pipe_name(pipe));
 190                 return 0;
 191         }
 192
 193         /* Get vtotal. */
 194         vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
 195
 196         if (INTEL_INFO(dev)->gen >= 4) {
 197                 /* No obvious pixelcount register. Only query vertical
 198                  * scanout position from Display scan line register.
 199                  */
 200                 position = I915_READ(PIPEDSL(pipe));
 201
 202                 /* Decode into vertical scanout position. Don't have
 203                  * horizontal scanout position.
 204                  */
 205                 *vpos = position & 0x1fff;
 206                 *hpos = 0;
 207         } else {
 208                 /* Have access to pixelcount since start of frame.
 209                  * We can split this into vertical and horizontal
 210                  * scanout position.
 211                  */
 212                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 213
 214                 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
 215                 *vpos = position / htotal;
 216                 *hpos = position - (*vpos * htotal);
 217         }
 218
 219         /* Query vblank area. */
 220         vbl = I915_READ(VBLANK(pipe));
 221
 222         /* Test position against vblank region. */
 223         vbl_start = vbl & 0x1fff;
 224         vbl_end = (vbl >> 16) & 0x1fff;
 225
 226         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 227                 in_vbl = false;
 228
 229         /* Inside "upper part" of vblank area? Apply corrective offset: */
 230         if (in_vbl && (*vpos >= vbl_start))
 231                 *vpos = *vpos - vtotal;
 232
 233         /* Readouts valid? */
 234         if (vbl > 0)
 235                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 236
 237         /* In vblank? */
 238         if (in_vbl)
 239                 ret |= DRM_SCANOUTPOS_INVBL;
 240
 241         return ret;
 242 }
 243
 244 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 245                               int *max_error,
 246                               struct timeval *vblank_time,
 247                               unsigned flags)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250         struct drm_crtc *crtc;
 251
 252         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 253                 DRM_ERROR("Invalid crtc %d\n", pipe);
 254                 return -EINVAL;
 255         }
 256
 257         /* Get drm_crtc to timestamp: */
 258         crtc = intel_get_crtc_for_pipe(dev, pipe);
 259         if (crtc == NULL) {
 260                 DRM_ERROR("Invalid crtc %d\n", pipe);
 261                 return -EINVAL;
 262         }
 263
 264         if (!crtc->enabled) {
 265                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 266                 return -EBUSY;
 267         }
 268
 269         /* Helper routine in DRM core does all the work: */
 270         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 271                                                      vblank_time, flags,
 272                                                      crtc);
 273 }
 274
 275 /*
 276  * Handle hotplug events outside the interrupt handler proper.
 277  */
 278 static void i915_hotplug_work_func(struct work_struct *work)
 279 {
 280         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 281                                                     hotplug_work);
 282         struct drm_device *dev = dev_priv->dev;
 283         struct drm_mode_config *mode_config = &dev->mode_config;
 284         struct intel_encoder *encoder;
 285
 286         mutex_lock(&mode_config->mutex);
 287         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 288
 289         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 290                 if (encoder->hot_plug)
 291                         encoder->hot_plug(encoder);
 292
 293         mutex_unlock(&mode_config->mutex);
 294
 295         /* Just fire off a uevent and let userspace tell us what to do */
 296         drm_helper_hpd_irq_event(dev);
 297 }
 298
 299 /* defined intel_pm.c */
 300 extern spinlock_t mchdev_lock;
 301
 302 static void ironlake_handle_rps_change(struct drm_device *dev)
 303 {
 304         drm_i915_private_t *dev_priv = dev->dev_private;
 305         u32 busy_up, busy_down, max_avg, min_avg;
 306         u8 new_delay;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&mchdev_lock, flags);
 310
 311         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 312
 313         new_delay = dev_priv->ips.cur_delay;
 314
 315         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 316         busy_up = I915_READ(RCPREVBSYTUPAVG);
 317         busy_down = I915_READ(RCPREVBSYTDNAVG);
 318         max_avg = I915_READ(RCBMAXAVG);
 319         min_avg = I915_READ(RCBMINAVG);
 320
 321         /* Handle RCS change request from hw */
 322         if (busy_up > max_avg) {
 323                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 324                         new_delay = dev_priv->ips.cur_delay - 1;
 325                 if (new_delay < dev_priv->ips.max_delay)
 326                         new_delay = dev_priv->ips.max_delay;
 327         } else if (busy_down < min_avg) {
 328                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 329                         new_delay = dev_priv->ips.cur_delay + 1;
 330                 if (new_delay > dev_priv->ips.min_delay)
 331                         new_delay = dev_priv->ips.min_delay;
 332         }
 333
 334         if (ironlake_set_drps(dev, new_delay))
 335                 dev_priv->ips.cur_delay = new_delay;
 336
 337         spin_unlock_irqrestore(&mchdev_lock, flags);
 338
 339         return;
 340 }
 341
 342 static void notify_ring(struct drm_device *dev,
 343                         struct intel_ring_buffer *ring)
 344 {
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346
 347         if (ring->obj == NULL)
 348                 return;
 349
 350         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 351
 352         wake_up_all(&ring->irq_queue);
 353         if (i915_enable_hangcheck) {
 354                 dev_priv->hangcheck_count = 0;
 355                 mod_timer(&dev_priv->hangcheck_timer,
 356                           jiffies +
 357                           msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 358         }
 359 }
 360
 361 static void gen6_pm_rps_work(struct work_struct *work)
 362 {
 363         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 364                                                     rps.work);
 365         u32 pm_iir, pm_imr;
 366         u8 new_delay;
 367
 368         spin_lock_irq(&dev_priv->rps.lock);
 369         pm_iir = dev_priv->rps.pm_iir;
 370         dev_priv->rps.pm_iir = 0;
 371         pm_imr = I915_READ(GEN6_PMIMR);
 372         I915_WRITE(GEN6_PMIMR, 0);
 373         spin_unlock_irq(&dev_priv->rps.lock);
 374
 375         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 376                 return;
 377
 378         mutex_lock(&dev_priv->dev->struct_mutex);
 379
 380         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 381                 new_delay = dev_priv->rps.cur_delay + 1;
 382         else
 383                 new_delay = dev_priv->rps.cur_delay - 1;
 384
 385         /* sysfs frequency interfaces may have snuck in while servicing the
 386          * interrupt
 387          */
 388         if (!(new_delay > dev_priv->rps.max_delay ||
 389               new_delay < dev_priv->rps.min_delay)) {
 390                 gen6_set_rps(dev_priv->dev, new_delay);
 391         }
 392
 393         mutex_unlock(&dev_priv->dev->struct_mutex);
 394 }
 395
 396
 397 /**
 398  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 399  * occurred.
 400  * @work: workqueue struct
 401  *
 402  * Doesn't actually do anything except notify userspace. As a consequence of
 403  * this event, userspace should try to remap the bad rows since statistically
 404  * it is likely the same row is more likely to go bad again.
 405  */
 406 static void ivybridge_parity_work(struct work_struct *work)
 407 {
 408         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 409                                                     parity_error_work);
 410         u32 error_status, row, bank, subbank;
 411         char *parity_event[5];
 412         uint32_t misccpctl;
 413         unsigned long flags;
 414
 415         /* We must turn off DOP level clock gating to access the L3 registers.
 416          * In order to prevent a get/put style interface, acquire struct mutex
 417          * any time we access those registers.
 418          */
 419         mutex_lock(&dev_priv->dev->struct_mutex);
 420
 421         misccpctl = I915_READ(GEN7_MISCCPCTL);
 422         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 423         POSTING_READ(GEN7_MISCCPCTL);
 424
 425         error_status = I915_READ(GEN7_L3CDERRST1);
 426         row = GEN7_PARITY_ERROR_ROW(error_status);
 427         bank = GEN7_PARITY_ERROR_BANK(error_status);
 428         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 429
 430         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 431                                     GEN7_L3CDERRST1_ENABLE);
 432         POSTING_READ(GEN7_L3CDERRST1);
 433
 434         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 435
 436         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 437         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 438         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 439         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 440
 441         mutex_unlock(&dev_priv->dev->struct_mutex);
 442
 443         parity_event[0] = "L3_PARITY_ERROR=1";
 444         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 445         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 446         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 447         parity_event[4] = NULL;
 448
 449         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 450                            KOBJ_CHANGE, parity_event);
 451
 452         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 453                   row, bank, subbank);
 454
 455         kfree(parity_event[3]);
 456         kfree(parity_event[2]);
 457         kfree(parity_event[1]);
 458 }
 459
 460 static void ivybridge_handle_parity_error(struct drm_device *dev)
 461 {
 462         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 463         unsigned long flags;
 464
 465         if (!HAS_L3_GPU_CACHE(dev))
 466                 return;
 467
 468         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 469         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 470         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 471         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 472
 473         queue_work(dev_priv->wq, &dev_priv->parity_error_work);
 474 }
 475
 476 static void snb_gt_irq_handler(struct drm_device *dev,
 477                                struct drm_i915_private *dev_priv,
 478                                u32 gt_iir)
 479 {
 480
 481         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 482                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 483                 notify_ring(dev, &dev_priv->ring[RCS]);
 484         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 485                 notify_ring(dev, &dev_priv->ring[VCS]);
 486         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 487                 notify_ring(dev, &dev_priv->ring[BCS]);
 488
 489         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 490                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 491                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 492                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 493                 i915_handle_error(dev, false);
 494         }
 495
 496         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 497                 ivybridge_handle_parity_error(dev);
 498 }
 499
 500 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 501                                 u32 pm_iir)
 502 {
 503         unsigned long flags;
 504
 505         /*
 506          * IIR bits should never already be set because IMR should
 507          * prevent an interrupt from being shown in IIR. The warning
 508          * displays a case where we've unsafely cleared
 509          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 510          * type is not a problem, it displays a problem in the logic.
 511          *
 512          * The mask bit in IMR is cleared by dev_priv->rps.work.
 513          */
 514
 515         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 516         dev_priv->rps.pm_iir |= pm_iir;
 517         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 518         POSTING_READ(GEN6_PMIMR);
 519         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 520
 521         queue_work(dev_priv->wq, &dev_priv->rps.work);
 522 }
 523
 524 static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
 525 {
 526         struct drm_device *dev = (struct drm_device *) arg;
 527         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 528         u32 iir, gt_iir, pm_iir;
 529         irqreturn_t ret = IRQ_NONE;
 530         unsigned long irqflags;
 531         int pipe;
 532         u32 pipe_stats[I915_MAX_PIPES];
 533         bool blc_event;
 534
 535         atomic_inc(&dev_priv->irq_received);
 536
 537         while (true) {
 538                 iir = I915_READ(VLV_IIR);
 539                 gt_iir = I915_READ(GTIIR);
 540                 pm_iir = I915_READ(GEN6_PMIIR);
 541
 542                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 543                         goto out;
 544
 545                 ret = IRQ_HANDLED;
 546
 547                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 548
 549                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 550                 for_each_pipe(pipe) {
 551                         int reg = PIPESTAT(pipe);
 552                         pipe_stats[pipe] = I915_READ(reg);
 553
 554                         /*
 555                          * Clear the PIPE*STAT regs before the IIR
 556                          */
 557                         if (pipe_stats[pipe] & 0x8000ffff) {
 558                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 559                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 560                                                          pipe_name(pipe));
 561                                 I915_WRITE(reg, pipe_stats[pipe]);
 562                         }
 563                 }
 564                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 565
 566                 for_each_pipe(pipe) {
 567                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 568                                 drm_handle_vblank(dev, pipe);
 569
 570                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 571                                 intel_prepare_page_flip(dev, pipe);
 572                                 intel_finish_page_flip(dev, pipe);
 573                         }
 574                 }
 575
 576                 /* Consume port.  Then clear IIR or we'll miss events */
 577                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 578                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 579
 580                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 581                                          hotplug_status);
 582                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 583                                 queue_work(dev_priv->wq,
 584                                            &dev_priv->hotplug_work);
 585
 586                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 587                         I915_READ(PORT_HOTPLUG_STAT);
 588                 }
 589
 590                 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
 591                         blc_event = true;
 592
 593                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 594                         gen6_queue_rps_work(dev_priv, pm_iir);
 595
 596                 I915_WRITE(GTIIR, gt_iir);
 597                 I915_WRITE(GEN6_PMIIR, pm_iir);
 598                 I915_WRITE(VLV_IIR, iir);
 599         }
 600
 601 out:
 602         return ret;
 603 }
 604
 605 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 606 {
 607         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 608         int pipe;
 609
 610         if (pch_iir & SDE_AUDIO_POWER_MASK)
 611                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 612                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 613                                  SDE_AUDIO_POWER_SHIFT);
 614
 615         if (pch_iir & SDE_GMBUS)
 616                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 617
 618         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 619                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 620
 621         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 622                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 623
 624         if (pch_iir & SDE_POISON)
 625                 DRM_ERROR("PCH poison interrupt\n");
 626
 627         if (pch_iir & SDE_FDI_MASK)
 628                 for_each_pipe(pipe)
 629                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 630                                          pipe_name(pipe),
 631                                          I915_READ(FDI_RX_IIR(pipe)));
 632
 633         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 634                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 635
 636         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 637                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 638
 639         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 640                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 641         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 642                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 643 }
 644
 645 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 646 {
 647         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 648         int pipe;
 649
 650         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 651                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 652                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 653                                  SDE_AUDIO_POWER_SHIFT_CPT);
 654
 655         if (pch_iir & SDE_AUX_MASK_CPT)
 656                 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
 657
 658         if (pch_iir & SDE_GMBUS_CPT)
 659                 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
 660
 661         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 662                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 663
 664         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 665                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 666
 667         if (pch_iir & SDE_FDI_MASK_CPT)
 668                 for_each_pipe(pipe)
 669                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 670                                          pipe_name(pipe),
 671                                          I915_READ(FDI_RX_IIR(pipe)));
 672 }
 673
 674 static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
 675 {
 676         struct drm_device *dev = (struct drm_device *) arg;
 677         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 678         u32 de_iir, gt_iir, de_ier, pm_iir;
 679         irqreturn_t ret = IRQ_NONE;
 680         int i;
 681
 682         atomic_inc(&dev_priv->irq_received);
 683
 684         /* disable master interrupt before clearing iir  */
 685         de_ier = I915_READ(DEIER);
 686         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 687
 688         gt_iir = I915_READ(GTIIR);
 689         if (gt_iir) {
 690                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 691                 I915_WRITE(GTIIR, gt_iir);
 692                 ret = IRQ_HANDLED;
 693         }
 694
 695         de_iir = I915_READ(DEIIR);
 696         if (de_iir) {
 697                 if (de_iir & DE_GSE_IVB)
 698                         intel_opregion_gse_intr(dev);
 699
 700                 for (i = 0; i < 3; i++) {
 701                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 702                                 intel_prepare_page_flip(dev, i);
 703                                 intel_finish_page_flip_plane(dev, i);
 704                         }
 705                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 706                                 drm_handle_vblank(dev, i);
 707                 }
 708
 709                 /* check event from PCH */
 710                 if (de_iir & DE_PCH_EVENT_IVB) {
 711                         u32 pch_iir = I915_READ(SDEIIR);
 712
 713                         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 714                                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 715                         cpt_irq_handler(dev, pch_iir);
 716
 717                         /* clear PCH hotplug event before clear CPU irq */
 718                         I915_WRITE(SDEIIR, pch_iir);
 719                 }
 720
 721                 I915_WRITE(DEIIR, de_iir);
 722                 ret = IRQ_HANDLED;
 723         }
 724
 725         pm_iir = I915_READ(GEN6_PMIIR);
 726         if (pm_iir) {
 727                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 728                         gen6_queue_rps_work(dev_priv, pm_iir);
 729                 I915_WRITE(GEN6_PMIIR, pm_iir);
 730                 ret = IRQ_HANDLED;
 731         }
 732
 733         I915_WRITE(DEIER, de_ier);
 734         POSTING_READ(DEIER);
 735
 736         return ret;
 737 }
 738
 739 static void ilk_gt_irq_handler(struct drm_device *dev,
 740                                struct drm_i915_private *dev_priv,
 741                                u32 gt_iir)
 742 {
 743         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 744                 notify_ring(dev, &dev_priv->ring[RCS]);
 745         if (gt_iir & GT_BSD_USER_INTERRUPT)
 746                 notify_ring(dev, &dev_priv->ring[VCS]);
 747 }
 748
 749 static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
 750 {
 751         struct drm_device *dev = (struct drm_device *) arg;
 752         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 753         int ret = IRQ_NONE;
 754         u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
 755         u32 hotplug_mask;
 756
 757         atomic_inc(&dev_priv->irq_received);
 758
 759         /* disable master interrupt before clearing iir  */
 760         de_ier = I915_READ(DEIER);
 761         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 762         POSTING_READ(DEIER);
 763
 764         de_iir = I915_READ(DEIIR);
 765         gt_iir = I915_READ(GTIIR);
 766         pch_iir = I915_READ(SDEIIR);
 767         pm_iir = I915_READ(GEN6_PMIIR);
 768
 769         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
 770             (!IS_GEN6(dev) || pm_iir == 0))
 771                 goto done;
 772
 773         if (HAS_PCH_CPT(dev))
 774                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 775         else
 776                 hotplug_mask = SDE_HOTPLUG_MASK;
 777
 778         ret = IRQ_HANDLED;
 779
 780         if (IS_GEN5(dev))
 781                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 782         else
 783                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 784
 785         if (de_iir & DE_GSE)
 786                 intel_opregion_gse_intr(dev);
 787
 788         if (de_iir & DE_PLANEA_FLIP_DONE) {
 789                 intel_prepare_page_flip(dev, 0);
 790                 intel_finish_page_flip_plane(dev, 0);
 791         }
 792
 793         if (de_iir & DE_PLANEB_FLIP_DONE) {
 794                 intel_prepare_page_flip(dev, 1);
 795                 intel_finish_page_flip_plane(dev, 1);
 796         }
 797
 798         if (de_iir & DE_PIPEA_VBLANK)
 799                 drm_handle_vblank(dev, 0);
 800
 801         if (de_iir & DE_PIPEB_VBLANK)
 802                 drm_handle_vblank(dev, 1);
 803
 804         /* check event from PCH */
 805         if (de_iir & DE_PCH_EVENT) {
 806                 if (pch_iir & hotplug_mask)
 807                         queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 808                 if (HAS_PCH_CPT(dev))
 809                         cpt_irq_handler(dev, pch_iir);
 810                 else
 811                         ibx_irq_handler(dev, pch_iir);
 812         }
 813
 814         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 815                 ironlake_handle_rps_change(dev);
 816
 817         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 818                 gen6_queue_rps_work(dev_priv, pm_iir);
 819
 820         /* should clear PCH hotplug event before clear CPU irq */
 821         I915_WRITE(SDEIIR, pch_iir);
 822         I915_WRITE(GTIIR, gt_iir);
 823         I915_WRITE(DEIIR, de_iir);
 824         I915_WRITE(GEN6_PMIIR, pm_iir);
 825
 826 done:
 827         I915_WRITE(DEIER, de_ier);
 828         POSTING_READ(DEIER);
 829
 830         return ret;
 831 }
 832
 833 /**
 834  * i915_error_work_func - do process context error handling work
 835  * @work: work struct
 836  *
 837  * Fire an error uevent so userspace can see that a hang or error
 838  * was detected.
 839  */
 840 static void i915_error_work_func(struct work_struct *work)
 841 {
 842         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 843                                                     error_work);
 844         struct drm_device *dev = dev_priv->dev;
 845         char *error_event[] = { "ERROR=1", NULL };
 846         char *reset_event[] = { "RESET=1", NULL };
 847         char *reset_done_event[] = { "ERROR=0", NULL };
 848
 849         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 850
 851         if (atomic_read(&dev_priv->mm.wedged)) {
 852                 DRM_DEBUG_DRIVER("resetting chip\n");
 853                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 854                 if (!i915_reset(dev)) {
 855                         atomic_set(&dev_priv->mm.wedged, 0);
 856                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 857                 }
 858                 complete_all(&dev_priv->error_completion);
 859         }
 860 }
 861
 862 /* NB: please notice the memset */
 863 static void i915_get_extra_instdone(struct drm_device *dev,
 864                                     uint32_t *instdone)
 865 {
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 868
 869         switch(INTEL_INFO(dev)->gen) {
 870         case 2:
 871         case 3:
 872                 instdone[0] = I915_READ(INSTDONE);
 873                 break;
 874         case 4:
 875         case 5:
 876         case 6:
 877                 instdone[0] = I915_READ(INSTDONE_I965);
 878                 instdone[1] = I915_READ(INSTDONE1);
 879                 break;
 880         default:
 881                 WARN_ONCE(1, "Unsupported platform\n");
 882         case 7:
 883                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
 884                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 885                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 886                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 887                 break;
 888         }
 889 }
 890
 891 #ifdef CONFIG_DEBUG_FS
 892 static struct drm_i915_error_object *
 893 i915_error_object_create(struct drm_i915_private *dev_priv,
 894                          struct drm_i915_gem_object *src)
 895 {
 896         struct drm_i915_error_object *dst;
 897         int i, count;
 898         u32 reloc_offset;
 899
 900         if (src == NULL || src->pages == NULL)
 901                 return NULL;
 902
 903         count = src->base.size / PAGE_SIZE;
 904
 905         dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
 906         if (dst == NULL)
 907                 return NULL;
 908
 909         reloc_offset = src->gtt_offset;
 910         for (i = 0; i < count; i++) {
 911                 unsigned long flags;
 912                 void *d;
 913
 914                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 915                 if (d == NULL)
 916                         goto unwind;
 917
 918                 local_irq_save(flags);
 919                 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
 920                     src->has_global_gtt_mapping) {
 921                         void __iomem *s;
 922
 923                         /* Simply ignore tiling or any overlapping fence.
 924                          * It's part of the error state, and this hopefully
 925                          * captures what the GPU read.
 926                          */
 927
 928                         s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 929                                                      reloc_offset);
 930                         memcpy_fromio(d, s, PAGE_SIZE);
 931                         io_mapping_unmap_atomic(s);
 932                 } else {
 933                         struct page *page;
 934                         void *s;
 935
 936                         page = i915_gem_object_get_page(src, i);
 937
 938                         drm_clflush_pages(&page, 1);
 939
 940                         s = kmap_atomic(page);
 941                         memcpy(d, s, PAGE_SIZE);
 942                         kunmap_atomic(s);
 943
 944                         drm_clflush_pages(&page, 1);
 945                 }
 946                 local_irq_restore(flags);
 947
 948                 dst->pages[i] = d;
 949
 950                 reloc_offset += PAGE_SIZE;
 951         }
 952         dst->page_count = count;
 953         dst->gtt_offset = src->gtt_offset;
 954
 955         return dst;
 956
 957 unwind:
 958         while (i--)
 959                 kfree(dst->pages[i]);
 960         kfree(dst);
 961         return NULL;
 962 }
 963
 964 static void
 965 i915_error_object_free(struct drm_i915_error_object *obj)
 966 {
 967         int page;
 968
 969         if (obj == NULL)
 970                 return;
 971
 972         for (page = 0; page < obj->page_count; page++)
 973                 kfree(obj->pages[page]);
 974
 975         kfree(obj);
 976 }
 977
 978 void
 979 i915_error_state_free(struct kref *error_ref)
 980 {
 981         struct drm_i915_error_state *error = container_of(error_ref,
 982                                                           typeof(*error), ref);
 983         int i;
 984
 985         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 986                 i915_error_object_free(error->ring[i].batchbuffer);
 987                 i915_error_object_free(error->ring[i].ringbuffer);
 988                 kfree(error->ring[i].requests);
 989         }
 990
 991         kfree(error->active_bo);
 992         kfree(error->overlay);
 993         kfree(error);
 994 }
 995 static void capture_bo(struct drm_i915_error_buffer *err,
 996                        struct drm_i915_gem_object *obj)
 997 {
 998         err->size = obj->base.size;
 999         err->name = obj->base.name;
1000         err->rseqno = obj->last_read_seqno;
1001         err->wseqno = obj->last_write_seqno;
1002         err->gtt_offset = obj->gtt_offset;
1003         err->read_domains = obj->base.read_domains;
1004         err->write_domain = obj->base.write_domain;
1005         err->fence_reg = obj->fence_reg;
1006         err->pinned = 0;
1007         if (obj->pin_count > 0)
1008                 err->pinned = 1;
1009         if (obj->user_pin_count > 0)
1010                 err->pinned = -1;
1011         err->tiling = obj->tiling_mode;
1012         err->dirty = obj->dirty;
1013         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1014         err->ring = obj->ring ? obj->ring->id : -1;
1015         err->cache_level = obj->cache_level;
1016 }
1017
1018 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1019                              int count, struct list_head *head)
1020 {
1021         struct drm_i915_gem_object *obj;
1022         int i = 0;
1023
1024         list_for_each_entry(obj, head, mm_list) {
1025                 capture_bo(err++, obj);
1026                 if (++i == count)
1027                         break;
1028         }
1029
1030         return i;
1031 }
1032
1033 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1034                              int count, struct list_head *head)
1035 {
1036         struct drm_i915_gem_object *obj;
1037         int i = 0;
1038
1039         list_for_each_entry(obj, head, gtt_list) {
1040                 if (obj->pin_count == 0)
1041                         continue;
1042
1043                 capture_bo(err++, obj);
1044                 if (++i == count)
1045                         break;
1046         }
1047
1048         return i;
1049 }
1050
1051 static void i915_gem_record_fences(struct drm_device *dev,
1052                                    struct drm_i915_error_state *error)
1053 {
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         int i;
1056
1057         /* Fences */
1058         switch (INTEL_INFO(dev)->gen) {
1059         case 7:
1060         case 6:
1061                 for (i = 0; i < 16; i++)
1062                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1063                 break;
1064         case 5:
1065         case 4:
1066                 for (i = 0; i < 16; i++)
1067                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1068                 break;
1069         case 3:
1070                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1071                         for (i = 0; i < 8; i++)
1072                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1073         case 2:
1074                 for (i = 0; i < 8; i++)
1075                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1076                 break;
1077
1078         }
1079 }
1080
1081 static struct drm_i915_error_object *
1082 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1083                              struct intel_ring_buffer *ring)
1084 {
1085         struct drm_i915_gem_object *obj;
1086         u32 seqno;
1087
1088         if (!ring->get_seqno)
1089                 return NULL;
1090
1091         seqno = ring->get_seqno(ring, false);
1092         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1093                 if (obj->ring != ring)
1094                         continue;
1095
1096                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1097                         continue;
1098
1099                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1100                         continue;
1101
1102                 /* We need to copy these to an anonymous buffer as the simplest
1103                  * method to avoid being overwritten by userspace.
1104                  */
1105                 return i915_error_object_create(dev_priv, obj);
1106         }
1107
1108         return NULL;
1109 }
1110
1111 static void i915_record_ring_state(struct drm_device *dev,
1112                                    struct drm_i915_error_state *error,
1113                                    struct intel_ring_buffer *ring)
1114 {
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116
1117         if (INTEL_INFO(dev)->gen >= 6) {
1118                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1119                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1120                 error->semaphore_mboxes[ring->id][0]
1121                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1122                 error->semaphore_mboxes[ring->id][1]
1123                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1124         }
1125
1126         if (INTEL_INFO(dev)->gen >= 4) {
1127                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1128                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1129                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1130                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1131                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1132                 if (ring->id == RCS)
1133                         error->bbaddr = I915_READ64(BB_ADDR);
1134         } else {
1135                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1136                 error->ipeir[ring->id] = I915_READ(IPEIR);
1137                 error->ipehr[ring->id] = I915_READ(IPEHR);
1138                 error->instdone[ring->id] = I915_READ(INSTDONE);
1139         }
1140
1141         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1142         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1143         error->seqno[ring->id] = ring->get_seqno(ring, false);
1144         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1145         error->head[ring->id] = I915_READ_HEAD(ring);
1146         error->tail[ring->id] = I915_READ_TAIL(ring);
1147
1148         error->cpu_ring_head[ring->id] = ring->head;
1149         error->cpu_ring_tail[ring->id] = ring->tail;
1150 }
1151
1152 static void i915_gem_record_rings(struct drm_device *dev,
1153                                   struct drm_i915_error_state *error)
1154 {
1155         struct drm_i915_private *dev_priv = dev->dev_private;
1156         struct intel_ring_buffer *ring;
1157         struct drm_i915_gem_request *request;
1158         int i, count;
1159
1160         for_each_ring(ring, dev_priv, i) {
1161                 i915_record_ring_state(dev, error, ring);
1162
1163                 error->ring[i].batchbuffer =
1164                         i915_error_first_batchbuffer(dev_priv, ring);
1165
1166                 error->ring[i].ringbuffer =
1167                         i915_error_object_create(dev_priv, ring->obj);
1168
1169                 count = 0;
1170                 list_for_each_entry(request, &ring->request_list, list)
1171                         count++;
1172
1173                 error->ring[i].num_requests = count;
1174                 error->ring[i].requests =
1175                         kmalloc(count*sizeof(struct drm_i915_error_request),
1176                                 GFP_ATOMIC);
1177                 if (error->ring[i].requests == NULL) {
1178                         error->ring[i].num_requests = 0;
1179                         continue;
1180                 }
1181
1182                 count = 0;
1183                 list_for_each_entry(request, &ring->request_list, list) {
1184                         struct drm_i915_error_request *erq;
1185
1186                         erq = &error->ring[i].requests[count++];
1187                         erq->seqno = request->seqno;
1188                         erq->jiffies = request->emitted_jiffies;
1189                         erq->tail = request->tail;
1190                 }
1191         }
1192 }
1193
1194 /**
1195  * i915_capture_error_state - capture an error record for later analysis
1196  * @dev: drm device
1197  *
1198  * Should be called when an error is detected (either a hang or an error
1199  * interrupt) to capture error state from the time of the error.  Fills
1200  * out a structure which becomes available in debugfs for user level tools
1201  * to pick up.
1202  */
1203 static void i915_capture_error_state(struct drm_device *dev)
1204 {
1205         struct drm_i915_private *dev_priv = dev->dev_private;
1206         struct drm_i915_gem_object *obj;
1207         struct drm_i915_error_state *error;
1208         unsigned long flags;
1209         int i, pipe;
1210
1211         spin_lock_irqsave(&dev_priv->error_lock, flags);
1212         error = dev_priv->first_error;
1213         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1214         if (error)
1215                 return;
1216
1217         /* Account for pipe specific data like PIPE*STAT */
1218         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1219         if (!error) {
1220                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1221                 return;
1222         }
1223
1224         DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1225                  dev->primary->index);
1226
1227         kref_init(&error->ref);
1228         error->eir = I915_READ(EIR);
1229         error->pgtbl_er = I915_READ(PGTBL_ER);
1230         error->ccid = I915_READ(CCID);
1231
1232         if (HAS_PCH_SPLIT(dev))
1233                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1234         else if (IS_VALLEYVIEW(dev))
1235                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1236         else if (IS_GEN2(dev))
1237                 error->ier = I915_READ16(IER);
1238         else
1239                 error->ier = I915_READ(IER);
1240
1241         for_each_pipe(pipe)
1242                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1243
1244         if (INTEL_INFO(dev)->gen >= 6) {
1245                 error->error = I915_READ(ERROR_GEN6);
1246                 error->done_reg = I915_READ(DONE_REG);
1247         }
1248
1249         if (INTEL_INFO(dev)->gen == 7)
1250                 error->err_int = I915_READ(GEN7_ERR_INT);
1251
1252         i915_get_extra_instdone(dev, error->extra_instdone);
1253
1254         i915_gem_record_fences(dev, error);
1255         i915_gem_record_rings(dev, error);
1256
1257         /* Record buffers on the active and pinned lists. */
1258         error->active_bo = NULL;
1259         error->pinned_bo = NULL;
1260
1261         i = 0;
1262         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1263                 i++;
1264         error->active_bo_count = i;
1265         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1266                 if (obj->pin_count)
1267                         i++;
1268         error->pinned_bo_count = i - error->active_bo_count;
1269
1270         error->active_bo = NULL;
1271         error->pinned_bo = NULL;
1272         if (i) {
1273                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1274                                            GFP_ATOMIC);
1275                 if (error->active_bo)
1276                         error->pinned_bo =
1277                                 error->active_bo + error->active_bo_count;
1278         }
1279
1280         if (error->active_bo)
1281                 error->active_bo_count =
1282                         capture_active_bo(error->active_bo,
1283                                           error->active_bo_count,
1284                                           &dev_priv->mm.active_list);
1285
1286         if (error->pinned_bo)
1287                 error->pinned_bo_count =
1288                         capture_pinned_bo(error->pinned_bo,
1289                                           error->pinned_bo_count,
1290                                           &dev_priv->mm.bound_list);
1291
1292         do_gettimeofday(&error->time);
1293
1294         error->overlay = intel_overlay_capture_error_state(dev);
1295         error->display = intel_display_capture_error_state(dev);
1296
1297         spin_lock_irqsave(&dev_priv->error_lock, flags);
1298         if (dev_priv->first_error == NULL) {
1299                 dev_priv->first_error = error;
1300                 error = NULL;
1301         }
1302         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1303
1304         if (error)
1305                 i915_error_state_free(&error->ref);
1306 }
1307
1308 void i915_destroy_error_state(struct drm_device *dev)
1309 {
1310         struct drm_i915_private *dev_priv = dev->dev_private;
1311         struct drm_i915_error_state *error;
1312         unsigned long flags;
1313
1314         spin_lock_irqsave(&dev_priv->error_lock, flags);
1315         error = dev_priv->first_error;
1316         dev_priv->first_error = NULL;
1317         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1318
1319         if (error)
1320                 kref_put(&error->ref, i915_error_state_free);
1321 }
1322 #else
1323 #define i915_capture_error_state(x)
1324 #endif
1325
1326 static void i915_report_and_clear_eir(struct drm_device *dev)
1327 {
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         uint32_t instdone[I915_NUM_INSTDONE_REG];
1330         u32 eir = I915_READ(EIR);
1331         int pipe, i;
1332
1333         if (!eir)
1334                 return;
1335
1336         pr_err("render error detected, EIR: 0x%08x\n", eir);
1337
1338         i915_get_extra_instdone(dev, instdone);
1339
1340         if (IS_G4X(dev)) {
1341                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1342                         u32 ipeir = I915_READ(IPEIR_I965);
1343
1344                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1345                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1346                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1347                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1348                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1349                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1350                         I915_WRITE(IPEIR_I965, ipeir);
1351                         POSTING_READ(IPEIR_I965);
1352                 }
1353                 if (eir & GM45_ERROR_PAGE_TABLE) {
1354                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1355                         pr_err("page table error\n");
1356                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1357                         I915_WRITE(PGTBL_ER, pgtbl_err);
1358                         POSTING_READ(PGTBL_ER);
1359                 }
1360         }
1361
1362         if (!IS_GEN2(dev)) {
1363                 if (eir & I915_ERROR_PAGE_TABLE) {
1364                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1365                         pr_err("page table error\n");
1366                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1367                         I915_WRITE(PGTBL_ER, pgtbl_err);
1368                         POSTING_READ(PGTBL_ER);
1369                 }
1370         }
1371
1372         if (eir & I915_ERROR_MEMORY_REFRESH) {
1373                 pr_err("memory refresh error:\n");
1374                 for_each_pipe(pipe)
1375                         pr_err("pipe %c stat: 0x%08x\n",
1376                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1377                 /* pipestat has already been acked */
1378         }
1379         if (eir & I915_ERROR_INSTRUCTION) {
1380                 pr_err("instruction error\n");
1381                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1382                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1383                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1384                 if (INTEL_INFO(dev)->gen < 4) {
1385                         u32 ipeir = I915_READ(IPEIR);
1386
1387                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1388                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1389                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1390                         I915_WRITE(IPEIR, ipeir);
1391                         POSTING_READ(IPEIR);
1392                 } else {
1393                         u32 ipeir = I915_READ(IPEIR_I965);
1394
1395                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1396                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1397                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1398                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1399                         I915_WRITE(IPEIR_I965, ipeir);
1400                         POSTING_READ(IPEIR_I965);
1401                 }
1402         }
1403
1404         I915_WRITE(EIR, eir);
1405         POSTING_READ(EIR);
1406         eir = I915_READ(EIR);
1407         if (eir) {
1408                 /*
1409                  * some errors might have become stuck,
1410                  * mask them.
1411                  */
1412                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1413                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1414                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1415         }
1416 }
1417
1418 /**
1419  * i915_handle_error - handle an error interrupt
1420  * @dev: drm device
1421  *
1422  * Do some basic checking of regsiter state at error interrupt time and
1423  * dump it to the syslog.  Also call i915_capture_error_state() to make
1424  * sure we get a record and make it available in debugfs.  Fire a uevent
1425  * so userspace knows something bad happened (should trigger collection
1426  * of a ring dump etc.).
1427  */
1428 void i915_handle_error(struct drm_device *dev, bool wedged)
1429 {
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         struct intel_ring_buffer *ring;
1432         int i;
1433
1434         i915_capture_error_state(dev);
1435         i915_report_and_clear_eir(dev);
1436
1437         if (wedged) {
1438                 INIT_COMPLETION(dev_priv->error_completion);
1439                 atomic_set(&dev_priv->mm.wedged, 1);
1440
1441                 /*
1442                  * Wakeup waiting processes so they don't hang
1443                  */
1444                 for_each_ring(ring, dev_priv, i)
1445                         wake_up_all(&ring->irq_queue);
1446         }
1447
1448         queue_work(dev_priv->wq, &dev_priv->error_work);
1449 }
1450
1451 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1452 {
1453         drm_i915_private_t *dev_priv = dev->dev_private;
1454         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1456         struct drm_i915_gem_object *obj;
1457         struct intel_unpin_work *work;
1458         unsigned long flags;
1459         bool stall_detected;
1460
1461         /* Ignore early vblank irqs */
1462         if (intel_crtc == NULL)
1463                 return;
1464
1465         spin_lock_irqsave(&dev->event_lock, flags);
1466         work = intel_crtc->unpin_work;
1467
1468         if (work == NULL || work->pending || !work->enable_stall_check) {
1469                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1470                 spin_unlock_irqrestore(&dev->event_lock, flags);
1471                 return;
1472         }
1473
1474         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1475         obj = work->pending_flip_obj;
1476         if (INTEL_INFO(dev)->gen >= 4) {
1477                 int dspsurf = DSPSURF(intel_crtc->plane);
1478                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1479                                         obj->gtt_offset;
1480         } else {
1481                 int dspaddr = DSPADDR(intel_crtc->plane);
1482                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1483                                                         crtc->y * crtc->fb->pitches[0] +
1484                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1485         }
1486
1487         spin_unlock_irqrestore(&dev->event_lock, flags);
1488
1489         if (stall_detected) {
1490                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1491                 intel_prepare_page_flip(dev, intel_crtc->plane);
1492         }
1493 }
1494
1495 /* Called from drm generic code, passed 'crtc' which
1496  * we use as a pipe index
1497  */
1498 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1499 {
1500         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1501         unsigned long irqflags;
1502
1503         if (!i915_pipe_enabled(dev, pipe))
1504                 return -EINVAL;
1505
1506         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1507         if (INTEL_INFO(dev)->gen >= 4)
1508                 i915_enable_pipestat(dev_priv, pipe,
1509                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1510         else
1511                 i915_enable_pipestat(dev_priv, pipe,
1512                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1513
1514         /* maintain vblank delivery even in deep C-states */
1515         if (dev_priv->info->gen == 3)
1516                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1517         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1518
1519         return 0;
1520 }
1521
1522 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1523 {
1524         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1525         unsigned long irqflags;
1526
1527         if (!i915_pipe_enabled(dev, pipe))
1528                 return -EINVAL;
1529
1530         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1531         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1532                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1533         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1534
1535         return 0;
1536 }
1537
1538 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1539 {
1540         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1541         unsigned long irqflags;
1542
1543         if (!i915_pipe_enabled(dev, pipe))
1544                 return -EINVAL;
1545
1546         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1547         ironlake_enable_display_irq(dev_priv,
1548                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1549         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1550
1551         return 0;
1552 }
1553
1554 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1555 {
1556         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1557         unsigned long irqflags;
1558         u32 imr;
1559
1560         if (!i915_pipe_enabled(dev, pipe))
1561                 return -EINVAL;
1562
1563         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1564         imr = I915_READ(VLV_IMR);
1565         if (pipe == 0)
1566                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1567         else
1568                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1569         I915_WRITE(VLV_IMR, imr);
1570         i915_enable_pipestat(dev_priv, pipe,
1571                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1572         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1573
1574         return 0;
1575 }
1576
1577 /* Called from drm generic code, passed 'crtc' which
1578  * we use as a pipe index
1579  */
1580 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1581 {
1582         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1583         unsigned long irqflags;
1584
1585         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1586         if (dev_priv->info->gen == 3)
1587                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1588
1589         i915_disable_pipestat(dev_priv, pipe,
1590                               PIPE_VBLANK_INTERRUPT_ENABLE |
1591                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1592         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1593 }
1594
1595 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1596 {
1597         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1598         unsigned long irqflags;
1599
1600         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1601         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1602                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1603         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1604 }
1605
1606 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1607 {
1608         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1609         unsigned long irqflags;
1610
1611         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1612         ironlake_disable_display_irq(dev_priv,
1613                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1614         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1615 }
1616
1617 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1618 {
1619         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1620         unsigned long irqflags;
1621         u32 imr;
1622
1623         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1624         i915_disable_pipestat(dev_priv, pipe,
1625                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1626         imr = I915_READ(VLV_IMR);
1627         if (pipe == 0)
1628                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1629         else
1630                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1631         I915_WRITE(VLV_IMR, imr);
1632         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1633 }
1634
1635 static u32
1636 ring_last_seqno(struct intel_ring_buffer *ring)
1637 {
1638         return list_entry(ring->request_list.prev,
1639                           struct drm_i915_gem_request, list)->seqno;
1640 }
1641
1642 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1643 {
1644         if (list_empty(&ring->request_list) ||
1645             i915_seqno_passed(ring->get_seqno(ring, false),
1646                               ring_last_seqno(ring))) {
1647                 /* Issue a wake-up to catch stuck h/w. */
1648                 if (waitqueue_active(&ring->irq_queue)) {
1649                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1650                                   ring->name);
1651                         wake_up_all(&ring->irq_queue);
1652                         *err = true;
1653                 }
1654                 return true;
1655         }
1656         return false;
1657 }
1658
1659 static bool kick_ring(struct intel_ring_buffer *ring)
1660 {
1661         struct drm_device *dev = ring->dev;
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663         u32 tmp = I915_READ_CTL(ring);
1664         if (tmp & RING_WAIT) {
1665                 DRM_ERROR("Kicking stuck wait on %s\n",
1666                           ring->name);
1667                 I915_WRITE_CTL(ring, tmp);
1668                 return true;
1669         }
1670         return false;
1671 }
1672
1673 static bool i915_hangcheck_hung(struct drm_device *dev)
1674 {
1675         drm_i915_private_t *dev_priv = dev->dev_private;
1676
1677         if (dev_priv->hangcheck_count++ > 1) {
1678                 bool hung = true;
1679
1680                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1681                 i915_handle_error(dev, true);
1682
1683                 if (!IS_GEN2(dev)) {
1684                         struct intel_ring_buffer *ring;
1685                         int i;
1686
1687                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1688                          * If so we can simply poke the RB_WAIT bit
1689                          * and break the hang. This should work on
1690                          * all but the second generation chipsets.
1691                          */
1692                         for_each_ring(ring, dev_priv, i)
1693                                 hung &= !kick_ring(ring);
1694                 }
1695
1696                 return hung;
1697         }
1698
1699         return false;
1700 }
1701
1702 /**
1703  * This is called when the chip hasn't reported back with completed
1704  * batchbuffers in a long time. The first time this is called we simply record
1705  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1706  * again, we assume the chip is wedged and try to fix it.
1707  */
1708 void i915_hangcheck_elapsed(unsigned long data)
1709 {
1710         struct drm_device *dev = (struct drm_device *)data;
1711         drm_i915_private_t *dev_priv = dev->dev_private;
1712         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1713         struct intel_ring_buffer *ring;
1714         bool err = false, idle;
1715         int i;
1716
1717         if (!i915_enable_hangcheck)
1718                 return;
1719
1720         memset(acthd, 0, sizeof(acthd));
1721         idle = true;
1722         for_each_ring(ring, dev_priv, i) {
1723             idle &= i915_hangcheck_ring_idle(ring, &err);
1724             acthd[i] = intel_ring_get_active_head(ring);
1725         }
1726
1727         /* If all work is done then ACTHD clearly hasn't advanced. */
1728         if (idle) {
1729                 if (err) {
1730                         if (i915_hangcheck_hung(dev))
1731                                 return;
1732
1733                         goto repeat;
1734                 }
1735
1736                 dev_priv->hangcheck_count = 0;
1737                 return;
1738         }
1739
1740         i915_get_extra_instdone(dev, instdone);
1741         if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1742             memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
1743                 if (i915_hangcheck_hung(dev))
1744                         return;
1745         } else {
1746                 dev_priv->hangcheck_count = 0;
1747
1748                 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1749                 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
1750         }
1751
1752 repeat:
1753         /* Reset timer case chip hangs without another request being added */
1754         mod_timer(&dev_priv->hangcheck_timer,
1755                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1756 }
1757
1758 /* drm_dma.h hooks
1759 */
1760 static void ironlake_irq_preinstall(struct drm_device *dev)
1761 {
1762         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1763
1764         atomic_set(&dev_priv->irq_received, 0);
1765
1766         I915_WRITE(HWSTAM, 0xeffe);
1767
1768         /* XXX hotplug from PCH */
1769
1770         I915_WRITE(DEIMR, 0xffffffff);
1771         I915_WRITE(DEIER, 0x0);
1772         POSTING_READ(DEIER);
1773
1774         /* and GT */
1775         I915_WRITE(GTIMR, 0xffffffff);
1776         I915_WRITE(GTIER, 0x0);
1777         POSTING_READ(GTIER);
1778
1779         /* south display irq */
1780         I915_WRITE(SDEIMR, 0xffffffff);
1781         I915_WRITE(SDEIER, 0x0);
1782         POSTING_READ(SDEIER);
1783 }
1784
1785 static void valleyview_irq_preinstall(struct drm_device *dev)
1786 {
1787         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1788         int pipe;
1789
1790         atomic_set(&dev_priv->irq_received, 0);
1791
1792         /* VLV magic */
1793         I915_WRITE(VLV_IMR, 0);
1794         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1795         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1796         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1797
1798         /* and GT */
1799         I915_WRITE(GTIIR, I915_READ(GTIIR));
1800         I915_WRITE(GTIIR, I915_READ(GTIIR));
1801         I915_WRITE(GTIMR, 0xffffffff);
1802         I915_WRITE(GTIER, 0x0);
1803         POSTING_READ(GTIER);
1804
1805         I915_WRITE(DPINVGTT, 0xff);
1806
1807         I915_WRITE(PORT_HOTPLUG_EN, 0);
1808         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1809         for_each_pipe(pipe)
1810                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1811         I915_WRITE(VLV_IIR, 0xffffffff);
1812         I915_WRITE(VLV_IMR, 0xffffffff);
1813         I915_WRITE(VLV_IER, 0x0);
1814         POSTING_READ(VLV_IER);
1815 }
1816
1817 /*
1818  * Enable digital hotplug on the PCH, and configure the DP short pulse
1819  * duration to 2ms (which is the minimum in the Display Port spec)
1820  *
1821  * This register is the same on all known PCH chips.
1822  */
1823
1824 static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1825 {
1826         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1827         u32     hotplug;
1828
1829         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1830         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1831         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1832         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1833         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1834         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1835 }
1836
1837 static int ironlake_irq_postinstall(struct drm_device *dev)
1838 {
1839         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1840         /* enable kind of interrupts always enabled */
1841         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1842                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1843         u32 render_irqs;
1844         u32 hotplug_mask;
1845
1846         dev_priv->irq_mask = ~display_mask;
1847
1848         /* should always can generate irq */
1849         I915_WRITE(DEIIR, I915_READ(DEIIR));
1850         I915_WRITE(DEIMR, dev_priv->irq_mask);
1851         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1852         POSTING_READ(DEIER);
1853
1854         dev_priv->gt_irq_mask = ~0;
1855
1856         I915_WRITE(GTIIR, I915_READ(GTIIR));
1857         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1858
1859         if (IS_GEN6(dev))
1860                 render_irqs =
1861                         GT_USER_INTERRUPT |
1862                         GEN6_BSD_USER_INTERRUPT |
1863                         GEN6_BLITTER_USER_INTERRUPT;
1864         else
1865                 render_irqs =
1866                         GT_USER_INTERRUPT |
1867                         GT_PIPE_NOTIFY |
1868                         GT_BSD_USER_INTERRUPT;
1869         I915_WRITE(GTIER, render_irqs);
1870         POSTING_READ(GTIER);
1871
1872         if (HAS_PCH_CPT(dev)) {
1873                 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1874                                 SDE_PORTB_HOTPLUG_CPT |
1875                                 SDE_PORTC_HOTPLUG_CPT |
1876                                 SDE_PORTD_HOTPLUG_CPT);
1877         } else {
1878                 hotplug_mask = (SDE_CRT_HOTPLUG |
1879                                 SDE_PORTB_HOTPLUG |
1880                                 SDE_PORTC_HOTPLUG |
1881                                 SDE_PORTD_HOTPLUG |
1882                                 SDE_AUX_MASK);
1883         }
1884
1885         dev_priv->pch_irq_mask = ~hotplug_mask;
1886
1887         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1888         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1889         I915_WRITE(SDEIER, hotplug_mask);
1890         POSTING_READ(SDEIER);
1891
1892         ironlake_enable_pch_hotplug(dev);
1893
1894         if (IS_IRONLAKE_M(dev)) {
1895                 /* Clear & enable PCU event interrupts */
1896                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1897                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1898                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1899         }
1900
1901         return 0;
1902 }
1903
1904 static int ivybridge_irq_postinstall(struct drm_device *dev)
1905 {
1906         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1907         /* enable kind of interrupts always enabled */
1908         u32 display_mask =
1909                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1910                 DE_PLANEC_FLIP_DONE_IVB |
1911                 DE_PLANEB_FLIP_DONE_IVB |
1912                 DE_PLANEA_FLIP_DONE_IVB;
1913         u32 render_irqs;
1914         u32 hotplug_mask;
1915
1916         dev_priv->irq_mask = ~display_mask;
1917
1918         /* should always can generate irq */
1919         I915_WRITE(DEIIR, I915_READ(DEIIR));
1920         I915_WRITE(DEIMR, dev_priv->irq_mask);
1921         I915_WRITE(DEIER,
1922                    display_mask |
1923                    DE_PIPEC_VBLANK_IVB |
1924                    DE_PIPEB_VBLANK_IVB |
1925                    DE_PIPEA_VBLANK_IVB);
1926         POSTING_READ(DEIER);
1927
1928         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1929
1930         I915_WRITE(GTIIR, I915_READ(GTIIR));
1931         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1932
1933         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1934                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1935         I915_WRITE(GTIER, render_irqs);
1936         POSTING_READ(GTIER);
1937
1938         hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1939                         SDE_PORTB_HOTPLUG_CPT |
1940                         SDE_PORTC_HOTPLUG_CPT |
1941                         SDE_PORTD_HOTPLUG_CPT);
1942         dev_priv->pch_irq_mask = ~hotplug_mask;
1943
1944         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1945         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1946         I915_WRITE(SDEIER, hotplug_mask);
1947         POSTING_READ(SDEIER);
1948
1949         ironlake_enable_pch_hotplug(dev);
1950
1951         return 0;
1952 }
1953
1954 static int valleyview_irq_postinstall(struct drm_device *dev)
1955 {
1956         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1957         u32 enable_mask;
1958         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1959         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
1960         u16 msid;
1961
1962         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1963         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1964                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1965                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1966                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1967
1968         /*
1969          *Leave vblank interrupts masked initially.  enable/disable will
1970          * toggle them based on usage.
1971          */
1972         dev_priv->irq_mask = (~enable_mask) |
1973                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1974                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1975
1976         dev_priv->pipestat[0] = 0;
1977         dev_priv->pipestat[1] = 0;
1978
1979         /* Hack for broken MSIs on VLV */
1980         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1981         pci_read_config_word(dev->pdev, 0x98, &msid);
1982         msid &= 0xff; /* mask out delivery bits */
1983         msid |= (1<<14);
1984         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1985
1986         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1987         I915_WRITE(VLV_IER, enable_mask);
1988         I915_WRITE(VLV_IIR, 0xffffffff);
1989         I915_WRITE(PIPESTAT(0), 0xffff);
1990         I915_WRITE(PIPESTAT(1), 0xffff);
1991         POSTING_READ(VLV_IER);
1992
1993         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1994         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1995
1996         I915_WRITE(VLV_IIR, 0xffffffff);
1997         I915_WRITE(VLV_IIR, 0xffffffff);
1998
1999         dev_priv->gt_irq_mask = ~0;
2000
2001         I915_WRITE(GTIIR, I915_READ(GTIIR));
2002         I915_WRITE(GTIIR, I915_READ(GTIIR));
2003         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2004         I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
2005                    GT_GEN6_BLT_CS_ERROR_INTERRUPT |
2006                    GT_GEN6_BLT_USER_INTERRUPT |
2007                    GT_GEN6_BSD_USER_INTERRUPT |
2008                    GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2009                    GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2010                    GT_PIPE_NOTIFY |
2011                    GT_RENDER_CS_ERROR_INTERRUPT |
2012                    GT_SYNC_STATUS |
2013                    GT_USER_INTERRUPT);
2014         POSTING_READ(GTIER);
2015
2016         /* ack & enable invalid PTE error interrupts */
2017 #if 0 /* FIXME: add support to irq handler for checking these bits */
2018         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2019         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2020 #endif
2021
2022         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2023 #if 0 /* FIXME: check register definitions; some have moved */
2024         /* Note HDMI and DP share bits */
2025         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2026                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2027         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2028                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2029         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2030                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2031         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2032                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2033         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2034                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2035         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2036                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2037                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2038         }
2039 #endif
2040
2041         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2042
2043         return 0;
2044 }
2045
2046 static void valleyview_irq_uninstall(struct drm_device *dev)
2047 {
2048         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2049         int pipe;
2050
2051         if (!dev_priv)
2052                 return;
2053
2054         for_each_pipe(pipe)
2055                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2056
2057         I915_WRITE(HWSTAM, 0xffffffff);
2058         I915_WRITE(PORT_HOTPLUG_EN, 0);
2059         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2060         for_each_pipe(pipe)
2061                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2062         I915_WRITE(VLV_IIR, 0xffffffff);
2063         I915_WRITE(VLV_IMR, 0xffffffff);
2064         I915_WRITE(VLV_IER, 0x0);
2065         POSTING_READ(VLV_IER);
2066 }
2067
2068 static void ironlake_irq_uninstall(struct drm_device *dev)
2069 {
2070         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2071
2072         if (!dev_priv)
2073                 return;
2074
2075         I915_WRITE(HWSTAM, 0xffffffff);
2076
2077         I915_WRITE(DEIMR, 0xffffffff);
2078         I915_WRITE(DEIER, 0x0);
2079         I915_WRITE(DEIIR, I915_READ(DEIIR));
2080
2081         I915_WRITE(GTIMR, 0xffffffff);
2082         I915_WRITE(GTIER, 0x0);
2083         I915_WRITE(GTIIR, I915_READ(GTIIR));
2084
2085         I915_WRITE(SDEIMR, 0xffffffff);
2086         I915_WRITE(SDEIER, 0x0);
2087         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2088 }
2089
2090 static void i8xx_irq_preinstall(struct drm_device * dev)
2091 {
2092         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2093         int pipe;
2094
2095         atomic_set(&dev_priv->irq_received, 0);
2096
2097         for_each_pipe(pipe)
2098                 I915_WRITE(PIPESTAT(pipe), 0);
2099         I915_WRITE16(IMR, 0xffff);
2100         I915_WRITE16(IER, 0x0);
2101         POSTING_READ16(IER);
2102 }
2103
2104 static int i8xx_irq_postinstall(struct drm_device *dev)
2105 {
2106         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2107
2108         dev_priv->pipestat[0] = 0;
2109         dev_priv->pipestat[1] = 0;
2110
2111         I915_WRITE16(EMR,
2112                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2113
2114         /* Unmask the interrupts that we always want on. */
2115         dev_priv->irq_mask =
2116                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2117                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2118                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2119                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2120                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2121         I915_WRITE16(IMR, dev_priv->irq_mask);
2122
2123         I915_WRITE16(IER,
2124                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2125                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2126                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2127                      I915_USER_INTERRUPT);
2128         POSTING_READ16(IER);
2129
2130         return 0;
2131 }
2132
2133 static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2134 {
2135         struct drm_device *dev = (struct drm_device *) arg;
2136         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2137         u16 iir, new_iir;
2138         u32 pipe_stats[2];
2139         unsigned long irqflags;
2140         int irq_received;
2141         int pipe;
2142         u16 flip_mask =
2143                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2144                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2145
2146         atomic_inc(&dev_priv->irq_received);
2147
2148         iir = I915_READ16(IIR);
2149         if (iir == 0)
2150                 return IRQ_NONE;
2151
2152         while (iir & ~flip_mask) {
2153                 /* Can't rely on pipestat interrupt bit in iir as it might
2154                  * have been cleared after the pipestat interrupt was received.
2155                  * It doesn't set the bit in iir again, but it still produces
2156                  * interrupts (for non-MSI).
2157                  */
2158                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2159                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2160                         i915_handle_error(dev, false);
2161
2162                 for_each_pipe(pipe) {
2163                         int reg = PIPESTAT(pipe);
2164                         pipe_stats[pipe] = I915_READ(reg);
2165
2166                         /*
2167                          * Clear the PIPE*STAT regs before the IIR
2168                          */
2169                         if (pipe_stats[pipe] & 0x8000ffff) {
2170                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2171                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2172                                                          pipe_name(pipe));
2173                                 I915_WRITE(reg, pipe_stats[pipe]);
2174                                 irq_received = 1;
2175                         }
2176                 }
2177                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2178
2179                 I915_WRITE16(IIR, iir & ~flip_mask);
2180                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2181
2182                 i915_update_dri1_breadcrumb(dev);
2183
2184                 if (iir & I915_USER_INTERRUPT)
2185                         notify_ring(dev, &dev_priv->ring[RCS]);
2186
2187                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2188                     drm_handle_vblank(dev, 0)) {
2189                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2190                                 intel_prepare_page_flip(dev, 0);
2191                                 intel_finish_page_flip(dev, 0);
2192                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2193                         }
2194                 }
2195
2196                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2197                     drm_handle_vblank(dev, 1)) {
2198                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2199                                 intel_prepare_page_flip(dev, 1);
2200                                 intel_finish_page_flip(dev, 1);
2201                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2202                         }
2203                 }
2204
2205                 iir = new_iir;
2206         }
2207
2208         return IRQ_HANDLED;
2209 }
2210
2211 static void i8xx_irq_uninstall(struct drm_device * dev)
2212 {
2213         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2214         int pipe;
2215
2216         for_each_pipe(pipe) {
2217                 /* Clear enable bits; then clear status bits */
2218                 I915_WRITE(PIPESTAT(pipe), 0);
2219                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2220         }
2221         I915_WRITE16(IMR, 0xffff);
2222         I915_WRITE16(IER, 0x0);
2223         I915_WRITE16(IIR, I915_READ16(IIR));
2224 }
2225
2226 static void i915_irq_preinstall(struct drm_device * dev)
2227 {
2228         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2229         int pipe;
2230
2231         atomic_set(&dev_priv->irq_received, 0);
2232
2233         if (I915_HAS_HOTPLUG(dev)) {
2234                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2235                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2236         }
2237
2238         I915_WRITE16(HWSTAM, 0xeffe);
2239         for_each_pipe(pipe)
2240                 I915_WRITE(PIPESTAT(pipe), 0);
2241         I915_WRITE(IMR, 0xffffffff);
2242         I915_WRITE(IER, 0x0);
2243         POSTING_READ(IER);
2244 }
2245
2246 static int i915_irq_postinstall(struct drm_device *dev)
2247 {
2248         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2249         u32 enable_mask;
2250
2251         dev_priv->pipestat[0] = 0;
2252         dev_priv->pipestat[1] = 0;
2253
2254         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2255
2256         /* Unmask the interrupts that we always want on. */
2257         dev_priv->irq_mask =
2258                 ~(I915_ASLE_INTERRUPT |
2259                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2260                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2261                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2262                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2263                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2264
2265         enable_mask =
2266                 I915_ASLE_INTERRUPT |
2267                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2268                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2269                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2270                 I915_USER_INTERRUPT;
2271
2272         if (I915_HAS_HOTPLUG(dev)) {
2273                 /* Enable in IER... */
2274                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2275                 /* and unmask in IMR */
2276                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2277         }
2278
2279         I915_WRITE(IMR, dev_priv->irq_mask);
2280         I915_WRITE(IER, enable_mask);
2281         POSTING_READ(IER);
2282
2283         if (I915_HAS_HOTPLUG(dev)) {
2284                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2285
2286                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2287                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2288                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2289                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2290                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2291                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
2292                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2293                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2294                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2295                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2296                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2297                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2298                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2299                 }
2300
2301                 /* Ignore TV since it's buggy */
2302
2303                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2304         }
2305
2306         intel_opregion_enable_asle(dev);
2307
2308         return 0;
2309 }
2310
2311 static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2312 {
2313         struct drm_device *dev = (struct drm_device *) arg;
2314         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2315         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2316         unsigned long irqflags;
2317         u32 flip_mask =
2318                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2319                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2320         u32 flip[2] = {
2321                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2322                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2323         };
2324         int pipe, ret = IRQ_NONE;
2325
2326         atomic_inc(&dev_priv->irq_received);
2327
2328         iir = I915_READ(IIR);
2329         do {
2330                 bool irq_received = (iir & ~flip_mask) != 0;
2331                 bool blc_event = false;
2332
2333                 /* Can't rely on pipestat interrupt bit in iir as it might
2334                  * have been cleared after the pipestat interrupt was received.
2335                  * It doesn't set the bit in iir again, but it still produces
2336                  * interrupts (for non-MSI).
2337                  */
2338                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2339                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2340                         i915_handle_error(dev, false);
2341
2342                 for_each_pipe(pipe) {
2343                         int reg = PIPESTAT(pipe);
2344                         pipe_stats[pipe] = I915_READ(reg);
2345
2346                         /* Clear the PIPE*STAT regs before the IIR */
2347                         if (pipe_stats[pipe] & 0x8000ffff) {
2348                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2349                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2350                                                          pipe_name(pipe));
2351                                 I915_WRITE(reg, pipe_stats[pipe]);
2352                                 irq_received = true;
2353                         }
2354                 }
2355                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2356
2357                 if (!irq_received)
2358                         break;
2359
2360                 /* Consume port.  Then clear IIR or we'll miss events */
2361                 if ((I915_HAS_HOTPLUG(dev)) &&
2362                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2363                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2364
2365                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2366                                   hotplug_status);
2367                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2368                                 queue_work(dev_priv->wq,
2369                                            &dev_priv->hotplug_work);
2370
2371                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2372                         POSTING_READ(PORT_HOTPLUG_STAT);
2373                 }
2374
2375                 I915_WRITE(IIR, iir & ~flip_mask);
2376                 new_iir = I915_READ(IIR); /* Flush posted writes */
2377
2378                 if (iir & I915_USER_INTERRUPT)
2379                         notify_ring(dev, &dev_priv->ring[RCS]);
2380
2381                 for_each_pipe(pipe) {
2382                         int plane = pipe;
2383                         if (IS_MOBILE(dev))
2384                                 plane = !plane;
2385                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2386                             drm_handle_vblank(dev, pipe)) {
2387                                 if (iir & flip[plane]) {
2388                                         intel_prepare_page_flip(dev, plane);
2389                                         intel_finish_page_flip(dev, pipe);
2390                                         flip_mask &= ~flip[plane];
2391                                 }
2392                         }
2393
2394                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2395                                 blc_event = true;
2396                 }
2397
2398                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2399                         intel_opregion_asle_intr(dev);
2400
2401                 /* With MSI, interrupts are only generated when iir
2402                  * transitions from zero to nonzero.  If another bit got
2403                  * set while we were handling the existing iir bits, then
2404                  * we would never get another interrupt.
2405                  *
2406                  * This is fine on non-MSI as well, as if we hit this path
2407                  * we avoid exiting the interrupt handler only to generate
2408                  * another one.
2409                  *
2410                  * Note that for MSI this could cause a stray interrupt report
2411                  * if an interrupt landed in the time between writing IIR and
2412                  * the posting read.  This should be rare enough to never
2413                  * trigger the 99% of 100,000 interrupts test for disabling
2414                  * stray interrupts.
2415                  */
2416                 ret = IRQ_HANDLED;
2417                 iir = new_iir;
2418         } while (iir & ~flip_mask);
2419
2420         i915_update_dri1_breadcrumb(dev);
2421
2422         return ret;
2423 }
2424
2425 static void i915_irq_uninstall(struct drm_device * dev)
2426 {
2427         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2428         int pipe;
2429
2430         if (I915_HAS_HOTPLUG(dev)) {
2431                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2432                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2433         }
2434
2435         I915_WRITE16(HWSTAM, 0xffff);
2436         for_each_pipe(pipe) {
2437                 /* Clear enable bits; then clear status bits */
2438                 I915_WRITE(PIPESTAT(pipe), 0);
2439                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2440         }
2441         I915_WRITE(IMR, 0xffffffff);
2442         I915_WRITE(IER, 0x0);
2443
2444         I915_WRITE(IIR, I915_READ(IIR));
2445 }
2446
2447 static void i965_irq_preinstall(struct drm_device * dev)
2448 {
2449         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2450         int pipe;
2451
2452         atomic_set(&dev_priv->irq_received, 0);
2453
2454         I915_WRITE(PORT_HOTPLUG_EN, 0);
2455         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2456
2457         I915_WRITE(HWSTAM, 0xeffe);
2458         for_each_pipe(pipe)
2459                 I915_WRITE(PIPESTAT(pipe), 0);
2460         I915_WRITE(IMR, 0xffffffff);
2461         I915_WRITE(IER, 0x0);
2462         POSTING_READ(IER);
2463 }
2464
2465 static int i965_irq_postinstall(struct drm_device *dev)
2466 {
2467         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2468         u32 hotplug_en;
2469         u32 enable_mask;
2470         u32 error_mask;
2471
2472         /* Unmask the interrupts that we always want on. */
2473         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2474                                I915_DISPLAY_PORT_INTERRUPT |
2475                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2476                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2477                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2478                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2479                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2480
2481         enable_mask = ~dev_priv->irq_mask;
2482         enable_mask |= I915_USER_INTERRUPT;
2483
2484         if (IS_G4X(dev))
2485                 enable_mask |= I915_BSD_USER_INTERRUPT;
2486
2487         dev_priv->pipestat[0] = 0;
2488         dev_priv->pipestat[1] = 0;
2489
2490         /*
2491          * Enable some error detection, note the instruction error mask
2492          * bit is reserved, so we leave it masked.
2493          */
2494         if (IS_G4X(dev)) {
2495                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2496                                GM45_ERROR_MEM_PRIV |
2497                                GM45_ERROR_CP_PRIV |
2498                                I915_ERROR_MEMORY_REFRESH);
2499         } else {
2500                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2501                                I915_ERROR_MEMORY_REFRESH);
2502         }
2503         I915_WRITE(EMR, error_mask);
2504
2505         I915_WRITE(IMR, dev_priv->irq_mask);
2506         I915_WRITE(IER, enable_mask);
2507         POSTING_READ(IER);
2508
2509         /* Note HDMI and DP share hotplug bits */
2510         hotplug_en = 0;
2511         if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2512                 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2513         if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2514                 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2515         if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2516                 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2517         if (IS_G4X(dev)) {
2518                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2519                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2520                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2521                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2522         } else {
2523                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2524                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2525                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2526                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2527         }
2528         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2529                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2530
2531                 /* Programming the CRT detection parameters tends
2532                    to generate a spurious hotplug event about three
2533                    seconds later.  So just do it once.
2534                    */
2535                 if (IS_G4X(dev))
2536                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2537                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2538         }
2539
2540         /* Ignore TV since it's buggy */
2541
2542         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2543
2544         intel_opregion_enable_asle(dev);
2545
2546         return 0;
2547 }
2548
2549 static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2550 {
2551         struct drm_device *dev = (struct drm_device *) arg;
2552         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2553         u32 iir, new_iir;
2554         u32 pipe_stats[I915_MAX_PIPES];
2555         unsigned long irqflags;
2556         int irq_received;
2557         int ret = IRQ_NONE, pipe;
2558
2559         atomic_inc(&dev_priv->irq_received);
2560
2561         iir = I915_READ(IIR);
2562
2563         for (;;) {
2564                 bool blc_event = false;
2565
2566                 irq_received = iir != 0;
2567
2568                 /* Can't rely on pipestat interrupt bit in iir as it might
2569                  * have been cleared after the pipestat interrupt was received.
2570                  * It doesn't set the bit in iir again, but it still produces
2571                  * interrupts (for non-MSI).
2572                  */
2573                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2574                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2575                         i915_handle_error(dev, false);
2576
2577                 for_each_pipe(pipe) {
2578                         int reg = PIPESTAT(pipe);
2579                         pipe_stats[pipe] = I915_READ(reg);
2580
2581                         /*
2582                          * Clear the PIPE*STAT regs before the IIR
2583                          */
2584                         if (pipe_stats[pipe] & 0x8000ffff) {
2585                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2586                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2587                                                          pipe_name(pipe));
2588                                 I915_WRITE(reg, pipe_stats[pipe]);
2589                                 irq_received = 1;
2590                         }
2591                 }
2592                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2593
2594                 if (!irq_received)
2595                         break;
2596
2597                 ret = IRQ_HANDLED;
2598
2599                 /* Consume port.  Then clear IIR or we'll miss events */
2600                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2601                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2602
2603                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2604                                   hotplug_status);
2605                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2606                                 queue_work(dev_priv->wq,
2607                                            &dev_priv->hotplug_work);
2608
2609                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2610                         I915_READ(PORT_HOTPLUG_STAT);
2611                 }
2612
2613                 I915_WRITE(IIR, iir);
2614                 new_iir = I915_READ(IIR); /* Flush posted writes */
2615
2616                 if (iir & I915_USER_INTERRUPT)
2617                         notify_ring(dev, &dev_priv->ring[RCS]);
2618                 if (iir & I915_BSD_USER_INTERRUPT)
2619                         notify_ring(dev, &dev_priv->ring[VCS]);
2620
2621                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2622                         intel_prepare_page_flip(dev, 0);
2623
2624                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2625                         intel_prepare_page_flip(dev, 1);
2626
2627                 for_each_pipe(pipe) {
2628                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2629                             drm_handle_vblank(dev, pipe)) {
2630                                 i915_pageflip_stall_check(dev, pipe);
2631                                 intel_finish_page_flip(dev, pipe);
2632                         }
2633
2634                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2635                                 blc_event = true;
2636                 }
2637
2638
2639                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2640                         intel_opregion_asle_intr(dev);
2641
2642                 /* With MSI, interrupts are only generated when iir
2643                  * transitions from zero to nonzero.  If another bit got
2644                  * set while we were handling the existing iir bits, then
2645                  * we would never get another interrupt.
2646                  *
2647                  * This is fine on non-MSI as well, as if we hit this path
2648                  * we avoid exiting the interrupt handler only to generate
2649                  * another one.
2650                  *
2651                  * Note that for MSI this could cause a stray interrupt report
2652                  * if an interrupt landed in the time between writing IIR and
2653                  * the posting read.  This should be rare enough to never
2654                  * trigger the 99% of 100,000 interrupts test for disabling
2655                  * stray interrupts.
2656                  */
2657                 iir = new_iir;
2658         }
2659
2660         i915_update_dri1_breadcrumb(dev);
2661
2662         return ret;
2663 }
2664
2665 static void i965_irq_uninstall(struct drm_device * dev)
2666 {
2667         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2668         int pipe;
2669
2670         if (!dev_priv)
2671                 return;
2672
2673         I915_WRITE(PORT_HOTPLUG_EN, 0);
2674         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2675
2676         I915_WRITE(HWSTAM, 0xffffffff);
2677         for_each_pipe(pipe)
2678                 I915_WRITE(PIPESTAT(pipe), 0);
2679         I915_WRITE(IMR, 0xffffffff);
2680         I915_WRITE(IER, 0x0);
2681
2682         for_each_pipe(pipe)
2683                 I915_WRITE(PIPESTAT(pipe),
2684                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2685         I915_WRITE(IIR, I915_READ(IIR));
2686 }
2687
2688 void intel_irq_init(struct drm_device *dev)
2689 {
2690         struct drm_i915_private *dev_priv = dev->dev_private;
2691
2692         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2693         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2694         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2695         INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
2696
2697         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2698         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2699         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2700                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2701                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2702         }
2703
2704         if (drm_core_check_feature(dev, DRIVER_MODESET))
2705                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2706         else
2707                 dev->driver->get_vblank_timestamp = NULL;
2708         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2709
2710         if (IS_VALLEYVIEW(dev)) {
2711                 dev->driver->irq_handler = valleyview_irq_handler;
2712                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2713                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2714                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2715                 dev->driver->enable_vblank = valleyview_enable_vblank;
2716                 dev->driver->disable_vblank = valleyview_disable_vblank;
2717         } else if (IS_IVYBRIDGE(dev)) {
2718                 /* Share pre & uninstall handlers with ILK/SNB */
2719                 dev->driver->irq_handler = ivybridge_irq_handler;
2720                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2721                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2722                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2723                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2724                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2725         } else if (IS_HASWELL(dev)) {
2726                 /* Share interrupts handling with IVB */
2727                 dev->driver->irq_handler = ivybridge_irq_handler;
2728                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2729                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2730                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2731                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2732                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2733         } else if (HAS_PCH_SPLIT(dev)) {
2734                 dev->driver->irq_handler = ironlake_irq_handler;
2735                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2736                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2737                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2738                 dev->driver->enable_vblank = ironlake_enable_vblank;
2739                 dev->driver->disable_vblank = ironlake_disable_vblank;
2740         } else {
2741                 if (INTEL_INFO(dev)->gen == 2) {
2742                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2743                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2744                         dev->driver->irq_handler = i8xx_irq_handler;
2745                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2746                 } else if (INTEL_INFO(dev)->gen == 3) {
2747                         /* IIR "flip pending" means done if this bit is set */
2748                         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2749
2750                         dev->driver->irq_preinstall = i915_irq_preinstall;
2751                         dev->driver->irq_postinstall = i915_irq_postinstall;
2752                         dev->driver->irq_uninstall = i915_irq_uninstall;
2753                         dev->driver->irq_handler = i915_irq_handler;
2754                 } else {
2755                         dev->driver->irq_preinstall = i965_irq_preinstall;
2756                         dev->driver->irq_postinstall = i965_irq_postinstall;
2757                         dev->driver->irq_uninstall = i965_irq_uninstall;
2758                         dev->driver->irq_handler = i965_irq_handler;
2759                 }
2760                 dev->driver->enable_vblank = i915_enable_vblank;
2761                 dev->driver->disable_vblank = i915_disable_vblank;
2762         }
2763 }