Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 static const u32 hpd_ibx[] = {
  40         [HPD_CRT] = SDE_CRT_HOTPLUG,
  41         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  42         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  43         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  44         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  45 };
  46
  47 static const u32 hpd_cpt[] = {
  48         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  49         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  50         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  51         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  52 };
  53
  54 static const u32 hpd_mask_i915[] = {
  55         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  56         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  57         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  58         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  59         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  60         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  61 };
  62
  63 static const u32 hpd_status_gen4[] = {
  64         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  65         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  66         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  67         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  68         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  69         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  70 };
  71
  72 static const u32 hpd_status_i965[] = {
  73          [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  74          [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  75          [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  76          [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  77          [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  78          [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  79 };
  80
  81 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  82         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  83         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  84         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  85         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  86         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  87         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  88 };
  89
  90
  91
  92 /* For display hotplug interrupt */
  93 static void
  94 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  95 {
  96         if ((dev_priv->irq_mask & mask) != 0) {
  97                 dev_priv->irq_mask &= ~mask;
  98                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  99                 POSTING_READ(DEIMR);
 100         }
 101 }
 102
 103 static inline void
 104 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 105 {
 106         if ((dev_priv->irq_mask & mask) != mask) {
 107                 dev_priv->irq_mask |= mask;
 108                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 109                 POSTING_READ(DEIMR);
 110         }
 111 }
 112
 113 void
 114 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 115 {
 116         u32 reg = PIPESTAT(pipe);
 117         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 118
 119         if ((pipestat & mask) == mask)
 120                 return;
 121
 122         /* Enable the interrupt, clear any pending status */
 123         pipestat |= mask | (mask >> 16);
 124         I915_WRITE(reg, pipestat);
 125         POSTING_READ(reg);
 126 }
 127
 128 void
 129 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 130 {
 131         u32 reg = PIPESTAT(pipe);
 132         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 133
 134         if ((pipestat & mask) == 0)
 135                 return;
 136
 137         pipestat &= ~mask;
 138         I915_WRITE(reg, pipestat);
 139         POSTING_READ(reg);
 140 }
 141
 142 /**
 143  * intel_enable_asle - enable ASLE interrupt for OpRegion
 144  */
 145 void intel_enable_asle(struct drm_device *dev)
 146 {
 147         drm_i915_private_t *dev_priv = dev->dev_private;
 148         unsigned long irqflags;
 149
 150         /* FIXME: opregion/asle for VLV */
 151         if (IS_VALLEYVIEW(dev))
 152                 return;
 153
 154         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 155
 156         if (HAS_PCH_SPLIT(dev))
 157                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 158         else {
 159                 i915_enable_pipestat(dev_priv, 1,
 160                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 161                 if (INTEL_INFO(dev)->gen >= 4)
 162                         i915_enable_pipestat(dev_priv, 0,
 163                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 164         }
 165
 166         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 167 }
 168
 169 /**
 170  * i915_pipe_enabled - check if a pipe is enabled
 171  * @dev: DRM device
 172  * @pipe: pipe to check
 173  *
 174  * Reading certain registers when the pipe is disabled can hang the chip.
 175  * Use this routine to make sure the PLL is running and the pipe is active
 176  * before reading such registers if unsure.
 177  */
 178 static int
 179 i915_pipe_enabled(struct drm_device *dev, int pipe)
 180 {
 181         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 182         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 183                                                                       pipe);
 184
 185         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 186 }
 187
 188 /* Called from drm generic code, passed a 'crtc', which
 189  * we use as a pipe index
 190  */
 191 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long high_frame;
 195         unsigned long low_frame;
 196         u32 high1, high2, low;
 197
 198         if (!i915_pipe_enabled(dev, pipe)) {
 199                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 200                                 "pipe %c\n", pipe_name(pipe));
 201                 return 0;
 202         }
 203
 204         high_frame = PIPEFRAME(pipe);
 205         low_frame = PIPEFRAMEPIXEL(pipe);
 206
 207         /*
 208          * High & low register fields aren't synchronized, so make sure
 209          * we get a low value that's stable across two reads of the high
 210          * register.
 211          */
 212         do {
 213                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 214                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 215                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 216         } while (high1 != high2);
 217
 218         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 219         low >>= PIPE_FRAME_LOW_SHIFT;
 220         return (high1 << 8) | low;
 221 }
 222
 223 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 224 {
 225         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 226         int reg = PIPE_FRMCOUNT_GM45(pipe);
 227
 228         if (!i915_pipe_enabled(dev, pipe)) {
 229                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 230                                  "pipe %c\n", pipe_name(pipe));
 231                 return 0;
 232         }
 233
 234         return I915_READ(reg);
 235 }
 236
 237 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 238                              int *vpos, int *hpos)
 239 {
 240         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 241         u32 vbl = 0, position = 0;
 242         int vbl_start, vbl_end, htotal, vtotal;
 243         bool in_vbl = true;
 244         int ret = 0;
 245         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 246                                                                       pipe);
 247
 248         if (!i915_pipe_enabled(dev, pipe)) {
 249                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 250                                  "pipe %c\n", pipe_name(pipe));
 251                 return 0;
 252         }
 253
 254         /* Get vtotal. */
 255         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 256
 257         if (INTEL_INFO(dev)->gen >= 4) {
 258                 /* No obvious pixelcount register. Only query vertical
 259                  * scanout position from Display scan line register.
 260                  */
 261                 position = I915_READ(PIPEDSL(pipe));
 262
 263                 /* Decode into vertical scanout position. Don't have
 264                  * horizontal scanout position.
 265                  */
 266                 *vpos = position & 0x1fff;
 267                 *hpos = 0;
 268         } else {
 269                 /* Have access to pixelcount since start of frame.
 270                  * We can split this into vertical and horizontal
 271                  * scanout position.
 272                  */
 273                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 274
 275                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 276                 *vpos = position / htotal;
 277                 *hpos = position - (*vpos * htotal);
 278         }
 279
 280         /* Query vblank area. */
 281         vbl = I915_READ(VBLANK(cpu_transcoder));
 282
 283         /* Test position against vblank region. */
 284         vbl_start = vbl & 0x1fff;
 285         vbl_end = (vbl >> 16) & 0x1fff;
 286
 287         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 288                 in_vbl = false;
 289
 290         /* Inside "upper part" of vblank area? Apply corrective offset: */
 291         if (in_vbl && (*vpos >= vbl_start))
 292                 *vpos = *vpos - vtotal;
 293
 294         /* Readouts valid? */
 295         if (vbl > 0)
 296                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 297
 298         /* In vblank? */
 299         if (in_vbl)
 300                 ret |= DRM_SCANOUTPOS_INVBL;
 301
 302         return ret;
 303 }
 304
 305 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 306                               int *max_error,
 307                               struct timeval *vblank_time,
 308                               unsigned flags)
 309 {
 310         struct drm_crtc *crtc;
 311
 312         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 313                 DRM_ERROR("Invalid crtc %d\n", pipe);
 314                 return -EINVAL;
 315         }
 316
 317         /* Get drm_crtc to timestamp: */
 318         crtc = intel_get_crtc_for_pipe(dev, pipe);
 319         if (crtc == NULL) {
 320                 DRM_ERROR("Invalid crtc %d\n", pipe);
 321                 return -EINVAL;
 322         }
 323
 324         if (!crtc->enabled) {
 325                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 326                 return -EBUSY;
 327         }
 328
 329         /* Helper routine in DRM core does all the work: */
 330         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 331                                                      vblank_time, flags,
 332                                                      crtc);
 333 }
 334
 335 /*
 336  * Handle hotplug events outside the interrupt handler proper.
 337  */
 338 static void i915_hotplug_work_func(struct work_struct *work)
 339 {
 340         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 341                                                     hotplug_work);
 342         struct drm_device *dev = dev_priv->dev;
 343         struct drm_mode_config *mode_config = &dev->mode_config;
 344         struct intel_encoder *encoder;
 345
 346         /* HPD irq before everything is fully set up. */
 347         if (!dev_priv->enable_hotplug_processing)
 348                 return;
 349
 350         mutex_lock(&mode_config->mutex);
 351         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 352
 353         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 354                 if (encoder->hot_plug)
 355                         encoder->hot_plug(encoder);
 356
 357         mutex_unlock(&mode_config->mutex);
 358
 359         /* Just fire off a uevent and let userspace tell us what to do */
 360         drm_helper_hpd_irq_event(dev);
 361 }
 362
 363 static void ironlake_handle_rps_change(struct drm_device *dev)
 364 {
 365         drm_i915_private_t *dev_priv = dev->dev_private;
 366         u32 busy_up, busy_down, max_avg, min_avg;
 367         u8 new_delay;
 368         unsigned long flags;
 369
 370         spin_lock_irqsave(&mchdev_lock, flags);
 371
 372         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 373
 374         new_delay = dev_priv->ips.cur_delay;
 375
 376         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 377         busy_up = I915_READ(RCPREVBSYTUPAVG);
 378         busy_down = I915_READ(RCPREVBSYTDNAVG);
 379         max_avg = I915_READ(RCBMAXAVG);
 380         min_avg = I915_READ(RCBMINAVG);
 381
 382         /* Handle RCS change request from hw */
 383         if (busy_up > max_avg) {
 384                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 385                         new_delay = dev_priv->ips.cur_delay - 1;
 386                 if (new_delay < dev_priv->ips.max_delay)
 387                         new_delay = dev_priv->ips.max_delay;
 388         } else if (busy_down < min_avg) {
 389                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 390                         new_delay = dev_priv->ips.cur_delay + 1;
 391                 if (new_delay > dev_priv->ips.min_delay)
 392                         new_delay = dev_priv->ips.min_delay;
 393         }
 394
 395         if (ironlake_set_drps(dev, new_delay))
 396                 dev_priv->ips.cur_delay = new_delay;
 397
 398         spin_unlock_irqrestore(&mchdev_lock, flags);
 399
 400         return;
 401 }
 402
 403 static void notify_ring(struct drm_device *dev,
 404                         struct intel_ring_buffer *ring)
 405 {
 406         struct drm_i915_private *dev_priv = dev->dev_private;
 407
 408         if (ring->obj == NULL)
 409                 return;
 410
 411         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 412
 413         wake_up_all(&ring->irq_queue);
 414         if (i915_enable_hangcheck) {
 415                 dev_priv->gpu_error.hangcheck_count = 0;
 416                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 417                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 418         }
 419 }
 420
 421 static void gen6_pm_rps_work(struct work_struct *work)
 422 {
 423         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 424                                                     rps.work);
 425         u32 pm_iir, pm_imr;
 426         u8 new_delay;
 427
 428         spin_lock_irq(&dev_priv->rps.lock);
 429         pm_iir = dev_priv->rps.pm_iir;
 430         dev_priv->rps.pm_iir = 0;
 431         pm_imr = I915_READ(GEN6_PMIMR);
 432         I915_WRITE(GEN6_PMIMR, 0);
 433         spin_unlock_irq(&dev_priv->rps.lock);
 434
 435         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 436                 return;
 437
 438         mutex_lock(&dev_priv->rps.hw_lock);
 439
 440         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 441                 new_delay = dev_priv->rps.cur_delay + 1;
 442         else
 443                 new_delay = dev_priv->rps.cur_delay - 1;
 444
 445         /* sysfs frequency interfaces may have snuck in while servicing the
 446          * interrupt
 447          */
 448         if (!(new_delay > dev_priv->rps.max_delay ||
 449               new_delay < dev_priv->rps.min_delay)) {
 450                 gen6_set_rps(dev_priv->dev, new_delay);
 451         }
 452
 453         mutex_unlock(&dev_priv->rps.hw_lock);
 454 }
 455
 456
 457 /**
 458  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 459  * occurred.
 460  * @work: workqueue struct
 461  *
 462  * Doesn't actually do anything except notify userspace. As a consequence of
 463  * this event, userspace should try to remap the bad rows since statistically
 464  * it is likely the same row is more likely to go bad again.
 465  */
 466 static void ivybridge_parity_work(struct work_struct *work)
 467 {
 468         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 469                                                     l3_parity.error_work);
 470         u32 error_status, row, bank, subbank;
 471         char *parity_event[5];
 472         uint32_t misccpctl;
 473         unsigned long flags;
 474
 475         /* We must turn off DOP level clock gating to access the L3 registers.
 476          * In order to prevent a get/put style interface, acquire struct mutex
 477          * any time we access those registers.
 478          */
 479         mutex_lock(&dev_priv->dev->struct_mutex);
 480
 481         misccpctl = I915_READ(GEN7_MISCCPCTL);
 482         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 483         POSTING_READ(GEN7_MISCCPCTL);
 484
 485         error_status = I915_READ(GEN7_L3CDERRST1);
 486         row = GEN7_PARITY_ERROR_ROW(error_status);
 487         bank = GEN7_PARITY_ERROR_BANK(error_status);
 488         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 489
 490         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 491                                     GEN7_L3CDERRST1_ENABLE);
 492         POSTING_READ(GEN7_L3CDERRST1);
 493
 494         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 495
 496         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 497         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 498         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 499         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 500
 501         mutex_unlock(&dev_priv->dev->struct_mutex);
 502
 503         parity_event[0] = "L3_PARITY_ERROR=1";
 504         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 505         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 506         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 507         parity_event[4] = NULL;
 508
 509         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 510                            KOBJ_CHANGE, parity_event);
 511
 512         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 513                   row, bank, subbank);
 514
 515         kfree(parity_event[3]);
 516         kfree(parity_event[2]);
 517         kfree(parity_event[1]);
 518 }
 519
 520 static void ivybridge_handle_parity_error(struct drm_device *dev)
 521 {
 522         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 523         unsigned long flags;
 524
 525         if (!HAS_L3_GPU_CACHE(dev))
 526                 return;
 527
 528         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 529         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 530         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 531         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 532
 533         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 534 }
 535
 536 static void snb_gt_irq_handler(struct drm_device *dev,
 537                                struct drm_i915_private *dev_priv,
 538                                u32 gt_iir)
 539 {
 540
 541         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 542                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 543                 notify_ring(dev, &dev_priv->ring[RCS]);
 544         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 545                 notify_ring(dev, &dev_priv->ring[VCS]);
 546         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 547                 notify_ring(dev, &dev_priv->ring[BCS]);
 548
 549         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 550                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 551                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 552                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 553                 i915_handle_error(dev, false);
 554         }
 555
 556         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 557                 ivybridge_handle_parity_error(dev);
 558 }
 559
 560 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 561                                 u32 pm_iir)
 562 {
 563         unsigned long flags;
 564
 565         /*
 566          * IIR bits should never already be set because IMR should
 567          * prevent an interrupt from being shown in IIR. The warning
 568          * displays a case where we've unsafely cleared
 569          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 570          * type is not a problem, it displays a problem in the logic.
 571          *
 572          * The mask bit in IMR is cleared by dev_priv->rps.work.
 573          */
 574
 575         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 576         dev_priv->rps.pm_iir |= pm_iir;
 577         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 578         POSTING_READ(GEN6_PMIMR);
 579         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 580
 581         queue_work(dev_priv->wq, &dev_priv->rps.work);
 582 }
 583
 584 static void gmbus_irq_handler(struct drm_device *dev)
 585 {
 586         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 587
 588         wake_up_all(&dev_priv->gmbus_wait_queue);
 589 }
 590
 591 static void dp_aux_irq_handler(struct drm_device *dev)
 592 {
 593         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 594
 595         wake_up_all(&dev_priv->gmbus_wait_queue);
 596 }
 597
 598 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 599 {
 600         struct drm_device *dev = (struct drm_device *) arg;
 601         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 602         u32 iir, gt_iir, pm_iir;
 603         irqreturn_t ret = IRQ_NONE;
 604         unsigned long irqflags;
 605         int pipe;
 606         u32 pipe_stats[I915_MAX_PIPES];
 607
 608         atomic_inc(&dev_priv->irq_received);
 609
 610         while (true) {
 611                 iir = I915_READ(VLV_IIR);
 612                 gt_iir = I915_READ(GTIIR);
 613                 pm_iir = I915_READ(GEN6_PMIIR);
 614
 615                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 616                         goto out;
 617
 618                 ret = IRQ_HANDLED;
 619
 620                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 621
 622                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 623                 for_each_pipe(pipe) {
 624                         int reg = PIPESTAT(pipe);
 625                         pipe_stats[pipe] = I915_READ(reg);
 626
 627                         /*
 628                          * Clear the PIPE*STAT regs before the IIR
 629                          */
 630                         if (pipe_stats[pipe] & 0x8000ffff) {
 631                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 632                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 633                                                          pipe_name(pipe));
 634                                 I915_WRITE(reg, pipe_stats[pipe]);
 635                         }
 636                 }
 637                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 638
 639                 for_each_pipe(pipe) {
 640                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 641                                 drm_handle_vblank(dev, pipe);
 642
 643                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 644                                 intel_prepare_page_flip(dev, pipe);
 645                                 intel_finish_page_flip(dev, pipe);
 646                         }
 647                 }
 648
 649                 /* Consume port.  Then clear IIR or we'll miss events */
 650                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 651                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 652
 653                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 654                                          hotplug_status);
 655                         if (hotplug_status & HOTPLUG_INT_STATUS_I915)
 656                                 queue_work(dev_priv->wq,
 657                                            &dev_priv->hotplug_work);
 658
 659                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 660                         I915_READ(PORT_HOTPLUG_STAT);
 661                 }
 662
 663                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 664                         gmbus_irq_handler(dev);
 665
 666                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 667                         gen6_queue_rps_work(dev_priv, pm_iir);
 668
 669                 I915_WRITE(GTIIR, gt_iir);
 670                 I915_WRITE(GEN6_PMIIR, pm_iir);
 671                 I915_WRITE(VLV_IIR, iir);
 672         }
 673
 674 out:
 675         return ret;
 676 }
 677
 678 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 679 {
 680         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 681         int pipe;
 682
 683         if (pch_iir & SDE_HOTPLUG_MASK)
 684                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 685
 686         if (pch_iir & SDE_AUDIO_POWER_MASK)
 687                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 688                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 689                                  SDE_AUDIO_POWER_SHIFT);
 690
 691         if (pch_iir & SDE_AUX_MASK)
 692                 dp_aux_irq_handler(dev);
 693
 694         if (pch_iir & SDE_GMBUS)
 695                 gmbus_irq_handler(dev);
 696
 697         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 698                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 699
 700         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 701                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 702
 703         if (pch_iir & SDE_POISON)
 704                 DRM_ERROR("PCH poison interrupt\n");
 705
 706         if (pch_iir & SDE_FDI_MASK)
 707                 for_each_pipe(pipe)
 708                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 709                                          pipe_name(pipe),
 710                                          I915_READ(FDI_RX_IIR(pipe)));
 711
 712         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 713                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 714
 715         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 716                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 717
 718         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 719                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 720         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 721                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 722 }
 723
 724 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 725 {
 726         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 727         int pipe;
 728
 729         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 730                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 731
 732         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 733                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 734                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 735                                  SDE_AUDIO_POWER_SHIFT_CPT);
 736
 737         if (pch_iir & SDE_AUX_MASK_CPT)
 738                 dp_aux_irq_handler(dev);
 739
 740         if (pch_iir & SDE_GMBUS_CPT)
 741                 gmbus_irq_handler(dev);
 742
 743         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 744                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 745
 746         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 747                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 748
 749         if (pch_iir & SDE_FDI_MASK_CPT)
 750                 for_each_pipe(pipe)
 751                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 752                                          pipe_name(pipe),
 753                                          I915_READ(FDI_RX_IIR(pipe)));
 754 }
 755
 756 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 757 {
 758         struct drm_device *dev = (struct drm_device *) arg;
 759         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 760         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 761         irqreturn_t ret = IRQ_NONE;
 762         int i;
 763
 764         atomic_inc(&dev_priv->irq_received);
 765
 766         /* disable master interrupt before clearing iir  */
 767         de_ier = I915_READ(DEIER);
 768         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 769
 770         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 771          * interrupts will will be stored on its back queue, and then we'll be
 772          * able to process them after we restore SDEIER (as soon as we restore
 773          * it, we'll get an interrupt if SDEIIR still has something to process
 774          * due to its back queue). */
 775         sde_ier = I915_READ(SDEIER);
 776         I915_WRITE(SDEIER, 0);
 777         POSTING_READ(SDEIER);
 778
 779         gt_iir = I915_READ(GTIIR);
 780         if (gt_iir) {
 781                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 782                 I915_WRITE(GTIIR, gt_iir);
 783                 ret = IRQ_HANDLED;
 784         }
 785
 786         de_iir = I915_READ(DEIIR);
 787         if (de_iir) {
 788                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
 789                         dp_aux_irq_handler(dev);
 790
 791                 if (de_iir & DE_GSE_IVB)
 792                         intel_opregion_gse_intr(dev);
 793
 794                 for (i = 0; i < 3; i++) {
 795                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 796                                 drm_handle_vblank(dev, i);
 797                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 798                                 intel_prepare_page_flip(dev, i);
 799                                 intel_finish_page_flip_plane(dev, i);
 800                         }
 801                 }
 802
 803                 /* check event from PCH */
 804                 if (de_iir & DE_PCH_EVENT_IVB) {
 805                         u32 pch_iir = I915_READ(SDEIIR);
 806
 807                         cpt_irq_handler(dev, pch_iir);
 808
 809                         /* clear PCH hotplug event before clear CPU irq */
 810                         I915_WRITE(SDEIIR, pch_iir);
 811                 }
 812
 813                 I915_WRITE(DEIIR, de_iir);
 814                 ret = IRQ_HANDLED;
 815         }
 816
 817         pm_iir = I915_READ(GEN6_PMIIR);
 818         if (pm_iir) {
 819                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 820                         gen6_queue_rps_work(dev_priv, pm_iir);
 821                 I915_WRITE(GEN6_PMIIR, pm_iir);
 822                 ret = IRQ_HANDLED;
 823         }
 824
 825         I915_WRITE(DEIER, de_ier);
 826         POSTING_READ(DEIER);
 827         I915_WRITE(SDEIER, sde_ier);
 828         POSTING_READ(SDEIER);
 829
 830         return ret;
 831 }
 832
 833 static void ilk_gt_irq_handler(struct drm_device *dev,
 834                                struct drm_i915_private *dev_priv,
 835                                u32 gt_iir)
 836 {
 837         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 838                 notify_ring(dev, &dev_priv->ring[RCS]);
 839         if (gt_iir & GT_BSD_USER_INTERRUPT)
 840                 notify_ring(dev, &dev_priv->ring[VCS]);
 841 }
 842
 843 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 844 {
 845         struct drm_device *dev = (struct drm_device *) arg;
 846         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 847         int ret = IRQ_NONE;
 848         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 849
 850         atomic_inc(&dev_priv->irq_received);
 851
 852         /* disable master interrupt before clearing iir  */
 853         de_ier = I915_READ(DEIER);
 854         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 855         POSTING_READ(DEIER);
 856
 857         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 858          * interrupts will will be stored on its back queue, and then we'll be
 859          * able to process them after we restore SDEIER (as soon as we restore
 860          * it, we'll get an interrupt if SDEIIR still has something to process
 861          * due to its back queue). */
 862         sde_ier = I915_READ(SDEIER);
 863         I915_WRITE(SDEIER, 0);
 864         POSTING_READ(SDEIER);
 865
 866         de_iir = I915_READ(DEIIR);
 867         gt_iir = I915_READ(GTIIR);
 868         pm_iir = I915_READ(GEN6_PMIIR);
 869
 870         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
 871                 goto done;
 872
 873         ret = IRQ_HANDLED;
 874
 875         if (IS_GEN5(dev))
 876                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 877         else
 878                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 879
 880         if (de_iir & DE_AUX_CHANNEL_A)
 881                 dp_aux_irq_handler(dev);
 882
 883         if (de_iir & DE_GSE)
 884                 intel_opregion_gse_intr(dev);
 885
 886         if (de_iir & DE_PIPEA_VBLANK)
 887                 drm_handle_vblank(dev, 0);
 888
 889         if (de_iir & DE_PIPEB_VBLANK)
 890                 drm_handle_vblank(dev, 1);
 891
 892         if (de_iir & DE_PLANEA_FLIP_DONE) {
 893                 intel_prepare_page_flip(dev, 0);
 894                 intel_finish_page_flip_plane(dev, 0);
 895         }
 896
 897         if (de_iir & DE_PLANEB_FLIP_DONE) {
 898                 intel_prepare_page_flip(dev, 1);
 899                 intel_finish_page_flip_plane(dev, 1);
 900         }
 901
 902         /* check event from PCH */
 903         if (de_iir & DE_PCH_EVENT) {
 904                 u32 pch_iir = I915_READ(SDEIIR);
 905
 906                 if (HAS_PCH_CPT(dev))
 907                         cpt_irq_handler(dev, pch_iir);
 908                 else
 909                         ibx_irq_handler(dev, pch_iir);
 910
 911                 /* should clear PCH hotplug event before clear CPU irq */
 912                 I915_WRITE(SDEIIR, pch_iir);
 913         }
 914
 915         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 916                 ironlake_handle_rps_change(dev);
 917
 918         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 919                 gen6_queue_rps_work(dev_priv, pm_iir);
 920
 921         I915_WRITE(GTIIR, gt_iir);
 922         I915_WRITE(DEIIR, de_iir);
 923         I915_WRITE(GEN6_PMIIR, pm_iir);
 924
 925 done:
 926         I915_WRITE(DEIER, de_ier);
 927         POSTING_READ(DEIER);
 928         I915_WRITE(SDEIER, sde_ier);
 929         POSTING_READ(SDEIER);
 930
 931         return ret;
 932 }
 933
 934 /**
 935  * i915_error_work_func - do process context error handling work
 936  * @work: work struct
 937  *
 938  * Fire an error uevent so userspace can see that a hang or error
 939  * was detected.
 940  */
 941 static void i915_error_work_func(struct work_struct *work)
 942 {
 943         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
 944                                                     work);
 945         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
 946                                                     gpu_error);
 947         struct drm_device *dev = dev_priv->dev;
 948         struct intel_ring_buffer *ring;
 949         char *error_event[] = { "ERROR=1", NULL };
 950         char *reset_event[] = { "RESET=1", NULL };
 951         char *reset_done_event[] = { "ERROR=0", NULL };
 952         int i, ret;
 953
 954         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 955
 956         /*
 957          * Note that there's only one work item which does gpu resets, so we
 958          * need not worry about concurrent gpu resets potentially incrementing
 959          * error->reset_counter twice. We only need to take care of another
 960          * racing irq/hangcheck declaring the gpu dead for a second time. A
 961          * quick check for that is good enough: schedule_work ensures the
 962          * correct ordering between hang detection and this work item, and since
 963          * the reset in-progress bit is only ever set by code outside of this
 964          * work we don't need to worry about any other races.
 965          */
 966         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
 967                 DRM_DEBUG_DRIVER("resetting chip\n");
 968                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
 969                                    reset_event);
 970
 971                 ret = i915_reset(dev);
 972
 973                 if (ret == 0) {
 974                         /*
 975                          * After all the gem state is reset, increment the reset
 976                          * counter and wake up everyone waiting for the reset to
 977                          * complete.
 978                          *
 979                          * Since unlock operations are a one-sided barrier only,
 980                          * we need to insert a barrier here to order any seqno
 981                          * updates before
 982                          * the counter increment.
 983                          */
 984                         smp_mb__before_atomic_inc();
 985                         atomic_inc(&dev_priv->gpu_error.reset_counter);
 986
 987                         kobject_uevent_env(&dev->primary->kdev.kobj,
 988                                            KOBJ_CHANGE, reset_done_event);
 989                 } else {
 990                         atomic_set(&error->reset_counter, I915_WEDGED);
 991                 }
 992
 993                 for_each_ring(ring, dev_priv, i)
 994                         wake_up_all(&ring->irq_queue);
 995
 996                 intel_display_handle_reset(dev);
 997
 998                 wake_up_all(&dev_priv->gpu_error.reset_queue);
 999         }
1000 }
1001
1002 /* NB: please notice the memset */
1003 static void i915_get_extra_instdone(struct drm_device *dev,
1004                                     uint32_t *instdone)
1005 {
1006         struct drm_i915_private *dev_priv = dev->dev_private;
1007         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1008
1009         switch(INTEL_INFO(dev)->gen) {
1010         case 2:
1011         case 3:
1012                 instdone[0] = I915_READ(INSTDONE);
1013                 break;
1014         case 4:
1015         case 5:
1016         case 6:
1017                 instdone[0] = I915_READ(INSTDONE_I965);
1018                 instdone[1] = I915_READ(INSTDONE1);
1019                 break;
1020         default:
1021                 WARN_ONCE(1, "Unsupported platform\n");
1022         case 7:
1023                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1024                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1025                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1026                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1027                 break;
1028         }
1029 }
1030
1031 #ifdef CONFIG_DEBUG_FS
1032 static struct drm_i915_error_object *
1033 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1034                                struct drm_i915_gem_object *src,
1035                                const int num_pages)
1036 {
1037         struct drm_i915_error_object *dst;
1038         int i;
1039         u32 reloc_offset;
1040
1041         if (src == NULL || src->pages == NULL)
1042                 return NULL;
1043
1044         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1045         if (dst == NULL)
1046                 return NULL;
1047
1048         reloc_offset = src->gtt_offset;
1049         for (i = 0; i < num_pages; i++) {
1050                 unsigned long flags;
1051                 void *d;
1052
1053                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1054                 if (d == NULL)
1055                         goto unwind;
1056
1057                 local_irq_save(flags);
1058                 if (reloc_offset < dev_priv->gtt.mappable_end &&
1059                     src->has_global_gtt_mapping) {
1060                         void __iomem *s;
1061
1062                         /* Simply ignore tiling or any overlapping fence.
1063                          * It's part of the error state, and this hopefully
1064                          * captures what the GPU read.
1065                          */
1066
1067                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1068                                                      reloc_offset);
1069                         memcpy_fromio(d, s, PAGE_SIZE);
1070                         io_mapping_unmap_atomic(s);
1071                 } else if (src->stolen) {
1072                         unsigned long offset;
1073
1074                         offset = dev_priv->mm.stolen_base;
1075                         offset += src->stolen->start;
1076                         offset += i << PAGE_SHIFT;
1077
1078                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1079                 } else {
1080                         struct page *page;
1081                         void *s;
1082
1083                         page = i915_gem_object_get_page(src, i);
1084
1085                         drm_clflush_pages(&page, 1);
1086
1087                         s = kmap_atomic(page);
1088                         memcpy(d, s, PAGE_SIZE);
1089                         kunmap_atomic(s);
1090
1091                         drm_clflush_pages(&page, 1);
1092                 }
1093                 local_irq_restore(flags);
1094
1095                 dst->pages[i] = d;
1096
1097                 reloc_offset += PAGE_SIZE;
1098         }
1099         dst->page_count = num_pages;
1100         dst->gtt_offset = src->gtt_offset;
1101
1102         return dst;
1103
1104 unwind:
1105         while (i--)
1106                 kfree(dst->pages[i]);
1107         kfree(dst);
1108         return NULL;
1109 }
1110 #define i915_error_object_create(dev_priv, src) \
1111         i915_error_object_create_sized((dev_priv), (src), \
1112                                        (src)->base.size>>PAGE_SHIFT)
1113
1114 static void
1115 i915_error_object_free(struct drm_i915_error_object *obj)
1116 {
1117         int page;
1118
1119         if (obj == NULL)
1120                 return;
1121
1122         for (page = 0; page < obj->page_count; page++)
1123                 kfree(obj->pages[page]);
1124
1125         kfree(obj);
1126 }
1127
1128 void
1129 i915_error_state_free(struct kref *error_ref)
1130 {
1131         struct drm_i915_error_state *error = container_of(error_ref,
1132                                                           typeof(*error), ref);
1133         int i;
1134
1135         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1136                 i915_error_object_free(error->ring[i].batchbuffer);
1137                 i915_error_object_free(error->ring[i].ringbuffer);
1138                 kfree(error->ring[i].requests);
1139         }
1140
1141         kfree(error->active_bo);
1142         kfree(error->overlay);
1143         kfree(error);
1144 }
1145 static void capture_bo(struct drm_i915_error_buffer *err,
1146                        struct drm_i915_gem_object *obj)
1147 {
1148         err->size = obj->base.size;
1149         err->name = obj->base.name;
1150         err->rseqno = obj->last_read_seqno;
1151         err->wseqno = obj->last_write_seqno;
1152         err->gtt_offset = obj->gtt_offset;
1153         err->read_domains = obj->base.read_domains;
1154         err->write_domain = obj->base.write_domain;
1155         err->fence_reg = obj->fence_reg;
1156         err->pinned = 0;
1157         if (obj->pin_count > 0)
1158                 err->pinned = 1;
1159         if (obj->user_pin_count > 0)
1160                 err->pinned = -1;
1161         err->tiling = obj->tiling_mode;
1162         err->dirty = obj->dirty;
1163         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1164         err->ring = obj->ring ? obj->ring->id : -1;
1165         err->cache_level = obj->cache_level;
1166 }
1167
1168 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1169                              int count, struct list_head *head)
1170 {
1171         struct drm_i915_gem_object *obj;
1172         int i = 0;
1173
1174         list_for_each_entry(obj, head, mm_list) {
1175                 capture_bo(err++, obj);
1176                 if (++i == count)
1177                         break;
1178         }
1179
1180         return i;
1181 }
1182
1183 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1184                              int count, struct list_head *head)
1185 {
1186         struct drm_i915_gem_object *obj;
1187         int i = 0;
1188
1189         list_for_each_entry(obj, head, gtt_list) {
1190                 if (obj->pin_count == 0)
1191                         continue;
1192
1193                 capture_bo(err++, obj);
1194                 if (++i == count)
1195                         break;
1196         }
1197
1198         return i;
1199 }
1200
1201 static void i915_gem_record_fences(struct drm_device *dev,
1202                                    struct drm_i915_error_state *error)
1203 {
1204         struct drm_i915_private *dev_priv = dev->dev_private;
1205         int i;
1206
1207         /* Fences */
1208         switch (INTEL_INFO(dev)->gen) {
1209         case 7:
1210         case 6:
1211                 for (i = 0; i < 16; i++)
1212                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1213                 break;
1214         case 5:
1215         case 4:
1216                 for (i = 0; i < 16; i++)
1217                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1218                 break;
1219         case 3:
1220                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1221                         for (i = 0; i < 8; i++)
1222                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1223         case 2:
1224                 for (i = 0; i < 8; i++)
1225                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1226                 break;
1227
1228         default:
1229                 BUG();
1230         }
1231 }
1232
1233 static struct drm_i915_error_object *
1234 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1235                              struct intel_ring_buffer *ring)
1236 {
1237         struct drm_i915_gem_object *obj;
1238         u32 seqno;
1239
1240         if (!ring->get_seqno)
1241                 return NULL;
1242
1243         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1244                 u32 acthd = I915_READ(ACTHD);
1245
1246                 if (WARN_ON(ring->id != RCS))
1247                         return NULL;
1248
1249                 obj = ring->private;
1250                 if (acthd >= obj->gtt_offset &&
1251                     acthd < obj->gtt_offset + obj->base.size)
1252                         return i915_error_object_create(dev_priv, obj);
1253         }
1254
1255         seqno = ring->get_seqno(ring, false);
1256         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1257                 if (obj->ring != ring)
1258                         continue;
1259
1260                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1261                         continue;
1262
1263                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1264                         continue;
1265
1266                 /* We need to copy these to an anonymous buffer as the simplest
1267                  * method to avoid being overwritten by userspace.
1268                  */
1269                 return i915_error_object_create(dev_priv, obj);
1270         }
1271
1272         return NULL;
1273 }
1274
1275 static void i915_record_ring_state(struct drm_device *dev,
1276                                    struct drm_i915_error_state *error,
1277                                    struct intel_ring_buffer *ring)
1278 {
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280
1281         if (INTEL_INFO(dev)->gen >= 6) {
1282                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1283                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1284                 error->semaphore_mboxes[ring->id][0]
1285                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1286                 error->semaphore_mboxes[ring->id][1]
1287                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1288                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1289                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1290         }
1291
1292         if (INTEL_INFO(dev)->gen >= 4) {
1293                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1294                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1295                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1296                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1297                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1298                 if (ring->id == RCS)
1299                         error->bbaddr = I915_READ64(BB_ADDR);
1300         } else {
1301                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1302                 error->ipeir[ring->id] = I915_READ(IPEIR);
1303                 error->ipehr[ring->id] = I915_READ(IPEHR);
1304                 error->instdone[ring->id] = I915_READ(INSTDONE);
1305         }
1306
1307         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1308         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1309         error->seqno[ring->id] = ring->get_seqno(ring, false);
1310         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1311         error->head[ring->id] = I915_READ_HEAD(ring);
1312         error->tail[ring->id] = I915_READ_TAIL(ring);
1313         error->ctl[ring->id] = I915_READ_CTL(ring);
1314
1315         error->cpu_ring_head[ring->id] = ring->head;
1316         error->cpu_ring_tail[ring->id] = ring->tail;
1317 }
1318
1319
1320 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1321                                            struct drm_i915_error_state *error,
1322                                            struct drm_i915_error_ring *ering)
1323 {
1324         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1325         struct drm_i915_gem_object *obj;
1326
1327         /* Currently render ring is the only HW context user */
1328         if (ring->id != RCS || !error->ccid)
1329                 return;
1330
1331         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1332                 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1333                         ering->ctx = i915_error_object_create_sized(dev_priv,
1334                                                                     obj, 1);
1335                 }
1336         }
1337 }
1338
1339 static void i915_gem_record_rings(struct drm_device *dev,
1340                                   struct drm_i915_error_state *error)
1341 {
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343         struct intel_ring_buffer *ring;
1344         struct drm_i915_gem_request *request;
1345         int i, count;
1346
1347         for_each_ring(ring, dev_priv, i) {
1348                 i915_record_ring_state(dev, error, ring);
1349
1350                 error->ring[i].batchbuffer =
1351                         i915_error_first_batchbuffer(dev_priv, ring);
1352
1353                 error->ring[i].ringbuffer =
1354                         i915_error_object_create(dev_priv, ring->obj);
1355
1356
1357                 i915_gem_record_active_context(ring, error, &error->ring[i]);
1358
1359                 count = 0;
1360                 list_for_each_entry(request, &ring->request_list, list)
1361                         count++;
1362
1363                 error->ring[i].num_requests = count;
1364                 error->ring[i].requests =
1365                         kmalloc(count*sizeof(struct drm_i915_error_request),
1366                                 GFP_ATOMIC);
1367                 if (error->ring[i].requests == NULL) {
1368                         error->ring[i].num_requests = 0;
1369                         continue;
1370                 }
1371
1372                 count = 0;
1373                 list_for_each_entry(request, &ring->request_list, list) {
1374                         struct drm_i915_error_request *erq;
1375
1376                         erq = &error->ring[i].requests[count++];
1377                         erq->seqno = request->seqno;
1378                         erq->jiffies = request->emitted_jiffies;
1379                         erq->tail = request->tail;
1380                 }
1381         }
1382 }
1383
1384 /**
1385  * i915_capture_error_state - capture an error record for later analysis
1386  * @dev: drm device
1387  *
1388  * Should be called when an error is detected (either a hang or an error
1389  * interrupt) to capture error state from the time of the error.  Fills
1390  * out a structure which becomes available in debugfs for user level tools
1391  * to pick up.
1392  */
1393 static void i915_capture_error_state(struct drm_device *dev)
1394 {
1395         struct drm_i915_private *dev_priv = dev->dev_private;
1396         struct drm_i915_gem_object *obj;
1397         struct drm_i915_error_state *error;
1398         unsigned long flags;
1399         int i, pipe;
1400
1401         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1402         error = dev_priv->gpu_error.first_error;
1403         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1404         if (error)
1405                 return;
1406
1407         /* Account for pipe specific data like PIPE*STAT */
1408         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1409         if (!error) {
1410                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1411                 return;
1412         }
1413
1414         DRM_INFO("capturing error event; look for more information in "
1415                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1416                  dev->primary->index);
1417
1418         kref_init(&error->ref);
1419         error->eir = I915_READ(EIR);
1420         error->pgtbl_er = I915_READ(PGTBL_ER);
1421         if (HAS_HW_CONTEXTS(dev))
1422                 error->ccid = I915_READ(CCID);
1423
1424         if (HAS_PCH_SPLIT(dev))
1425                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1426         else if (IS_VALLEYVIEW(dev))
1427                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1428         else if (IS_GEN2(dev))
1429                 error->ier = I915_READ16(IER);
1430         else
1431                 error->ier = I915_READ(IER);
1432
1433         if (INTEL_INFO(dev)->gen >= 6)
1434                 error->derrmr = I915_READ(DERRMR);
1435
1436         if (IS_VALLEYVIEW(dev))
1437                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1438         else if (INTEL_INFO(dev)->gen >= 7)
1439                 error->forcewake = I915_READ(FORCEWAKE_MT);
1440         else if (INTEL_INFO(dev)->gen == 6)
1441                 error->forcewake = I915_READ(FORCEWAKE);
1442
1443         if (!HAS_PCH_SPLIT(dev))
1444                 for_each_pipe(pipe)
1445                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1446
1447         if (INTEL_INFO(dev)->gen >= 6) {
1448                 error->error = I915_READ(ERROR_GEN6);
1449                 error->done_reg = I915_READ(DONE_REG);
1450         }
1451
1452         if (INTEL_INFO(dev)->gen == 7)
1453                 error->err_int = I915_READ(GEN7_ERR_INT);
1454
1455         i915_get_extra_instdone(dev, error->extra_instdone);
1456
1457         i915_gem_record_fences(dev, error);
1458         i915_gem_record_rings(dev, error);
1459
1460         /* Record buffers on the active and pinned lists. */
1461         error->active_bo = NULL;
1462         error->pinned_bo = NULL;
1463
1464         i = 0;
1465         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1466                 i++;
1467         error->active_bo_count = i;
1468         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1469                 if (obj->pin_count)
1470                         i++;
1471         error->pinned_bo_count = i - error->active_bo_count;
1472
1473         error->active_bo = NULL;
1474         error->pinned_bo = NULL;
1475         if (i) {
1476                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1477                                            GFP_ATOMIC);
1478                 if (error->active_bo)
1479                         error->pinned_bo =
1480                                 error->active_bo + error->active_bo_count;
1481         }
1482
1483         if (error->active_bo)
1484                 error->active_bo_count =
1485                         capture_active_bo(error->active_bo,
1486                                           error->active_bo_count,
1487                                           &dev_priv->mm.active_list);
1488
1489         if (error->pinned_bo)
1490                 error->pinned_bo_count =
1491                         capture_pinned_bo(error->pinned_bo,
1492                                           error->pinned_bo_count,
1493                                           &dev_priv->mm.bound_list);
1494
1495         do_gettimeofday(&error->time);
1496
1497         error->overlay = intel_overlay_capture_error_state(dev);
1498         error->display = intel_display_capture_error_state(dev);
1499
1500         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1501         if (dev_priv->gpu_error.first_error == NULL) {
1502                 dev_priv->gpu_error.first_error = error;
1503                 error = NULL;
1504         }
1505         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1506
1507         if (error)
1508                 i915_error_state_free(&error->ref);
1509 }
1510
1511 void i915_destroy_error_state(struct drm_device *dev)
1512 {
1513         struct drm_i915_private *dev_priv = dev->dev_private;
1514         struct drm_i915_error_state *error;
1515         unsigned long flags;
1516
1517         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1518         error = dev_priv->gpu_error.first_error;
1519         dev_priv->gpu_error.first_error = NULL;
1520         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1521
1522         if (error)
1523                 kref_put(&error->ref, i915_error_state_free);
1524 }
1525 #else
1526 #define i915_capture_error_state(x)
1527 #endif
1528
1529 static void i915_report_and_clear_eir(struct drm_device *dev)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         uint32_t instdone[I915_NUM_INSTDONE_REG];
1533         u32 eir = I915_READ(EIR);
1534         int pipe, i;
1535
1536         if (!eir)
1537                 return;
1538
1539         pr_err("render error detected, EIR: 0x%08x\n", eir);
1540
1541         i915_get_extra_instdone(dev, instdone);
1542
1543         if (IS_G4X(dev)) {
1544                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1545                         u32 ipeir = I915_READ(IPEIR_I965);
1546
1547                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1548                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1549                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1550                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1551                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1552                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1553                         I915_WRITE(IPEIR_I965, ipeir);
1554                         POSTING_READ(IPEIR_I965);
1555                 }
1556                 if (eir & GM45_ERROR_PAGE_TABLE) {
1557                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1558                         pr_err("page table error\n");
1559                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1560                         I915_WRITE(PGTBL_ER, pgtbl_err);
1561                         POSTING_READ(PGTBL_ER);
1562                 }
1563         }
1564
1565         if (!IS_GEN2(dev)) {
1566                 if (eir & I915_ERROR_PAGE_TABLE) {
1567                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1568                         pr_err("page table error\n");
1569                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1570                         I915_WRITE(PGTBL_ER, pgtbl_err);
1571                         POSTING_READ(PGTBL_ER);
1572                 }
1573         }
1574
1575         if (eir & I915_ERROR_MEMORY_REFRESH) {
1576                 pr_err("memory refresh error:\n");
1577                 for_each_pipe(pipe)
1578                         pr_err("pipe %c stat: 0x%08x\n",
1579                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1580                 /* pipestat has already been acked */
1581         }
1582         if (eir & I915_ERROR_INSTRUCTION) {
1583                 pr_err("instruction error\n");
1584                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1585                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1586                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1587                 if (INTEL_INFO(dev)->gen < 4) {
1588                         u32 ipeir = I915_READ(IPEIR);
1589
1590                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1591                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1592                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1593                         I915_WRITE(IPEIR, ipeir);
1594                         POSTING_READ(IPEIR);
1595                 } else {
1596                         u32 ipeir = I915_READ(IPEIR_I965);
1597
1598                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1599                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1600                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1601                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1602                         I915_WRITE(IPEIR_I965, ipeir);
1603                         POSTING_READ(IPEIR_I965);
1604                 }
1605         }
1606
1607         I915_WRITE(EIR, eir);
1608         POSTING_READ(EIR);
1609         eir = I915_READ(EIR);
1610         if (eir) {
1611                 /*
1612                  * some errors might have become stuck,
1613                  * mask them.
1614                  */
1615                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1616                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1617                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1618         }
1619 }
1620
1621 /**
1622  * i915_handle_error - handle an error interrupt
1623  * @dev: drm device
1624  *
1625  * Do some basic checking of regsiter state at error interrupt time and
1626  * dump it to the syslog.  Also call i915_capture_error_state() to make
1627  * sure we get a record and make it available in debugfs.  Fire a uevent
1628  * so userspace knows something bad happened (should trigger collection
1629  * of a ring dump etc.).
1630  */
1631 void i915_handle_error(struct drm_device *dev, bool wedged)
1632 {
1633         struct drm_i915_private *dev_priv = dev->dev_private;
1634         struct intel_ring_buffer *ring;
1635         int i;
1636
1637         i915_capture_error_state(dev);
1638         i915_report_and_clear_eir(dev);
1639
1640         if (wedged) {
1641                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1642                                 &dev_priv->gpu_error.reset_counter);
1643
1644                 /*
1645                  * Wakeup waiting processes so that the reset work item
1646                  * doesn't deadlock trying to grab various locks.
1647                  */
1648                 for_each_ring(ring, dev_priv, i)
1649                         wake_up_all(&ring->irq_queue);
1650         }
1651
1652         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1653 }
1654
1655 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1656 {
1657         drm_i915_private_t *dev_priv = dev->dev_private;
1658         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1659         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1660         struct drm_i915_gem_object *obj;
1661         struct intel_unpin_work *work;
1662         unsigned long flags;
1663         bool stall_detected;
1664
1665         /* Ignore early vblank irqs */
1666         if (intel_crtc == NULL)
1667                 return;
1668
1669         spin_lock_irqsave(&dev->event_lock, flags);
1670         work = intel_crtc->unpin_work;
1671
1672         if (work == NULL ||
1673             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1674             !work->enable_stall_check) {
1675                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1676                 spin_unlock_irqrestore(&dev->event_lock, flags);
1677                 return;
1678         }
1679
1680         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1681         obj = work->pending_flip_obj;
1682         if (INTEL_INFO(dev)->gen >= 4) {
1683                 int dspsurf = DSPSURF(intel_crtc->plane);
1684                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1685                                         obj->gtt_offset;
1686         } else {
1687                 int dspaddr = DSPADDR(intel_crtc->plane);
1688                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1689                                                         crtc->y * crtc->fb->pitches[0] +
1690                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1691         }
1692
1693         spin_unlock_irqrestore(&dev->event_lock, flags);
1694
1695         if (stall_detected) {
1696                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1697                 intel_prepare_page_flip(dev, intel_crtc->plane);
1698         }
1699 }
1700
1701 /* Called from drm generic code, passed 'crtc' which
1702  * we use as a pipe index
1703  */
1704 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1705 {
1706         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1707         unsigned long irqflags;
1708
1709         if (!i915_pipe_enabled(dev, pipe))
1710                 return -EINVAL;
1711
1712         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1713         if (INTEL_INFO(dev)->gen >= 4)
1714                 i915_enable_pipestat(dev_priv, pipe,
1715                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1716         else
1717                 i915_enable_pipestat(dev_priv, pipe,
1718                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1719
1720         /* maintain vblank delivery even in deep C-states */
1721         if (dev_priv->info->gen == 3)
1722                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1723         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1724
1725         return 0;
1726 }
1727
1728 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1729 {
1730         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1731         unsigned long irqflags;
1732
1733         if (!i915_pipe_enabled(dev, pipe))
1734                 return -EINVAL;
1735
1736         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1737         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1738                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1739         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1740
1741         return 0;
1742 }
1743
1744 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1745 {
1746         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1747         unsigned long irqflags;
1748
1749         if (!i915_pipe_enabled(dev, pipe))
1750                 return -EINVAL;
1751
1752         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1753         ironlake_enable_display_irq(dev_priv,
1754                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1755         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1756
1757         return 0;
1758 }
1759
1760 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1761 {
1762         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1763         unsigned long irqflags;
1764         u32 imr;
1765
1766         if (!i915_pipe_enabled(dev, pipe))
1767                 return -EINVAL;
1768
1769         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1770         imr = I915_READ(VLV_IMR);
1771         if (pipe == 0)
1772                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1773         else
1774                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1775         I915_WRITE(VLV_IMR, imr);
1776         i915_enable_pipestat(dev_priv, pipe,
1777                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1778         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1779
1780         return 0;
1781 }
1782
1783 /* Called from drm generic code, passed 'crtc' which
1784  * we use as a pipe index
1785  */
1786 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1787 {
1788         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1789         unsigned long irqflags;
1790
1791         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1792         if (dev_priv->info->gen == 3)
1793                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1794
1795         i915_disable_pipestat(dev_priv, pipe,
1796                               PIPE_VBLANK_INTERRUPT_ENABLE |
1797                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1798         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1799 }
1800
1801 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1802 {
1803         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1804         unsigned long irqflags;
1805
1806         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1807         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1808                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1809         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1810 }
1811
1812 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1813 {
1814         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1815         unsigned long irqflags;
1816
1817         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1818         ironlake_disable_display_irq(dev_priv,
1819                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1820         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1821 }
1822
1823 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1824 {
1825         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1826         unsigned long irqflags;
1827         u32 imr;
1828
1829         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1830         i915_disable_pipestat(dev_priv, pipe,
1831                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1832         imr = I915_READ(VLV_IMR);
1833         if (pipe == 0)
1834                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1835         else
1836                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1837         I915_WRITE(VLV_IMR, imr);
1838         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1839 }
1840
1841 static u32
1842 ring_last_seqno(struct intel_ring_buffer *ring)
1843 {
1844         return list_entry(ring->request_list.prev,
1845                           struct drm_i915_gem_request, list)->seqno;
1846 }
1847
1848 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1849 {
1850         if (list_empty(&ring->request_list) ||
1851             i915_seqno_passed(ring->get_seqno(ring, false),
1852                               ring_last_seqno(ring))) {
1853                 /* Issue a wake-up to catch stuck h/w. */
1854                 if (waitqueue_active(&ring->irq_queue)) {
1855                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1856                                   ring->name);
1857                         wake_up_all(&ring->irq_queue);
1858                         *err = true;
1859                 }
1860                 return true;
1861         }
1862         return false;
1863 }
1864
1865 static bool semaphore_passed(struct intel_ring_buffer *ring)
1866 {
1867         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1868         u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1869         struct intel_ring_buffer *signaller;
1870         u32 cmd, ipehr, acthd_min;
1871
1872         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1873         if ((ipehr & ~(0x3 << 16)) !=
1874             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1875                 return false;
1876
1877         /* ACTHD is likely pointing to the dword after the actual command,
1878          * so scan backwards until we find the MBOX.
1879          */
1880         acthd_min = max((int)acthd - 3 * 4, 0);
1881         do {
1882                 cmd = ioread32(ring->virtual_start + acthd);
1883                 if (cmd == ipehr)
1884                         break;
1885
1886                 acthd -= 4;
1887                 if (acthd < acthd_min)
1888                         return false;
1889         } while (1);
1890
1891         signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1892         return i915_seqno_passed(signaller->get_seqno(signaller, false),
1893                                  ioread32(ring->virtual_start+acthd+4)+1);
1894 }
1895
1896 static bool kick_ring(struct intel_ring_buffer *ring)
1897 {
1898         struct drm_device *dev = ring->dev;
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         u32 tmp = I915_READ_CTL(ring);
1901         if (tmp & RING_WAIT) {
1902                 DRM_ERROR("Kicking stuck wait on %s\n",
1903                           ring->name);
1904                 I915_WRITE_CTL(ring, tmp);
1905                 return true;
1906         }
1907
1908         if (INTEL_INFO(dev)->gen >= 6 &&
1909             tmp & RING_WAIT_SEMAPHORE &&
1910             semaphore_passed(ring)) {
1911                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1912                           ring->name);
1913                 I915_WRITE_CTL(ring, tmp);
1914                 return true;
1915         }
1916         return false;
1917 }
1918
1919 static bool i915_hangcheck_hung(struct drm_device *dev)
1920 {
1921         drm_i915_private_t *dev_priv = dev->dev_private;
1922
1923         if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1924                 bool hung = true;
1925
1926                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1927                 i915_handle_error(dev, true);
1928
1929                 if (!IS_GEN2(dev)) {
1930                         struct intel_ring_buffer *ring;
1931                         int i;
1932
1933                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1934                          * If so we can simply poke the RB_WAIT bit
1935                          * and break the hang. This should work on
1936                          * all but the second generation chipsets.
1937                          */
1938                         for_each_ring(ring, dev_priv, i)
1939                                 hung &= !kick_ring(ring);
1940                 }
1941
1942                 return hung;
1943         }
1944
1945         return false;
1946 }
1947
1948 /**
1949  * This is called when the chip hasn't reported back with completed
1950  * batchbuffers in a long time. The first time this is called we simply record
1951  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1952  * again, we assume the chip is wedged and try to fix it.
1953  */
1954 void i915_hangcheck_elapsed(unsigned long data)
1955 {
1956         struct drm_device *dev = (struct drm_device *)data;
1957         drm_i915_private_t *dev_priv = dev->dev_private;
1958         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1959         struct intel_ring_buffer *ring;
1960         bool err = false, idle;
1961         int i;
1962
1963         if (!i915_enable_hangcheck)
1964                 return;
1965
1966         memset(acthd, 0, sizeof(acthd));
1967         idle = true;
1968         for_each_ring(ring, dev_priv, i) {
1969             idle &= i915_hangcheck_ring_idle(ring, &err);
1970             acthd[i] = intel_ring_get_active_head(ring);
1971         }
1972
1973         /* If all work is done then ACTHD clearly hasn't advanced. */
1974         if (idle) {
1975                 if (err) {
1976                         if (i915_hangcheck_hung(dev))
1977                                 return;
1978
1979                         goto repeat;
1980                 }
1981
1982                 dev_priv->gpu_error.hangcheck_count = 0;
1983                 return;
1984         }
1985
1986         i915_get_extra_instdone(dev, instdone);
1987         if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1988                    sizeof(acthd)) == 0 &&
1989             memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1990                    sizeof(instdone)) == 0) {
1991                 if (i915_hangcheck_hung(dev))
1992                         return;
1993         } else {
1994                 dev_priv->gpu_error.hangcheck_count = 0;
1995
1996                 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1997                        sizeof(acthd));
1998                 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1999                        sizeof(instdone));
2000         }
2001
2002 repeat:
2003         /* Reset timer case chip hangs without another request being added */
2004         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2005                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2006 }
2007
2008 /* drm_dma.h hooks
2009 */
2010 static void ironlake_irq_preinstall(struct drm_device *dev)
2011 {
2012         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2013
2014         atomic_set(&dev_priv->irq_received, 0);
2015
2016         I915_WRITE(HWSTAM, 0xeffe);
2017
2018         /* XXX hotplug from PCH */
2019
2020         I915_WRITE(DEIMR, 0xffffffff);
2021         I915_WRITE(DEIER, 0x0);
2022         POSTING_READ(DEIER);
2023
2024         /* and GT */
2025         I915_WRITE(GTIMR, 0xffffffff);
2026         I915_WRITE(GTIER, 0x0);
2027         POSTING_READ(GTIER);
2028
2029         /* south display irq */
2030         I915_WRITE(SDEIMR, 0xffffffff);
2031         /*
2032          * SDEIER is also touched by the interrupt handler to work around missed
2033          * PCH interrupts. Hence we can't update it after the interrupt handler
2034          * is enabled - instead we unconditionally enable all PCH interrupt
2035          * sources here, but then only unmask them as needed with SDEIMR.
2036          */
2037         I915_WRITE(SDEIER, 0xffffffff);
2038         POSTING_READ(SDEIER);
2039 }
2040
2041 static void valleyview_irq_preinstall(struct drm_device *dev)
2042 {
2043         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2044         int pipe;
2045
2046         atomic_set(&dev_priv->irq_received, 0);
2047
2048         /* VLV magic */
2049         I915_WRITE(VLV_IMR, 0);
2050         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2051         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2052         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2053
2054         /* and GT */
2055         I915_WRITE(GTIIR, I915_READ(GTIIR));
2056         I915_WRITE(GTIIR, I915_READ(GTIIR));
2057         I915_WRITE(GTIMR, 0xffffffff);
2058         I915_WRITE(GTIER, 0x0);
2059         POSTING_READ(GTIER);
2060
2061         I915_WRITE(DPINVGTT, 0xff);
2062
2063         I915_WRITE(PORT_HOTPLUG_EN, 0);
2064         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2065         for_each_pipe(pipe)
2066                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2067         I915_WRITE(VLV_IIR, 0xffffffff);
2068         I915_WRITE(VLV_IMR, 0xffffffff);
2069         I915_WRITE(VLV_IER, 0x0);
2070         POSTING_READ(VLV_IER);
2071 }
2072
2073 static void ibx_hpd_irq_setup(struct drm_device *dev)
2074 {
2075         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2076         struct drm_mode_config *mode_config = &dev->mode_config;
2077         struct intel_encoder *intel_encoder;
2078         u32 mask = ~I915_READ(SDEIMR);
2079         u32 hotplug;
2080
2081         if (HAS_PCH_IBX(dev)) {
2082                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2083                         mask |= hpd_ibx[intel_encoder->hpd_pin];
2084         } else {
2085                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2086                         mask |= hpd_cpt[intel_encoder->hpd_pin];
2087         }
2088
2089         I915_WRITE(SDEIMR, ~mask);
2090
2091         /*
2092          * Enable digital hotplug on the PCH, and configure the DP short pulse
2093          * duration to 2ms (which is the minimum in the Display Port spec)
2094          *
2095          * This register is the same on all known PCH chips.
2096          */
2097         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2098         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2099         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2100         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2101         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2102         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2103 }
2104
2105 static void ibx_irq_postinstall(struct drm_device *dev)
2106 {
2107         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2108         u32 mask;
2109
2110         if (HAS_PCH_IBX(dev))
2111                 mask = SDE_GMBUS | SDE_AUX_MASK;
2112         else
2113                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2114         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2115         I915_WRITE(SDEIMR, ~mask);
2116 }
2117
2118 static int ironlake_irq_postinstall(struct drm_device *dev)
2119 {
2120         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2121         /* enable kind of interrupts always enabled */
2122         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2123                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2124                            DE_AUX_CHANNEL_A;
2125         u32 render_irqs;
2126
2127         dev_priv->irq_mask = ~display_mask;
2128
2129         /* should always can generate irq */
2130         I915_WRITE(DEIIR, I915_READ(DEIIR));
2131         I915_WRITE(DEIMR, dev_priv->irq_mask);
2132         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2133         POSTING_READ(DEIER);
2134
2135         dev_priv->gt_irq_mask = ~0;
2136
2137         I915_WRITE(GTIIR, I915_READ(GTIIR));
2138         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2139
2140         if (IS_GEN6(dev))
2141                 render_irqs =
2142                         GT_USER_INTERRUPT |
2143                         GEN6_BSD_USER_INTERRUPT |
2144                         GEN6_BLITTER_USER_INTERRUPT;
2145         else
2146                 render_irqs =
2147                         GT_USER_INTERRUPT |
2148                         GT_PIPE_NOTIFY |
2149                         GT_BSD_USER_INTERRUPT;
2150         I915_WRITE(GTIER, render_irqs);
2151         POSTING_READ(GTIER);
2152
2153         ibx_irq_postinstall(dev);
2154
2155         if (IS_IRONLAKE_M(dev)) {
2156                 /* Clear & enable PCU event interrupts */
2157                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2158                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2159                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2160         }
2161
2162         return 0;
2163 }
2164
2165 static int ivybridge_irq_postinstall(struct drm_device *dev)
2166 {
2167         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2168         /* enable kind of interrupts always enabled */
2169         u32 display_mask =
2170                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2171                 DE_PLANEC_FLIP_DONE_IVB |
2172                 DE_PLANEB_FLIP_DONE_IVB |
2173                 DE_PLANEA_FLIP_DONE_IVB |
2174                 DE_AUX_CHANNEL_A_IVB;
2175         u32 render_irqs;
2176
2177         dev_priv->irq_mask = ~display_mask;
2178
2179         /* should always can generate irq */
2180         I915_WRITE(DEIIR, I915_READ(DEIIR));
2181         I915_WRITE(DEIMR, dev_priv->irq_mask);
2182         I915_WRITE(DEIER,
2183                    display_mask |
2184                    DE_PIPEC_VBLANK_IVB |
2185                    DE_PIPEB_VBLANK_IVB |
2186                    DE_PIPEA_VBLANK_IVB);
2187         POSTING_READ(DEIER);
2188
2189         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2190
2191         I915_WRITE(GTIIR, I915_READ(GTIIR));
2192         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2193
2194         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2195                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2196         I915_WRITE(GTIER, render_irqs);
2197         POSTING_READ(GTIER);
2198
2199         ibx_irq_postinstall(dev);
2200
2201         return 0;
2202 }
2203
2204 static int valleyview_irq_postinstall(struct drm_device *dev)
2205 {
2206         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2207         u32 enable_mask;
2208         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2209         u32 render_irqs;
2210         u16 msid;
2211
2212         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2213         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2214                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2215                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2216                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2217
2218         /*
2219          *Leave vblank interrupts masked initially.  enable/disable will
2220          * toggle them based on usage.
2221          */
2222         dev_priv->irq_mask = (~enable_mask) |
2223                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2224                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2225
2226         /* Hack for broken MSIs on VLV */
2227         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2228         pci_read_config_word(dev->pdev, 0x98, &msid);
2229         msid &= 0xff; /* mask out delivery bits */
2230         msid |= (1<<14);
2231         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2232
2233         I915_WRITE(PORT_HOTPLUG_EN, 0);
2234         POSTING_READ(PORT_HOTPLUG_EN);
2235
2236         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2237         I915_WRITE(VLV_IER, enable_mask);
2238         I915_WRITE(VLV_IIR, 0xffffffff);
2239         I915_WRITE(PIPESTAT(0), 0xffff);
2240         I915_WRITE(PIPESTAT(1), 0xffff);
2241         POSTING_READ(VLV_IER);
2242
2243         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2244         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2245         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2246
2247         I915_WRITE(VLV_IIR, 0xffffffff);
2248         I915_WRITE(VLV_IIR, 0xffffffff);
2249
2250         I915_WRITE(GTIIR, I915_READ(GTIIR));
2251         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2252
2253         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2254                 GEN6_BLITTER_USER_INTERRUPT;
2255         I915_WRITE(GTIER, render_irqs);
2256         POSTING_READ(GTIER);
2257
2258         /* ack & enable invalid PTE error interrupts */
2259 #if 0 /* FIXME: add support to irq handler for checking these bits */
2260         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2261         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2262 #endif
2263
2264         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2265
2266         return 0;
2267 }
2268
2269 static void valleyview_irq_uninstall(struct drm_device *dev)
2270 {
2271         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2272         int pipe;
2273
2274         if (!dev_priv)
2275                 return;
2276
2277         for_each_pipe(pipe)
2278                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2279
2280         I915_WRITE(HWSTAM, 0xffffffff);
2281         I915_WRITE(PORT_HOTPLUG_EN, 0);
2282         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2283         for_each_pipe(pipe)
2284                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2285         I915_WRITE(VLV_IIR, 0xffffffff);
2286         I915_WRITE(VLV_IMR, 0xffffffff);
2287         I915_WRITE(VLV_IER, 0x0);
2288         POSTING_READ(VLV_IER);
2289 }
2290
2291 static void ironlake_irq_uninstall(struct drm_device *dev)
2292 {
2293         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2294
2295         if (!dev_priv)
2296                 return;
2297
2298         I915_WRITE(HWSTAM, 0xffffffff);
2299
2300         I915_WRITE(DEIMR, 0xffffffff);
2301         I915_WRITE(DEIER, 0x0);
2302         I915_WRITE(DEIIR, I915_READ(DEIIR));
2303
2304         I915_WRITE(GTIMR, 0xffffffff);
2305         I915_WRITE(GTIER, 0x0);
2306         I915_WRITE(GTIIR, I915_READ(GTIIR));
2307
2308         I915_WRITE(SDEIMR, 0xffffffff);
2309         I915_WRITE(SDEIER, 0x0);
2310         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2311 }
2312
2313 static void i8xx_irq_preinstall(struct drm_device * dev)
2314 {
2315         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2316         int pipe;
2317
2318         atomic_set(&dev_priv->irq_received, 0);
2319
2320         for_each_pipe(pipe)
2321                 I915_WRITE(PIPESTAT(pipe), 0);
2322         I915_WRITE16(IMR, 0xffff);
2323         I915_WRITE16(IER, 0x0);
2324         POSTING_READ16(IER);
2325 }
2326
2327 static int i8xx_irq_postinstall(struct drm_device *dev)
2328 {
2329         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2330
2331         I915_WRITE16(EMR,
2332                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2333
2334         /* Unmask the interrupts that we always want on. */
2335         dev_priv->irq_mask =
2336                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2337                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2338                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2339                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2340                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2341         I915_WRITE16(IMR, dev_priv->irq_mask);
2342
2343         I915_WRITE16(IER,
2344                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2345                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2346                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2347                      I915_USER_INTERRUPT);
2348         POSTING_READ16(IER);
2349
2350         return 0;
2351 }
2352
2353 /*
2354  * Returns true when a page flip has completed.
2355  */
2356 static bool i8xx_handle_vblank(struct drm_device *dev,
2357                                int pipe, u16 iir)
2358 {
2359         drm_i915_private_t *dev_priv = dev->dev_private;
2360         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2361
2362         if (!drm_handle_vblank(dev, pipe))
2363                 return false;
2364
2365         if ((iir & flip_pending) == 0)
2366                 return false;
2367
2368         intel_prepare_page_flip(dev, pipe);
2369
2370         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2371          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2372          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2373          * the flip is completed (no longer pending). Since this doesn't raise
2374          * an interrupt per se, we watch for the change at vblank.
2375          */
2376         if (I915_READ16(ISR) & flip_pending)
2377                 return false;
2378
2379         intel_finish_page_flip(dev, pipe);
2380
2381         return true;
2382 }
2383
2384 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2385 {
2386         struct drm_device *dev = (struct drm_device *) arg;
2387         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2388         u16 iir, new_iir;
2389         u32 pipe_stats[2];
2390         unsigned long irqflags;
2391         int irq_received;
2392         int pipe;
2393         u16 flip_mask =
2394                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2395                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2396
2397         atomic_inc(&dev_priv->irq_received);
2398
2399         iir = I915_READ16(IIR);
2400         if (iir == 0)
2401                 return IRQ_NONE;
2402
2403         while (iir & ~flip_mask) {
2404                 /* Can't rely on pipestat interrupt bit in iir as it might
2405                  * have been cleared after the pipestat interrupt was received.
2406                  * It doesn't set the bit in iir again, but it still produces
2407                  * interrupts (for non-MSI).
2408                  */
2409                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2410                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2411                         i915_handle_error(dev, false);
2412
2413                 for_each_pipe(pipe) {
2414                         int reg = PIPESTAT(pipe);
2415                         pipe_stats[pipe] = I915_READ(reg);
2416
2417                         /*
2418                          * Clear the PIPE*STAT regs before the IIR
2419                          */
2420                         if (pipe_stats[pipe] & 0x8000ffff) {
2421                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2422                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2423                                                          pipe_name(pipe));
2424                                 I915_WRITE(reg, pipe_stats[pipe]);
2425                                 irq_received = 1;
2426                         }
2427                 }
2428                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2429
2430                 I915_WRITE16(IIR, iir & ~flip_mask);
2431                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2432
2433                 i915_update_dri1_breadcrumb(dev);
2434
2435                 if (iir & I915_USER_INTERRUPT)
2436                         notify_ring(dev, &dev_priv->ring[RCS]);
2437
2438                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2439                     i8xx_handle_vblank(dev, 0, iir))
2440                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2441
2442                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2443                     i8xx_handle_vblank(dev, 1, iir))
2444                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2445
2446                 iir = new_iir;
2447         }
2448
2449         return IRQ_HANDLED;
2450 }
2451
2452 static void i8xx_irq_uninstall(struct drm_device * dev)
2453 {
2454         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2455         int pipe;
2456
2457         for_each_pipe(pipe) {
2458                 /* Clear enable bits; then clear status bits */
2459                 I915_WRITE(PIPESTAT(pipe), 0);
2460                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2461         }
2462         I915_WRITE16(IMR, 0xffff);
2463         I915_WRITE16(IER, 0x0);
2464         I915_WRITE16(IIR, I915_READ16(IIR));
2465 }
2466
2467 static void i915_irq_preinstall(struct drm_device * dev)
2468 {
2469         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2470         int pipe;
2471
2472         atomic_set(&dev_priv->irq_received, 0);
2473
2474         if (I915_HAS_HOTPLUG(dev)) {
2475                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2476                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2477         }
2478
2479         I915_WRITE16(HWSTAM, 0xeffe);
2480         for_each_pipe(pipe)
2481                 I915_WRITE(PIPESTAT(pipe), 0);
2482         I915_WRITE(IMR, 0xffffffff);
2483         I915_WRITE(IER, 0x0);
2484         POSTING_READ(IER);
2485 }
2486
2487 static int i915_irq_postinstall(struct drm_device *dev)
2488 {
2489         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2490         u32 enable_mask;
2491
2492         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2493
2494         /* Unmask the interrupts that we always want on. */
2495         dev_priv->irq_mask =
2496                 ~(I915_ASLE_INTERRUPT |
2497                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2498                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2499                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2500                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2501                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2502
2503         enable_mask =
2504                 I915_ASLE_INTERRUPT |
2505                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2506                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2507                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2508                 I915_USER_INTERRUPT;
2509
2510         if (I915_HAS_HOTPLUG(dev)) {
2511                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2512                 POSTING_READ(PORT_HOTPLUG_EN);
2513
2514                 /* Enable in IER... */
2515                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2516                 /* and unmask in IMR */
2517                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2518         }
2519
2520         I915_WRITE(IMR, dev_priv->irq_mask);
2521         I915_WRITE(IER, enable_mask);
2522         POSTING_READ(IER);
2523
2524         intel_opregion_enable_asle(dev);
2525
2526         return 0;
2527 }
2528
2529 /*
2530  * Returns true when a page flip has completed.
2531  */
2532 static bool i915_handle_vblank(struct drm_device *dev,
2533                                int plane, int pipe, u32 iir)
2534 {
2535         drm_i915_private_t *dev_priv = dev->dev_private;
2536         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2537
2538         if (!drm_handle_vblank(dev, pipe))
2539                 return false;
2540
2541         if ((iir & flip_pending) == 0)
2542                 return false;
2543
2544         intel_prepare_page_flip(dev, plane);
2545
2546         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2547          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2548          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2549          * the flip is completed (no longer pending). Since this doesn't raise
2550          * an interrupt per se, we watch for the change at vblank.
2551          */
2552         if (I915_READ(ISR) & flip_pending)
2553                 return false;
2554
2555         intel_finish_page_flip(dev, pipe);
2556
2557         return true;
2558 }
2559
2560 static irqreturn_t i915_irq_handler(int irq, void *arg)
2561 {
2562         struct drm_device *dev = (struct drm_device *) arg;
2563         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2564         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2565         unsigned long irqflags;
2566         u32 flip_mask =
2567                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2568                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2569         int pipe, ret = IRQ_NONE;
2570
2571         atomic_inc(&dev_priv->irq_received);
2572
2573         iir = I915_READ(IIR);
2574         do {
2575                 bool irq_received = (iir & ~flip_mask) != 0;
2576                 bool blc_event = false;
2577
2578                 /* Can't rely on pipestat interrupt bit in iir as it might
2579                  * have been cleared after the pipestat interrupt was received.
2580                  * It doesn't set the bit in iir again, but it still produces
2581                  * interrupts (for non-MSI).
2582                  */
2583                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2584                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2585                         i915_handle_error(dev, false);
2586
2587                 for_each_pipe(pipe) {
2588                         int reg = PIPESTAT(pipe);
2589                         pipe_stats[pipe] = I915_READ(reg);
2590
2591                         /* Clear the PIPE*STAT regs before the IIR */
2592                         if (pipe_stats[pipe] & 0x8000ffff) {
2593                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2594                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2595                                                          pipe_name(pipe));
2596                                 I915_WRITE(reg, pipe_stats[pipe]);
2597                                 irq_received = true;
2598                         }
2599                 }
2600                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2601
2602                 if (!irq_received)
2603                         break;
2604
2605                 /* Consume port.  Then clear IIR or we'll miss events */
2606                 if ((I915_HAS_HOTPLUG(dev)) &&
2607                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2608                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2609
2610                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2611                                   hotplug_status);
2612                         if (hotplug_status & HOTPLUG_INT_STATUS_I915)
2613                                 queue_work(dev_priv->wq,
2614                                            &dev_priv->hotplug_work);
2615
2616                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2617                         POSTING_READ(PORT_HOTPLUG_STAT);
2618                 }
2619
2620                 I915_WRITE(IIR, iir & ~flip_mask);
2621                 new_iir = I915_READ(IIR); /* Flush posted writes */
2622
2623                 if (iir & I915_USER_INTERRUPT)
2624                         notify_ring(dev, &dev_priv->ring[RCS]);
2625
2626                 for_each_pipe(pipe) {
2627                         int plane = pipe;
2628                         if (IS_MOBILE(dev))
2629                                 plane = !plane;
2630
2631                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2632                             i915_handle_vblank(dev, plane, pipe, iir))
2633                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2634
2635                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2636                                 blc_event = true;
2637                 }
2638
2639                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2640                         intel_opregion_asle_intr(dev);
2641
2642                 /* With MSI, interrupts are only generated when iir
2643                  * transitions from zero to nonzero.  If another bit got
2644                  * set while we were handling the existing iir bits, then
2645                  * we would never get another interrupt.
2646                  *
2647                  * This is fine on non-MSI as well, as if we hit this path
2648                  * we avoid exiting the interrupt handler only to generate
2649                  * another one.
2650                  *
2651                  * Note that for MSI this could cause a stray interrupt report
2652                  * if an interrupt landed in the time between writing IIR and
2653                  * the posting read.  This should be rare enough to never
2654                  * trigger the 99% of 100,000 interrupts test for disabling
2655                  * stray interrupts.
2656                  */
2657                 ret = IRQ_HANDLED;
2658                 iir = new_iir;
2659         } while (iir & ~flip_mask);
2660
2661         i915_update_dri1_breadcrumb(dev);
2662
2663         return ret;
2664 }
2665
2666 static void i915_irq_uninstall(struct drm_device * dev)
2667 {
2668         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2669         int pipe;
2670
2671         if (I915_HAS_HOTPLUG(dev)) {
2672                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2673                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2674         }
2675
2676         I915_WRITE16(HWSTAM, 0xffff);
2677         for_each_pipe(pipe) {
2678                 /* Clear enable bits; then clear status bits */
2679                 I915_WRITE(PIPESTAT(pipe), 0);
2680                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2681         }
2682         I915_WRITE(IMR, 0xffffffff);
2683         I915_WRITE(IER, 0x0);
2684
2685         I915_WRITE(IIR, I915_READ(IIR));
2686 }
2687
2688 static void i965_irq_preinstall(struct drm_device * dev)
2689 {
2690         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2691         int pipe;
2692
2693         atomic_set(&dev_priv->irq_received, 0);
2694
2695         I915_WRITE(PORT_HOTPLUG_EN, 0);
2696         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2697
2698         I915_WRITE(HWSTAM, 0xeffe);
2699         for_each_pipe(pipe)
2700                 I915_WRITE(PIPESTAT(pipe), 0);
2701         I915_WRITE(IMR, 0xffffffff);
2702         I915_WRITE(IER, 0x0);
2703         POSTING_READ(IER);
2704 }
2705
2706 static int i965_irq_postinstall(struct drm_device *dev)
2707 {
2708         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2709         u32 enable_mask;
2710         u32 error_mask;
2711
2712         /* Unmask the interrupts that we always want on. */
2713         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2714                                I915_DISPLAY_PORT_INTERRUPT |
2715                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2716                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2717                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2718                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2719                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2720
2721         enable_mask = ~dev_priv->irq_mask;
2722         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2723                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2724         enable_mask |= I915_USER_INTERRUPT;
2725
2726         if (IS_G4X(dev))
2727                 enable_mask |= I915_BSD_USER_INTERRUPT;
2728
2729         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2730
2731         /*
2732          * Enable some error detection, note the instruction error mask
2733          * bit is reserved, so we leave it masked.
2734          */
2735         if (IS_G4X(dev)) {
2736                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2737                                GM45_ERROR_MEM_PRIV |
2738                                GM45_ERROR_CP_PRIV |
2739                                I915_ERROR_MEMORY_REFRESH);
2740         } else {
2741                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2742                                I915_ERROR_MEMORY_REFRESH);
2743         }
2744         I915_WRITE(EMR, error_mask);
2745
2746         I915_WRITE(IMR, dev_priv->irq_mask);
2747         I915_WRITE(IER, enable_mask);
2748         POSTING_READ(IER);
2749
2750         I915_WRITE(PORT_HOTPLUG_EN, 0);
2751         POSTING_READ(PORT_HOTPLUG_EN);
2752
2753         intel_opregion_enable_asle(dev);
2754
2755         return 0;
2756 }
2757
2758 static void i915_hpd_irq_setup(struct drm_device *dev)
2759 {
2760         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2761         struct drm_mode_config *mode_config = &dev->mode_config;
2762         struct intel_encoder *encoder;
2763         u32 hotplug_en;
2764
2765         if (I915_HAS_HOTPLUG(dev)) {
2766                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2767                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2768                 /* Note HDMI and DP share hotplug bits */
2769                 /* enable bits are the same for all generations */
2770                 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
2771                         hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
2772                 /* Programming the CRT detection parameters tends
2773                    to generate a spurious hotplug event about three
2774                    seconds later.  So just do it once.
2775                 */
2776                 if (IS_G4X(dev))
2777                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2778                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2779
2780                 /* Ignore TV since it's buggy */
2781                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2782         }
2783 }
2784
2785 static irqreturn_t i965_irq_handler(int irq, void *arg)
2786 {
2787         struct drm_device *dev = (struct drm_device *) arg;
2788         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2789         u32 iir, new_iir;
2790         u32 pipe_stats[I915_MAX_PIPES];
2791         unsigned long irqflags;
2792         int irq_received;
2793         int ret = IRQ_NONE, pipe;
2794         u32 flip_mask =
2795                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2796                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2797
2798         atomic_inc(&dev_priv->irq_received);
2799
2800         iir = I915_READ(IIR);
2801
2802         for (;;) {
2803                 bool blc_event = false;
2804
2805                 irq_received = (iir & ~flip_mask) != 0;
2806
2807                 /* Can't rely on pipestat interrupt bit in iir as it might
2808                  * have been cleared after the pipestat interrupt was received.
2809                  * It doesn't set the bit in iir again, but it still produces
2810                  * interrupts (for non-MSI).
2811                  */
2812                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2813                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2814                         i915_handle_error(dev, false);
2815
2816                 for_each_pipe(pipe) {
2817                         int reg = PIPESTAT(pipe);
2818                         pipe_stats[pipe] = I915_READ(reg);
2819
2820                         /*
2821                          * Clear the PIPE*STAT regs before the IIR
2822                          */
2823                         if (pipe_stats[pipe] & 0x8000ffff) {
2824                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2825                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2826                                                          pipe_name(pipe));
2827                                 I915_WRITE(reg, pipe_stats[pipe]);
2828                                 irq_received = 1;
2829                         }
2830                 }
2831                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2832
2833                 if (!irq_received)
2834                         break;
2835
2836                 ret = IRQ_HANDLED;
2837
2838                 /* Consume port.  Then clear IIR or we'll miss events */
2839                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2840                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2841
2842                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2843                                   hotplug_status);
2844                         if (hotplug_status & (IS_G4X(dev) ?
2845                                               HOTPLUG_INT_STATUS_G4X :
2846                                               HOTPLUG_INT_STATUS_I965))
2847                                 queue_work(dev_priv->wq,
2848                                            &dev_priv->hotplug_work);
2849
2850                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2851                         I915_READ(PORT_HOTPLUG_STAT);
2852                 }
2853
2854                 I915_WRITE(IIR, iir & ~flip_mask);
2855                 new_iir = I915_READ(IIR); /* Flush posted writes */
2856
2857                 if (iir & I915_USER_INTERRUPT)
2858                         notify_ring(dev, &dev_priv->ring[RCS]);
2859                 if (iir & I915_BSD_USER_INTERRUPT)
2860                         notify_ring(dev, &dev_priv->ring[VCS]);
2861
2862                 for_each_pipe(pipe) {
2863                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2864                             i915_handle_vblank(dev, pipe, pipe, iir))
2865                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2866
2867                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2868                                 blc_event = true;
2869                 }
2870
2871
2872                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2873                         intel_opregion_asle_intr(dev);
2874
2875                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2876                         gmbus_irq_handler(dev);
2877
2878                 /* With MSI, interrupts are only generated when iir
2879                  * transitions from zero to nonzero.  If another bit got
2880                  * set while we were handling the existing iir bits, then
2881                  * we would never get another interrupt.
2882                  *
2883                  * This is fine on non-MSI as well, as if we hit this path
2884                  * we avoid exiting the interrupt handler only to generate
2885                  * another one.
2886                  *
2887                  * Note that for MSI this could cause a stray interrupt report
2888                  * if an interrupt landed in the time between writing IIR and
2889                  * the posting read.  This should be rare enough to never
2890                  * trigger the 99% of 100,000 interrupts test for disabling
2891                  * stray interrupts.
2892                  */
2893                 iir = new_iir;
2894         }
2895
2896         i915_update_dri1_breadcrumb(dev);
2897
2898         return ret;
2899 }
2900
2901 static void i965_irq_uninstall(struct drm_device * dev)
2902 {
2903         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2904         int pipe;
2905
2906         if (!dev_priv)
2907                 return;
2908
2909         I915_WRITE(PORT_HOTPLUG_EN, 0);
2910         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2911
2912         I915_WRITE(HWSTAM, 0xffffffff);
2913         for_each_pipe(pipe)
2914                 I915_WRITE(PIPESTAT(pipe), 0);
2915         I915_WRITE(IMR, 0xffffffff);
2916         I915_WRITE(IER, 0x0);
2917
2918         for_each_pipe(pipe)
2919                 I915_WRITE(PIPESTAT(pipe),
2920                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2921         I915_WRITE(IIR, I915_READ(IIR));
2922 }
2923
2924 void intel_irq_init(struct drm_device *dev)
2925 {
2926         struct drm_i915_private *dev_priv = dev->dev_private;
2927
2928         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2929         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2930         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2931         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2932
2933         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2934                     i915_hangcheck_elapsed,
2935                     (unsigned long) dev);
2936
2937         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2938
2939         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2940         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2941         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2942                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2943                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2944         }
2945
2946         if (drm_core_check_feature(dev, DRIVER_MODESET))
2947                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2948         else
2949                 dev->driver->get_vblank_timestamp = NULL;
2950         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2951
2952         if (IS_VALLEYVIEW(dev)) {
2953                 dev->driver->irq_handler = valleyview_irq_handler;
2954                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2955                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2956                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2957                 dev->driver->enable_vblank = valleyview_enable_vblank;
2958                 dev->driver->disable_vblank = valleyview_disable_vblank;
2959                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2960         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2961                 /* Share pre & uninstall handlers with ILK/SNB */
2962                 dev->driver->irq_handler = ivybridge_irq_handler;
2963                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2964                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2965                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2966                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2967                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2968                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2969         } else if (HAS_PCH_SPLIT(dev)) {
2970                 dev->driver->irq_handler = ironlake_irq_handler;
2971                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2972                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2973                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2974                 dev->driver->enable_vblank = ironlake_enable_vblank;
2975                 dev->driver->disable_vblank = ironlake_disable_vblank;
2976                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
2977         } else {
2978                 if (INTEL_INFO(dev)->gen == 2) {
2979                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2980                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2981                         dev->driver->irq_handler = i8xx_irq_handler;
2982                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2983                 } else if (INTEL_INFO(dev)->gen == 3) {
2984                         dev->driver->irq_preinstall = i915_irq_preinstall;
2985                         dev->driver->irq_postinstall = i915_irq_postinstall;
2986                         dev->driver->irq_uninstall = i915_irq_uninstall;
2987                         dev->driver->irq_handler = i915_irq_handler;
2988                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2989                 } else {
2990                         dev->driver->irq_preinstall = i965_irq_preinstall;
2991                         dev->driver->irq_postinstall = i965_irq_postinstall;
2992                         dev->driver->irq_uninstall = i965_irq_uninstall;
2993                         dev->driver->irq_handler = i965_irq_handler;
2994                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2995                 }
2996                 dev->driver->enable_vblank = i915_enable_vblank;
2997                 dev->driver->disable_vblank = i915_disable_vblank;
2998         }
2999 }
3000
3001 void intel_hpd_init(struct drm_device *dev)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004
3005         if (dev_priv->display.hpd_irq_setup)
3006                 dev_priv->display.hpd_irq_setup(dev);
3007 }