Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include <drm/i915_drm.h>
  27 #include "i915_drv.h"
  28 #include "i915_trace.h"
  29 #include "intel_drv.h"
  30
  31 typedef uint32_t gen6_gtt_pte_t;
  32
  33 /* PPGTT stuff */
  34 #define GEN6_GTT_ADDR_ENCODE(addr)      ((addr) | (((addr) >> 28) & 0xff0))
  35
  36 #define GEN6_PDE_VALID                  (1 << 0)
  37 /* gen6+ has bit 11-4 for physical addr bit 39-32 */
  38 #define GEN6_PDE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  39
  40 #define GEN6_PTE_VALID                  (1 << 0)
  41 #define GEN6_PTE_UNCACHED               (1 << 1)
  42 #define HSW_PTE_UNCACHED                (0)
  43 #define GEN6_PTE_CACHE_LLC              (2 << 1)
  44 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
  45 #define GEN6_PTE_ADDR_ENCODE(addr)      GEN6_GTT_ADDR_ENCODE(addr)
  46
  47 static inline gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,
  48                                              dma_addr_t addr,
  49                                              enum i915_cache_level level)
  50 {
  51         gen6_gtt_pte_t pte = GEN6_PTE_VALID;
  52         pte |= GEN6_PTE_ADDR_ENCODE(addr);
  53
  54         switch (level) {
  55         case I915_CACHE_LLC_MLC:
  56                 /* Haswell doesn't set L3 this way */
  57                 if (IS_HASWELL(dev))
  58                         pte |= GEN6_PTE_CACHE_LLC;
  59                 else
  60                         pte |= GEN6_PTE_CACHE_LLC_MLC;
  61                 break;
  62         case I915_CACHE_LLC:
  63                 pte |= GEN6_PTE_CACHE_LLC;
  64                 break;
  65         case I915_CACHE_NONE:
  66                 if (IS_HASWELL(dev))
  67                         pte |= HSW_PTE_UNCACHED;
  68                 else
  69                         pte |= GEN6_PTE_UNCACHED;
  70                 break;
  71         default:
  72                 BUG();
  73         }
  74
  75         return pte;
  76 }
  77
  78 static void gen6_ppgtt_enable(struct drm_device *dev)
  79 {
  80         drm_i915_private_t *dev_priv = dev->dev_private;
  81         uint32_t pd_offset;
  82         struct intel_ring_buffer *ring;
  83         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
  84         gen6_gtt_pte_t __iomem *pd_addr;
  85         uint32_t pd_entry;
  86         int i;
  87
  88         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
  89                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
  90         for (i = 0; i < ppgtt->num_pd_entries; i++) {
  91                 dma_addr_t pt_addr;
  92
  93                 pt_addr = ppgtt->pt_dma_addr[i];
  94                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
  95                 pd_entry |= GEN6_PDE_VALID;
  96
  97                 writel(pd_entry, pd_addr + i);
  98         }
  99         readl(pd_addr);
 100
 101         pd_offset = ppgtt->pd_offset;
 102         pd_offset /= 64; /* in cachelines, */
 103         pd_offset <<= 16;
 104
 105         if (INTEL_INFO(dev)->gen == 6) {
 106                 uint32_t ecochk, gab_ctl, ecobits;
 107
 108                 ecobits = I915_READ(GAC_ECO_BITS);
 109                 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 110
 111                 gab_ctl = I915_READ(GAB_CTL);
 112                 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 113
 114                 ecochk = I915_READ(GAM_ECOCHK);
 115                 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
 116                                        ECOCHK_PPGTT_CACHE64B);
 117                 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 118         } else if (INTEL_INFO(dev)->gen >= 7) {
 119                 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
 120                 /* GFX_MODE is per-ring on gen7+ */
 121         }
 122
 123         for_each_ring(ring, dev_priv, i) {
 124                 if (INTEL_INFO(dev)->gen >= 7)
 125                         I915_WRITE(RING_MODE_GEN7(ring),
 126                                    _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 127
 128                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 129                 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
 130         }
 131 }
 132
 133 /* PPGTT support for Sandybdrige/Gen6 and later */
 134 static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
 135                                    unsigned first_entry,
 136                                    unsigned num_entries)
 137 {
 138         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 139         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 140         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 141         unsigned last_pte, i;
 142
 143         scratch_pte = gen6_pte_encode(ppgtt->dev,
 144                                       ppgtt->scratch_page_dma_addr,
 145                                       I915_CACHE_LLC);
 146
 147         while (num_entries) {
 148                 last_pte = first_pte + num_entries;
 149                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 150                         last_pte = I915_PPGTT_PT_ENTRIES;
 151
 152                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 153
 154                 for (i = first_pte; i < last_pte; i++)
 155                         pt_vaddr[i] = scratch_pte;
 156
 157                 kunmap_atomic(pt_vaddr);
 158
 159                 num_entries -= last_pte - first_pte;
 160                 first_pte = 0;
 161                 act_pt++;
 162         }
 163 }
 164
 165 static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
 166                                       struct sg_table *pages,
 167                                       unsigned first_entry,
 168                                       enum i915_cache_level cache_level)
 169 {
 170         gen6_gtt_pte_t *pt_vaddr;
 171         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 172         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 173         struct sg_page_iter sg_iter;
 174
 175         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 176         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 177                 dma_addr_t page_addr;
 178
 179                 page_addr = sg_page_iter_dma_address(&sg_iter);
 180                 pt_vaddr[act_pte] = gen6_pte_encode(ppgtt->dev, page_addr,
 181                                                     cache_level);
 182                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 183                         kunmap_atomic(pt_vaddr);
 184                         act_pt++;
 185                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 186                         act_pte = 0;
 187
 188                 }
 189         }
 190         kunmap_atomic(pt_vaddr);
 191 }
 192
 193 static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
 194 {
 195         int i;
 196
 197         if (ppgtt->pt_dma_addr) {
 198                 for (i = 0; i < ppgtt->num_pd_entries; i++)
 199                         pci_unmap_page(ppgtt->dev->pdev,
 200                                        ppgtt->pt_dma_addr[i],
 201                                        4096, PCI_DMA_BIDIRECTIONAL);
 202         }
 203
 204         kfree(ppgtt->pt_dma_addr);
 205         for (i = 0; i < ppgtt->num_pd_entries; i++)
 206                 __free_page(ppgtt->pt_pages[i]);
 207         kfree(ppgtt->pt_pages);
 208         kfree(ppgtt);
 209 }
 210
 211 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 212 {
 213         struct drm_device *dev = ppgtt->dev;
 214         struct drm_i915_private *dev_priv = dev->dev_private;
 215         unsigned first_pd_entry_in_global_pt;
 216         int i;
 217         int ret = -ENOMEM;
 218
 219         /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
 220          * entries. For aliasing ppgtt support we just steal them at the end for
 221          * now. */
 222         first_pd_entry_in_global_pt =
 223                 gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 224
 225         ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
 226         ppgtt->enable = gen6_ppgtt_enable;
 227         ppgtt->clear_range = gen6_ppgtt_clear_range;
 228         ppgtt->insert_entries = gen6_ppgtt_insert_entries;
 229         ppgtt->cleanup = gen6_ppgtt_cleanup;
 230         ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
 231                                   GFP_KERNEL);
 232         if (!ppgtt->pt_pages)
 233                 return -ENOMEM;
 234
 235         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 236                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
 237                 if (!ppgtt->pt_pages[i])
 238                         goto err_pt_alloc;
 239         }
 240
 241         ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
 242                                      GFP_KERNEL);
 243         if (!ppgtt->pt_dma_addr)
 244                 goto err_pt_alloc;
 245
 246         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 247                 dma_addr_t pt_addr;
 248
 249                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
 250                                        PCI_DMA_BIDIRECTIONAL);
 251
 252                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
 253                         ret = -EIO;
 254                         goto err_pd_pin;
 255
 256                 }
 257                 ppgtt->pt_dma_addr[i] = pt_addr;
 258         }
 259
 260         ppgtt->clear_range(ppgtt, 0,
 261                            ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
 262
 263         ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
 264
 265         return 0;
 266
 267 err_pd_pin:
 268         if (ppgtt->pt_dma_addr) {
 269                 for (i--; i >= 0; i--)
 270                         pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
 271                                        4096, PCI_DMA_BIDIRECTIONAL);
 272         }
 273 err_pt_alloc:
 274         kfree(ppgtt->pt_dma_addr);
 275         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 276                 if (ppgtt->pt_pages[i])
 277                         __free_page(ppgtt->pt_pages[i]);
 278         }
 279         kfree(ppgtt->pt_pages);
 280
 281         return ret;
 282 }
 283
 284 static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
 285 {
 286         struct drm_i915_private *dev_priv = dev->dev_private;
 287         struct i915_hw_ppgtt *ppgtt;
 288         int ret;
 289
 290         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 291         if (!ppgtt)
 292                 return -ENOMEM;
 293
 294         ppgtt->dev = dev;
 295         ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
 296
 297         if (INTEL_INFO(dev)->gen < 8)
 298                 ret = gen6_ppgtt_init(ppgtt);
 299         else
 300                 BUG();
 301
 302         if (ret)
 303                 kfree(ppgtt);
 304         else
 305                 dev_priv->mm.aliasing_ppgtt = ppgtt;
 306
 307         return ret;
 308 }
 309
 310 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
 311 {
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 314
 315         if (!ppgtt)
 316                 return;
 317
 318         ppgtt->cleanup(ppgtt);
 319         dev_priv->mm.aliasing_ppgtt = NULL;
 320 }
 321
 322 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
 323                             struct drm_i915_gem_object *obj,
 324                             enum i915_cache_level cache_level)
 325 {
 326         ppgtt->insert_entries(ppgtt, obj->pages,
 327                               obj->gtt_space->start >> PAGE_SHIFT,
 328                               cache_level);
 329 }
 330
 331 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
 332                               struct drm_i915_gem_object *obj)
 333 {
 334         ppgtt->clear_range(ppgtt,
 335                            obj->gtt_space->start >> PAGE_SHIFT,
 336                            obj->base.size >> PAGE_SHIFT);
 337 }
 338
 339 extern int intel_iommu_gfx_mapped;
 340 /* Certain Gen5 chipsets require require idling the GPU before
 341  * unmapping anything from the GTT when VT-d is enabled.
 342  */
 343 static inline bool needs_idle_maps(struct drm_device *dev)
 344 {
 345 #ifdef CONFIG_INTEL_IOMMU
 346         /* Query intel_iommu to see if we need the workaround. Presumably that
 347          * was loaded first.
 348          */
 349         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 350                 return true;
 351 #endif
 352         return false;
 353 }
 354
 355 static bool do_idling(struct drm_i915_private *dev_priv)
 356 {
 357         bool ret = dev_priv->mm.interruptible;
 358
 359         if (unlikely(dev_priv->gtt.do_idle_maps)) {
 360                 dev_priv->mm.interruptible = false;
 361                 if (i915_gpu_idle(dev_priv->dev)) {
 362                         DRM_ERROR("Couldn't idle GPU\n");
 363                         /* Wait a bit, in hopes it avoids the hang */
 364                         udelay(10);
 365                 }
 366         }
 367
 368         return ret;
 369 }
 370
 371 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
 372 {
 373         if (unlikely(dev_priv->gtt.do_idle_maps))
 374                 dev_priv->mm.interruptible = interruptible;
 375 }
 376
 377 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 378 {
 379         struct drm_i915_private *dev_priv = dev->dev_private;
 380         struct drm_i915_gem_object *obj;
 381
 382         /* First fill our portion of the GTT with scratch pages */
 383         dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
 384                                       dev_priv->gtt.total / PAGE_SIZE);
 385
 386         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 387                 i915_gem_clflush_object(obj);
 388                 i915_gem_gtt_bind_object(obj, obj->cache_level);
 389         }
 390
 391         i915_gem_chipset_flush(dev);
 392 }
 393
 394 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
 395 {
 396         if (obj->has_dma_mapping)
 397                 return 0;
 398
 399         if (!dma_map_sg(&obj->base.dev->pdev->dev,
 400                         obj->pages->sgl, obj->pages->nents,
 401                         PCI_DMA_BIDIRECTIONAL))
 402                 return -ENOSPC;
 403
 404         return 0;
 405 }
 406
 407 /*
 408  * Binds an object into the global gtt with the specified cache level. The object
 409  * will be accessible to the GPU via commands whose operands reference offsets
 410  * within the global GTT as well as accessible by the GPU through the GMADR
 411  * mapped BAR (dev_priv->mm.gtt->gtt).
 412  */
 413 static void gen6_ggtt_insert_entries(struct drm_device *dev,
 414                                      struct sg_table *st,
 415                                      unsigned int first_entry,
 416                                      enum i915_cache_level level)
 417 {
 418         struct drm_i915_private *dev_priv = dev->dev_private;
 419         gen6_gtt_pte_t __iomem *gtt_entries =
 420                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 421         int i = 0;
 422         struct sg_page_iter sg_iter;
 423         dma_addr_t addr;
 424
 425         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 426                 addr = sg_page_iter_dma_address(&sg_iter);
 427                 iowrite32(gen6_pte_encode(dev, addr, level), &gtt_entries[i]);
 428                 i++;
 429         }
 430
 431         /* XXX: This serves as a posting read to make sure that the PTE has
 432          * actually been updated. There is some concern that even though
 433          * registers and PTEs are within the same BAR that they are potentially
 434          * of NUMA access patterns. Therefore, even with the way we assume
 435          * hardware should work, we must keep this posting read for paranoia.
 436          */
 437         if (i != 0)
 438                 WARN_ON(readl(&gtt_entries[i-1])
 439                         != gen6_pte_encode(dev, addr, level));
 440
 441         /* This next bit makes the above posting read even more important. We
 442          * want to flush the TLBs only after we're certain all the PTE updates
 443          * have finished.
 444          */
 445         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 446         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 447 }
 448
 449 static void gen6_ggtt_clear_range(struct drm_device *dev,
 450                                   unsigned int first_entry,
 451                                   unsigned int num_entries)
 452 {
 453         struct drm_i915_private *dev_priv = dev->dev_private;
 454         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
 455                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 456         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 457         int i;
 458
 459         if (WARN(num_entries > max_entries,
 460                  "First entry = %d; Num entries = %d (max=%d)\n",
 461                  first_entry, num_entries, max_entries))
 462                 num_entries = max_entries;
 463
 464         scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
 465                                       I915_CACHE_LLC);
 466         for (i = 0; i < num_entries; i++)
 467                 iowrite32(scratch_pte, &gtt_base[i]);
 468         readl(gtt_base);
 469 }
 470
 471
 472 static void i915_ggtt_insert_entries(struct drm_device *dev,
 473                                      struct sg_table *st,
 474                                      unsigned int pg_start,
 475                                      enum i915_cache_level cache_level)
 476 {
 477         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 478                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 479
 480         intel_gtt_insert_sg_entries(st, pg_start, flags);
 481
 482 }
 483
 484 static void i915_ggtt_clear_range(struct drm_device *dev,
 485                                   unsigned int first_entry,
 486                                   unsigned int num_entries)
 487 {
 488         intel_gtt_clear_range(first_entry, num_entries);
 489 }
 490
 491
 492 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
 493                               enum i915_cache_level cache_level)
 494 {
 495         struct drm_device *dev = obj->base.dev;
 496         struct drm_i915_private *dev_priv = dev->dev_private;
 497
 498         dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
 499                                          obj->gtt_space->start >> PAGE_SHIFT,
 500                                          cache_level);
 501
 502         obj->has_global_gtt_mapping = 1;
 503 }
 504
 505 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
 506 {
 507         struct drm_device *dev = obj->base.dev;
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509
 510         dev_priv->gtt.gtt_clear_range(obj->base.dev,
 511                                       obj->gtt_space->start >> PAGE_SHIFT,
 512                                       obj->base.size >> PAGE_SHIFT);
 513
 514         obj->has_global_gtt_mapping = 0;
 515 }
 516
 517 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
 518 {
 519         struct drm_device *dev = obj->base.dev;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         bool interruptible;
 522
 523         interruptible = do_idling(dev_priv);
 524
 525         if (!obj->has_dma_mapping)
 526                 dma_unmap_sg(&dev->pdev->dev,
 527                              obj->pages->sgl, obj->pages->nents,
 528                              PCI_DMA_BIDIRECTIONAL);
 529
 530         undo_idling(dev_priv, interruptible);
 531 }
 532
 533 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 534                                   unsigned long color,
 535                                   unsigned long *start,
 536                                   unsigned long *end)
 537 {
 538         if (node->color != color)
 539                 *start += 4096;
 540
 541         if (!list_empty(&node->node_list)) {
 542                 node = list_entry(node->node_list.next,
 543                                   struct drm_mm_node,
 544                                   node_list);
 545                 if (node->allocated && node->color != color)
 546                         *end -= 4096;
 547         }
 548 }
 549 void i915_gem_setup_global_gtt(struct drm_device *dev,
 550                                unsigned long start,
 551                                unsigned long mappable_end,
 552                                unsigned long end)
 553 {
 554         /* Let GEM Manage all of the aperture.
 555          *
 556          * However, leave one page at the end still bound to the scratch page.
 557          * There are a number of places where the hardware apparently prefetches
 558          * past the end of the object, and we've seen multiple hangs with the
 559          * GPU head pointer stuck in a batchbuffer bound at the last page of the
 560          * aperture.  One page should be enough to keep any prefetching inside
 561          * of the aperture.
 562          */
 563         drm_i915_private_t *dev_priv = dev->dev_private;
 564         struct drm_mm_node *entry;
 565         struct drm_i915_gem_object *obj;
 566         unsigned long hole_start, hole_end;
 567
 568         BUG_ON(mappable_end > end);
 569
 570         /* Subtract the guard page ... */
 571         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
 572         if (!HAS_LLC(dev))
 573                 dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust;
 574
 575         /* Mark any preallocated objects as occupied */
 576         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
 577                 DRM_DEBUG_KMS("reserving preallocated space: %x + %zx\n",
 578                               obj->gtt_offset, obj->base.size);
 579
 580                 BUG_ON(obj->gtt_space != I915_GTT_RESERVED);
 581                 obj->gtt_space = drm_mm_create_block(&dev_priv->mm.gtt_space,
 582                                                      obj->gtt_offset,
 583                                                      obj->base.size,
 584                                                      false);
 585                 obj->has_global_gtt_mapping = 1;
 586         }
 587
 588         dev_priv->gtt.start = start;
 589         dev_priv->gtt.total = end - start;
 590
 591         /* Clear any non-preallocated blocks */
 592         drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
 593                              hole_start, hole_end) {
 594                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 595                               hole_start, hole_end);
 596                 dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
 597                                               (hole_end-hole_start) / PAGE_SIZE);
 598         }
 599
 600         /* And finally clear the reserved guard page */
 601         dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
 602 }
 603
 604 static bool
 605 intel_enable_ppgtt(struct drm_device *dev)
 606 {
 607         if (i915_enable_ppgtt >= 0)
 608                 return i915_enable_ppgtt;
 609
 610 #ifdef CONFIG_INTEL_IOMMU
 611         /* Disable ppgtt on SNB if VT-d is on. */
 612         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 613                 return false;
 614 #endif
 615
 616         return true;
 617 }
 618
 619 void i915_gem_init_global_gtt(struct drm_device *dev)
 620 {
 621         struct drm_i915_private *dev_priv = dev->dev_private;
 622         unsigned long gtt_size, mappable_size;
 623
 624         gtt_size = dev_priv->gtt.total;
 625         mappable_size = dev_priv->gtt.mappable_end;
 626
 627         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 628                 int ret;
 629
 630                 if (INTEL_INFO(dev)->gen <= 7) {
 631                         /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 632                          * aperture accordingly when using aliasing ppgtt. */
 633                         gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 634                 }
 635
 636                 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 637
 638                 ret = i915_gem_init_aliasing_ppgtt(dev);
 639                 if (!ret)
 640                         return;
 641
 642                 DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
 643                 drm_mm_takedown(&dev_priv->mm.gtt_space);
 644                 gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 645         }
 646         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
 647 }
 648
 649 static int setup_scratch_page(struct drm_device *dev)
 650 {
 651         struct drm_i915_private *dev_priv = dev->dev_private;
 652         struct page *page;
 653         dma_addr_t dma_addr;
 654
 655         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 656         if (page == NULL)
 657                 return -ENOMEM;
 658         get_page(page);
 659         set_pages_uc(page, 1);
 660
 661 #ifdef CONFIG_INTEL_IOMMU
 662         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
 663                                 PCI_DMA_BIDIRECTIONAL);
 664         if (pci_dma_mapping_error(dev->pdev, dma_addr))
 665                 return -EINVAL;
 666 #else
 667         dma_addr = page_to_phys(page);
 668 #endif
 669         dev_priv->gtt.scratch_page = page;
 670         dev_priv->gtt.scratch_page_dma = dma_addr;
 671
 672         return 0;
 673 }
 674
 675 static void teardown_scratch_page(struct drm_device *dev)
 676 {
 677         struct drm_i915_private *dev_priv = dev->dev_private;
 678         set_pages_wb(dev_priv->gtt.scratch_page, 1);
 679         pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
 680                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 681         put_page(dev_priv->gtt.scratch_page);
 682         __free_page(dev_priv->gtt.scratch_page);
 683 }
 684
 685 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
 686 {
 687         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 688         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 689         return snb_gmch_ctl << 20;
 690 }
 691
 692 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
 693 {
 694         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 695         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 696         return snb_gmch_ctl << 25; /* 32 MB units */
 697 }
 698
 699 static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
 700 {
 701         static const int stolen_decoder[] = {
 702                 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
 703         snb_gmch_ctl >>= IVB_GMCH_GMS_SHIFT;
 704         snb_gmch_ctl &= IVB_GMCH_GMS_MASK;
 705         return stolen_decoder[snb_gmch_ctl] << 20;
 706 }
 707
 708 static int gen6_gmch_probe(struct drm_device *dev,
 709                            size_t *gtt_total,
 710                            size_t *stolen,
 711                            phys_addr_t *mappable_base,
 712                            unsigned long *mappable_end)
 713 {
 714         struct drm_i915_private *dev_priv = dev->dev_private;
 715         phys_addr_t gtt_bus_addr;
 716         unsigned int gtt_size;
 717         u16 snb_gmch_ctl;
 718         int ret;
 719
 720         *mappable_base = pci_resource_start(dev->pdev, 2);
 721         *mappable_end = pci_resource_len(dev->pdev, 2);
 722
 723         /* 64/512MB is the current min/max we actually know of, but this is just
 724          * a coarse sanity check.
 725          */
 726         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 727                 DRM_ERROR("Unknown GMADR size (%lx)\n",
 728                           dev_priv->gtt.mappable_end);
 729                 return -ENXIO;
 730         }
 731
 732         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 733                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 734         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 735         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 736
 737         if (IS_GEN7(dev) && !IS_VALLEYVIEW(dev))
 738                 *stolen = gen7_get_stolen_size(snb_gmch_ctl);
 739         else
 740                 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
 741
 742         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
 743
 744         /* For Modern GENs the PTEs and register space are split in the BAR */
 745         gtt_bus_addr = pci_resource_start(dev->pdev, 0) +
 746                 (pci_resource_len(dev->pdev, 0) / 2);
 747
 748         dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
 749         if (!dev_priv->gtt.gsm) {
 750                 DRM_ERROR("Failed to map the gtt page table\n");
 751                 return -ENOMEM;
 752         }
 753
 754         ret = setup_scratch_page(dev);
 755         if (ret)
 756                 DRM_ERROR("Scratch setup failed\n");
 757
 758         dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
 759         dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
 760
 761         return ret;
 762 }
 763
 764 static void gen6_gmch_remove(struct drm_device *dev)
 765 {
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         iounmap(dev_priv->gtt.gsm);
 768         teardown_scratch_page(dev_priv->dev);
 769 }
 770
 771 static int i915_gmch_probe(struct drm_device *dev,
 772                            size_t *gtt_total,
 773                            size_t *stolen,
 774                            phys_addr_t *mappable_base,
 775                            unsigned long *mappable_end)
 776 {
 777         struct drm_i915_private *dev_priv = dev->dev_private;
 778         int ret;
 779
 780         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 781         if (!ret) {
 782                 DRM_ERROR("failed to set up gmch\n");
 783                 return -EIO;
 784         }
 785
 786         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 787
 788         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 789         dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
 790         dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
 791
 792         return 0;
 793 }
 794
 795 static void i915_gmch_remove(struct drm_device *dev)
 796 {
 797         intel_gmch_remove();
 798 }
 799
 800 int i915_gem_gtt_init(struct drm_device *dev)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         struct i915_gtt *gtt = &dev_priv->gtt;
 804         unsigned long gtt_size;
 805         int ret;
 806
 807         if (INTEL_INFO(dev)->gen <= 5) {
 808                 dev_priv->gtt.gtt_probe = i915_gmch_probe;
 809                 dev_priv->gtt.gtt_remove = i915_gmch_remove;
 810         } else {
 811                 dev_priv->gtt.gtt_probe = gen6_gmch_probe;
 812                 dev_priv->gtt.gtt_remove = gen6_gmch_remove;
 813         }
 814
 815         ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
 816                                      &dev_priv->gtt.stolen_size,
 817                                      &gtt->mappable_base,
 818                                      &gtt->mappable_end);
 819         if (ret)
 820                 return ret;
 821
 822         gtt_size = (dev_priv->gtt.total >> PAGE_SHIFT) * sizeof(gen6_gtt_pte_t);
 823
 824         /* GMADR is the PCI mmio aperture into the global GTT. */
 825         DRM_INFO("Memory usable by graphics device = %zdM\n",
 826                  dev_priv->gtt.total >> 20);
 827         DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
 828                          dev_priv->gtt.mappable_end >> 20);
 829         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
 830                          dev_priv->gtt.stolen_size >> 20);
 831
 832         return 0;
 833 }