2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
39 static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 bool map_and_fenceable);
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
60 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
63 i915_gem_release_mmap(obj);
65 /* As we do not have an associated fence register, we will force
66 * a tiling change if we ever need to acquire one.
68 obj->fence_dirty = false;
69 obj->fence_reg = I915_FENCE_REG_NONE;
72 /* some bookkeeping */
73 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
76 dev_priv->mm.object_count++;
77 dev_priv->mm.object_memory += size;
80 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
83 dev_priv->mm.object_count--;
84 dev_priv->mm.object_memory -= size;
88 i915_gem_wait_for_error(struct drm_device *dev)
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 struct completion *x = &dev_priv->error_completion;
95 if (!atomic_read(&dev_priv->mm.wedged))
98 ret = wait_for_completion_interruptible(x);
102 if (atomic_read(&dev_priv->mm.wedged)) {
103 /* GPU is hung, bump the completion count to account for
104 * the token we just consumed so that we never hit zero and
105 * end up waiting upon a subsequent completion event that
108 spin_lock_irqsave(&x->wait.lock, flags);
110 spin_unlock_irqrestore(&x->wait.lock, flags);
115 int i915_mutex_lock_interruptible(struct drm_device *dev)
119 ret = i915_gem_wait_for_error(dev);
123 ret = mutex_lock_interruptible(&dev->struct_mutex);
127 WARN_ON(i915_verify_lists(dev));
132 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
138 i915_gem_init_ioctl(struct drm_device *dev, void *data,
139 struct drm_file *file)
141 struct drm_i915_gem_init *args = data;
143 if (drm_core_check_feature(dev, DRIVER_MODESET))
146 if (args->gtt_start >= args->gtt_end ||
147 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
150 /* GEM with user mode setting was never supported on ilk and later. */
151 if (INTEL_INFO(dev)->gen >= 5)
154 mutex_lock(&dev->struct_mutex);
155 i915_gem_init_global_gtt(dev, args->gtt_start,
156 args->gtt_end, args->gtt_end);
157 mutex_unlock(&dev->struct_mutex);
163 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_get_aperture *args = data;
168 struct drm_i915_gem_object *obj;
172 mutex_lock(&dev->struct_mutex);
173 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
175 pinned += obj->gtt_space->size;
176 mutex_unlock(&dev->struct_mutex);
178 args->aper_size = dev_priv->mm.gtt_total;
179 args->aper_available_size = args->aper_size - pinned;
185 i915_gem_create(struct drm_file *file,
186 struct drm_device *dev,
190 struct drm_i915_gem_object *obj;
194 size = roundup(size, PAGE_SIZE);
198 /* Allocate the new object */
199 obj = i915_gem_alloc_object(dev, size);
203 ret = drm_gem_handle_create(file, &obj->base, &handle);
205 drm_gem_object_release(&obj->base);
206 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
211 /* drop reference from allocate - handle holds it now */
212 drm_gem_object_unreference(&obj->base);
213 trace_i915_gem_object_create(obj);
220 i915_gem_dumb_create(struct drm_file *file,
221 struct drm_device *dev,
222 struct drm_mode_create_dumb *args)
224 /* have to work out size/pitch and return them */
225 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
226 args->size = args->pitch * args->height;
227 return i915_gem_create(file, dev,
228 args->size, &args->handle);
231 int i915_gem_dumb_destroy(struct drm_file *file,
232 struct drm_device *dev,
235 return drm_gem_handle_delete(file, handle);
239 * Creates a new mm object and returns a handle to it.
242 i915_gem_create_ioctl(struct drm_device *dev, void *data,
243 struct drm_file *file)
245 struct drm_i915_gem_create *args = data;
247 return i915_gem_create(file, dev,
248 args->size, &args->handle);
251 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
253 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
255 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
256 obj->tiling_mode != I915_TILING_NONE;
260 __copy_to_user_swizzled(char __user *cpu_vaddr,
261 const char *gpu_vaddr, int gpu_offset,
264 int ret, cpu_offset = 0;
267 int cacheline_end = ALIGN(gpu_offset + 1, 64);
268 int this_length = min(cacheline_end - gpu_offset, length);
269 int swizzled_gpu_offset = gpu_offset ^ 64;
271 ret = __copy_to_user(cpu_vaddr + cpu_offset,
272 gpu_vaddr + swizzled_gpu_offset,
277 cpu_offset += this_length;
278 gpu_offset += this_length;
279 length -= this_length;
286 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
287 const char __user *cpu_vaddr,
290 int ret, cpu_offset = 0;
293 int cacheline_end = ALIGN(gpu_offset + 1, 64);
294 int this_length = min(cacheline_end - gpu_offset, length);
295 int swizzled_gpu_offset = gpu_offset ^ 64;
297 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
298 cpu_vaddr + cpu_offset,
303 cpu_offset += this_length;
304 gpu_offset += this_length;
305 length -= this_length;
311 /* Per-page copy function for the shmem pread fastpath.
312 * Flushes invalid cachelines before reading the target if
313 * needs_clflush is set. */
315 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
316 char __user *user_data,
317 bool page_do_bit17_swizzling, bool needs_clflush)
322 if (unlikely(page_do_bit17_swizzling))
325 vaddr = kmap_atomic(page);
327 drm_clflush_virt_range(vaddr + shmem_page_offset,
329 ret = __copy_to_user_inatomic(user_data,
330 vaddr + shmem_page_offset,
332 kunmap_atomic(vaddr);
338 shmem_clflush_swizzled_range(char *addr, unsigned long length,
341 if (unlikely(swizzled)) {
342 unsigned long start = (unsigned long) addr;
343 unsigned long end = (unsigned long) addr + length;
345 /* For swizzling simply ensure that we always flush both
346 * channels. Lame, but simple and it works. Swizzled
347 * pwrite/pread is far from a hotpath - current userspace
348 * doesn't use it at all. */
349 start = round_down(start, 128);
350 end = round_up(end, 128);
352 drm_clflush_virt_range((void *)start, end - start);
354 drm_clflush_virt_range(addr, length);
359 /* Only difference to the fast-path function is that this can handle bit17
360 * and uses non-atomic copy and kmap functions. */
362 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
363 char __user *user_data,
364 bool page_do_bit17_swizzling, bool needs_clflush)
371 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
373 page_do_bit17_swizzling);
375 if (page_do_bit17_swizzling)
376 ret = __copy_to_user_swizzled(user_data,
377 vaddr, shmem_page_offset,
380 ret = __copy_to_user(user_data,
381 vaddr + shmem_page_offset,
389 i915_gem_shmem_pread(struct drm_device *dev,
390 struct drm_i915_gem_object *obj,
391 struct drm_i915_gem_pread *args,
392 struct drm_file *file)
394 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
395 char __user *user_data;
398 int shmem_page_offset, page_length, ret = 0;
399 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
400 int hit_slowpath = 0;
402 int needs_clflush = 0;
405 user_data = (char __user *) (uintptr_t) args->data_ptr;
408 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
410 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
411 /* If we're not in the cpu read domain, set ourself into the gtt
412 * read domain and manually flush cachelines (if required). This
413 * optimizes for the case when the gpu will dirty the data
414 * anyway again before the next pread happens. */
415 if (obj->cache_level == I915_CACHE_NONE)
417 ret = i915_gem_object_set_to_gtt_domain(obj, false);
422 offset = args->offset;
427 /* Operation in this page
429 * shmem_page_offset = offset within page in shmem file
430 * page_length = bytes to copy for this page
432 shmem_page_offset = offset_in_page(offset);
433 page_length = remain;
434 if ((shmem_page_offset + page_length) > PAGE_SIZE)
435 page_length = PAGE_SIZE - shmem_page_offset;
438 page = obj->pages[offset >> PAGE_SHIFT];
441 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
449 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
450 (page_to_phys(page) & (1 << 17)) != 0;
452 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
453 user_data, page_do_bit17_swizzling,
459 page_cache_get(page);
460 mutex_unlock(&dev->struct_mutex);
463 ret = fault_in_multipages_writeable(user_data, remain);
464 /* Userspace is tricking us, but we've already clobbered
465 * its pages with the prefault and promised to write the
466 * data up to the first fault. Hence ignore any errors
467 * and just continue. */
472 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
473 user_data, page_do_bit17_swizzling,
476 mutex_lock(&dev->struct_mutex);
477 page_cache_release(page);
479 mark_page_accessed(page);
481 page_cache_release(page);
488 remain -= page_length;
489 user_data += page_length;
490 offset += page_length;
495 /* Fixup: Kill any reinstated backing storage pages */
496 if (obj->madv == __I915_MADV_PURGED)
497 i915_gem_object_truncate(obj);
504 * Reads data from the object referenced by handle.
506 * On error, the contents of *data are undefined.
509 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
510 struct drm_file *file)
512 struct drm_i915_gem_pread *args = data;
513 struct drm_i915_gem_object *obj;
519 if (!access_ok(VERIFY_WRITE,
520 (char __user *)(uintptr_t)args->data_ptr,
524 ret = i915_mutex_lock_interruptible(dev);
528 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
529 if (&obj->base == NULL) {
534 /* Bounds check source. */
535 if (args->offset > obj->base.size ||
536 args->size > obj->base.size - args->offset) {
541 trace_i915_gem_object_pread(obj, args->offset, args->size);
543 ret = i915_gem_shmem_pread(dev, obj, args, file);
546 drm_gem_object_unreference(&obj->base);
548 mutex_unlock(&dev->struct_mutex);
552 /* This is the fast write path which cannot handle
553 * page faults in the source data
557 fast_user_write(struct io_mapping *mapping,
558 loff_t page_base, int page_offset,
559 char __user *user_data,
562 void __iomem *vaddr_atomic;
564 unsigned long unwritten;
566 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
567 /* We can use the cpu mem copy function because this is X86. */
568 vaddr = (void __force*)vaddr_atomic + page_offset;
569 unwritten = __copy_from_user_inatomic_nocache(vaddr,
571 io_mapping_unmap_atomic(vaddr_atomic);
576 * This is the fast pwrite path, where we copy the data directly from the
577 * user into the GTT, uncached.
580 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
581 struct drm_i915_gem_object *obj,
582 struct drm_i915_gem_pwrite *args,
583 struct drm_file *file)
585 drm_i915_private_t *dev_priv = dev->dev_private;
587 loff_t offset, page_base;
588 char __user *user_data;
589 int page_offset, page_length, ret;
591 ret = i915_gem_object_pin(obj, 0, true);
595 ret = i915_gem_object_set_to_gtt_domain(obj, true);
599 ret = i915_gem_object_put_fence(obj);
603 user_data = (char __user *) (uintptr_t) args->data_ptr;
606 offset = obj->gtt_offset + args->offset;
609 /* Operation in this page
611 * page_base = page offset within aperture
612 * page_offset = offset within page
613 * page_length = bytes to copy for this page
615 page_base = offset & PAGE_MASK;
616 page_offset = offset_in_page(offset);
617 page_length = remain;
618 if ((page_offset + remain) > PAGE_SIZE)
619 page_length = PAGE_SIZE - page_offset;
621 /* If we get a fault while copying data, then (presumably) our
622 * source page isn't available. Return the error and we'll
623 * retry in the slow path.
625 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
626 page_offset, user_data, page_length)) {
631 remain -= page_length;
632 user_data += page_length;
633 offset += page_length;
637 i915_gem_object_unpin(obj);
642 /* Per-page copy function for the shmem pwrite fastpath.
643 * Flushes invalid cachelines before writing to the target if
644 * needs_clflush_before is set and flushes out any written cachelines after
645 * writing if needs_clflush is set. */
647 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
648 char __user *user_data,
649 bool page_do_bit17_swizzling,
650 bool needs_clflush_before,
651 bool needs_clflush_after)
656 if (unlikely(page_do_bit17_swizzling))
659 vaddr = kmap_atomic(page);
660 if (needs_clflush_before)
661 drm_clflush_virt_range(vaddr + shmem_page_offset,
663 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
666 if (needs_clflush_after)
667 drm_clflush_virt_range(vaddr + shmem_page_offset,
669 kunmap_atomic(vaddr);
674 /* Only difference to the fast-path function is that this can handle bit17
675 * and uses non-atomic copy and kmap functions. */
677 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
678 char __user *user_data,
679 bool page_do_bit17_swizzling,
680 bool needs_clflush_before,
681 bool needs_clflush_after)
687 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
688 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
690 page_do_bit17_swizzling);
691 if (page_do_bit17_swizzling)
692 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
696 ret = __copy_from_user(vaddr + shmem_page_offset,
699 if (needs_clflush_after)
700 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
702 page_do_bit17_swizzling);
709 i915_gem_shmem_pwrite(struct drm_device *dev,
710 struct drm_i915_gem_object *obj,
711 struct drm_i915_gem_pwrite *args,
712 struct drm_file *file)
714 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
717 char __user *user_data;
718 int shmem_page_offset, page_length, ret = 0;
719 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
720 int hit_slowpath = 0;
721 int needs_clflush_after = 0;
722 int needs_clflush_before = 0;
725 user_data = (char __user *) (uintptr_t) args->data_ptr;
728 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
730 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
731 /* If we're not in the cpu write domain, set ourself into the gtt
732 * write domain and manually flush cachelines (if required). This
733 * optimizes for the case when the gpu will use the data
734 * right away and we therefore have to clflush anyway. */
735 if (obj->cache_level == I915_CACHE_NONE)
736 needs_clflush_after = 1;
737 ret = i915_gem_object_set_to_gtt_domain(obj, true);
741 /* Same trick applies for invalidate partially written cachelines before
743 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
744 && obj->cache_level == I915_CACHE_NONE)
745 needs_clflush_before = 1;
747 offset = args->offset;
752 int partial_cacheline_write;
754 /* Operation in this page
756 * shmem_page_offset = offset within page in shmem file
757 * page_length = bytes to copy for this page
759 shmem_page_offset = offset_in_page(offset);
761 page_length = remain;
762 if ((shmem_page_offset + page_length) > PAGE_SIZE)
763 page_length = PAGE_SIZE - shmem_page_offset;
765 /* If we don't overwrite a cacheline completely we need to be
766 * careful to have up-to-date data by first clflushing. Don't
767 * overcomplicate things and flush the entire patch. */
768 partial_cacheline_write = needs_clflush_before &&
769 ((shmem_page_offset | page_length)
770 & (boot_cpu_data.x86_clflush_size - 1));
773 page = obj->pages[offset >> PAGE_SHIFT];
776 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
784 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
785 (page_to_phys(page) & (1 << 17)) != 0;
787 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
788 user_data, page_do_bit17_swizzling,
789 partial_cacheline_write,
790 needs_clflush_after);
795 page_cache_get(page);
796 mutex_unlock(&dev->struct_mutex);
798 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
799 user_data, page_do_bit17_swizzling,
800 partial_cacheline_write,
801 needs_clflush_after);
803 mutex_lock(&dev->struct_mutex);
804 page_cache_release(page);
806 set_page_dirty(page);
807 mark_page_accessed(page);
809 page_cache_release(page);
816 remain -= page_length;
817 user_data += page_length;
818 offset += page_length;
823 /* Fixup: Kill any reinstated backing storage pages */
824 if (obj->madv == __I915_MADV_PURGED)
825 i915_gem_object_truncate(obj);
826 /* and flush dirty cachelines in case the object isn't in the cpu write
828 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
829 i915_gem_clflush_object(obj);
830 intel_gtt_chipset_flush();
834 if (needs_clflush_after)
835 intel_gtt_chipset_flush();
841 * Writes data to the object referenced by handle.
843 * On error, the contents of the buffer that were to be modified are undefined.
846 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *file)
849 struct drm_i915_gem_pwrite *args = data;
850 struct drm_i915_gem_object *obj;
856 if (!access_ok(VERIFY_READ,
857 (char __user *)(uintptr_t)args->data_ptr,
861 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
866 ret = i915_mutex_lock_interruptible(dev);
870 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
871 if (&obj->base == NULL) {
876 /* Bounds check destination. */
877 if (args->offset > obj->base.size ||
878 args->size > obj->base.size - args->offset) {
883 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
886 /* We can only do the GTT pwrite on untiled buffers, as otherwise
887 * it would end up going through the fenced access, and we'll get
888 * different detiling behavior between reading and writing.
889 * pread/pwrite currently are reading and writing from the CPU
890 * perspective, requiring manual detiling by the client.
893 ret = i915_gem_phys_pwrite(dev, obj, args, file);
897 if (obj->gtt_space &&
898 obj->cache_level == I915_CACHE_NONE &&
899 obj->tiling_mode == I915_TILING_NONE &&
900 obj->map_and_fenceable &&
901 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
902 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
903 /* Note that the gtt paths might fail with non-page-backed user
904 * pointers (e.g. gtt mappings when moving data between
905 * textures). Fallback to the shmem path in that case. */
909 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
912 drm_gem_object_unreference(&obj->base);
914 mutex_unlock(&dev->struct_mutex);
919 * Called when user space prepares to use an object with the CPU, either
920 * through the mmap ioctl's mapping or a GTT mapping.
923 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
924 struct drm_file *file)
926 struct drm_i915_gem_set_domain *args = data;
927 struct drm_i915_gem_object *obj;
928 uint32_t read_domains = args->read_domains;
929 uint32_t write_domain = args->write_domain;
932 /* Only handle setting domains to types used by the CPU. */
933 if (write_domain & I915_GEM_GPU_DOMAINS)
936 if (read_domains & I915_GEM_GPU_DOMAINS)
939 /* Having something in the write domain implies it's in the read
940 * domain, and only that read domain. Enforce that in the request.
942 if (write_domain != 0 && read_domains != write_domain)
945 ret = i915_mutex_lock_interruptible(dev);
949 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
950 if (&obj->base == NULL) {
955 if (read_domains & I915_GEM_DOMAIN_GTT) {
956 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
958 /* Silently promote "you're not bound, there was nothing to do"
959 * to success, since the client was just asking us to
960 * make sure everything was done.
965 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
968 drm_gem_object_unreference(&obj->base);
970 mutex_unlock(&dev->struct_mutex);
975 * Called when user space has done writes to this buffer
978 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file)
981 struct drm_i915_gem_sw_finish *args = data;
982 struct drm_i915_gem_object *obj;
985 ret = i915_mutex_lock_interruptible(dev);
989 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
990 if (&obj->base == NULL) {
995 /* Pinned buffers may be scanout, so flush the cache */
997 i915_gem_object_flush_cpu_write_domain(obj);
999 drm_gem_object_unreference(&obj->base);
1001 mutex_unlock(&dev->struct_mutex);
1006 * Maps the contents of an object, returning the address it is mapped
1009 * While the mapping holds a reference on the contents of the object, it doesn't
1010 * imply a ref on the object itself.
1013 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1014 struct drm_file *file)
1016 struct drm_i915_gem_mmap *args = data;
1017 struct drm_gem_object *obj;
1020 obj = drm_gem_object_lookup(dev, file, args->handle);
1024 addr = vm_mmap(obj->filp, 0, args->size,
1025 PROT_READ | PROT_WRITE, MAP_SHARED,
1027 drm_gem_object_unreference_unlocked(obj);
1028 if (IS_ERR((void *)addr))
1031 args->addr_ptr = (uint64_t) addr;
1037 * i915_gem_fault - fault a page into the GTT
1038 * vma: VMA in question
1041 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1042 * from userspace. The fault handler takes care of binding the object to
1043 * the GTT (if needed), allocating and programming a fence register (again,
1044 * only if needed based on whether the old reg is still valid or the object
1045 * is tiled) and inserting a new PTE into the faulting process.
1047 * Note that the faulting process may involve evicting existing objects
1048 * from the GTT and/or fence registers to make room. So performance may
1049 * suffer if the GTT working set is large or there are few fence registers
1052 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1054 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1055 struct drm_device *dev = obj->base.dev;
1056 drm_i915_private_t *dev_priv = dev->dev_private;
1057 pgoff_t page_offset;
1060 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1062 /* We don't use vmf->pgoff since that has the fake offset */
1063 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1066 ret = i915_mutex_lock_interruptible(dev);
1070 trace_i915_gem_object_fault(obj, page_offset, true, write);
1072 /* Now bind it into the GTT if needed */
1073 if (!obj->map_and_fenceable) {
1074 ret = i915_gem_object_unbind(obj);
1078 if (!obj->gtt_space) {
1079 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1083 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1088 if (!obj->has_global_gtt_mapping)
1089 i915_gem_gtt_bind_object(obj, obj->cache_level);
1091 ret = i915_gem_object_get_fence(obj);
1095 if (i915_gem_object_is_inactive(obj))
1096 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1098 obj->fault_mappable = true;
1100 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1103 /* Finally, remap it using the new GTT offset */
1104 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1106 mutex_unlock(&dev->struct_mutex);
1111 /* Give the error handler a chance to run and move the
1112 * objects off the GPU active list. Next time we service the
1113 * fault, we should be able to transition the page into the
1114 * GTT without touching the GPU (and so avoid further
1115 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1116 * with coherency, just lost writes.
1122 return VM_FAULT_NOPAGE;
1124 return VM_FAULT_OOM;
1126 return VM_FAULT_SIGBUS;
1131 * i915_gem_release_mmap - remove physical page mappings
1132 * @obj: obj in question
1134 * Preserve the reservation of the mmapping with the DRM core code, but
1135 * relinquish ownership of the pages back to the system.
1137 * It is vital that we remove the page mapping if we have mapped a tiled
1138 * object through the GTT and then lose the fence register due to
1139 * resource pressure. Similarly if the object has been moved out of the
1140 * aperture, than pages mapped into userspace must be revoked. Removing the
1141 * mapping will then trigger a page fault on the next user access, allowing
1142 * fixup by i915_gem_fault().
1145 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1147 if (!obj->fault_mappable)
1150 if (obj->base.dev->dev_mapping)
1151 unmap_mapping_range(obj->base.dev->dev_mapping,
1152 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1155 obj->fault_mappable = false;
1159 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1163 if (INTEL_INFO(dev)->gen >= 4 ||
1164 tiling_mode == I915_TILING_NONE)
1167 /* Previous chips need a power-of-two fence region when tiling */
1168 if (INTEL_INFO(dev)->gen == 3)
1169 gtt_size = 1024*1024;
1171 gtt_size = 512*1024;
1173 while (gtt_size < size)
1180 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1181 * @obj: object to check
1183 * Return the required GTT alignment for an object, taking into account
1184 * potential fence register mapping.
1187 i915_gem_get_gtt_alignment(struct drm_device *dev,
1192 * Minimum alignment is 4k (GTT page size), but might be greater
1193 * if a fence register is needed for the object.
1195 if (INTEL_INFO(dev)->gen >= 4 ||
1196 tiling_mode == I915_TILING_NONE)
1200 * Previous chips need to be aligned to the size of the smallest
1201 * fence register that can contain the object.
1203 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1207 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1210 * @size: size of the object
1211 * @tiling_mode: tiling mode of the object
1213 * Return the required GTT alignment for an object, only taking into account
1214 * unfenced tiled surface requirements.
1217 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1222 * Minimum alignment is 4k (GTT page size) for sane hw.
1224 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1225 tiling_mode == I915_TILING_NONE)
1228 /* Previous hardware however needs to be aligned to a power-of-two
1229 * tile height. The simplest method for determining this is to reuse
1230 * the power-of-tile object size.
1232 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1236 i915_gem_mmap_gtt(struct drm_file *file,
1237 struct drm_device *dev,
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 struct drm_i915_gem_object *obj;
1245 ret = i915_mutex_lock_interruptible(dev);
1249 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1250 if (&obj->base == NULL) {
1255 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1260 if (obj->madv != I915_MADV_WILLNEED) {
1261 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1266 if (!obj->base.map_list.map) {
1267 ret = drm_gem_create_mmap_offset(&obj->base);
1272 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1275 drm_gem_object_unreference(&obj->base);
1277 mutex_unlock(&dev->struct_mutex);
1282 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1284 * @data: GTT mapping ioctl data
1285 * @file: GEM object info
1287 * Simply returns the fake offset to userspace so it can mmap it.
1288 * The mmap call will end up in drm_gem_mmap(), which will set things
1289 * up so we can get faults in the handler above.
1291 * The fault handler will take care of binding the object into the GTT
1292 * (since it may have been evicted to make room for something), allocating
1293 * a fence register, and mapping the appropriate aperture address into
1297 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1298 struct drm_file *file)
1300 struct drm_i915_gem_mmap_gtt *args = data;
1302 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1307 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1311 struct address_space *mapping;
1312 struct inode *inode;
1315 /* Get the list of pages out of our struct file. They'll be pinned
1316 * at this point until we release them.
1318 page_count = obj->base.size / PAGE_SIZE;
1319 BUG_ON(obj->pages != NULL);
1320 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1321 if (obj->pages == NULL)
1324 inode = obj->base.filp->f_path.dentry->d_inode;
1325 mapping = inode->i_mapping;
1326 gfpmask |= mapping_gfp_mask(mapping);
1328 for (i = 0; i < page_count; i++) {
1329 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1333 obj->pages[i] = page;
1336 if (i915_gem_object_needs_bit17_swizzle(obj))
1337 i915_gem_object_do_bit_17_swizzle(obj);
1343 page_cache_release(obj->pages[i]);
1345 drm_free_large(obj->pages);
1347 return PTR_ERR(page);
1351 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1353 int page_count = obj->base.size / PAGE_SIZE;
1356 BUG_ON(obj->madv == __I915_MADV_PURGED);
1358 if (i915_gem_object_needs_bit17_swizzle(obj))
1359 i915_gem_object_save_bit_17_swizzle(obj);
1361 if (obj->madv == I915_MADV_DONTNEED)
1364 for (i = 0; i < page_count; i++) {
1366 set_page_dirty(obj->pages[i]);
1368 if (obj->madv == I915_MADV_WILLNEED)
1369 mark_page_accessed(obj->pages[i]);
1371 page_cache_release(obj->pages[i]);
1375 drm_free_large(obj->pages);
1380 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1381 struct intel_ring_buffer *ring,
1384 struct drm_device *dev = obj->base.dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1387 BUG_ON(ring == NULL);
1390 /* Add a reference if we're newly entering the active list. */
1392 drm_gem_object_reference(&obj->base);
1396 /* Move from whatever list we were on to the tail of execution. */
1397 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1398 list_move_tail(&obj->ring_list, &ring->active_list);
1400 obj->last_rendering_seqno = seqno;
1402 if (obj->fenced_gpu_access) {
1403 obj->last_fenced_seqno = seqno;
1405 /* Bump MRU to take account of the delayed flush */
1406 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1407 struct drm_i915_fence_reg *reg;
1409 reg = &dev_priv->fence_regs[obj->fence_reg];
1410 list_move_tail(®->lru_list,
1411 &dev_priv->mm.fence_list);
1417 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1419 list_del_init(&obj->ring_list);
1420 obj->last_rendering_seqno = 0;
1421 obj->last_fenced_seqno = 0;
1425 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1427 struct drm_device *dev = obj->base.dev;
1428 drm_i915_private_t *dev_priv = dev->dev_private;
1430 BUG_ON(!obj->active);
1431 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1433 i915_gem_object_move_off_active(obj);
1437 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1439 struct drm_device *dev = obj->base.dev;
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1442 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1444 BUG_ON(!list_empty(&obj->gpu_write_list));
1445 BUG_ON(!obj->active);
1448 i915_gem_object_move_off_active(obj);
1449 obj->fenced_gpu_access = false;
1452 obj->pending_gpu_write = false;
1453 drm_gem_object_unreference(&obj->base);
1455 WARN_ON(i915_verify_lists(dev));
1458 /* Immediately discard the backing storage */
1460 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1462 struct inode *inode;
1464 /* Our goal here is to return as much of the memory as
1465 * is possible back to the system as we are called from OOM.
1466 * To do this we must instruct the shmfs to drop all of its
1467 * backing pages, *now*.
1469 inode = obj->base.filp->f_path.dentry->d_inode;
1470 shmem_truncate_range(inode, 0, (loff_t)-1);
1472 if (obj->base.map_list.map)
1473 drm_gem_free_mmap_offset(&obj->base);
1475 obj->madv = __I915_MADV_PURGED;
1479 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1481 return obj->madv == I915_MADV_DONTNEED;
1485 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1486 uint32_t flush_domains)
1488 struct drm_i915_gem_object *obj, *next;
1490 list_for_each_entry_safe(obj, next,
1491 &ring->gpu_write_list,
1493 if (obj->base.write_domain & flush_domains) {
1494 uint32_t old_write_domain = obj->base.write_domain;
1496 obj->base.write_domain = 0;
1497 list_del_init(&obj->gpu_write_list);
1498 i915_gem_object_move_to_active(obj, ring,
1499 i915_gem_next_request_seqno(ring));
1501 trace_i915_gem_object_change_domain(obj,
1502 obj->base.read_domains,
1509 i915_gem_get_seqno(struct drm_device *dev)
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 u32 seqno = dev_priv->next_seqno;
1514 /* reserve 0 for non-seqno */
1515 if (++dev_priv->next_seqno == 0)
1516 dev_priv->next_seqno = 1;
1522 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1524 if (ring->outstanding_lazy_request == 0)
1525 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1527 return ring->outstanding_lazy_request;
1531 i915_add_request(struct intel_ring_buffer *ring,
1532 struct drm_file *file,
1533 struct drm_i915_gem_request *request)
1535 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1537 u32 request_ring_position;
1541 BUG_ON(request == NULL);
1542 seqno = i915_gem_next_request_seqno(ring);
1544 /* Record the position of the start of the request so that
1545 * should we detect the updated seqno part-way through the
1546 * GPU processing the request, we never over-estimate the
1547 * position of the head.
1549 request_ring_position = intel_ring_get_tail(ring);
1551 ret = ring->add_request(ring, &seqno);
1555 trace_i915_gem_request_add(ring, seqno);
1557 request->seqno = seqno;
1558 request->ring = ring;
1559 request->tail = request_ring_position;
1560 request->emitted_jiffies = jiffies;
1561 was_empty = list_empty(&ring->request_list);
1562 list_add_tail(&request->list, &ring->request_list);
1565 struct drm_i915_file_private *file_priv = file->driver_priv;
1567 spin_lock(&file_priv->mm.lock);
1568 request->file_priv = file_priv;
1569 list_add_tail(&request->client_list,
1570 &file_priv->mm.request_list);
1571 spin_unlock(&file_priv->mm.lock);
1574 ring->outstanding_lazy_request = 0;
1576 if (!dev_priv->mm.suspended) {
1577 if (i915_enable_hangcheck) {
1578 mod_timer(&dev_priv->hangcheck_timer,
1580 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1583 queue_delayed_work(dev_priv->wq,
1584 &dev_priv->mm.retire_work, HZ);
1590 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1592 struct drm_i915_file_private *file_priv = request->file_priv;
1597 spin_lock(&file_priv->mm.lock);
1598 if (request->file_priv) {
1599 list_del(&request->client_list);
1600 request->file_priv = NULL;
1602 spin_unlock(&file_priv->mm.lock);
1605 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1606 struct intel_ring_buffer *ring)
1608 while (!list_empty(&ring->request_list)) {
1609 struct drm_i915_gem_request *request;
1611 request = list_first_entry(&ring->request_list,
1612 struct drm_i915_gem_request,
1615 list_del(&request->list);
1616 i915_gem_request_remove_from_client(request);
1620 while (!list_empty(&ring->active_list)) {
1621 struct drm_i915_gem_object *obj;
1623 obj = list_first_entry(&ring->active_list,
1624 struct drm_i915_gem_object,
1627 obj->base.write_domain = 0;
1628 list_del_init(&obj->gpu_write_list);
1629 i915_gem_object_move_to_inactive(obj);
1633 static void i915_gem_reset_fences(struct drm_device *dev)
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1638 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1639 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1641 i915_gem_write_fence(dev, i, NULL);
1644 i915_gem_object_fence_lost(reg->obj);
1648 INIT_LIST_HEAD(®->lru_list);
1651 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1654 void i915_gem_reset(struct drm_device *dev)
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 struct drm_i915_gem_object *obj;
1658 struct intel_ring_buffer *ring;
1661 for_each_ring(ring, dev_priv, i)
1662 i915_gem_reset_ring_lists(dev_priv, ring);
1664 /* Remove anything from the flushing lists. The GPU cache is likely
1665 * to be lost on reset along with the data, so simply move the
1666 * lost bo to the inactive list.
1668 while (!list_empty(&dev_priv->mm.flushing_list)) {
1669 obj = list_first_entry(&dev_priv->mm.flushing_list,
1670 struct drm_i915_gem_object,
1673 obj->base.write_domain = 0;
1674 list_del_init(&obj->gpu_write_list);
1675 i915_gem_object_move_to_inactive(obj);
1678 /* Move everything out of the GPU domains to ensure we do any
1679 * necessary invalidation upon reuse.
1681 list_for_each_entry(obj,
1682 &dev_priv->mm.inactive_list,
1685 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1688 /* The fence registers are invalidated so clear them out */
1689 i915_gem_reset_fences(dev);
1693 * This function clears the request list as sequence numbers are passed.
1696 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1701 if (list_empty(&ring->request_list))
1704 WARN_ON(i915_verify_lists(ring->dev));
1706 seqno = ring->get_seqno(ring);
1708 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1709 if (seqno >= ring->sync_seqno[i])
1710 ring->sync_seqno[i] = 0;
1712 while (!list_empty(&ring->request_list)) {
1713 struct drm_i915_gem_request *request;
1715 request = list_first_entry(&ring->request_list,
1716 struct drm_i915_gem_request,
1719 if (!i915_seqno_passed(seqno, request->seqno))
1722 trace_i915_gem_request_retire(ring, request->seqno);
1723 /* We know the GPU must have read the request to have
1724 * sent us the seqno + interrupt, so use the position
1725 * of tail of the request to update the last known position
1728 ring->last_retired_head = request->tail;
1730 list_del(&request->list);
1731 i915_gem_request_remove_from_client(request);
1735 /* Move any buffers on the active list that are no longer referenced
1736 * by the ringbuffer to the flushing/inactive lists as appropriate.
1738 while (!list_empty(&ring->active_list)) {
1739 struct drm_i915_gem_object *obj;
1741 obj = list_first_entry(&ring->active_list,
1742 struct drm_i915_gem_object,
1745 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1748 if (obj->base.write_domain != 0)
1749 i915_gem_object_move_to_flushing(obj);
1751 i915_gem_object_move_to_inactive(obj);
1754 if (unlikely(ring->trace_irq_seqno &&
1755 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1756 ring->irq_put(ring);
1757 ring->trace_irq_seqno = 0;
1760 WARN_ON(i915_verify_lists(ring->dev));
1764 i915_gem_retire_requests(struct drm_device *dev)
1766 drm_i915_private_t *dev_priv = dev->dev_private;
1767 struct intel_ring_buffer *ring;
1770 for_each_ring(ring, dev_priv, i)
1771 i915_gem_retire_requests_ring(ring);
1775 i915_gem_retire_work_handler(struct work_struct *work)
1777 drm_i915_private_t *dev_priv;
1778 struct drm_device *dev;
1779 struct intel_ring_buffer *ring;
1783 dev_priv = container_of(work, drm_i915_private_t,
1784 mm.retire_work.work);
1785 dev = dev_priv->dev;
1787 /* Come back later if the device is busy... */
1788 if (!mutex_trylock(&dev->struct_mutex)) {
1789 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1793 i915_gem_retire_requests(dev);
1795 /* Send a periodic flush down the ring so we don't hold onto GEM
1796 * objects indefinitely.
1799 for_each_ring(ring, dev_priv, i) {
1800 if (!list_empty(&ring->gpu_write_list)) {
1801 struct drm_i915_gem_request *request;
1804 ret = i915_gem_flush_ring(ring,
1805 0, I915_GEM_GPU_DOMAINS);
1806 request = kzalloc(sizeof(*request), GFP_KERNEL);
1807 if (ret || request == NULL ||
1808 i915_add_request(ring, NULL, request))
1812 idle &= list_empty(&ring->request_list);
1815 if (!dev_priv->mm.suspended && !idle)
1816 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1818 mutex_unlock(&dev->struct_mutex);
1822 i915_gem_check_wedge(struct drm_i915_private *dev_priv)
1824 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1826 if (atomic_read(&dev_priv->mm.wedged)) {
1827 struct completion *x = &dev_priv->error_completion;
1828 bool recovery_complete;
1829 unsigned long flags;
1831 /* Give the error handler a chance to run. */
1832 spin_lock_irqsave(&x->wait.lock, flags);
1833 recovery_complete = x->done > 0;
1834 spin_unlock_irqrestore(&x->wait.lock, flags);
1836 return recovery_complete ? -EIO : -EAGAIN;
1843 * Compare seqno against outstanding lazy request. Emit a request if they are
1847 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1851 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1853 if (seqno == ring->outstanding_lazy_request) {
1854 struct drm_i915_gem_request *request;
1856 request = kzalloc(sizeof(*request), GFP_KERNEL);
1857 if (request == NULL)
1860 ret = i915_add_request(ring, NULL, request);
1866 BUG_ON(seqno != request->seqno);
1872 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1875 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1878 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1881 trace_i915_gem_request_wait_begin(ring, seqno);
1882 if (WARN_ON(!ring->irq_get(ring)))
1886 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1887 atomic_read(&dev_priv->mm.wedged))
1890 ret = wait_event_interruptible(ring->irq_queue,
1893 wait_event(ring->irq_queue, EXIT_COND);
1895 ring->irq_put(ring);
1896 trace_i915_gem_request_wait_end(ring, seqno);
1903 * Waits for a sequence number to be signaled, and cleans up the
1904 * request and object lists appropriately for that event.
1907 i915_wait_request(struct intel_ring_buffer *ring,
1910 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1915 ret = i915_gem_check_wedge(dev_priv);
1919 ret = i915_gem_check_olr(ring, seqno);
1923 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible);
1924 if (atomic_read(&dev_priv->mm.wedged))
1931 * Ensures that all rendering to the object has completed and the object is
1932 * safe to unbind from the GTT or access from the CPU.
1935 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
1939 /* This function only exists to support waiting for existing rendering,
1940 * not for emitting required flushes.
1942 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
1944 /* If there is rendering queued on the buffer being evicted, wait for
1948 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
1951 i915_gem_retire_requests_ring(obj->ring);
1958 * i915_gem_object_sync - sync an object to a ring.
1960 * @obj: object which may be in use on another ring.
1961 * @to: ring we wish to use the object on. May be NULL.
1963 * This code is meant to abstract object synchronization with the GPU.
1964 * Calling with NULL implies synchronizing the object with the CPU
1965 * rather than a particular GPU ring.
1967 * Returns 0 if successful, else propagates up the lower layer error.
1970 i915_gem_object_sync(struct drm_i915_gem_object *obj,
1971 struct intel_ring_buffer *to)
1973 struct intel_ring_buffer *from = obj->ring;
1977 if (from == NULL || to == from)
1980 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
1981 return i915_gem_object_wait_rendering(obj);
1983 idx = intel_ring_sync_index(from, to);
1985 seqno = obj->last_rendering_seqno;
1986 if (seqno <= from->sync_seqno[idx])
1989 ret = i915_gem_check_olr(obj->ring, seqno);
1993 ret = to->sync_to(to, from, seqno);
1995 from->sync_seqno[idx] = seqno;
2000 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2002 u32 old_write_domain, old_read_domains;
2004 /* Act a barrier for all accesses through the GTT */
2007 /* Force a pagefault for domain tracking on next user access */
2008 i915_gem_release_mmap(obj);
2010 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2013 old_read_domains = obj->base.read_domains;
2014 old_write_domain = obj->base.write_domain;
2016 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2017 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2019 trace_i915_gem_object_change_domain(obj,
2025 * Unbinds an object from the GTT aperture.
2028 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2030 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2033 if (obj->gtt_space == NULL)
2036 if (obj->pin_count != 0) {
2037 DRM_ERROR("Attempting to unbind pinned buffer\n");
2041 ret = i915_gem_object_finish_gpu(obj);
2044 /* Continue on if we fail due to EIO, the GPU is hung so we
2045 * should be safe and we need to cleanup or else we might
2046 * cause memory corruption through use-after-free.
2049 i915_gem_object_finish_gtt(obj);
2051 /* Move the object to the CPU domain to ensure that
2052 * any possible CPU writes while it's not in the GTT
2053 * are flushed when we go to remap it.
2056 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2057 if (ret == -ERESTARTSYS)
2060 /* In the event of a disaster, abandon all caches and
2061 * hope for the best.
2063 i915_gem_clflush_object(obj);
2064 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2067 /* release the fence reg _after_ flushing */
2068 ret = i915_gem_object_put_fence(obj);
2072 trace_i915_gem_object_unbind(obj);
2074 if (obj->has_global_gtt_mapping)
2075 i915_gem_gtt_unbind_object(obj);
2076 if (obj->has_aliasing_ppgtt_mapping) {
2077 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2078 obj->has_aliasing_ppgtt_mapping = 0;
2080 i915_gem_gtt_finish_object(obj);
2082 i915_gem_object_put_pages_gtt(obj);
2084 list_del_init(&obj->gtt_list);
2085 list_del_init(&obj->mm_list);
2086 /* Avoid an unnecessary call to unbind on rebind. */
2087 obj->map_and_fenceable = true;
2089 drm_mm_put_block(obj->gtt_space);
2090 obj->gtt_space = NULL;
2091 obj->gtt_offset = 0;
2093 if (i915_gem_object_is_purgeable(obj))
2094 i915_gem_object_truncate(obj);
2100 i915_gem_flush_ring(struct intel_ring_buffer *ring,
2101 uint32_t invalidate_domains,
2102 uint32_t flush_domains)
2106 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2109 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2111 ret = ring->flush(ring, invalidate_domains, flush_domains);
2115 if (flush_domains & I915_GEM_GPU_DOMAINS)
2116 i915_gem_process_flushing_list(ring, flush_domains);
2121 static int i915_ring_idle(struct intel_ring_buffer *ring)
2125 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2128 if (!list_empty(&ring->gpu_write_list)) {
2129 ret = i915_gem_flush_ring(ring,
2130 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2135 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2138 int i915_gpu_idle(struct drm_device *dev)
2140 drm_i915_private_t *dev_priv = dev->dev_private;
2141 struct intel_ring_buffer *ring;
2144 /* Flush everything onto the inactive list. */
2145 for_each_ring(ring, dev_priv, i) {
2146 ret = i915_ring_idle(ring);
2150 /* Is the device fubar? */
2151 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
2158 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2159 struct drm_i915_gem_object *obj)
2161 drm_i915_private_t *dev_priv = dev->dev_private;
2165 u32 size = obj->gtt_space->size;
2167 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2169 val |= obj->gtt_offset & 0xfffff000;
2170 val |= (uint64_t)((obj->stride / 128) - 1) <<
2171 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2173 if (obj->tiling_mode == I915_TILING_Y)
2174 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2175 val |= I965_FENCE_REG_VALID;
2179 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2180 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2183 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2184 struct drm_i915_gem_object *obj)
2186 drm_i915_private_t *dev_priv = dev->dev_private;
2190 u32 size = obj->gtt_space->size;
2192 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2194 val |= obj->gtt_offset & 0xfffff000;
2195 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2196 if (obj->tiling_mode == I915_TILING_Y)
2197 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2198 val |= I965_FENCE_REG_VALID;
2202 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2203 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2206 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2207 struct drm_i915_gem_object *obj)
2209 drm_i915_private_t *dev_priv = dev->dev_private;
2213 u32 size = obj->gtt_space->size;
2217 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2218 (size & -size) != size ||
2219 (obj->gtt_offset & (size - 1)),
2220 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2221 obj->gtt_offset, obj->map_and_fenceable, size);
2223 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2228 /* Note: pitch better be a power of two tile widths */
2229 pitch_val = obj->stride / tile_width;
2230 pitch_val = ffs(pitch_val) - 1;
2232 val = obj->gtt_offset;
2233 if (obj->tiling_mode == I915_TILING_Y)
2234 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2235 val |= I915_FENCE_SIZE_BITS(size);
2236 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2237 val |= I830_FENCE_REG_VALID;
2242 reg = FENCE_REG_830_0 + reg * 4;
2244 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2246 I915_WRITE(reg, val);
2250 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2251 struct drm_i915_gem_object *obj)
2253 drm_i915_private_t *dev_priv = dev->dev_private;
2257 u32 size = obj->gtt_space->size;
2260 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2261 (size & -size) != size ||
2262 (obj->gtt_offset & (size - 1)),
2263 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2264 obj->gtt_offset, size);
2266 pitch_val = obj->stride / 128;
2267 pitch_val = ffs(pitch_val) - 1;
2269 val = obj->gtt_offset;
2270 if (obj->tiling_mode == I915_TILING_Y)
2271 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2272 val |= I830_FENCE_SIZE_BITS(size);
2273 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2274 val |= I830_FENCE_REG_VALID;
2278 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2279 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2282 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2283 struct drm_i915_gem_object *obj)
2285 switch (INTEL_INFO(dev)->gen) {
2287 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2289 case 4: i965_write_fence_reg(dev, reg, obj); break;
2290 case 3: i915_write_fence_reg(dev, reg, obj); break;
2291 case 2: i830_write_fence_reg(dev, reg, obj); break;
2296 static inline int fence_number(struct drm_i915_private *dev_priv,
2297 struct drm_i915_fence_reg *fence)
2299 return fence - dev_priv->fence_regs;
2302 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2303 struct drm_i915_fence_reg *fence,
2306 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2307 int reg = fence_number(dev_priv, fence);
2309 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2312 obj->fence_reg = reg;
2314 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2316 obj->fence_reg = I915_FENCE_REG_NONE;
2318 list_del_init(&fence->lru_list);
2323 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2327 if (obj->fenced_gpu_access) {
2328 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2329 ret = i915_gem_flush_ring(obj->ring,
2330 0, obj->base.write_domain);
2335 obj->fenced_gpu_access = false;
2338 if (obj->last_fenced_seqno) {
2339 ret = i915_wait_request(obj->ring, obj->last_fenced_seqno);
2343 obj->last_fenced_seqno = 0;
2346 /* Ensure that all CPU reads are completed before installing a fence
2347 * and all writes before removing the fence.
2349 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2356 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2358 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2361 ret = i915_gem_object_flush_fence(obj);
2365 if (obj->fence_reg == I915_FENCE_REG_NONE)
2368 i915_gem_object_update_fence(obj,
2369 &dev_priv->fence_regs[obj->fence_reg],
2371 i915_gem_object_fence_lost(obj);
2376 static struct drm_i915_fence_reg *
2377 i915_find_fence_reg(struct drm_device *dev)
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct drm_i915_fence_reg *reg, *avail;
2383 /* First try to find a free reg */
2385 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2386 reg = &dev_priv->fence_regs[i];
2390 if (!reg->pin_count)
2397 /* None available, try to steal one or wait for a user to finish */
2398 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2409 * i915_gem_object_get_fence - set up fencing for an object
2410 * @obj: object to map through a fence reg
2412 * When mapping objects through the GTT, userspace wants to be able to write
2413 * to them without having to worry about swizzling if the object is tiled.
2414 * This function walks the fence regs looking for a free one for @obj,
2415 * stealing one if it can't find any.
2417 * It then sets up the reg based on the object's properties: address, pitch
2418 * and tiling format.
2420 * For an untiled surface, this removes any existing fence.
2423 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2425 struct drm_device *dev = obj->base.dev;
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 bool enable = obj->tiling_mode != I915_TILING_NONE;
2428 struct drm_i915_fence_reg *reg;
2431 /* Have we updated the tiling parameters upon the object and so
2432 * will need to serialise the write to the associated fence register?
2434 if (obj->fence_dirty) {
2435 ret = i915_gem_object_flush_fence(obj);
2440 /* Just update our place in the LRU if our fence is getting reused. */
2441 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2442 reg = &dev_priv->fence_regs[obj->fence_reg];
2443 if (!obj->fence_dirty) {
2444 list_move_tail(®->lru_list,
2445 &dev_priv->mm.fence_list);
2448 } else if (enable) {
2449 reg = i915_find_fence_reg(dev);
2454 struct drm_i915_gem_object *old = reg->obj;
2456 ret = i915_gem_object_flush_fence(old);
2460 i915_gem_object_fence_lost(old);
2465 i915_gem_object_update_fence(obj, reg, enable);
2466 obj->fence_dirty = false;
2472 * Finds free space in the GTT aperture and binds the object there.
2475 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2477 bool map_and_fenceable)
2479 struct drm_device *dev = obj->base.dev;
2480 drm_i915_private_t *dev_priv = dev->dev_private;
2481 struct drm_mm_node *free_space;
2482 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2483 u32 size, fence_size, fence_alignment, unfenced_alignment;
2484 bool mappable, fenceable;
2487 if (obj->madv != I915_MADV_WILLNEED) {
2488 DRM_ERROR("Attempting to bind a purgeable object\n");
2492 fence_size = i915_gem_get_gtt_size(dev,
2495 fence_alignment = i915_gem_get_gtt_alignment(dev,
2498 unfenced_alignment =
2499 i915_gem_get_unfenced_gtt_alignment(dev,
2504 alignment = map_and_fenceable ? fence_alignment :
2506 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2507 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2511 size = map_and_fenceable ? fence_size : obj->base.size;
2513 /* If the object is bigger than the entire aperture, reject it early
2514 * before evicting everything in a vain attempt to find space.
2516 if (obj->base.size >
2517 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2518 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2523 if (map_and_fenceable)
2525 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2527 dev_priv->mm.gtt_mappable_end,
2530 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2531 size, alignment, 0);
2533 if (free_space != NULL) {
2534 if (map_and_fenceable)
2536 drm_mm_get_block_range_generic(free_space,
2538 dev_priv->mm.gtt_mappable_end,
2542 drm_mm_get_block(free_space, size, alignment);
2544 if (obj->gtt_space == NULL) {
2545 /* If the gtt is empty and we're still having trouble
2546 * fitting our object in, we're out of memory.
2548 ret = i915_gem_evict_something(dev, size, alignment,
2556 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2558 drm_mm_put_block(obj->gtt_space);
2559 obj->gtt_space = NULL;
2561 if (ret == -ENOMEM) {
2562 /* first try to reclaim some memory by clearing the GTT */
2563 ret = i915_gem_evict_everything(dev, false);
2565 /* now try to shrink everyone else */
2580 ret = i915_gem_gtt_prepare_object(obj);
2582 i915_gem_object_put_pages_gtt(obj);
2583 drm_mm_put_block(obj->gtt_space);
2584 obj->gtt_space = NULL;
2586 if (i915_gem_evict_everything(dev, false))
2592 if (!dev_priv->mm.aliasing_ppgtt)
2593 i915_gem_gtt_bind_object(obj, obj->cache_level);
2595 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2596 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2598 /* Assert that the object is not currently in any GPU domain. As it
2599 * wasn't in the GTT, there shouldn't be any way it could have been in
2602 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2603 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2605 obj->gtt_offset = obj->gtt_space->start;
2608 obj->gtt_space->size == fence_size &&
2609 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2612 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2614 obj->map_and_fenceable = mappable && fenceable;
2616 trace_i915_gem_object_bind(obj, map_and_fenceable);
2621 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2623 /* If we don't have a page list set up, then we're not pinned
2624 * to GPU, and we can ignore the cache flush because it'll happen
2625 * again at bind time.
2627 if (obj->pages == NULL)
2630 /* If the GPU is snooping the contents of the CPU cache,
2631 * we do not need to manually clear the CPU cache lines. However,
2632 * the caches are only snooped when the render cache is
2633 * flushed/invalidated. As we always have to emit invalidations
2634 * and flushes when moving into and out of the RENDER domain, correct
2635 * snooping behaviour occurs naturally as the result of our domain
2638 if (obj->cache_level != I915_CACHE_NONE)
2641 trace_i915_gem_object_clflush(obj);
2643 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2646 /** Flushes any GPU write domain for the object if it's dirty. */
2648 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2650 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2653 /* Queue the GPU write cache flushing we need. */
2654 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2657 /** Flushes the GTT write domain for the object if it's dirty. */
2659 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2661 uint32_t old_write_domain;
2663 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2666 /* No actual flushing is required for the GTT write domain. Writes
2667 * to it immediately go to main memory as far as we know, so there's
2668 * no chipset flush. It also doesn't land in render cache.
2670 * However, we do have to enforce the order so that all writes through
2671 * the GTT land before any writes to the device, such as updates to
2676 old_write_domain = obj->base.write_domain;
2677 obj->base.write_domain = 0;
2679 trace_i915_gem_object_change_domain(obj,
2680 obj->base.read_domains,
2684 /** Flushes the CPU write domain for the object if it's dirty. */
2686 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2688 uint32_t old_write_domain;
2690 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2693 i915_gem_clflush_object(obj);
2694 intel_gtt_chipset_flush();
2695 old_write_domain = obj->base.write_domain;
2696 obj->base.write_domain = 0;
2698 trace_i915_gem_object_change_domain(obj,
2699 obj->base.read_domains,
2704 * Moves a single object to the GTT read, and possibly write domain.
2706 * This function returns when the move is complete, including waiting on
2710 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2712 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2713 uint32_t old_write_domain, old_read_domains;
2716 /* Not valid to be called on unbound objects. */
2717 if (obj->gtt_space == NULL)
2720 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2723 ret = i915_gem_object_flush_gpu_write_domain(obj);
2727 if (obj->pending_gpu_write || write) {
2728 ret = i915_gem_object_wait_rendering(obj);
2733 i915_gem_object_flush_cpu_write_domain(obj);
2735 old_write_domain = obj->base.write_domain;
2736 old_read_domains = obj->base.read_domains;
2738 /* It should now be out of any other write domains, and we can update
2739 * the domain values for our changes.
2741 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2742 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2744 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2745 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2749 trace_i915_gem_object_change_domain(obj,
2753 /* And bump the LRU for this access */
2754 if (i915_gem_object_is_inactive(obj))
2755 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2760 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2761 enum i915_cache_level cache_level)
2763 struct drm_device *dev = obj->base.dev;
2764 drm_i915_private_t *dev_priv = dev->dev_private;
2767 if (obj->cache_level == cache_level)
2770 if (obj->pin_count) {
2771 DRM_DEBUG("can not change the cache level of pinned objects\n");
2775 if (obj->gtt_space) {
2776 ret = i915_gem_object_finish_gpu(obj);
2780 i915_gem_object_finish_gtt(obj);
2782 /* Before SandyBridge, you could not use tiling or fence
2783 * registers with snooped memory, so relinquish any fences
2784 * currently pointing to our region in the aperture.
2786 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2787 ret = i915_gem_object_put_fence(obj);
2792 if (obj->has_global_gtt_mapping)
2793 i915_gem_gtt_bind_object(obj, cache_level);
2794 if (obj->has_aliasing_ppgtt_mapping)
2795 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2799 if (cache_level == I915_CACHE_NONE) {
2800 u32 old_read_domains, old_write_domain;
2802 /* If we're coming from LLC cached, then we haven't
2803 * actually been tracking whether the data is in the
2804 * CPU cache or not, since we only allow one bit set
2805 * in obj->write_domain and have been skipping the clflushes.
2806 * Just set it to the CPU cache for now.
2808 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2809 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2811 old_read_domains = obj->base.read_domains;
2812 old_write_domain = obj->base.write_domain;
2814 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2815 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2817 trace_i915_gem_object_change_domain(obj,
2822 obj->cache_level = cache_level;
2827 * Prepare buffer for display plane (scanout, cursors, etc).
2828 * Can be called from an uninterruptible phase (modesetting) and allows
2829 * any flushes to be pipelined (for pageflips).
2832 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2834 struct intel_ring_buffer *pipelined)
2836 u32 old_read_domains, old_write_domain;
2839 ret = i915_gem_object_flush_gpu_write_domain(obj);
2843 if (pipelined != obj->ring) {
2844 ret = i915_gem_object_sync(obj, pipelined);
2849 /* The display engine is not coherent with the LLC cache on gen6. As
2850 * a result, we make sure that the pinning that is about to occur is
2851 * done with uncached PTEs. This is lowest common denominator for all
2854 * However for gen6+, we could do better by using the GFDT bit instead
2855 * of uncaching, which would allow us to flush all the LLC-cached data
2856 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2858 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2862 /* As the user may map the buffer once pinned in the display plane
2863 * (e.g. libkms for the bootup splash), we have to ensure that we
2864 * always use map_and_fenceable for all scanout buffers.
2866 ret = i915_gem_object_pin(obj, alignment, true);
2870 i915_gem_object_flush_cpu_write_domain(obj);
2872 old_write_domain = obj->base.write_domain;
2873 old_read_domains = obj->base.read_domains;
2875 /* It should now be out of any other write domains, and we can update
2876 * the domain values for our changes.
2878 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2879 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2881 trace_i915_gem_object_change_domain(obj,
2889 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2893 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2896 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2897 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2902 ret = i915_gem_object_wait_rendering(obj);
2906 /* Ensure that we invalidate the GPU's caches and TLBs. */
2907 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2912 * Moves a single object to the CPU read, and possibly write domain.
2914 * This function returns when the move is complete, including waiting on
2918 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2920 uint32_t old_write_domain, old_read_domains;
2923 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2926 ret = i915_gem_object_flush_gpu_write_domain(obj);
2930 if (write || obj->pending_gpu_write) {
2931 ret = i915_gem_object_wait_rendering(obj);
2936 i915_gem_object_flush_gtt_write_domain(obj);
2938 old_write_domain = obj->base.write_domain;
2939 old_read_domains = obj->base.read_domains;
2941 /* Flush the CPU cache if it's still invalid. */
2942 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2943 i915_gem_clflush_object(obj);
2945 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2948 /* It should now be out of any other write domains, and we can update
2949 * the domain values for our changes.
2951 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2953 /* If we're writing through the CPU, then the GPU read domains will
2954 * need to be invalidated at next use.
2957 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2958 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2961 trace_i915_gem_object_change_domain(obj,
2968 /* Throttle our rendering by waiting until the ring has completed our requests
2969 * emitted over 20 msec ago.
2971 * Note that if we were to use the current jiffies each time around the loop,
2972 * we wouldn't escape the function with any frames outstanding if the time to
2973 * render a frame was over 20ms.
2975 * This should get us reasonable parallelism between CPU and GPU but also
2976 * relatively low latency when blocking on a particular request to finish.
2979 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct drm_i915_file_private *file_priv = file->driver_priv;
2983 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
2984 struct drm_i915_gem_request *request;
2985 struct intel_ring_buffer *ring = NULL;
2989 if (atomic_read(&dev_priv->mm.wedged))
2992 spin_lock(&file_priv->mm.lock);
2993 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
2994 if (time_after_eq(request->emitted_jiffies, recent_enough))
2997 ring = request->ring;
2998 seqno = request->seqno;
3000 spin_unlock(&file_priv->mm.lock);
3005 ret = __wait_seqno(ring, seqno, true);
3007 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3013 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3015 bool map_and_fenceable)
3019 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
3021 if (obj->gtt_space != NULL) {
3022 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3023 (map_and_fenceable && !obj->map_and_fenceable)) {
3024 WARN(obj->pin_count,
3025 "bo is already pinned with incorrect alignment:"
3026 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3027 " obj->map_and_fenceable=%d\n",
3028 obj->gtt_offset, alignment,
3030 obj->map_and_fenceable);
3031 ret = i915_gem_object_unbind(obj);
3037 if (obj->gtt_space == NULL) {
3038 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3044 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3045 i915_gem_gtt_bind_object(obj, obj->cache_level);
3048 obj->pin_mappable |= map_and_fenceable;
3054 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3056 BUG_ON(obj->pin_count == 0);
3057 BUG_ON(obj->gtt_space == NULL);
3059 if (--obj->pin_count == 0)
3060 obj->pin_mappable = false;
3064 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3065 struct drm_file *file)
3067 struct drm_i915_gem_pin *args = data;
3068 struct drm_i915_gem_object *obj;
3071 ret = i915_mutex_lock_interruptible(dev);
3075 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3076 if (&obj->base == NULL) {
3081 if (obj->madv != I915_MADV_WILLNEED) {
3082 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3087 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3088 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3094 obj->user_pin_count++;
3095 obj->pin_filp = file;
3096 if (obj->user_pin_count == 1) {
3097 ret = i915_gem_object_pin(obj, args->alignment, true);
3102 /* XXX - flush the CPU caches for pinned objects
3103 * as the X server doesn't manage domains yet
3105 i915_gem_object_flush_cpu_write_domain(obj);
3106 args->offset = obj->gtt_offset;
3108 drm_gem_object_unreference(&obj->base);
3110 mutex_unlock(&dev->struct_mutex);
3115 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3116 struct drm_file *file)
3118 struct drm_i915_gem_pin *args = data;
3119 struct drm_i915_gem_object *obj;
3122 ret = i915_mutex_lock_interruptible(dev);
3126 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3127 if (&obj->base == NULL) {
3132 if (obj->pin_filp != file) {
3133 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3138 obj->user_pin_count--;
3139 if (obj->user_pin_count == 0) {
3140 obj->pin_filp = NULL;
3141 i915_gem_object_unpin(obj);
3145 drm_gem_object_unreference(&obj->base);
3147 mutex_unlock(&dev->struct_mutex);
3152 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3153 struct drm_file *file)
3155 struct drm_i915_gem_busy *args = data;
3156 struct drm_i915_gem_object *obj;
3159 ret = i915_mutex_lock_interruptible(dev);
3163 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3164 if (&obj->base == NULL) {
3169 /* Count all active objects as busy, even if they are currently not used
3170 * by the gpu. Users of this interface expect objects to eventually
3171 * become non-busy without any further actions, therefore emit any
3172 * necessary flushes here.
3174 args->busy = obj->active;
3176 /* Unconditionally flush objects, even when the gpu still uses this
3177 * object. Userspace calling this function indicates that it wants to
3178 * use this buffer rather sooner than later, so issuing the required
3179 * flush earlier is beneficial.
3181 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3182 ret = i915_gem_flush_ring(obj->ring,
3183 0, obj->base.write_domain);
3185 ret = i915_gem_check_olr(obj->ring,
3186 obj->last_rendering_seqno);
3189 /* Update the active list for the hardware's current position.
3190 * Otherwise this only updates on a delayed timer or when irqs
3191 * are actually unmasked, and our working set ends up being
3192 * larger than required.
3194 i915_gem_retire_requests_ring(obj->ring);
3196 args->busy = obj->active;
3199 drm_gem_object_unreference(&obj->base);
3201 mutex_unlock(&dev->struct_mutex);
3206 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3207 struct drm_file *file_priv)
3209 return i915_gem_ring_throttle(dev, file_priv);
3213 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3214 struct drm_file *file_priv)
3216 struct drm_i915_gem_madvise *args = data;
3217 struct drm_i915_gem_object *obj;
3220 switch (args->madv) {
3221 case I915_MADV_DONTNEED:
3222 case I915_MADV_WILLNEED:
3228 ret = i915_mutex_lock_interruptible(dev);
3232 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3233 if (&obj->base == NULL) {
3238 if (obj->pin_count) {
3243 if (obj->madv != __I915_MADV_PURGED)
3244 obj->madv = args->madv;
3246 /* if the object is no longer bound, discard its backing storage */
3247 if (i915_gem_object_is_purgeable(obj) &&
3248 obj->gtt_space == NULL)
3249 i915_gem_object_truncate(obj);
3251 args->retained = obj->madv != __I915_MADV_PURGED;
3254 drm_gem_object_unreference(&obj->base);
3256 mutex_unlock(&dev->struct_mutex);
3260 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264 struct drm_i915_gem_object *obj;
3265 struct address_space *mapping;
3268 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3272 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3277 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3278 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3279 /* 965gm cannot relocate objects above 4GiB. */
3280 mask &= ~__GFP_HIGHMEM;
3281 mask |= __GFP_DMA32;
3284 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3285 mapping_set_gfp_mask(mapping, mask);
3287 i915_gem_info_add_obj(dev_priv, size);
3289 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3290 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3293 /* On some devices, we can have the GPU use the LLC (the CPU
3294 * cache) for about a 10% performance improvement
3295 * compared to uncached. Graphics requests other than
3296 * display scanout are coherent with the CPU in
3297 * accessing this cache. This means in this mode we
3298 * don't need to clflush on the CPU side, and on the
3299 * GPU side we only need to flush internal caches to
3300 * get data visible to the CPU.
3302 * However, we maintain the display planes as UC, and so
3303 * need to rebind when first used as such.
3305 obj->cache_level = I915_CACHE_LLC;
3307 obj->cache_level = I915_CACHE_NONE;
3309 obj->base.driver_private = NULL;
3310 obj->fence_reg = I915_FENCE_REG_NONE;
3311 INIT_LIST_HEAD(&obj->mm_list);
3312 INIT_LIST_HEAD(&obj->gtt_list);
3313 INIT_LIST_HEAD(&obj->ring_list);
3314 INIT_LIST_HEAD(&obj->exec_list);
3315 INIT_LIST_HEAD(&obj->gpu_write_list);
3316 obj->madv = I915_MADV_WILLNEED;
3317 /* Avoid an unnecessary call to unbind on the first bind. */
3318 obj->map_and_fenceable = true;
3323 int i915_gem_init_object(struct drm_gem_object *obj)
3330 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3332 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3333 struct drm_device *dev = obj->base.dev;
3334 drm_i915_private_t *dev_priv = dev->dev_private;
3336 trace_i915_gem_object_destroy(obj);
3339 i915_gem_detach_phys_object(dev, obj);
3342 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3343 bool was_interruptible;
3345 was_interruptible = dev_priv->mm.interruptible;
3346 dev_priv->mm.interruptible = false;
3348 WARN_ON(i915_gem_object_unbind(obj));
3350 dev_priv->mm.interruptible = was_interruptible;
3353 if (obj->base.map_list.map)
3354 drm_gem_free_mmap_offset(&obj->base);
3356 drm_gem_object_release(&obj->base);
3357 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3364 i915_gem_idle(struct drm_device *dev)
3366 drm_i915_private_t *dev_priv = dev->dev_private;
3369 mutex_lock(&dev->struct_mutex);
3371 if (dev_priv->mm.suspended) {
3372 mutex_unlock(&dev->struct_mutex);
3376 ret = i915_gpu_idle(dev);
3378 mutex_unlock(&dev->struct_mutex);
3381 i915_gem_retire_requests(dev);
3383 /* Under UMS, be paranoid and evict. */
3384 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3385 i915_gem_evict_everything(dev, false);
3387 i915_gem_reset_fences(dev);
3389 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3390 * We need to replace this with a semaphore, or something.
3391 * And not confound mm.suspended!
3393 dev_priv->mm.suspended = 1;
3394 del_timer_sync(&dev_priv->hangcheck_timer);
3396 i915_kernel_lost_context(dev);
3397 i915_gem_cleanup_ringbuffer(dev);
3399 mutex_unlock(&dev->struct_mutex);
3401 /* Cancel the retire work handler, which should be idle now. */
3402 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3407 void i915_gem_init_swizzling(struct drm_device *dev)
3409 drm_i915_private_t *dev_priv = dev->dev_private;
3411 if (INTEL_INFO(dev)->gen < 5 ||
3412 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3415 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3416 DISP_TILE_SURFACE_SWIZZLING);
3421 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3423 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3425 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3428 void i915_gem_init_ppgtt(struct drm_device *dev)
3430 drm_i915_private_t *dev_priv = dev->dev_private;
3432 struct intel_ring_buffer *ring;
3433 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3434 uint32_t __iomem *pd_addr;
3438 if (!dev_priv->mm.aliasing_ppgtt)
3442 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3443 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3446 if (dev_priv->mm.gtt->needs_dmar)
3447 pt_addr = ppgtt->pt_dma_addr[i];
3449 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3451 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3452 pd_entry |= GEN6_PDE_VALID;
3454 writel(pd_entry, pd_addr + i);
3458 pd_offset = ppgtt->pd_offset;
3459 pd_offset /= 64; /* in cachelines, */
3462 if (INTEL_INFO(dev)->gen == 6) {
3463 uint32_t ecochk, gab_ctl, ecobits;
3465 ecobits = I915_READ(GAC_ECO_BITS);
3466 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3468 gab_ctl = I915_READ(GAB_CTL);
3469 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3471 ecochk = I915_READ(GAM_ECOCHK);
3472 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3473 ECOCHK_PPGTT_CACHE64B);
3474 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3475 } else if (INTEL_INFO(dev)->gen >= 7) {
3476 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3477 /* GFX_MODE is per-ring on gen7+ */
3480 for_each_ring(ring, dev_priv, i) {
3481 if (INTEL_INFO(dev)->gen >= 7)
3482 I915_WRITE(RING_MODE_GEN7(ring),
3483 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3485 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3486 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3491 i915_gem_init_hw(struct drm_device *dev)
3493 drm_i915_private_t *dev_priv = dev->dev_private;
3496 i915_gem_init_swizzling(dev);
3498 ret = intel_init_render_ring_buffer(dev);
3503 ret = intel_init_bsd_ring_buffer(dev);
3505 goto cleanup_render_ring;
3509 ret = intel_init_blt_ring_buffer(dev);
3511 goto cleanup_bsd_ring;
3514 dev_priv->next_seqno = 1;
3516 i915_gem_init_ppgtt(dev);
3521 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3522 cleanup_render_ring:
3523 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3528 intel_enable_ppgtt(struct drm_device *dev)
3530 if (i915_enable_ppgtt >= 0)
3531 return i915_enable_ppgtt;
3533 #ifdef CONFIG_INTEL_IOMMU
3534 /* Disable ppgtt on SNB if VT-d is on. */
3535 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3542 int i915_gem_init(struct drm_device *dev)
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 unsigned long gtt_size, mappable_size;
3548 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3549 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3551 mutex_lock(&dev->struct_mutex);
3552 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3553 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3554 * aperture accordingly when using aliasing ppgtt. */
3555 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3557 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3559 ret = i915_gem_init_aliasing_ppgtt(dev);
3561 mutex_unlock(&dev->struct_mutex);
3565 /* Let GEM Manage all of the aperture.
3567 * However, leave one page at the end still bound to the scratch
3568 * page. There are a number of places where the hardware
3569 * apparently prefetches past the end of the object, and we've
3570 * seen multiple hangs with the GPU head pointer stuck in a
3571 * batchbuffer bound at the last page of the aperture. One page
3572 * should be enough to keep any prefetching inside of the
3575 i915_gem_init_global_gtt(dev, 0, mappable_size,
3579 ret = i915_gem_init_hw(dev);
3580 mutex_unlock(&dev->struct_mutex);
3582 i915_gem_cleanup_aliasing_ppgtt(dev);
3586 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3587 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3588 dev_priv->dri1.allow_batchbuffer = 1;
3593 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3595 drm_i915_private_t *dev_priv = dev->dev_private;
3596 struct intel_ring_buffer *ring;
3599 for_each_ring(ring, dev_priv, i)
3600 intel_cleanup_ring_buffer(ring);
3604 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3605 struct drm_file *file_priv)
3607 drm_i915_private_t *dev_priv = dev->dev_private;
3610 if (drm_core_check_feature(dev, DRIVER_MODESET))
3613 if (atomic_read(&dev_priv->mm.wedged)) {
3614 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3615 atomic_set(&dev_priv->mm.wedged, 0);
3618 mutex_lock(&dev->struct_mutex);
3619 dev_priv->mm.suspended = 0;
3621 ret = i915_gem_init_hw(dev);
3623 mutex_unlock(&dev->struct_mutex);
3627 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3628 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3629 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3630 mutex_unlock(&dev->struct_mutex);
3632 ret = drm_irq_install(dev);
3634 goto cleanup_ringbuffer;
3639 mutex_lock(&dev->struct_mutex);
3640 i915_gem_cleanup_ringbuffer(dev);
3641 dev_priv->mm.suspended = 1;
3642 mutex_unlock(&dev->struct_mutex);
3648 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3649 struct drm_file *file_priv)
3651 if (drm_core_check_feature(dev, DRIVER_MODESET))
3654 drm_irq_uninstall(dev);
3655 return i915_gem_idle(dev);
3659 i915_gem_lastclose(struct drm_device *dev)
3663 if (drm_core_check_feature(dev, DRIVER_MODESET))
3666 ret = i915_gem_idle(dev);
3668 DRM_ERROR("failed to idle hardware: %d\n", ret);
3672 init_ring_lists(struct intel_ring_buffer *ring)
3674 INIT_LIST_HEAD(&ring->active_list);
3675 INIT_LIST_HEAD(&ring->request_list);
3676 INIT_LIST_HEAD(&ring->gpu_write_list);
3680 i915_gem_load(struct drm_device *dev)
3683 drm_i915_private_t *dev_priv = dev->dev_private;
3685 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3686 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3687 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3688 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3689 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3690 for (i = 0; i < I915_NUM_RINGS; i++)
3691 init_ring_lists(&dev_priv->ring[i]);
3692 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3693 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3694 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3695 i915_gem_retire_work_handler);
3696 init_completion(&dev_priv->error_completion);
3698 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3700 I915_WRITE(MI_ARB_STATE,
3701 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3704 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3706 /* Old X drivers will take 0-2 for front, back, depth buffers */
3707 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3708 dev_priv->fence_reg_start = 3;
3710 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3711 dev_priv->num_fence_regs = 16;
3713 dev_priv->num_fence_regs = 8;
3715 /* Initialize fence registers to zero */
3716 i915_gem_reset_fences(dev);
3718 i915_gem_detect_bit_6_swizzle(dev);
3719 init_waitqueue_head(&dev_priv->pending_flip_queue);
3721 dev_priv->mm.interruptible = true;
3723 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3724 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3725 register_shrinker(&dev_priv->mm.inactive_shrinker);
3729 * Create a physically contiguous memory object for this object
3730 * e.g. for cursor + overlay regs
3732 static int i915_gem_init_phys_object(struct drm_device *dev,
3733 int id, int size, int align)
3735 drm_i915_private_t *dev_priv = dev->dev_private;
3736 struct drm_i915_gem_phys_object *phys_obj;
3739 if (dev_priv->mm.phys_objs[id - 1] || !size)
3742 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3748 phys_obj->handle = drm_pci_alloc(dev, size, align);
3749 if (!phys_obj->handle) {
3754 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3757 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3765 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3767 drm_i915_private_t *dev_priv = dev->dev_private;
3768 struct drm_i915_gem_phys_object *phys_obj;
3770 if (!dev_priv->mm.phys_objs[id - 1])
3773 phys_obj = dev_priv->mm.phys_objs[id - 1];
3774 if (phys_obj->cur_obj) {
3775 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3779 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3781 drm_pci_free(dev, phys_obj->handle);
3783 dev_priv->mm.phys_objs[id - 1] = NULL;
3786 void i915_gem_free_all_phys_object(struct drm_device *dev)
3790 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3791 i915_gem_free_phys_object(dev, i);
3794 void i915_gem_detach_phys_object(struct drm_device *dev,
3795 struct drm_i915_gem_object *obj)
3797 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3804 vaddr = obj->phys_obj->handle->vaddr;
3806 page_count = obj->base.size / PAGE_SIZE;
3807 for (i = 0; i < page_count; i++) {
3808 struct page *page = shmem_read_mapping_page(mapping, i);
3809 if (!IS_ERR(page)) {
3810 char *dst = kmap_atomic(page);
3811 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3814 drm_clflush_pages(&page, 1);
3816 set_page_dirty(page);
3817 mark_page_accessed(page);
3818 page_cache_release(page);
3821 intel_gtt_chipset_flush();
3823 obj->phys_obj->cur_obj = NULL;
3824 obj->phys_obj = NULL;
3828 i915_gem_attach_phys_object(struct drm_device *dev,
3829 struct drm_i915_gem_object *obj,
3833 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3834 drm_i915_private_t *dev_priv = dev->dev_private;
3839 if (id > I915_MAX_PHYS_OBJECT)
3842 if (obj->phys_obj) {
3843 if (obj->phys_obj->id == id)
3845 i915_gem_detach_phys_object(dev, obj);
3848 /* create a new object */
3849 if (!dev_priv->mm.phys_objs[id - 1]) {
3850 ret = i915_gem_init_phys_object(dev, id,
3851 obj->base.size, align);
3853 DRM_ERROR("failed to init phys object %d size: %zu\n",
3854 id, obj->base.size);
3859 /* bind to the object */
3860 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3861 obj->phys_obj->cur_obj = obj;
3863 page_count = obj->base.size / PAGE_SIZE;
3865 for (i = 0; i < page_count; i++) {
3869 page = shmem_read_mapping_page(mapping, i);
3871 return PTR_ERR(page);
3873 src = kmap_atomic(page);
3874 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3875 memcpy(dst, src, PAGE_SIZE);
3878 mark_page_accessed(page);
3879 page_cache_release(page);
3886 i915_gem_phys_pwrite(struct drm_device *dev,
3887 struct drm_i915_gem_object *obj,
3888 struct drm_i915_gem_pwrite *args,
3889 struct drm_file *file_priv)
3891 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
3892 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3894 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
3895 unsigned long unwritten;
3897 /* The physical object once assigned is fixed for the lifetime
3898 * of the obj, so we can safely drop the lock and continue
3901 mutex_unlock(&dev->struct_mutex);
3902 unwritten = copy_from_user(vaddr, user_data, args->size);
3903 mutex_lock(&dev->struct_mutex);
3908 intel_gtt_chipset_flush();
3912 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3914 struct drm_i915_file_private *file_priv = file->driver_priv;
3916 /* Clean up our request list when the client is going away, so that
3917 * later retire_requests won't dereference our soon-to-be-gone
3920 spin_lock(&file_priv->mm.lock);
3921 while (!list_empty(&file_priv->mm.request_list)) {
3922 struct drm_i915_gem_request *request;
3924 request = list_first_entry(&file_priv->mm.request_list,
3925 struct drm_i915_gem_request,
3927 list_del(&request->client_list);
3928 request->file_priv = NULL;
3930 spin_unlock(&file_priv->mm.lock);
3934 i915_gpu_is_active(struct drm_device *dev)
3936 drm_i915_private_t *dev_priv = dev->dev_private;
3939 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
3940 list_empty(&dev_priv->mm.active_list);
3942 return !lists_empty;
3946 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
3948 struct drm_i915_private *dev_priv =
3949 container_of(shrinker,
3950 struct drm_i915_private,
3951 mm.inactive_shrinker);
3952 struct drm_device *dev = dev_priv->dev;
3953 struct drm_i915_gem_object *obj, *next;
3954 int nr_to_scan = sc->nr_to_scan;
3957 if (!mutex_trylock(&dev->struct_mutex))
3960 /* "fast-path" to count number of available objects */
3961 if (nr_to_scan == 0) {
3963 list_for_each_entry(obj,
3964 &dev_priv->mm.inactive_list,
3967 mutex_unlock(&dev->struct_mutex);
3968 return cnt / 100 * sysctl_vfs_cache_pressure;
3972 /* first scan for clean buffers */
3973 i915_gem_retire_requests(dev);
3975 list_for_each_entry_safe(obj, next,
3976 &dev_priv->mm.inactive_list,
3978 if (i915_gem_object_is_purgeable(obj)) {
3979 if (i915_gem_object_unbind(obj) == 0 &&
3985 /* second pass, evict/count anything still on the inactive list */
3987 list_for_each_entry_safe(obj, next,
3988 &dev_priv->mm.inactive_list,
3991 i915_gem_object_unbind(obj) == 0)
3997 if (nr_to_scan && i915_gpu_is_active(dev)) {
3999 * We are desperate for pages, so as a last resort, wait
4000 * for the GPU to finish and discard whatever we can.
4001 * This has a dramatic impact to reduce the number of
4002 * OOM-killer events whilst running the GPU aggressively.
4004 if (i915_gpu_idle(dev) == 0)
4007 mutex_unlock(&dev->struct_mutex);
4008 return cnt / 100 * sysctl_vfs_cache_pressure;