2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct drm_device *dev)
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct completion *x = &dev_priv->error_completion;
97 if (!atomic_read(&dev_priv->mm.wedged))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret < 0) {
113 if (atomic_read(&dev_priv->mm.wedged)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x->wait.lock, flags);
121 spin_unlock_irqrestore(&x->wait.lock, flags);
126 int i915_mutex_lock_interruptible(struct drm_device *dev)
130 ret = i915_gem_wait_for_error(dev);
134 ret = mutex_lock_interruptible(&dev->struct_mutex);
138 WARN_ON(i915_verify_lists(dev));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
145 return obj->gtt_space && !obj->active;
149 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150 struct drm_file *file)
152 struct drm_i915_gem_init *args = data;
154 if (drm_core_check_feature(dev, DRIVER_MODESET))
157 if (args->gtt_start >= args->gtt_end ||
158 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev)->gen >= 5)
165 mutex_lock(&dev->struct_mutex);
166 i915_gem_init_global_gtt(dev, args->gtt_start,
167 args->gtt_end, args->gtt_end);
168 mutex_unlock(&dev->struct_mutex);
174 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
175 struct drm_file *file)
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 struct drm_i915_gem_get_aperture *args = data;
179 struct drm_i915_gem_object *obj;
183 mutex_lock(&dev->struct_mutex);
184 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
186 pinned += obj->gtt_space->size;
187 mutex_unlock(&dev->struct_mutex);
189 args->aper_size = dev_priv->mm.gtt_total;
190 args->aper_available_size = args->aper_size - pinned;
195 void *i915_gem_object_alloc(struct drm_device *dev)
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
201 void i915_gem_object_free(struct drm_i915_gem_object *obj)
203 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
204 kmem_cache_free(dev_priv->slab, obj);
208 i915_gem_create(struct drm_file *file,
209 struct drm_device *dev,
213 struct drm_i915_gem_object *obj;
217 size = roundup(size, PAGE_SIZE);
221 /* Allocate the new object */
222 obj = i915_gem_alloc_object(dev, size);
226 ret = drm_gem_handle_create(file, &obj->base, &handle);
228 drm_gem_object_release(&obj->base);
229 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
230 i915_gem_object_free(obj);
234 /* drop reference from allocate - handle holds it now */
235 drm_gem_object_unreference(&obj->base);
236 trace_i915_gem_object_create(obj);
243 i915_gem_dumb_create(struct drm_file *file,
244 struct drm_device *dev,
245 struct drm_mode_create_dumb *args)
247 /* have to work out size/pitch and return them */
248 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
249 args->size = args->pitch * args->height;
250 return i915_gem_create(file, dev,
251 args->size, &args->handle);
254 int i915_gem_dumb_destroy(struct drm_file *file,
255 struct drm_device *dev,
258 return drm_gem_handle_delete(file, handle);
262 * Creates a new mm object and returns a handle to it.
265 i915_gem_create_ioctl(struct drm_device *dev, void *data,
266 struct drm_file *file)
268 struct drm_i915_gem_create *args = data;
270 return i915_gem_create(file, dev,
271 args->size, &args->handle);
275 __copy_to_user_swizzled(char __user *cpu_vaddr,
276 const char *gpu_vaddr, int gpu_offset,
279 int ret, cpu_offset = 0;
282 int cacheline_end = ALIGN(gpu_offset + 1, 64);
283 int this_length = min(cacheline_end - gpu_offset, length);
284 int swizzled_gpu_offset = gpu_offset ^ 64;
286 ret = __copy_to_user(cpu_vaddr + cpu_offset,
287 gpu_vaddr + swizzled_gpu_offset,
292 cpu_offset += this_length;
293 gpu_offset += this_length;
294 length -= this_length;
301 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
302 const char __user *cpu_vaddr,
305 int ret, cpu_offset = 0;
308 int cacheline_end = ALIGN(gpu_offset + 1, 64);
309 int this_length = min(cacheline_end - gpu_offset, length);
310 int swizzled_gpu_offset = gpu_offset ^ 64;
312 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
313 cpu_vaddr + cpu_offset,
318 cpu_offset += this_length;
319 gpu_offset += this_length;
320 length -= this_length;
326 /* Per-page copy function for the shmem pread fastpath.
327 * Flushes invalid cachelines before reading the target if
328 * needs_clflush is set. */
330 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
331 char __user *user_data,
332 bool page_do_bit17_swizzling, bool needs_clflush)
337 if (unlikely(page_do_bit17_swizzling))
340 vaddr = kmap_atomic(page);
342 drm_clflush_virt_range(vaddr + shmem_page_offset,
344 ret = __copy_to_user_inatomic(user_data,
345 vaddr + shmem_page_offset,
347 kunmap_atomic(vaddr);
349 return ret ? -EFAULT : 0;
353 shmem_clflush_swizzled_range(char *addr, unsigned long length,
356 if (unlikely(swizzled)) {
357 unsigned long start = (unsigned long) addr;
358 unsigned long end = (unsigned long) addr + length;
360 /* For swizzling simply ensure that we always flush both
361 * channels. Lame, but simple and it works. Swizzled
362 * pwrite/pread is far from a hotpath - current userspace
363 * doesn't use it at all. */
364 start = round_down(start, 128);
365 end = round_up(end, 128);
367 drm_clflush_virt_range((void *)start, end - start);
369 drm_clflush_virt_range(addr, length);
374 /* Only difference to the fast-path function is that this can handle bit17
375 * and uses non-atomic copy and kmap functions. */
377 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
378 char __user *user_data,
379 bool page_do_bit17_swizzling, bool needs_clflush)
386 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
388 page_do_bit17_swizzling);
390 if (page_do_bit17_swizzling)
391 ret = __copy_to_user_swizzled(user_data,
392 vaddr, shmem_page_offset,
395 ret = __copy_to_user(user_data,
396 vaddr + shmem_page_offset,
400 return ret ? - EFAULT : 0;
404 i915_gem_shmem_pread(struct drm_device *dev,
405 struct drm_i915_gem_object *obj,
406 struct drm_i915_gem_pread *args,
407 struct drm_file *file)
409 char __user *user_data;
412 int shmem_page_offset, page_length, ret = 0;
413 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
415 int needs_clflush = 0;
416 struct scatterlist *sg;
419 user_data = (char __user *) (uintptr_t) args->data_ptr;
422 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
424 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
425 /* If we're not in the cpu read domain, set ourself into the gtt
426 * read domain and manually flush cachelines (if required). This
427 * optimizes for the case when the gpu will dirty the data
428 * anyway again before the next pread happens. */
429 if (obj->cache_level == I915_CACHE_NONE)
431 if (obj->gtt_space) {
432 ret = i915_gem_object_set_to_gtt_domain(obj, false);
438 ret = i915_gem_object_get_pages(obj);
442 i915_gem_object_pin_pages(obj);
444 offset = args->offset;
446 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
449 if (i < offset >> PAGE_SHIFT)
455 /* Operation in this page
457 * shmem_page_offset = offset within page in shmem file
458 * page_length = bytes to copy for this page
460 shmem_page_offset = offset_in_page(offset);
461 page_length = remain;
462 if ((shmem_page_offset + page_length) > PAGE_SIZE)
463 page_length = PAGE_SIZE - shmem_page_offset;
466 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
467 (page_to_phys(page) & (1 << 17)) != 0;
469 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
470 user_data, page_do_bit17_swizzling,
475 mutex_unlock(&dev->struct_mutex);
478 ret = fault_in_multipages_writeable(user_data, remain);
479 /* Userspace is tricking us, but we've already clobbered
480 * its pages with the prefault and promised to write the
481 * data up to the first fault. Hence ignore any errors
482 * and just continue. */
487 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
488 user_data, page_do_bit17_swizzling,
491 mutex_lock(&dev->struct_mutex);
494 mark_page_accessed(page);
499 remain -= page_length;
500 user_data += page_length;
501 offset += page_length;
505 i915_gem_object_unpin_pages(obj);
511 * Reads data from the object referenced by handle.
513 * On error, the contents of *data are undefined.
516 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
517 struct drm_file *file)
519 struct drm_i915_gem_pread *args = data;
520 struct drm_i915_gem_object *obj;
526 if (!access_ok(VERIFY_WRITE,
527 (char __user *)(uintptr_t)args->data_ptr,
531 ret = i915_mutex_lock_interruptible(dev);
535 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
536 if (&obj->base == NULL) {
541 /* Bounds check source. */
542 if (args->offset > obj->base.size ||
543 args->size > obj->base.size - args->offset) {
548 /* prime objects have no backing filp to GEM pread/pwrite
551 if (!obj->base.filp) {
556 trace_i915_gem_object_pread(obj, args->offset, args->size);
558 ret = i915_gem_shmem_pread(dev, obj, args, file);
561 drm_gem_object_unreference(&obj->base);
563 mutex_unlock(&dev->struct_mutex);
567 /* This is the fast write path which cannot handle
568 * page faults in the source data
572 fast_user_write(struct io_mapping *mapping,
573 loff_t page_base, int page_offset,
574 char __user *user_data,
577 void __iomem *vaddr_atomic;
579 unsigned long unwritten;
581 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
582 /* We can use the cpu mem copy function because this is X86. */
583 vaddr = (void __force*)vaddr_atomic + page_offset;
584 unwritten = __copy_from_user_inatomic_nocache(vaddr,
586 io_mapping_unmap_atomic(vaddr_atomic);
591 * This is the fast pwrite path, where we copy the data directly from the
592 * user into the GTT, uncached.
595 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
596 struct drm_i915_gem_object *obj,
597 struct drm_i915_gem_pwrite *args,
598 struct drm_file *file)
600 drm_i915_private_t *dev_priv = dev->dev_private;
602 loff_t offset, page_base;
603 char __user *user_data;
604 int page_offset, page_length, ret;
606 ret = i915_gem_object_pin(obj, 0, true, true);
610 ret = i915_gem_object_set_to_gtt_domain(obj, true);
614 ret = i915_gem_object_put_fence(obj);
618 user_data = (char __user *) (uintptr_t) args->data_ptr;
621 offset = obj->gtt_offset + args->offset;
624 /* Operation in this page
626 * page_base = page offset within aperture
627 * page_offset = offset within page
628 * page_length = bytes to copy for this page
630 page_base = offset & PAGE_MASK;
631 page_offset = offset_in_page(offset);
632 page_length = remain;
633 if ((page_offset + remain) > PAGE_SIZE)
634 page_length = PAGE_SIZE - page_offset;
636 /* If we get a fault while copying data, then (presumably) our
637 * source page isn't available. Return the error and we'll
638 * retry in the slow path.
640 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
641 page_offset, user_data, page_length)) {
646 remain -= page_length;
647 user_data += page_length;
648 offset += page_length;
652 i915_gem_object_unpin(obj);
657 /* Per-page copy function for the shmem pwrite fastpath.
658 * Flushes invalid cachelines before writing to the target if
659 * needs_clflush_before is set and flushes out any written cachelines after
660 * writing if needs_clflush is set. */
662 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
663 char __user *user_data,
664 bool page_do_bit17_swizzling,
665 bool needs_clflush_before,
666 bool needs_clflush_after)
671 if (unlikely(page_do_bit17_swizzling))
674 vaddr = kmap_atomic(page);
675 if (needs_clflush_before)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
678 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
681 if (needs_clflush_after)
682 drm_clflush_virt_range(vaddr + shmem_page_offset,
684 kunmap_atomic(vaddr);
686 return ret ? -EFAULT : 0;
689 /* Only difference to the fast-path function is that this can handle bit17
690 * and uses non-atomic copy and kmap functions. */
692 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
693 char __user *user_data,
694 bool page_do_bit17_swizzling,
695 bool needs_clflush_before,
696 bool needs_clflush_after)
702 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
703 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
705 page_do_bit17_swizzling);
706 if (page_do_bit17_swizzling)
707 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
711 ret = __copy_from_user(vaddr + shmem_page_offset,
714 if (needs_clflush_after)
715 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
717 page_do_bit17_swizzling);
720 return ret ? -EFAULT : 0;
724 i915_gem_shmem_pwrite(struct drm_device *dev,
725 struct drm_i915_gem_object *obj,
726 struct drm_i915_gem_pwrite *args,
727 struct drm_file *file)
731 char __user *user_data;
732 int shmem_page_offset, page_length, ret = 0;
733 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
734 int hit_slowpath = 0;
735 int needs_clflush_after = 0;
736 int needs_clflush_before = 0;
738 struct scatterlist *sg;
740 user_data = (char __user *) (uintptr_t) args->data_ptr;
743 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
745 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
746 /* If we're not in the cpu write domain, set ourself into the gtt
747 * write domain and manually flush cachelines (if required). This
748 * optimizes for the case when the gpu will use the data
749 * right away and we therefore have to clflush anyway. */
750 if (obj->cache_level == I915_CACHE_NONE)
751 needs_clflush_after = 1;
752 if (obj->gtt_space) {
753 ret = i915_gem_object_set_to_gtt_domain(obj, true);
758 /* Same trick applies for invalidate partially written cachelines before
760 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
761 && obj->cache_level == I915_CACHE_NONE)
762 needs_clflush_before = 1;
764 ret = i915_gem_object_get_pages(obj);
768 i915_gem_object_pin_pages(obj);
770 offset = args->offset;
773 for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) {
775 int partial_cacheline_write;
777 if (i < offset >> PAGE_SHIFT)
783 /* Operation in this page
785 * shmem_page_offset = offset within page in shmem file
786 * page_length = bytes to copy for this page
788 shmem_page_offset = offset_in_page(offset);
790 page_length = remain;
791 if ((shmem_page_offset + page_length) > PAGE_SIZE)
792 page_length = PAGE_SIZE - shmem_page_offset;
794 /* If we don't overwrite a cacheline completely we need to be
795 * careful to have up-to-date data by first clflushing. Don't
796 * overcomplicate things and flush the entire patch. */
797 partial_cacheline_write = needs_clflush_before &&
798 ((shmem_page_offset | page_length)
799 & (boot_cpu_data.x86_clflush_size - 1));
802 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
803 (page_to_phys(page) & (1 << 17)) != 0;
805 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
806 user_data, page_do_bit17_swizzling,
807 partial_cacheline_write,
808 needs_clflush_after);
813 mutex_unlock(&dev->struct_mutex);
814 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
815 user_data, page_do_bit17_swizzling,
816 partial_cacheline_write,
817 needs_clflush_after);
819 mutex_lock(&dev->struct_mutex);
822 set_page_dirty(page);
823 mark_page_accessed(page);
828 remain -= page_length;
829 user_data += page_length;
830 offset += page_length;
834 i915_gem_object_unpin_pages(obj);
838 * Fixup: Flush cpu caches in case we didn't flush the dirty
839 * cachelines in-line while writing and the object moved
840 * out of the cpu write domain while we've dropped the lock.
842 if (!needs_clflush_after &&
843 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
844 i915_gem_clflush_object(obj);
845 i915_gem_chipset_flush(dev);
849 if (needs_clflush_after)
850 i915_gem_chipset_flush(dev);
856 * Writes data to the object referenced by handle.
858 * On error, the contents of the buffer that were to be modified are undefined.
861 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
862 struct drm_file *file)
864 struct drm_i915_gem_pwrite *args = data;
865 struct drm_i915_gem_object *obj;
871 if (!access_ok(VERIFY_READ,
872 (char __user *)(uintptr_t)args->data_ptr,
876 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
881 ret = i915_mutex_lock_interruptible(dev);
885 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
886 if (&obj->base == NULL) {
891 /* Bounds check destination. */
892 if (args->offset > obj->base.size ||
893 args->size > obj->base.size - args->offset) {
898 /* prime objects have no backing filp to GEM pread/pwrite
901 if (!obj->base.filp) {
906 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
909 /* We can only do the GTT pwrite on untiled buffers, as otherwise
910 * it would end up going through the fenced access, and we'll get
911 * different detiling behavior between reading and writing.
912 * pread/pwrite currently are reading and writing from the CPU
913 * perspective, requiring manual detiling by the client.
916 ret = i915_gem_phys_pwrite(dev, obj, args, file);
920 if (obj->cache_level == I915_CACHE_NONE &&
921 obj->tiling_mode == I915_TILING_NONE &&
922 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
923 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
924 /* Note that the gtt paths might fail with non-page-backed user
925 * pointers (e.g. gtt mappings when moving data between
926 * textures). Fallback to the shmem path in that case. */
929 if (ret == -EFAULT || ret == -ENOSPC)
930 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
933 drm_gem_object_unreference(&obj->base);
935 mutex_unlock(&dev->struct_mutex);
940 i915_gem_check_wedge(struct drm_i915_private *dev_priv,
943 if (atomic_read(&dev_priv->mm.wedged)) {
944 struct completion *x = &dev_priv->error_completion;
945 bool recovery_complete;
948 /* Give the error handler a chance to run. */
949 spin_lock_irqsave(&x->wait.lock, flags);
950 recovery_complete = x->done > 0;
951 spin_unlock_irqrestore(&x->wait.lock, flags);
953 /* Non-interruptible callers can't handle -EAGAIN, hence return
954 * -EIO unconditionally for these. */
958 /* Recovery complete, but still wedged means reset failure. */
959 if (recovery_complete)
969 * Compare seqno against outstanding lazy request. Emit a request if they are
973 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
977 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
980 if (seqno == ring->outstanding_lazy_request)
981 ret = i915_add_request(ring, NULL, NULL);
987 * __wait_seqno - wait until execution of seqno has finished
988 * @ring: the ring expected to report seqno
990 * @interruptible: do an interruptible wait (normally yes)
991 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
993 * Returns 0 if the seqno was found within the alloted time. Else returns the
994 * errno with remaining time filled in timeout argument.
996 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
997 bool interruptible, struct timespec *timeout)
999 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1000 struct timespec before, now, wait_time={1,0};
1001 unsigned long timeout_jiffies;
1003 bool wait_forever = true;
1006 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1009 trace_i915_gem_request_wait_begin(ring, seqno);
1011 if (timeout != NULL) {
1012 wait_time = *timeout;
1013 wait_forever = false;
1016 timeout_jiffies = timespec_to_jiffies(&wait_time);
1018 if (WARN_ON(!ring->irq_get(ring)))
1021 /* Record current time in case interrupted by signal, or wedged * */
1022 getrawmonotonic(&before);
1025 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1026 atomic_read(&dev_priv->mm.wedged))
1029 end = wait_event_interruptible_timeout(ring->irq_queue,
1033 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1036 ret = i915_gem_check_wedge(dev_priv, interruptible);
1039 } while (end == 0 && wait_forever);
1041 getrawmonotonic(&now);
1043 ring->irq_put(ring);
1044 trace_i915_gem_request_wait_end(ring, seqno);
1048 struct timespec sleep_time = timespec_sub(now, before);
1049 *timeout = timespec_sub(*timeout, sleep_time);
1054 case -EAGAIN: /* Wedged */
1055 case -ERESTARTSYS: /* Signal */
1057 case 0: /* Timeout */
1059 set_normalized_timespec(timeout, 0, 0);
1061 default: /* Completed */
1062 WARN_ON(end < 0); /* We're not aware of other errors */
1068 * Waits for a sequence number to be signaled, and cleans up the
1069 * request and object lists appropriately for that event.
1072 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1074 struct drm_device *dev = ring->dev;
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 bool interruptible = dev_priv->mm.interruptible;
1079 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1082 ret = i915_gem_check_wedge(dev_priv, interruptible);
1086 ret = i915_gem_check_olr(ring, seqno);
1090 return __wait_seqno(ring, seqno, interruptible, NULL);
1094 * Ensures that all rendering to the object has completed and the object is
1095 * safe to unbind from the GTT or access from the CPU.
1097 static __must_check int
1098 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1101 struct intel_ring_buffer *ring = obj->ring;
1105 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1109 ret = i915_wait_seqno(ring, seqno);
1113 i915_gem_retire_requests_ring(ring);
1115 /* Manually manage the write flush as we may have not yet
1116 * retired the buffer.
1118 if (obj->last_write_seqno &&
1119 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1120 obj->last_write_seqno = 0;
1121 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1127 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1128 * as the object state may change during this call.
1130 static __must_check int
1131 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1134 struct drm_device *dev = obj->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 struct intel_ring_buffer *ring = obj->ring;
1140 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1141 BUG_ON(!dev_priv->mm.interruptible);
1143 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1147 ret = i915_gem_check_wedge(dev_priv, true);
1151 ret = i915_gem_check_olr(ring, seqno);
1155 mutex_unlock(&dev->struct_mutex);
1156 ret = __wait_seqno(ring, seqno, true, NULL);
1157 mutex_lock(&dev->struct_mutex);
1159 i915_gem_retire_requests_ring(ring);
1161 /* Manually manage the write flush as we may have not yet
1162 * retired the buffer.
1164 if (obj->last_write_seqno &&
1165 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1166 obj->last_write_seqno = 0;
1167 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file)
1181 struct drm_i915_gem_set_domain *args = data;
1182 struct drm_i915_gem_object *obj;
1183 uint32_t read_domains = args->read_domains;
1184 uint32_t write_domain = args->write_domain;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain & I915_GEM_GPU_DOMAINS)
1191 if (read_domains & I915_GEM_GPU_DOMAINS)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain != 0 && read_domains != write_domain)
1200 ret = i915_mutex_lock_interruptible(dev);
1204 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1205 if (&obj->base == NULL) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1218 if (read_domains & I915_GEM_DOMAIN_GTT) {
1219 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1232 drm_gem_object_unreference(&obj->base);
1234 mutex_unlock(&dev->struct_mutex);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1243 struct drm_file *file)
1245 struct drm_i915_gem_sw_finish *args = data;
1246 struct drm_i915_gem_object *obj;
1249 ret = i915_mutex_lock_interruptible(dev);
1253 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1254 if (&obj->base == NULL) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj);
1263 drm_gem_object_unreference(&obj->base);
1265 mutex_unlock(&dev->struct_mutex);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1278 struct drm_file *file)
1280 struct drm_i915_gem_mmap *args = data;
1281 struct drm_gem_object *obj;
1284 obj = drm_gem_object_lookup(dev, file, args->handle);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj);
1296 addr = vm_mmap(obj->filp, 0, args->size,
1297 PROT_READ | PROT_WRITE, MAP_SHARED,
1299 drm_gem_object_unreference_unlocked(obj);
1300 if (IS_ERR((void *)addr))
1303 args->addr_ptr = (uint64_t) addr;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1326 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1327 struct drm_device *dev = obj->base.dev;
1328 drm_i915_private_t *dev_priv = dev->dev_private;
1329 pgoff_t page_offset;
1332 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1338 ret = i915_mutex_lock_interruptible(dev);
1342 trace_i915_gem_object_fault(obj, page_offset, true, write);
1344 /* Access to snoopable pages through the GTT is incoherent. */
1345 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1350 /* Now bind it into the GTT if needed */
1351 ret = i915_gem_object_pin(obj, 0, true, false);
1355 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1359 ret = i915_gem_object_get_fence(obj);
1363 obj->fault_mappable = true;
1365 pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1368 /* Finally, remap it using the new GTT offset */
1369 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1371 i915_gem_object_unpin(obj);
1373 mutex_unlock(&dev->struct_mutex);
1377 /* If this -EIO is due to a gpu hang, give the reset code a
1378 * chance to clean up the mess. Otherwise return the proper
1380 if (!atomic_read(&dev_priv->mm.wedged))
1381 return VM_FAULT_SIGBUS;
1383 /* Give the error handler a chance to run and move the
1384 * objects off the GPU active list. Next time we service the
1385 * fault, we should be able to transition the page into the
1386 * GTT without touching the GPU (and so avoid further
1387 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1388 * with coherency, just lost writes.
1396 * EBUSY is ok: this just means that another thread
1397 * already did the job.
1399 return VM_FAULT_NOPAGE;
1401 return VM_FAULT_OOM;
1403 return VM_FAULT_SIGBUS;
1405 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1406 return VM_FAULT_SIGBUS;
1411 * i915_gem_release_mmap - remove physical page mappings
1412 * @obj: obj in question
1414 * Preserve the reservation of the mmapping with the DRM core code, but
1415 * relinquish ownership of the pages back to the system.
1417 * It is vital that we remove the page mapping if we have mapped a tiled
1418 * object through the GTT and then lose the fence register due to
1419 * resource pressure. Similarly if the object has been moved out of the
1420 * aperture, than pages mapped into userspace must be revoked. Removing the
1421 * mapping will then trigger a page fault on the next user access, allowing
1422 * fixup by i915_gem_fault().
1425 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1427 if (!obj->fault_mappable)
1430 if (obj->base.dev->dev_mapping)
1431 unmap_mapping_range(obj->base.dev->dev_mapping,
1432 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1435 obj->fault_mappable = false;
1439 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1443 if (INTEL_INFO(dev)->gen >= 4 ||
1444 tiling_mode == I915_TILING_NONE)
1447 /* Previous chips need a power-of-two fence region when tiling */
1448 if (INTEL_INFO(dev)->gen == 3)
1449 gtt_size = 1024*1024;
1451 gtt_size = 512*1024;
1453 while (gtt_size < size)
1460 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1461 * @obj: object to check
1463 * Return the required GTT alignment for an object, taking into account
1464 * potential fence register mapping.
1467 i915_gem_get_gtt_alignment(struct drm_device *dev,
1472 * Minimum alignment is 4k (GTT page size), but might be greater
1473 * if a fence register is needed for the object.
1475 if (INTEL_INFO(dev)->gen >= 4 ||
1476 tiling_mode == I915_TILING_NONE)
1480 * Previous chips need to be aligned to the size of the smallest
1481 * fence register that can contain the object.
1483 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1487 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1490 * @size: size of the object
1491 * @tiling_mode: tiling mode of the object
1493 * Return the required GTT alignment for an object, only taking into account
1494 * unfenced tiled surface requirements.
1497 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1502 * Minimum alignment is 4k (GTT page size) for sane hw.
1504 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1505 tiling_mode == I915_TILING_NONE)
1508 /* Previous hardware however needs to be aligned to a power-of-two
1509 * tile height. The simplest method for determining this is to reuse
1510 * the power-of-tile object size.
1512 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1515 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1517 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1520 if (obj->base.map_list.map)
1523 ret = drm_gem_create_mmap_offset(&obj->base);
1527 /* Badly fragmented mmap space? The only way we can recover
1528 * space is by destroying unwanted objects. We can't randomly release
1529 * mmap_offsets as userspace expects them to be persistent for the
1530 * lifetime of the objects. The closest we can is to release the
1531 * offsets on purgeable objects by truncating it and marking it purged,
1532 * which prevents userspace from ever using that object again.
1534 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1535 ret = drm_gem_create_mmap_offset(&obj->base);
1539 i915_gem_shrink_all(dev_priv);
1540 return drm_gem_create_mmap_offset(&obj->base);
1543 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1545 if (!obj->base.map_list.map)
1548 drm_gem_free_mmap_offset(&obj->base);
1552 i915_gem_mmap_gtt(struct drm_file *file,
1553 struct drm_device *dev,
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 struct drm_i915_gem_object *obj;
1561 ret = i915_mutex_lock_interruptible(dev);
1565 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1566 if (&obj->base == NULL) {
1571 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1576 if (obj->madv != I915_MADV_WILLNEED) {
1577 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1582 ret = i915_gem_object_create_mmap_offset(obj);
1586 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1589 drm_gem_object_unreference(&obj->base);
1591 mutex_unlock(&dev->struct_mutex);
1596 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1598 * @data: GTT mapping ioctl data
1599 * @file: GEM object info
1601 * Simply returns the fake offset to userspace so it can mmap it.
1602 * The mmap call will end up in drm_gem_mmap(), which will set things
1603 * up so we can get faults in the handler above.
1605 * The fault handler will take care of binding the object into the GTT
1606 * (since it may have been evicted to make room for something), allocating
1607 * a fence register, and mapping the appropriate aperture address into
1611 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1612 struct drm_file *file)
1614 struct drm_i915_gem_mmap_gtt *args = data;
1616 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1619 /* Immediately discard the backing storage */
1621 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1623 struct inode *inode;
1625 i915_gem_object_free_mmap_offset(obj);
1627 if (obj->base.filp == NULL)
1630 /* Our goal here is to return as much of the memory as
1631 * is possible back to the system as we are called from OOM.
1632 * To do this we must instruct the shmfs to drop all of its
1633 * backing pages, *now*.
1635 inode = obj->base.filp->f_path.dentry->d_inode;
1636 shmem_truncate_range(inode, 0, (loff_t)-1);
1638 obj->madv = __I915_MADV_PURGED;
1642 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1644 return obj->madv == I915_MADV_DONTNEED;
1648 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1650 int page_count = obj->base.size / PAGE_SIZE;
1651 struct scatterlist *sg;
1654 BUG_ON(obj->madv == __I915_MADV_PURGED);
1656 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1658 /* In the event of a disaster, abandon all caches and
1659 * hope for the best.
1661 WARN_ON(ret != -EIO);
1662 i915_gem_clflush_object(obj);
1663 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1666 if (i915_gem_object_needs_bit17_swizzle(obj))
1667 i915_gem_object_save_bit_17_swizzle(obj);
1669 if (obj->madv == I915_MADV_DONTNEED)
1672 for_each_sg(obj->pages->sgl, sg, page_count, i) {
1673 struct page *page = sg_page(sg);
1676 set_page_dirty(page);
1678 if (obj->madv == I915_MADV_WILLNEED)
1679 mark_page_accessed(page);
1681 page_cache_release(page);
1685 sg_free_table(obj->pages);
1690 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1692 const struct drm_i915_gem_object_ops *ops = obj->ops;
1694 if (obj->pages == NULL)
1697 BUG_ON(obj->gtt_space);
1699 if (obj->pages_pin_count)
1702 ops->put_pages(obj);
1705 list_del(&obj->gtt_list);
1706 if (i915_gem_object_is_purgeable(obj))
1707 i915_gem_object_truncate(obj);
1713 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1715 struct drm_i915_gem_object *obj, *next;
1718 list_for_each_entry_safe(obj, next,
1719 &dev_priv->mm.unbound_list,
1721 if (i915_gem_object_is_purgeable(obj) &&
1722 i915_gem_object_put_pages(obj) == 0) {
1723 count += obj->base.size >> PAGE_SHIFT;
1724 if (count >= target)
1729 list_for_each_entry_safe(obj, next,
1730 &dev_priv->mm.inactive_list,
1732 if (i915_gem_object_is_purgeable(obj) &&
1733 i915_gem_object_unbind(obj) == 0 &&
1734 i915_gem_object_put_pages(obj) == 0) {
1735 count += obj->base.size >> PAGE_SHIFT;
1736 if (count >= target)
1745 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1747 struct drm_i915_gem_object *obj, *next;
1749 i915_gem_evict_everything(dev_priv->dev);
1751 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1752 i915_gem_object_put_pages(obj);
1756 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1758 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1760 struct address_space *mapping;
1761 struct sg_table *st;
1762 struct scatterlist *sg;
1766 /* Assert that the object is not currently in any GPU domain. As it
1767 * wasn't in the GTT, there shouldn't be any way it could have been in
1770 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1771 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1773 st = kmalloc(sizeof(*st), GFP_KERNEL);
1777 page_count = obj->base.size / PAGE_SIZE;
1778 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1784 /* Get the list of pages out of our struct file. They'll be pinned
1785 * at this point until we release them.
1787 * Fail silently without starting the shrinker
1789 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
1790 gfp = mapping_gfp_mask(mapping);
1791 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1792 gfp &= ~(__GFP_IO | __GFP_WAIT);
1793 for_each_sg(st->sgl, sg, page_count, i) {
1794 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1796 i915_gem_purge(dev_priv, page_count);
1797 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1800 /* We've tried hard to allocate the memory by reaping
1801 * our own buffer, now let the real VM do its job and
1802 * go down in flames if truly OOM.
1804 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN);
1805 gfp |= __GFP_IO | __GFP_WAIT;
1807 i915_gem_shrink_all(dev_priv);
1808 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1812 gfp |= __GFP_NORETRY | __GFP_NOWARN;
1813 gfp &= ~(__GFP_IO | __GFP_WAIT);
1816 sg_set_page(sg, page, PAGE_SIZE, 0);
1821 if (i915_gem_object_needs_bit17_swizzle(obj))
1822 i915_gem_object_do_bit_17_swizzle(obj);
1827 for_each_sg(st->sgl, sg, i, page_count)
1828 page_cache_release(sg_page(sg));
1831 return PTR_ERR(page);
1834 /* Ensure that the associated pages are gathered from the backing storage
1835 * and pinned into our object. i915_gem_object_get_pages() may be called
1836 * multiple times before they are released by a single call to
1837 * i915_gem_object_put_pages() - once the pages are no longer referenced
1838 * either as a result of memory pressure (reaping pages under the shrinker)
1839 * or as the object is itself released.
1842 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1844 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1845 const struct drm_i915_gem_object_ops *ops = obj->ops;
1851 BUG_ON(obj->pages_pin_count);
1853 ret = ops->get_pages(obj);
1857 list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
1862 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1863 struct intel_ring_buffer *ring)
1865 struct drm_device *dev = obj->base.dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 u32 seqno = intel_ring_get_seqno(ring);
1869 BUG_ON(ring == NULL);
1872 /* Add a reference if we're newly entering the active list. */
1874 drm_gem_object_reference(&obj->base);
1878 /* Move from whatever list we were on to the tail of execution. */
1879 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1880 list_move_tail(&obj->ring_list, &ring->active_list);
1882 obj->last_read_seqno = seqno;
1884 if (obj->fenced_gpu_access) {
1885 obj->last_fenced_seqno = seqno;
1887 /* Bump MRU to take account of the delayed flush */
1888 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1889 struct drm_i915_fence_reg *reg;
1891 reg = &dev_priv->fence_regs[obj->fence_reg];
1892 list_move_tail(®->lru_list,
1893 &dev_priv->mm.fence_list);
1899 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1901 struct drm_device *dev = obj->base.dev;
1902 struct drm_i915_private *dev_priv = dev->dev_private;
1904 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1905 BUG_ON(!obj->active);
1907 if (obj->pin_count) /* are we a framebuffer? */
1908 intel_mark_fb_idle(obj);
1910 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1912 list_del_init(&obj->ring_list);
1915 obj->last_read_seqno = 0;
1916 obj->last_write_seqno = 0;
1917 obj->base.write_domain = 0;
1919 obj->last_fenced_seqno = 0;
1920 obj->fenced_gpu_access = false;
1923 drm_gem_object_unreference(&obj->base);
1925 WARN_ON(i915_verify_lists(dev));
1929 i915_gem_handle_seqno_wrap(struct drm_device *dev)
1931 struct drm_i915_private *dev_priv = dev->dev_private;
1932 struct intel_ring_buffer *ring;
1935 /* The hardware uses various monotonic 32-bit counters, if we
1936 * detect that they will wraparound we need to idle the GPU
1937 * and reset those counters.
1940 for_each_ring(ring, dev_priv, i) {
1941 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1942 ret |= ring->sync_seqno[j] != 0;
1947 /* Carefully retire all requests without writing to the rings */
1948 for_each_ring(ring, dev_priv, i) {
1949 ret = intel_ring_idle(ring);
1953 i915_gem_retire_requests(dev);
1955 /* Finally reset hw state */
1956 for_each_ring(ring, dev_priv, i) {
1957 ret = intel_ring_handle_seqno_wrap(ring);
1961 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1962 ring->sync_seqno[j] = 0;
1969 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1973 /* reserve 0 for non-seqno */
1974 if (dev_priv->next_seqno == 0) {
1975 int ret = i915_gem_handle_seqno_wrap(dev);
1979 dev_priv->next_seqno = 1;
1982 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
1987 i915_add_request(struct intel_ring_buffer *ring,
1988 struct drm_file *file,
1991 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1992 struct drm_i915_gem_request *request;
1993 u32 request_ring_position;
1998 * Emit any outstanding flushes - execbuf can fail to emit the flush
1999 * after having emitted the batchbuffer command. Hence we need to fix
2000 * things up similar to emitting the lazy request. The difference here
2001 * is that the flush _must_ happen before the next request, no matter
2004 ret = intel_ring_flush_all_caches(ring);
2008 request = kmalloc(sizeof(*request), GFP_KERNEL);
2009 if (request == NULL)
2013 /* Record the position of the start of the request so that
2014 * should we detect the updated seqno part-way through the
2015 * GPU processing the request, we never over-estimate the
2016 * position of the head.
2018 request_ring_position = intel_ring_get_tail(ring);
2020 ret = ring->add_request(ring);
2026 request->seqno = intel_ring_get_seqno(ring);
2027 request->ring = ring;
2028 request->tail = request_ring_position;
2029 request->emitted_jiffies = jiffies;
2030 was_empty = list_empty(&ring->request_list);
2031 list_add_tail(&request->list, &ring->request_list);
2032 request->file_priv = NULL;
2035 struct drm_i915_file_private *file_priv = file->driver_priv;
2037 spin_lock(&file_priv->mm.lock);
2038 request->file_priv = file_priv;
2039 list_add_tail(&request->client_list,
2040 &file_priv->mm.request_list);
2041 spin_unlock(&file_priv->mm.lock);
2044 trace_i915_gem_request_add(ring, request->seqno);
2045 ring->outstanding_lazy_request = 0;
2047 if (!dev_priv->mm.suspended) {
2048 if (i915_enable_hangcheck) {
2049 mod_timer(&dev_priv->hangcheck_timer,
2050 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2053 queue_delayed_work(dev_priv->wq,
2054 &dev_priv->mm.retire_work,
2055 round_jiffies_up_relative(HZ));
2056 intel_mark_busy(dev_priv->dev);
2061 *out_seqno = request->seqno;
2066 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2068 struct drm_i915_file_private *file_priv = request->file_priv;
2073 spin_lock(&file_priv->mm.lock);
2074 if (request->file_priv) {
2075 list_del(&request->client_list);
2076 request->file_priv = NULL;
2078 spin_unlock(&file_priv->mm.lock);
2081 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2082 struct intel_ring_buffer *ring)
2084 while (!list_empty(&ring->request_list)) {
2085 struct drm_i915_gem_request *request;
2087 request = list_first_entry(&ring->request_list,
2088 struct drm_i915_gem_request,
2091 list_del(&request->list);
2092 i915_gem_request_remove_from_client(request);
2096 while (!list_empty(&ring->active_list)) {
2097 struct drm_i915_gem_object *obj;
2099 obj = list_first_entry(&ring->active_list,
2100 struct drm_i915_gem_object,
2103 i915_gem_object_move_to_inactive(obj);
2107 static void i915_gem_reset_fences(struct drm_device *dev)
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2112 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2113 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2115 i915_gem_write_fence(dev, i, NULL);
2118 i915_gem_object_fence_lost(reg->obj);
2122 INIT_LIST_HEAD(®->lru_list);
2125 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2128 void i915_gem_reset(struct drm_device *dev)
2130 struct drm_i915_private *dev_priv = dev->dev_private;
2131 struct drm_i915_gem_object *obj;
2132 struct intel_ring_buffer *ring;
2135 for_each_ring(ring, dev_priv, i)
2136 i915_gem_reset_ring_lists(dev_priv, ring);
2138 /* Move everything out of the GPU domains to ensure we do any
2139 * necessary invalidation upon reuse.
2141 list_for_each_entry(obj,
2142 &dev_priv->mm.inactive_list,
2145 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2148 /* The fence registers are invalidated so clear them out */
2149 i915_gem_reset_fences(dev);
2153 * This function clears the request list as sequence numbers are passed.
2156 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2160 if (list_empty(&ring->request_list))
2163 WARN_ON(i915_verify_lists(ring->dev));
2165 seqno = ring->get_seqno(ring, true);
2167 while (!list_empty(&ring->request_list)) {
2168 struct drm_i915_gem_request *request;
2170 request = list_first_entry(&ring->request_list,
2171 struct drm_i915_gem_request,
2174 if (!i915_seqno_passed(seqno, request->seqno))
2177 trace_i915_gem_request_retire(ring, request->seqno);
2178 /* We know the GPU must have read the request to have
2179 * sent us the seqno + interrupt, so use the position
2180 * of tail of the request to update the last known position
2183 ring->last_retired_head = request->tail;
2185 list_del(&request->list);
2186 i915_gem_request_remove_from_client(request);
2190 /* Move any buffers on the active list that are no longer referenced
2191 * by the ringbuffer to the flushing/inactive lists as appropriate.
2193 while (!list_empty(&ring->active_list)) {
2194 struct drm_i915_gem_object *obj;
2196 obj = list_first_entry(&ring->active_list,
2197 struct drm_i915_gem_object,
2200 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2203 i915_gem_object_move_to_inactive(obj);
2206 if (unlikely(ring->trace_irq_seqno &&
2207 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2208 ring->irq_put(ring);
2209 ring->trace_irq_seqno = 0;
2212 WARN_ON(i915_verify_lists(ring->dev));
2216 i915_gem_retire_requests(struct drm_device *dev)
2218 drm_i915_private_t *dev_priv = dev->dev_private;
2219 struct intel_ring_buffer *ring;
2222 for_each_ring(ring, dev_priv, i)
2223 i915_gem_retire_requests_ring(ring);
2227 i915_gem_retire_work_handler(struct work_struct *work)
2229 drm_i915_private_t *dev_priv;
2230 struct drm_device *dev;
2231 struct intel_ring_buffer *ring;
2235 dev_priv = container_of(work, drm_i915_private_t,
2236 mm.retire_work.work);
2237 dev = dev_priv->dev;
2239 /* Come back later if the device is busy... */
2240 if (!mutex_trylock(&dev->struct_mutex)) {
2241 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2242 round_jiffies_up_relative(HZ));
2246 i915_gem_retire_requests(dev);
2248 /* Send a periodic flush down the ring so we don't hold onto GEM
2249 * objects indefinitely.
2252 for_each_ring(ring, dev_priv, i) {
2253 if (ring->gpu_caches_dirty)
2254 i915_add_request(ring, NULL, NULL);
2256 idle &= list_empty(&ring->request_list);
2259 if (!dev_priv->mm.suspended && !idle)
2260 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2261 round_jiffies_up_relative(HZ));
2263 intel_mark_idle(dev);
2265 mutex_unlock(&dev->struct_mutex);
2269 * Ensures that an object will eventually get non-busy by flushing any required
2270 * write domains, emitting any outstanding lazy request and retiring and
2271 * completed requests.
2274 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2279 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2283 i915_gem_retire_requests_ring(obj->ring);
2290 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2291 * @DRM_IOCTL_ARGS: standard ioctl arguments
2293 * Returns 0 if successful, else an error is returned with the remaining time in
2294 * the timeout parameter.
2295 * -ETIME: object is still busy after timeout
2296 * -ERESTARTSYS: signal interrupted the wait
2297 * -ENONENT: object doesn't exist
2298 * Also possible, but rare:
2299 * -EAGAIN: GPU wedged
2301 * -ENODEV: Internal IRQ fail
2302 * -E?: The add request failed
2304 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2305 * non-zero timeout parameter the wait ioctl will wait for the given number of
2306 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2307 * without holding struct_mutex the object may become re-busied before this
2308 * function completes. A similar but shorter * race condition exists in the busy
2312 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2314 struct drm_i915_gem_wait *args = data;
2315 struct drm_i915_gem_object *obj;
2316 struct intel_ring_buffer *ring = NULL;
2317 struct timespec timeout_stack, *timeout = NULL;
2321 if (args->timeout_ns >= 0) {
2322 timeout_stack = ns_to_timespec(args->timeout_ns);
2323 timeout = &timeout_stack;
2326 ret = i915_mutex_lock_interruptible(dev);
2330 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2331 if (&obj->base == NULL) {
2332 mutex_unlock(&dev->struct_mutex);
2336 /* Need to make sure the object gets inactive eventually. */
2337 ret = i915_gem_object_flush_active(obj);
2342 seqno = obj->last_read_seqno;
2349 /* Do this after OLR check to make sure we make forward progress polling
2350 * on this IOCTL with a 0 timeout (like busy ioctl)
2352 if (!args->timeout_ns) {
2357 drm_gem_object_unreference(&obj->base);
2358 mutex_unlock(&dev->struct_mutex);
2360 ret = __wait_seqno(ring, seqno, true, timeout);
2362 WARN_ON(!timespec_valid(timeout));
2363 args->timeout_ns = timespec_to_ns(timeout);
2368 drm_gem_object_unreference(&obj->base);
2369 mutex_unlock(&dev->struct_mutex);
2374 * i915_gem_object_sync - sync an object to a ring.
2376 * @obj: object which may be in use on another ring.
2377 * @to: ring we wish to use the object on. May be NULL.
2379 * This code is meant to abstract object synchronization with the GPU.
2380 * Calling with NULL implies synchronizing the object with the CPU
2381 * rather than a particular GPU ring.
2383 * Returns 0 if successful, else propagates up the lower layer error.
2386 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2387 struct intel_ring_buffer *to)
2389 struct intel_ring_buffer *from = obj->ring;
2393 if (from == NULL || to == from)
2396 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2397 return i915_gem_object_wait_rendering(obj, false);
2399 idx = intel_ring_sync_index(from, to);
2401 seqno = obj->last_read_seqno;
2402 if (seqno <= from->sync_seqno[idx])
2405 ret = i915_gem_check_olr(obj->ring, seqno);
2409 ret = to->sync_to(to, from, seqno);
2411 /* We use last_read_seqno because sync_to()
2412 * might have just caused seqno wrap under
2415 from->sync_seqno[idx] = obj->last_read_seqno;
2420 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2422 u32 old_write_domain, old_read_domains;
2424 /* Act a barrier for all accesses through the GTT */
2427 /* Force a pagefault for domain tracking on next user access */
2428 i915_gem_release_mmap(obj);
2430 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2433 old_read_domains = obj->base.read_domains;
2434 old_write_domain = obj->base.write_domain;
2436 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2437 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2439 trace_i915_gem_object_change_domain(obj,
2445 * Unbinds an object from the GTT aperture.
2448 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2450 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2453 if (obj->gtt_space == NULL)
2459 BUG_ON(obj->pages == NULL);
2461 ret = i915_gem_object_finish_gpu(obj);
2464 /* Continue on if we fail due to EIO, the GPU is hung so we
2465 * should be safe and we need to cleanup or else we might
2466 * cause memory corruption through use-after-free.
2469 i915_gem_object_finish_gtt(obj);
2471 /* release the fence reg _after_ flushing */
2472 ret = i915_gem_object_put_fence(obj);
2476 trace_i915_gem_object_unbind(obj);
2478 if (obj->has_global_gtt_mapping)
2479 i915_gem_gtt_unbind_object(obj);
2480 if (obj->has_aliasing_ppgtt_mapping) {
2481 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2482 obj->has_aliasing_ppgtt_mapping = 0;
2484 i915_gem_gtt_finish_object(obj);
2486 list_del(&obj->mm_list);
2487 list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list);
2488 /* Avoid an unnecessary call to unbind on rebind. */
2489 obj->map_and_fenceable = true;
2491 drm_mm_put_block(obj->gtt_space);
2492 obj->gtt_space = NULL;
2493 obj->gtt_offset = 0;
2498 int i915_gpu_idle(struct drm_device *dev)
2500 drm_i915_private_t *dev_priv = dev->dev_private;
2501 struct intel_ring_buffer *ring;
2504 /* Flush everything onto the inactive list. */
2505 for_each_ring(ring, dev_priv, i) {
2506 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2510 ret = intel_ring_idle(ring);
2518 static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2519 struct drm_i915_gem_object *obj)
2521 drm_i915_private_t *dev_priv = dev->dev_private;
2525 u32 size = obj->gtt_space->size;
2527 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2529 val |= obj->gtt_offset & 0xfffff000;
2530 val |= (uint64_t)((obj->stride / 128) - 1) <<
2531 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2533 if (obj->tiling_mode == I915_TILING_Y)
2534 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2535 val |= I965_FENCE_REG_VALID;
2539 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2540 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2543 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2544 struct drm_i915_gem_object *obj)
2546 drm_i915_private_t *dev_priv = dev->dev_private;
2550 u32 size = obj->gtt_space->size;
2552 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2554 val |= obj->gtt_offset & 0xfffff000;
2555 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2556 if (obj->tiling_mode == I915_TILING_Y)
2557 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2558 val |= I965_FENCE_REG_VALID;
2562 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2563 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2566 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2567 struct drm_i915_gem_object *obj)
2569 drm_i915_private_t *dev_priv = dev->dev_private;
2573 u32 size = obj->gtt_space->size;
2577 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2578 (size & -size) != size ||
2579 (obj->gtt_offset & (size - 1)),
2580 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2581 obj->gtt_offset, obj->map_and_fenceable, size);
2583 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2588 /* Note: pitch better be a power of two tile widths */
2589 pitch_val = obj->stride / tile_width;
2590 pitch_val = ffs(pitch_val) - 1;
2592 val = obj->gtt_offset;
2593 if (obj->tiling_mode == I915_TILING_Y)
2594 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2595 val |= I915_FENCE_SIZE_BITS(size);
2596 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2597 val |= I830_FENCE_REG_VALID;
2602 reg = FENCE_REG_830_0 + reg * 4;
2604 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2606 I915_WRITE(reg, val);
2610 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2611 struct drm_i915_gem_object *obj)
2613 drm_i915_private_t *dev_priv = dev->dev_private;
2617 u32 size = obj->gtt_space->size;
2620 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2621 (size & -size) != size ||
2622 (obj->gtt_offset & (size - 1)),
2623 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2624 obj->gtt_offset, size);
2626 pitch_val = obj->stride / 128;
2627 pitch_val = ffs(pitch_val) - 1;
2629 val = obj->gtt_offset;
2630 if (obj->tiling_mode == I915_TILING_Y)
2631 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2632 val |= I830_FENCE_SIZE_BITS(size);
2633 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2634 val |= I830_FENCE_REG_VALID;
2638 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2639 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2642 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2643 struct drm_i915_gem_object *obj)
2645 switch (INTEL_INFO(dev)->gen) {
2647 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2649 case 4: i965_write_fence_reg(dev, reg, obj); break;
2650 case 3: i915_write_fence_reg(dev, reg, obj); break;
2651 case 2: i830_write_fence_reg(dev, reg, obj); break;
2656 static inline int fence_number(struct drm_i915_private *dev_priv,
2657 struct drm_i915_fence_reg *fence)
2659 return fence - dev_priv->fence_regs;
2662 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2663 struct drm_i915_fence_reg *fence,
2666 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2667 int reg = fence_number(dev_priv, fence);
2669 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2672 obj->fence_reg = reg;
2674 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2676 obj->fence_reg = I915_FENCE_REG_NONE;
2678 list_del_init(&fence->lru_list);
2683 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2685 if (obj->last_fenced_seqno) {
2686 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2690 obj->last_fenced_seqno = 0;
2693 /* Ensure that all CPU reads are completed before installing a fence
2694 * and all writes before removing the fence.
2696 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2699 obj->fenced_gpu_access = false;
2704 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2706 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2709 ret = i915_gem_object_flush_fence(obj);
2713 if (obj->fence_reg == I915_FENCE_REG_NONE)
2716 i915_gem_object_update_fence(obj,
2717 &dev_priv->fence_regs[obj->fence_reg],
2719 i915_gem_object_fence_lost(obj);
2724 static struct drm_i915_fence_reg *
2725 i915_find_fence_reg(struct drm_device *dev)
2727 struct drm_i915_private *dev_priv = dev->dev_private;
2728 struct drm_i915_fence_reg *reg, *avail;
2731 /* First try to find a free reg */
2733 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2734 reg = &dev_priv->fence_regs[i];
2738 if (!reg->pin_count)
2745 /* None available, try to steal one or wait for a user to finish */
2746 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2757 * i915_gem_object_get_fence - set up fencing for an object
2758 * @obj: object to map through a fence reg
2760 * When mapping objects through the GTT, userspace wants to be able to write
2761 * to them without having to worry about swizzling if the object is tiled.
2762 * This function walks the fence regs looking for a free one for @obj,
2763 * stealing one if it can't find any.
2765 * It then sets up the reg based on the object's properties: address, pitch
2766 * and tiling format.
2768 * For an untiled surface, this removes any existing fence.
2771 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2773 struct drm_device *dev = obj->base.dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 bool enable = obj->tiling_mode != I915_TILING_NONE;
2776 struct drm_i915_fence_reg *reg;
2779 /* Have we updated the tiling parameters upon the object and so
2780 * will need to serialise the write to the associated fence register?
2782 if (obj->fence_dirty) {
2783 ret = i915_gem_object_flush_fence(obj);
2788 /* Just update our place in the LRU if our fence is getting reused. */
2789 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2790 reg = &dev_priv->fence_regs[obj->fence_reg];
2791 if (!obj->fence_dirty) {
2792 list_move_tail(®->lru_list,
2793 &dev_priv->mm.fence_list);
2796 } else if (enable) {
2797 reg = i915_find_fence_reg(dev);
2802 struct drm_i915_gem_object *old = reg->obj;
2804 ret = i915_gem_object_flush_fence(old);
2808 i915_gem_object_fence_lost(old);
2813 i915_gem_object_update_fence(obj, reg, enable);
2814 obj->fence_dirty = false;
2819 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2820 struct drm_mm_node *gtt_space,
2821 unsigned long cache_level)
2823 struct drm_mm_node *other;
2825 /* On non-LLC machines we have to be careful when putting differing
2826 * types of snoopable memory together to avoid the prefetcher
2827 * crossing memory domains and dying.
2832 if (gtt_space == NULL)
2835 if (list_empty(>t_space->node_list))
2838 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
2839 if (other->allocated && !other->hole_follows && other->color != cache_level)
2842 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
2843 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
2849 static void i915_gem_verify_gtt(struct drm_device *dev)
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 struct drm_i915_gem_object *obj;
2856 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
2857 if (obj->gtt_space == NULL) {
2858 printk(KERN_ERR "object found on GTT list with no space reserved\n");
2863 if (obj->cache_level != obj->gtt_space->color) {
2864 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2865 obj->gtt_space->start,
2866 obj->gtt_space->start + obj->gtt_space->size,
2868 obj->gtt_space->color);
2873 if (!i915_gem_valid_gtt_space(dev,
2875 obj->cache_level)) {
2876 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2877 obj->gtt_space->start,
2878 obj->gtt_space->start + obj->gtt_space->size,
2890 * Finds free space in the GTT aperture and binds the object there.
2893 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2895 bool map_and_fenceable,
2898 struct drm_device *dev = obj->base.dev;
2899 drm_i915_private_t *dev_priv = dev->dev_private;
2900 struct drm_mm_node *free_space;
2901 u32 size, fence_size, fence_alignment, unfenced_alignment;
2902 bool mappable, fenceable;
2905 if (obj->madv != I915_MADV_WILLNEED) {
2906 DRM_ERROR("Attempting to bind a purgeable object\n");
2910 fence_size = i915_gem_get_gtt_size(dev,
2913 fence_alignment = i915_gem_get_gtt_alignment(dev,
2916 unfenced_alignment =
2917 i915_gem_get_unfenced_gtt_alignment(dev,
2922 alignment = map_and_fenceable ? fence_alignment :
2924 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2925 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2929 size = map_and_fenceable ? fence_size : obj->base.size;
2931 /* If the object is bigger than the entire aperture, reject it early
2932 * before evicting everything in a vain attempt to find space.
2934 if (obj->base.size >
2935 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2936 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2940 ret = i915_gem_object_get_pages(obj);
2944 i915_gem_object_pin_pages(obj);
2947 if (map_and_fenceable)
2948 free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space,
2949 size, alignment, obj->cache_level,
2950 0, dev_priv->mm.gtt_mappable_end,
2953 free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space,
2954 size, alignment, obj->cache_level,
2957 if (free_space != NULL) {
2958 if (map_and_fenceable)
2960 drm_mm_get_block_range_generic(free_space,
2961 size, alignment, obj->cache_level,
2962 0, dev_priv->mm.gtt_mappable_end,
2966 drm_mm_get_block_generic(free_space,
2967 size, alignment, obj->cache_level,
2970 if (free_space == NULL) {
2971 ret = i915_gem_evict_something(dev, size, alignment,
2976 i915_gem_object_unpin_pages(obj);
2982 if (WARN_ON(!i915_gem_valid_gtt_space(dev,
2984 obj->cache_level))) {
2985 i915_gem_object_unpin_pages(obj);
2986 drm_mm_put_block(free_space);
2990 ret = i915_gem_gtt_prepare_object(obj);
2992 i915_gem_object_unpin_pages(obj);
2993 drm_mm_put_block(free_space);
2997 list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list);
2998 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3000 obj->gtt_space = free_space;
3001 obj->gtt_offset = free_space->start;
3004 free_space->size == fence_size &&
3005 (free_space->start & (fence_alignment - 1)) == 0;
3008 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3010 obj->map_and_fenceable = mappable && fenceable;
3012 i915_gem_object_unpin_pages(obj);
3013 trace_i915_gem_object_bind(obj, map_and_fenceable);
3014 i915_gem_verify_gtt(dev);
3019 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3021 /* If we don't have a page list set up, then we're not pinned
3022 * to GPU, and we can ignore the cache flush because it'll happen
3023 * again at bind time.
3025 if (obj->pages == NULL)
3028 /* If the GPU is snooping the contents of the CPU cache,
3029 * we do not need to manually clear the CPU cache lines. However,
3030 * the caches are only snooped when the render cache is
3031 * flushed/invalidated. As we always have to emit invalidations
3032 * and flushes when moving into and out of the RENDER domain, correct
3033 * snooping behaviour occurs naturally as the result of our domain
3036 if (obj->cache_level != I915_CACHE_NONE)
3039 trace_i915_gem_object_clflush(obj);
3041 drm_clflush_sg(obj->pages);
3044 /** Flushes the GTT write domain for the object if it's dirty. */
3046 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3048 uint32_t old_write_domain;
3050 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3053 /* No actual flushing is required for the GTT write domain. Writes
3054 * to it immediately go to main memory as far as we know, so there's
3055 * no chipset flush. It also doesn't land in render cache.
3057 * However, we do have to enforce the order so that all writes through
3058 * the GTT land before any writes to the device, such as updates to
3063 old_write_domain = obj->base.write_domain;
3064 obj->base.write_domain = 0;
3066 trace_i915_gem_object_change_domain(obj,
3067 obj->base.read_domains,
3071 /** Flushes the CPU write domain for the object if it's dirty. */
3073 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3075 uint32_t old_write_domain;
3077 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3080 i915_gem_clflush_object(obj);
3081 i915_gem_chipset_flush(obj->base.dev);
3082 old_write_domain = obj->base.write_domain;
3083 obj->base.write_domain = 0;
3085 trace_i915_gem_object_change_domain(obj,
3086 obj->base.read_domains,
3091 * Moves a single object to the GTT read, and possibly write domain.
3093 * This function returns when the move is complete, including waiting on
3097 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3099 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3100 uint32_t old_write_domain, old_read_domains;
3103 /* Not valid to be called on unbound objects. */
3104 if (obj->gtt_space == NULL)
3107 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3110 ret = i915_gem_object_wait_rendering(obj, !write);
3114 i915_gem_object_flush_cpu_write_domain(obj);
3116 old_write_domain = obj->base.write_domain;
3117 old_read_domains = obj->base.read_domains;
3119 /* It should now be out of any other write domains, and we can update
3120 * the domain values for our changes.
3122 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3123 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3125 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3126 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3130 trace_i915_gem_object_change_domain(obj,
3134 /* And bump the LRU for this access */
3135 if (i915_gem_object_is_inactive(obj))
3136 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3141 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3142 enum i915_cache_level cache_level)
3144 struct drm_device *dev = obj->base.dev;
3145 drm_i915_private_t *dev_priv = dev->dev_private;
3148 if (obj->cache_level == cache_level)
3151 if (obj->pin_count) {
3152 DRM_DEBUG("can not change the cache level of pinned objects\n");
3156 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3157 ret = i915_gem_object_unbind(obj);
3162 if (obj->gtt_space) {
3163 ret = i915_gem_object_finish_gpu(obj);
3167 i915_gem_object_finish_gtt(obj);
3169 /* Before SandyBridge, you could not use tiling or fence
3170 * registers with snooped memory, so relinquish any fences
3171 * currently pointing to our region in the aperture.
3173 if (INTEL_INFO(dev)->gen < 6) {
3174 ret = i915_gem_object_put_fence(obj);
3179 if (obj->has_global_gtt_mapping)
3180 i915_gem_gtt_bind_object(obj, cache_level);
3181 if (obj->has_aliasing_ppgtt_mapping)
3182 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3185 obj->gtt_space->color = cache_level;
3188 if (cache_level == I915_CACHE_NONE) {
3189 u32 old_read_domains, old_write_domain;
3191 /* If we're coming from LLC cached, then we haven't
3192 * actually been tracking whether the data is in the
3193 * CPU cache or not, since we only allow one bit set
3194 * in obj->write_domain and have been skipping the clflushes.
3195 * Just set it to the CPU cache for now.
3197 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3198 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3200 old_read_domains = obj->base.read_domains;
3201 old_write_domain = obj->base.write_domain;
3203 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3204 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3206 trace_i915_gem_object_change_domain(obj,
3211 obj->cache_level = cache_level;
3212 i915_gem_verify_gtt(dev);
3216 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3217 struct drm_file *file)
3219 struct drm_i915_gem_caching *args = data;
3220 struct drm_i915_gem_object *obj;
3223 ret = i915_mutex_lock_interruptible(dev);
3227 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3228 if (&obj->base == NULL) {
3233 args->caching = obj->cache_level != I915_CACHE_NONE;
3235 drm_gem_object_unreference(&obj->base);
3237 mutex_unlock(&dev->struct_mutex);
3241 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3242 struct drm_file *file)
3244 struct drm_i915_gem_caching *args = data;
3245 struct drm_i915_gem_object *obj;
3246 enum i915_cache_level level;
3249 switch (args->caching) {
3250 case I915_CACHING_NONE:
3251 level = I915_CACHE_NONE;
3253 case I915_CACHING_CACHED:
3254 level = I915_CACHE_LLC;
3260 ret = i915_mutex_lock_interruptible(dev);
3264 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3265 if (&obj->base == NULL) {
3270 ret = i915_gem_object_set_cache_level(obj, level);
3272 drm_gem_object_unreference(&obj->base);
3274 mutex_unlock(&dev->struct_mutex);
3279 * Prepare buffer for display plane (scanout, cursors, etc).
3280 * Can be called from an uninterruptible phase (modesetting) and allows
3281 * any flushes to be pipelined (for pageflips).
3284 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3286 struct intel_ring_buffer *pipelined)
3288 u32 old_read_domains, old_write_domain;
3291 if (pipelined != obj->ring) {
3292 ret = i915_gem_object_sync(obj, pipelined);
3297 /* The display engine is not coherent with the LLC cache on gen6. As
3298 * a result, we make sure that the pinning that is about to occur is
3299 * done with uncached PTEs. This is lowest common denominator for all
3302 * However for gen6+, we could do better by using the GFDT bit instead
3303 * of uncaching, which would allow us to flush all the LLC-cached data
3304 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3306 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3310 /* As the user may map the buffer once pinned in the display plane
3311 * (e.g. libkms for the bootup splash), we have to ensure that we
3312 * always use map_and_fenceable for all scanout buffers.
3314 ret = i915_gem_object_pin(obj, alignment, true, false);
3318 i915_gem_object_flush_cpu_write_domain(obj);
3320 old_write_domain = obj->base.write_domain;
3321 old_read_domains = obj->base.read_domains;
3323 /* It should now be out of any other write domains, and we can update
3324 * the domain values for our changes.
3326 obj->base.write_domain = 0;
3327 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3329 trace_i915_gem_object_change_domain(obj,
3337 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3341 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3344 ret = i915_gem_object_wait_rendering(obj, false);
3348 /* Ensure that we invalidate the GPU's caches and TLBs. */
3349 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3354 * Moves a single object to the CPU read, and possibly write domain.
3356 * This function returns when the move is complete, including waiting on
3360 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3362 uint32_t old_write_domain, old_read_domains;
3365 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3368 ret = i915_gem_object_wait_rendering(obj, !write);
3372 i915_gem_object_flush_gtt_write_domain(obj);
3374 old_write_domain = obj->base.write_domain;
3375 old_read_domains = obj->base.read_domains;
3377 /* Flush the CPU cache if it's still invalid. */
3378 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3379 i915_gem_clflush_object(obj);
3381 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3384 /* It should now be out of any other write domains, and we can update
3385 * the domain values for our changes.
3387 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3389 /* If we're writing through the CPU, then the GPU read domains will
3390 * need to be invalidated at next use.
3393 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3394 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3397 trace_i915_gem_object_change_domain(obj,
3404 /* Throttle our rendering by waiting until the ring has completed our requests
3405 * emitted over 20 msec ago.
3407 * Note that if we were to use the current jiffies each time around the loop,
3408 * we wouldn't escape the function with any frames outstanding if the time to
3409 * render a frame was over 20ms.
3411 * This should get us reasonable parallelism between CPU and GPU but also
3412 * relatively low latency when blocking on a particular request to finish.
3415 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3417 struct drm_i915_private *dev_priv = dev->dev_private;
3418 struct drm_i915_file_private *file_priv = file->driver_priv;
3419 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3420 struct drm_i915_gem_request *request;
3421 struct intel_ring_buffer *ring = NULL;
3425 if (atomic_read(&dev_priv->mm.wedged))
3428 spin_lock(&file_priv->mm.lock);
3429 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3430 if (time_after_eq(request->emitted_jiffies, recent_enough))
3433 ring = request->ring;
3434 seqno = request->seqno;
3436 spin_unlock(&file_priv->mm.lock);
3441 ret = __wait_seqno(ring, seqno, true, NULL);
3443 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3449 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3451 bool map_and_fenceable,
3456 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3459 if (obj->gtt_space != NULL) {
3460 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3461 (map_and_fenceable && !obj->map_and_fenceable)) {
3462 WARN(obj->pin_count,
3463 "bo is already pinned with incorrect alignment:"
3464 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3465 " obj->map_and_fenceable=%d\n",
3466 obj->gtt_offset, alignment,
3468 obj->map_and_fenceable);
3469 ret = i915_gem_object_unbind(obj);
3475 if (obj->gtt_space == NULL) {
3476 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3478 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3484 if (!dev_priv->mm.aliasing_ppgtt)
3485 i915_gem_gtt_bind_object(obj, obj->cache_level);
3488 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3489 i915_gem_gtt_bind_object(obj, obj->cache_level);
3492 obj->pin_mappable |= map_and_fenceable;
3498 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3500 BUG_ON(obj->pin_count == 0);
3501 BUG_ON(obj->gtt_space == NULL);
3503 if (--obj->pin_count == 0)
3504 obj->pin_mappable = false;
3508 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3509 struct drm_file *file)
3511 struct drm_i915_gem_pin *args = data;
3512 struct drm_i915_gem_object *obj;
3515 ret = i915_mutex_lock_interruptible(dev);
3519 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3520 if (&obj->base == NULL) {
3525 if (obj->madv != I915_MADV_WILLNEED) {
3526 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3531 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3532 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3538 obj->user_pin_count++;
3539 obj->pin_filp = file;
3540 if (obj->user_pin_count == 1) {
3541 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3546 /* XXX - flush the CPU caches for pinned objects
3547 * as the X server doesn't manage domains yet
3549 i915_gem_object_flush_cpu_write_domain(obj);
3550 args->offset = obj->gtt_offset;
3552 drm_gem_object_unreference(&obj->base);
3554 mutex_unlock(&dev->struct_mutex);
3559 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3560 struct drm_file *file)
3562 struct drm_i915_gem_pin *args = data;
3563 struct drm_i915_gem_object *obj;
3566 ret = i915_mutex_lock_interruptible(dev);
3570 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3571 if (&obj->base == NULL) {
3576 if (obj->pin_filp != file) {
3577 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3582 obj->user_pin_count--;
3583 if (obj->user_pin_count == 0) {
3584 obj->pin_filp = NULL;
3585 i915_gem_object_unpin(obj);
3589 drm_gem_object_unreference(&obj->base);
3591 mutex_unlock(&dev->struct_mutex);
3596 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3597 struct drm_file *file)
3599 struct drm_i915_gem_busy *args = data;
3600 struct drm_i915_gem_object *obj;
3603 ret = i915_mutex_lock_interruptible(dev);
3607 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3608 if (&obj->base == NULL) {
3613 /* Count all active objects as busy, even if they are currently not used
3614 * by the gpu. Users of this interface expect objects to eventually
3615 * become non-busy without any further actions, therefore emit any
3616 * necessary flushes here.
3618 ret = i915_gem_object_flush_active(obj);
3620 args->busy = obj->active;
3622 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3623 args->busy |= intel_ring_flag(obj->ring) << 16;
3626 drm_gem_object_unreference(&obj->base);
3628 mutex_unlock(&dev->struct_mutex);
3633 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3634 struct drm_file *file_priv)
3636 return i915_gem_ring_throttle(dev, file_priv);
3640 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3641 struct drm_file *file_priv)
3643 struct drm_i915_gem_madvise *args = data;
3644 struct drm_i915_gem_object *obj;
3647 switch (args->madv) {
3648 case I915_MADV_DONTNEED:
3649 case I915_MADV_WILLNEED:
3655 ret = i915_mutex_lock_interruptible(dev);
3659 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3660 if (&obj->base == NULL) {
3665 if (obj->pin_count) {
3670 if (obj->madv != __I915_MADV_PURGED)
3671 obj->madv = args->madv;
3673 /* if the object is no longer attached, discard its backing storage */
3674 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3675 i915_gem_object_truncate(obj);
3677 args->retained = obj->madv != __I915_MADV_PURGED;
3680 drm_gem_object_unreference(&obj->base);
3682 mutex_unlock(&dev->struct_mutex);
3686 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3687 const struct drm_i915_gem_object_ops *ops)
3689 INIT_LIST_HEAD(&obj->mm_list);
3690 INIT_LIST_HEAD(&obj->gtt_list);
3691 INIT_LIST_HEAD(&obj->ring_list);
3692 INIT_LIST_HEAD(&obj->exec_list);
3696 obj->fence_reg = I915_FENCE_REG_NONE;
3697 obj->madv = I915_MADV_WILLNEED;
3698 /* Avoid an unnecessary call to unbind on the first bind. */
3699 obj->map_and_fenceable = true;
3701 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3704 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3705 .get_pages = i915_gem_object_get_pages_gtt,
3706 .put_pages = i915_gem_object_put_pages_gtt,
3709 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3712 struct drm_i915_gem_object *obj;
3713 struct address_space *mapping;
3716 obj = i915_gem_object_alloc(dev);
3720 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3721 i915_gem_object_free(obj);
3725 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3726 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3727 /* 965gm cannot relocate objects above 4GiB. */
3728 mask &= ~__GFP_HIGHMEM;
3729 mask |= __GFP_DMA32;
3732 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3733 mapping_set_gfp_mask(mapping, mask);
3735 i915_gem_object_init(obj, &i915_gem_object_ops);
3737 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3738 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3741 /* On some devices, we can have the GPU use the LLC (the CPU
3742 * cache) for about a 10% performance improvement
3743 * compared to uncached. Graphics requests other than
3744 * display scanout are coherent with the CPU in
3745 * accessing this cache. This means in this mode we
3746 * don't need to clflush on the CPU side, and on the
3747 * GPU side we only need to flush internal caches to
3748 * get data visible to the CPU.
3750 * However, we maintain the display planes as UC, and so
3751 * need to rebind when first used as such.
3753 obj->cache_level = I915_CACHE_LLC;
3755 obj->cache_level = I915_CACHE_NONE;
3760 int i915_gem_init_object(struct drm_gem_object *obj)
3767 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3769 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3770 struct drm_device *dev = obj->base.dev;
3771 drm_i915_private_t *dev_priv = dev->dev_private;
3773 trace_i915_gem_object_destroy(obj);
3776 i915_gem_detach_phys_object(dev, obj);
3779 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3780 bool was_interruptible;
3782 was_interruptible = dev_priv->mm.interruptible;
3783 dev_priv->mm.interruptible = false;
3785 WARN_ON(i915_gem_object_unbind(obj));
3787 dev_priv->mm.interruptible = was_interruptible;
3790 obj->pages_pin_count = 0;
3791 i915_gem_object_put_pages(obj);
3792 i915_gem_object_free_mmap_offset(obj);
3793 i915_gem_object_release_stolen(obj);
3797 if (obj->base.import_attach)
3798 drm_prime_gem_destroy(&obj->base, NULL);
3800 drm_gem_object_release(&obj->base);
3801 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3804 i915_gem_object_free(obj);
3808 i915_gem_idle(struct drm_device *dev)
3810 drm_i915_private_t *dev_priv = dev->dev_private;
3813 mutex_lock(&dev->struct_mutex);
3815 if (dev_priv->mm.suspended) {
3816 mutex_unlock(&dev->struct_mutex);
3820 ret = i915_gpu_idle(dev);
3822 mutex_unlock(&dev->struct_mutex);
3825 i915_gem_retire_requests(dev);
3827 /* Under UMS, be paranoid and evict. */
3828 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3829 i915_gem_evict_everything(dev);
3831 i915_gem_reset_fences(dev);
3833 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3834 * We need to replace this with a semaphore, or something.
3835 * And not confound mm.suspended!
3837 dev_priv->mm.suspended = 1;
3838 del_timer_sync(&dev_priv->hangcheck_timer);
3840 i915_kernel_lost_context(dev);
3841 i915_gem_cleanup_ringbuffer(dev);
3843 mutex_unlock(&dev->struct_mutex);
3845 /* Cancel the retire work handler, which should be idle now. */
3846 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3851 void i915_gem_l3_remap(struct drm_device *dev)
3853 drm_i915_private_t *dev_priv = dev->dev_private;
3857 if (!IS_IVYBRIDGE(dev))
3860 if (!dev_priv->l3_parity.remap_info)
3863 misccpctl = I915_READ(GEN7_MISCCPCTL);
3864 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
3865 POSTING_READ(GEN7_MISCCPCTL);
3867 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
3868 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
3869 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
3870 DRM_DEBUG("0x%x was already programmed to %x\n",
3871 GEN7_L3LOG_BASE + i, remap);
3872 if (remap && !dev_priv->l3_parity.remap_info[i/4])
3873 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3874 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
3877 /* Make sure all the writes land before disabling dop clock gating */
3878 POSTING_READ(GEN7_L3LOG_BASE);
3880 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
3883 void i915_gem_init_swizzling(struct drm_device *dev)
3885 drm_i915_private_t *dev_priv = dev->dev_private;
3887 if (INTEL_INFO(dev)->gen < 5 ||
3888 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3891 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3892 DISP_TILE_SURFACE_SWIZZLING);
3897 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3899 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3901 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3905 intel_enable_blt(struct drm_device *dev)
3910 /* The blitter was dysfunctional on early prototypes */
3911 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
3912 DRM_INFO("BLT not supported on this pre-production hardware;"
3913 " graphics performance will be degraded.\n");
3921 i915_gem_init_hw(struct drm_device *dev)
3923 drm_i915_private_t *dev_priv = dev->dev_private;
3926 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3929 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
3930 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3932 i915_gem_l3_remap(dev);
3934 i915_gem_init_swizzling(dev);
3936 ret = intel_init_render_ring_buffer(dev);
3941 ret = intel_init_bsd_ring_buffer(dev);
3943 goto cleanup_render_ring;
3946 if (intel_enable_blt(dev)) {
3947 ret = intel_init_blt_ring_buffer(dev);
3949 goto cleanup_bsd_ring;
3952 dev_priv->next_seqno = (u32)-1 - 0x1000;
3955 * XXX: There was some w/a described somewhere suggesting loading
3956 * contexts before PPGTT.
3958 i915_gem_context_init(dev);
3959 i915_gem_init_ppgtt(dev);
3964 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3965 cleanup_render_ring:
3966 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3971 intel_enable_ppgtt(struct drm_device *dev)
3973 if (i915_enable_ppgtt >= 0)
3974 return i915_enable_ppgtt;
3976 #ifdef CONFIG_INTEL_IOMMU
3977 /* Disable ppgtt on SNB if VT-d is on. */
3978 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3985 int i915_gem_init(struct drm_device *dev)
3987 struct drm_i915_private *dev_priv = dev->dev_private;
3988 unsigned long gtt_size, mappable_size;
3991 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3992 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3994 mutex_lock(&dev->struct_mutex);
3995 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3996 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3997 * aperture accordingly when using aliasing ppgtt. */
3998 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
4000 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
4002 ret = i915_gem_init_aliasing_ppgtt(dev);
4004 mutex_unlock(&dev->struct_mutex);
4008 /* Let GEM Manage all of the aperture.
4010 * However, leave one page at the end still bound to the scratch
4011 * page. There are a number of places where the hardware
4012 * apparently prefetches past the end of the object, and we've
4013 * seen multiple hangs with the GPU head pointer stuck in a
4014 * batchbuffer bound at the last page of the aperture. One page
4015 * should be enough to keep any prefetching inside of the
4018 i915_gem_init_global_gtt(dev, 0, mappable_size,
4022 ret = i915_gem_init_hw(dev);
4023 mutex_unlock(&dev->struct_mutex);
4025 i915_gem_cleanup_aliasing_ppgtt(dev);
4029 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4030 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4031 dev_priv->dri1.allow_batchbuffer = 1;
4036 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4038 drm_i915_private_t *dev_priv = dev->dev_private;
4039 struct intel_ring_buffer *ring;
4042 for_each_ring(ring, dev_priv, i)
4043 intel_cleanup_ring_buffer(ring);
4047 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4048 struct drm_file *file_priv)
4050 drm_i915_private_t *dev_priv = dev->dev_private;
4053 if (drm_core_check_feature(dev, DRIVER_MODESET))
4056 if (atomic_read(&dev_priv->mm.wedged)) {
4057 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4058 atomic_set(&dev_priv->mm.wedged, 0);
4061 mutex_lock(&dev->struct_mutex);
4062 dev_priv->mm.suspended = 0;
4064 ret = i915_gem_init_hw(dev);
4066 mutex_unlock(&dev->struct_mutex);
4070 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4071 mutex_unlock(&dev->struct_mutex);
4073 ret = drm_irq_install(dev);
4075 goto cleanup_ringbuffer;
4080 mutex_lock(&dev->struct_mutex);
4081 i915_gem_cleanup_ringbuffer(dev);
4082 dev_priv->mm.suspended = 1;
4083 mutex_unlock(&dev->struct_mutex);
4089 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4090 struct drm_file *file_priv)
4092 if (drm_core_check_feature(dev, DRIVER_MODESET))
4095 drm_irq_uninstall(dev);
4096 return i915_gem_idle(dev);
4100 i915_gem_lastclose(struct drm_device *dev)
4104 if (drm_core_check_feature(dev, DRIVER_MODESET))
4107 ret = i915_gem_idle(dev);
4109 DRM_ERROR("failed to idle hardware: %d\n", ret);
4113 init_ring_lists(struct intel_ring_buffer *ring)
4115 INIT_LIST_HEAD(&ring->active_list);
4116 INIT_LIST_HEAD(&ring->request_list);
4120 i915_gem_load(struct drm_device *dev)
4122 drm_i915_private_t *dev_priv = dev->dev_private;
4126 kmem_cache_create("i915_gem_object",
4127 sizeof(struct drm_i915_gem_object), 0,
4131 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4132 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4133 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4134 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4135 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4136 for (i = 0; i < I915_NUM_RINGS; i++)
4137 init_ring_lists(&dev_priv->ring[i]);
4138 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4139 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4140 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4141 i915_gem_retire_work_handler);
4142 init_completion(&dev_priv->error_completion);
4144 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4146 I915_WRITE(MI_ARB_STATE,
4147 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4150 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4152 /* Old X drivers will take 0-2 for front, back, depth buffers */
4153 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4154 dev_priv->fence_reg_start = 3;
4156 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4157 dev_priv->num_fence_regs = 16;
4159 dev_priv->num_fence_regs = 8;
4161 /* Initialize fence registers to zero */
4162 i915_gem_reset_fences(dev);
4164 i915_gem_detect_bit_6_swizzle(dev);
4165 init_waitqueue_head(&dev_priv->pending_flip_queue);
4167 dev_priv->mm.interruptible = true;
4169 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4170 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4171 register_shrinker(&dev_priv->mm.inactive_shrinker);
4175 * Create a physically contiguous memory object for this object
4176 * e.g. for cursor + overlay regs
4178 static int i915_gem_init_phys_object(struct drm_device *dev,
4179 int id, int size, int align)
4181 drm_i915_private_t *dev_priv = dev->dev_private;
4182 struct drm_i915_gem_phys_object *phys_obj;
4185 if (dev_priv->mm.phys_objs[id - 1] || !size)
4188 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4194 phys_obj->handle = drm_pci_alloc(dev, size, align);
4195 if (!phys_obj->handle) {
4200 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4203 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4211 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4213 drm_i915_private_t *dev_priv = dev->dev_private;
4214 struct drm_i915_gem_phys_object *phys_obj;
4216 if (!dev_priv->mm.phys_objs[id - 1])
4219 phys_obj = dev_priv->mm.phys_objs[id - 1];
4220 if (phys_obj->cur_obj) {
4221 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4225 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4227 drm_pci_free(dev, phys_obj->handle);
4229 dev_priv->mm.phys_objs[id - 1] = NULL;
4232 void i915_gem_free_all_phys_object(struct drm_device *dev)
4236 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4237 i915_gem_free_phys_object(dev, i);
4240 void i915_gem_detach_phys_object(struct drm_device *dev,
4241 struct drm_i915_gem_object *obj)
4243 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4250 vaddr = obj->phys_obj->handle->vaddr;
4252 page_count = obj->base.size / PAGE_SIZE;
4253 for (i = 0; i < page_count; i++) {
4254 struct page *page = shmem_read_mapping_page(mapping, i);
4255 if (!IS_ERR(page)) {
4256 char *dst = kmap_atomic(page);
4257 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4260 drm_clflush_pages(&page, 1);
4262 set_page_dirty(page);
4263 mark_page_accessed(page);
4264 page_cache_release(page);
4267 i915_gem_chipset_flush(dev);
4269 obj->phys_obj->cur_obj = NULL;
4270 obj->phys_obj = NULL;
4274 i915_gem_attach_phys_object(struct drm_device *dev,
4275 struct drm_i915_gem_object *obj,
4279 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
4280 drm_i915_private_t *dev_priv = dev->dev_private;
4285 if (id > I915_MAX_PHYS_OBJECT)
4288 if (obj->phys_obj) {
4289 if (obj->phys_obj->id == id)
4291 i915_gem_detach_phys_object(dev, obj);
4294 /* create a new object */
4295 if (!dev_priv->mm.phys_objs[id - 1]) {
4296 ret = i915_gem_init_phys_object(dev, id,
4297 obj->base.size, align);
4299 DRM_ERROR("failed to init phys object %d size: %zu\n",
4300 id, obj->base.size);
4305 /* bind to the object */
4306 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4307 obj->phys_obj->cur_obj = obj;
4309 page_count = obj->base.size / PAGE_SIZE;
4311 for (i = 0; i < page_count; i++) {
4315 page = shmem_read_mapping_page(mapping, i);
4317 return PTR_ERR(page);
4319 src = kmap_atomic(page);
4320 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4321 memcpy(dst, src, PAGE_SIZE);
4324 mark_page_accessed(page);
4325 page_cache_release(page);
4332 i915_gem_phys_pwrite(struct drm_device *dev,
4333 struct drm_i915_gem_object *obj,
4334 struct drm_i915_gem_pwrite *args,
4335 struct drm_file *file_priv)
4337 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4338 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
4340 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4341 unsigned long unwritten;
4343 /* The physical object once assigned is fixed for the lifetime
4344 * of the obj, so we can safely drop the lock and continue
4347 mutex_unlock(&dev->struct_mutex);
4348 unwritten = copy_from_user(vaddr, user_data, args->size);
4349 mutex_lock(&dev->struct_mutex);
4354 i915_gem_chipset_flush(dev);
4358 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4360 struct drm_i915_file_private *file_priv = file->driver_priv;
4362 /* Clean up our request list when the client is going away, so that
4363 * later retire_requests won't dereference our soon-to-be-gone
4366 spin_lock(&file_priv->mm.lock);
4367 while (!list_empty(&file_priv->mm.request_list)) {
4368 struct drm_i915_gem_request *request;
4370 request = list_first_entry(&file_priv->mm.request_list,
4371 struct drm_i915_gem_request,
4373 list_del(&request->client_list);
4374 request->file_priv = NULL;
4376 spin_unlock(&file_priv->mm.lock);
4379 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4381 if (!mutex_is_locked(mutex))
4384 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4385 return mutex->owner == task;
4387 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4393 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4395 struct drm_i915_private *dev_priv =
4396 container_of(shrinker,
4397 struct drm_i915_private,
4398 mm.inactive_shrinker);
4399 struct drm_device *dev = dev_priv->dev;
4400 struct drm_i915_gem_object *obj;
4401 int nr_to_scan = sc->nr_to_scan;
4405 if (!mutex_trylock(&dev->struct_mutex)) {
4406 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4413 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4415 i915_gem_shrink_all(dev_priv);
4419 list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list)
4420 if (obj->pages_pin_count == 0)
4421 cnt += obj->base.size >> PAGE_SHIFT;
4422 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
4423 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4424 cnt += obj->base.size >> PAGE_SHIFT;
4427 mutex_unlock(&dev->struct_mutex);