2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
43 bool map_and_fenceable,
45 static int i915_gem_phys_pwrite(struct drm_device *dev,
46 struct drm_i915_gem_object *obj,
47 struct drm_i915_gem_pwrite *args,
48 struct drm_file *file);
50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
51 struct drm_i915_gem_object *obj);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
53 struct drm_i915_fence_reg *fence,
56 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
57 struct shrink_control *sc);
58 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
59 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
65 i915_gem_release_mmap(obj);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj->fence_dirty = false;
71 obj->fence_reg = I915_FENCE_REG_NONE;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
78 dev_priv->mm.object_count++;
79 dev_priv->mm.object_memory += size;
82 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
85 dev_priv->mm.object_count--;
86 dev_priv->mm.object_memory -= size;
90 i915_gem_wait_for_error(struct i915_gpu_error *error)
94 #define EXIT_COND (!i915_reset_in_progress(error) || \
95 i915_terminally_wedged(error))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret = wait_event_interruptible_timeout(error->reset_queue,
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret < 0) {
118 int i915_mutex_lock_interruptible(struct drm_device *dev)
120 struct drm_i915_private *dev_priv = dev->dev_private;
123 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
127 ret = mutex_lock_interruptible(&dev->struct_mutex);
131 WARN_ON(i915_verify_lists(dev));
136 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
138 return obj->gtt_space && !obj->active;
142 i915_gem_init_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file)
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 struct drm_i915_gem_init *args = data;
148 if (drm_core_check_feature(dev, DRIVER_MODESET))
151 if (args->gtt_start >= args->gtt_end ||
152 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
155 /* GEM with user mode setting was never supported on ilk and later. */
156 if (INTEL_INFO(dev)->gen >= 5)
159 mutex_lock(&dev->struct_mutex);
160 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
162 dev_priv->gtt.mappable_end = args->gtt_end;
163 mutex_unlock(&dev->struct_mutex);
169 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
170 struct drm_file *file)
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct drm_i915_gem_get_aperture *args = data;
174 struct drm_i915_gem_object *obj;
178 mutex_lock(&dev->struct_mutex);
179 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
181 pinned += obj->gtt_space->size;
182 mutex_unlock(&dev->struct_mutex);
184 args->aper_size = dev_priv->gtt.total;
185 args->aper_available_size = args->aper_size - pinned;
190 void *i915_gem_object_alloc(struct drm_device *dev)
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
196 void i915_gem_object_free(struct drm_i915_gem_object *obj)
198 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
199 kmem_cache_free(dev_priv->slab, obj);
203 i915_gem_create(struct drm_file *file,
204 struct drm_device *dev,
208 struct drm_i915_gem_object *obj;
212 size = roundup(size, PAGE_SIZE);
216 /* Allocate the new object */
217 obj = i915_gem_alloc_object(dev, size);
221 ret = drm_gem_handle_create(file, &obj->base, &handle);
223 drm_gem_object_release(&obj->base);
224 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
225 i915_gem_object_free(obj);
229 /* drop reference from allocate - handle holds it now */
230 drm_gem_object_unreference(&obj->base);
231 trace_i915_gem_object_create(obj);
238 i915_gem_dumb_create(struct drm_file *file,
239 struct drm_device *dev,
240 struct drm_mode_create_dumb *args)
242 /* have to work out size/pitch and return them */
243 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
244 args->size = args->pitch * args->height;
245 return i915_gem_create(file, dev,
246 args->size, &args->handle);
249 int i915_gem_dumb_destroy(struct drm_file *file,
250 struct drm_device *dev,
253 return drm_gem_handle_delete(file, handle);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device *dev, void *data,
261 struct drm_file *file)
263 struct drm_i915_gem_create *args = data;
265 return i915_gem_create(file, dev,
266 args->size, &args->handle);
270 __copy_to_user_swizzled(char __user *cpu_vaddr,
271 const char *gpu_vaddr, int gpu_offset,
274 int ret, cpu_offset = 0;
277 int cacheline_end = ALIGN(gpu_offset + 1, 64);
278 int this_length = min(cacheline_end - gpu_offset, length);
279 int swizzled_gpu_offset = gpu_offset ^ 64;
281 ret = __copy_to_user(cpu_vaddr + cpu_offset,
282 gpu_vaddr + swizzled_gpu_offset,
287 cpu_offset += this_length;
288 gpu_offset += this_length;
289 length -= this_length;
296 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
297 const char __user *cpu_vaddr,
300 int ret, cpu_offset = 0;
303 int cacheline_end = ALIGN(gpu_offset + 1, 64);
304 int this_length = min(cacheline_end - gpu_offset, length);
305 int swizzled_gpu_offset = gpu_offset ^ 64;
307 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
308 cpu_vaddr + cpu_offset,
313 cpu_offset += this_length;
314 gpu_offset += this_length;
315 length -= this_length;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
326 char __user *user_data,
327 bool page_do_bit17_swizzling, bool needs_clflush)
332 if (unlikely(page_do_bit17_swizzling))
335 vaddr = kmap_atomic(page);
337 drm_clflush_virt_range(vaddr + shmem_page_offset,
339 ret = __copy_to_user_inatomic(user_data,
340 vaddr + shmem_page_offset,
342 kunmap_atomic(vaddr);
344 return ret ? -EFAULT : 0;
348 shmem_clflush_swizzled_range(char *addr, unsigned long length,
351 if (unlikely(swizzled)) {
352 unsigned long start = (unsigned long) addr;
353 unsigned long end = (unsigned long) addr + length;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start = round_down(start, 128);
360 end = round_up(end, 128);
362 drm_clflush_virt_range((void *)start, end - start);
364 drm_clflush_virt_range(addr, length);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
373 char __user *user_data,
374 bool page_do_bit17_swizzling, bool needs_clflush)
381 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
383 page_do_bit17_swizzling);
385 if (page_do_bit17_swizzling)
386 ret = __copy_to_user_swizzled(user_data,
387 vaddr, shmem_page_offset,
390 ret = __copy_to_user(user_data,
391 vaddr + shmem_page_offset,
395 return ret ? - EFAULT : 0;
399 i915_gem_shmem_pread(struct drm_device *dev,
400 struct drm_i915_gem_object *obj,
401 struct drm_i915_gem_pread *args,
402 struct drm_file *file)
404 char __user *user_data;
407 int shmem_page_offset, page_length, ret = 0;
408 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
410 int needs_clflush = 0;
411 struct sg_page_iter sg_iter;
413 user_data = to_user_ptr(args->data_ptr);
416 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
418 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj->cache_level == I915_CACHE_NONE)
425 if (obj->gtt_space) {
426 ret = i915_gem_object_set_to_gtt_domain(obj, false);
432 ret = i915_gem_object_get_pages(obj);
436 i915_gem_object_pin_pages(obj);
438 offset = args->offset;
440 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
441 offset >> PAGE_SHIFT) {
442 struct page *page = sg_page_iter_page(&sg_iter);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset = offset_in_page(offset);
453 page_length = remain;
454 if ((shmem_page_offset + page_length) > PAGE_SIZE)
455 page_length = PAGE_SIZE - shmem_page_offset;
457 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
458 (page_to_phys(page) & (1 << 17)) != 0;
460 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
461 user_data, page_do_bit17_swizzling,
466 mutex_unlock(&dev->struct_mutex);
469 ret = fault_in_multipages_writeable(user_data, remain);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
479 user_data, page_do_bit17_swizzling,
482 mutex_lock(&dev->struct_mutex);
485 mark_page_accessed(page);
490 remain -= page_length;
491 user_data += page_length;
492 offset += page_length;
496 i915_gem_object_unpin_pages(obj);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
508 struct drm_file *file)
510 struct drm_i915_gem_pread *args = data;
511 struct drm_i915_gem_object *obj;
517 if (!access_ok(VERIFY_WRITE,
518 to_user_ptr(args->data_ptr),
522 ret = i915_mutex_lock_interruptible(dev);
526 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
527 if (&obj->base == NULL) {
532 /* Bounds check source. */
533 if (args->offset > obj->base.size ||
534 args->size > obj->base.size - args->offset) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj->base.filp) {
547 trace_i915_gem_object_pread(obj, args->offset, args->size);
549 ret = i915_gem_shmem_pread(dev, obj, args, file);
552 drm_gem_object_unreference(&obj->base);
554 mutex_unlock(&dev->struct_mutex);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping *mapping,
564 loff_t page_base, int page_offset,
565 char __user *user_data,
568 void __iomem *vaddr_atomic;
570 unsigned long unwritten;
572 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr = (void __force*)vaddr_atomic + page_offset;
575 unwritten = __copy_from_user_inatomic_nocache(vaddr,
577 io_mapping_unmap_atomic(vaddr_atomic);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
587 struct drm_i915_gem_object *obj,
588 struct drm_i915_gem_pwrite *args,
589 struct drm_file *file)
591 drm_i915_private_t *dev_priv = dev->dev_private;
593 loff_t offset, page_base;
594 char __user *user_data;
595 int page_offset, page_length, ret;
597 ret = i915_gem_object_pin(obj, 0, true, true);
601 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 ret = i915_gem_object_put_fence(obj);
609 user_data = to_user_ptr(args->data_ptr);
612 offset = obj->gtt_offset + args->offset;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base = offset & PAGE_MASK;
622 page_offset = offset_in_page(offset);
623 page_length = remain;
624 if ((page_offset + remain) > PAGE_SIZE)
625 page_length = PAGE_SIZE - page_offset;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv->gtt.mappable, page_base,
632 page_offset, user_data, page_length)) {
637 remain -= page_length;
638 user_data += page_length;
639 offset += page_length;
643 i915_gem_object_unpin(obj);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
654 char __user *user_data,
655 bool page_do_bit17_swizzling,
656 bool needs_clflush_before,
657 bool needs_clflush_after)
662 if (unlikely(page_do_bit17_swizzling))
665 vaddr = kmap_atomic(page);
666 if (needs_clflush_before)
667 drm_clflush_virt_range(vaddr + shmem_page_offset,
669 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
672 if (needs_clflush_after)
673 drm_clflush_virt_range(vaddr + shmem_page_offset,
675 kunmap_atomic(vaddr);
677 return ret ? -EFAULT : 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
684 char __user *user_data,
685 bool page_do_bit17_swizzling,
686 bool needs_clflush_before,
687 bool needs_clflush_after)
693 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
694 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
696 page_do_bit17_swizzling);
697 if (page_do_bit17_swizzling)
698 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 ret = __copy_from_user(vaddr + shmem_page_offset,
705 if (needs_clflush_after)
706 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
708 page_do_bit17_swizzling);
711 return ret ? -EFAULT : 0;
715 i915_gem_shmem_pwrite(struct drm_device *dev,
716 struct drm_i915_gem_object *obj,
717 struct drm_i915_gem_pwrite *args,
718 struct drm_file *file)
722 char __user *user_data;
723 int shmem_page_offset, page_length, ret = 0;
724 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
725 int hit_slowpath = 0;
726 int needs_clflush_after = 0;
727 int needs_clflush_before = 0;
728 struct sg_page_iter sg_iter;
730 user_data = to_user_ptr(args->data_ptr);
733 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
735 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj->cache_level == I915_CACHE_NONE)
741 needs_clflush_after = 1;
742 if (obj->gtt_space) {
743 ret = i915_gem_object_set_to_gtt_domain(obj, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
751 && obj->cache_level == I915_CACHE_NONE)
752 needs_clflush_before = 1;
754 ret = i915_gem_object_get_pages(obj);
758 i915_gem_object_pin_pages(obj);
760 offset = args->offset;
763 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
764 offset >> PAGE_SHIFT) {
765 struct page *page = sg_page_iter_page(&sg_iter);
766 int partial_cacheline_write;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset = offset_in_page(offset);
778 page_length = remain;
779 if ((shmem_page_offset + page_length) > PAGE_SIZE)
780 page_length = PAGE_SIZE - shmem_page_offset;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write = needs_clflush_before &&
786 ((shmem_page_offset | page_length)
787 & (boot_cpu_data.x86_clflush_size - 1));
789 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
790 (page_to_phys(page) & (1 << 17)) != 0;
792 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
793 user_data, page_do_bit17_swizzling,
794 partial_cacheline_write,
795 needs_clflush_after);
800 mutex_unlock(&dev->struct_mutex);
801 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
802 user_data, page_do_bit17_swizzling,
803 partial_cacheline_write,
804 needs_clflush_after);
806 mutex_lock(&dev->struct_mutex);
809 set_page_dirty(page);
810 mark_page_accessed(page);
815 remain -= page_length;
816 user_data += page_length;
817 offset += page_length;
821 i915_gem_object_unpin_pages(obj);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after &&
830 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
831 i915_gem_clflush_object(obj);
832 i915_gem_chipset_flush(dev);
836 if (needs_clflush_after)
837 i915_gem_chipset_flush(dev);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file)
851 struct drm_i915_gem_pwrite *args = data;
852 struct drm_i915_gem_object *obj;
858 if (!access_ok(VERIFY_READ,
859 to_user_ptr(args->data_ptr),
863 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
868 ret = i915_mutex_lock_interruptible(dev);
872 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
873 if (&obj->base == NULL) {
878 /* Bounds check destination. */
879 if (args->offset > obj->base.size ||
880 args->size > obj->base.size - args->offset) {
885 /* prime objects have no backing filp to GEM pread/pwrite
888 if (!obj->base.filp) {
893 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
896 /* We can only do the GTT pwrite on untiled buffers, as otherwise
897 * it would end up going through the fenced access, and we'll get
898 * different detiling behavior between reading and writing.
899 * pread/pwrite currently are reading and writing from the CPU
900 * perspective, requiring manual detiling by the client.
903 ret = i915_gem_phys_pwrite(dev, obj, args, file);
907 if (obj->cache_level == I915_CACHE_NONE &&
908 obj->tiling_mode == I915_TILING_NONE &&
909 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
910 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
911 /* Note that the gtt paths might fail with non-page-backed user
912 * pointers (e.g. gtt mappings when moving data between
913 * textures). Fallback to the shmem path in that case. */
916 if (ret == -EFAULT || ret == -ENOSPC)
917 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
920 drm_gem_object_unreference(&obj->base);
922 mutex_unlock(&dev->struct_mutex);
927 i915_gem_check_wedge(struct i915_gpu_error *error,
930 if (i915_reset_in_progress(error)) {
931 /* Non-interruptible callers can't handle -EAGAIN, hence return
932 * -EIO unconditionally for these. */
936 /* Recovery complete, but the reset failed ... */
937 if (i915_terminally_wedged(error))
947 * Compare seqno against outstanding lazy request. Emit a request if they are
951 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
955 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
958 if (seqno == ring->outstanding_lazy_request)
959 ret = i915_add_request(ring, NULL);
965 * __wait_seqno - wait until execution of seqno has finished
966 * @ring: the ring expected to report seqno
968 * @reset_counter: reset sequence associated with the given seqno
969 * @interruptible: do an interruptible wait (normally yes)
970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
972 * Note: It is of utmost importance that the passed in seqno and reset_counter
973 * values have been read by the caller in an smp safe manner. Where read-side
974 * locks are involved, it is sufficient to read the reset_counter before
975 * unlocking the lock that protects the seqno. For lockless tricks, the
976 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
979 * Returns 0 if the seqno was found within the alloted time. Else returns the
980 * errno with remaining time filled in timeout argument.
982 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
983 unsigned reset_counter,
984 bool interruptible, struct timespec *timeout)
986 drm_i915_private_t *dev_priv = ring->dev->dev_private;
987 struct timespec before, now, wait_time={1,0};
988 unsigned long timeout_jiffies;
990 bool wait_forever = true;
993 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
996 trace_i915_gem_request_wait_begin(ring, seqno);
998 if (timeout != NULL) {
999 wait_time = *timeout;
1000 wait_forever = false;
1003 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1005 if (WARN_ON(!ring->irq_get(ring)))
1008 /* Record current time in case interrupted by signal, or wedged * */
1009 getrawmonotonic(&before);
1012 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013 i915_reset_in_progress(&dev_priv->gpu_error) || \
1014 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1017 end = wait_event_interruptible_timeout(ring->irq_queue,
1021 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1024 /* We need to check whether any gpu reset happened in between
1025 * the caller grabbing the seqno and now ... */
1026 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1029 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1031 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1034 } while (end == 0 && wait_forever);
1036 getrawmonotonic(&now);
1038 ring->irq_put(ring);
1039 trace_i915_gem_request_wait_end(ring, seqno);
1043 struct timespec sleep_time = timespec_sub(now, before);
1044 *timeout = timespec_sub(*timeout, sleep_time);
1045 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1046 set_normalized_timespec(timeout, 0, 0);
1051 case -EAGAIN: /* Wedged */
1052 case -ERESTARTSYS: /* Signal */
1054 case 0: /* Timeout */
1056 default: /* Completed */
1057 WARN_ON(end < 0); /* We're not aware of other errors */
1063 * Waits for a sequence number to be signaled, and cleans up the
1064 * request and object lists appropriately for that event.
1067 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1069 struct drm_device *dev = ring->dev;
1070 struct drm_i915_private *dev_priv = dev->dev_private;
1071 bool interruptible = dev_priv->mm.interruptible;
1074 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1077 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1081 ret = i915_gem_check_olr(ring, seqno);
1085 return __wait_seqno(ring, seqno,
1086 atomic_read(&dev_priv->gpu_error.reset_counter),
1087 interruptible, NULL);
1091 * Ensures that all rendering to the object has completed and the object is
1092 * safe to unbind from the GTT or access from the CPU.
1094 static __must_check int
1095 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1098 struct intel_ring_buffer *ring = obj->ring;
1102 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1106 ret = i915_wait_seqno(ring, seqno);
1110 i915_gem_retire_requests_ring(ring);
1112 /* Manually manage the write flush as we may have not yet
1113 * retired the buffer.
1115 if (obj->last_write_seqno &&
1116 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1117 obj->last_write_seqno = 0;
1118 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1124 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1125 * as the object state may change during this call.
1127 static __must_check int
1128 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1131 struct drm_device *dev = obj->base.dev;
1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133 struct intel_ring_buffer *ring = obj->ring;
1134 unsigned reset_counter;
1138 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1139 BUG_ON(!dev_priv->mm.interruptible);
1141 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1145 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1149 ret = i915_gem_check_olr(ring, seqno);
1153 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1154 mutex_unlock(&dev->struct_mutex);
1155 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1156 mutex_lock(&dev->struct_mutex);
1158 i915_gem_retire_requests_ring(ring);
1160 /* Manually manage the write flush as we may have not yet
1161 * retired the buffer.
1163 if (obj->last_write_seqno &&
1164 i915_seqno_passed(seqno, obj->last_write_seqno)) {
1165 obj->last_write_seqno = 0;
1166 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1173 * Called when user space prepares to use an object with the CPU, either
1174 * through the mmap ioctl's mapping or a GTT mapping.
1177 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1178 struct drm_file *file)
1180 struct drm_i915_gem_set_domain *args = data;
1181 struct drm_i915_gem_object *obj;
1182 uint32_t read_domains = args->read_domains;
1183 uint32_t write_domain = args->write_domain;
1186 /* Only handle setting domains to types used by the CPU. */
1187 if (write_domain & I915_GEM_GPU_DOMAINS)
1190 if (read_domains & I915_GEM_GPU_DOMAINS)
1193 /* Having something in the write domain implies it's in the read
1194 * domain, and only that read domain. Enforce that in the request.
1196 if (write_domain != 0 && read_domains != write_domain)
1199 ret = i915_mutex_lock_interruptible(dev);
1203 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1204 if (&obj->base == NULL) {
1209 /* Try to flush the object off the GPU without holding the lock.
1210 * We will repeat the flush holding the lock in the normal manner
1211 * to catch cases where we are gazumped.
1213 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1217 if (read_domains & I915_GEM_DOMAIN_GTT) {
1218 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1220 /* Silently promote "you're not bound, there was nothing to do"
1221 * to success, since the client was just asking us to
1222 * make sure everything was done.
1227 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1231 drm_gem_object_unreference(&obj->base);
1233 mutex_unlock(&dev->struct_mutex);
1238 * Called when user space has done writes to this buffer
1241 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1242 struct drm_file *file)
1244 struct drm_i915_gem_sw_finish *args = data;
1245 struct drm_i915_gem_object *obj;
1248 ret = i915_mutex_lock_interruptible(dev);
1252 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1253 if (&obj->base == NULL) {
1258 /* Pinned buffers may be scanout, so flush the cache */
1260 i915_gem_object_flush_cpu_write_domain(obj);
1262 drm_gem_object_unreference(&obj->base);
1264 mutex_unlock(&dev->struct_mutex);
1269 * Maps the contents of an object, returning the address it is mapped
1272 * While the mapping holds a reference on the contents of the object, it doesn't
1273 * imply a ref on the object itself.
1276 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1277 struct drm_file *file)
1279 struct drm_i915_gem_mmap *args = data;
1280 struct drm_gem_object *obj;
1283 obj = drm_gem_object_lookup(dev, file, args->handle);
1287 /* prime objects have no backing filp to GEM mmap
1291 drm_gem_object_unreference_unlocked(obj);
1295 addr = vm_mmap(obj->filp, 0, args->size,
1296 PROT_READ | PROT_WRITE, MAP_SHARED,
1298 drm_gem_object_unreference_unlocked(obj);
1299 if (IS_ERR((void *)addr))
1302 args->addr_ptr = (uint64_t) addr;
1308 * i915_gem_fault - fault a page into the GTT
1309 * vma: VMA in question
1312 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1313 * from userspace. The fault handler takes care of binding the object to
1314 * the GTT (if needed), allocating and programming a fence register (again,
1315 * only if needed based on whether the old reg is still valid or the object
1316 * is tiled) and inserting a new PTE into the faulting process.
1318 * Note that the faulting process may involve evicting existing objects
1319 * from the GTT and/or fence registers to make room. So performance may
1320 * suffer if the GTT working set is large or there are few fence registers
1323 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1325 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1326 struct drm_device *dev = obj->base.dev;
1327 drm_i915_private_t *dev_priv = dev->dev_private;
1328 pgoff_t page_offset;
1331 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1333 /* We don't use vmf->pgoff since that has the fake offset */
1334 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1337 ret = i915_mutex_lock_interruptible(dev);
1341 trace_i915_gem_object_fault(obj, page_offset, true, write);
1343 /* Access to snoopable pages through the GTT is incoherent. */
1344 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1349 /* Now bind it into the GTT if needed */
1350 ret = i915_gem_object_pin(obj, 0, true, false);
1354 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1358 ret = i915_gem_object_get_fence(obj);
1362 obj->fault_mappable = true;
1364 pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
1367 /* Finally, remap it using the new GTT offset */
1368 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1370 i915_gem_object_unpin(obj);
1372 mutex_unlock(&dev->struct_mutex);
1376 /* If this -EIO is due to a gpu hang, give the reset code a
1377 * chance to clean up the mess. Otherwise return the proper
1379 if (i915_terminally_wedged(&dev_priv->gpu_error))
1380 return VM_FAULT_SIGBUS;
1382 /* Give the error handler a chance to run and move the
1383 * objects off the GPU active list. Next time we service the
1384 * fault, we should be able to transition the page into the
1385 * GTT without touching the GPU (and so avoid further
1386 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1387 * with coherency, just lost writes.
1395 * EBUSY is ok: this just means that another thread
1396 * already did the job.
1398 return VM_FAULT_NOPAGE;
1400 return VM_FAULT_OOM;
1402 return VM_FAULT_SIGBUS;
1404 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1405 return VM_FAULT_SIGBUS;
1410 * i915_gem_release_mmap - remove physical page mappings
1411 * @obj: obj in question
1413 * Preserve the reservation of the mmapping with the DRM core code, but
1414 * relinquish ownership of the pages back to the system.
1416 * It is vital that we remove the page mapping if we have mapped a tiled
1417 * object through the GTT and then lose the fence register due to
1418 * resource pressure. Similarly if the object has been moved out of the
1419 * aperture, than pages mapped into userspace must be revoked. Removing the
1420 * mapping will then trigger a page fault on the next user access, allowing
1421 * fixup by i915_gem_fault().
1424 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1426 if (!obj->fault_mappable)
1429 if (obj->base.dev->dev_mapping)
1430 unmap_mapping_range(obj->base.dev->dev_mapping,
1431 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1434 obj->fault_mappable = false;
1438 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1442 if (INTEL_INFO(dev)->gen >= 4 ||
1443 tiling_mode == I915_TILING_NONE)
1446 /* Previous chips need a power-of-two fence region when tiling */
1447 if (INTEL_INFO(dev)->gen == 3)
1448 gtt_size = 1024*1024;
1450 gtt_size = 512*1024;
1452 while (gtt_size < size)
1459 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1460 * @obj: object to check
1462 * Return the required GTT alignment for an object, taking into account
1463 * potential fence register mapping.
1466 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1467 int tiling_mode, bool fenced)
1470 * Minimum alignment is 4k (GTT page size), but might be greater
1471 * if a fence register is needed for the object.
1473 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1474 tiling_mode == I915_TILING_NONE)
1478 * Previous chips need to be aligned to the size of the smallest
1479 * fence register that can contain the object.
1481 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1484 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1486 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1489 if (obj->base.map_list.map)
1492 dev_priv->mm.shrinker_no_lock_stealing = true;
1494 ret = drm_gem_create_mmap_offset(&obj->base);
1498 /* Badly fragmented mmap space? The only way we can recover
1499 * space is by destroying unwanted objects. We can't randomly release
1500 * mmap_offsets as userspace expects them to be persistent for the
1501 * lifetime of the objects. The closest we can is to release the
1502 * offsets on purgeable objects by truncating it and marking it purged,
1503 * which prevents userspace from ever using that object again.
1505 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1506 ret = drm_gem_create_mmap_offset(&obj->base);
1510 i915_gem_shrink_all(dev_priv);
1511 ret = drm_gem_create_mmap_offset(&obj->base);
1513 dev_priv->mm.shrinker_no_lock_stealing = false;
1518 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1520 if (!obj->base.map_list.map)
1523 drm_gem_free_mmap_offset(&obj->base);
1527 i915_gem_mmap_gtt(struct drm_file *file,
1528 struct drm_device *dev,
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533 struct drm_i915_gem_object *obj;
1536 ret = i915_mutex_lock_interruptible(dev);
1540 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1541 if (&obj->base == NULL) {
1546 if (obj->base.size > dev_priv->gtt.mappable_end) {
1551 if (obj->madv != I915_MADV_WILLNEED) {
1552 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1557 ret = i915_gem_object_create_mmap_offset(obj);
1561 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1564 drm_gem_object_unreference(&obj->base);
1566 mutex_unlock(&dev->struct_mutex);
1571 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1573 * @data: GTT mapping ioctl data
1574 * @file: GEM object info
1576 * Simply returns the fake offset to userspace so it can mmap it.
1577 * The mmap call will end up in drm_gem_mmap(), which will set things
1578 * up so we can get faults in the handler above.
1580 * The fault handler will take care of binding the object into the GTT
1581 * (since it may have been evicted to make room for something), allocating
1582 * a fence register, and mapping the appropriate aperture address into
1586 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1587 struct drm_file *file)
1589 struct drm_i915_gem_mmap_gtt *args = data;
1591 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1594 /* Immediately discard the backing storage */
1596 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1598 struct inode *inode;
1600 i915_gem_object_free_mmap_offset(obj);
1602 if (obj->base.filp == NULL)
1605 /* Our goal here is to return as much of the memory as
1606 * is possible back to the system as we are called from OOM.
1607 * To do this we must instruct the shmfs to drop all of its
1608 * backing pages, *now*.
1610 inode = file_inode(obj->base.filp);
1611 shmem_truncate_range(inode, 0, (loff_t)-1);
1613 obj->madv = __I915_MADV_PURGED;
1617 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1619 return obj->madv == I915_MADV_DONTNEED;
1623 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1625 struct sg_page_iter sg_iter;
1628 BUG_ON(obj->madv == __I915_MADV_PURGED);
1630 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1632 /* In the event of a disaster, abandon all caches and
1633 * hope for the best.
1635 WARN_ON(ret != -EIO);
1636 i915_gem_clflush_object(obj);
1637 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1640 if (i915_gem_object_needs_bit17_swizzle(obj))
1641 i915_gem_object_save_bit_17_swizzle(obj);
1643 if (obj->madv == I915_MADV_DONTNEED)
1646 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1647 struct page *page = sg_page_iter_page(&sg_iter);
1650 set_page_dirty(page);
1652 if (obj->madv == I915_MADV_WILLNEED)
1653 mark_page_accessed(page);
1655 page_cache_release(page);
1659 sg_free_table(obj->pages);
1664 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1666 const struct drm_i915_gem_object_ops *ops = obj->ops;
1668 if (obj->pages == NULL)
1671 BUG_ON(obj->gtt_space);
1673 if (obj->pages_pin_count)
1676 /* ->put_pages might need to allocate memory for the bit17 swizzle
1677 * array, hence protect them from being reaped by removing them from gtt
1679 list_del(&obj->global_list);
1681 ops->put_pages(obj);
1684 if (i915_gem_object_is_purgeable(obj))
1685 i915_gem_object_truncate(obj);
1691 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1692 bool purgeable_only)
1694 struct drm_i915_gem_object *obj, *next;
1697 list_for_each_entry_safe(obj, next,
1698 &dev_priv->mm.unbound_list,
1700 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1701 i915_gem_object_put_pages(obj) == 0) {
1702 count += obj->base.size >> PAGE_SHIFT;
1703 if (count >= target)
1708 list_for_each_entry_safe(obj, next,
1709 &dev_priv->mm.inactive_list,
1711 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1712 i915_gem_object_unbind(obj) == 0 &&
1713 i915_gem_object_put_pages(obj) == 0) {
1714 count += obj->base.size >> PAGE_SHIFT;
1715 if (count >= target)
1724 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1726 return __i915_gem_shrink(dev_priv, target, true);
1730 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1732 struct drm_i915_gem_object *obj, *next;
1734 i915_gem_evict_everything(dev_priv->dev);
1736 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1738 i915_gem_object_put_pages(obj);
1742 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1744 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1746 struct address_space *mapping;
1747 struct sg_table *st;
1748 struct scatterlist *sg;
1749 struct sg_page_iter sg_iter;
1751 unsigned long last_pfn = 0; /* suppress gcc warning */
1754 /* Assert that the object is not currently in any GPU domain. As it
1755 * wasn't in the GTT, there shouldn't be any way it could have been in
1758 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1759 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1761 st = kmalloc(sizeof(*st), GFP_KERNEL);
1765 page_count = obj->base.size / PAGE_SIZE;
1766 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1772 /* Get the list of pages out of our struct file. They'll be pinned
1773 * at this point until we release them.
1775 * Fail silently without starting the shrinker
1777 mapping = file_inode(obj->base.filp)->i_mapping;
1778 gfp = mapping_gfp_mask(mapping);
1779 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1780 gfp &= ~(__GFP_IO | __GFP_WAIT);
1783 for (i = 0; i < page_count; i++) {
1784 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1786 i915_gem_purge(dev_priv, page_count);
1787 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1790 /* We've tried hard to allocate the memory by reaping
1791 * our own buffer, now let the real VM do its job and
1792 * go down in flames if truly OOM.
1794 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1795 gfp |= __GFP_IO | __GFP_WAIT;
1797 i915_gem_shrink_all(dev_priv);
1798 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1802 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1803 gfp &= ~(__GFP_IO | __GFP_WAIT);
1806 if (!i || page_to_pfn(page) != last_pfn + 1) {
1810 sg_set_page(sg, page, PAGE_SIZE, 0);
1812 sg->length += PAGE_SIZE;
1814 last_pfn = page_to_pfn(page);
1820 if (i915_gem_object_needs_bit17_swizzle(obj))
1821 i915_gem_object_do_bit_17_swizzle(obj);
1827 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1828 page_cache_release(sg_page_iter_page(&sg_iter));
1831 return PTR_ERR(page);
1834 /* Ensure that the associated pages are gathered from the backing storage
1835 * and pinned into our object. i915_gem_object_get_pages() may be called
1836 * multiple times before they are released by a single call to
1837 * i915_gem_object_put_pages() - once the pages are no longer referenced
1838 * either as a result of memory pressure (reaping pages under the shrinker)
1839 * or as the object is itself released.
1842 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1844 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1845 const struct drm_i915_gem_object_ops *ops = obj->ops;
1851 if (obj->madv != I915_MADV_WILLNEED) {
1852 DRM_ERROR("Attempting to obtain a purgeable object\n");
1856 BUG_ON(obj->pages_pin_count);
1858 ret = ops->get_pages(obj);
1862 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1867 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1868 struct intel_ring_buffer *ring)
1870 struct drm_device *dev = obj->base.dev;
1871 struct drm_i915_private *dev_priv = dev->dev_private;
1872 u32 seqno = intel_ring_get_seqno(ring);
1874 BUG_ON(ring == NULL);
1877 /* Add a reference if we're newly entering the active list. */
1879 drm_gem_object_reference(&obj->base);
1883 /* Move from whatever list we were on to the tail of execution. */
1884 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1885 list_move_tail(&obj->ring_list, &ring->active_list);
1887 obj->last_read_seqno = seqno;
1889 if (obj->fenced_gpu_access) {
1890 obj->last_fenced_seqno = seqno;
1892 /* Bump MRU to take account of the delayed flush */
1893 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1894 struct drm_i915_fence_reg *reg;
1896 reg = &dev_priv->fence_regs[obj->fence_reg];
1897 list_move_tail(®->lru_list,
1898 &dev_priv->mm.fence_list);
1904 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1906 struct drm_device *dev = obj->base.dev;
1907 struct drm_i915_private *dev_priv = dev->dev_private;
1909 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1910 BUG_ON(!obj->active);
1912 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1914 list_del_init(&obj->ring_list);
1917 obj->last_read_seqno = 0;
1918 obj->last_write_seqno = 0;
1919 obj->base.write_domain = 0;
1921 obj->last_fenced_seqno = 0;
1922 obj->fenced_gpu_access = false;
1925 drm_gem_object_unreference(&obj->base);
1927 WARN_ON(i915_verify_lists(dev));
1931 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1933 struct drm_i915_private *dev_priv = dev->dev_private;
1934 struct intel_ring_buffer *ring;
1937 /* Carefully retire all requests without writing to the rings */
1938 for_each_ring(ring, dev_priv, i) {
1939 ret = intel_ring_idle(ring);
1943 i915_gem_retire_requests(dev);
1945 /* Finally reset hw state */
1946 for_each_ring(ring, dev_priv, i) {
1947 intel_ring_init_seqno(ring, seqno);
1949 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1950 ring->sync_seqno[j] = 0;
1956 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1958 struct drm_i915_private *dev_priv = dev->dev_private;
1964 /* HWS page needs to be set less than what we
1965 * will inject to ring
1967 ret = i915_gem_init_seqno(dev, seqno - 1);
1971 /* Carefully set the last_seqno value so that wrap
1972 * detection still works
1974 dev_priv->next_seqno = seqno;
1975 dev_priv->last_seqno = seqno - 1;
1976 if (dev_priv->last_seqno == 0)
1977 dev_priv->last_seqno--;
1983 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1987 /* reserve 0 for non-seqno */
1988 if (dev_priv->next_seqno == 0) {
1989 int ret = i915_gem_init_seqno(dev, 0);
1993 dev_priv->next_seqno = 1;
1996 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2000 int __i915_add_request(struct intel_ring_buffer *ring,
2001 struct drm_file *file,
2002 struct drm_i915_gem_object *obj,
2005 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2006 struct drm_i915_gem_request *request;
2007 u32 request_ring_position, request_start;
2011 request_start = intel_ring_get_tail(ring);
2013 * Emit any outstanding flushes - execbuf can fail to emit the flush
2014 * after having emitted the batchbuffer command. Hence we need to fix
2015 * things up similar to emitting the lazy request. The difference here
2016 * is that the flush _must_ happen before the next request, no matter
2019 ret = intel_ring_flush_all_caches(ring);
2023 request = kmalloc(sizeof(*request), GFP_KERNEL);
2024 if (request == NULL)
2028 /* Record the position of the start of the request so that
2029 * should we detect the updated seqno part-way through the
2030 * GPU processing the request, we never over-estimate the
2031 * position of the head.
2033 request_ring_position = intel_ring_get_tail(ring);
2035 ret = ring->add_request(ring);
2041 request->seqno = intel_ring_get_seqno(ring);
2042 request->ring = ring;
2043 request->head = request_start;
2044 request->tail = request_ring_position;
2045 request->ctx = ring->last_context;
2046 request->batch_obj = obj;
2048 /* Whilst this request exists, batch_obj will be on the
2049 * active_list, and so will hold the active reference. Only when this
2050 * request is retired will the the batch_obj be moved onto the
2051 * inactive_list and lose its active reference. Hence we do not need
2052 * to explicitly hold another reference here.
2056 i915_gem_context_reference(request->ctx);
2058 request->emitted_jiffies = jiffies;
2059 was_empty = list_empty(&ring->request_list);
2060 list_add_tail(&request->list, &ring->request_list);
2061 request->file_priv = NULL;
2064 struct drm_i915_file_private *file_priv = file->driver_priv;
2066 spin_lock(&file_priv->mm.lock);
2067 request->file_priv = file_priv;
2068 list_add_tail(&request->client_list,
2069 &file_priv->mm.request_list);
2070 spin_unlock(&file_priv->mm.lock);
2073 trace_i915_gem_request_add(ring, request->seqno);
2074 ring->outstanding_lazy_request = 0;
2076 if (!dev_priv->mm.suspended) {
2077 if (i915_enable_hangcheck) {
2078 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2079 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2082 queue_delayed_work(dev_priv->wq,
2083 &dev_priv->mm.retire_work,
2084 round_jiffies_up_relative(HZ));
2085 intel_mark_busy(dev_priv->dev);
2090 *out_seqno = request->seqno;
2095 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2097 struct drm_i915_file_private *file_priv = request->file_priv;
2102 spin_lock(&file_priv->mm.lock);
2103 if (request->file_priv) {
2104 list_del(&request->client_list);
2105 request->file_priv = NULL;
2107 spin_unlock(&file_priv->mm.lock);
2110 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj)
2112 if (acthd >= obj->gtt_offset &&
2113 acthd < obj->gtt_offset + obj->base.size)
2119 static bool i915_head_inside_request(const u32 acthd_unmasked,
2120 const u32 request_start,
2121 const u32 request_end)
2123 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2125 if (request_start < request_end) {
2126 if (acthd >= request_start && acthd < request_end)
2128 } else if (request_start > request_end) {
2129 if (acthd >= request_start || acthd < request_end)
2136 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2137 const u32 acthd, bool *inside)
2139 /* There is a possibility that unmasked head address
2140 * pointing inside the ring, matches the batch_obj address range.
2141 * However this is extremely unlikely.
2144 if (request->batch_obj) {
2145 if (i915_head_inside_object(acthd, request->batch_obj)) {
2151 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2159 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2160 struct drm_i915_gem_request *request,
2163 struct i915_ctx_hang_stats *hs = NULL;
2164 bool inside, guilty;
2166 /* Innocent until proven guilty */
2169 if (ring->hangcheck.action != wait &&
2170 i915_request_guilty(request, acthd, &inside)) {
2171 DRM_ERROR("%s hung %s bo (0x%x ctx %d) at 0x%x\n",
2173 inside ? "inside" : "flushing",
2174 request->batch_obj ?
2175 request->batch_obj->gtt_offset : 0,
2176 request->ctx ? request->ctx->id : 0,
2182 /* If contexts are disabled or this is the default context, use
2183 * file_priv->reset_state
2185 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2186 hs = &request->ctx->hang_stats;
2187 else if (request->file_priv)
2188 hs = &request->file_priv->hang_stats;
2194 hs->batch_pending++;
2198 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2200 list_del(&request->list);
2201 i915_gem_request_remove_from_client(request);
2204 i915_gem_context_unreference(request->ctx);
2209 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2210 struct intel_ring_buffer *ring)
2212 u32 completed_seqno;
2215 acthd = intel_ring_get_active_head(ring);
2216 completed_seqno = ring->get_seqno(ring, false);
2218 while (!list_empty(&ring->request_list)) {
2219 struct drm_i915_gem_request *request;
2221 request = list_first_entry(&ring->request_list,
2222 struct drm_i915_gem_request,
2225 if (request->seqno > completed_seqno)
2226 i915_set_reset_status(ring, request, acthd);
2228 i915_gem_free_request(request);
2231 while (!list_empty(&ring->active_list)) {
2232 struct drm_i915_gem_object *obj;
2234 obj = list_first_entry(&ring->active_list,
2235 struct drm_i915_gem_object,
2238 i915_gem_object_move_to_inactive(obj);
2242 static void i915_gem_reset_fences(struct drm_device *dev)
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2247 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2248 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2251 i915_gem_object_fence_lost(reg->obj);
2253 i915_gem_write_fence(dev, i, NULL);
2257 INIT_LIST_HEAD(®->lru_list);
2260 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
2263 void i915_gem_reset(struct drm_device *dev)
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct drm_i915_gem_object *obj;
2267 struct intel_ring_buffer *ring;
2270 for_each_ring(ring, dev_priv, i)
2271 i915_gem_reset_ring_lists(dev_priv, ring);
2273 /* Move everything out of the GPU domains to ensure we do any
2274 * necessary invalidation upon reuse.
2276 list_for_each_entry(obj,
2277 &dev_priv->mm.inactive_list,
2280 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2283 /* The fence registers are invalidated so clear them out */
2284 i915_gem_reset_fences(dev);
2288 * This function clears the request list as sequence numbers are passed.
2291 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2295 if (list_empty(&ring->request_list))
2298 WARN_ON(i915_verify_lists(ring->dev));
2300 seqno = ring->get_seqno(ring, true);
2302 while (!list_empty(&ring->request_list)) {
2303 struct drm_i915_gem_request *request;
2305 request = list_first_entry(&ring->request_list,
2306 struct drm_i915_gem_request,
2309 if (!i915_seqno_passed(seqno, request->seqno))
2312 trace_i915_gem_request_retire(ring, request->seqno);
2313 /* We know the GPU must have read the request to have
2314 * sent us the seqno + interrupt, so use the position
2315 * of tail of the request to update the last known position
2318 ring->last_retired_head = request->tail;
2320 i915_gem_free_request(request);
2323 /* Move any buffers on the active list that are no longer referenced
2324 * by the ringbuffer to the flushing/inactive lists as appropriate.
2326 while (!list_empty(&ring->active_list)) {
2327 struct drm_i915_gem_object *obj;
2329 obj = list_first_entry(&ring->active_list,
2330 struct drm_i915_gem_object,
2333 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2336 i915_gem_object_move_to_inactive(obj);
2339 if (unlikely(ring->trace_irq_seqno &&
2340 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2341 ring->irq_put(ring);
2342 ring->trace_irq_seqno = 0;
2345 WARN_ON(i915_verify_lists(ring->dev));
2349 i915_gem_retire_requests(struct drm_device *dev)
2351 drm_i915_private_t *dev_priv = dev->dev_private;
2352 struct intel_ring_buffer *ring;
2355 for_each_ring(ring, dev_priv, i)
2356 i915_gem_retire_requests_ring(ring);
2360 i915_gem_retire_work_handler(struct work_struct *work)
2362 drm_i915_private_t *dev_priv;
2363 struct drm_device *dev;
2364 struct intel_ring_buffer *ring;
2368 dev_priv = container_of(work, drm_i915_private_t,
2369 mm.retire_work.work);
2370 dev = dev_priv->dev;
2372 /* Come back later if the device is busy... */
2373 if (!mutex_trylock(&dev->struct_mutex)) {
2374 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2375 round_jiffies_up_relative(HZ));
2379 i915_gem_retire_requests(dev);
2381 /* Send a periodic flush down the ring so we don't hold onto GEM
2382 * objects indefinitely.
2385 for_each_ring(ring, dev_priv, i) {
2386 if (ring->gpu_caches_dirty)
2387 i915_add_request(ring, NULL);
2389 idle &= list_empty(&ring->request_list);
2392 if (!dev_priv->mm.suspended && !idle)
2393 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2394 round_jiffies_up_relative(HZ));
2396 intel_mark_idle(dev);
2398 mutex_unlock(&dev->struct_mutex);
2402 * Ensures that an object will eventually get non-busy by flushing any required
2403 * write domains, emitting any outstanding lazy request and retiring and
2404 * completed requests.
2407 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2412 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2416 i915_gem_retire_requests_ring(obj->ring);
2423 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2424 * @DRM_IOCTL_ARGS: standard ioctl arguments
2426 * Returns 0 if successful, else an error is returned with the remaining time in
2427 * the timeout parameter.
2428 * -ETIME: object is still busy after timeout
2429 * -ERESTARTSYS: signal interrupted the wait
2430 * -ENONENT: object doesn't exist
2431 * Also possible, but rare:
2432 * -EAGAIN: GPU wedged
2434 * -ENODEV: Internal IRQ fail
2435 * -E?: The add request failed
2437 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2438 * non-zero timeout parameter the wait ioctl will wait for the given number of
2439 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2440 * without holding struct_mutex the object may become re-busied before this
2441 * function completes. A similar but shorter * race condition exists in the busy
2445 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2447 drm_i915_private_t *dev_priv = dev->dev_private;
2448 struct drm_i915_gem_wait *args = data;
2449 struct drm_i915_gem_object *obj;
2450 struct intel_ring_buffer *ring = NULL;
2451 struct timespec timeout_stack, *timeout = NULL;
2452 unsigned reset_counter;
2456 if (args->timeout_ns >= 0) {
2457 timeout_stack = ns_to_timespec(args->timeout_ns);
2458 timeout = &timeout_stack;
2461 ret = i915_mutex_lock_interruptible(dev);
2465 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2466 if (&obj->base == NULL) {
2467 mutex_unlock(&dev->struct_mutex);
2471 /* Need to make sure the object gets inactive eventually. */
2472 ret = i915_gem_object_flush_active(obj);
2477 seqno = obj->last_read_seqno;
2484 /* Do this after OLR check to make sure we make forward progress polling
2485 * on this IOCTL with a 0 timeout (like busy ioctl)
2487 if (!args->timeout_ns) {
2492 drm_gem_object_unreference(&obj->base);
2493 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2494 mutex_unlock(&dev->struct_mutex);
2496 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2498 args->timeout_ns = timespec_to_ns(timeout);
2502 drm_gem_object_unreference(&obj->base);
2503 mutex_unlock(&dev->struct_mutex);
2508 * i915_gem_object_sync - sync an object to a ring.
2510 * @obj: object which may be in use on another ring.
2511 * @to: ring we wish to use the object on. May be NULL.
2513 * This code is meant to abstract object synchronization with the GPU.
2514 * Calling with NULL implies synchronizing the object with the CPU
2515 * rather than a particular GPU ring.
2517 * Returns 0 if successful, else propagates up the lower layer error.
2520 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2521 struct intel_ring_buffer *to)
2523 struct intel_ring_buffer *from = obj->ring;
2527 if (from == NULL || to == from)
2530 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2531 return i915_gem_object_wait_rendering(obj, false);
2533 idx = intel_ring_sync_index(from, to);
2535 seqno = obj->last_read_seqno;
2536 if (seqno <= from->sync_seqno[idx])
2539 ret = i915_gem_check_olr(obj->ring, seqno);
2543 ret = to->sync_to(to, from, seqno);
2545 /* We use last_read_seqno because sync_to()
2546 * might have just caused seqno wrap under
2549 from->sync_seqno[idx] = obj->last_read_seqno;
2554 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2556 u32 old_write_domain, old_read_domains;
2558 /* Force a pagefault for domain tracking on next user access */
2559 i915_gem_release_mmap(obj);
2561 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2564 /* Wait for any direct GTT access to complete */
2567 old_read_domains = obj->base.read_domains;
2568 old_write_domain = obj->base.write_domain;
2570 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2571 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2573 trace_i915_gem_object_change_domain(obj,
2579 * Unbinds an object from the GTT aperture.
2582 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2584 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2587 if (obj->gtt_space == NULL)
2593 BUG_ON(obj->pages == NULL);
2595 ret = i915_gem_object_finish_gpu(obj);
2598 /* Continue on if we fail due to EIO, the GPU is hung so we
2599 * should be safe and we need to cleanup or else we might
2600 * cause memory corruption through use-after-free.
2603 i915_gem_object_finish_gtt(obj);
2605 /* release the fence reg _after_ flushing */
2606 ret = i915_gem_object_put_fence(obj);
2610 trace_i915_gem_object_unbind(obj);
2612 if (obj->has_global_gtt_mapping)
2613 i915_gem_gtt_unbind_object(obj);
2614 if (obj->has_aliasing_ppgtt_mapping) {
2615 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2616 obj->has_aliasing_ppgtt_mapping = 0;
2618 i915_gem_gtt_finish_object(obj);
2619 i915_gem_object_unpin_pages(obj);
2621 list_del(&obj->mm_list);
2622 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2623 /* Avoid an unnecessary call to unbind on rebind. */
2624 obj->map_and_fenceable = true;
2626 drm_mm_put_block(obj->gtt_space);
2627 obj->gtt_space = NULL;
2628 obj->gtt_offset = 0;
2633 int i915_gpu_idle(struct drm_device *dev)
2635 drm_i915_private_t *dev_priv = dev->dev_private;
2636 struct intel_ring_buffer *ring;
2639 /* Flush everything onto the inactive list. */
2640 for_each_ring(ring, dev_priv, i) {
2641 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2645 ret = intel_ring_idle(ring);
2653 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2654 struct drm_i915_gem_object *obj)
2656 drm_i915_private_t *dev_priv = dev->dev_private;
2658 int fence_pitch_shift;
2661 if (INTEL_INFO(dev)->gen >= 6) {
2662 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2663 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2665 fence_reg = FENCE_REG_965_0;
2666 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2670 u32 size = obj->gtt_space->size;
2672 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2674 val |= obj->gtt_offset & 0xfffff000;
2675 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2676 if (obj->tiling_mode == I915_TILING_Y)
2677 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2678 val |= I965_FENCE_REG_VALID;
2682 fence_reg += reg * 8;
2683 I915_WRITE64(fence_reg, val);
2684 POSTING_READ(fence_reg);
2687 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2688 struct drm_i915_gem_object *obj)
2690 drm_i915_private_t *dev_priv = dev->dev_private;
2694 u32 size = obj->gtt_space->size;
2698 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2699 (size & -size) != size ||
2700 (obj->gtt_offset & (size - 1)),
2701 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2702 obj->gtt_offset, obj->map_and_fenceable, size);
2704 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2709 /* Note: pitch better be a power of two tile widths */
2710 pitch_val = obj->stride / tile_width;
2711 pitch_val = ffs(pitch_val) - 1;
2713 val = obj->gtt_offset;
2714 if (obj->tiling_mode == I915_TILING_Y)
2715 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2716 val |= I915_FENCE_SIZE_BITS(size);
2717 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2718 val |= I830_FENCE_REG_VALID;
2723 reg = FENCE_REG_830_0 + reg * 4;
2725 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2727 I915_WRITE(reg, val);
2731 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2732 struct drm_i915_gem_object *obj)
2734 drm_i915_private_t *dev_priv = dev->dev_private;
2738 u32 size = obj->gtt_space->size;
2741 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2742 (size & -size) != size ||
2743 (obj->gtt_offset & (size - 1)),
2744 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2745 obj->gtt_offset, size);
2747 pitch_val = obj->stride / 128;
2748 pitch_val = ffs(pitch_val) - 1;
2750 val = obj->gtt_offset;
2751 if (obj->tiling_mode == I915_TILING_Y)
2752 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2753 val |= I830_FENCE_SIZE_BITS(size);
2754 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2755 val |= I830_FENCE_REG_VALID;
2759 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2760 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2763 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2765 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2768 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2769 struct drm_i915_gem_object *obj)
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2773 /* Ensure that all CPU reads are completed before installing a fence
2774 * and all writes before removing the fence.
2776 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2779 switch (INTEL_INFO(dev)->gen) {
2783 case 4: i965_write_fence_reg(dev, reg, obj); break;
2784 case 3: i915_write_fence_reg(dev, reg, obj); break;
2785 case 2: i830_write_fence_reg(dev, reg, obj); break;
2789 /* And similarly be paranoid that no direct access to this region
2790 * is reordered to before the fence is installed.
2792 if (i915_gem_object_needs_mb(obj))
2796 static inline int fence_number(struct drm_i915_private *dev_priv,
2797 struct drm_i915_fence_reg *fence)
2799 return fence - dev_priv->fence_regs;
2802 struct write_fence {
2803 struct drm_device *dev;
2804 struct drm_i915_gem_object *obj;
2808 static void i915_gem_write_fence__ipi(void *data)
2810 struct write_fence *args = data;
2812 /* Required for SNB+ with LLC */
2815 /* Required for VLV */
2816 i915_gem_write_fence(args->dev, args->fence, args->obj);
2819 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2820 struct drm_i915_fence_reg *fence,
2823 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2824 struct write_fence args = {
2825 .dev = obj->base.dev,
2826 .fence = fence_number(dev_priv, fence),
2827 .obj = enable ? obj : NULL,
2830 /* In order to fully serialize access to the fenced region and
2831 * the update to the fence register we need to take extreme
2832 * measures on SNB+. In theory, the write to the fence register
2833 * flushes all memory transactions before, and coupled with the
2834 * mb() placed around the register write we serialise all memory
2835 * operations with respect to the changes in the tiler. Yet, on
2836 * SNB+ we need to take a step further and emit an explicit wbinvd()
2837 * on each processor in order to manually flush all memory
2838 * transactions before updating the fence register.
2840 * However, Valleyview complicates matter. There the wbinvd is
2841 * insufficient and unlike SNB/IVB requires the serialising
2842 * register write. (Note that that register write by itself is
2843 * conversely not sufficient for SNB+.) To compromise, we do both.
2845 if (INTEL_INFO(args.dev)->gen >= 6)
2846 on_each_cpu(i915_gem_write_fence__ipi, &args, 1);
2848 i915_gem_write_fence(args.dev, args.fence, args.obj);
2851 obj->fence_reg = args.fence;
2853 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2855 obj->fence_reg = I915_FENCE_REG_NONE;
2857 list_del_init(&fence->lru_list);
2862 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2864 if (obj->last_fenced_seqno) {
2865 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2869 obj->last_fenced_seqno = 0;
2872 obj->fenced_gpu_access = false;
2877 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2879 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2880 struct drm_i915_fence_reg *fence;
2883 ret = i915_gem_object_wait_fence(obj);
2887 if (obj->fence_reg == I915_FENCE_REG_NONE)
2890 fence = &dev_priv->fence_regs[obj->fence_reg];
2892 i915_gem_object_fence_lost(obj);
2893 i915_gem_object_update_fence(obj, fence, false);
2898 static struct drm_i915_fence_reg *
2899 i915_find_fence_reg(struct drm_device *dev)
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct drm_i915_fence_reg *reg, *avail;
2905 /* First try to find a free reg */
2907 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2908 reg = &dev_priv->fence_regs[i];
2912 if (!reg->pin_count)
2919 /* None available, try to steal one or wait for a user to finish */
2920 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2931 * i915_gem_object_get_fence - set up fencing for an object
2932 * @obj: object to map through a fence reg
2934 * When mapping objects through the GTT, userspace wants to be able to write
2935 * to them without having to worry about swizzling if the object is tiled.
2936 * This function walks the fence regs looking for a free one for @obj,
2937 * stealing one if it can't find any.
2939 * It then sets up the reg based on the object's properties: address, pitch
2940 * and tiling format.
2942 * For an untiled surface, this removes any existing fence.
2945 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2947 struct drm_device *dev = obj->base.dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 bool enable = obj->tiling_mode != I915_TILING_NONE;
2950 struct drm_i915_fence_reg *reg;
2953 /* Have we updated the tiling parameters upon the object and so
2954 * will need to serialise the write to the associated fence register?
2956 if (obj->fence_dirty) {
2957 ret = i915_gem_object_wait_fence(obj);
2962 /* Just update our place in the LRU if our fence is getting reused. */
2963 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2964 reg = &dev_priv->fence_regs[obj->fence_reg];
2965 if (!obj->fence_dirty) {
2966 list_move_tail(®->lru_list,
2967 &dev_priv->mm.fence_list);
2970 } else if (enable) {
2971 reg = i915_find_fence_reg(dev);
2976 struct drm_i915_gem_object *old = reg->obj;
2978 ret = i915_gem_object_wait_fence(old);
2982 i915_gem_object_fence_lost(old);
2987 i915_gem_object_update_fence(obj, reg, enable);
2988 obj->fence_dirty = false;
2993 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
2994 struct drm_mm_node *gtt_space,
2995 unsigned long cache_level)
2997 struct drm_mm_node *other;
2999 /* On non-LLC machines we have to be careful when putting differing
3000 * types of snoopable memory together to avoid the prefetcher
3001 * crossing memory domains and dying.
3006 if (gtt_space == NULL)
3009 if (list_empty(>t_space->node_list))
3012 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3013 if (other->allocated && !other->hole_follows && other->color != cache_level)
3016 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3017 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3023 static void i915_gem_verify_gtt(struct drm_device *dev)
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3027 struct drm_i915_gem_object *obj;
3030 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3031 if (obj->gtt_space == NULL) {
3032 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3037 if (obj->cache_level != obj->gtt_space->color) {
3038 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3039 obj->gtt_space->start,
3040 obj->gtt_space->start + obj->gtt_space->size,
3042 obj->gtt_space->color);
3047 if (!i915_gem_valid_gtt_space(dev,
3049 obj->cache_level)) {
3050 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3051 obj->gtt_space->start,
3052 obj->gtt_space->start + obj->gtt_space->size,
3064 * Finds free space in the GTT aperture and binds the object there.
3067 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
3069 bool map_and_fenceable,
3072 struct drm_device *dev = obj->base.dev;
3073 drm_i915_private_t *dev_priv = dev->dev_private;
3074 struct drm_mm_node *node;
3075 u32 size, fence_size, fence_alignment, unfenced_alignment;
3076 bool mappable, fenceable;
3077 size_t gtt_max = map_and_fenceable ?
3078 dev_priv->gtt.mappable_end : dev_priv->gtt.total;
3081 fence_size = i915_gem_get_gtt_size(dev,
3084 fence_alignment = i915_gem_get_gtt_alignment(dev,
3086 obj->tiling_mode, true);
3087 unfenced_alignment =
3088 i915_gem_get_gtt_alignment(dev,
3090 obj->tiling_mode, false);
3093 alignment = map_and_fenceable ? fence_alignment :
3095 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3096 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3100 size = map_and_fenceable ? fence_size : obj->base.size;
3102 /* If the object is bigger than the entire aperture, reject it early
3103 * before evicting everything in a vain attempt to find space.
3105 if (obj->base.size > gtt_max) {
3106 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%ld\n",
3108 map_and_fenceable ? "mappable" : "total",
3113 ret = i915_gem_object_get_pages(obj);
3117 i915_gem_object_pin_pages(obj);
3119 node = kzalloc(sizeof(*node), GFP_KERNEL);
3121 i915_gem_object_unpin_pages(obj);
3126 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
3128 obj->cache_level, 0, gtt_max);
3130 ret = i915_gem_evict_something(dev, size, alignment,
3137 i915_gem_object_unpin_pages(obj);
3141 if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) {
3142 i915_gem_object_unpin_pages(obj);
3143 drm_mm_put_block(node);
3147 ret = i915_gem_gtt_prepare_object(obj);
3149 i915_gem_object_unpin_pages(obj);
3150 drm_mm_put_block(node);
3154 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3155 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3157 obj->gtt_space = node;
3158 obj->gtt_offset = node->start;
3161 node->size == fence_size &&
3162 (node->start & (fence_alignment - 1)) == 0;
3165 obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
3167 obj->map_and_fenceable = mappable && fenceable;
3169 trace_i915_gem_object_bind(obj, map_and_fenceable);
3170 i915_gem_verify_gtt(dev);
3175 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3177 /* If we don't have a page list set up, then we're not pinned
3178 * to GPU, and we can ignore the cache flush because it'll happen
3179 * again at bind time.
3181 if (obj->pages == NULL)
3185 * Stolen memory is always coherent with the GPU as it is explicitly
3186 * marked as wc by the system, or the system is cache-coherent.
3191 /* If the GPU is snooping the contents of the CPU cache,
3192 * we do not need to manually clear the CPU cache lines. However,
3193 * the caches are only snooped when the render cache is
3194 * flushed/invalidated. As we always have to emit invalidations
3195 * and flushes when moving into and out of the RENDER domain, correct
3196 * snooping behaviour occurs naturally as the result of our domain
3199 if (obj->cache_level != I915_CACHE_NONE)
3202 trace_i915_gem_object_clflush(obj);
3204 drm_clflush_sg(obj->pages);
3207 /** Flushes the GTT write domain for the object if it's dirty. */
3209 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3211 uint32_t old_write_domain;
3213 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3216 /* No actual flushing is required for the GTT write domain. Writes
3217 * to it immediately go to main memory as far as we know, so there's
3218 * no chipset flush. It also doesn't land in render cache.
3220 * However, we do have to enforce the order so that all writes through
3221 * the GTT land before any writes to the device, such as updates to
3226 old_write_domain = obj->base.write_domain;
3227 obj->base.write_domain = 0;
3229 trace_i915_gem_object_change_domain(obj,
3230 obj->base.read_domains,
3234 /** Flushes the CPU write domain for the object if it's dirty. */
3236 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3238 uint32_t old_write_domain;
3240 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3243 i915_gem_clflush_object(obj);
3244 i915_gem_chipset_flush(obj->base.dev);
3245 old_write_domain = obj->base.write_domain;
3246 obj->base.write_domain = 0;
3248 trace_i915_gem_object_change_domain(obj,
3249 obj->base.read_domains,
3254 * Moves a single object to the GTT read, and possibly write domain.
3256 * This function returns when the move is complete, including waiting on
3260 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3262 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3263 uint32_t old_write_domain, old_read_domains;
3266 /* Not valid to be called on unbound objects. */
3267 if (obj->gtt_space == NULL)
3270 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3273 ret = i915_gem_object_wait_rendering(obj, !write);
3277 i915_gem_object_flush_cpu_write_domain(obj);
3279 /* Serialise direct access to this object with the barriers for
3280 * coherent writes from the GPU, by effectively invalidating the
3281 * GTT domain upon first access.
3283 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3286 old_write_domain = obj->base.write_domain;
3287 old_read_domains = obj->base.read_domains;
3289 /* It should now be out of any other write domains, and we can update
3290 * the domain values for our changes.
3292 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3293 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3295 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3296 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3300 trace_i915_gem_object_change_domain(obj,
3304 /* And bump the LRU for this access */
3305 if (i915_gem_object_is_inactive(obj))
3306 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
3311 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3312 enum i915_cache_level cache_level)
3314 struct drm_device *dev = obj->base.dev;
3315 drm_i915_private_t *dev_priv = dev->dev_private;
3318 if (obj->cache_level == cache_level)
3321 if (obj->pin_count) {
3322 DRM_DEBUG("can not change the cache level of pinned objects\n");
3326 if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) {
3327 ret = i915_gem_object_unbind(obj);
3332 if (obj->gtt_space) {
3333 ret = i915_gem_object_finish_gpu(obj);
3337 i915_gem_object_finish_gtt(obj);
3339 /* Before SandyBridge, you could not use tiling or fence
3340 * registers with snooped memory, so relinquish any fences
3341 * currently pointing to our region in the aperture.
3343 if (INTEL_INFO(dev)->gen < 6) {
3344 ret = i915_gem_object_put_fence(obj);
3349 if (obj->has_global_gtt_mapping)
3350 i915_gem_gtt_bind_object(obj, cache_level);
3351 if (obj->has_aliasing_ppgtt_mapping)
3352 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3355 obj->gtt_space->color = cache_level;
3358 if (cache_level == I915_CACHE_NONE) {
3359 u32 old_read_domains, old_write_domain;
3361 /* If we're coming from LLC cached, then we haven't
3362 * actually been tracking whether the data is in the
3363 * CPU cache or not, since we only allow one bit set
3364 * in obj->write_domain and have been skipping the clflushes.
3365 * Just set it to the CPU cache for now.
3367 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3368 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3370 old_read_domains = obj->base.read_domains;
3371 old_write_domain = obj->base.write_domain;
3373 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3374 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3376 trace_i915_gem_object_change_domain(obj,
3381 obj->cache_level = cache_level;
3382 i915_gem_verify_gtt(dev);
3386 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3387 struct drm_file *file)
3389 struct drm_i915_gem_caching *args = data;
3390 struct drm_i915_gem_object *obj;
3393 ret = i915_mutex_lock_interruptible(dev);
3397 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3398 if (&obj->base == NULL) {
3403 args->caching = obj->cache_level != I915_CACHE_NONE;
3405 drm_gem_object_unreference(&obj->base);
3407 mutex_unlock(&dev->struct_mutex);
3411 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3412 struct drm_file *file)
3414 struct drm_i915_gem_caching *args = data;
3415 struct drm_i915_gem_object *obj;
3416 enum i915_cache_level level;
3419 switch (args->caching) {
3420 case I915_CACHING_NONE:
3421 level = I915_CACHE_NONE;
3423 case I915_CACHING_CACHED:
3424 level = I915_CACHE_LLC;
3430 ret = i915_mutex_lock_interruptible(dev);
3434 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3435 if (&obj->base == NULL) {
3440 ret = i915_gem_object_set_cache_level(obj, level);
3442 drm_gem_object_unreference(&obj->base);
3444 mutex_unlock(&dev->struct_mutex);
3449 * Prepare buffer for display plane (scanout, cursors, etc).
3450 * Can be called from an uninterruptible phase (modesetting) and allows
3451 * any flushes to be pipelined (for pageflips).
3454 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3456 struct intel_ring_buffer *pipelined)
3458 u32 old_read_domains, old_write_domain;
3461 if (pipelined != obj->ring) {
3462 ret = i915_gem_object_sync(obj, pipelined);
3467 /* The display engine is not coherent with the LLC cache on gen6. As
3468 * a result, we make sure that the pinning that is about to occur is
3469 * done with uncached PTEs. This is lowest common denominator for all
3472 * However for gen6+, we could do better by using the GFDT bit instead
3473 * of uncaching, which would allow us to flush all the LLC-cached data
3474 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3476 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3480 /* As the user may map the buffer once pinned in the display plane
3481 * (e.g. libkms for the bootup splash), we have to ensure that we
3482 * always use map_and_fenceable for all scanout buffers.
3484 ret = i915_gem_object_pin(obj, alignment, true, false);
3488 i915_gem_object_flush_cpu_write_domain(obj);
3490 old_write_domain = obj->base.write_domain;
3491 old_read_domains = obj->base.read_domains;
3493 /* It should now be out of any other write domains, and we can update
3494 * the domain values for our changes.
3496 obj->base.write_domain = 0;
3497 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3499 trace_i915_gem_object_change_domain(obj,
3507 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3511 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3514 ret = i915_gem_object_wait_rendering(obj, false);
3518 /* Ensure that we invalidate the GPU's caches and TLBs. */
3519 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3524 * Moves a single object to the CPU read, and possibly write domain.
3526 * This function returns when the move is complete, including waiting on
3530 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3532 uint32_t old_write_domain, old_read_domains;
3535 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3538 ret = i915_gem_object_wait_rendering(obj, !write);
3542 i915_gem_object_flush_gtt_write_domain(obj);
3544 old_write_domain = obj->base.write_domain;
3545 old_read_domains = obj->base.read_domains;
3547 /* Flush the CPU cache if it's still invalid. */
3548 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3549 i915_gem_clflush_object(obj);
3551 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3554 /* It should now be out of any other write domains, and we can update
3555 * the domain values for our changes.
3557 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3559 /* If we're writing through the CPU, then the GPU read domains will
3560 * need to be invalidated at next use.
3563 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3564 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3567 trace_i915_gem_object_change_domain(obj,
3574 /* Throttle our rendering by waiting until the ring has completed our requests
3575 * emitted over 20 msec ago.
3577 * Note that if we were to use the current jiffies each time around the loop,
3578 * we wouldn't escape the function with any frames outstanding if the time to
3579 * render a frame was over 20ms.
3581 * This should get us reasonable parallelism between CPU and GPU but also
3582 * relatively low latency when blocking on a particular request to finish.
3585 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 struct drm_i915_file_private *file_priv = file->driver_priv;
3589 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3590 struct drm_i915_gem_request *request;
3591 struct intel_ring_buffer *ring = NULL;
3592 unsigned reset_counter;
3596 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3600 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3604 spin_lock(&file_priv->mm.lock);
3605 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3606 if (time_after_eq(request->emitted_jiffies, recent_enough))
3609 ring = request->ring;
3610 seqno = request->seqno;
3612 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3613 spin_unlock(&file_priv->mm.lock);
3618 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3620 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3626 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3628 bool map_and_fenceable,
3633 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3636 if (obj->gtt_space != NULL) {
3637 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3638 (map_and_fenceable && !obj->map_and_fenceable)) {
3639 WARN(obj->pin_count,
3640 "bo is already pinned with incorrect alignment:"
3641 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3642 " obj->map_and_fenceable=%d\n",
3643 obj->gtt_offset, alignment,
3645 obj->map_and_fenceable);
3646 ret = i915_gem_object_unbind(obj);
3652 if (obj->gtt_space == NULL) {
3653 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3655 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3661 if (!dev_priv->mm.aliasing_ppgtt)
3662 i915_gem_gtt_bind_object(obj, obj->cache_level);
3665 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3666 i915_gem_gtt_bind_object(obj, obj->cache_level);
3669 obj->pin_mappable |= map_and_fenceable;
3675 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3677 BUG_ON(obj->pin_count == 0);
3678 BUG_ON(obj->gtt_space == NULL);
3680 if (--obj->pin_count == 0)
3681 obj->pin_mappable = false;
3685 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3686 struct drm_file *file)
3688 struct drm_i915_gem_pin *args = data;
3689 struct drm_i915_gem_object *obj;
3692 ret = i915_mutex_lock_interruptible(dev);
3696 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3697 if (&obj->base == NULL) {
3702 if (obj->madv != I915_MADV_WILLNEED) {
3703 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3708 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3709 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3715 if (obj->user_pin_count == 0) {
3716 ret = i915_gem_object_pin(obj, args->alignment, true, false);
3721 obj->user_pin_count++;
3722 obj->pin_filp = file;
3724 /* XXX - flush the CPU caches for pinned objects
3725 * as the X server doesn't manage domains yet
3727 i915_gem_object_flush_cpu_write_domain(obj);
3728 args->offset = obj->gtt_offset;
3730 drm_gem_object_unreference(&obj->base);
3732 mutex_unlock(&dev->struct_mutex);
3737 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3738 struct drm_file *file)
3740 struct drm_i915_gem_pin *args = data;
3741 struct drm_i915_gem_object *obj;
3744 ret = i915_mutex_lock_interruptible(dev);
3748 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3749 if (&obj->base == NULL) {
3754 if (obj->pin_filp != file) {
3755 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3760 obj->user_pin_count--;
3761 if (obj->user_pin_count == 0) {
3762 obj->pin_filp = NULL;
3763 i915_gem_object_unpin(obj);
3767 drm_gem_object_unreference(&obj->base);
3769 mutex_unlock(&dev->struct_mutex);
3774 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3775 struct drm_file *file)
3777 struct drm_i915_gem_busy *args = data;
3778 struct drm_i915_gem_object *obj;
3781 ret = i915_mutex_lock_interruptible(dev);
3785 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3786 if (&obj->base == NULL) {
3791 /* Count all active objects as busy, even if they are currently not used
3792 * by the gpu. Users of this interface expect objects to eventually
3793 * become non-busy without any further actions, therefore emit any
3794 * necessary flushes here.
3796 ret = i915_gem_object_flush_active(obj);
3798 args->busy = obj->active;
3800 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3801 args->busy |= intel_ring_flag(obj->ring) << 16;
3804 drm_gem_object_unreference(&obj->base);
3806 mutex_unlock(&dev->struct_mutex);
3811 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3812 struct drm_file *file_priv)
3814 return i915_gem_ring_throttle(dev, file_priv);
3818 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3819 struct drm_file *file_priv)
3821 struct drm_i915_gem_madvise *args = data;
3822 struct drm_i915_gem_object *obj;
3825 switch (args->madv) {
3826 case I915_MADV_DONTNEED:
3827 case I915_MADV_WILLNEED:
3833 ret = i915_mutex_lock_interruptible(dev);
3837 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3838 if (&obj->base == NULL) {
3843 if (obj->pin_count) {
3848 if (obj->madv != __I915_MADV_PURGED)
3849 obj->madv = args->madv;
3851 /* if the object is no longer attached, discard its backing storage */
3852 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3853 i915_gem_object_truncate(obj);
3855 args->retained = obj->madv != __I915_MADV_PURGED;
3858 drm_gem_object_unreference(&obj->base);
3860 mutex_unlock(&dev->struct_mutex);
3864 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3865 const struct drm_i915_gem_object_ops *ops)
3867 INIT_LIST_HEAD(&obj->mm_list);
3868 INIT_LIST_HEAD(&obj->global_list);
3869 INIT_LIST_HEAD(&obj->ring_list);
3870 INIT_LIST_HEAD(&obj->exec_list);
3874 obj->fence_reg = I915_FENCE_REG_NONE;
3875 obj->madv = I915_MADV_WILLNEED;
3876 /* Avoid an unnecessary call to unbind on the first bind. */
3877 obj->map_and_fenceable = true;
3879 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3882 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3883 .get_pages = i915_gem_object_get_pages_gtt,
3884 .put_pages = i915_gem_object_put_pages_gtt,
3887 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3890 struct drm_i915_gem_object *obj;
3891 struct address_space *mapping;
3894 obj = i915_gem_object_alloc(dev);
3898 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3899 i915_gem_object_free(obj);
3903 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3904 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3905 /* 965gm cannot relocate objects above 4GiB. */
3906 mask &= ~__GFP_HIGHMEM;
3907 mask |= __GFP_DMA32;
3910 mapping = file_inode(obj->base.filp)->i_mapping;
3911 mapping_set_gfp_mask(mapping, mask);
3913 i915_gem_object_init(obj, &i915_gem_object_ops);
3915 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3916 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3919 /* On some devices, we can have the GPU use the LLC (the CPU
3920 * cache) for about a 10% performance improvement
3921 * compared to uncached. Graphics requests other than
3922 * display scanout are coherent with the CPU in
3923 * accessing this cache. This means in this mode we
3924 * don't need to clflush on the CPU side, and on the
3925 * GPU side we only need to flush internal caches to
3926 * get data visible to the CPU.
3928 * However, we maintain the display planes as UC, and so
3929 * need to rebind when first used as such.
3931 obj->cache_level = I915_CACHE_LLC;
3933 obj->cache_level = I915_CACHE_NONE;
3938 int i915_gem_init_object(struct drm_gem_object *obj)
3945 void i915_gem_free_object(struct drm_gem_object *gem_obj)
3947 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3948 struct drm_device *dev = obj->base.dev;
3949 drm_i915_private_t *dev_priv = dev->dev_private;
3951 trace_i915_gem_object_destroy(obj);
3954 i915_gem_detach_phys_object(dev, obj);
3957 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3958 bool was_interruptible;
3960 was_interruptible = dev_priv->mm.interruptible;
3961 dev_priv->mm.interruptible = false;
3963 WARN_ON(i915_gem_object_unbind(obj));
3965 dev_priv->mm.interruptible = was_interruptible;
3968 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3969 * before progressing. */
3971 i915_gem_object_unpin_pages(obj);
3973 if (WARN_ON(obj->pages_pin_count))
3974 obj->pages_pin_count = 0;
3975 i915_gem_object_put_pages(obj);
3976 i915_gem_object_free_mmap_offset(obj);
3977 i915_gem_object_release_stolen(obj);
3981 if (obj->base.import_attach)
3982 drm_prime_gem_destroy(&obj->base, NULL);
3984 drm_gem_object_release(&obj->base);
3985 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3988 i915_gem_object_free(obj);
3992 i915_gem_idle(struct drm_device *dev)
3994 drm_i915_private_t *dev_priv = dev->dev_private;
3997 mutex_lock(&dev->struct_mutex);
3999 if (dev_priv->mm.suspended) {
4000 mutex_unlock(&dev->struct_mutex);
4004 ret = i915_gpu_idle(dev);
4006 mutex_unlock(&dev->struct_mutex);
4009 i915_gem_retire_requests(dev);
4011 /* Under UMS, be paranoid and evict. */
4012 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4013 i915_gem_evict_everything(dev);
4015 i915_gem_reset_fences(dev);
4017 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4018 * We need to replace this with a semaphore, or something.
4019 * And not confound mm.suspended!
4021 dev_priv->mm.suspended = 1;
4022 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4024 i915_kernel_lost_context(dev);
4025 i915_gem_cleanup_ringbuffer(dev);
4027 mutex_unlock(&dev->struct_mutex);
4029 /* Cancel the retire work handler, which should be idle now. */
4030 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4035 void i915_gem_l3_remap(struct drm_device *dev)
4037 drm_i915_private_t *dev_priv = dev->dev_private;
4041 if (!HAS_L3_GPU_CACHE(dev))
4044 if (!dev_priv->l3_parity.remap_info)
4047 misccpctl = I915_READ(GEN7_MISCCPCTL);
4048 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4049 POSTING_READ(GEN7_MISCCPCTL);
4051 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4052 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4053 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4054 DRM_DEBUG("0x%x was already programmed to %x\n",
4055 GEN7_L3LOG_BASE + i, remap);
4056 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4057 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4058 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4061 /* Make sure all the writes land before disabling dop clock gating */
4062 POSTING_READ(GEN7_L3LOG_BASE);
4064 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4067 void i915_gem_init_swizzling(struct drm_device *dev)
4069 drm_i915_private_t *dev_priv = dev->dev_private;
4071 if (INTEL_INFO(dev)->gen < 5 ||
4072 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4075 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4076 DISP_TILE_SURFACE_SWIZZLING);
4081 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4083 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4084 else if (IS_GEN7(dev))
4085 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4091 intel_enable_blt(struct drm_device *dev)
4096 /* The blitter was dysfunctional on early prototypes */
4097 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4098 DRM_INFO("BLT not supported on this pre-production hardware;"
4099 " graphics performance will be degraded.\n");
4106 static int i915_gem_init_rings(struct drm_device *dev)
4108 struct drm_i915_private *dev_priv = dev->dev_private;
4111 ret = intel_init_render_ring_buffer(dev);
4116 ret = intel_init_bsd_ring_buffer(dev);
4118 goto cleanup_render_ring;
4121 if (intel_enable_blt(dev)) {
4122 ret = intel_init_blt_ring_buffer(dev);
4124 goto cleanup_bsd_ring;
4127 if (HAS_VEBOX(dev)) {
4128 ret = intel_init_vebox_ring_buffer(dev);
4130 goto cleanup_blt_ring;
4134 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4136 goto cleanup_vebox_ring;
4141 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4143 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4145 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4146 cleanup_render_ring:
4147 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4153 i915_gem_init_hw(struct drm_device *dev)
4155 drm_i915_private_t *dev_priv = dev->dev_private;
4158 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4161 if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
4162 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4164 if (HAS_PCH_NOP(dev)) {
4165 u32 temp = I915_READ(GEN7_MSG_CTL);
4166 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4167 I915_WRITE(GEN7_MSG_CTL, temp);
4170 i915_gem_l3_remap(dev);
4172 i915_gem_init_swizzling(dev);
4174 ret = i915_gem_init_rings(dev);
4179 * XXX: There was some w/a described somewhere suggesting loading
4180 * contexts before PPGTT.
4182 i915_gem_context_init(dev);
4183 if (dev_priv->mm.aliasing_ppgtt) {
4184 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4186 i915_gem_cleanup_aliasing_ppgtt(dev);
4187 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4194 int i915_gem_init(struct drm_device *dev)
4196 struct drm_i915_private *dev_priv = dev->dev_private;
4199 mutex_lock(&dev->struct_mutex);
4201 if (IS_VALLEYVIEW(dev)) {
4202 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4203 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4204 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4205 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4208 i915_gem_init_global_gtt(dev);
4210 ret = i915_gem_init_hw(dev);
4211 mutex_unlock(&dev->struct_mutex);
4213 i915_gem_cleanup_aliasing_ppgtt(dev);
4217 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4218 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4219 dev_priv->dri1.allow_batchbuffer = 1;
4224 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4226 drm_i915_private_t *dev_priv = dev->dev_private;
4227 struct intel_ring_buffer *ring;
4230 for_each_ring(ring, dev_priv, i)
4231 intel_cleanup_ring_buffer(ring);
4235 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4236 struct drm_file *file_priv)
4238 drm_i915_private_t *dev_priv = dev->dev_private;
4241 if (drm_core_check_feature(dev, DRIVER_MODESET))
4244 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4245 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4246 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4249 mutex_lock(&dev->struct_mutex);
4250 dev_priv->mm.suspended = 0;
4252 ret = i915_gem_init_hw(dev);
4254 mutex_unlock(&dev->struct_mutex);
4258 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4259 mutex_unlock(&dev->struct_mutex);
4261 ret = drm_irq_install(dev);
4263 goto cleanup_ringbuffer;
4268 mutex_lock(&dev->struct_mutex);
4269 i915_gem_cleanup_ringbuffer(dev);
4270 dev_priv->mm.suspended = 1;
4271 mutex_unlock(&dev->struct_mutex);
4277 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4278 struct drm_file *file_priv)
4280 if (drm_core_check_feature(dev, DRIVER_MODESET))
4283 drm_irq_uninstall(dev);
4284 return i915_gem_idle(dev);
4288 i915_gem_lastclose(struct drm_device *dev)
4292 if (drm_core_check_feature(dev, DRIVER_MODESET))
4295 ret = i915_gem_idle(dev);
4297 DRM_ERROR("failed to idle hardware: %d\n", ret);
4301 init_ring_lists(struct intel_ring_buffer *ring)
4303 INIT_LIST_HEAD(&ring->active_list);
4304 INIT_LIST_HEAD(&ring->request_list);
4308 i915_gem_load(struct drm_device *dev)
4310 drm_i915_private_t *dev_priv = dev->dev_private;
4314 kmem_cache_create("i915_gem_object",
4315 sizeof(struct drm_i915_gem_object), 0,
4319 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4320 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4321 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4322 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4323 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4324 for (i = 0; i < I915_NUM_RINGS; i++)
4325 init_ring_lists(&dev_priv->ring[i]);
4326 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4327 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4328 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4329 i915_gem_retire_work_handler);
4330 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4332 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4334 I915_WRITE(MI_ARB_STATE,
4335 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4338 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4340 /* Old X drivers will take 0-2 for front, back, depth buffers */
4341 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4342 dev_priv->fence_reg_start = 3;
4344 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4345 dev_priv->num_fence_regs = 32;
4346 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4347 dev_priv->num_fence_regs = 16;
4349 dev_priv->num_fence_regs = 8;
4351 /* Initialize fence registers to zero */
4352 i915_gem_reset_fences(dev);
4354 i915_gem_detect_bit_6_swizzle(dev);
4355 init_waitqueue_head(&dev_priv->pending_flip_queue);
4357 dev_priv->mm.interruptible = true;
4359 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4360 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4361 register_shrinker(&dev_priv->mm.inactive_shrinker);
4365 * Create a physically contiguous memory object for this object
4366 * e.g. for cursor + overlay regs
4368 static int i915_gem_init_phys_object(struct drm_device *dev,
4369 int id, int size, int align)
4371 drm_i915_private_t *dev_priv = dev->dev_private;
4372 struct drm_i915_gem_phys_object *phys_obj;
4375 if (dev_priv->mm.phys_objs[id - 1] || !size)
4378 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4384 phys_obj->handle = drm_pci_alloc(dev, size, align);
4385 if (!phys_obj->handle) {
4390 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4393 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4401 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4403 drm_i915_private_t *dev_priv = dev->dev_private;
4404 struct drm_i915_gem_phys_object *phys_obj;
4406 if (!dev_priv->mm.phys_objs[id - 1])
4409 phys_obj = dev_priv->mm.phys_objs[id - 1];
4410 if (phys_obj->cur_obj) {
4411 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4415 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4417 drm_pci_free(dev, phys_obj->handle);
4419 dev_priv->mm.phys_objs[id - 1] = NULL;
4422 void i915_gem_free_all_phys_object(struct drm_device *dev)
4426 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4427 i915_gem_free_phys_object(dev, i);
4430 void i915_gem_detach_phys_object(struct drm_device *dev,
4431 struct drm_i915_gem_object *obj)
4433 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4440 vaddr = obj->phys_obj->handle->vaddr;
4442 page_count = obj->base.size / PAGE_SIZE;
4443 for (i = 0; i < page_count; i++) {
4444 struct page *page = shmem_read_mapping_page(mapping, i);
4445 if (!IS_ERR(page)) {
4446 char *dst = kmap_atomic(page);
4447 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4450 drm_clflush_pages(&page, 1);
4452 set_page_dirty(page);
4453 mark_page_accessed(page);
4454 page_cache_release(page);
4457 i915_gem_chipset_flush(dev);
4459 obj->phys_obj->cur_obj = NULL;
4460 obj->phys_obj = NULL;
4464 i915_gem_attach_phys_object(struct drm_device *dev,
4465 struct drm_i915_gem_object *obj,
4469 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4470 drm_i915_private_t *dev_priv = dev->dev_private;
4475 if (id > I915_MAX_PHYS_OBJECT)
4478 if (obj->phys_obj) {
4479 if (obj->phys_obj->id == id)
4481 i915_gem_detach_phys_object(dev, obj);
4484 /* create a new object */
4485 if (!dev_priv->mm.phys_objs[id - 1]) {
4486 ret = i915_gem_init_phys_object(dev, id,
4487 obj->base.size, align);
4489 DRM_ERROR("failed to init phys object %d size: %zu\n",
4490 id, obj->base.size);
4495 /* bind to the object */
4496 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4497 obj->phys_obj->cur_obj = obj;
4499 page_count = obj->base.size / PAGE_SIZE;
4501 for (i = 0; i < page_count; i++) {
4505 page = shmem_read_mapping_page(mapping, i);
4507 return PTR_ERR(page);
4509 src = kmap_atomic(page);
4510 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4511 memcpy(dst, src, PAGE_SIZE);
4514 mark_page_accessed(page);
4515 page_cache_release(page);
4522 i915_gem_phys_pwrite(struct drm_device *dev,
4523 struct drm_i915_gem_object *obj,
4524 struct drm_i915_gem_pwrite *args,
4525 struct drm_file *file_priv)
4527 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4528 char __user *user_data = to_user_ptr(args->data_ptr);
4530 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4531 unsigned long unwritten;
4533 /* The physical object once assigned is fixed for the lifetime
4534 * of the obj, so we can safely drop the lock and continue
4537 mutex_unlock(&dev->struct_mutex);
4538 unwritten = copy_from_user(vaddr, user_data, args->size);
4539 mutex_lock(&dev->struct_mutex);
4544 i915_gem_chipset_flush(dev);
4548 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4550 struct drm_i915_file_private *file_priv = file->driver_priv;
4552 /* Clean up our request list when the client is going away, so that
4553 * later retire_requests won't dereference our soon-to-be-gone
4556 spin_lock(&file_priv->mm.lock);
4557 while (!list_empty(&file_priv->mm.request_list)) {
4558 struct drm_i915_gem_request *request;
4560 request = list_first_entry(&file_priv->mm.request_list,
4561 struct drm_i915_gem_request,
4563 list_del(&request->client_list);
4564 request->file_priv = NULL;
4566 spin_unlock(&file_priv->mm.lock);
4569 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4571 if (!mutex_is_locked(mutex))
4574 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4575 return mutex->owner == task;
4577 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4583 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4585 struct drm_i915_private *dev_priv =
4586 container_of(shrinker,
4587 struct drm_i915_private,
4588 mm.inactive_shrinker);
4589 struct drm_device *dev = dev_priv->dev;
4590 struct drm_i915_gem_object *obj;
4591 int nr_to_scan = sc->nr_to_scan;
4595 if (!mutex_trylock(&dev->struct_mutex)) {
4596 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4599 if (dev_priv->mm.shrinker_no_lock_stealing)
4606 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4608 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4611 i915_gem_shrink_all(dev_priv);
4615 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4616 if (obj->pages_pin_count == 0)
4617 cnt += obj->base.size >> PAGE_SHIFT;
4618 list_for_each_entry(obj, &dev_priv->mm.inactive_list, global_list)
4619 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4620 cnt += obj->base.size >> PAGE_SHIFT;
4623 mutex_unlock(&dev->struct_mutex);