2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
42 static __must_check int
43 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
44 struct i915_address_space *vm,
46 bool map_and_fenceable,
48 static int i915_gem_phys_pwrite(struct drm_device *dev,
49 struct drm_i915_gem_object *obj,
50 struct drm_i915_gem_pwrite *args,
51 struct drm_file *file);
53 static void i915_gem_write_fence(struct drm_device *dev, int reg,
54 struct drm_i915_gem_object *obj);
55 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
56 struct drm_i915_fence_reg *fence,
59 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
60 struct shrink_control *sc);
61 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
62 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
63 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
65 static bool cpu_cache_is_coherent(struct drm_device *dev,
66 enum i915_cache_level level)
68 return HAS_LLC(dev) || level != I915_CACHE_NONE;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
73 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
76 return obj->pin_display;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
82 i915_gem_release_mmap(obj);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj->fence_dirty = false;
88 obj->fence_reg = I915_FENCE_REG_NONE;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count++;
97 dev_priv->mm.object_memory += size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
101 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
104 spin_lock(&dev_priv->mm.object_stat_lock);
105 dev_priv->mm.object_count--;
106 dev_priv->mm.object_memory -= size;
107 spin_unlock(&dev_priv->mm.object_stat_lock);
111 i915_gem_wait_for_error(struct i915_gpu_error *error)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret = wait_event_interruptible_timeout(error->reset_queue,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret < 0) {
139 int i915_mutex_lock_interruptible(struct drm_device *dev)
141 struct drm_i915_private *dev_priv = dev->dev_private;
144 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
148 ret = mutex_lock_interruptible(&dev->struct_mutex);
152 WARN_ON(i915_verify_lists(dev));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
159 return i915_gem_obj_bound_any(obj) && !obj->active;
163 i915_gem_init_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file)
166 struct drm_i915_private *dev_priv = dev->dev_private;
167 struct drm_i915_gem_init *args = data;
169 if (drm_core_check_feature(dev, DRIVER_MODESET))
172 if (args->gtt_start >= args->gtt_end ||
173 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
176 /* GEM with user mode setting was never supported on ilk and later. */
177 if (INTEL_INFO(dev)->gen >= 5)
180 mutex_lock(&dev->struct_mutex);
181 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
183 dev_priv->gtt.mappable_end = args->gtt_end;
184 mutex_unlock(&dev->struct_mutex);
190 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
191 struct drm_file *file)
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 struct drm_i915_gem_get_aperture *args = data;
195 struct drm_i915_gem_object *obj;
199 mutex_lock(&dev->struct_mutex);
200 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
202 pinned += i915_gem_obj_ggtt_size(obj);
203 mutex_unlock(&dev->struct_mutex);
205 args->aper_size = dev_priv->gtt.base.total;
206 args->aper_available_size = args->aper_size - pinned;
211 void *i915_gem_object_alloc(struct drm_device *dev)
213 struct drm_i915_private *dev_priv = dev->dev_private;
214 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
217 void i915_gem_object_free(struct drm_i915_gem_object *obj)
219 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
220 kmem_cache_free(dev_priv->slab, obj);
224 i915_gem_create(struct drm_file *file,
225 struct drm_device *dev,
229 struct drm_i915_gem_object *obj;
233 size = roundup(size, PAGE_SIZE);
237 /* Allocate the new object */
238 obj = i915_gem_alloc_object(dev, size);
242 ret = drm_gem_handle_create(file, &obj->base, &handle);
243 /* drop reference from allocate - handle holds it now */
244 drm_gem_object_unreference_unlocked(&obj->base);
253 i915_gem_dumb_create(struct drm_file *file,
254 struct drm_device *dev,
255 struct drm_mode_create_dumb *args)
257 /* have to work out size/pitch and return them */
258 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
259 args->size = args->pitch * args->height;
260 return i915_gem_create(file, dev,
261 args->size, &args->handle);
264 int i915_gem_dumb_destroy(struct drm_file *file,
265 struct drm_device *dev,
268 return drm_gem_handle_delete(file, handle);
272 * Creates a new mm object and returns a handle to it.
275 i915_gem_create_ioctl(struct drm_device *dev, void *data,
276 struct drm_file *file)
278 struct drm_i915_gem_create *args = data;
280 return i915_gem_create(file, dev,
281 args->size, &args->handle);
285 __copy_to_user_swizzled(char __user *cpu_vaddr,
286 const char *gpu_vaddr, int gpu_offset,
289 int ret, cpu_offset = 0;
292 int cacheline_end = ALIGN(gpu_offset + 1, 64);
293 int this_length = min(cacheline_end - gpu_offset, length);
294 int swizzled_gpu_offset = gpu_offset ^ 64;
296 ret = __copy_to_user(cpu_vaddr + cpu_offset,
297 gpu_vaddr + swizzled_gpu_offset,
302 cpu_offset += this_length;
303 gpu_offset += this_length;
304 length -= this_length;
311 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
312 const char __user *cpu_vaddr,
315 int ret, cpu_offset = 0;
318 int cacheline_end = ALIGN(gpu_offset + 1, 64);
319 int this_length = min(cacheline_end - gpu_offset, length);
320 int swizzled_gpu_offset = gpu_offset ^ 64;
322 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
323 cpu_vaddr + cpu_offset,
328 cpu_offset += this_length;
329 gpu_offset += this_length;
330 length -= this_length;
336 /* Per-page copy function for the shmem pread fastpath.
337 * Flushes invalid cachelines before reading the target if
338 * needs_clflush is set. */
340 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
341 char __user *user_data,
342 bool page_do_bit17_swizzling, bool needs_clflush)
347 if (unlikely(page_do_bit17_swizzling))
350 vaddr = kmap_atomic(page);
352 drm_clflush_virt_range(vaddr + shmem_page_offset,
354 ret = __copy_to_user_inatomic(user_data,
355 vaddr + shmem_page_offset,
357 kunmap_atomic(vaddr);
359 return ret ? -EFAULT : 0;
363 shmem_clflush_swizzled_range(char *addr, unsigned long length,
366 if (unlikely(swizzled)) {
367 unsigned long start = (unsigned long) addr;
368 unsigned long end = (unsigned long) addr + length;
370 /* For swizzling simply ensure that we always flush both
371 * channels. Lame, but simple and it works. Swizzled
372 * pwrite/pread is far from a hotpath - current userspace
373 * doesn't use it at all. */
374 start = round_down(start, 128);
375 end = round_up(end, 128);
377 drm_clflush_virt_range((void *)start, end - start);
379 drm_clflush_virt_range(addr, length);
384 /* Only difference to the fast-path function is that this can handle bit17
385 * and uses non-atomic copy and kmap functions. */
387 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
388 char __user *user_data,
389 bool page_do_bit17_swizzling, bool needs_clflush)
396 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
398 page_do_bit17_swizzling);
400 if (page_do_bit17_swizzling)
401 ret = __copy_to_user_swizzled(user_data,
402 vaddr, shmem_page_offset,
405 ret = __copy_to_user(user_data,
406 vaddr + shmem_page_offset,
410 return ret ? - EFAULT : 0;
414 i915_gem_shmem_pread(struct drm_device *dev,
415 struct drm_i915_gem_object *obj,
416 struct drm_i915_gem_pread *args,
417 struct drm_file *file)
419 char __user *user_data;
422 int shmem_page_offset, page_length, ret = 0;
423 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
425 int needs_clflush = 0;
426 struct sg_page_iter sg_iter;
428 user_data = to_user_ptr(args->data_ptr);
431 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
433 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
434 /* If we're not in the cpu read domain, set ourself into the gtt
435 * read domain and manually flush cachelines (if required). This
436 * optimizes for the case when the gpu will dirty the data
437 * anyway again before the next pread happens. */
438 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
439 if (i915_gem_obj_bound_any(obj)) {
440 ret = i915_gem_object_set_to_gtt_domain(obj, false);
446 ret = i915_gem_object_get_pages(obj);
450 i915_gem_object_pin_pages(obj);
452 offset = args->offset;
454 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
455 offset >> PAGE_SHIFT) {
456 struct page *page = sg_page_iter_page(&sg_iter);
461 /* Operation in this page
463 * shmem_page_offset = offset within page in shmem file
464 * page_length = bytes to copy for this page
466 shmem_page_offset = offset_in_page(offset);
467 page_length = remain;
468 if ((shmem_page_offset + page_length) > PAGE_SIZE)
469 page_length = PAGE_SIZE - shmem_page_offset;
471 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
472 (page_to_phys(page) & (1 << 17)) != 0;
474 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
475 user_data, page_do_bit17_swizzling,
480 mutex_unlock(&dev->struct_mutex);
482 if (likely(!i915_prefault_disable) && !prefaulted) {
483 ret = fault_in_multipages_writeable(user_data, remain);
484 /* Userspace is tricking us, but we've already clobbered
485 * its pages with the prefault and promised to write the
486 * data up to the first fault. Hence ignore any errors
487 * and just continue. */
492 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
493 user_data, page_do_bit17_swizzling,
496 mutex_lock(&dev->struct_mutex);
499 mark_page_accessed(page);
504 remain -= page_length;
505 user_data += page_length;
506 offset += page_length;
510 i915_gem_object_unpin_pages(obj);
516 * Reads data from the object referenced by handle.
518 * On error, the contents of *data are undefined.
521 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
522 struct drm_file *file)
524 struct drm_i915_gem_pread *args = data;
525 struct drm_i915_gem_object *obj;
531 if (!access_ok(VERIFY_WRITE,
532 to_user_ptr(args->data_ptr),
536 ret = i915_mutex_lock_interruptible(dev);
540 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
541 if (&obj->base == NULL) {
546 /* Bounds check source. */
547 if (args->offset > obj->base.size ||
548 args->size > obj->base.size - args->offset) {
553 /* prime objects have no backing filp to GEM pread/pwrite
556 if (!obj->base.filp) {
561 trace_i915_gem_object_pread(obj, args->offset, args->size);
563 ret = i915_gem_shmem_pread(dev, obj, args, file);
566 drm_gem_object_unreference(&obj->base);
568 mutex_unlock(&dev->struct_mutex);
572 /* This is the fast write path which cannot handle
573 * page faults in the source data
577 fast_user_write(struct io_mapping *mapping,
578 loff_t page_base, int page_offset,
579 char __user *user_data,
582 void __iomem *vaddr_atomic;
584 unsigned long unwritten;
586 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
587 /* We can use the cpu mem copy function because this is X86. */
588 vaddr = (void __force*)vaddr_atomic + page_offset;
589 unwritten = __copy_from_user_inatomic_nocache(vaddr,
591 io_mapping_unmap_atomic(vaddr_atomic);
596 * This is the fast pwrite path, where we copy the data directly from the
597 * user into the GTT, uncached.
600 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
601 struct drm_i915_gem_object *obj,
602 struct drm_i915_gem_pwrite *args,
603 struct drm_file *file)
605 drm_i915_private_t *dev_priv = dev->dev_private;
607 loff_t offset, page_base;
608 char __user *user_data;
609 int page_offset, page_length, ret;
611 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
615 ret = i915_gem_object_set_to_gtt_domain(obj, true);
619 ret = i915_gem_object_put_fence(obj);
623 user_data = to_user_ptr(args->data_ptr);
626 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = offset & PAGE_MASK;
636 page_offset = offset_in_page(offset);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 /* If we get a fault while copying data, then (presumably) our
642 * source page isn't available. Return the error and we'll
643 * retry in the slow path.
645 if (fast_user_write(dev_priv->gtt.mappable, page_base,
646 page_offset, user_data, page_length)) {
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
662 /* Per-page copy function for the shmem pwrite fastpath.
663 * Flushes invalid cachelines before writing to the target if
664 * needs_clflush_before is set and flushes out any written cachelines after
665 * writing if needs_clflush is set. */
667 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
668 char __user *user_data,
669 bool page_do_bit17_swizzling,
670 bool needs_clflush_before,
671 bool needs_clflush_after)
676 if (unlikely(page_do_bit17_swizzling))
679 vaddr = kmap_atomic(page);
680 if (needs_clflush_before)
681 drm_clflush_virt_range(vaddr + shmem_page_offset,
683 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
686 if (needs_clflush_after)
687 drm_clflush_virt_range(vaddr + shmem_page_offset,
689 kunmap_atomic(vaddr);
691 return ret ? -EFAULT : 0;
694 /* Only difference to the fast-path function is that this can handle bit17
695 * and uses non-atomic copy and kmap functions. */
697 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
698 char __user *user_data,
699 bool page_do_bit17_swizzling,
700 bool needs_clflush_before,
701 bool needs_clflush_after)
707 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
708 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
710 page_do_bit17_swizzling);
711 if (page_do_bit17_swizzling)
712 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
716 ret = __copy_from_user(vaddr + shmem_page_offset,
719 if (needs_clflush_after)
720 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
722 page_do_bit17_swizzling);
725 return ret ? -EFAULT : 0;
729 i915_gem_shmem_pwrite(struct drm_device *dev,
730 struct drm_i915_gem_object *obj,
731 struct drm_i915_gem_pwrite *args,
732 struct drm_file *file)
736 char __user *user_data;
737 int shmem_page_offset, page_length, ret = 0;
738 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
739 int hit_slowpath = 0;
740 int needs_clflush_after = 0;
741 int needs_clflush_before = 0;
742 struct sg_page_iter sg_iter;
744 user_data = to_user_ptr(args->data_ptr);
747 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
749 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
750 /* If we're not in the cpu write domain, set ourself into the gtt
751 * write domain and manually flush cachelines (if required). This
752 * optimizes for the case when the gpu will use the data
753 * right away and we therefore have to clflush anyway. */
754 needs_clflush_after = cpu_write_needs_clflush(obj);
755 if (i915_gem_obj_bound_any(obj)) {
756 ret = i915_gem_object_set_to_gtt_domain(obj, true);
761 /* Same trick applies to invalidate partially written cachelines read
763 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
764 needs_clflush_before =
765 !cpu_cache_is_coherent(dev, obj->cache_level);
767 ret = i915_gem_object_get_pages(obj);
771 i915_gem_object_pin_pages(obj);
773 offset = args->offset;
776 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
777 offset >> PAGE_SHIFT) {
778 struct page *page = sg_page_iter_page(&sg_iter);
779 int partial_cacheline_write;
784 /* Operation in this page
786 * shmem_page_offset = offset within page in shmem file
787 * page_length = bytes to copy for this page
789 shmem_page_offset = offset_in_page(offset);
791 page_length = remain;
792 if ((shmem_page_offset + page_length) > PAGE_SIZE)
793 page_length = PAGE_SIZE - shmem_page_offset;
795 /* If we don't overwrite a cacheline completely we need to be
796 * careful to have up-to-date data by first clflushing. Don't
797 * overcomplicate things and flush the entire patch. */
798 partial_cacheline_write = needs_clflush_before &&
799 ((shmem_page_offset | page_length)
800 & (boot_cpu_data.x86_clflush_size - 1));
802 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
803 (page_to_phys(page) & (1 << 17)) != 0;
805 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
806 user_data, page_do_bit17_swizzling,
807 partial_cacheline_write,
808 needs_clflush_after);
813 mutex_unlock(&dev->struct_mutex);
814 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
815 user_data, page_do_bit17_swizzling,
816 partial_cacheline_write,
817 needs_clflush_after);
819 mutex_lock(&dev->struct_mutex);
822 set_page_dirty(page);
823 mark_page_accessed(page);
828 remain -= page_length;
829 user_data += page_length;
830 offset += page_length;
834 i915_gem_object_unpin_pages(obj);
838 * Fixup: Flush cpu caches in case we didn't flush the dirty
839 * cachelines in-line while writing and the object moved
840 * out of the cpu write domain while we've dropped the lock.
842 if (!needs_clflush_after &&
843 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
844 if (i915_gem_clflush_object(obj, obj->pin_display))
845 i915_gem_chipset_flush(dev);
849 if (needs_clflush_after)
850 i915_gem_chipset_flush(dev);
856 * Writes data to the object referenced by handle.
858 * On error, the contents of the buffer that were to be modified are undefined.
861 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
862 struct drm_file *file)
864 struct drm_i915_gem_pwrite *args = data;
865 struct drm_i915_gem_object *obj;
871 if (!access_ok(VERIFY_READ,
872 to_user_ptr(args->data_ptr),
876 if (likely(!i915_prefault_disable)) {
877 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
883 ret = i915_mutex_lock_interruptible(dev);
887 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
888 if (&obj->base == NULL) {
893 /* Bounds check destination. */
894 if (args->offset > obj->base.size ||
895 args->size > obj->base.size - args->offset) {
900 /* prime objects have no backing filp to GEM pread/pwrite
903 if (!obj->base.filp) {
908 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
911 /* We can only do the GTT pwrite on untiled buffers, as otherwise
912 * it would end up going through the fenced access, and we'll get
913 * different detiling behavior between reading and writing.
914 * pread/pwrite currently are reading and writing from the CPU
915 * perspective, requiring manual detiling by the client.
918 ret = i915_gem_phys_pwrite(dev, obj, args, file);
922 if (obj->tiling_mode == I915_TILING_NONE &&
923 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
924 cpu_write_needs_clflush(obj)) {
925 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
926 /* Note that the gtt paths might fail with non-page-backed user
927 * pointers (e.g. gtt mappings when moving data between
928 * textures). Fallback to the shmem path in that case. */
931 if (ret == -EFAULT || ret == -ENOSPC)
932 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
935 drm_gem_object_unreference(&obj->base);
937 mutex_unlock(&dev->struct_mutex);
942 i915_gem_check_wedge(struct i915_gpu_error *error,
945 if (i915_reset_in_progress(error)) {
946 /* Non-interruptible callers can't handle -EAGAIN, hence return
947 * -EIO unconditionally for these. */
951 /* Recovery complete, but the reset failed ... */
952 if (i915_terminally_wedged(error))
962 * Compare seqno against outstanding lazy request. Emit a request if they are
966 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
970 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
973 if (seqno == ring->outstanding_lazy_request)
974 ret = i915_add_request(ring, NULL);
980 * __wait_seqno - wait until execution of seqno has finished
981 * @ring: the ring expected to report seqno
983 * @reset_counter: reset sequence associated with the given seqno
984 * @interruptible: do an interruptible wait (normally yes)
985 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
987 * Note: It is of utmost importance that the passed in seqno and reset_counter
988 * values have been read by the caller in an smp safe manner. Where read-side
989 * locks are involved, it is sufficient to read the reset_counter before
990 * unlocking the lock that protects the seqno. For lockless tricks, the
991 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
994 * Returns 0 if the seqno was found within the alloted time. Else returns the
995 * errno with remaining time filled in timeout argument.
997 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
998 unsigned reset_counter,
999 bool interruptible, struct timespec *timeout)
1001 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1002 struct timespec before, now, wait_time={1,0};
1003 unsigned long timeout_jiffies;
1005 bool wait_forever = true;
1008 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1011 trace_i915_gem_request_wait_begin(ring, seqno);
1013 if (timeout != NULL) {
1014 wait_time = *timeout;
1015 wait_forever = false;
1018 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1020 if (WARN_ON(!ring->irq_get(ring)))
1023 /* Record current time in case interrupted by signal, or wedged * */
1024 getrawmonotonic(&before);
1027 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1028 i915_reset_in_progress(&dev_priv->gpu_error) || \
1029 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1032 end = wait_event_interruptible_timeout(ring->irq_queue,
1036 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1039 /* We need to check whether any gpu reset happened in between
1040 * the caller grabbing the seqno and now ... */
1041 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1044 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1046 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1049 } while (end == 0 && wait_forever);
1051 getrawmonotonic(&now);
1053 ring->irq_put(ring);
1054 trace_i915_gem_request_wait_end(ring, seqno);
1058 struct timespec sleep_time = timespec_sub(now, before);
1059 *timeout = timespec_sub(*timeout, sleep_time);
1060 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1061 set_normalized_timespec(timeout, 0, 0);
1066 case -EAGAIN: /* Wedged */
1067 case -ERESTARTSYS: /* Signal */
1069 case 0: /* Timeout */
1071 default: /* Completed */
1072 WARN_ON(end < 0); /* We're not aware of other errors */
1078 * Waits for a sequence number to be signaled, and cleans up the
1079 * request and object lists appropriately for that event.
1082 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1084 struct drm_device *dev = ring->dev;
1085 struct drm_i915_private *dev_priv = dev->dev_private;
1086 bool interruptible = dev_priv->mm.interruptible;
1089 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1092 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1096 ret = i915_gem_check_olr(ring, seqno);
1100 return __wait_seqno(ring, seqno,
1101 atomic_read(&dev_priv->gpu_error.reset_counter),
1102 interruptible, NULL);
1106 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1107 struct intel_ring_buffer *ring)
1109 i915_gem_retire_requests_ring(ring);
1111 /* Manually manage the write flush as we may have not yet
1112 * retired the buffer.
1114 * Note that the last_write_seqno is always the earlier of
1115 * the two (read/write) seqno, so if we haved successfully waited,
1116 * we know we have passed the last write.
1118 obj->last_write_seqno = 0;
1119 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1125 * Ensures that all rendering to the object has completed and the object is
1126 * safe to unbind from the GTT or access from the CPU.
1128 static __must_check int
1129 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1132 struct intel_ring_buffer *ring = obj->ring;
1136 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1140 ret = i915_wait_seqno(ring, seqno);
1144 return i915_gem_object_wait_rendering__tail(obj, ring);
1147 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1148 * as the object state may change during this call.
1150 static __must_check int
1151 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1154 struct drm_device *dev = obj->base.dev;
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 struct intel_ring_buffer *ring = obj->ring;
1157 unsigned reset_counter;
1161 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1162 BUG_ON(!dev_priv->mm.interruptible);
1164 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1168 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1172 ret = i915_gem_check_olr(ring, seqno);
1176 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1177 mutex_unlock(&dev->struct_mutex);
1178 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1179 mutex_lock(&dev->struct_mutex);
1183 return i915_gem_object_wait_rendering__tail(obj, ring);
1187 * Called when user space prepares to use an object with the CPU, either
1188 * through the mmap ioctl's mapping or a GTT mapping.
1191 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1192 struct drm_file *file)
1194 struct drm_i915_gem_set_domain *args = data;
1195 struct drm_i915_gem_object *obj;
1196 uint32_t read_domains = args->read_domains;
1197 uint32_t write_domain = args->write_domain;
1200 /* Only handle setting domains to types used by the CPU. */
1201 if (write_domain & I915_GEM_GPU_DOMAINS)
1204 if (read_domains & I915_GEM_GPU_DOMAINS)
1207 /* Having something in the write domain implies it's in the read
1208 * domain, and only that read domain. Enforce that in the request.
1210 if (write_domain != 0 && read_domains != write_domain)
1213 ret = i915_mutex_lock_interruptible(dev);
1217 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1218 if (&obj->base == NULL) {
1223 /* Try to flush the object off the GPU without holding the lock.
1224 * We will repeat the flush holding the lock in the normal manner
1225 * to catch cases where we are gazumped.
1227 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1231 if (read_domains & I915_GEM_DOMAIN_GTT) {
1232 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1234 /* Silently promote "you're not bound, there was nothing to do"
1235 * to success, since the client was just asking us to
1236 * make sure everything was done.
1241 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1245 drm_gem_object_unreference(&obj->base);
1247 mutex_unlock(&dev->struct_mutex);
1252 * Called when user space has done writes to this buffer
1255 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1256 struct drm_file *file)
1258 struct drm_i915_gem_sw_finish *args = data;
1259 struct drm_i915_gem_object *obj;
1262 ret = i915_mutex_lock_interruptible(dev);
1266 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1267 if (&obj->base == NULL) {
1272 /* Pinned buffers may be scanout, so flush the cache */
1273 if (obj->pin_display)
1274 i915_gem_object_flush_cpu_write_domain(obj, true);
1276 drm_gem_object_unreference(&obj->base);
1278 mutex_unlock(&dev->struct_mutex);
1283 * Maps the contents of an object, returning the address it is mapped
1286 * While the mapping holds a reference on the contents of the object, it doesn't
1287 * imply a ref on the object itself.
1290 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1291 struct drm_file *file)
1293 struct drm_i915_gem_mmap *args = data;
1294 struct drm_gem_object *obj;
1297 obj = drm_gem_object_lookup(dev, file, args->handle);
1301 /* prime objects have no backing filp to GEM mmap
1305 drm_gem_object_unreference_unlocked(obj);
1309 addr = vm_mmap(obj->filp, 0, args->size,
1310 PROT_READ | PROT_WRITE, MAP_SHARED,
1312 drm_gem_object_unreference_unlocked(obj);
1313 if (IS_ERR((void *)addr))
1316 args->addr_ptr = (uint64_t) addr;
1322 * i915_gem_fault - fault a page into the GTT
1323 * vma: VMA in question
1326 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1327 * from userspace. The fault handler takes care of binding the object to
1328 * the GTT (if needed), allocating and programming a fence register (again,
1329 * only if needed based on whether the old reg is still valid or the object
1330 * is tiled) and inserting a new PTE into the faulting process.
1332 * Note that the faulting process may involve evicting existing objects
1333 * from the GTT and/or fence registers to make room. So performance may
1334 * suffer if the GTT working set is large or there are few fence registers
1337 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1339 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1340 struct drm_device *dev = obj->base.dev;
1341 drm_i915_private_t *dev_priv = dev->dev_private;
1342 pgoff_t page_offset;
1345 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1347 /* We don't use vmf->pgoff since that has the fake offset */
1348 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1351 ret = i915_mutex_lock_interruptible(dev);
1355 trace_i915_gem_object_fault(obj, page_offset, true, write);
1357 /* Access to snoopable pages through the GTT is incoherent. */
1358 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1363 /* Now bind it into the GTT if needed */
1364 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1368 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1372 ret = i915_gem_object_get_fence(obj);
1376 obj->fault_mappable = true;
1378 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1382 /* Finally, remap it using the new GTT offset */
1383 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1385 i915_gem_object_unpin(obj);
1387 mutex_unlock(&dev->struct_mutex);
1391 /* If this -EIO is due to a gpu hang, give the reset code a
1392 * chance to clean up the mess. Otherwise return the proper
1394 if (i915_terminally_wedged(&dev_priv->gpu_error))
1395 return VM_FAULT_SIGBUS;
1397 /* Give the error handler a chance to run and move the
1398 * objects off the GPU active list. Next time we service the
1399 * fault, we should be able to transition the page into the
1400 * GTT without touching the GPU (and so avoid further
1401 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1402 * with coherency, just lost writes.
1410 * EBUSY is ok: this just means that another thread
1411 * already did the job.
1413 return VM_FAULT_NOPAGE;
1415 return VM_FAULT_OOM;
1417 return VM_FAULT_SIGBUS;
1419 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1420 return VM_FAULT_SIGBUS;
1425 * i915_gem_release_mmap - remove physical page mappings
1426 * @obj: obj in question
1428 * Preserve the reservation of the mmapping with the DRM core code, but
1429 * relinquish ownership of the pages back to the system.
1431 * It is vital that we remove the page mapping if we have mapped a tiled
1432 * object through the GTT and then lose the fence register due to
1433 * resource pressure. Similarly if the object has been moved out of the
1434 * aperture, than pages mapped into userspace must be revoked. Removing the
1435 * mapping will then trigger a page fault on the next user access, allowing
1436 * fixup by i915_gem_fault().
1439 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1441 if (!obj->fault_mappable)
1444 if (obj->base.dev->dev_mapping)
1445 unmap_mapping_range(obj->base.dev->dev_mapping,
1446 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1449 obj->fault_mappable = false;
1453 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1457 if (INTEL_INFO(dev)->gen >= 4 ||
1458 tiling_mode == I915_TILING_NONE)
1461 /* Previous chips need a power-of-two fence region when tiling */
1462 if (INTEL_INFO(dev)->gen == 3)
1463 gtt_size = 1024*1024;
1465 gtt_size = 512*1024;
1467 while (gtt_size < size)
1474 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1475 * @obj: object to check
1477 * Return the required GTT alignment for an object, taking into account
1478 * potential fence register mapping.
1481 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1482 int tiling_mode, bool fenced)
1485 * Minimum alignment is 4k (GTT page size), but might be greater
1486 * if a fence register is needed for the object.
1488 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1489 tiling_mode == I915_TILING_NONE)
1493 * Previous chips need to be aligned to the size of the smallest
1494 * fence register that can contain the object.
1496 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1499 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1501 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1504 if (obj->base.map_list.map)
1507 dev_priv->mm.shrinker_no_lock_stealing = true;
1509 ret = drm_gem_create_mmap_offset(&obj->base);
1513 /* Badly fragmented mmap space? The only way we can recover
1514 * space is by destroying unwanted objects. We can't randomly release
1515 * mmap_offsets as userspace expects them to be persistent for the
1516 * lifetime of the objects. The closest we can is to release the
1517 * offsets on purgeable objects by truncating it and marking it purged,
1518 * which prevents userspace from ever using that object again.
1520 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1521 ret = drm_gem_create_mmap_offset(&obj->base);
1525 i915_gem_shrink_all(dev_priv);
1526 ret = drm_gem_create_mmap_offset(&obj->base);
1528 dev_priv->mm.shrinker_no_lock_stealing = false;
1533 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1535 if (!obj->base.map_list.map)
1538 drm_gem_free_mmap_offset(&obj->base);
1542 i915_gem_mmap_gtt(struct drm_file *file,
1543 struct drm_device *dev,
1547 struct drm_i915_private *dev_priv = dev->dev_private;
1548 struct drm_i915_gem_object *obj;
1551 ret = i915_mutex_lock_interruptible(dev);
1555 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1556 if (&obj->base == NULL) {
1561 if (obj->base.size > dev_priv->gtt.mappable_end) {
1566 if (obj->madv != I915_MADV_WILLNEED) {
1567 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1572 ret = i915_gem_object_create_mmap_offset(obj);
1576 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1579 drm_gem_object_unreference(&obj->base);
1581 mutex_unlock(&dev->struct_mutex);
1586 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1588 * @data: GTT mapping ioctl data
1589 * @file: GEM object info
1591 * Simply returns the fake offset to userspace so it can mmap it.
1592 * The mmap call will end up in drm_gem_mmap(), which will set things
1593 * up so we can get faults in the handler above.
1595 * The fault handler will take care of binding the object into the GTT
1596 * (since it may have been evicted to make room for something), allocating
1597 * a fence register, and mapping the appropriate aperture address into
1601 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1602 struct drm_file *file)
1604 struct drm_i915_gem_mmap_gtt *args = data;
1606 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1609 /* Immediately discard the backing storage */
1611 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1613 struct inode *inode;
1615 i915_gem_object_free_mmap_offset(obj);
1617 if (obj->base.filp == NULL)
1620 /* Our goal here is to return as much of the memory as
1621 * is possible back to the system as we are called from OOM.
1622 * To do this we must instruct the shmfs to drop all of its
1623 * backing pages, *now*.
1625 inode = file_inode(obj->base.filp);
1626 shmem_truncate_range(inode, 0, (loff_t)-1);
1628 obj->madv = __I915_MADV_PURGED;
1632 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1634 return obj->madv == I915_MADV_DONTNEED;
1638 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1640 struct sg_page_iter sg_iter;
1643 BUG_ON(obj->madv == __I915_MADV_PURGED);
1645 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1647 /* In the event of a disaster, abandon all caches and
1648 * hope for the best.
1650 WARN_ON(ret != -EIO);
1651 i915_gem_clflush_object(obj, true);
1652 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1655 if (i915_gem_object_needs_bit17_swizzle(obj))
1656 i915_gem_object_save_bit_17_swizzle(obj);
1658 if (obj->madv == I915_MADV_DONTNEED)
1661 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1662 struct page *page = sg_page_iter_page(&sg_iter);
1665 set_page_dirty(page);
1667 if (obj->madv == I915_MADV_WILLNEED)
1668 mark_page_accessed(page);
1670 page_cache_release(page);
1674 sg_free_table(obj->pages);
1679 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1681 const struct drm_i915_gem_object_ops *ops = obj->ops;
1683 if (obj->pages == NULL)
1686 if (obj->pages_pin_count)
1689 BUG_ON(i915_gem_obj_bound_any(obj));
1691 /* ->put_pages might need to allocate memory for the bit17 swizzle
1692 * array, hence protect them from being reaped by removing them from gtt
1694 list_del(&obj->global_list);
1696 ops->put_pages(obj);
1699 if (i915_gem_object_is_purgeable(obj))
1700 i915_gem_object_truncate(obj);
1706 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1707 bool purgeable_only)
1709 struct drm_i915_gem_object *obj, *next;
1712 list_for_each_entry_safe(obj, next,
1713 &dev_priv->mm.unbound_list,
1715 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1716 i915_gem_object_put_pages(obj) == 0) {
1717 count += obj->base.size >> PAGE_SHIFT;
1718 if (count >= target)
1723 list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
1725 struct i915_vma *vma, *v;
1727 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1730 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1731 if (i915_vma_unbind(vma))
1734 if (!i915_gem_object_put_pages(obj)) {
1735 count += obj->base.size >> PAGE_SHIFT;
1736 if (count >= target)
1745 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1747 return __i915_gem_shrink(dev_priv, target, true);
1751 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1753 struct drm_i915_gem_object *obj, *next;
1755 i915_gem_evict_everything(dev_priv->dev);
1757 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1759 i915_gem_object_put_pages(obj);
1763 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1765 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1767 struct address_space *mapping;
1768 struct sg_table *st;
1769 struct scatterlist *sg;
1770 struct sg_page_iter sg_iter;
1772 unsigned long last_pfn = 0; /* suppress gcc warning */
1775 /* Assert that the object is not currently in any GPU domain. As it
1776 * wasn't in the GTT, there shouldn't be any way it could have been in
1779 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1780 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1782 st = kmalloc(sizeof(*st), GFP_KERNEL);
1786 page_count = obj->base.size / PAGE_SIZE;
1787 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1793 /* Get the list of pages out of our struct file. They'll be pinned
1794 * at this point until we release them.
1796 * Fail silently without starting the shrinker
1798 mapping = file_inode(obj->base.filp)->i_mapping;
1799 gfp = mapping_gfp_mask(mapping);
1800 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1801 gfp &= ~(__GFP_IO | __GFP_WAIT);
1804 for (i = 0; i < page_count; i++) {
1805 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1807 i915_gem_purge(dev_priv, page_count);
1808 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1811 /* We've tried hard to allocate the memory by reaping
1812 * our own buffer, now let the real VM do its job and
1813 * go down in flames if truly OOM.
1815 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1816 gfp |= __GFP_IO | __GFP_WAIT;
1818 i915_gem_shrink_all(dev_priv);
1819 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1823 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1824 gfp &= ~(__GFP_IO | __GFP_WAIT);
1826 #ifdef CONFIG_SWIOTLB
1827 if (swiotlb_nr_tbl()) {
1829 sg_set_page(sg, page, PAGE_SIZE, 0);
1834 if (!i || page_to_pfn(page) != last_pfn + 1) {
1838 sg_set_page(sg, page, PAGE_SIZE, 0);
1840 sg->length += PAGE_SIZE;
1842 last_pfn = page_to_pfn(page);
1844 #ifdef CONFIG_SWIOTLB
1845 if (!swiotlb_nr_tbl())
1850 if (i915_gem_object_needs_bit17_swizzle(obj))
1851 i915_gem_object_do_bit_17_swizzle(obj);
1857 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1858 page_cache_release(sg_page_iter_page(&sg_iter));
1861 return PTR_ERR(page);
1864 /* Ensure that the associated pages are gathered from the backing storage
1865 * and pinned into our object. i915_gem_object_get_pages() may be called
1866 * multiple times before they are released by a single call to
1867 * i915_gem_object_put_pages() - once the pages are no longer referenced
1868 * either as a result of memory pressure (reaping pages under the shrinker)
1869 * or as the object is itself released.
1872 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1874 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1875 const struct drm_i915_gem_object_ops *ops = obj->ops;
1881 if (obj->madv != I915_MADV_WILLNEED) {
1882 DRM_ERROR("Attempting to obtain a purgeable object\n");
1886 BUG_ON(obj->pages_pin_count);
1888 ret = ops->get_pages(obj);
1892 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1897 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1898 struct intel_ring_buffer *ring)
1900 struct drm_device *dev = obj->base.dev;
1901 struct drm_i915_private *dev_priv = dev->dev_private;
1902 u32 seqno = intel_ring_get_seqno(ring);
1904 BUG_ON(ring == NULL);
1905 if (obj->ring != ring && obj->last_write_seqno) {
1906 /* Keep the seqno relative to the current ring */
1907 obj->last_write_seqno = seqno;
1911 /* Add a reference if we're newly entering the active list. */
1913 drm_gem_object_reference(&obj->base);
1917 list_move_tail(&obj->ring_list, &ring->active_list);
1919 obj->last_read_seqno = seqno;
1921 if (obj->fenced_gpu_access) {
1922 obj->last_fenced_seqno = seqno;
1924 /* Bump MRU to take account of the delayed flush */
1925 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1926 struct drm_i915_fence_reg *reg;
1928 reg = &dev_priv->fence_regs[obj->fence_reg];
1929 list_move_tail(®->lru_list,
1930 &dev_priv->mm.fence_list);
1936 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1938 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1939 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1940 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1942 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1943 BUG_ON(!obj->active);
1945 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1947 list_del_init(&obj->ring_list);
1950 obj->last_read_seqno = 0;
1951 obj->last_write_seqno = 0;
1952 obj->base.write_domain = 0;
1954 obj->last_fenced_seqno = 0;
1955 obj->fenced_gpu_access = false;
1958 drm_gem_object_unreference(&obj->base);
1960 WARN_ON(i915_verify_lists(dev));
1964 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1966 struct drm_i915_private *dev_priv = dev->dev_private;
1967 struct intel_ring_buffer *ring;
1970 /* Carefully retire all requests without writing to the rings */
1971 for_each_ring(ring, dev_priv, i) {
1972 ret = intel_ring_idle(ring);
1976 i915_gem_retire_requests(dev);
1978 /* Finally reset hw state */
1979 for_each_ring(ring, dev_priv, i) {
1980 intel_ring_init_seqno(ring, seqno);
1982 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1983 ring->sync_seqno[j] = 0;
1989 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1997 /* HWS page needs to be set less than what we
1998 * will inject to ring
2000 ret = i915_gem_init_seqno(dev, seqno - 1);
2004 /* Carefully set the last_seqno value so that wrap
2005 * detection still works
2007 dev_priv->next_seqno = seqno;
2008 dev_priv->last_seqno = seqno - 1;
2009 if (dev_priv->last_seqno == 0)
2010 dev_priv->last_seqno--;
2016 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2018 struct drm_i915_private *dev_priv = dev->dev_private;
2020 /* reserve 0 for non-seqno */
2021 if (dev_priv->next_seqno == 0) {
2022 int ret = i915_gem_init_seqno(dev, 0);
2026 dev_priv->next_seqno = 1;
2029 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2033 int __i915_add_request(struct intel_ring_buffer *ring,
2034 struct drm_file *file,
2035 struct drm_i915_gem_object *obj,
2038 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2039 struct drm_i915_gem_request *request;
2040 u32 request_ring_position, request_start;
2044 request_start = intel_ring_get_tail(ring);
2046 * Emit any outstanding flushes - execbuf can fail to emit the flush
2047 * after having emitted the batchbuffer command. Hence we need to fix
2048 * things up similar to emitting the lazy request. The difference here
2049 * is that the flush _must_ happen before the next request, no matter
2052 ret = intel_ring_flush_all_caches(ring);
2056 request = kmalloc(sizeof(*request), GFP_KERNEL);
2057 if (request == NULL)
2061 /* Record the position of the start of the request so that
2062 * should we detect the updated seqno part-way through the
2063 * GPU processing the request, we never over-estimate the
2064 * position of the head.
2066 request_ring_position = intel_ring_get_tail(ring);
2068 ret = ring->add_request(ring);
2074 request->seqno = intel_ring_get_seqno(ring);
2075 request->ring = ring;
2076 request->head = request_start;
2077 request->tail = request_ring_position;
2078 request->ctx = ring->last_context;
2079 request->batch_obj = obj;
2081 /* Whilst this request exists, batch_obj will be on the
2082 * active_list, and so will hold the active reference. Only when this
2083 * request is retired will the the batch_obj be moved onto the
2084 * inactive_list and lose its active reference. Hence we do not need
2085 * to explicitly hold another reference here.
2089 i915_gem_context_reference(request->ctx);
2091 request->emitted_jiffies = jiffies;
2092 was_empty = list_empty(&ring->request_list);
2093 list_add_tail(&request->list, &ring->request_list);
2094 request->file_priv = NULL;
2097 struct drm_i915_file_private *file_priv = file->driver_priv;
2099 spin_lock(&file_priv->mm.lock);
2100 request->file_priv = file_priv;
2101 list_add_tail(&request->client_list,
2102 &file_priv->mm.request_list);
2103 spin_unlock(&file_priv->mm.lock);
2106 trace_i915_gem_request_add(ring, request->seqno);
2107 ring->outstanding_lazy_request = 0;
2109 if (!dev_priv->ums.mm_suspended) {
2110 i915_queue_hangcheck(ring->dev);
2113 queue_delayed_work(dev_priv->wq,
2114 &dev_priv->mm.retire_work,
2115 round_jiffies_up_relative(HZ));
2116 intel_mark_busy(dev_priv->dev);
2121 *out_seqno = request->seqno;
2126 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2128 struct drm_i915_file_private *file_priv = request->file_priv;
2133 spin_lock(&file_priv->mm.lock);
2134 if (request->file_priv) {
2135 list_del(&request->client_list);
2136 request->file_priv = NULL;
2138 spin_unlock(&file_priv->mm.lock);
2141 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2142 struct i915_address_space *vm)
2144 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2145 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2151 static bool i915_head_inside_request(const u32 acthd_unmasked,
2152 const u32 request_start,
2153 const u32 request_end)
2155 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2157 if (request_start < request_end) {
2158 if (acthd >= request_start && acthd < request_end)
2160 } else if (request_start > request_end) {
2161 if (acthd >= request_start || acthd < request_end)
2168 static struct i915_address_space *
2169 request_to_vm(struct drm_i915_gem_request *request)
2171 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2172 struct i915_address_space *vm;
2174 vm = &dev_priv->gtt.base;
2179 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2180 const u32 acthd, bool *inside)
2182 /* There is a possibility that unmasked head address
2183 * pointing inside the ring, matches the batch_obj address range.
2184 * However this is extremely unlikely.
2186 if (request->batch_obj) {
2187 if (i915_head_inside_object(acthd, request->batch_obj,
2188 request_to_vm(request))) {
2194 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2202 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2203 struct drm_i915_gem_request *request,
2206 struct i915_ctx_hang_stats *hs = NULL;
2207 bool inside, guilty;
2208 unsigned long offset = 0;
2210 /* Innocent until proven guilty */
2213 if (request->batch_obj)
2214 offset = i915_gem_obj_offset(request->batch_obj,
2215 request_to_vm(request));
2217 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2218 i915_request_guilty(request, acthd, &inside)) {
2219 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2221 inside ? "inside" : "flushing",
2223 request->ctx ? request->ctx->id : 0,
2229 /* If contexts are disabled or this is the default context, use
2230 * file_priv->reset_state
2232 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2233 hs = &request->ctx->hang_stats;
2234 else if (request->file_priv)
2235 hs = &request->file_priv->hang_stats;
2241 hs->batch_pending++;
2245 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2247 list_del(&request->list);
2248 i915_gem_request_remove_from_client(request);
2251 i915_gem_context_unreference(request->ctx);
2256 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2257 struct intel_ring_buffer *ring)
2259 u32 completed_seqno;
2262 acthd = intel_ring_get_active_head(ring);
2263 completed_seqno = ring->get_seqno(ring, false);
2265 while (!list_empty(&ring->request_list)) {
2266 struct drm_i915_gem_request *request;
2268 request = list_first_entry(&ring->request_list,
2269 struct drm_i915_gem_request,
2272 if (request->seqno > completed_seqno)
2273 i915_set_reset_status(ring, request, acthd);
2275 i915_gem_free_request(request);
2278 while (!list_empty(&ring->active_list)) {
2279 struct drm_i915_gem_object *obj;
2281 obj = list_first_entry(&ring->active_list,
2282 struct drm_i915_gem_object,
2285 i915_gem_object_move_to_inactive(obj);
2289 void i915_gem_restore_fences(struct drm_device *dev)
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2294 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2295 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2298 * Commit delayed tiling changes if we have an object still
2299 * attached to the fence, otherwise just clear the fence.
2302 i915_gem_object_update_fence(reg->obj, reg,
2303 reg->obj->tiling_mode);
2305 i915_gem_write_fence(dev, i, NULL);
2310 void i915_gem_reset(struct drm_device *dev)
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_ring_buffer *ring;
2316 for_each_ring(ring, dev_priv, i)
2317 i915_gem_reset_ring_lists(dev_priv, ring);
2319 i915_gem_restore_fences(dev);
2323 * This function clears the request list as sequence numbers are passed.
2326 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2330 if (list_empty(&ring->request_list))
2333 WARN_ON(i915_verify_lists(ring->dev));
2335 seqno = ring->get_seqno(ring, true);
2337 while (!list_empty(&ring->request_list)) {
2338 struct drm_i915_gem_request *request;
2340 request = list_first_entry(&ring->request_list,
2341 struct drm_i915_gem_request,
2344 if (!i915_seqno_passed(seqno, request->seqno))
2347 trace_i915_gem_request_retire(ring, request->seqno);
2348 /* We know the GPU must have read the request to have
2349 * sent us the seqno + interrupt, so use the position
2350 * of tail of the request to update the last known position
2353 ring->last_retired_head = request->tail;
2355 i915_gem_free_request(request);
2358 /* Move any buffers on the active list that are no longer referenced
2359 * by the ringbuffer to the flushing/inactive lists as appropriate.
2361 while (!list_empty(&ring->active_list)) {
2362 struct drm_i915_gem_object *obj;
2364 obj = list_first_entry(&ring->active_list,
2365 struct drm_i915_gem_object,
2368 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2371 i915_gem_object_move_to_inactive(obj);
2374 if (unlikely(ring->trace_irq_seqno &&
2375 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2376 ring->irq_put(ring);
2377 ring->trace_irq_seqno = 0;
2380 WARN_ON(i915_verify_lists(ring->dev));
2384 i915_gem_retire_requests(struct drm_device *dev)
2386 drm_i915_private_t *dev_priv = dev->dev_private;
2387 struct intel_ring_buffer *ring;
2390 for_each_ring(ring, dev_priv, i)
2391 i915_gem_retire_requests_ring(ring);
2395 i915_gem_retire_work_handler(struct work_struct *work)
2397 drm_i915_private_t *dev_priv;
2398 struct drm_device *dev;
2399 struct intel_ring_buffer *ring;
2403 dev_priv = container_of(work, drm_i915_private_t,
2404 mm.retire_work.work);
2405 dev = dev_priv->dev;
2407 /* Come back later if the device is busy... */
2408 if (!mutex_trylock(&dev->struct_mutex)) {
2409 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2410 round_jiffies_up_relative(HZ));
2414 i915_gem_retire_requests(dev);
2416 /* Send a periodic flush down the ring so we don't hold onto GEM
2417 * objects indefinitely.
2420 for_each_ring(ring, dev_priv, i) {
2421 if (ring->gpu_caches_dirty)
2422 i915_add_request(ring, NULL);
2424 idle &= list_empty(&ring->request_list);
2427 if (!dev_priv->ums.mm_suspended && !idle)
2428 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2429 round_jiffies_up_relative(HZ));
2431 intel_mark_idle(dev);
2433 mutex_unlock(&dev->struct_mutex);
2437 * Ensures that an object will eventually get non-busy by flushing any required
2438 * write domains, emitting any outstanding lazy request and retiring and
2439 * completed requests.
2442 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2447 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2451 i915_gem_retire_requests_ring(obj->ring);
2458 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2459 * @DRM_IOCTL_ARGS: standard ioctl arguments
2461 * Returns 0 if successful, else an error is returned with the remaining time in
2462 * the timeout parameter.
2463 * -ETIME: object is still busy after timeout
2464 * -ERESTARTSYS: signal interrupted the wait
2465 * -ENONENT: object doesn't exist
2466 * Also possible, but rare:
2467 * -EAGAIN: GPU wedged
2469 * -ENODEV: Internal IRQ fail
2470 * -E?: The add request failed
2472 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2473 * non-zero timeout parameter the wait ioctl will wait for the given number of
2474 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2475 * without holding struct_mutex the object may become re-busied before this
2476 * function completes. A similar but shorter * race condition exists in the busy
2480 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2482 drm_i915_private_t *dev_priv = dev->dev_private;
2483 struct drm_i915_gem_wait *args = data;
2484 struct drm_i915_gem_object *obj;
2485 struct intel_ring_buffer *ring = NULL;
2486 struct timespec timeout_stack, *timeout = NULL;
2487 unsigned reset_counter;
2491 if (args->timeout_ns >= 0) {
2492 timeout_stack = ns_to_timespec(args->timeout_ns);
2493 timeout = &timeout_stack;
2496 ret = i915_mutex_lock_interruptible(dev);
2500 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2501 if (&obj->base == NULL) {
2502 mutex_unlock(&dev->struct_mutex);
2506 /* Need to make sure the object gets inactive eventually. */
2507 ret = i915_gem_object_flush_active(obj);
2512 seqno = obj->last_read_seqno;
2519 /* Do this after OLR check to make sure we make forward progress polling
2520 * on this IOCTL with a 0 timeout (like busy ioctl)
2522 if (!args->timeout_ns) {
2527 drm_gem_object_unreference(&obj->base);
2528 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2529 mutex_unlock(&dev->struct_mutex);
2531 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2533 args->timeout_ns = timespec_to_ns(timeout);
2537 drm_gem_object_unreference(&obj->base);
2538 mutex_unlock(&dev->struct_mutex);
2543 * i915_gem_object_sync - sync an object to a ring.
2545 * @obj: object which may be in use on another ring.
2546 * @to: ring we wish to use the object on. May be NULL.
2548 * This code is meant to abstract object synchronization with the GPU.
2549 * Calling with NULL implies synchronizing the object with the CPU
2550 * rather than a particular GPU ring.
2552 * Returns 0 if successful, else propagates up the lower layer error.
2555 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2556 struct intel_ring_buffer *to)
2558 struct intel_ring_buffer *from = obj->ring;
2562 if (from == NULL || to == from)
2565 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2566 return i915_gem_object_wait_rendering(obj, false);
2568 idx = intel_ring_sync_index(from, to);
2570 seqno = obj->last_read_seqno;
2571 if (seqno <= from->sync_seqno[idx])
2574 ret = i915_gem_check_olr(obj->ring, seqno);
2578 ret = to->sync_to(to, from, seqno);
2580 /* We use last_read_seqno because sync_to()
2581 * might have just caused seqno wrap under
2584 from->sync_seqno[idx] = obj->last_read_seqno;
2589 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2591 u32 old_write_domain, old_read_domains;
2593 /* Force a pagefault for domain tracking on next user access */
2594 i915_gem_release_mmap(obj);
2596 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2599 /* Wait for any direct GTT access to complete */
2602 old_read_domains = obj->base.read_domains;
2603 old_write_domain = obj->base.write_domain;
2605 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2606 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2608 trace_i915_gem_object_change_domain(obj,
2613 int i915_vma_unbind(struct i915_vma *vma)
2615 struct drm_i915_gem_object *obj = vma->obj;
2616 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2619 if (list_empty(&vma->vma_link))
2625 BUG_ON(obj->pages == NULL);
2627 ret = i915_gem_object_finish_gpu(obj);
2630 /* Continue on if we fail due to EIO, the GPU is hung so we
2631 * should be safe and we need to cleanup or else we might
2632 * cause memory corruption through use-after-free.
2635 i915_gem_object_finish_gtt(obj);
2637 /* release the fence reg _after_ flushing */
2638 ret = i915_gem_object_put_fence(obj);
2642 trace_i915_vma_unbind(vma);
2644 if (obj->has_global_gtt_mapping)
2645 i915_gem_gtt_unbind_object(obj);
2646 if (obj->has_aliasing_ppgtt_mapping) {
2647 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2648 obj->has_aliasing_ppgtt_mapping = 0;
2650 i915_gem_gtt_finish_object(obj);
2651 i915_gem_object_unpin_pages(obj);
2653 list_del(&vma->mm_list);
2654 /* Avoid an unnecessary call to unbind on rebind. */
2655 if (i915_is_ggtt(vma->vm))
2656 obj->map_and_fenceable = true;
2658 drm_mm_remove_node(&vma->node);
2659 i915_gem_vma_destroy(vma);
2661 /* Since the unbound list is global, only move to that list if
2662 * no more VMAs exist.
2663 * NB: Until we have real VMAs there will only ever be one */
2664 WARN_ON(!list_empty(&obj->vma_list));
2665 if (list_empty(&obj->vma_list))
2666 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2672 * Unbinds an object from the global GTT aperture.
2675 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2677 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2678 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2680 if (!i915_gem_obj_ggtt_bound(obj))
2686 BUG_ON(obj->pages == NULL);
2688 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2691 int i915_gpu_idle(struct drm_device *dev)
2693 drm_i915_private_t *dev_priv = dev->dev_private;
2694 struct intel_ring_buffer *ring;
2697 /* Flush everything onto the inactive list. */
2698 for_each_ring(ring, dev_priv, i) {
2699 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2703 ret = intel_ring_idle(ring);
2711 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2712 struct drm_i915_gem_object *obj)
2714 drm_i915_private_t *dev_priv = dev->dev_private;
2716 int fence_pitch_shift;
2718 if (INTEL_INFO(dev)->gen >= 6) {
2719 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2720 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2722 fence_reg = FENCE_REG_965_0;
2723 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2726 fence_reg += reg * 8;
2728 /* To w/a incoherency with non-atomic 64-bit register updates,
2729 * we split the 64-bit update into two 32-bit writes. In order
2730 * for a partial fence not to be evaluated between writes, we
2731 * precede the update with write to turn off the fence register,
2732 * and only enable the fence as the last step.
2734 * For extra levels of paranoia, we make sure each step lands
2735 * before applying the next step.
2737 I915_WRITE(fence_reg, 0);
2738 POSTING_READ(fence_reg);
2741 u32 size = i915_gem_obj_ggtt_size(obj);
2744 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2746 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2747 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2748 if (obj->tiling_mode == I915_TILING_Y)
2749 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2750 val |= I965_FENCE_REG_VALID;
2752 I915_WRITE(fence_reg + 4, val >> 32);
2753 POSTING_READ(fence_reg + 4);
2755 I915_WRITE(fence_reg + 0, val);
2756 POSTING_READ(fence_reg);
2758 I915_WRITE(fence_reg + 4, 0);
2759 POSTING_READ(fence_reg + 4);
2763 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2764 struct drm_i915_gem_object *obj)
2766 drm_i915_private_t *dev_priv = dev->dev_private;
2770 u32 size = i915_gem_obj_ggtt_size(obj);
2774 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2775 (size & -size) != size ||
2776 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2777 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2778 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2780 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2785 /* Note: pitch better be a power of two tile widths */
2786 pitch_val = obj->stride / tile_width;
2787 pitch_val = ffs(pitch_val) - 1;
2789 val = i915_gem_obj_ggtt_offset(obj);
2790 if (obj->tiling_mode == I915_TILING_Y)
2791 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2792 val |= I915_FENCE_SIZE_BITS(size);
2793 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2794 val |= I830_FENCE_REG_VALID;
2799 reg = FENCE_REG_830_0 + reg * 4;
2801 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2803 I915_WRITE(reg, val);
2807 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2808 struct drm_i915_gem_object *obj)
2810 drm_i915_private_t *dev_priv = dev->dev_private;
2814 u32 size = i915_gem_obj_ggtt_size(obj);
2817 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2818 (size & -size) != size ||
2819 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2820 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2821 i915_gem_obj_ggtt_offset(obj), size);
2823 pitch_val = obj->stride / 128;
2824 pitch_val = ffs(pitch_val) - 1;
2826 val = i915_gem_obj_ggtt_offset(obj);
2827 if (obj->tiling_mode == I915_TILING_Y)
2828 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2829 val |= I830_FENCE_SIZE_BITS(size);
2830 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2831 val |= I830_FENCE_REG_VALID;
2835 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2836 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2839 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2841 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2844 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2845 struct drm_i915_gem_object *obj)
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2849 /* Ensure that all CPU reads are completed before installing a fence
2850 * and all writes before removing the fence.
2852 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2855 WARN(obj && (!obj->stride || !obj->tiling_mode),
2856 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2857 obj->stride, obj->tiling_mode);
2859 switch (INTEL_INFO(dev)->gen) {
2863 case 4: i965_write_fence_reg(dev, reg, obj); break;
2864 case 3: i915_write_fence_reg(dev, reg, obj); break;
2865 case 2: i830_write_fence_reg(dev, reg, obj); break;
2869 /* And similarly be paranoid that no direct access to this region
2870 * is reordered to before the fence is installed.
2872 if (i915_gem_object_needs_mb(obj))
2876 static inline int fence_number(struct drm_i915_private *dev_priv,
2877 struct drm_i915_fence_reg *fence)
2879 return fence - dev_priv->fence_regs;
2882 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2883 struct drm_i915_fence_reg *fence,
2886 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2887 int reg = fence_number(dev_priv, fence);
2889 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2892 obj->fence_reg = reg;
2894 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2896 obj->fence_reg = I915_FENCE_REG_NONE;
2898 list_del_init(&fence->lru_list);
2900 obj->fence_dirty = false;
2904 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2906 if (obj->last_fenced_seqno) {
2907 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2911 obj->last_fenced_seqno = 0;
2914 obj->fenced_gpu_access = false;
2919 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2921 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2922 struct drm_i915_fence_reg *fence;
2925 ret = i915_gem_object_wait_fence(obj);
2929 if (obj->fence_reg == I915_FENCE_REG_NONE)
2932 fence = &dev_priv->fence_regs[obj->fence_reg];
2934 i915_gem_object_fence_lost(obj);
2935 i915_gem_object_update_fence(obj, fence, false);
2940 static struct drm_i915_fence_reg *
2941 i915_find_fence_reg(struct drm_device *dev)
2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944 struct drm_i915_fence_reg *reg, *avail;
2947 /* First try to find a free reg */
2949 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2950 reg = &dev_priv->fence_regs[i];
2954 if (!reg->pin_count)
2961 /* None available, try to steal one or wait for a user to finish */
2962 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2973 * i915_gem_object_get_fence - set up fencing for an object
2974 * @obj: object to map through a fence reg
2976 * When mapping objects through the GTT, userspace wants to be able to write
2977 * to them without having to worry about swizzling if the object is tiled.
2978 * This function walks the fence regs looking for a free one for @obj,
2979 * stealing one if it can't find any.
2981 * It then sets up the reg based on the object's properties: address, pitch
2982 * and tiling format.
2984 * For an untiled surface, this removes any existing fence.
2987 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2989 struct drm_device *dev = obj->base.dev;
2990 struct drm_i915_private *dev_priv = dev->dev_private;
2991 bool enable = obj->tiling_mode != I915_TILING_NONE;
2992 struct drm_i915_fence_reg *reg;
2995 /* Have we updated the tiling parameters upon the object and so
2996 * will need to serialise the write to the associated fence register?
2998 if (obj->fence_dirty) {
2999 ret = i915_gem_object_wait_fence(obj);
3004 /* Just update our place in the LRU if our fence is getting reused. */
3005 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3006 reg = &dev_priv->fence_regs[obj->fence_reg];
3007 if (!obj->fence_dirty) {
3008 list_move_tail(®->lru_list,
3009 &dev_priv->mm.fence_list);
3012 } else if (enable) {
3013 reg = i915_find_fence_reg(dev);
3018 struct drm_i915_gem_object *old = reg->obj;
3020 ret = i915_gem_object_wait_fence(old);
3024 i915_gem_object_fence_lost(old);
3029 i915_gem_object_update_fence(obj, reg, enable);
3034 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3035 struct drm_mm_node *gtt_space,
3036 unsigned long cache_level)
3038 struct drm_mm_node *other;
3040 /* On non-LLC machines we have to be careful when putting differing
3041 * types of snoopable memory together to avoid the prefetcher
3042 * crossing memory domains and dying.
3047 if (!drm_mm_node_allocated(gtt_space))
3050 if (list_empty(>t_space->node_list))
3053 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3054 if (other->allocated && !other->hole_follows && other->color != cache_level)
3057 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3058 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3064 static void i915_gem_verify_gtt(struct drm_device *dev)
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3068 struct drm_i915_gem_object *obj;
3071 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3072 if (obj->gtt_space == NULL) {
3073 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3078 if (obj->cache_level != obj->gtt_space->color) {
3079 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3080 i915_gem_obj_ggtt_offset(obj),
3081 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3083 obj->gtt_space->color);
3088 if (!i915_gem_valid_gtt_space(dev,
3090 obj->cache_level)) {
3091 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3092 i915_gem_obj_ggtt_offset(obj),
3093 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3105 * Finds free space in the GTT aperture and binds the object there.
3108 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3109 struct i915_address_space *vm,
3111 bool map_and_fenceable,
3114 struct drm_device *dev = obj->base.dev;
3115 drm_i915_private_t *dev_priv = dev->dev_private;
3116 u32 size, fence_size, fence_alignment, unfenced_alignment;
3117 bool mappable, fenceable;
3119 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3120 struct i915_vma *vma;
3123 if (WARN_ON(!list_empty(&obj->vma_list)))
3126 fence_size = i915_gem_get_gtt_size(dev,
3129 fence_alignment = i915_gem_get_gtt_alignment(dev,
3131 obj->tiling_mode, true);
3132 unfenced_alignment =
3133 i915_gem_get_gtt_alignment(dev,
3135 obj->tiling_mode, false);
3138 alignment = map_and_fenceable ? fence_alignment :
3140 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3141 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3145 size = map_and_fenceable ? fence_size : obj->base.size;
3147 /* If the object is bigger than the entire aperture, reject it early
3148 * before evicting everything in a vain attempt to find space.
3150 if (obj->base.size > gtt_max) {
3151 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3153 map_and_fenceable ? "mappable" : "total",
3158 ret = i915_gem_object_get_pages(obj);
3162 i915_gem_object_pin_pages(obj);
3164 /* FIXME: For now we only ever use 1 VMA per object */
3165 BUG_ON(!i915_is_ggtt(vm));
3166 WARN_ON(!list_empty(&obj->vma_list));
3168 vma = i915_gem_vma_create(obj, vm);
3175 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3177 obj->cache_level, 0, gtt_max);
3179 ret = i915_gem_evict_something(dev, vm, size, alignment,
3188 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3189 obj->cache_level))) {
3191 goto err_remove_node;
3194 ret = i915_gem_gtt_prepare_object(obj);
3196 goto err_remove_node;
3198 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3199 list_add_tail(&vma->mm_list, &vm->inactive_list);
3203 i915_gem_obj_ggtt_size(obj) == fence_size &&
3204 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3208 vma->node.start + obj->base.size <= dev_priv->gtt.mappable_end;
3210 /* Map and fenceable only changes if the VM is the global GGTT */
3211 if (i915_is_ggtt(vm))
3212 obj->map_and_fenceable = mappable && fenceable;
3214 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3216 trace_i915_vma_bind(vma, map_and_fenceable);
3217 i915_gem_verify_gtt(dev);
3221 drm_mm_remove_node(&vma->node);
3223 i915_gem_vma_destroy(vma);
3225 i915_gem_object_unpin_pages(obj);
3230 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3233 /* If we don't have a page list set up, then we're not pinned
3234 * to GPU, and we can ignore the cache flush because it'll happen
3235 * again at bind time.
3237 if (obj->pages == NULL)
3241 * Stolen memory is always coherent with the GPU as it is explicitly
3242 * marked as wc by the system, or the system is cache-coherent.
3247 /* If the GPU is snooping the contents of the CPU cache,
3248 * we do not need to manually clear the CPU cache lines. However,
3249 * the caches are only snooped when the render cache is
3250 * flushed/invalidated. As we always have to emit invalidations
3251 * and flushes when moving into and out of the RENDER domain, correct
3252 * snooping behaviour occurs naturally as the result of our domain
3255 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3258 trace_i915_gem_object_clflush(obj);
3259 drm_clflush_sg(obj->pages);
3264 /** Flushes the GTT write domain for the object if it's dirty. */
3266 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3268 uint32_t old_write_domain;
3270 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3273 /* No actual flushing is required for the GTT write domain. Writes
3274 * to it immediately go to main memory as far as we know, so there's
3275 * no chipset flush. It also doesn't land in render cache.
3277 * However, we do have to enforce the order so that all writes through
3278 * the GTT land before any writes to the device, such as updates to
3283 old_write_domain = obj->base.write_domain;
3284 obj->base.write_domain = 0;
3286 trace_i915_gem_object_change_domain(obj,
3287 obj->base.read_domains,
3291 /** Flushes the CPU write domain for the object if it's dirty. */
3293 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3296 uint32_t old_write_domain;
3298 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3301 if (i915_gem_clflush_object(obj, force))
3302 i915_gem_chipset_flush(obj->base.dev);
3304 old_write_domain = obj->base.write_domain;
3305 obj->base.write_domain = 0;
3307 trace_i915_gem_object_change_domain(obj,
3308 obj->base.read_domains,
3313 * Moves a single object to the GTT read, and possibly write domain.
3315 * This function returns when the move is complete, including waiting on
3319 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3321 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3322 uint32_t old_write_domain, old_read_domains;
3325 /* Not valid to be called on unbound objects. */
3326 if (!i915_gem_obj_bound_any(obj))
3329 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3332 ret = i915_gem_object_wait_rendering(obj, !write);
3336 i915_gem_object_flush_cpu_write_domain(obj, false);
3338 /* Serialise direct access to this object with the barriers for
3339 * coherent writes from the GPU, by effectively invalidating the
3340 * GTT domain upon first access.
3342 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3345 old_write_domain = obj->base.write_domain;
3346 old_read_domains = obj->base.read_domains;
3348 /* It should now be out of any other write domains, and we can update
3349 * the domain values for our changes.
3351 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3352 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3354 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3355 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3359 trace_i915_gem_object_change_domain(obj,
3363 /* And bump the LRU for this access */
3364 if (i915_gem_object_is_inactive(obj)) {
3365 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3366 &dev_priv->gtt.base);
3368 list_move_tail(&vma->mm_list,
3369 &dev_priv->gtt.base.inactive_list);
3376 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3377 enum i915_cache_level cache_level)
3379 struct drm_device *dev = obj->base.dev;
3380 drm_i915_private_t *dev_priv = dev->dev_private;
3381 struct i915_vma *vma;
3384 if (obj->cache_level == cache_level)
3387 if (obj->pin_count) {
3388 DRM_DEBUG("can not change the cache level of pinned objects\n");
3392 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3393 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3394 ret = i915_vma_unbind(vma);
3402 if (i915_gem_obj_bound_any(obj)) {
3403 ret = i915_gem_object_finish_gpu(obj);
3407 i915_gem_object_finish_gtt(obj);
3409 /* Before SandyBridge, you could not use tiling or fence
3410 * registers with snooped memory, so relinquish any fences
3411 * currently pointing to our region in the aperture.
3413 if (INTEL_INFO(dev)->gen < 6) {
3414 ret = i915_gem_object_put_fence(obj);
3419 if (obj->has_global_gtt_mapping)
3420 i915_gem_gtt_bind_object(obj, cache_level);
3421 if (obj->has_aliasing_ppgtt_mapping)
3422 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3426 list_for_each_entry(vma, &obj->vma_list, vma_link)
3427 vma->node.color = cache_level;
3428 obj->cache_level = cache_level;
3430 if (cpu_write_needs_clflush(obj)) {
3431 u32 old_read_domains, old_write_domain;
3433 /* If we're coming from LLC cached, then we haven't
3434 * actually been tracking whether the data is in the
3435 * CPU cache or not, since we only allow one bit set
3436 * in obj->write_domain and have been skipping the clflushes.
3437 * Just set it to the CPU cache for now.
3439 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3440 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3442 old_read_domains = obj->base.read_domains;
3443 old_write_domain = obj->base.write_domain;
3445 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3446 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3448 trace_i915_gem_object_change_domain(obj,
3453 i915_gem_verify_gtt(dev);
3457 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3458 struct drm_file *file)
3460 struct drm_i915_gem_caching *args = data;
3461 struct drm_i915_gem_object *obj;
3464 ret = i915_mutex_lock_interruptible(dev);
3468 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3469 if (&obj->base == NULL) {
3474 switch (obj->cache_level) {
3475 case I915_CACHE_LLC:
3476 case I915_CACHE_L3_LLC:
3477 args->caching = I915_CACHING_CACHED;
3481 args->caching = I915_CACHING_DISPLAY;
3485 args->caching = I915_CACHING_NONE;
3489 drm_gem_object_unreference(&obj->base);
3491 mutex_unlock(&dev->struct_mutex);
3495 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3496 struct drm_file *file)
3498 struct drm_i915_gem_caching *args = data;
3499 struct drm_i915_gem_object *obj;
3500 enum i915_cache_level level;
3503 switch (args->caching) {
3504 case I915_CACHING_NONE:
3505 level = I915_CACHE_NONE;
3507 case I915_CACHING_CACHED:
3508 level = I915_CACHE_LLC;
3510 case I915_CACHING_DISPLAY:
3511 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3517 ret = i915_mutex_lock_interruptible(dev);
3521 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3522 if (&obj->base == NULL) {
3527 ret = i915_gem_object_set_cache_level(obj, level);
3529 drm_gem_object_unreference(&obj->base);
3531 mutex_unlock(&dev->struct_mutex);
3535 static bool is_pin_display(struct drm_i915_gem_object *obj)
3537 /* There are 3 sources that pin objects:
3538 * 1. The display engine (scanouts, sprites, cursors);
3539 * 2. Reservations for execbuffer;
3542 * We can ignore reservations as we hold the struct_mutex and
3543 * are only called outside of the reservation path. The user
3544 * can only increment pin_count once, and so if after
3545 * subtracting the potential reference by the user, any pin_count
3546 * remains, it must be due to another use by the display engine.
3548 return obj->pin_count - !!obj->user_pin_count;
3552 * Prepare buffer for display plane (scanout, cursors, etc).
3553 * Can be called from an uninterruptible phase (modesetting) and allows
3554 * any flushes to be pipelined (for pageflips).
3557 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3559 struct intel_ring_buffer *pipelined)
3561 u32 old_read_domains, old_write_domain;
3564 if (pipelined != obj->ring) {
3565 ret = i915_gem_object_sync(obj, pipelined);
3570 /* Mark the pin_display early so that we account for the
3571 * display coherency whilst setting up the cache domains.
3573 obj->pin_display = true;
3575 /* The display engine is not coherent with the LLC cache on gen6. As
3576 * a result, we make sure that the pinning that is about to occur is
3577 * done with uncached PTEs. This is lowest common denominator for all
3580 * However for gen6+, we could do better by using the GFDT bit instead
3581 * of uncaching, which would allow us to flush all the LLC-cached data
3582 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3584 ret = i915_gem_object_set_cache_level(obj,
3585 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3587 goto err_unpin_display;
3589 /* As the user may map the buffer once pinned in the display plane
3590 * (e.g. libkms for the bootup splash), we have to ensure that we
3591 * always use map_and_fenceable for all scanout buffers.
3593 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3595 goto err_unpin_display;
3597 i915_gem_object_flush_cpu_write_domain(obj, true);
3599 old_write_domain = obj->base.write_domain;
3600 old_read_domains = obj->base.read_domains;
3602 /* It should now be out of any other write domains, and we can update
3603 * the domain values for our changes.
3605 obj->base.write_domain = 0;
3606 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3608 trace_i915_gem_object_change_domain(obj,
3615 obj->pin_display = is_pin_display(obj);
3620 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3622 i915_gem_object_unpin(obj);
3623 obj->pin_display = is_pin_display(obj);
3627 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3631 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3634 ret = i915_gem_object_wait_rendering(obj, false);
3638 /* Ensure that we invalidate the GPU's caches and TLBs. */
3639 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3644 * Moves a single object to the CPU read, and possibly write domain.
3646 * This function returns when the move is complete, including waiting on
3650 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3652 uint32_t old_write_domain, old_read_domains;
3655 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3658 ret = i915_gem_object_wait_rendering(obj, !write);
3662 i915_gem_object_flush_gtt_write_domain(obj);
3664 old_write_domain = obj->base.write_domain;
3665 old_read_domains = obj->base.read_domains;
3667 /* Flush the CPU cache if it's still invalid. */
3668 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3669 i915_gem_clflush_object(obj, false);
3671 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3674 /* It should now be out of any other write domains, and we can update
3675 * the domain values for our changes.
3677 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3679 /* If we're writing through the CPU, then the GPU read domains will
3680 * need to be invalidated at next use.
3683 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3684 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3687 trace_i915_gem_object_change_domain(obj,
3694 /* Throttle our rendering by waiting until the ring has completed our requests
3695 * emitted over 20 msec ago.
3697 * Note that if we were to use the current jiffies each time around the loop,
3698 * we wouldn't escape the function with any frames outstanding if the time to
3699 * render a frame was over 20ms.
3701 * This should get us reasonable parallelism between CPU and GPU but also
3702 * relatively low latency when blocking on a particular request to finish.
3705 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct drm_i915_file_private *file_priv = file->driver_priv;
3709 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3710 struct drm_i915_gem_request *request;
3711 struct intel_ring_buffer *ring = NULL;
3712 unsigned reset_counter;
3716 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3720 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3724 spin_lock(&file_priv->mm.lock);
3725 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3726 if (time_after_eq(request->emitted_jiffies, recent_enough))
3729 ring = request->ring;
3730 seqno = request->seqno;
3732 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3733 spin_unlock(&file_priv->mm.lock);
3738 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3740 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3746 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3747 struct i915_address_space *vm,
3749 bool map_and_fenceable,
3752 struct i915_vma *vma;
3755 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3758 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3760 vma = i915_gem_obj_to_vma(obj, vm);
3764 vma->node.start & (alignment - 1)) ||
3765 (map_and_fenceable && !obj->map_and_fenceable)) {
3766 WARN(obj->pin_count,
3767 "bo is already pinned with incorrect alignment:"
3768 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3769 " obj->map_and_fenceable=%d\n",
3770 i915_gem_obj_offset(obj, vm), alignment,
3772 obj->map_and_fenceable);
3773 ret = i915_vma_unbind(vma);
3779 if (!i915_gem_obj_bound(obj, vm)) {
3780 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3782 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3788 if (!dev_priv->mm.aliasing_ppgtt)
3789 i915_gem_gtt_bind_object(obj, obj->cache_level);
3792 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3793 i915_gem_gtt_bind_object(obj, obj->cache_level);
3796 obj->pin_mappable |= map_and_fenceable;
3802 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3804 BUG_ON(obj->pin_count == 0);
3805 BUG_ON(!i915_gem_obj_bound_any(obj));
3807 if (--obj->pin_count == 0)
3808 obj->pin_mappable = false;
3812 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3813 struct drm_file *file)
3815 struct drm_i915_gem_pin *args = data;
3816 struct drm_i915_gem_object *obj;
3819 ret = i915_mutex_lock_interruptible(dev);
3823 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3824 if (&obj->base == NULL) {
3829 if (obj->madv != I915_MADV_WILLNEED) {
3830 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3835 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3836 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3842 if (obj->user_pin_count == 0) {
3843 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3848 obj->user_pin_count++;
3849 obj->pin_filp = file;
3851 args->offset = i915_gem_obj_ggtt_offset(obj);
3853 drm_gem_object_unreference(&obj->base);
3855 mutex_unlock(&dev->struct_mutex);
3860 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3861 struct drm_file *file)
3863 struct drm_i915_gem_pin *args = data;
3864 struct drm_i915_gem_object *obj;
3867 ret = i915_mutex_lock_interruptible(dev);
3871 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3872 if (&obj->base == NULL) {
3877 if (obj->pin_filp != file) {
3878 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3883 obj->user_pin_count--;
3884 if (obj->user_pin_count == 0) {
3885 obj->pin_filp = NULL;
3886 i915_gem_object_unpin(obj);
3890 drm_gem_object_unreference(&obj->base);
3892 mutex_unlock(&dev->struct_mutex);
3897 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3898 struct drm_file *file)
3900 struct drm_i915_gem_busy *args = data;
3901 struct drm_i915_gem_object *obj;
3904 ret = i915_mutex_lock_interruptible(dev);
3908 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3909 if (&obj->base == NULL) {
3914 /* Count all active objects as busy, even if they are currently not used
3915 * by the gpu. Users of this interface expect objects to eventually
3916 * become non-busy without any further actions, therefore emit any
3917 * necessary flushes here.
3919 ret = i915_gem_object_flush_active(obj);
3921 args->busy = obj->active;
3923 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3924 args->busy |= intel_ring_flag(obj->ring) << 16;
3927 drm_gem_object_unreference(&obj->base);
3929 mutex_unlock(&dev->struct_mutex);
3934 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3935 struct drm_file *file_priv)
3937 return i915_gem_ring_throttle(dev, file_priv);
3941 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3942 struct drm_file *file_priv)
3944 struct drm_i915_gem_madvise *args = data;
3945 struct drm_i915_gem_object *obj;
3948 switch (args->madv) {
3949 case I915_MADV_DONTNEED:
3950 case I915_MADV_WILLNEED:
3956 ret = i915_mutex_lock_interruptible(dev);
3960 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3961 if (&obj->base == NULL) {
3966 if (obj->pin_count) {
3971 if (obj->madv != __I915_MADV_PURGED)
3972 obj->madv = args->madv;
3974 /* if the object is no longer attached, discard its backing storage */
3975 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3976 i915_gem_object_truncate(obj);
3978 args->retained = obj->madv != __I915_MADV_PURGED;
3981 drm_gem_object_unreference(&obj->base);
3983 mutex_unlock(&dev->struct_mutex);
3987 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3988 const struct drm_i915_gem_object_ops *ops)
3990 INIT_LIST_HEAD(&obj->global_list);
3991 INIT_LIST_HEAD(&obj->ring_list);
3992 INIT_LIST_HEAD(&obj->exec_list);
3993 INIT_LIST_HEAD(&obj->vma_list);
3997 obj->fence_reg = I915_FENCE_REG_NONE;
3998 obj->madv = I915_MADV_WILLNEED;
3999 /* Avoid an unnecessary call to unbind on the first bind. */
4000 obj->map_and_fenceable = true;
4002 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4005 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4006 .get_pages = i915_gem_object_get_pages_gtt,
4007 .put_pages = i915_gem_object_put_pages_gtt,
4010 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4013 struct drm_i915_gem_object *obj;
4014 struct address_space *mapping;
4017 obj = i915_gem_object_alloc(dev);
4021 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4022 i915_gem_object_free(obj);
4026 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4027 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4028 /* 965gm cannot relocate objects above 4GiB. */
4029 mask &= ~__GFP_HIGHMEM;
4030 mask |= __GFP_DMA32;
4033 mapping = file_inode(obj->base.filp)->i_mapping;
4034 mapping_set_gfp_mask(mapping, mask);
4036 i915_gem_object_init(obj, &i915_gem_object_ops);
4038 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4039 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4042 /* On some devices, we can have the GPU use the LLC (the CPU
4043 * cache) for about a 10% performance improvement
4044 * compared to uncached. Graphics requests other than
4045 * display scanout are coherent with the CPU in
4046 * accessing this cache. This means in this mode we
4047 * don't need to clflush on the CPU side, and on the
4048 * GPU side we only need to flush internal caches to
4049 * get data visible to the CPU.
4051 * However, we maintain the display planes as UC, and so
4052 * need to rebind when first used as such.
4054 obj->cache_level = I915_CACHE_LLC;
4056 obj->cache_level = I915_CACHE_NONE;
4058 trace_i915_gem_object_create(obj);
4063 int i915_gem_init_object(struct drm_gem_object *obj)
4070 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4072 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4073 struct drm_device *dev = obj->base.dev;
4074 drm_i915_private_t *dev_priv = dev->dev_private;
4075 struct i915_vma *vma, *next;
4077 trace_i915_gem_object_destroy(obj);
4080 i915_gem_detach_phys_object(dev, obj);
4083 /* NB: 0 or 1 elements */
4084 WARN_ON(!list_empty(&obj->vma_list) &&
4085 !list_is_singular(&obj->vma_list));
4086 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4087 int ret = i915_vma_unbind(vma);
4088 if (WARN_ON(ret == -ERESTARTSYS)) {
4089 bool was_interruptible;
4091 was_interruptible = dev_priv->mm.interruptible;
4092 dev_priv->mm.interruptible = false;
4094 WARN_ON(i915_vma_unbind(vma));
4096 dev_priv->mm.interruptible = was_interruptible;
4100 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4101 * before progressing. */
4103 i915_gem_object_unpin_pages(obj);
4105 if (WARN_ON(obj->pages_pin_count))
4106 obj->pages_pin_count = 0;
4107 i915_gem_object_put_pages(obj);
4108 i915_gem_object_free_mmap_offset(obj);
4109 i915_gem_object_release_stolen(obj);
4113 if (obj->base.import_attach)
4114 drm_prime_gem_destroy(&obj->base, NULL);
4116 drm_gem_object_release(&obj->base);
4117 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4120 i915_gem_object_free(obj);
4123 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4124 struct i915_address_space *vm)
4126 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4128 return ERR_PTR(-ENOMEM);
4130 INIT_LIST_HEAD(&vma->vma_link);
4131 INIT_LIST_HEAD(&vma->mm_list);
4135 /* Keep GGTT vmas first to make debug easier */
4136 if (i915_is_ggtt(vm))
4137 list_add(&vma->vma_link, &obj->vma_list);
4139 list_add_tail(&vma->vma_link, &obj->vma_list);
4144 void i915_gem_vma_destroy(struct i915_vma *vma)
4146 WARN_ON(vma->node.allocated);
4147 list_del(&vma->vma_link);
4152 i915_gem_idle(struct drm_device *dev)
4154 drm_i915_private_t *dev_priv = dev->dev_private;
4157 if (dev_priv->ums.mm_suspended) {
4158 mutex_unlock(&dev->struct_mutex);
4162 ret = i915_gpu_idle(dev);
4164 mutex_unlock(&dev->struct_mutex);
4167 i915_gem_retire_requests(dev);
4169 /* Under UMS, be paranoid and evict. */
4170 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4171 i915_gem_evict_everything(dev);
4173 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4175 i915_kernel_lost_context(dev);
4176 i915_gem_cleanup_ringbuffer(dev);
4178 /* Cancel the retire work handler, which should be idle now. */
4179 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4184 void i915_gem_l3_remap(struct drm_device *dev)
4186 drm_i915_private_t *dev_priv = dev->dev_private;
4190 if (!HAS_L3_GPU_CACHE(dev))
4193 if (!dev_priv->l3_parity.remap_info)
4196 misccpctl = I915_READ(GEN7_MISCCPCTL);
4197 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4198 POSTING_READ(GEN7_MISCCPCTL);
4200 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4201 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4202 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4203 DRM_DEBUG("0x%x was already programmed to %x\n",
4204 GEN7_L3LOG_BASE + i, remap);
4205 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4206 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4207 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4210 /* Make sure all the writes land before disabling dop clock gating */
4211 POSTING_READ(GEN7_L3LOG_BASE);
4213 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4216 void i915_gem_init_swizzling(struct drm_device *dev)
4218 drm_i915_private_t *dev_priv = dev->dev_private;
4220 if (INTEL_INFO(dev)->gen < 5 ||
4221 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4224 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4225 DISP_TILE_SURFACE_SWIZZLING);
4230 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4232 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4233 else if (IS_GEN7(dev))
4234 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4240 intel_enable_blt(struct drm_device *dev)
4245 /* The blitter was dysfunctional on early prototypes */
4246 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4247 DRM_INFO("BLT not supported on this pre-production hardware;"
4248 " graphics performance will be degraded.\n");
4255 static int i915_gem_init_rings(struct drm_device *dev)
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4260 ret = intel_init_render_ring_buffer(dev);
4265 ret = intel_init_bsd_ring_buffer(dev);
4267 goto cleanup_render_ring;
4270 if (intel_enable_blt(dev)) {
4271 ret = intel_init_blt_ring_buffer(dev);
4273 goto cleanup_bsd_ring;
4276 if (HAS_VEBOX(dev)) {
4277 ret = intel_init_vebox_ring_buffer(dev);
4279 goto cleanup_blt_ring;
4283 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4285 goto cleanup_vebox_ring;
4290 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4292 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4294 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4295 cleanup_render_ring:
4296 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4302 i915_gem_init_hw(struct drm_device *dev)
4304 drm_i915_private_t *dev_priv = dev->dev_private;
4307 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4310 if (dev_priv->ellc_size)
4311 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4313 if (HAS_PCH_NOP(dev)) {
4314 u32 temp = I915_READ(GEN7_MSG_CTL);
4315 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4316 I915_WRITE(GEN7_MSG_CTL, temp);
4319 i915_gem_l3_remap(dev);
4321 i915_gem_init_swizzling(dev);
4323 ret = i915_gem_init_rings(dev);
4328 * XXX: There was some w/a described somewhere suggesting loading
4329 * contexts before PPGTT.
4331 i915_gem_context_init(dev);
4332 if (dev_priv->mm.aliasing_ppgtt) {
4333 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4335 i915_gem_cleanup_aliasing_ppgtt(dev);
4336 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4343 int i915_gem_init(struct drm_device *dev)
4345 struct drm_i915_private *dev_priv = dev->dev_private;
4348 mutex_lock(&dev->struct_mutex);
4350 if (IS_VALLEYVIEW(dev)) {
4351 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4352 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4353 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4354 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4357 i915_gem_init_global_gtt(dev);
4359 ret = i915_gem_init_hw(dev);
4360 mutex_unlock(&dev->struct_mutex);
4362 i915_gem_cleanup_aliasing_ppgtt(dev);
4366 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4367 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4368 dev_priv->dri1.allow_batchbuffer = 1;
4373 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4375 drm_i915_private_t *dev_priv = dev->dev_private;
4376 struct intel_ring_buffer *ring;
4379 for_each_ring(ring, dev_priv, i)
4380 intel_cleanup_ring_buffer(ring);
4384 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4385 struct drm_file *file_priv)
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4390 if (drm_core_check_feature(dev, DRIVER_MODESET))
4393 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4394 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4395 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4398 mutex_lock(&dev->struct_mutex);
4399 dev_priv->ums.mm_suspended = 0;
4401 ret = i915_gem_init_hw(dev);
4403 mutex_unlock(&dev->struct_mutex);
4407 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4408 mutex_unlock(&dev->struct_mutex);
4410 ret = drm_irq_install(dev);
4412 goto cleanup_ringbuffer;
4417 mutex_lock(&dev->struct_mutex);
4418 i915_gem_cleanup_ringbuffer(dev);
4419 dev_priv->ums.mm_suspended = 1;
4420 mutex_unlock(&dev->struct_mutex);
4426 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4427 struct drm_file *file_priv)
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4432 if (drm_core_check_feature(dev, DRIVER_MODESET))
4435 drm_irq_uninstall(dev);
4437 mutex_lock(&dev->struct_mutex);
4438 ret = i915_gem_idle(dev);
4440 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4441 * We need to replace this with a semaphore, or something.
4442 * And not confound ums.mm_suspended!
4445 dev_priv->ums.mm_suspended = 1;
4446 mutex_unlock(&dev->struct_mutex);
4452 i915_gem_lastclose(struct drm_device *dev)
4456 if (drm_core_check_feature(dev, DRIVER_MODESET))
4459 mutex_lock(&dev->struct_mutex);
4460 ret = i915_gem_idle(dev);
4462 DRM_ERROR("failed to idle hardware: %d\n", ret);
4463 mutex_unlock(&dev->struct_mutex);
4467 init_ring_lists(struct intel_ring_buffer *ring)
4469 INIT_LIST_HEAD(&ring->active_list);
4470 INIT_LIST_HEAD(&ring->request_list);
4473 static void i915_init_vm(struct drm_i915_private *dev_priv,
4474 struct i915_address_space *vm)
4476 vm->dev = dev_priv->dev;
4477 INIT_LIST_HEAD(&vm->active_list);
4478 INIT_LIST_HEAD(&vm->inactive_list);
4479 INIT_LIST_HEAD(&vm->global_link);
4480 list_add(&vm->global_link, &dev_priv->vm_list);
4484 i915_gem_load(struct drm_device *dev)
4486 drm_i915_private_t *dev_priv = dev->dev_private;
4490 kmem_cache_create("i915_gem_object",
4491 sizeof(struct drm_i915_gem_object), 0,
4495 INIT_LIST_HEAD(&dev_priv->vm_list);
4496 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4498 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4499 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4500 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4501 for (i = 0; i < I915_NUM_RINGS; i++)
4502 init_ring_lists(&dev_priv->ring[i]);
4503 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4504 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4505 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4506 i915_gem_retire_work_handler);
4507 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4509 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4511 I915_WRITE(MI_ARB_STATE,
4512 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4515 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4517 /* Old X drivers will take 0-2 for front, back, depth buffers */
4518 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4519 dev_priv->fence_reg_start = 3;
4521 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4522 dev_priv->num_fence_regs = 32;
4523 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4524 dev_priv->num_fence_regs = 16;
4526 dev_priv->num_fence_regs = 8;
4528 /* Initialize fence registers to zero */
4529 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4530 i915_gem_restore_fences(dev);
4532 i915_gem_detect_bit_6_swizzle(dev);
4533 init_waitqueue_head(&dev_priv->pending_flip_queue);
4535 dev_priv->mm.interruptible = true;
4537 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4538 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4539 register_shrinker(&dev_priv->mm.inactive_shrinker);
4543 * Create a physically contiguous memory object for this object
4544 * e.g. for cursor + overlay regs
4546 static int i915_gem_init_phys_object(struct drm_device *dev,
4547 int id, int size, int align)
4549 drm_i915_private_t *dev_priv = dev->dev_private;
4550 struct drm_i915_gem_phys_object *phys_obj;
4553 if (dev_priv->mm.phys_objs[id - 1] || !size)
4556 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4562 phys_obj->handle = drm_pci_alloc(dev, size, align);
4563 if (!phys_obj->handle) {
4568 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4571 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4579 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4581 drm_i915_private_t *dev_priv = dev->dev_private;
4582 struct drm_i915_gem_phys_object *phys_obj;
4584 if (!dev_priv->mm.phys_objs[id - 1])
4587 phys_obj = dev_priv->mm.phys_objs[id - 1];
4588 if (phys_obj->cur_obj) {
4589 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4593 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4595 drm_pci_free(dev, phys_obj->handle);
4597 dev_priv->mm.phys_objs[id - 1] = NULL;
4600 void i915_gem_free_all_phys_object(struct drm_device *dev)
4604 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4605 i915_gem_free_phys_object(dev, i);
4608 void i915_gem_detach_phys_object(struct drm_device *dev,
4609 struct drm_i915_gem_object *obj)
4611 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4618 vaddr = obj->phys_obj->handle->vaddr;
4620 page_count = obj->base.size / PAGE_SIZE;
4621 for (i = 0; i < page_count; i++) {
4622 struct page *page = shmem_read_mapping_page(mapping, i);
4623 if (!IS_ERR(page)) {
4624 char *dst = kmap_atomic(page);
4625 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4628 drm_clflush_pages(&page, 1);
4630 set_page_dirty(page);
4631 mark_page_accessed(page);
4632 page_cache_release(page);
4635 i915_gem_chipset_flush(dev);
4637 obj->phys_obj->cur_obj = NULL;
4638 obj->phys_obj = NULL;
4642 i915_gem_attach_phys_object(struct drm_device *dev,
4643 struct drm_i915_gem_object *obj,
4647 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4648 drm_i915_private_t *dev_priv = dev->dev_private;
4653 if (id > I915_MAX_PHYS_OBJECT)
4656 if (obj->phys_obj) {
4657 if (obj->phys_obj->id == id)
4659 i915_gem_detach_phys_object(dev, obj);
4662 /* create a new object */
4663 if (!dev_priv->mm.phys_objs[id - 1]) {
4664 ret = i915_gem_init_phys_object(dev, id,
4665 obj->base.size, align);
4667 DRM_ERROR("failed to init phys object %d size: %zu\n",
4668 id, obj->base.size);
4673 /* bind to the object */
4674 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4675 obj->phys_obj->cur_obj = obj;
4677 page_count = obj->base.size / PAGE_SIZE;
4679 for (i = 0; i < page_count; i++) {
4683 page = shmem_read_mapping_page(mapping, i);
4685 return PTR_ERR(page);
4687 src = kmap_atomic(page);
4688 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4689 memcpy(dst, src, PAGE_SIZE);
4692 mark_page_accessed(page);
4693 page_cache_release(page);
4700 i915_gem_phys_pwrite(struct drm_device *dev,
4701 struct drm_i915_gem_object *obj,
4702 struct drm_i915_gem_pwrite *args,
4703 struct drm_file *file_priv)
4705 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4706 char __user *user_data = to_user_ptr(args->data_ptr);
4708 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4709 unsigned long unwritten;
4711 /* The physical object once assigned is fixed for the lifetime
4712 * of the obj, so we can safely drop the lock and continue
4715 mutex_unlock(&dev->struct_mutex);
4716 unwritten = copy_from_user(vaddr, user_data, args->size);
4717 mutex_lock(&dev->struct_mutex);
4722 i915_gem_chipset_flush(dev);
4726 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4728 struct drm_i915_file_private *file_priv = file->driver_priv;
4730 /* Clean up our request list when the client is going away, so that
4731 * later retire_requests won't dereference our soon-to-be-gone
4734 spin_lock(&file_priv->mm.lock);
4735 while (!list_empty(&file_priv->mm.request_list)) {
4736 struct drm_i915_gem_request *request;
4738 request = list_first_entry(&file_priv->mm.request_list,
4739 struct drm_i915_gem_request,
4741 list_del(&request->client_list);
4742 request->file_priv = NULL;
4744 spin_unlock(&file_priv->mm.lock);
4747 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4749 if (!mutex_is_locked(mutex))
4752 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4753 return mutex->owner == task;
4755 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4761 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4763 struct drm_i915_private *dev_priv =
4764 container_of(shrinker,
4765 struct drm_i915_private,
4766 mm.inactive_shrinker);
4767 struct drm_device *dev = dev_priv->dev;
4768 struct drm_i915_gem_object *obj;
4769 int nr_to_scan = sc->nr_to_scan;
4773 if (!mutex_trylock(&dev->struct_mutex)) {
4774 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4777 if (dev_priv->mm.shrinker_no_lock_stealing)
4784 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4786 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4789 i915_gem_shrink_all(dev_priv);
4793 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4794 if (obj->pages_pin_count == 0)
4795 cnt += obj->base.size >> PAGE_SHIFT;
4797 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4801 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4802 cnt += obj->base.size >> PAGE_SHIFT;
4806 mutex_unlock(&dev->struct_mutex);
4810 /* All the new VM stuff */
4811 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4812 struct i915_address_space *vm)
4814 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4815 struct i915_vma *vma;
4817 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4818 vm = &dev_priv->gtt.base;
4820 BUG_ON(list_empty(&o->vma_list));
4821 list_for_each_entry(vma, &o->vma_list, vma_link) {
4823 return vma->node.start;
4829 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4830 struct i915_address_space *vm)
4832 struct i915_vma *vma;
4834 list_for_each_entry(vma, &o->vma_list, vma_link)
4835 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4841 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4843 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4844 struct i915_address_space *vm;
4846 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
4847 if (i915_gem_obj_bound(o, vm))
4853 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4854 struct i915_address_space *vm)
4856 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4857 struct i915_vma *vma;
4859 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4860 vm = &dev_priv->gtt.base;
4862 BUG_ON(list_empty(&o->vma_list));
4864 list_for_each_entry(vma, &o->vma_list, vma_link)
4866 return vma->node.size;
4871 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4872 struct i915_address_space *vm)
4874 struct i915_vma *vma;
4875 list_for_each_entry(vma, &obj->vma_list, vma_link)