2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
53 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
54 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
64 drm_i915_private_t *dev_priv = dev->dev_private;
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
72 drm_mm_init(&dev_priv->mm.gtt_space, start,
75 dev->gtt_total = (uint32_t) (end - start);
81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
84 struct drm_i915_gem_init *args = data;
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
89 mutex_unlock(&dev->struct_mutex);
95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
98 struct drm_i915_gem_get_aperture *args = data;
100 if (!(dev->driver->driver_features & DRIVER_GEM))
103 args->aper_size = dev->gtt_total;
104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
123 args->size = roundup(args->size, PAGE_SIZE);
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
138 args->handle = handle;
144 fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
156 kunmap_atomic(vaddr, KM_USER0);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
174 slow_shmem_copy(struct page *dst_page,
176 struct page *src_page,
180 char *dst_vaddr, *src_vaddr;
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
201 slow_shmem_bit17_copy(struct page *gpu_page,
203 struct page *cpu_page,
208 char *gpu_vaddr, *cpu_vaddr;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
278 mutex_lock(&dev->struct_mutex);
280 ret = i915_gem_object_get_pages(obj);
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
289 obj_priv = obj->driver_private;
290 offset = args->offset;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
317 i915_gem_object_put_pages(obj);
319 mutex_unlock(&dev->struct_mutex);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
341 ret = i915_gem_object_get_pages(obj);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
350 ret = i915_gem_evict_something(dev, obj->size);
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
384 uint64_t data_ptr = args->data_ptr;
385 int do_bit17_swizzling;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
398 if (user_pages == NULL)
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
403 num_pages, 1, 0, user_pages, NULL);
404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
407 goto fail_put_user_pages;
410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
412 mutex_lock(&dev->struct_mutex);
414 ret = i915_gem_object_get_pages_or_evict(obj);
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
423 obj_priv = obj->driver_private;
424 offset = args->offset;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
449 user_pages[data_page_index],
454 ret = slow_shmem_copy(user_pages[data_page_index],
456 obj_priv->pages[shmem_page_index],
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
469 i915_gem_object_put_pages(obj);
471 mutex_unlock(&dev->struct_mutex);
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
477 drm_free_large(user_pages);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
499 obj_priv = obj->driver_private;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
520 drm_gem_object_unreference(obj);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
536 unsigned long unwritten;
538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
541 io_mapping_unmap_atomic(vaddr_atomic);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
557 char *src_vaddr, *dst_vaddr;
558 unsigned long unwritten;
560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
573 fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
579 unsigned long unwritten;
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
585 kunmap_atomic(vaddr, KM_USER0);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
602 drm_i915_private_t *dev_priv = dev->dev_private;
604 loff_t offset, page_base;
605 char __user *user_data;
606 int page_offset, page_length;
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
611 if (!access_ok(VERIFY_READ, user_data, remain))
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
618 mutex_unlock(&dev->struct_mutex);
621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
685 uint64_t data_ptr = args->data_ptr;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
698 if (user_pages == NULL)
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
707 goto out_unpin_pages;
710 mutex_lock(&dev->struct_mutex);
711 ret = i915_gem_object_pin(obj, 0);
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
717 goto out_unpin_object;
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object;
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
761 i915_gem_object_unpin(obj);
763 mutex_unlock(&dev->struct_mutex);
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
767 drm_free_large(user_pages);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
791 mutex_lock(&dev->struct_mutex);
793 ret = i915_gem_object_get_pages(obj);
797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
801 obj_priv = obj->driver_private;
802 offset = args->offset;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
830 i915_gem_object_put_pages(obj);
832 mutex_unlock(&dev->struct_mutex);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
859 uint64_t data_ptr = args->data_ptr;
860 int do_bit17_swizzling;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
873 if (user_pages == NULL)
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
882 goto fail_put_user_pages;
885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
887 mutex_lock(&dev->struct_mutex);
889 ret = i915_gem_object_get_pages_or_evict(obj);
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
897 obj_priv = obj->driver_private;
898 offset = args->offset;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
924 user_pages[data_page_index],
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
931 user_pages[data_page_index],
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
944 i915_gem_object_put_pages(obj);
946 mutex_unlock(&dev->struct_mutex);
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
950 drm_free_large(user_pages);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
972 obj_priv = obj->driver_private;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1011 DRM_INFO("pwrite failed %d\n", ret);
1014 drm_gem_object_unreference(obj);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
1030 struct drm_i915_gem_object *obj_priv;
1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain & I915_GEM_GPU_DOMAINS)
1042 if (read_domains & I915_GEM_GPU_DOMAINS)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain != 0 && read_domains != write_domain)
1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1054 obj_priv = obj->driver_private;
1056 mutex_lock(&dev->struct_mutex);
1058 intel_mark_busy(dev, obj);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj, obj->size, read_domains, write_domain);
1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1108 mutex_unlock(&dev->struct_mutex);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__, args->handle, obj, obj->size);
1116 obj_priv = obj->driver_private;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1150 offset = args->offset;
1152 down_write(¤t->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1156 up_write(¤t->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1163 args->addr_ptr = (uint64_t) addr;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1216 /* Need a new fence register? */
1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1218 ret = i915_gem_object_get_fence_reg(obj);
1220 mutex_unlock(&dev->struct_mutex);
1221 return VM_FAULT_SIGBUS;
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1231 mutex_unlock(&dev->struct_mutex);
1236 return VM_FAULT_OOM;
1239 return VM_FAULT_SIGBUS;
1241 return VM_FAULT_NOPAGE;
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1254 * This routine allocates and attaches a fake offset for @obj.
1257 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
1263 struct drm_local_map *map;
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1306 drm_mm_put_block(list->file_offset_node);
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1328 i915_gem_release_mmap(struct drm_gem_object *obj)
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1339 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1359 obj_priv->mmap_offset = 0;
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1370 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1392 for (i = start; i < obj->size; i <<= 1)
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1414 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1430 mutex_lock(&dev->struct_mutex);
1432 obj_priv = obj->driver_private;
1434 if (obj_priv->madv != I915_MADV_WILLNEED) {
1435 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1436 drm_gem_object_unreference(obj);
1437 mutex_unlock(&dev->struct_mutex);
1442 if (!obj_priv->mmap_offset) {
1443 ret = i915_gem_create_mmap_offset(obj);
1445 drm_gem_object_unreference(obj);
1446 mutex_unlock(&dev->struct_mutex);
1451 args->offset = obj_priv->mmap_offset;
1454 * Pull it into the GTT so that we have a page list (makes the
1455 * initial fault faster and any subsequent flushing possible).
1457 if (!obj_priv->agp_mem) {
1458 ret = i915_gem_object_bind_to_gtt(obj, 0);
1460 drm_gem_object_unreference(obj);
1461 mutex_unlock(&dev->struct_mutex);
1464 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1467 drm_gem_object_unreference(obj);
1468 mutex_unlock(&dev->struct_mutex);
1474 i915_gem_object_put_pages(struct drm_gem_object *obj)
1476 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1477 int page_count = obj->size / PAGE_SIZE;
1480 BUG_ON(obj_priv->pages_refcount == 0);
1481 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1483 if (--obj_priv->pages_refcount != 0)
1486 if (obj_priv->tiling_mode != I915_TILING_NONE)
1487 i915_gem_object_save_bit_17_swizzle(obj);
1489 if (obj_priv->madv == I915_MADV_DONTNEED)
1490 obj_priv->dirty = 0;
1492 for (i = 0; i < page_count; i++) {
1493 if (obj_priv->pages[i] == NULL)
1496 if (obj_priv->dirty)
1497 set_page_dirty(obj_priv->pages[i]);
1499 if (obj_priv->madv == I915_MADV_WILLNEED)
1500 mark_page_accessed(obj_priv->pages[i]);
1502 page_cache_release(obj_priv->pages[i]);
1504 obj_priv->dirty = 0;
1506 drm_free_large(obj_priv->pages);
1507 obj_priv->pages = NULL;
1511 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1517 /* Add a reference if we're newly entering the active list. */
1518 if (!obj_priv->active) {
1519 drm_gem_object_reference(obj);
1520 obj_priv->active = 1;
1522 /* Move from whatever list we were on to the tail of execution. */
1523 spin_lock(&dev_priv->mm.active_list_lock);
1524 list_move_tail(&obj_priv->list,
1525 &dev_priv->mm.active_list);
1526 spin_unlock(&dev_priv->mm.active_list_lock);
1527 obj_priv->last_rendering_seqno = seqno;
1531 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1533 struct drm_device *dev = obj->dev;
1534 drm_i915_private_t *dev_priv = dev->dev_private;
1535 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1537 BUG_ON(!obj_priv->active);
1538 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1539 obj_priv->last_rendering_seqno = 0;
1542 /* Immediately discard the backing storage */
1544 i915_gem_object_truncate(struct drm_gem_object *obj)
1546 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1547 struct inode *inode;
1549 inode = obj->filp->f_path.dentry->d_inode;
1550 if (inode->i_op->truncate)
1551 inode->i_op->truncate (inode);
1553 obj_priv->madv = __I915_MADV_PURGED;
1557 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1559 return obj_priv->madv == I915_MADV_DONTNEED;
1563 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1565 struct drm_device *dev = obj->dev;
1566 drm_i915_private_t *dev_priv = dev->dev_private;
1567 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1569 i915_verify_inactive(dev, __FILE__, __LINE__);
1570 if (obj_priv->pin_count != 0)
1571 list_del_init(&obj_priv->list);
1573 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1575 obj_priv->last_rendering_seqno = 0;
1576 if (obj_priv->active) {
1577 obj_priv->active = 0;
1578 drm_gem_object_unreference(obj);
1580 i915_verify_inactive(dev, __FILE__, __LINE__);
1584 * Creates a new sequence number, emitting a write of it to the status page
1585 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1587 * Must be called with struct_lock held.
1589 * Returned sequence numbers are nonzero on success.
1592 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1593 uint32_t flush_domains)
1595 drm_i915_private_t *dev_priv = dev->dev_private;
1596 struct drm_i915_file_private *i915_file_priv = NULL;
1597 struct drm_i915_gem_request *request;
1602 if (file_priv != NULL)
1603 i915_file_priv = file_priv->driver_priv;
1605 request = kzalloc(sizeof(*request), GFP_KERNEL);
1606 if (request == NULL)
1609 /* Grab the seqno we're going to make this request be, and bump the
1610 * next (skipping 0 so it can be the reserved no-seqno value).
1612 seqno = dev_priv->mm.next_gem_seqno;
1613 dev_priv->mm.next_gem_seqno++;
1614 if (dev_priv->mm.next_gem_seqno == 0)
1615 dev_priv->mm.next_gem_seqno++;
1618 OUT_RING(MI_STORE_DWORD_INDEX);
1619 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1622 OUT_RING(MI_USER_INTERRUPT);
1625 DRM_DEBUG("%d\n", seqno);
1627 request->seqno = seqno;
1628 request->emitted_jiffies = jiffies;
1629 was_empty = list_empty(&dev_priv->mm.request_list);
1630 list_add_tail(&request->list, &dev_priv->mm.request_list);
1631 if (i915_file_priv) {
1632 list_add_tail(&request->client_list,
1633 &i915_file_priv->mm.request_list);
1635 INIT_LIST_HEAD(&request->client_list);
1638 /* Associate any objects on the flushing list matching the write
1639 * domain we're flushing with our flush.
1641 if (flush_domains != 0) {
1642 struct drm_i915_gem_object *obj_priv, *next;
1644 list_for_each_entry_safe(obj_priv, next,
1645 &dev_priv->mm.flushing_list, list) {
1646 struct drm_gem_object *obj = obj_priv->obj;
1648 if ((obj->write_domain & flush_domains) ==
1649 obj->write_domain) {
1650 uint32_t old_write_domain = obj->write_domain;
1652 obj->write_domain = 0;
1653 i915_gem_object_move_to_active(obj, seqno);
1655 trace_i915_gem_object_change_domain(obj,
1663 if (!dev_priv->mm.suspended) {
1664 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1666 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1672 * Command execution barrier
1674 * Ensures that all commands in the ring are finished
1675 * before signalling the CPU
1678 i915_retire_commands(struct drm_device *dev)
1680 drm_i915_private_t *dev_priv = dev->dev_private;
1681 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1682 uint32_t flush_domains = 0;
1685 /* The sampler always gets flushed on i965 (sigh) */
1687 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1690 OUT_RING(0); /* noop */
1692 return flush_domains;
1696 * Moves buffers associated only with the given active seqno from the active
1697 * to inactive list, potentially freeing them.
1700 i915_gem_retire_request(struct drm_device *dev,
1701 struct drm_i915_gem_request *request)
1703 drm_i915_private_t *dev_priv = dev->dev_private;
1705 trace_i915_gem_request_retire(dev, request->seqno);
1707 /* Move any buffers on the active list that are no longer referenced
1708 * by the ringbuffer to the flushing/inactive lists as appropriate.
1710 spin_lock(&dev_priv->mm.active_list_lock);
1711 while (!list_empty(&dev_priv->mm.active_list)) {
1712 struct drm_gem_object *obj;
1713 struct drm_i915_gem_object *obj_priv;
1715 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1716 struct drm_i915_gem_object,
1718 obj = obj_priv->obj;
1720 /* If the seqno being retired doesn't match the oldest in the
1721 * list, then the oldest in the list must still be newer than
1724 if (obj_priv->last_rendering_seqno != request->seqno)
1728 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1729 __func__, request->seqno, obj);
1732 if (obj->write_domain != 0)
1733 i915_gem_object_move_to_flushing(obj);
1735 /* Take a reference on the object so it won't be
1736 * freed while the spinlock is held. The list
1737 * protection for this spinlock is safe when breaking
1738 * the lock like this since the next thing we do
1739 * is just get the head of the list again.
1741 drm_gem_object_reference(obj);
1742 i915_gem_object_move_to_inactive(obj);
1743 spin_unlock(&dev_priv->mm.active_list_lock);
1744 drm_gem_object_unreference(obj);
1745 spin_lock(&dev_priv->mm.active_list_lock);
1749 spin_unlock(&dev_priv->mm.active_list_lock);
1753 * Returns true if seq1 is later than seq2.
1756 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1758 return (int32_t)(seq1 - seq2) >= 0;
1762 i915_get_gem_seqno(struct drm_device *dev)
1764 drm_i915_private_t *dev_priv = dev->dev_private;
1766 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1770 * This function clears the request list as sequence numbers are passed.
1773 i915_gem_retire_requests(struct drm_device *dev)
1775 drm_i915_private_t *dev_priv = dev->dev_private;
1778 if (!dev_priv->hw_status_page)
1781 seqno = i915_get_gem_seqno(dev);
1783 while (!list_empty(&dev_priv->mm.request_list)) {
1784 struct drm_i915_gem_request *request;
1785 uint32_t retiring_seqno;
1787 request = list_first_entry(&dev_priv->mm.request_list,
1788 struct drm_i915_gem_request,
1790 retiring_seqno = request->seqno;
1792 if (i915_seqno_passed(seqno, retiring_seqno) ||
1793 atomic_read(&dev_priv->mm.wedged)) {
1794 i915_gem_retire_request(dev, request);
1796 list_del(&request->list);
1797 list_del(&request->client_list);
1805 i915_gem_retire_work_handler(struct work_struct *work)
1807 drm_i915_private_t *dev_priv;
1808 struct drm_device *dev;
1810 dev_priv = container_of(work, drm_i915_private_t,
1811 mm.retire_work.work);
1812 dev = dev_priv->dev;
1814 mutex_lock(&dev->struct_mutex);
1815 i915_gem_retire_requests(dev);
1816 if (!dev_priv->mm.suspended &&
1817 !list_empty(&dev_priv->mm.request_list))
1818 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1819 mutex_unlock(&dev->struct_mutex);
1823 * Waits for a sequence number to be signaled, and cleans up the
1824 * request and object lists appropriately for that event.
1827 i915_wait_request(struct drm_device *dev, uint32_t seqno)
1829 drm_i915_private_t *dev_priv = dev->dev_private;
1835 if (atomic_read(&dev_priv->mm.wedged))
1838 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1840 ier = I915_READ(DEIER) | I915_READ(GTIER);
1842 ier = I915_READ(IER);
1844 DRM_ERROR("something (likely vbetool) disabled "
1845 "interrupts, re-enabling\n");
1846 i915_driver_irq_preinstall(dev);
1847 i915_driver_irq_postinstall(dev);
1850 trace_i915_gem_request_wait_begin(dev, seqno);
1852 dev_priv->mm.waiting_gem_seqno = seqno;
1853 i915_user_irq_get(dev);
1854 ret = wait_event_interruptible(dev_priv->irq_queue,
1855 i915_seqno_passed(i915_get_gem_seqno(dev),
1857 atomic_read(&dev_priv->mm.wedged));
1858 i915_user_irq_put(dev);
1859 dev_priv->mm.waiting_gem_seqno = 0;
1861 trace_i915_gem_request_wait_end(dev, seqno);
1863 if (atomic_read(&dev_priv->mm.wedged))
1866 if (ret && ret != -ERESTARTSYS)
1867 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1868 __func__, ret, seqno, i915_get_gem_seqno(dev));
1870 /* Directly dispatch request retiring. While we have the work queue
1871 * to handle this, the waiter on a request often wants an associated
1872 * buffer to have made it to the inactive list, and we would need
1873 * a separate wait queue to handle that.
1876 i915_gem_retire_requests(dev);
1882 i915_gem_flush(struct drm_device *dev,
1883 uint32_t invalidate_domains,
1884 uint32_t flush_domains)
1886 drm_i915_private_t *dev_priv = dev->dev_private;
1891 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1892 invalidate_domains, flush_domains);
1894 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1895 invalidate_domains, flush_domains);
1897 if (flush_domains & I915_GEM_DOMAIN_CPU)
1898 drm_agp_chipset_flush(dev);
1900 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1902 * read/write caches:
1904 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1905 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1906 * also flushed at 2d versus 3d pipeline switches.
1910 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1911 * MI_READ_FLUSH is set, and is always flushed on 965.
1913 * I915_GEM_DOMAIN_COMMAND may not exist?
1915 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1916 * invalidated when MI_EXE_FLUSH is set.
1918 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1919 * invalidated with every MI_FLUSH.
1923 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1924 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1925 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1926 * are flushed at any MI_FLUSH.
1929 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1930 if ((invalidate_domains|flush_domains) &
1931 I915_GEM_DOMAIN_RENDER)
1932 cmd &= ~MI_NO_WRITE_FLUSH;
1933 if (!IS_I965G(dev)) {
1935 * On the 965, the sampler cache always gets flushed
1936 * and this bit is reserved.
1938 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1939 cmd |= MI_READ_FLUSH;
1941 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1942 cmd |= MI_EXE_FLUSH;
1945 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1949 OUT_RING(0); /* noop */
1955 * Ensures that all rendering to the object has completed and the object is
1956 * safe to unbind from the GTT or access from the CPU.
1959 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1961 struct drm_device *dev = obj->dev;
1962 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1965 /* This function only exists to support waiting for existing rendering,
1966 * not for emitting required flushes.
1968 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1970 /* If there is rendering queued on the buffer being evicted, wait for
1973 if (obj_priv->active) {
1975 DRM_INFO("%s: object %p wait for seqno %08x\n",
1976 __func__, obj, obj_priv->last_rendering_seqno);
1978 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1987 * Unbinds an object from the GTT aperture.
1990 i915_gem_object_unbind(struct drm_gem_object *obj)
1992 struct drm_device *dev = obj->dev;
1993 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1997 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1998 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
2000 if (obj_priv->gtt_space == NULL)
2003 if (obj_priv->pin_count != 0) {
2004 DRM_ERROR("Attempting to unbind pinned buffer\n");
2008 /* blow away mappings if mapped through GTT */
2009 i915_gem_release_mmap(obj);
2011 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2012 i915_gem_clear_fence_reg(obj);
2014 /* Move the object to the CPU domain to ensure that
2015 * any possible CPU writes while it's not in the GTT
2016 * are flushed when we go to remap it. This will
2017 * also ensure that all pending GPU writes are finished
2020 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2022 if (ret != -ERESTARTSYS)
2023 DRM_ERROR("set_domain failed: %d\n", ret);
2027 BUG_ON(obj_priv->active);
2029 if (obj_priv->agp_mem != NULL) {
2030 drm_unbind_agp(obj_priv->agp_mem);
2031 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2032 obj_priv->agp_mem = NULL;
2035 i915_gem_object_put_pages(obj);
2036 BUG_ON(obj_priv->pages_refcount);
2038 if (obj_priv->gtt_space) {
2039 atomic_dec(&dev->gtt_count);
2040 atomic_sub(obj->size, &dev->gtt_memory);
2042 drm_mm_put_block(obj_priv->gtt_space);
2043 obj_priv->gtt_space = NULL;
2046 /* Remove ourselves from the LRU list if present. */
2047 if (!list_empty(&obj_priv->list))
2048 list_del_init(&obj_priv->list);
2050 if (i915_gem_object_is_purgeable(obj_priv))
2051 i915_gem_object_truncate(obj);
2053 trace_i915_gem_object_unbind(obj);
2058 static struct drm_gem_object *
2059 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2061 drm_i915_private_t *dev_priv = dev->dev_private;
2062 struct drm_i915_gem_object *obj_priv;
2063 struct drm_gem_object *best = NULL;
2064 struct drm_gem_object *first = NULL;
2066 /* Try to find the smallest clean object */
2067 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2068 struct drm_gem_object *obj = obj_priv->obj;
2069 if (obj->size >= min_size) {
2070 if ((!obj_priv->dirty ||
2071 i915_gem_object_is_purgeable(obj_priv)) &&
2072 (!best || obj->size < best->size)) {
2074 if (best->size == min_size)
2082 return best ? best : first;
2086 i915_gem_evict_everything(struct drm_device *dev)
2088 drm_i915_private_t *dev_priv = dev->dev_private;
2093 spin_lock(&dev_priv->mm.active_list_lock);
2094 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2095 list_empty(&dev_priv->mm.flushing_list) &&
2096 list_empty(&dev_priv->mm.active_list));
2097 spin_unlock(&dev_priv->mm.active_list_lock);
2102 /* Flush everything (on to the inactive lists) and evict */
2103 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2104 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2108 ret = i915_wait_request(dev, seqno);
2112 ret = i915_gem_evict_from_inactive_list(dev);
2116 spin_lock(&dev_priv->mm.active_list_lock);
2117 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2118 list_empty(&dev_priv->mm.flushing_list) &&
2119 list_empty(&dev_priv->mm.active_list));
2120 spin_unlock(&dev_priv->mm.active_list_lock);
2121 BUG_ON(!lists_empty);
2127 i915_gem_evict_something(struct drm_device *dev, int min_size)
2129 drm_i915_private_t *dev_priv = dev->dev_private;
2130 struct drm_gem_object *obj;
2134 i915_gem_retire_requests(dev);
2136 /* If there's an inactive buffer available now, grab it
2139 obj = i915_gem_find_inactive_object(dev, min_size);
2141 struct drm_i915_gem_object *obj_priv;
2144 DRM_INFO("%s: evicting %p\n", __func__, obj);
2146 obj_priv = obj->driver_private;
2147 BUG_ON(obj_priv->pin_count != 0);
2148 BUG_ON(obj_priv->active);
2150 /* Wait on the rendering and unbind the buffer. */
2151 return i915_gem_object_unbind(obj);
2154 /* If we didn't get anything, but the ring is still processing
2155 * things, wait for the next to finish and hopefully leave us
2156 * a buffer to evict.
2158 if (!list_empty(&dev_priv->mm.request_list)) {
2159 struct drm_i915_gem_request *request;
2161 request = list_first_entry(&dev_priv->mm.request_list,
2162 struct drm_i915_gem_request,
2165 ret = i915_wait_request(dev, request->seqno);
2172 /* If we didn't have anything on the request list but there
2173 * are buffers awaiting a flush, emit one and try again.
2174 * When we wait on it, those buffers waiting for that flush
2175 * will get moved to inactive.
2177 if (!list_empty(&dev_priv->mm.flushing_list)) {
2178 struct drm_i915_gem_object *obj_priv;
2180 /* Find an object that we can immediately reuse */
2181 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2182 obj = obj_priv->obj;
2183 if (obj->size >= min_size)
2195 seqno = i915_add_request(dev, NULL, obj->write_domain);
2199 ret = i915_wait_request(dev, seqno);
2207 /* If we didn't do any of the above, there's no single buffer
2208 * large enough to swap out for the new one, so just evict
2209 * everything and start again. (This should be rare.)
2211 if (!list_empty (&dev_priv->mm.inactive_list))
2212 return i915_gem_evict_from_inactive_list(dev);
2214 return i915_gem_evict_everything(dev);
2219 i915_gem_object_get_pages(struct drm_gem_object *obj)
2221 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2223 struct address_space *mapping;
2224 struct inode *inode;
2228 if (obj_priv->pages_refcount++ != 0)
2231 /* Get the list of pages out of our struct file. They'll be pinned
2232 * at this point until we release them.
2234 page_count = obj->size / PAGE_SIZE;
2235 BUG_ON(obj_priv->pages != NULL);
2236 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2237 if (obj_priv->pages == NULL) {
2238 obj_priv->pages_refcount--;
2242 inode = obj->filp->f_path.dentry->d_inode;
2243 mapping = inode->i_mapping;
2244 for (i = 0; i < page_count; i++) {
2245 page = read_mapping_page(mapping, i, NULL);
2247 ret = PTR_ERR(page);
2248 i915_gem_object_put_pages(obj);
2251 obj_priv->pages[i] = page;
2254 if (obj_priv->tiling_mode != I915_TILING_NONE)
2255 i915_gem_object_do_bit_17_swizzle(obj);
2260 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2262 struct drm_gem_object *obj = reg->obj;
2263 struct drm_device *dev = obj->dev;
2264 drm_i915_private_t *dev_priv = dev->dev_private;
2265 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2266 int regnum = obj_priv->fence_reg;
2269 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2271 val |= obj_priv->gtt_offset & 0xfffff000;
2272 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2273 if (obj_priv->tiling_mode == I915_TILING_Y)
2274 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2275 val |= I965_FENCE_REG_VALID;
2277 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2280 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2282 struct drm_gem_object *obj = reg->obj;
2283 struct drm_device *dev = obj->dev;
2284 drm_i915_private_t *dev_priv = dev->dev_private;
2285 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2286 int regnum = obj_priv->fence_reg;
2288 uint32_t fence_reg, val;
2291 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2292 (obj_priv->gtt_offset & (obj->size - 1))) {
2293 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2294 __func__, obj_priv->gtt_offset, obj->size);
2298 if (obj_priv->tiling_mode == I915_TILING_Y &&
2299 HAS_128_BYTE_Y_TILING(dev))
2304 /* Note: pitch better be a power of two tile widths */
2305 pitch_val = obj_priv->stride / tile_width;
2306 pitch_val = ffs(pitch_val) - 1;
2308 val = obj_priv->gtt_offset;
2309 if (obj_priv->tiling_mode == I915_TILING_Y)
2310 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2311 val |= I915_FENCE_SIZE_BITS(obj->size);
2312 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2313 val |= I830_FENCE_REG_VALID;
2316 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2318 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2319 I915_WRITE(fence_reg, val);
2322 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2324 struct drm_gem_object *obj = reg->obj;
2325 struct drm_device *dev = obj->dev;
2326 drm_i915_private_t *dev_priv = dev->dev_private;
2327 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2328 int regnum = obj_priv->fence_reg;
2331 uint32_t fence_size_bits;
2333 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2334 (obj_priv->gtt_offset & (obj->size - 1))) {
2335 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2336 __func__, obj_priv->gtt_offset);
2340 pitch_val = obj_priv->stride / 128;
2341 pitch_val = ffs(pitch_val) - 1;
2342 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2344 val = obj_priv->gtt_offset;
2345 if (obj_priv->tiling_mode == I915_TILING_Y)
2346 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2347 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2348 WARN_ON(fence_size_bits & ~0x00000f00);
2349 val |= fence_size_bits;
2350 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2351 val |= I830_FENCE_REG_VALID;
2353 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2357 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2358 * @obj: object to map through a fence reg
2360 * When mapping objects through the GTT, userspace wants to be able to write
2361 * to them without having to worry about swizzling if the object is tiled.
2363 * This function walks the fence regs looking for a free one for @obj,
2364 * stealing one if it can't find any.
2366 * It then sets up the reg based on the object's properties: address, pitch
2367 * and tiling format.
2370 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2372 struct drm_device *dev = obj->dev;
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2375 struct drm_i915_fence_reg *reg = NULL;
2376 struct drm_i915_gem_object *old_obj_priv = NULL;
2379 /* Just update our place in the LRU if our fence is getting used. */
2380 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2381 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2385 switch (obj_priv->tiling_mode) {
2386 case I915_TILING_NONE:
2387 WARN(1, "allocating a fence for non-tiled object?\n");
2390 if (!obj_priv->stride)
2392 WARN((obj_priv->stride & (512 - 1)),
2393 "object 0x%08x is X tiled but has non-512B pitch\n",
2394 obj_priv->gtt_offset);
2397 if (!obj_priv->stride)
2399 WARN((obj_priv->stride & (128 - 1)),
2400 "object 0x%08x is Y tiled but has non-128B pitch\n",
2401 obj_priv->gtt_offset);
2405 /* First try to find a free reg */
2407 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2408 reg = &dev_priv->fence_regs[i];
2412 old_obj_priv = reg->obj->driver_private;
2413 if (!old_obj_priv->pin_count)
2417 /* None available, try to steal one or wait for a user to finish */
2418 if (i == dev_priv->num_fence_regs) {
2419 struct drm_gem_object *old_obj = NULL;
2424 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2426 old_obj = old_obj_priv->obj;
2428 if (old_obj_priv->pin_count)
2431 /* Take a reference, as otherwise the wait_rendering
2432 * below may cause the object to get freed out from
2435 drm_gem_object_reference(old_obj);
2437 /* i915 uses fences for GPU access to tiled buffers */
2438 if (IS_I965G(dev) || !old_obj_priv->active)
2441 /* This brings the object to the head of the LRU if it
2442 * had been written to. The only way this should
2443 * result in us waiting longer than the expected
2444 * optimal amount of time is if there was a
2445 * fence-using buffer later that was read-only.
2447 i915_gem_object_flush_gpu_write_domain(old_obj);
2448 ret = i915_gem_object_wait_rendering(old_obj);
2450 drm_gem_object_unreference(old_obj);
2458 * Zap this virtual mapping so we can set up a fence again
2459 * for this object next time we need it.
2461 i915_gem_release_mmap(old_obj);
2463 i = old_obj_priv->fence_reg;
2464 reg = &dev_priv->fence_regs[i];
2466 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2467 list_del_init(&old_obj_priv->fence_list);
2469 drm_gem_object_unreference(old_obj);
2472 obj_priv->fence_reg = i;
2473 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2478 i965_write_fence_reg(reg);
2479 else if (IS_I9XX(dev))
2480 i915_write_fence_reg(reg);
2482 i830_write_fence_reg(reg);
2484 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2490 * i915_gem_clear_fence_reg - clear out fence register info
2491 * @obj: object to clear
2493 * Zeroes out the fence register itself and clears out the associated
2494 * data structures in dev_priv and obj_priv.
2497 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2499 struct drm_device *dev = obj->dev;
2500 drm_i915_private_t *dev_priv = dev->dev_private;
2501 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2504 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2508 if (obj_priv->fence_reg < 8)
2509 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2511 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2514 I915_WRITE(fence_reg, 0);
2517 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2518 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2519 list_del_init(&obj_priv->fence_list);
2523 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2524 * to the buffer to finish, and then resets the fence register.
2525 * @obj: tiled object holding a fence register.
2527 * Zeroes out the fence register itself and clears out the associated
2528 * data structures in dev_priv and obj_priv.
2531 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2533 struct drm_device *dev = obj->dev;
2534 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2536 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2539 /* On the i915, GPU access to tiled buffers is via a fence,
2540 * therefore we must wait for any outstanding access to complete
2541 * before clearing the fence.
2543 if (!IS_I965G(dev)) {
2546 i915_gem_object_flush_gpu_write_domain(obj);
2547 i915_gem_object_flush_gtt_write_domain(obj);
2548 ret = i915_gem_object_wait_rendering(obj);
2553 i915_gem_clear_fence_reg (obj);
2559 * Finds free space in the GTT aperture and binds the object there.
2562 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2564 struct drm_device *dev = obj->dev;
2565 drm_i915_private_t *dev_priv = dev->dev_private;
2566 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2567 struct drm_mm_node *free_space;
2568 bool retry_alloc = false;
2571 if (dev_priv->mm.suspended)
2574 if (obj_priv->madv != I915_MADV_WILLNEED) {
2575 DRM_ERROR("Attempting to bind a purgeable object\n");
2580 alignment = i915_gem_get_gtt_alignment(obj);
2581 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2582 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2587 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2588 obj->size, alignment, 0);
2589 if (free_space != NULL) {
2590 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2592 if (obj_priv->gtt_space != NULL) {
2593 obj_priv->gtt_space->private = obj;
2594 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2597 if (obj_priv->gtt_space == NULL) {
2598 /* If the gtt is empty and we're still having trouble
2599 * fitting our object in, we're out of memory.
2602 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2604 ret = i915_gem_evict_something(dev, obj->size);
2612 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2613 obj->size, obj_priv->gtt_offset);
2616 i915_gem_object_set_page_gfp_mask (obj,
2617 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2619 ret = i915_gem_object_get_pages(obj);
2621 i915_gem_object_set_page_gfp_mask (obj,
2622 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2625 drm_mm_put_block(obj_priv->gtt_space);
2626 obj_priv->gtt_space = NULL;
2628 if (ret == -ENOMEM) {
2629 /* first try to clear up some space from the GTT */
2630 ret = i915_gem_evict_something(dev, obj->size);
2632 /* now try to shrink everyone else */
2633 if (! retry_alloc) {
2647 /* Create an AGP memory structure pointing at our pages, and bind it
2650 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2652 obj->size >> PAGE_SHIFT,
2653 obj_priv->gtt_offset,
2654 obj_priv->agp_type);
2655 if (obj_priv->agp_mem == NULL) {
2656 i915_gem_object_put_pages(obj);
2657 drm_mm_put_block(obj_priv->gtt_space);
2658 obj_priv->gtt_space = NULL;
2660 ret = i915_gem_evict_something(dev, obj->size);
2666 atomic_inc(&dev->gtt_count);
2667 atomic_add(obj->size, &dev->gtt_memory);
2669 /* Assert that the object is not currently in any GPU domain. As it
2670 * wasn't in the GTT, there shouldn't be any way it could have been in
2673 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2674 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2676 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2682 i915_gem_clflush_object(struct drm_gem_object *obj)
2684 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2686 /* If we don't have a page list set up, then we're not pinned
2687 * to GPU, and we can ignore the cache flush because it'll happen
2688 * again at bind time.
2690 if (obj_priv->pages == NULL)
2693 trace_i915_gem_object_clflush(obj);
2695 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2698 /** Flushes any GPU write domain for the object if it's dirty. */
2700 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2702 struct drm_device *dev = obj->dev;
2704 uint32_t old_write_domain;
2706 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2709 /* Queue the GPU write cache flushing we need. */
2710 old_write_domain = obj->write_domain;
2711 i915_gem_flush(dev, 0, obj->write_domain);
2712 seqno = i915_add_request(dev, NULL, obj->write_domain);
2713 obj->write_domain = 0;
2714 i915_gem_object_move_to_active(obj, seqno);
2716 trace_i915_gem_object_change_domain(obj,
2721 /** Flushes the GTT write domain for the object if it's dirty. */
2723 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2725 uint32_t old_write_domain;
2727 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2730 /* No actual flushing is required for the GTT write domain. Writes
2731 * to it immediately go to main memory as far as we know, so there's
2732 * no chipset flush. It also doesn't land in render cache.
2734 old_write_domain = obj->write_domain;
2735 obj->write_domain = 0;
2737 trace_i915_gem_object_change_domain(obj,
2742 /** Flushes the CPU write domain for the object if it's dirty. */
2744 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2746 struct drm_device *dev = obj->dev;
2747 uint32_t old_write_domain;
2749 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2752 i915_gem_clflush_object(obj);
2753 drm_agp_chipset_flush(dev);
2754 old_write_domain = obj->write_domain;
2755 obj->write_domain = 0;
2757 trace_i915_gem_object_change_domain(obj,
2763 * Moves a single object to the GTT read, and possibly write domain.
2765 * This function returns when the move is complete, including waiting on
2769 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2771 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2772 uint32_t old_write_domain, old_read_domains;
2775 /* Not valid to be called on unbound objects. */
2776 if (obj_priv->gtt_space == NULL)
2779 i915_gem_object_flush_gpu_write_domain(obj);
2780 /* Wait on any GPU rendering and flushing to occur. */
2781 ret = i915_gem_object_wait_rendering(obj);
2785 old_write_domain = obj->write_domain;
2786 old_read_domains = obj->read_domains;
2788 /* If we're writing through the GTT domain, then CPU and GPU caches
2789 * will need to be invalidated at next use.
2792 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2794 i915_gem_object_flush_cpu_write_domain(obj);
2796 /* It should now be out of any other write domains, and we can update
2797 * the domain values for our changes.
2799 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2800 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2802 obj->write_domain = I915_GEM_DOMAIN_GTT;
2803 obj_priv->dirty = 1;
2806 trace_i915_gem_object_change_domain(obj,
2814 * Moves a single object to the CPU read, and possibly write domain.
2816 * This function returns when the move is complete, including waiting on
2820 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2822 uint32_t old_write_domain, old_read_domains;
2825 i915_gem_object_flush_gpu_write_domain(obj);
2826 /* Wait on any GPU rendering and flushing to occur. */
2827 ret = i915_gem_object_wait_rendering(obj);
2831 i915_gem_object_flush_gtt_write_domain(obj);
2833 /* If we have a partially-valid cache of the object in the CPU,
2834 * finish invalidating it and free the per-page flags.
2836 i915_gem_object_set_to_full_cpu_read_domain(obj);
2838 old_write_domain = obj->write_domain;
2839 old_read_domains = obj->read_domains;
2841 /* Flush the CPU cache if it's still invalid. */
2842 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2843 i915_gem_clflush_object(obj);
2845 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2848 /* It should now be out of any other write domains, and we can update
2849 * the domain values for our changes.
2851 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2853 /* If we're writing through the CPU, then the GPU read domains will
2854 * need to be invalidated at next use.
2857 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2858 obj->write_domain = I915_GEM_DOMAIN_CPU;
2861 trace_i915_gem_object_change_domain(obj,
2869 * Set the next domain for the specified object. This
2870 * may not actually perform the necessary flushing/invaliding though,
2871 * as that may want to be batched with other set_domain operations
2873 * This is (we hope) the only really tricky part of gem. The goal
2874 * is fairly simple -- track which caches hold bits of the object
2875 * and make sure they remain coherent. A few concrete examples may
2876 * help to explain how it works. For shorthand, we use the notation
2877 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2878 * a pair of read and write domain masks.
2880 * Case 1: the batch buffer
2886 * 5. Unmapped from GTT
2889 * Let's take these a step at a time
2892 * Pages allocated from the kernel may still have
2893 * cache contents, so we set them to (CPU, CPU) always.
2894 * 2. Written by CPU (using pwrite)
2895 * The pwrite function calls set_domain (CPU, CPU) and
2896 * this function does nothing (as nothing changes)
2898 * This function asserts that the object is not
2899 * currently in any GPU-based read or write domains
2901 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2902 * As write_domain is zero, this function adds in the
2903 * current read domains (CPU+COMMAND, 0).
2904 * flush_domains is set to CPU.
2905 * invalidate_domains is set to COMMAND
2906 * clflush is run to get data out of the CPU caches
2907 * then i915_dev_set_domain calls i915_gem_flush to
2908 * emit an MI_FLUSH and drm_agp_chipset_flush
2909 * 5. Unmapped from GTT
2910 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2911 * flush_domains and invalidate_domains end up both zero
2912 * so no flushing/invalidating happens
2916 * Case 2: The shared render buffer
2920 * 3. Read/written by GPU
2921 * 4. set_domain to (CPU,CPU)
2922 * 5. Read/written by CPU
2923 * 6. Read/written by GPU
2926 * Same as last example, (CPU, CPU)
2928 * Nothing changes (assertions find that it is not in the GPU)
2929 * 3. Read/written by GPU
2930 * execbuffer calls set_domain (RENDER, RENDER)
2931 * flush_domains gets CPU
2932 * invalidate_domains gets GPU
2934 * MI_FLUSH and drm_agp_chipset_flush
2935 * 4. set_domain (CPU, CPU)
2936 * flush_domains gets GPU
2937 * invalidate_domains gets CPU
2938 * wait_rendering (obj) to make sure all drawing is complete.
2939 * This will include an MI_FLUSH to get the data from GPU
2941 * clflush (obj) to invalidate the CPU cache
2942 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2943 * 5. Read/written by CPU
2944 * cache lines are loaded and dirtied
2945 * 6. Read written by GPU
2946 * Same as last GPU access
2948 * Case 3: The constant buffer
2953 * 4. Updated (written) by CPU again
2962 * flush_domains = CPU
2963 * invalidate_domains = RENDER
2966 * drm_agp_chipset_flush
2967 * 4. Updated (written) by CPU again
2969 * flush_domains = 0 (no previous write domain)
2970 * invalidate_domains = 0 (no new read domains)
2973 * flush_domains = CPU
2974 * invalidate_domains = RENDER
2977 * drm_agp_chipset_flush
2980 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2982 struct drm_device *dev = obj->dev;
2983 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2984 uint32_t invalidate_domains = 0;
2985 uint32_t flush_domains = 0;
2986 uint32_t old_read_domains;
2988 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2989 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2991 intel_mark_busy(dev, obj);
2994 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2996 obj->read_domains, obj->pending_read_domains,
2997 obj->write_domain, obj->pending_write_domain);
3000 * If the object isn't moving to a new write domain,
3001 * let the object stay in multiple read domains
3003 if (obj->pending_write_domain == 0)
3004 obj->pending_read_domains |= obj->read_domains;
3006 obj_priv->dirty = 1;
3009 * Flush the current write domain if
3010 * the new read domains don't match. Invalidate
3011 * any read domains which differ from the old
3014 if (obj->write_domain &&
3015 obj->write_domain != obj->pending_read_domains) {
3016 flush_domains |= obj->write_domain;
3017 invalidate_domains |=
3018 obj->pending_read_domains & ~obj->write_domain;
3021 * Invalidate any read caches which may have
3022 * stale data. That is, any new read domains.
3024 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3025 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3027 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3028 __func__, flush_domains, invalidate_domains);
3030 i915_gem_clflush_object(obj);
3033 old_read_domains = obj->read_domains;
3035 /* The actual obj->write_domain will be updated with
3036 * pending_write_domain after we emit the accumulated flush for all
3037 * of our domain changes in execbuffers (which clears objects'
3038 * write_domains). So if we have a current write domain that we
3039 * aren't changing, set pending_write_domain to that.
3041 if (flush_domains == 0 && obj->pending_write_domain == 0)
3042 obj->pending_write_domain = obj->write_domain;
3043 obj->read_domains = obj->pending_read_domains;
3045 dev->invalidate_domains |= invalidate_domains;
3046 dev->flush_domains |= flush_domains;
3048 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3050 obj->read_domains, obj->write_domain,
3051 dev->invalidate_domains, dev->flush_domains);
3054 trace_i915_gem_object_change_domain(obj,
3060 * Moves the object from a partially CPU read to a full one.
3062 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3063 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3066 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3068 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3070 if (!obj_priv->page_cpu_valid)
3073 /* If we're partially in the CPU read domain, finish moving it in.
3075 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3078 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3079 if (obj_priv->page_cpu_valid[i])
3081 drm_clflush_pages(obj_priv->pages + i, 1);
3085 /* Free the page_cpu_valid mappings which are now stale, whether
3086 * or not we've got I915_GEM_DOMAIN_CPU.
3088 kfree(obj_priv->page_cpu_valid);
3089 obj_priv->page_cpu_valid = NULL;
3093 * Set the CPU read domain on a range of the object.
3095 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3096 * not entirely valid. The page_cpu_valid member of the object flags which
3097 * pages have been flushed, and will be respected by
3098 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3099 * of the whole object.
3101 * This function returns when the move is complete, including waiting on
3105 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3106 uint64_t offset, uint64_t size)
3108 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3109 uint32_t old_read_domains;
3112 if (offset == 0 && size == obj->size)
3113 return i915_gem_object_set_to_cpu_domain(obj, 0);
3115 i915_gem_object_flush_gpu_write_domain(obj);
3116 /* Wait on any GPU rendering and flushing to occur. */
3117 ret = i915_gem_object_wait_rendering(obj);
3120 i915_gem_object_flush_gtt_write_domain(obj);
3122 /* If we're already fully in the CPU read domain, we're done. */
3123 if (obj_priv->page_cpu_valid == NULL &&
3124 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3127 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3128 * newly adding I915_GEM_DOMAIN_CPU
3130 if (obj_priv->page_cpu_valid == NULL) {
3131 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3133 if (obj_priv->page_cpu_valid == NULL)
3135 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3136 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3138 /* Flush the cache on any pages that are still invalid from the CPU's
3141 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3143 if (obj_priv->page_cpu_valid[i])
3146 drm_clflush_pages(obj_priv->pages + i, 1);
3148 obj_priv->page_cpu_valid[i] = 1;
3151 /* It should now be out of any other write domains, and we can update
3152 * the domain values for our changes.
3154 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3156 old_read_domains = obj->read_domains;
3157 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3159 trace_i915_gem_object_change_domain(obj,
3167 * Pin an object to the GTT and evaluate the relocations landing in it.
3170 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3171 struct drm_file *file_priv,
3172 struct drm_i915_gem_exec_object *entry,
3173 struct drm_i915_gem_relocation_entry *relocs)
3175 struct drm_device *dev = obj->dev;
3176 drm_i915_private_t *dev_priv = dev->dev_private;
3177 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3179 void __iomem *reloc_page;
3181 /* Choose the GTT offset for our buffer and put it there. */
3182 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3186 entry->offset = obj_priv->gtt_offset;
3188 /* Apply the relocations, using the GTT aperture to avoid cache
3189 * flushing requirements.
3191 for (i = 0; i < entry->relocation_count; i++) {
3192 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3193 struct drm_gem_object *target_obj;
3194 struct drm_i915_gem_object *target_obj_priv;
3195 uint32_t reloc_val, reloc_offset;
3196 uint32_t __iomem *reloc_entry;
3198 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3199 reloc->target_handle);
3200 if (target_obj == NULL) {
3201 i915_gem_object_unpin(obj);
3204 target_obj_priv = target_obj->driver_private;
3207 DRM_INFO("%s: obj %p offset %08x target %d "
3208 "read %08x write %08x gtt %08x "
3209 "presumed %08x delta %08x\n",
3212 (int) reloc->offset,
3213 (int) reloc->target_handle,
3214 (int) reloc->read_domains,
3215 (int) reloc->write_domain,
3216 (int) target_obj_priv->gtt_offset,
3217 (int) reloc->presumed_offset,
3221 /* The target buffer should have appeared before us in the
3222 * exec_object list, so it should have a GTT space bound by now.
3224 if (target_obj_priv->gtt_space == NULL) {
3225 DRM_ERROR("No GTT space found for object %d\n",
3226 reloc->target_handle);
3227 drm_gem_object_unreference(target_obj);
3228 i915_gem_object_unpin(obj);
3232 /* Validate that the target is in a valid r/w GPU domain */
3233 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3234 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3235 DRM_ERROR("reloc with read/write CPU domains: "
3236 "obj %p target %d offset %d "
3237 "read %08x write %08x",
3238 obj, reloc->target_handle,
3239 (int) reloc->offset,
3240 reloc->read_domains,
3241 reloc->write_domain);
3242 drm_gem_object_unreference(target_obj);
3243 i915_gem_object_unpin(obj);
3246 if (reloc->write_domain && target_obj->pending_write_domain &&
3247 reloc->write_domain != target_obj->pending_write_domain) {
3248 DRM_ERROR("Write domain conflict: "
3249 "obj %p target %d offset %d "
3250 "new %08x old %08x\n",
3251 obj, reloc->target_handle,
3252 (int) reloc->offset,
3253 reloc->write_domain,
3254 target_obj->pending_write_domain);
3255 drm_gem_object_unreference(target_obj);
3256 i915_gem_object_unpin(obj);
3260 target_obj->pending_read_domains |= reloc->read_domains;
3261 target_obj->pending_write_domain |= reloc->write_domain;
3263 /* If the relocation already has the right value in it, no
3264 * more work needs to be done.
3266 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3267 drm_gem_object_unreference(target_obj);
3271 /* Check that the relocation address is valid... */
3272 if (reloc->offset > obj->size - 4) {
3273 DRM_ERROR("Relocation beyond object bounds: "
3274 "obj %p target %d offset %d size %d.\n",
3275 obj, reloc->target_handle,
3276 (int) reloc->offset, (int) obj->size);
3277 drm_gem_object_unreference(target_obj);
3278 i915_gem_object_unpin(obj);
3281 if (reloc->offset & 3) {
3282 DRM_ERROR("Relocation not 4-byte aligned: "
3283 "obj %p target %d offset %d.\n",
3284 obj, reloc->target_handle,
3285 (int) reloc->offset);
3286 drm_gem_object_unreference(target_obj);
3287 i915_gem_object_unpin(obj);
3291 /* and points to somewhere within the target object. */
3292 if (reloc->delta >= target_obj->size) {
3293 DRM_ERROR("Relocation beyond target object bounds: "
3294 "obj %p target %d delta %d size %d.\n",
3295 obj, reloc->target_handle,
3296 (int) reloc->delta, (int) target_obj->size);
3297 drm_gem_object_unreference(target_obj);
3298 i915_gem_object_unpin(obj);
3302 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3304 drm_gem_object_unreference(target_obj);
3305 i915_gem_object_unpin(obj);
3309 /* Map the page containing the relocation we're going to
3312 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3313 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3316 reloc_entry = (uint32_t __iomem *)(reloc_page +
3317 (reloc_offset & (PAGE_SIZE - 1)));
3318 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3321 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3322 obj, (unsigned int) reloc->offset,
3323 readl(reloc_entry), reloc_val);
3325 writel(reloc_val, reloc_entry);
3326 io_mapping_unmap_atomic(reloc_page);
3328 /* The updated presumed offset for this entry will be
3329 * copied back out to the user.
3331 reloc->presumed_offset = target_obj_priv->gtt_offset;
3333 drm_gem_object_unreference(target_obj);
3338 i915_gem_dump_object(obj, 128, __func__, ~0);
3343 /** Dispatch a batchbuffer to the ring
3346 i915_dispatch_gem_execbuffer(struct drm_device *dev,
3347 struct drm_i915_gem_execbuffer *exec,
3348 struct drm_clip_rect *cliprects,
3349 uint64_t exec_offset)
3351 drm_i915_private_t *dev_priv = dev->dev_private;
3352 int nbox = exec->num_cliprects;
3354 uint32_t exec_start, exec_len;
3357 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3358 exec_len = (uint32_t) exec->batch_len;
3360 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3362 count = nbox ? nbox : 1;
3364 for (i = 0; i < count; i++) {
3366 int ret = i915_emit_box(dev, cliprects, i,
3367 exec->DR1, exec->DR4);
3372 if (IS_I830(dev) || IS_845G(dev)) {
3374 OUT_RING(MI_BATCH_BUFFER);
3375 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3376 OUT_RING(exec_start + exec_len - 4);
3381 if (IS_I965G(dev)) {
3382 OUT_RING(MI_BATCH_BUFFER_START |
3384 MI_BATCH_NON_SECURE_I965);
3385 OUT_RING(exec_start);
3387 OUT_RING(MI_BATCH_BUFFER_START |
3389 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3395 /* XXX breadcrumb */
3399 /* Throttle our rendering by waiting until the ring has completed our requests
3400 * emitted over 20 msec ago.
3402 * Note that if we were to use the current jiffies each time around the loop,
3403 * we wouldn't escape the function with any frames outstanding if the time to
3404 * render a frame was over 20ms.
3406 * This should get us reasonable parallelism between CPU and GPU but also
3407 * relatively low latency when blocking on a particular request to finish.
3410 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3412 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3414 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3416 mutex_lock(&dev->struct_mutex);
3417 while (!list_empty(&i915_file_priv->mm.request_list)) {
3418 struct drm_i915_gem_request *request;
3420 request = list_first_entry(&i915_file_priv->mm.request_list,
3421 struct drm_i915_gem_request,
3424 if (time_after_eq(request->emitted_jiffies, recent_enough))
3427 ret = i915_wait_request(dev, request->seqno);
3431 mutex_unlock(&dev->struct_mutex);
3437 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3438 uint32_t buffer_count,
3439 struct drm_i915_gem_relocation_entry **relocs)
3441 uint32_t reloc_count = 0, reloc_index = 0, i;
3445 for (i = 0; i < buffer_count; i++) {
3446 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3448 reloc_count += exec_list[i].relocation_count;
3451 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3452 if (*relocs == NULL)
3455 for (i = 0; i < buffer_count; i++) {
3456 struct drm_i915_gem_relocation_entry __user *user_relocs;
3458 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3460 ret = copy_from_user(&(*relocs)[reloc_index],
3462 exec_list[i].relocation_count *
3465 drm_free_large(*relocs);
3470 reloc_index += exec_list[i].relocation_count;
3477 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3478 uint32_t buffer_count,
3479 struct drm_i915_gem_relocation_entry *relocs)
3481 uint32_t reloc_count = 0, i;
3484 for (i = 0; i < buffer_count; i++) {
3485 struct drm_i915_gem_relocation_entry __user *user_relocs;
3488 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3490 unwritten = copy_to_user(user_relocs,
3491 &relocs[reloc_count],
3492 exec_list[i].relocation_count *
3500 reloc_count += exec_list[i].relocation_count;
3504 drm_free_large(relocs);
3510 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3511 uint64_t exec_offset)
3513 uint32_t exec_start, exec_len;
3515 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3516 exec_len = (uint32_t) exec->batch_len;
3518 if ((exec_start | exec_len) & 0x7)
3528 i915_gem_execbuffer(struct drm_device *dev, void *data,
3529 struct drm_file *file_priv)
3531 drm_i915_private_t *dev_priv = dev->dev_private;
3532 struct drm_i915_gem_execbuffer *args = data;
3533 struct drm_i915_gem_exec_object *exec_list = NULL;
3534 struct drm_gem_object **object_list = NULL;
3535 struct drm_gem_object *batch_obj;
3536 struct drm_i915_gem_object *obj_priv;
3537 struct drm_clip_rect *cliprects = NULL;
3538 struct drm_i915_gem_relocation_entry *relocs;
3539 int ret, ret2, i, pinned = 0;
3540 uint64_t exec_offset;
3541 uint32_t seqno, flush_domains, reloc_index;
3545 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3546 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3549 if (args->buffer_count < 1) {
3550 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3553 /* Copy in the exec list from userland */
3554 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3555 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
3556 if (exec_list == NULL || object_list == NULL) {
3557 DRM_ERROR("Failed to allocate exec or object list "
3559 args->buffer_count);
3563 ret = copy_from_user(exec_list,
3564 (struct drm_i915_relocation_entry __user *)
3565 (uintptr_t) args->buffers_ptr,
3566 sizeof(*exec_list) * args->buffer_count);
3568 DRM_ERROR("copy %d exec entries failed %d\n",
3569 args->buffer_count, ret);
3573 if (args->num_cliprects != 0) {
3574 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3576 if (cliprects == NULL)
3579 ret = copy_from_user(cliprects,
3580 (struct drm_clip_rect __user *)
3581 (uintptr_t) args->cliprects_ptr,
3582 sizeof(*cliprects) * args->num_cliprects);
3584 DRM_ERROR("copy %d cliprects failed: %d\n",
3585 args->num_cliprects, ret);
3590 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3595 mutex_lock(&dev->struct_mutex);
3597 i915_verify_inactive(dev, __FILE__, __LINE__);
3599 if (atomic_read(&dev_priv->mm.wedged)) {
3600 DRM_ERROR("Execbuf while wedged\n");
3601 mutex_unlock(&dev->struct_mutex);
3606 if (dev_priv->mm.suspended) {
3607 DRM_ERROR("Execbuf while VT-switched.\n");
3608 mutex_unlock(&dev->struct_mutex);
3613 /* Look up object handles */
3614 for (i = 0; i < args->buffer_count; i++) {
3615 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3616 exec_list[i].handle);
3617 if (object_list[i] == NULL) {
3618 DRM_ERROR("Invalid object handle %d at index %d\n",
3619 exec_list[i].handle, i);
3624 obj_priv = object_list[i]->driver_private;
3625 if (obj_priv->in_execbuffer) {
3626 DRM_ERROR("Object %p appears more than once in object list\n",
3631 obj_priv->in_execbuffer = true;
3634 /* Pin and relocate */
3635 for (pin_tries = 0; ; pin_tries++) {
3639 for (i = 0; i < args->buffer_count; i++) {
3640 object_list[i]->pending_read_domains = 0;
3641 object_list[i]->pending_write_domain = 0;
3642 ret = i915_gem_object_pin_and_relocate(object_list[i],
3645 &relocs[reloc_index]);
3649 reloc_index += exec_list[i].relocation_count;
3655 /* error other than GTT full, or we've already tried again */
3656 if (ret != -ENOSPC || pin_tries >= 1) {
3657 if (ret != -ERESTARTSYS) {
3658 unsigned long long total_size = 0;
3659 for (i = 0; i < args->buffer_count; i++)
3660 total_size += object_list[i]->size;
3661 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3662 pinned+1, args->buffer_count,
3664 DRM_ERROR("%d objects [%d pinned], "
3665 "%d object bytes [%d pinned], "
3666 "%d/%d gtt bytes\n",
3667 atomic_read(&dev->object_count),
3668 atomic_read(&dev->pin_count),
3669 atomic_read(&dev->object_memory),
3670 atomic_read(&dev->pin_memory),
3671 atomic_read(&dev->gtt_memory),
3677 /* unpin all of our buffers */
3678 for (i = 0; i < pinned; i++)
3679 i915_gem_object_unpin(object_list[i]);
3682 /* evict everyone we can from the aperture */
3683 ret = i915_gem_evict_everything(dev);
3684 if (ret && ret != -ENOSPC)
3688 /* Set the pending read domains for the batch buffer to COMMAND */
3689 batch_obj = object_list[args->buffer_count-1];
3690 if (batch_obj->pending_write_domain) {
3691 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3695 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3697 /* Sanity check the batch buffer, prior to moving objects */
3698 exec_offset = exec_list[args->buffer_count - 1].offset;
3699 ret = i915_gem_check_execbuffer (args, exec_offset);
3701 DRM_ERROR("execbuf with invalid offset/length\n");
3705 i915_verify_inactive(dev, __FILE__, __LINE__);
3707 /* Zero the global flush/invalidate flags. These
3708 * will be modified as new domains are computed
3711 dev->invalidate_domains = 0;
3712 dev->flush_domains = 0;
3714 for (i = 0; i < args->buffer_count; i++) {
3715 struct drm_gem_object *obj = object_list[i];
3717 /* Compute new gpu domains and update invalidate/flush */
3718 i915_gem_object_set_to_gpu_domain(obj);
3721 i915_verify_inactive(dev, __FILE__, __LINE__);
3723 if (dev->invalidate_domains | dev->flush_domains) {
3725 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3727 dev->invalidate_domains,
3728 dev->flush_domains);
3731 dev->invalidate_domains,
3732 dev->flush_domains);
3733 if (dev->flush_domains)
3734 (void)i915_add_request(dev, file_priv,
3735 dev->flush_domains);
3738 for (i = 0; i < args->buffer_count; i++) {
3739 struct drm_gem_object *obj = object_list[i];
3740 uint32_t old_write_domain = obj->write_domain;
3742 obj->write_domain = obj->pending_write_domain;
3743 trace_i915_gem_object_change_domain(obj,
3748 i915_verify_inactive(dev, __FILE__, __LINE__);
3751 for (i = 0; i < args->buffer_count; i++) {
3752 i915_gem_object_check_coherency(object_list[i],
3753 exec_list[i].handle);
3758 i915_gem_dump_object(batch_obj,
3764 /* Exec the batchbuffer */
3765 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
3767 DRM_ERROR("dispatch failed %d\n", ret);
3772 * Ensure that the commands in the batch buffer are
3773 * finished before the interrupt fires
3775 flush_domains = i915_retire_commands(dev);
3777 i915_verify_inactive(dev, __FILE__, __LINE__);
3780 * Get a seqno representing the execution of the current buffer,
3781 * which we can wait on. We would like to mitigate these interrupts,
3782 * likely by only creating seqnos occasionally (so that we have
3783 * *some* interrupts representing completion of buffers that we can
3784 * wait on when trying to clear up gtt space).
3786 seqno = i915_add_request(dev, file_priv, flush_domains);
3788 for (i = 0; i < args->buffer_count; i++) {
3789 struct drm_gem_object *obj = object_list[i];
3791 i915_gem_object_move_to_active(obj, seqno);
3793 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3797 i915_dump_lru(dev, __func__);
3800 i915_verify_inactive(dev, __FILE__, __LINE__);
3803 for (i = 0; i < pinned; i++)
3804 i915_gem_object_unpin(object_list[i]);
3806 for (i = 0; i < args->buffer_count; i++) {
3807 if (object_list[i]) {
3808 obj_priv = object_list[i]->driver_private;
3809 obj_priv->in_execbuffer = false;
3811 drm_gem_object_unreference(object_list[i]);
3814 mutex_unlock(&dev->struct_mutex);
3817 /* Copy the new buffer offsets back to the user's exec list. */
3818 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3819 (uintptr_t) args->buffers_ptr,
3821 sizeof(*exec_list) * args->buffer_count);
3824 DRM_ERROR("failed to copy %d exec entries "
3825 "back to user (%d)\n",
3826 args->buffer_count, ret);
3830 /* Copy the updated relocations out regardless of current error
3831 * state. Failure to update the relocs would mean that the next
3832 * time userland calls execbuf, it would do so with presumed offset
3833 * state that didn't match the actual object state.
3835 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3838 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3845 drm_free_large(object_list);
3846 drm_free_large(exec_list);
3853 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3855 struct drm_device *dev = obj->dev;
3856 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3859 i915_verify_inactive(dev, __FILE__, __LINE__);
3860 if (obj_priv->gtt_space == NULL) {
3861 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3866 * Pre-965 chips need a fence register set up in order to
3867 * properly handle tiled surfaces.
3869 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
3870 ret = i915_gem_object_get_fence_reg(obj);
3872 if (ret != -EBUSY && ret != -ERESTARTSYS)
3873 DRM_ERROR("Failure to install fence: %d\n",
3878 obj_priv->pin_count++;
3880 /* If the object is not active and not pending a flush,
3881 * remove it from the inactive list
3883 if (obj_priv->pin_count == 1) {
3884 atomic_inc(&dev->pin_count);
3885 atomic_add(obj->size, &dev->pin_memory);
3886 if (!obj_priv->active &&
3887 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3888 !list_empty(&obj_priv->list))
3889 list_del_init(&obj_priv->list);
3891 i915_verify_inactive(dev, __FILE__, __LINE__);
3897 i915_gem_object_unpin(struct drm_gem_object *obj)
3899 struct drm_device *dev = obj->dev;
3900 drm_i915_private_t *dev_priv = dev->dev_private;
3901 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3903 i915_verify_inactive(dev, __FILE__, __LINE__);
3904 obj_priv->pin_count--;
3905 BUG_ON(obj_priv->pin_count < 0);
3906 BUG_ON(obj_priv->gtt_space == NULL);
3908 /* If the object is no longer pinned, and is
3909 * neither active nor being flushed, then stick it on
3912 if (obj_priv->pin_count == 0) {
3913 if (!obj_priv->active &&
3914 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3915 list_move_tail(&obj_priv->list,
3916 &dev_priv->mm.inactive_list);
3917 atomic_dec(&dev->pin_count);
3918 atomic_sub(obj->size, &dev->pin_memory);
3920 i915_verify_inactive(dev, __FILE__, __LINE__);
3924 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3925 struct drm_file *file_priv)
3927 struct drm_i915_gem_pin *args = data;
3928 struct drm_gem_object *obj;
3929 struct drm_i915_gem_object *obj_priv;
3932 mutex_lock(&dev->struct_mutex);
3934 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3936 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3938 mutex_unlock(&dev->struct_mutex);
3941 obj_priv = obj->driver_private;
3943 if (obj_priv->madv != I915_MADV_WILLNEED) {
3944 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3945 drm_gem_object_unreference(obj);
3946 mutex_unlock(&dev->struct_mutex);
3950 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3951 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3953 drm_gem_object_unreference(obj);
3954 mutex_unlock(&dev->struct_mutex);
3958 obj_priv->user_pin_count++;
3959 obj_priv->pin_filp = file_priv;
3960 if (obj_priv->user_pin_count == 1) {
3961 ret = i915_gem_object_pin(obj, args->alignment);
3963 drm_gem_object_unreference(obj);
3964 mutex_unlock(&dev->struct_mutex);
3969 /* XXX - flush the CPU caches for pinned objects
3970 * as the X server doesn't manage domains yet
3972 i915_gem_object_flush_cpu_write_domain(obj);
3973 args->offset = obj_priv->gtt_offset;
3974 drm_gem_object_unreference(obj);
3975 mutex_unlock(&dev->struct_mutex);
3981 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3982 struct drm_file *file_priv)
3984 struct drm_i915_gem_pin *args = data;
3985 struct drm_gem_object *obj;
3986 struct drm_i915_gem_object *obj_priv;
3988 mutex_lock(&dev->struct_mutex);
3990 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3992 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3994 mutex_unlock(&dev->struct_mutex);
3998 obj_priv = obj->driver_private;
3999 if (obj_priv->pin_filp != file_priv) {
4000 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4002 drm_gem_object_unreference(obj);
4003 mutex_unlock(&dev->struct_mutex);
4006 obj_priv->user_pin_count--;
4007 if (obj_priv->user_pin_count == 0) {
4008 obj_priv->pin_filp = NULL;
4009 i915_gem_object_unpin(obj);
4012 drm_gem_object_unreference(obj);
4013 mutex_unlock(&dev->struct_mutex);
4018 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4019 struct drm_file *file_priv)
4021 struct drm_i915_gem_busy *args = data;
4022 struct drm_gem_object *obj;
4023 struct drm_i915_gem_object *obj_priv;
4025 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4027 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4032 mutex_lock(&dev->struct_mutex);
4033 /* Update the active list for the hardware's current position.
4034 * Otherwise this only updates on a delayed timer or when irqs are
4035 * actually unmasked, and our working set ends up being larger than
4038 i915_gem_retire_requests(dev);
4040 obj_priv = obj->driver_private;
4041 /* Don't count being on the flushing list against the object being
4042 * done. Otherwise, a buffer left on the flushing list but not getting
4043 * flushed (because nobody's flushing that domain) won't ever return
4044 * unbusy and get reused by libdrm's bo cache. The other expected
4045 * consumer of this interface, OpenGL's occlusion queries, also specs
4046 * that the objects get unbusy "eventually" without any interference.
4048 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4050 drm_gem_object_unreference(obj);
4051 mutex_unlock(&dev->struct_mutex);
4056 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4057 struct drm_file *file_priv)
4059 return i915_gem_ring_throttle(dev, file_priv);
4063 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4064 struct drm_file *file_priv)
4066 struct drm_i915_gem_madvise *args = data;
4067 struct drm_gem_object *obj;
4068 struct drm_i915_gem_object *obj_priv;
4070 switch (args->madv) {
4071 case I915_MADV_DONTNEED:
4072 case I915_MADV_WILLNEED:
4078 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4080 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4085 mutex_lock(&dev->struct_mutex);
4086 obj_priv = obj->driver_private;
4088 if (obj_priv->pin_count) {
4089 drm_gem_object_unreference(obj);
4090 mutex_unlock(&dev->struct_mutex);
4092 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4096 if (obj_priv->madv != __I915_MADV_PURGED)
4097 obj_priv->madv = args->madv;
4099 /* if the object is no longer bound, discard its backing storage */
4100 if (i915_gem_object_is_purgeable(obj_priv) &&
4101 obj_priv->gtt_space == NULL)
4102 i915_gem_object_truncate(obj);
4104 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4106 drm_gem_object_unreference(obj);
4107 mutex_unlock(&dev->struct_mutex);
4112 int i915_gem_init_object(struct drm_gem_object *obj)
4114 struct drm_i915_gem_object *obj_priv;
4116 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
4117 if (obj_priv == NULL)
4121 * We've just allocated pages from the kernel,
4122 * so they've just been written by the CPU with
4123 * zeros. They'll need to be clflushed before we
4124 * use them with the GPU.
4126 obj->write_domain = I915_GEM_DOMAIN_CPU;
4127 obj->read_domains = I915_GEM_DOMAIN_CPU;
4129 obj_priv->agp_type = AGP_USER_MEMORY;
4131 obj->driver_private = obj_priv;
4132 obj_priv->obj = obj;
4133 obj_priv->fence_reg = I915_FENCE_REG_NONE;
4134 INIT_LIST_HEAD(&obj_priv->list);
4135 INIT_LIST_HEAD(&obj_priv->fence_list);
4136 obj_priv->madv = I915_MADV_WILLNEED;
4138 trace_i915_gem_object_create(obj);
4143 void i915_gem_free_object(struct drm_gem_object *obj)
4145 struct drm_device *dev = obj->dev;
4146 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4148 trace_i915_gem_object_destroy(obj);
4150 while (obj_priv->pin_count > 0)
4151 i915_gem_object_unpin(obj);
4153 if (obj_priv->phys_obj)
4154 i915_gem_detach_phys_object(dev, obj);
4156 i915_gem_object_unbind(obj);
4158 if (obj_priv->mmap_offset)
4159 i915_gem_free_mmap_offset(obj);
4161 kfree(obj_priv->page_cpu_valid);
4162 kfree(obj_priv->bit_17);
4163 kfree(obj->driver_private);
4166 /** Unbinds all inactive objects. */
4168 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4170 drm_i915_private_t *dev_priv = dev->dev_private;
4172 while (!list_empty(&dev_priv->mm.inactive_list)) {
4173 struct drm_gem_object *obj;
4176 obj = list_first_entry(&dev_priv->mm.inactive_list,
4177 struct drm_i915_gem_object,
4180 ret = i915_gem_object_unbind(obj);
4182 DRM_ERROR("Error unbinding object: %d\n", ret);
4191 i915_gem_idle(struct drm_device *dev)
4193 drm_i915_private_t *dev_priv = dev->dev_private;
4194 uint32_t seqno, cur_seqno, last_seqno;
4197 mutex_lock(&dev->struct_mutex);
4199 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4200 mutex_unlock(&dev->struct_mutex);
4204 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4205 * We need to replace this with a semaphore, or something.
4207 dev_priv->mm.suspended = 1;
4208 del_timer(&dev_priv->hangcheck_timer);
4210 /* Cancel the retire work handler, wait for it to finish if running
4212 mutex_unlock(&dev->struct_mutex);
4213 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4214 mutex_lock(&dev->struct_mutex);
4216 i915_kernel_lost_context(dev);
4218 /* Flush the GPU along with all non-CPU write domains
4220 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4221 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
4224 mutex_unlock(&dev->struct_mutex);
4228 dev_priv->mm.waiting_gem_seqno = seqno;
4232 cur_seqno = i915_get_gem_seqno(dev);
4233 if (i915_seqno_passed(cur_seqno, seqno))
4235 if (last_seqno == cur_seqno) {
4236 if (stuck++ > 100) {
4237 DRM_ERROR("hardware wedged\n");
4238 atomic_set(&dev_priv->mm.wedged, 1);
4239 DRM_WAKEUP(&dev_priv->irq_queue);
4244 last_seqno = cur_seqno;
4246 dev_priv->mm.waiting_gem_seqno = 0;
4248 i915_gem_retire_requests(dev);
4250 spin_lock(&dev_priv->mm.active_list_lock);
4251 if (!atomic_read(&dev_priv->mm.wedged)) {
4252 /* Active and flushing should now be empty as we've
4253 * waited for a sequence higher than any pending execbuffer
4255 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4256 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4257 /* Request should now be empty as we've also waited
4258 * for the last request in the list
4260 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4263 /* Empty the active and flushing lists to inactive. If there's
4264 * anything left at this point, it means that we're wedged and
4265 * nothing good's going to happen by leaving them there. So strip
4266 * the GPU domains and just stuff them onto inactive.
4268 while (!list_empty(&dev_priv->mm.active_list)) {
4269 struct drm_gem_object *obj;
4270 uint32_t old_write_domain;
4272 obj = list_first_entry(&dev_priv->mm.active_list,
4273 struct drm_i915_gem_object,
4275 old_write_domain = obj->write_domain;
4276 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4277 i915_gem_object_move_to_inactive(obj);
4279 trace_i915_gem_object_change_domain(obj,
4283 spin_unlock(&dev_priv->mm.active_list_lock);
4285 while (!list_empty(&dev_priv->mm.flushing_list)) {
4286 struct drm_gem_object *obj;
4287 uint32_t old_write_domain;
4289 obj = list_first_entry(&dev_priv->mm.flushing_list,
4290 struct drm_i915_gem_object,
4292 old_write_domain = obj->write_domain;
4293 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4294 i915_gem_object_move_to_inactive(obj);
4296 trace_i915_gem_object_change_domain(obj,
4302 /* Move all inactive buffers out of the GTT. */
4303 ret = i915_gem_evict_from_inactive_list(dev);
4304 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
4306 mutex_unlock(&dev->struct_mutex);
4310 i915_gem_cleanup_ringbuffer(dev);
4311 mutex_unlock(&dev->struct_mutex);
4317 i915_gem_init_hws(struct drm_device *dev)
4319 drm_i915_private_t *dev_priv = dev->dev_private;
4320 struct drm_gem_object *obj;
4321 struct drm_i915_gem_object *obj_priv;
4324 /* If we need a physical address for the status page, it's already
4325 * initialized at driver load time.
4327 if (!I915_NEED_GFX_HWS(dev))
4330 obj = drm_gem_object_alloc(dev, 4096);
4332 DRM_ERROR("Failed to allocate status page\n");
4335 obj_priv = obj->driver_private;
4336 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4338 ret = i915_gem_object_pin(obj, 4096);
4340 drm_gem_object_unreference(obj);
4344 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
4346 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
4347 if (dev_priv->hw_status_page == NULL) {
4348 DRM_ERROR("Failed to map status page.\n");
4349 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4350 i915_gem_object_unpin(obj);
4351 drm_gem_object_unreference(obj);
4354 dev_priv->hws_obj = obj;
4355 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4356 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
4357 I915_READ(HWS_PGA); /* posting read */
4358 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4364 i915_gem_cleanup_hws(struct drm_device *dev)
4366 drm_i915_private_t *dev_priv = dev->dev_private;
4367 struct drm_gem_object *obj;
4368 struct drm_i915_gem_object *obj_priv;
4370 if (dev_priv->hws_obj == NULL)
4373 obj = dev_priv->hws_obj;
4374 obj_priv = obj->driver_private;
4376 kunmap(obj_priv->pages[0]);
4377 i915_gem_object_unpin(obj);
4378 drm_gem_object_unreference(obj);
4379 dev_priv->hws_obj = NULL;
4381 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4382 dev_priv->hw_status_page = NULL;
4384 /* Write high address into HWS_PGA when disabling. */
4385 I915_WRITE(HWS_PGA, 0x1ffff000);
4389 i915_gem_init_ringbuffer(struct drm_device *dev)
4391 drm_i915_private_t *dev_priv = dev->dev_private;
4392 struct drm_gem_object *obj;
4393 struct drm_i915_gem_object *obj_priv;
4394 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
4398 ret = i915_gem_init_hws(dev);
4402 obj = drm_gem_object_alloc(dev, 128 * 1024);
4404 DRM_ERROR("Failed to allocate ringbuffer\n");
4405 i915_gem_cleanup_hws(dev);
4408 obj_priv = obj->driver_private;
4410 ret = i915_gem_object_pin(obj, 4096);
4412 drm_gem_object_unreference(obj);
4413 i915_gem_cleanup_hws(dev);
4417 /* Set up the kernel mapping for the ring. */
4418 ring->Size = obj->size;
4420 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4421 ring->map.size = obj->size;
4423 ring->map.flags = 0;
4426 drm_core_ioremap_wc(&ring->map, dev);
4427 if (ring->map.handle == NULL) {
4428 DRM_ERROR("Failed to map ringbuffer.\n");
4429 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4430 i915_gem_object_unpin(obj);
4431 drm_gem_object_unreference(obj);
4432 i915_gem_cleanup_hws(dev);
4435 ring->ring_obj = obj;
4436 ring->virtual_start = ring->map.handle;
4438 /* Stop the ring if it's running. */
4439 I915_WRITE(PRB0_CTL, 0);
4440 I915_WRITE(PRB0_TAIL, 0);
4441 I915_WRITE(PRB0_HEAD, 0);
4443 /* Initialize the ring. */
4444 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
4445 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4447 /* G45 ring initialization fails to reset head to zero */
4449 DRM_ERROR("Ring head not reset to zero "
4450 "ctl %08x head %08x tail %08x start %08x\n",
4451 I915_READ(PRB0_CTL),
4452 I915_READ(PRB0_HEAD),
4453 I915_READ(PRB0_TAIL),
4454 I915_READ(PRB0_START));
4455 I915_WRITE(PRB0_HEAD, 0);
4457 DRM_ERROR("Ring head forced to zero "
4458 "ctl %08x head %08x tail %08x start %08x\n",
4459 I915_READ(PRB0_CTL),
4460 I915_READ(PRB0_HEAD),
4461 I915_READ(PRB0_TAIL),
4462 I915_READ(PRB0_START));
4465 I915_WRITE(PRB0_CTL,
4466 ((obj->size - 4096) & RING_NR_PAGES) |
4470 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4472 /* If the head is still not zero, the ring is dead */
4474 DRM_ERROR("Ring initialization failed "
4475 "ctl %08x head %08x tail %08x start %08x\n",
4476 I915_READ(PRB0_CTL),
4477 I915_READ(PRB0_HEAD),
4478 I915_READ(PRB0_TAIL),
4479 I915_READ(PRB0_START));
4483 /* Update our cache of the ring state */
4484 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4485 i915_kernel_lost_context(dev);
4487 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4488 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4489 ring->space = ring->head - (ring->tail + 8);
4490 if (ring->space < 0)
4491 ring->space += ring->Size;
4498 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4500 drm_i915_private_t *dev_priv = dev->dev_private;
4502 if (dev_priv->ring.ring_obj == NULL)
4505 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4507 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4508 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4509 dev_priv->ring.ring_obj = NULL;
4510 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4512 i915_gem_cleanup_hws(dev);
4516 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4517 struct drm_file *file_priv)
4519 drm_i915_private_t *dev_priv = dev->dev_private;
4522 if (drm_core_check_feature(dev, DRIVER_MODESET))
4525 if (atomic_read(&dev_priv->mm.wedged)) {
4526 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4527 atomic_set(&dev_priv->mm.wedged, 0);
4530 mutex_lock(&dev->struct_mutex);
4531 dev_priv->mm.suspended = 0;
4533 ret = i915_gem_init_ringbuffer(dev);
4535 mutex_unlock(&dev->struct_mutex);
4539 spin_lock(&dev_priv->mm.active_list_lock);
4540 BUG_ON(!list_empty(&dev_priv->mm.active_list));
4541 spin_unlock(&dev_priv->mm.active_list_lock);
4543 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4544 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4545 BUG_ON(!list_empty(&dev_priv->mm.request_list));
4546 mutex_unlock(&dev->struct_mutex);
4548 drm_irq_install(dev);
4554 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4555 struct drm_file *file_priv)
4559 if (drm_core_check_feature(dev, DRIVER_MODESET))
4562 ret = i915_gem_idle(dev);
4563 drm_irq_uninstall(dev);
4569 i915_gem_lastclose(struct drm_device *dev)
4573 if (drm_core_check_feature(dev, DRIVER_MODESET))
4576 ret = i915_gem_idle(dev);
4578 DRM_ERROR("failed to idle hardware: %d\n", ret);
4582 i915_gem_load(struct drm_device *dev)
4585 drm_i915_private_t *dev_priv = dev->dev_private;
4587 spin_lock_init(&dev_priv->mm.active_list_lock);
4588 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4589 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4590 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4591 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4592 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4593 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4594 i915_gem_retire_work_handler);
4595 dev_priv->mm.next_gem_seqno = 1;
4597 spin_lock(&shrink_list_lock);
4598 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4599 spin_unlock(&shrink_list_lock);
4601 /* Old X drivers will take 0-2 for front, back, depth buffers */
4602 dev_priv->fence_reg_start = 3;
4604 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4605 dev_priv->num_fence_regs = 16;
4607 dev_priv->num_fence_regs = 8;
4609 /* Initialize fence registers to zero */
4610 if (IS_I965G(dev)) {
4611 for (i = 0; i < 16; i++)
4612 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4614 for (i = 0; i < 8; i++)
4615 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4616 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4617 for (i = 0; i < 8; i++)
4618 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4621 i915_gem_detect_bit_6_swizzle(dev);
4625 * Create a physically contiguous memory object for this object
4626 * e.g. for cursor + overlay regs
4628 int i915_gem_init_phys_object(struct drm_device *dev,
4631 drm_i915_private_t *dev_priv = dev->dev_private;
4632 struct drm_i915_gem_phys_object *phys_obj;
4635 if (dev_priv->mm.phys_objs[id - 1] || !size)
4638 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4644 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4645 if (!phys_obj->handle) {
4650 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4653 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4661 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4663 drm_i915_private_t *dev_priv = dev->dev_private;
4664 struct drm_i915_gem_phys_object *phys_obj;
4666 if (!dev_priv->mm.phys_objs[id - 1])
4669 phys_obj = dev_priv->mm.phys_objs[id - 1];
4670 if (phys_obj->cur_obj) {
4671 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4675 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4677 drm_pci_free(dev, phys_obj->handle);
4679 dev_priv->mm.phys_objs[id - 1] = NULL;
4682 void i915_gem_free_all_phys_object(struct drm_device *dev)
4686 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4687 i915_gem_free_phys_object(dev, i);
4690 void i915_gem_detach_phys_object(struct drm_device *dev,
4691 struct drm_gem_object *obj)
4693 struct drm_i915_gem_object *obj_priv;
4698 obj_priv = obj->driver_private;
4699 if (!obj_priv->phys_obj)
4702 ret = i915_gem_object_get_pages(obj);
4706 page_count = obj->size / PAGE_SIZE;
4708 for (i = 0; i < page_count; i++) {
4709 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4710 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4712 memcpy(dst, src, PAGE_SIZE);
4713 kunmap_atomic(dst, KM_USER0);
4715 drm_clflush_pages(obj_priv->pages, page_count);
4716 drm_agp_chipset_flush(dev);
4718 i915_gem_object_put_pages(obj);
4720 obj_priv->phys_obj->cur_obj = NULL;
4721 obj_priv->phys_obj = NULL;
4725 i915_gem_attach_phys_object(struct drm_device *dev,
4726 struct drm_gem_object *obj, int id)
4728 drm_i915_private_t *dev_priv = dev->dev_private;
4729 struct drm_i915_gem_object *obj_priv;
4734 if (id > I915_MAX_PHYS_OBJECT)
4737 obj_priv = obj->driver_private;
4739 if (obj_priv->phys_obj) {
4740 if (obj_priv->phys_obj->id == id)
4742 i915_gem_detach_phys_object(dev, obj);
4746 /* create a new object */
4747 if (!dev_priv->mm.phys_objs[id - 1]) {
4748 ret = i915_gem_init_phys_object(dev, id,
4751 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4756 /* bind to the object */
4757 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4758 obj_priv->phys_obj->cur_obj = obj;
4760 ret = i915_gem_object_get_pages(obj);
4762 DRM_ERROR("failed to get page list\n");
4766 page_count = obj->size / PAGE_SIZE;
4768 for (i = 0; i < page_count; i++) {
4769 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4770 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4772 memcpy(dst, src, PAGE_SIZE);
4773 kunmap_atomic(src, KM_USER0);
4776 i915_gem_object_put_pages(obj);
4784 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4785 struct drm_i915_gem_pwrite *args,
4786 struct drm_file *file_priv)
4788 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4791 char __user *user_data;
4793 user_data = (char __user *) (uintptr_t) args->data_ptr;
4794 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4796 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
4797 ret = copy_from_user(obj_addr, user_data, args->size);
4801 drm_agp_chipset_flush(dev);
4805 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4807 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4809 /* Clean up our request list when the client is going away, so that
4810 * later retire_requests won't dereference our soon-to-be-gone
4813 mutex_lock(&dev->struct_mutex);
4814 while (!list_empty(&i915_file_priv->mm.request_list))
4815 list_del_init(i915_file_priv->mm.request_list.next);
4816 mutex_unlock(&dev->struct_mutex);
4820 i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4822 drm_i915_private_t *dev_priv, *next_dev;
4823 struct drm_i915_gem_object *obj_priv, *next_obj;
4825 int would_deadlock = 1;
4827 /* "fast-path" to count number of available objects */
4828 if (nr_to_scan == 0) {
4829 spin_lock(&shrink_list_lock);
4830 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4831 struct drm_device *dev = dev_priv->dev;
4833 if (mutex_trylock(&dev->struct_mutex)) {
4834 list_for_each_entry(obj_priv,
4835 &dev_priv->mm.inactive_list,
4838 mutex_unlock(&dev->struct_mutex);
4841 spin_unlock(&shrink_list_lock);
4843 return (cnt / 100) * sysctl_vfs_cache_pressure;
4846 spin_lock(&shrink_list_lock);
4848 /* first scan for clean buffers */
4849 list_for_each_entry_safe(dev_priv, next_dev,
4850 &shrink_list, mm.shrink_list) {
4851 struct drm_device *dev = dev_priv->dev;
4853 if (! mutex_trylock(&dev->struct_mutex))
4856 spin_unlock(&shrink_list_lock);
4858 i915_gem_retire_requests(dev);
4860 list_for_each_entry_safe(obj_priv, next_obj,
4861 &dev_priv->mm.inactive_list,
4863 if (i915_gem_object_is_purgeable(obj_priv)) {
4864 i915_gem_object_unbind(obj_priv->obj);
4865 if (--nr_to_scan <= 0)
4870 spin_lock(&shrink_list_lock);
4871 mutex_unlock(&dev->struct_mutex);
4875 if (nr_to_scan <= 0)
4879 /* second pass, evict/count anything still on the inactive list */
4880 list_for_each_entry_safe(dev_priv, next_dev,
4881 &shrink_list, mm.shrink_list) {
4882 struct drm_device *dev = dev_priv->dev;
4884 if (! mutex_trylock(&dev->struct_mutex))
4887 spin_unlock(&shrink_list_lock);
4889 list_for_each_entry_safe(obj_priv, next_obj,
4890 &dev_priv->mm.inactive_list,
4892 if (nr_to_scan > 0) {
4893 i915_gem_object_unbind(obj_priv->obj);
4899 spin_lock(&shrink_list_lock);
4900 mutex_unlock(&dev->struct_mutex);
4905 spin_unlock(&shrink_list_lock);
4910 return (cnt / 100) * sysctl_vfs_cache_pressure;
4915 static struct shrinker shrinker = {
4916 .shrink = i915_gem_shrink,
4917 .seeks = DEFAULT_SEEKS,
4921 i915_gem_shrinker_init(void)
4923 register_shrinker(&shrinker);
4927 i915_gem_shrinker_exit(void)
4929 unregister_shrinker(&shrinker);