2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
41 static __must_check int
42 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
43 struct i915_address_space *vm,
45 bool map_and_fenceable,
47 static int i915_gem_phys_pwrite(struct drm_device *dev,
48 struct drm_i915_gem_object *obj,
49 struct drm_i915_gem_pwrite *args,
50 struct drm_file *file);
52 static void i915_gem_write_fence(struct drm_device *dev, int reg,
53 struct drm_i915_gem_object *obj);
54 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
55 struct drm_i915_fence_reg *fence,
58 static int i915_gem_inactive_shrink(struct shrinker *shrinker,
59 struct shrink_control *sc);
60 static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
61 static void i915_gem_shrink_all(struct drm_i915_private *dev_priv);
62 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
64 static bool cpu_cache_is_coherent(struct drm_device *dev,
65 enum i915_cache_level level)
67 return HAS_LLC(dev) || level != I915_CACHE_NONE;
70 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
73 i915_gem_release_mmap(obj);
75 /* As we do not have an associated fence register, we will force
76 * a tiling change if we ever need to acquire one.
78 obj->fence_dirty = false;
79 obj->fence_reg = I915_FENCE_REG_NONE;
82 /* some bookkeeping */
83 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
86 spin_lock(&dev_priv->mm.object_stat_lock);
87 dev_priv->mm.object_count++;
88 dev_priv->mm.object_memory += size;
89 spin_unlock(&dev_priv->mm.object_stat_lock);
92 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
95 spin_lock(&dev_priv->mm.object_stat_lock);
96 dev_priv->mm.object_count--;
97 dev_priv->mm.object_memory -= size;
98 spin_unlock(&dev_priv->mm.object_stat_lock);
102 i915_gem_wait_for_error(struct i915_gpu_error *error)
106 #define EXIT_COND (!i915_reset_in_progress(error) || \
107 i915_terminally_wedged(error))
112 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
113 * userspace. If it takes that long something really bad is going on and
114 * we should simply try to bail out and fail as gracefully as possible.
116 ret = wait_event_interruptible_timeout(error->reset_queue,
120 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
122 } else if (ret < 0) {
130 int i915_mutex_lock_interruptible(struct drm_device *dev)
132 struct drm_i915_private *dev_priv = dev->dev_private;
135 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
139 ret = mutex_lock_interruptible(&dev->struct_mutex);
143 WARN_ON(i915_verify_lists(dev));
148 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
150 return i915_gem_obj_bound_any(obj) && !obj->active;
154 i915_gem_init_ioctl(struct drm_device *dev, void *data,
155 struct drm_file *file)
157 struct drm_i915_private *dev_priv = dev->dev_private;
158 struct drm_i915_gem_init *args = data;
160 if (drm_core_check_feature(dev, DRIVER_MODESET))
163 if (args->gtt_start >= args->gtt_end ||
164 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
167 /* GEM with user mode setting was never supported on ilk and later. */
168 if (INTEL_INFO(dev)->gen >= 5)
171 mutex_lock(&dev->struct_mutex);
172 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
174 dev_priv->gtt.mappable_end = args->gtt_end;
175 mutex_unlock(&dev->struct_mutex);
181 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
182 struct drm_file *file)
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 struct drm_i915_gem_get_aperture *args = data;
186 struct drm_i915_gem_object *obj;
190 mutex_lock(&dev->struct_mutex);
191 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
193 pinned += i915_gem_obj_ggtt_size(obj);
194 mutex_unlock(&dev->struct_mutex);
196 args->aper_size = dev_priv->gtt.base.total;
197 args->aper_available_size = args->aper_size - pinned;
202 void *i915_gem_object_alloc(struct drm_device *dev)
204 struct drm_i915_private *dev_priv = dev->dev_private;
205 return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO);
208 void i915_gem_object_free(struct drm_i915_gem_object *obj)
210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
211 kmem_cache_free(dev_priv->slab, obj);
215 i915_gem_create(struct drm_file *file,
216 struct drm_device *dev,
220 struct drm_i915_gem_object *obj;
224 size = roundup(size, PAGE_SIZE);
228 /* Allocate the new object */
229 obj = i915_gem_alloc_object(dev, size);
233 ret = drm_gem_handle_create(file, &obj->base, &handle);
234 /* drop reference from allocate - handle holds it now */
235 drm_gem_object_unreference_unlocked(&obj->base);
244 i915_gem_dumb_create(struct drm_file *file,
245 struct drm_device *dev,
246 struct drm_mode_create_dumb *args)
248 /* have to work out size/pitch and return them */
249 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
250 args->size = args->pitch * args->height;
251 return i915_gem_create(file, dev,
252 args->size, &args->handle);
255 int i915_gem_dumb_destroy(struct drm_file *file,
256 struct drm_device *dev,
259 return drm_gem_handle_delete(file, handle);
263 * Creates a new mm object and returns a handle to it.
266 i915_gem_create_ioctl(struct drm_device *dev, void *data,
267 struct drm_file *file)
269 struct drm_i915_gem_create *args = data;
271 return i915_gem_create(file, dev,
272 args->size, &args->handle);
276 __copy_to_user_swizzled(char __user *cpu_vaddr,
277 const char *gpu_vaddr, int gpu_offset,
280 int ret, cpu_offset = 0;
283 int cacheline_end = ALIGN(gpu_offset + 1, 64);
284 int this_length = min(cacheline_end - gpu_offset, length);
285 int swizzled_gpu_offset = gpu_offset ^ 64;
287 ret = __copy_to_user(cpu_vaddr + cpu_offset,
288 gpu_vaddr + swizzled_gpu_offset,
293 cpu_offset += this_length;
294 gpu_offset += this_length;
295 length -= this_length;
302 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
303 const char __user *cpu_vaddr,
306 int ret, cpu_offset = 0;
309 int cacheline_end = ALIGN(gpu_offset + 1, 64);
310 int this_length = min(cacheline_end - gpu_offset, length);
311 int swizzled_gpu_offset = gpu_offset ^ 64;
313 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
314 cpu_vaddr + cpu_offset,
319 cpu_offset += this_length;
320 gpu_offset += this_length;
321 length -= this_length;
327 /* Per-page copy function for the shmem pread fastpath.
328 * Flushes invalid cachelines before reading the target if
329 * needs_clflush is set. */
331 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
332 char __user *user_data,
333 bool page_do_bit17_swizzling, bool needs_clflush)
338 if (unlikely(page_do_bit17_swizzling))
341 vaddr = kmap_atomic(page);
343 drm_clflush_virt_range(vaddr + shmem_page_offset,
345 ret = __copy_to_user_inatomic(user_data,
346 vaddr + shmem_page_offset,
348 kunmap_atomic(vaddr);
350 return ret ? -EFAULT : 0;
354 shmem_clflush_swizzled_range(char *addr, unsigned long length,
357 if (unlikely(swizzled)) {
358 unsigned long start = (unsigned long) addr;
359 unsigned long end = (unsigned long) addr + length;
361 /* For swizzling simply ensure that we always flush both
362 * channels. Lame, but simple and it works. Swizzled
363 * pwrite/pread is far from a hotpath - current userspace
364 * doesn't use it at all. */
365 start = round_down(start, 128);
366 end = round_up(end, 128);
368 drm_clflush_virt_range((void *)start, end - start);
370 drm_clflush_virt_range(addr, length);
375 /* Only difference to the fast-path function is that this can handle bit17
376 * and uses non-atomic copy and kmap functions. */
378 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
379 char __user *user_data,
380 bool page_do_bit17_swizzling, bool needs_clflush)
387 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
389 page_do_bit17_swizzling);
391 if (page_do_bit17_swizzling)
392 ret = __copy_to_user_swizzled(user_data,
393 vaddr, shmem_page_offset,
396 ret = __copy_to_user(user_data,
397 vaddr + shmem_page_offset,
401 return ret ? - EFAULT : 0;
405 i915_gem_shmem_pread(struct drm_device *dev,
406 struct drm_i915_gem_object *obj,
407 struct drm_i915_gem_pread *args,
408 struct drm_file *file)
410 char __user *user_data;
413 int shmem_page_offset, page_length, ret = 0;
414 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
416 int needs_clflush = 0;
417 struct sg_page_iter sg_iter;
419 user_data = to_user_ptr(args->data_ptr);
422 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
424 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
425 /* If we're not in the cpu read domain, set ourself into the gtt
426 * read domain and manually flush cachelines (if required). This
427 * optimizes for the case when the gpu will dirty the data
428 * anyway again before the next pread happens. */
429 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
430 if (i915_gem_obj_bound_any(obj)) {
431 ret = i915_gem_object_set_to_gtt_domain(obj, false);
437 ret = i915_gem_object_get_pages(obj);
441 i915_gem_object_pin_pages(obj);
443 offset = args->offset;
445 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
446 offset >> PAGE_SHIFT) {
447 struct page *page = sg_page_iter_page(&sg_iter);
452 /* Operation in this page
454 * shmem_page_offset = offset within page in shmem file
455 * page_length = bytes to copy for this page
457 shmem_page_offset = offset_in_page(offset);
458 page_length = remain;
459 if ((shmem_page_offset + page_length) > PAGE_SIZE)
460 page_length = PAGE_SIZE - shmem_page_offset;
462 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
463 (page_to_phys(page) & (1 << 17)) != 0;
465 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
466 user_data, page_do_bit17_swizzling,
471 mutex_unlock(&dev->struct_mutex);
473 if (likely(!i915_prefault_disable) && !prefaulted) {
474 ret = fault_in_multipages_writeable(user_data, remain);
475 /* Userspace is tricking us, but we've already clobbered
476 * its pages with the prefault and promised to write the
477 * data up to the first fault. Hence ignore any errors
478 * and just continue. */
483 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
484 user_data, page_do_bit17_swizzling,
487 mutex_lock(&dev->struct_mutex);
490 mark_page_accessed(page);
495 remain -= page_length;
496 user_data += page_length;
497 offset += page_length;
501 i915_gem_object_unpin_pages(obj);
507 * Reads data from the object referenced by handle.
509 * On error, the contents of *data are undefined.
512 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
513 struct drm_file *file)
515 struct drm_i915_gem_pread *args = data;
516 struct drm_i915_gem_object *obj;
522 if (!access_ok(VERIFY_WRITE,
523 to_user_ptr(args->data_ptr),
527 ret = i915_mutex_lock_interruptible(dev);
531 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
532 if (&obj->base == NULL) {
537 /* Bounds check source. */
538 if (args->offset > obj->base.size ||
539 args->size > obj->base.size - args->offset) {
544 /* prime objects have no backing filp to GEM pread/pwrite
547 if (!obj->base.filp) {
552 trace_i915_gem_object_pread(obj, args->offset, args->size);
554 ret = i915_gem_shmem_pread(dev, obj, args, file);
557 drm_gem_object_unreference(&obj->base);
559 mutex_unlock(&dev->struct_mutex);
563 /* This is the fast write path which cannot handle
564 * page faults in the source data
568 fast_user_write(struct io_mapping *mapping,
569 loff_t page_base, int page_offset,
570 char __user *user_data,
573 void __iomem *vaddr_atomic;
575 unsigned long unwritten;
577 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
578 /* We can use the cpu mem copy function because this is X86. */
579 vaddr = (void __force*)vaddr_atomic + page_offset;
580 unwritten = __copy_from_user_inatomic_nocache(vaddr,
582 io_mapping_unmap_atomic(vaddr_atomic);
587 * This is the fast pwrite path, where we copy the data directly from the
588 * user into the GTT, uncached.
591 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
592 struct drm_i915_gem_object *obj,
593 struct drm_i915_gem_pwrite *args,
594 struct drm_file *file)
596 drm_i915_private_t *dev_priv = dev->dev_private;
598 loff_t offset, page_base;
599 char __user *user_data;
600 int page_offset, page_length, ret;
602 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
606 ret = i915_gem_object_set_to_gtt_domain(obj, true);
610 ret = i915_gem_object_put_fence(obj);
614 user_data = to_user_ptr(args->data_ptr);
617 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
620 /* Operation in this page
622 * page_base = page offset within aperture
623 * page_offset = offset within page
624 * page_length = bytes to copy for this page
626 page_base = offset & PAGE_MASK;
627 page_offset = offset_in_page(offset);
628 page_length = remain;
629 if ((page_offset + remain) > PAGE_SIZE)
630 page_length = PAGE_SIZE - page_offset;
632 /* If we get a fault while copying data, then (presumably) our
633 * source page isn't available. Return the error and we'll
634 * retry in the slow path.
636 if (fast_user_write(dev_priv->gtt.mappable, page_base,
637 page_offset, user_data, page_length)) {
642 remain -= page_length;
643 user_data += page_length;
644 offset += page_length;
648 i915_gem_object_unpin(obj);
653 /* Per-page copy function for the shmem pwrite fastpath.
654 * Flushes invalid cachelines before writing to the target if
655 * needs_clflush_before is set and flushes out any written cachelines after
656 * writing if needs_clflush is set. */
658 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
659 char __user *user_data,
660 bool page_do_bit17_swizzling,
661 bool needs_clflush_before,
662 bool needs_clflush_after)
667 if (unlikely(page_do_bit17_swizzling))
670 vaddr = kmap_atomic(page);
671 if (needs_clflush_before)
672 drm_clflush_virt_range(vaddr + shmem_page_offset,
674 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
677 if (needs_clflush_after)
678 drm_clflush_virt_range(vaddr + shmem_page_offset,
680 kunmap_atomic(vaddr);
682 return ret ? -EFAULT : 0;
685 /* Only difference to the fast-path function is that this can handle bit17
686 * and uses non-atomic copy and kmap functions. */
688 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
689 char __user *user_data,
690 bool page_do_bit17_swizzling,
691 bool needs_clflush_before,
692 bool needs_clflush_after)
698 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
699 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
701 page_do_bit17_swizzling);
702 if (page_do_bit17_swizzling)
703 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
707 ret = __copy_from_user(vaddr + shmem_page_offset,
710 if (needs_clflush_after)
711 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
713 page_do_bit17_swizzling);
716 return ret ? -EFAULT : 0;
720 i915_gem_shmem_pwrite(struct drm_device *dev,
721 struct drm_i915_gem_object *obj,
722 struct drm_i915_gem_pwrite *args,
723 struct drm_file *file)
727 char __user *user_data;
728 int shmem_page_offset, page_length, ret = 0;
729 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
730 int hit_slowpath = 0;
731 int needs_clflush_after = 0;
732 int needs_clflush_before = 0;
733 struct sg_page_iter sg_iter;
735 user_data = to_user_ptr(args->data_ptr);
738 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
740 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
741 /* If we're not in the cpu write domain, set ourself into the gtt
742 * write domain and manually flush cachelines (if required). This
743 * optimizes for the case when the gpu will use the data
744 * right away and we therefore have to clflush anyway. */
745 if (obj->cache_level == I915_CACHE_NONE)
746 needs_clflush_after = 1;
747 if (i915_gem_obj_bound_any(obj)) {
748 ret = i915_gem_object_set_to_gtt_domain(obj, true);
753 /* Same trick applies to invalidate partially written cachelines read
755 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
756 needs_clflush_before =
757 !cpu_cache_is_coherent(dev, obj->cache_level);
759 ret = i915_gem_object_get_pages(obj);
763 i915_gem_object_pin_pages(obj);
765 offset = args->offset;
768 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
769 offset >> PAGE_SHIFT) {
770 struct page *page = sg_page_iter_page(&sg_iter);
771 int partial_cacheline_write;
776 /* Operation in this page
778 * shmem_page_offset = offset within page in shmem file
779 * page_length = bytes to copy for this page
781 shmem_page_offset = offset_in_page(offset);
783 page_length = remain;
784 if ((shmem_page_offset + page_length) > PAGE_SIZE)
785 page_length = PAGE_SIZE - shmem_page_offset;
787 /* If we don't overwrite a cacheline completely we need to be
788 * careful to have up-to-date data by first clflushing. Don't
789 * overcomplicate things and flush the entire patch. */
790 partial_cacheline_write = needs_clflush_before &&
791 ((shmem_page_offset | page_length)
792 & (boot_cpu_data.x86_clflush_size - 1));
794 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
795 (page_to_phys(page) & (1 << 17)) != 0;
797 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
798 user_data, page_do_bit17_swizzling,
799 partial_cacheline_write,
800 needs_clflush_after);
805 mutex_unlock(&dev->struct_mutex);
806 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
807 user_data, page_do_bit17_swizzling,
808 partial_cacheline_write,
809 needs_clflush_after);
811 mutex_lock(&dev->struct_mutex);
814 set_page_dirty(page);
815 mark_page_accessed(page);
820 remain -= page_length;
821 user_data += page_length;
822 offset += page_length;
826 i915_gem_object_unpin_pages(obj);
830 * Fixup: Flush cpu caches in case we didn't flush the dirty
831 * cachelines in-line while writing and the object moved
832 * out of the cpu write domain while we've dropped the lock.
834 if (!needs_clflush_after &&
835 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
836 i915_gem_clflush_object(obj);
837 i915_gem_chipset_flush(dev);
841 if (needs_clflush_after)
842 i915_gem_chipset_flush(dev);
848 * Writes data to the object referenced by handle.
850 * On error, the contents of the buffer that were to be modified are undefined.
853 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
854 struct drm_file *file)
856 struct drm_i915_gem_pwrite *args = data;
857 struct drm_i915_gem_object *obj;
863 if (!access_ok(VERIFY_READ,
864 to_user_ptr(args->data_ptr),
868 if (likely(!i915_prefault_disable)) {
869 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
875 ret = i915_mutex_lock_interruptible(dev);
879 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
880 if (&obj->base == NULL) {
885 /* Bounds check destination. */
886 if (args->offset > obj->base.size ||
887 args->size > obj->base.size - args->offset) {
892 /* prime objects have no backing filp to GEM pread/pwrite
895 if (!obj->base.filp) {
900 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
903 /* We can only do the GTT pwrite on untiled buffers, as otherwise
904 * it would end up going through the fenced access, and we'll get
905 * different detiling behavior between reading and writing.
906 * pread/pwrite currently are reading and writing from the CPU
907 * perspective, requiring manual detiling by the client.
910 ret = i915_gem_phys_pwrite(dev, obj, args, file);
914 if (obj->cache_level == I915_CACHE_NONE &&
915 obj->tiling_mode == I915_TILING_NONE &&
916 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
917 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
918 /* Note that the gtt paths might fail with non-page-backed user
919 * pointers (e.g. gtt mappings when moving data between
920 * textures). Fallback to the shmem path in that case. */
923 if (ret == -EFAULT || ret == -ENOSPC)
924 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
927 drm_gem_object_unreference(&obj->base);
929 mutex_unlock(&dev->struct_mutex);
934 i915_gem_check_wedge(struct i915_gpu_error *error,
937 if (i915_reset_in_progress(error)) {
938 /* Non-interruptible callers can't handle -EAGAIN, hence return
939 * -EIO unconditionally for these. */
943 /* Recovery complete, but the reset failed ... */
944 if (i915_terminally_wedged(error))
954 * Compare seqno against outstanding lazy request. Emit a request if they are
958 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
962 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
965 if (seqno == ring->outstanding_lazy_request)
966 ret = i915_add_request(ring, NULL);
972 * __wait_seqno - wait until execution of seqno has finished
973 * @ring: the ring expected to report seqno
975 * @reset_counter: reset sequence associated with the given seqno
976 * @interruptible: do an interruptible wait (normally yes)
977 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
979 * Note: It is of utmost importance that the passed in seqno and reset_counter
980 * values have been read by the caller in an smp safe manner. Where read-side
981 * locks are involved, it is sufficient to read the reset_counter before
982 * unlocking the lock that protects the seqno. For lockless tricks, the
983 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
986 * Returns 0 if the seqno was found within the alloted time. Else returns the
987 * errno with remaining time filled in timeout argument.
989 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
990 unsigned reset_counter,
991 bool interruptible, struct timespec *timeout)
993 drm_i915_private_t *dev_priv = ring->dev->dev_private;
994 struct timespec before, now, wait_time={1,0};
995 unsigned long timeout_jiffies;
997 bool wait_forever = true;
1000 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1003 trace_i915_gem_request_wait_begin(ring, seqno);
1005 if (timeout != NULL) {
1006 wait_time = *timeout;
1007 wait_forever = false;
1010 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1012 if (WARN_ON(!ring->irq_get(ring)))
1015 /* Record current time in case interrupted by signal, or wedged * */
1016 getrawmonotonic(&before);
1019 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1020 i915_reset_in_progress(&dev_priv->gpu_error) || \
1021 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1024 end = wait_event_interruptible_timeout(ring->irq_queue,
1028 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1031 /* We need to check whether any gpu reset happened in between
1032 * the caller grabbing the seqno and now ... */
1033 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1036 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1038 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1041 } while (end == 0 && wait_forever);
1043 getrawmonotonic(&now);
1045 ring->irq_put(ring);
1046 trace_i915_gem_request_wait_end(ring, seqno);
1050 struct timespec sleep_time = timespec_sub(now, before);
1051 *timeout = timespec_sub(*timeout, sleep_time);
1052 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1053 set_normalized_timespec(timeout, 0, 0);
1058 case -EAGAIN: /* Wedged */
1059 case -ERESTARTSYS: /* Signal */
1061 case 0: /* Timeout */
1063 default: /* Completed */
1064 WARN_ON(end < 0); /* We're not aware of other errors */
1070 * Waits for a sequence number to be signaled, and cleans up the
1071 * request and object lists appropriately for that event.
1074 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1076 struct drm_device *dev = ring->dev;
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 bool interruptible = dev_priv->mm.interruptible;
1081 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1084 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1088 ret = i915_gem_check_olr(ring, seqno);
1092 return __wait_seqno(ring, seqno,
1093 atomic_read(&dev_priv->gpu_error.reset_counter),
1094 interruptible, NULL);
1098 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1099 struct intel_ring_buffer *ring)
1101 i915_gem_retire_requests_ring(ring);
1103 /* Manually manage the write flush as we may have not yet
1104 * retired the buffer.
1106 * Note that the last_write_seqno is always the earlier of
1107 * the two (read/write) seqno, so if we haved successfully waited,
1108 * we know we have passed the last write.
1110 obj->last_write_seqno = 0;
1111 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1117 * Ensures that all rendering to the object has completed and the object is
1118 * safe to unbind from the GTT or access from the CPU.
1120 static __must_check int
1121 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1124 struct intel_ring_buffer *ring = obj->ring;
1128 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1132 ret = i915_wait_seqno(ring, seqno);
1136 return i915_gem_object_wait_rendering__tail(obj, ring);
1139 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1140 * as the object state may change during this call.
1142 static __must_check int
1143 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1146 struct drm_device *dev = obj->base.dev;
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148 struct intel_ring_buffer *ring = obj->ring;
1149 unsigned reset_counter;
1153 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1154 BUG_ON(!dev_priv->mm.interruptible);
1156 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1160 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1164 ret = i915_gem_check_olr(ring, seqno);
1168 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1169 mutex_unlock(&dev->struct_mutex);
1170 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1171 mutex_lock(&dev->struct_mutex);
1175 return i915_gem_object_wait_rendering__tail(obj, ring);
1179 * Called when user space prepares to use an object with the CPU, either
1180 * through the mmap ioctl's mapping or a GTT mapping.
1183 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1184 struct drm_file *file)
1186 struct drm_i915_gem_set_domain *args = data;
1187 struct drm_i915_gem_object *obj;
1188 uint32_t read_domains = args->read_domains;
1189 uint32_t write_domain = args->write_domain;
1192 /* Only handle setting domains to types used by the CPU. */
1193 if (write_domain & I915_GEM_GPU_DOMAINS)
1196 if (read_domains & I915_GEM_GPU_DOMAINS)
1199 /* Having something in the write domain implies it's in the read
1200 * domain, and only that read domain. Enforce that in the request.
1202 if (write_domain != 0 && read_domains != write_domain)
1205 ret = i915_mutex_lock_interruptible(dev);
1209 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1210 if (&obj->base == NULL) {
1215 /* Try to flush the object off the GPU without holding the lock.
1216 * We will repeat the flush holding the lock in the normal manner
1217 * to catch cases where we are gazumped.
1219 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1223 if (read_domains & I915_GEM_DOMAIN_GTT) {
1224 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1226 /* Silently promote "you're not bound, there was nothing to do"
1227 * to success, since the client was just asking us to
1228 * make sure everything was done.
1233 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1237 drm_gem_object_unreference(&obj->base);
1239 mutex_unlock(&dev->struct_mutex);
1244 * Called when user space has done writes to this buffer
1247 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1248 struct drm_file *file)
1250 struct drm_i915_gem_sw_finish *args = data;
1251 struct drm_i915_gem_object *obj;
1254 ret = i915_mutex_lock_interruptible(dev);
1258 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1259 if (&obj->base == NULL) {
1264 /* Pinned buffers may be scanout, so flush the cache */
1266 i915_gem_object_flush_cpu_write_domain(obj);
1268 drm_gem_object_unreference(&obj->base);
1270 mutex_unlock(&dev->struct_mutex);
1275 * Maps the contents of an object, returning the address it is mapped
1278 * While the mapping holds a reference on the contents of the object, it doesn't
1279 * imply a ref on the object itself.
1282 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1283 struct drm_file *file)
1285 struct drm_i915_gem_mmap *args = data;
1286 struct drm_gem_object *obj;
1289 obj = drm_gem_object_lookup(dev, file, args->handle);
1293 /* prime objects have no backing filp to GEM mmap
1297 drm_gem_object_unreference_unlocked(obj);
1301 addr = vm_mmap(obj->filp, 0, args->size,
1302 PROT_READ | PROT_WRITE, MAP_SHARED,
1304 drm_gem_object_unreference_unlocked(obj);
1305 if (IS_ERR((void *)addr))
1308 args->addr_ptr = (uint64_t) addr;
1314 * i915_gem_fault - fault a page into the GTT
1315 * vma: VMA in question
1318 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1319 * from userspace. The fault handler takes care of binding the object to
1320 * the GTT (if needed), allocating and programming a fence register (again,
1321 * only if needed based on whether the old reg is still valid or the object
1322 * is tiled) and inserting a new PTE into the faulting process.
1324 * Note that the faulting process may involve evicting existing objects
1325 * from the GTT and/or fence registers to make room. So performance may
1326 * suffer if the GTT working set is large or there are few fence registers
1329 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1331 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1332 struct drm_device *dev = obj->base.dev;
1333 drm_i915_private_t *dev_priv = dev->dev_private;
1334 pgoff_t page_offset;
1337 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1339 /* We don't use vmf->pgoff since that has the fake offset */
1340 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1343 ret = i915_mutex_lock_interruptible(dev);
1347 trace_i915_gem_object_fault(obj, page_offset, true, write);
1349 /* Access to snoopable pages through the GTT is incoherent. */
1350 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1355 /* Now bind it into the GTT if needed */
1356 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1360 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1364 ret = i915_gem_object_get_fence(obj);
1368 obj->fault_mappable = true;
1370 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1374 /* Finally, remap it using the new GTT offset */
1375 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1377 i915_gem_object_unpin(obj);
1379 mutex_unlock(&dev->struct_mutex);
1383 /* If this -EIO is due to a gpu hang, give the reset code a
1384 * chance to clean up the mess. Otherwise return the proper
1386 if (i915_terminally_wedged(&dev_priv->gpu_error))
1387 return VM_FAULT_SIGBUS;
1389 /* Give the error handler a chance to run and move the
1390 * objects off the GPU active list. Next time we service the
1391 * fault, we should be able to transition the page into the
1392 * GTT without touching the GPU (and so avoid further
1393 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1394 * with coherency, just lost writes.
1402 * EBUSY is ok: this just means that another thread
1403 * already did the job.
1405 return VM_FAULT_NOPAGE;
1407 return VM_FAULT_OOM;
1409 return VM_FAULT_SIGBUS;
1411 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1412 return VM_FAULT_SIGBUS;
1417 * i915_gem_release_mmap - remove physical page mappings
1418 * @obj: obj in question
1420 * Preserve the reservation of the mmapping with the DRM core code, but
1421 * relinquish ownership of the pages back to the system.
1423 * It is vital that we remove the page mapping if we have mapped a tiled
1424 * object through the GTT and then lose the fence register due to
1425 * resource pressure. Similarly if the object has been moved out of the
1426 * aperture, than pages mapped into userspace must be revoked. Removing the
1427 * mapping will then trigger a page fault on the next user access, allowing
1428 * fixup by i915_gem_fault().
1431 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1433 if (!obj->fault_mappable)
1436 if (obj->base.dev->dev_mapping)
1437 unmap_mapping_range(obj->base.dev->dev_mapping,
1438 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1441 obj->fault_mappable = false;
1445 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1449 if (INTEL_INFO(dev)->gen >= 4 ||
1450 tiling_mode == I915_TILING_NONE)
1453 /* Previous chips need a power-of-two fence region when tiling */
1454 if (INTEL_INFO(dev)->gen == 3)
1455 gtt_size = 1024*1024;
1457 gtt_size = 512*1024;
1459 while (gtt_size < size)
1466 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1467 * @obj: object to check
1469 * Return the required GTT alignment for an object, taking into account
1470 * potential fence register mapping.
1473 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1474 int tiling_mode, bool fenced)
1477 * Minimum alignment is 4k (GTT page size), but might be greater
1478 * if a fence register is needed for the object.
1480 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1481 tiling_mode == I915_TILING_NONE)
1485 * Previous chips need to be aligned to the size of the smallest
1486 * fence register that can contain the object.
1488 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1491 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1493 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1496 if (obj->base.map_list.map)
1499 dev_priv->mm.shrinker_no_lock_stealing = true;
1501 ret = drm_gem_create_mmap_offset(&obj->base);
1505 /* Badly fragmented mmap space? The only way we can recover
1506 * space is by destroying unwanted objects. We can't randomly release
1507 * mmap_offsets as userspace expects them to be persistent for the
1508 * lifetime of the objects. The closest we can is to release the
1509 * offsets on purgeable objects by truncating it and marking it purged,
1510 * which prevents userspace from ever using that object again.
1512 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1513 ret = drm_gem_create_mmap_offset(&obj->base);
1517 i915_gem_shrink_all(dev_priv);
1518 ret = drm_gem_create_mmap_offset(&obj->base);
1520 dev_priv->mm.shrinker_no_lock_stealing = false;
1525 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1527 if (!obj->base.map_list.map)
1530 drm_gem_free_mmap_offset(&obj->base);
1534 i915_gem_mmap_gtt(struct drm_file *file,
1535 struct drm_device *dev,
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 struct drm_i915_gem_object *obj;
1543 ret = i915_mutex_lock_interruptible(dev);
1547 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1548 if (&obj->base == NULL) {
1553 if (obj->base.size > dev_priv->gtt.mappable_end) {
1558 if (obj->madv != I915_MADV_WILLNEED) {
1559 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1564 ret = i915_gem_object_create_mmap_offset(obj);
1568 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1571 drm_gem_object_unreference(&obj->base);
1573 mutex_unlock(&dev->struct_mutex);
1578 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1580 * @data: GTT mapping ioctl data
1581 * @file: GEM object info
1583 * Simply returns the fake offset to userspace so it can mmap it.
1584 * The mmap call will end up in drm_gem_mmap(), which will set things
1585 * up so we can get faults in the handler above.
1587 * The fault handler will take care of binding the object into the GTT
1588 * (since it may have been evicted to make room for something), allocating
1589 * a fence register, and mapping the appropriate aperture address into
1593 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1594 struct drm_file *file)
1596 struct drm_i915_gem_mmap_gtt *args = data;
1598 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1601 /* Immediately discard the backing storage */
1603 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1605 struct inode *inode;
1607 i915_gem_object_free_mmap_offset(obj);
1609 if (obj->base.filp == NULL)
1612 /* Our goal here is to return as much of the memory as
1613 * is possible back to the system as we are called from OOM.
1614 * To do this we must instruct the shmfs to drop all of its
1615 * backing pages, *now*.
1617 inode = file_inode(obj->base.filp);
1618 shmem_truncate_range(inode, 0, (loff_t)-1);
1620 obj->madv = __I915_MADV_PURGED;
1624 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1626 return obj->madv == I915_MADV_DONTNEED;
1630 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1632 struct sg_page_iter sg_iter;
1635 BUG_ON(obj->madv == __I915_MADV_PURGED);
1637 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1639 /* In the event of a disaster, abandon all caches and
1640 * hope for the best.
1642 WARN_ON(ret != -EIO);
1643 i915_gem_clflush_object(obj);
1644 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1647 if (i915_gem_object_needs_bit17_swizzle(obj))
1648 i915_gem_object_save_bit_17_swizzle(obj);
1650 if (obj->madv == I915_MADV_DONTNEED)
1653 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1654 struct page *page = sg_page_iter_page(&sg_iter);
1657 set_page_dirty(page);
1659 if (obj->madv == I915_MADV_WILLNEED)
1660 mark_page_accessed(page);
1662 page_cache_release(page);
1666 sg_free_table(obj->pages);
1671 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1673 const struct drm_i915_gem_object_ops *ops = obj->ops;
1675 if (obj->pages == NULL)
1678 if (obj->pages_pin_count)
1681 BUG_ON(i915_gem_obj_bound_any(obj));
1683 /* ->put_pages might need to allocate memory for the bit17 swizzle
1684 * array, hence protect them from being reaped by removing them from gtt
1686 list_del(&obj->global_list);
1688 ops->put_pages(obj);
1691 if (i915_gem_object_is_purgeable(obj))
1692 i915_gem_object_truncate(obj);
1698 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1699 bool purgeable_only)
1701 struct drm_i915_gem_object *obj, *next;
1704 list_for_each_entry_safe(obj, next,
1705 &dev_priv->mm.unbound_list,
1707 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1708 i915_gem_object_put_pages(obj) == 0) {
1709 count += obj->base.size >> PAGE_SHIFT;
1710 if (count >= target)
1715 list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
1717 struct i915_vma *vma, *v;
1719 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1722 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1723 if (i915_vma_unbind(vma))
1726 if (!i915_gem_object_put_pages(obj)) {
1727 count += obj->base.size >> PAGE_SHIFT;
1728 if (count >= target)
1737 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1739 return __i915_gem_shrink(dev_priv, target, true);
1743 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1745 struct drm_i915_gem_object *obj, *next;
1747 i915_gem_evict_everything(dev_priv->dev);
1749 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1751 i915_gem_object_put_pages(obj);
1755 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1757 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1759 struct address_space *mapping;
1760 struct sg_table *st;
1761 struct scatterlist *sg;
1762 struct sg_page_iter sg_iter;
1764 unsigned long last_pfn = 0; /* suppress gcc warning */
1767 /* Assert that the object is not currently in any GPU domain. As it
1768 * wasn't in the GTT, there shouldn't be any way it could have been in
1771 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1772 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1774 st = kmalloc(sizeof(*st), GFP_KERNEL);
1778 page_count = obj->base.size / PAGE_SIZE;
1779 if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
1785 /* Get the list of pages out of our struct file. They'll be pinned
1786 * at this point until we release them.
1788 * Fail silently without starting the shrinker
1790 mapping = file_inode(obj->base.filp)->i_mapping;
1791 gfp = mapping_gfp_mask(mapping);
1792 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1793 gfp &= ~(__GFP_IO | __GFP_WAIT);
1796 for (i = 0; i < page_count; i++) {
1797 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1799 i915_gem_purge(dev_priv, page_count);
1800 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1803 /* We've tried hard to allocate the memory by reaping
1804 * our own buffer, now let the real VM do its job and
1805 * go down in flames if truly OOM.
1807 gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD);
1808 gfp |= __GFP_IO | __GFP_WAIT;
1810 i915_gem_shrink_all(dev_priv);
1811 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
1815 gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
1816 gfp &= ~(__GFP_IO | __GFP_WAIT);
1818 #ifdef CONFIG_SWIOTLB
1819 if (swiotlb_nr_tbl()) {
1821 sg_set_page(sg, page, PAGE_SIZE, 0);
1826 if (!i || page_to_pfn(page) != last_pfn + 1) {
1830 sg_set_page(sg, page, PAGE_SIZE, 0);
1832 sg->length += PAGE_SIZE;
1834 last_pfn = page_to_pfn(page);
1836 #ifdef CONFIG_SWIOTLB
1837 if (!swiotlb_nr_tbl())
1842 if (i915_gem_object_needs_bit17_swizzle(obj))
1843 i915_gem_object_do_bit_17_swizzle(obj);
1849 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
1850 page_cache_release(sg_page_iter_page(&sg_iter));
1853 return PTR_ERR(page);
1856 /* Ensure that the associated pages are gathered from the backing storage
1857 * and pinned into our object. i915_gem_object_get_pages() may be called
1858 * multiple times before they are released by a single call to
1859 * i915_gem_object_put_pages() - once the pages are no longer referenced
1860 * either as a result of memory pressure (reaping pages under the shrinker)
1861 * or as the object is itself released.
1864 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1866 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1867 const struct drm_i915_gem_object_ops *ops = obj->ops;
1873 if (obj->madv != I915_MADV_WILLNEED) {
1874 DRM_ERROR("Attempting to obtain a purgeable object\n");
1878 BUG_ON(obj->pages_pin_count);
1880 ret = ops->get_pages(obj);
1884 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
1889 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1890 struct intel_ring_buffer *ring)
1892 struct drm_device *dev = obj->base.dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 u32 seqno = intel_ring_get_seqno(ring);
1896 BUG_ON(ring == NULL);
1897 if (obj->ring != ring && obj->last_write_seqno) {
1898 /* Keep the seqno relative to the current ring */
1899 obj->last_write_seqno = seqno;
1903 /* Add a reference if we're newly entering the active list. */
1905 drm_gem_object_reference(&obj->base);
1909 list_move_tail(&obj->ring_list, &ring->active_list);
1911 obj->last_read_seqno = seqno;
1913 if (obj->fenced_gpu_access) {
1914 obj->last_fenced_seqno = seqno;
1916 /* Bump MRU to take account of the delayed flush */
1917 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1918 struct drm_i915_fence_reg *reg;
1920 reg = &dev_priv->fence_regs[obj->fence_reg];
1921 list_move_tail(®->lru_list,
1922 &dev_priv->mm.fence_list);
1928 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1930 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1931 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1932 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1934 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
1935 BUG_ON(!obj->active);
1937 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
1939 list_del_init(&obj->ring_list);
1942 obj->last_read_seqno = 0;
1943 obj->last_write_seqno = 0;
1944 obj->base.write_domain = 0;
1946 obj->last_fenced_seqno = 0;
1947 obj->fenced_gpu_access = false;
1950 drm_gem_object_unreference(&obj->base);
1952 WARN_ON(i915_verify_lists(dev));
1956 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
1958 struct drm_i915_private *dev_priv = dev->dev_private;
1959 struct intel_ring_buffer *ring;
1962 /* Carefully retire all requests without writing to the rings */
1963 for_each_ring(ring, dev_priv, i) {
1964 ret = intel_ring_idle(ring);
1968 i915_gem_retire_requests(dev);
1970 /* Finally reset hw state */
1971 for_each_ring(ring, dev_priv, i) {
1972 intel_ring_init_seqno(ring, seqno);
1974 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
1975 ring->sync_seqno[j] = 0;
1981 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1989 /* HWS page needs to be set less than what we
1990 * will inject to ring
1992 ret = i915_gem_init_seqno(dev, seqno - 1);
1996 /* Carefully set the last_seqno value so that wrap
1997 * detection still works
1999 dev_priv->next_seqno = seqno;
2000 dev_priv->last_seqno = seqno - 1;
2001 if (dev_priv->last_seqno == 0)
2002 dev_priv->last_seqno--;
2008 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2012 /* reserve 0 for non-seqno */
2013 if (dev_priv->next_seqno == 0) {
2014 int ret = i915_gem_init_seqno(dev, 0);
2018 dev_priv->next_seqno = 1;
2021 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2025 int __i915_add_request(struct intel_ring_buffer *ring,
2026 struct drm_file *file,
2027 struct drm_i915_gem_object *obj,
2030 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2031 struct drm_i915_gem_request *request;
2032 u32 request_ring_position, request_start;
2036 request_start = intel_ring_get_tail(ring);
2038 * Emit any outstanding flushes - execbuf can fail to emit the flush
2039 * after having emitted the batchbuffer command. Hence we need to fix
2040 * things up similar to emitting the lazy request. The difference here
2041 * is that the flush _must_ happen before the next request, no matter
2044 ret = intel_ring_flush_all_caches(ring);
2048 request = kmalloc(sizeof(*request), GFP_KERNEL);
2049 if (request == NULL)
2053 /* Record the position of the start of the request so that
2054 * should we detect the updated seqno part-way through the
2055 * GPU processing the request, we never over-estimate the
2056 * position of the head.
2058 request_ring_position = intel_ring_get_tail(ring);
2060 ret = ring->add_request(ring);
2066 request->seqno = intel_ring_get_seqno(ring);
2067 request->ring = ring;
2068 request->head = request_start;
2069 request->tail = request_ring_position;
2070 request->ctx = ring->last_context;
2071 request->batch_obj = obj;
2073 /* Whilst this request exists, batch_obj will be on the
2074 * active_list, and so will hold the active reference. Only when this
2075 * request is retired will the the batch_obj be moved onto the
2076 * inactive_list and lose its active reference. Hence we do not need
2077 * to explicitly hold another reference here.
2081 i915_gem_context_reference(request->ctx);
2083 request->emitted_jiffies = jiffies;
2084 was_empty = list_empty(&ring->request_list);
2085 list_add_tail(&request->list, &ring->request_list);
2086 request->file_priv = NULL;
2089 struct drm_i915_file_private *file_priv = file->driver_priv;
2091 spin_lock(&file_priv->mm.lock);
2092 request->file_priv = file_priv;
2093 list_add_tail(&request->client_list,
2094 &file_priv->mm.request_list);
2095 spin_unlock(&file_priv->mm.lock);
2098 trace_i915_gem_request_add(ring, request->seqno);
2099 ring->outstanding_lazy_request = 0;
2101 if (!dev_priv->ums.mm_suspended) {
2102 i915_queue_hangcheck(ring->dev);
2105 queue_delayed_work(dev_priv->wq,
2106 &dev_priv->mm.retire_work,
2107 round_jiffies_up_relative(HZ));
2108 intel_mark_busy(dev_priv->dev);
2113 *out_seqno = request->seqno;
2118 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2120 struct drm_i915_file_private *file_priv = request->file_priv;
2125 spin_lock(&file_priv->mm.lock);
2126 if (request->file_priv) {
2127 list_del(&request->client_list);
2128 request->file_priv = NULL;
2130 spin_unlock(&file_priv->mm.lock);
2133 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2134 struct i915_address_space *vm)
2136 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2137 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2143 static bool i915_head_inside_request(const u32 acthd_unmasked,
2144 const u32 request_start,
2145 const u32 request_end)
2147 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2149 if (request_start < request_end) {
2150 if (acthd >= request_start && acthd < request_end)
2152 } else if (request_start > request_end) {
2153 if (acthd >= request_start || acthd < request_end)
2160 static struct i915_address_space *
2161 request_to_vm(struct drm_i915_gem_request *request)
2163 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2164 struct i915_address_space *vm;
2166 vm = &dev_priv->gtt.base;
2171 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2172 const u32 acthd, bool *inside)
2174 /* There is a possibility that unmasked head address
2175 * pointing inside the ring, matches the batch_obj address range.
2176 * However this is extremely unlikely.
2178 if (request->batch_obj) {
2179 if (i915_head_inside_object(acthd, request->batch_obj,
2180 request_to_vm(request))) {
2186 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2194 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2195 struct drm_i915_gem_request *request,
2198 struct i915_ctx_hang_stats *hs = NULL;
2199 bool inside, guilty;
2200 unsigned long offset = 0;
2202 /* Innocent until proven guilty */
2205 if (request->batch_obj)
2206 offset = i915_gem_obj_offset(request->batch_obj,
2207 request_to_vm(request));
2209 if (ring->hangcheck.action != wait &&
2210 i915_request_guilty(request, acthd, &inside)) {
2211 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2213 inside ? "inside" : "flushing",
2215 request->ctx ? request->ctx->id : 0,
2221 /* If contexts are disabled or this is the default context, use
2222 * file_priv->reset_state
2224 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2225 hs = &request->ctx->hang_stats;
2226 else if (request->file_priv)
2227 hs = &request->file_priv->hang_stats;
2233 hs->batch_pending++;
2237 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2239 list_del(&request->list);
2240 i915_gem_request_remove_from_client(request);
2243 i915_gem_context_unreference(request->ctx);
2248 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2249 struct intel_ring_buffer *ring)
2251 u32 completed_seqno;
2254 acthd = intel_ring_get_active_head(ring);
2255 completed_seqno = ring->get_seqno(ring, false);
2257 while (!list_empty(&ring->request_list)) {
2258 struct drm_i915_gem_request *request;
2260 request = list_first_entry(&ring->request_list,
2261 struct drm_i915_gem_request,
2264 if (request->seqno > completed_seqno)
2265 i915_set_reset_status(ring, request, acthd);
2267 i915_gem_free_request(request);
2270 while (!list_empty(&ring->active_list)) {
2271 struct drm_i915_gem_object *obj;
2273 obj = list_first_entry(&ring->active_list,
2274 struct drm_i915_gem_object,
2277 i915_gem_object_move_to_inactive(obj);
2281 void i915_gem_restore_fences(struct drm_device *dev)
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2286 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2287 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2290 * Commit delayed tiling changes if we have an object still
2291 * attached to the fence, otherwise just clear the fence.
2294 i915_gem_object_update_fence(reg->obj, reg,
2295 reg->obj->tiling_mode);
2297 i915_gem_write_fence(dev, i, NULL);
2302 void i915_gem_reset(struct drm_device *dev)
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct intel_ring_buffer *ring;
2308 for_each_ring(ring, dev_priv, i)
2309 i915_gem_reset_ring_lists(dev_priv, ring);
2311 i915_gem_restore_fences(dev);
2315 * This function clears the request list as sequence numbers are passed.
2318 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2322 if (list_empty(&ring->request_list))
2325 WARN_ON(i915_verify_lists(ring->dev));
2327 seqno = ring->get_seqno(ring, true);
2329 while (!list_empty(&ring->request_list)) {
2330 struct drm_i915_gem_request *request;
2332 request = list_first_entry(&ring->request_list,
2333 struct drm_i915_gem_request,
2336 if (!i915_seqno_passed(seqno, request->seqno))
2339 trace_i915_gem_request_retire(ring, request->seqno);
2340 /* We know the GPU must have read the request to have
2341 * sent us the seqno + interrupt, so use the position
2342 * of tail of the request to update the last known position
2345 ring->last_retired_head = request->tail;
2347 i915_gem_free_request(request);
2350 /* Move any buffers on the active list that are no longer referenced
2351 * by the ringbuffer to the flushing/inactive lists as appropriate.
2353 while (!list_empty(&ring->active_list)) {
2354 struct drm_i915_gem_object *obj;
2356 obj = list_first_entry(&ring->active_list,
2357 struct drm_i915_gem_object,
2360 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2363 i915_gem_object_move_to_inactive(obj);
2366 if (unlikely(ring->trace_irq_seqno &&
2367 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2368 ring->irq_put(ring);
2369 ring->trace_irq_seqno = 0;
2372 WARN_ON(i915_verify_lists(ring->dev));
2376 i915_gem_retire_requests(struct drm_device *dev)
2378 drm_i915_private_t *dev_priv = dev->dev_private;
2379 struct intel_ring_buffer *ring;
2382 for_each_ring(ring, dev_priv, i)
2383 i915_gem_retire_requests_ring(ring);
2387 i915_gem_retire_work_handler(struct work_struct *work)
2389 drm_i915_private_t *dev_priv;
2390 struct drm_device *dev;
2391 struct intel_ring_buffer *ring;
2395 dev_priv = container_of(work, drm_i915_private_t,
2396 mm.retire_work.work);
2397 dev = dev_priv->dev;
2399 /* Come back later if the device is busy... */
2400 if (!mutex_trylock(&dev->struct_mutex)) {
2401 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2402 round_jiffies_up_relative(HZ));
2406 i915_gem_retire_requests(dev);
2408 /* Send a periodic flush down the ring so we don't hold onto GEM
2409 * objects indefinitely.
2412 for_each_ring(ring, dev_priv, i) {
2413 if (ring->gpu_caches_dirty)
2414 i915_add_request(ring, NULL);
2416 idle &= list_empty(&ring->request_list);
2419 if (!dev_priv->ums.mm_suspended && !idle)
2420 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2421 round_jiffies_up_relative(HZ));
2423 intel_mark_idle(dev);
2425 mutex_unlock(&dev->struct_mutex);
2429 * Ensures that an object will eventually get non-busy by flushing any required
2430 * write domains, emitting any outstanding lazy request and retiring and
2431 * completed requests.
2434 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2439 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2443 i915_gem_retire_requests_ring(obj->ring);
2450 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2451 * @DRM_IOCTL_ARGS: standard ioctl arguments
2453 * Returns 0 if successful, else an error is returned with the remaining time in
2454 * the timeout parameter.
2455 * -ETIME: object is still busy after timeout
2456 * -ERESTARTSYS: signal interrupted the wait
2457 * -ENONENT: object doesn't exist
2458 * Also possible, but rare:
2459 * -EAGAIN: GPU wedged
2461 * -ENODEV: Internal IRQ fail
2462 * -E?: The add request failed
2464 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2465 * non-zero timeout parameter the wait ioctl will wait for the given number of
2466 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2467 * without holding struct_mutex the object may become re-busied before this
2468 * function completes. A similar but shorter * race condition exists in the busy
2472 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2474 drm_i915_private_t *dev_priv = dev->dev_private;
2475 struct drm_i915_gem_wait *args = data;
2476 struct drm_i915_gem_object *obj;
2477 struct intel_ring_buffer *ring = NULL;
2478 struct timespec timeout_stack, *timeout = NULL;
2479 unsigned reset_counter;
2483 if (args->timeout_ns >= 0) {
2484 timeout_stack = ns_to_timespec(args->timeout_ns);
2485 timeout = &timeout_stack;
2488 ret = i915_mutex_lock_interruptible(dev);
2492 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2493 if (&obj->base == NULL) {
2494 mutex_unlock(&dev->struct_mutex);
2498 /* Need to make sure the object gets inactive eventually. */
2499 ret = i915_gem_object_flush_active(obj);
2504 seqno = obj->last_read_seqno;
2511 /* Do this after OLR check to make sure we make forward progress polling
2512 * on this IOCTL with a 0 timeout (like busy ioctl)
2514 if (!args->timeout_ns) {
2519 drm_gem_object_unreference(&obj->base);
2520 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2521 mutex_unlock(&dev->struct_mutex);
2523 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2525 args->timeout_ns = timespec_to_ns(timeout);
2529 drm_gem_object_unreference(&obj->base);
2530 mutex_unlock(&dev->struct_mutex);
2535 * i915_gem_object_sync - sync an object to a ring.
2537 * @obj: object which may be in use on another ring.
2538 * @to: ring we wish to use the object on. May be NULL.
2540 * This code is meant to abstract object synchronization with the GPU.
2541 * Calling with NULL implies synchronizing the object with the CPU
2542 * rather than a particular GPU ring.
2544 * Returns 0 if successful, else propagates up the lower layer error.
2547 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2548 struct intel_ring_buffer *to)
2550 struct intel_ring_buffer *from = obj->ring;
2554 if (from == NULL || to == from)
2557 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2558 return i915_gem_object_wait_rendering(obj, false);
2560 idx = intel_ring_sync_index(from, to);
2562 seqno = obj->last_read_seqno;
2563 if (seqno <= from->sync_seqno[idx])
2566 ret = i915_gem_check_olr(obj->ring, seqno);
2570 ret = to->sync_to(to, from, seqno);
2572 /* We use last_read_seqno because sync_to()
2573 * might have just caused seqno wrap under
2576 from->sync_seqno[idx] = obj->last_read_seqno;
2581 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2583 u32 old_write_domain, old_read_domains;
2585 /* Force a pagefault for domain tracking on next user access */
2586 i915_gem_release_mmap(obj);
2588 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2591 /* Wait for any direct GTT access to complete */
2594 old_read_domains = obj->base.read_domains;
2595 old_write_domain = obj->base.write_domain;
2597 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2598 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2600 trace_i915_gem_object_change_domain(obj,
2605 int i915_vma_unbind(struct i915_vma *vma)
2607 struct drm_i915_gem_object *obj = vma->obj;
2608 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2611 if (list_empty(&vma->vma_link))
2617 BUG_ON(obj->pages == NULL);
2619 ret = i915_gem_object_finish_gpu(obj);
2622 /* Continue on if we fail due to EIO, the GPU is hung so we
2623 * should be safe and we need to cleanup or else we might
2624 * cause memory corruption through use-after-free.
2627 i915_gem_object_finish_gtt(obj);
2629 /* release the fence reg _after_ flushing */
2630 ret = i915_gem_object_put_fence(obj);
2634 trace_i915_vma_unbind(vma);
2636 if (obj->has_global_gtt_mapping)
2637 i915_gem_gtt_unbind_object(obj);
2638 if (obj->has_aliasing_ppgtt_mapping) {
2639 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2640 obj->has_aliasing_ppgtt_mapping = 0;
2642 i915_gem_gtt_finish_object(obj);
2643 i915_gem_object_unpin_pages(obj);
2645 list_del(&vma->mm_list);
2646 /* Avoid an unnecessary call to unbind on rebind. */
2647 if (i915_is_ggtt(vma->vm))
2648 obj->map_and_fenceable = true;
2650 drm_mm_remove_node(&vma->node);
2651 i915_gem_vma_destroy(vma);
2653 /* Since the unbound list is global, only move to that list if
2654 * no more VMAs exist.
2655 * NB: Until we have real VMAs there will only ever be one */
2656 WARN_ON(!list_empty(&obj->vma_list));
2657 if (list_empty(&obj->vma_list))
2658 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2664 * Unbinds an object from the global GTT aperture.
2667 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2669 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2670 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2672 if (!i915_gem_obj_ggtt_bound(obj))
2678 BUG_ON(obj->pages == NULL);
2680 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2683 int i915_gpu_idle(struct drm_device *dev)
2685 drm_i915_private_t *dev_priv = dev->dev_private;
2686 struct intel_ring_buffer *ring;
2689 /* Flush everything onto the inactive list. */
2690 for_each_ring(ring, dev_priv, i) {
2691 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2695 ret = intel_ring_idle(ring);
2703 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2704 struct drm_i915_gem_object *obj)
2706 drm_i915_private_t *dev_priv = dev->dev_private;
2708 int fence_pitch_shift;
2710 if (INTEL_INFO(dev)->gen >= 6) {
2711 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2712 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2714 fence_reg = FENCE_REG_965_0;
2715 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2718 fence_reg += reg * 8;
2720 /* To w/a incoherency with non-atomic 64-bit register updates,
2721 * we split the 64-bit update into two 32-bit writes. In order
2722 * for a partial fence not to be evaluated between writes, we
2723 * precede the update with write to turn off the fence register,
2724 * and only enable the fence as the last step.
2726 * For extra levels of paranoia, we make sure each step lands
2727 * before applying the next step.
2729 I915_WRITE(fence_reg, 0);
2730 POSTING_READ(fence_reg);
2733 u32 size = i915_gem_obj_ggtt_size(obj);
2736 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2738 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2739 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2740 if (obj->tiling_mode == I915_TILING_Y)
2741 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2742 val |= I965_FENCE_REG_VALID;
2744 I915_WRITE(fence_reg + 4, val >> 32);
2745 POSTING_READ(fence_reg + 4);
2747 I915_WRITE(fence_reg + 0, val);
2748 POSTING_READ(fence_reg);
2750 I915_WRITE(fence_reg + 4, 0);
2751 POSTING_READ(fence_reg + 4);
2755 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2756 struct drm_i915_gem_object *obj)
2758 drm_i915_private_t *dev_priv = dev->dev_private;
2762 u32 size = i915_gem_obj_ggtt_size(obj);
2766 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2767 (size & -size) != size ||
2768 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2769 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2770 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2772 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2777 /* Note: pitch better be a power of two tile widths */
2778 pitch_val = obj->stride / tile_width;
2779 pitch_val = ffs(pitch_val) - 1;
2781 val = i915_gem_obj_ggtt_offset(obj);
2782 if (obj->tiling_mode == I915_TILING_Y)
2783 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2784 val |= I915_FENCE_SIZE_BITS(size);
2785 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2786 val |= I830_FENCE_REG_VALID;
2791 reg = FENCE_REG_830_0 + reg * 4;
2793 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2795 I915_WRITE(reg, val);
2799 static void i830_write_fence_reg(struct drm_device *dev, int reg,
2800 struct drm_i915_gem_object *obj)
2802 drm_i915_private_t *dev_priv = dev->dev_private;
2806 u32 size = i915_gem_obj_ggtt_size(obj);
2809 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
2810 (size & -size) != size ||
2811 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2812 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2813 i915_gem_obj_ggtt_offset(obj), size);
2815 pitch_val = obj->stride / 128;
2816 pitch_val = ffs(pitch_val) - 1;
2818 val = i915_gem_obj_ggtt_offset(obj);
2819 if (obj->tiling_mode == I915_TILING_Y)
2820 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2821 val |= I830_FENCE_SIZE_BITS(size);
2822 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2823 val |= I830_FENCE_REG_VALID;
2827 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2828 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2831 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2833 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2836 static void i915_gem_write_fence(struct drm_device *dev, int reg,
2837 struct drm_i915_gem_object *obj)
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2841 /* Ensure that all CPU reads are completed before installing a fence
2842 * and all writes before removing the fence.
2844 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2847 WARN(obj && (!obj->stride || !obj->tiling_mode),
2848 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2849 obj->stride, obj->tiling_mode);
2851 switch (INTEL_INFO(dev)->gen) {
2855 case 4: i965_write_fence_reg(dev, reg, obj); break;
2856 case 3: i915_write_fence_reg(dev, reg, obj); break;
2857 case 2: i830_write_fence_reg(dev, reg, obj); break;
2861 /* And similarly be paranoid that no direct access to this region
2862 * is reordered to before the fence is installed.
2864 if (i915_gem_object_needs_mb(obj))
2868 static inline int fence_number(struct drm_i915_private *dev_priv,
2869 struct drm_i915_fence_reg *fence)
2871 return fence - dev_priv->fence_regs;
2874 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2875 struct drm_i915_fence_reg *fence,
2878 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2879 int reg = fence_number(dev_priv, fence);
2881 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2884 obj->fence_reg = reg;
2886 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2888 obj->fence_reg = I915_FENCE_REG_NONE;
2890 list_del_init(&fence->lru_list);
2892 obj->fence_dirty = false;
2896 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
2898 if (obj->last_fenced_seqno) {
2899 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
2903 obj->last_fenced_seqno = 0;
2906 obj->fenced_gpu_access = false;
2911 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2913 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2914 struct drm_i915_fence_reg *fence;
2917 ret = i915_gem_object_wait_fence(obj);
2921 if (obj->fence_reg == I915_FENCE_REG_NONE)
2924 fence = &dev_priv->fence_regs[obj->fence_reg];
2926 i915_gem_object_fence_lost(obj);
2927 i915_gem_object_update_fence(obj, fence, false);
2932 static struct drm_i915_fence_reg *
2933 i915_find_fence_reg(struct drm_device *dev)
2935 struct drm_i915_private *dev_priv = dev->dev_private;
2936 struct drm_i915_fence_reg *reg, *avail;
2939 /* First try to find a free reg */
2941 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2942 reg = &dev_priv->fence_regs[i];
2946 if (!reg->pin_count)
2953 /* None available, try to steal one or wait for a user to finish */
2954 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2965 * i915_gem_object_get_fence - set up fencing for an object
2966 * @obj: object to map through a fence reg
2968 * When mapping objects through the GTT, userspace wants to be able to write
2969 * to them without having to worry about swizzling if the object is tiled.
2970 * This function walks the fence regs looking for a free one for @obj,
2971 * stealing one if it can't find any.
2973 * It then sets up the reg based on the object's properties: address, pitch
2974 * and tiling format.
2976 * For an untiled surface, this removes any existing fence.
2979 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2981 struct drm_device *dev = obj->base.dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983 bool enable = obj->tiling_mode != I915_TILING_NONE;
2984 struct drm_i915_fence_reg *reg;
2987 /* Have we updated the tiling parameters upon the object and so
2988 * will need to serialise the write to the associated fence register?
2990 if (obj->fence_dirty) {
2991 ret = i915_gem_object_wait_fence(obj);
2996 /* Just update our place in the LRU if our fence is getting reused. */
2997 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2998 reg = &dev_priv->fence_regs[obj->fence_reg];
2999 if (!obj->fence_dirty) {
3000 list_move_tail(®->lru_list,
3001 &dev_priv->mm.fence_list);
3004 } else if (enable) {
3005 reg = i915_find_fence_reg(dev);
3010 struct drm_i915_gem_object *old = reg->obj;
3012 ret = i915_gem_object_wait_fence(old);
3016 i915_gem_object_fence_lost(old);
3021 i915_gem_object_update_fence(obj, reg, enable);
3026 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3027 struct drm_mm_node *gtt_space,
3028 unsigned long cache_level)
3030 struct drm_mm_node *other;
3032 /* On non-LLC machines we have to be careful when putting differing
3033 * types of snoopable memory together to avoid the prefetcher
3034 * crossing memory domains and dying.
3039 if (!drm_mm_node_allocated(gtt_space))
3042 if (list_empty(>t_space->node_list))
3045 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3046 if (other->allocated && !other->hole_follows && other->color != cache_level)
3049 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3050 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3056 static void i915_gem_verify_gtt(struct drm_device *dev)
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 struct drm_i915_gem_object *obj;
3063 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3064 if (obj->gtt_space == NULL) {
3065 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3070 if (obj->cache_level != obj->gtt_space->color) {
3071 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3072 i915_gem_obj_ggtt_offset(obj),
3073 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3075 obj->gtt_space->color);
3080 if (!i915_gem_valid_gtt_space(dev,
3082 obj->cache_level)) {
3083 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3084 i915_gem_obj_ggtt_offset(obj),
3085 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3097 * Finds free space in the GTT aperture and binds the object there.
3100 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3101 struct i915_address_space *vm,
3103 bool map_and_fenceable,
3106 struct drm_device *dev = obj->base.dev;
3107 drm_i915_private_t *dev_priv = dev->dev_private;
3108 u32 size, fence_size, fence_alignment, unfenced_alignment;
3109 bool mappable, fenceable;
3111 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3112 struct i915_vma *vma;
3115 if (WARN_ON(!list_empty(&obj->vma_list)))
3118 fence_size = i915_gem_get_gtt_size(dev,
3121 fence_alignment = i915_gem_get_gtt_alignment(dev,
3123 obj->tiling_mode, true);
3124 unfenced_alignment =
3125 i915_gem_get_gtt_alignment(dev,
3127 obj->tiling_mode, false);
3130 alignment = map_and_fenceable ? fence_alignment :
3132 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3133 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3137 size = map_and_fenceable ? fence_size : obj->base.size;
3139 /* If the object is bigger than the entire aperture, reject it early
3140 * before evicting everything in a vain attempt to find space.
3142 if (obj->base.size > gtt_max) {
3143 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3145 map_and_fenceable ? "mappable" : "total",
3150 ret = i915_gem_object_get_pages(obj);
3154 i915_gem_object_pin_pages(obj);
3156 /* FIXME: For now we only ever use 1 VMA per object */
3157 BUG_ON(!i915_is_ggtt(vm));
3158 WARN_ON(!list_empty(&obj->vma_list));
3160 vma = i915_gem_vma_create(obj, vm);
3167 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3169 obj->cache_level, 0, gtt_max);
3171 ret = i915_gem_evict_something(dev, vm, size, alignment,
3180 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3181 obj->cache_level))) {
3183 goto err_remove_node;
3186 ret = i915_gem_gtt_prepare_object(obj);
3188 goto err_remove_node;
3190 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3191 list_add_tail(&vma->mm_list, &vm->inactive_list);
3195 i915_gem_obj_ggtt_size(obj) == fence_size &&
3196 (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0;
3200 vma->node.start + obj->base.size <= dev_priv->gtt.mappable_end;
3202 /* Map and fenceable only changes if the VM is the global GGTT */
3203 if (i915_is_ggtt(vm))
3204 obj->map_and_fenceable = mappable && fenceable;
3206 trace_i915_vma_bind(vma, map_and_fenceable);
3207 i915_gem_verify_gtt(dev);
3211 drm_mm_remove_node(&vma->node);
3213 i915_gem_vma_destroy(vma);
3215 i915_gem_object_unpin_pages(obj);
3220 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
3222 /* If we don't have a page list set up, then we're not pinned
3223 * to GPU, and we can ignore the cache flush because it'll happen
3224 * again at bind time.
3226 if (obj->pages == NULL)
3230 * Stolen memory is always coherent with the GPU as it is explicitly
3231 * marked as wc by the system, or the system is cache-coherent.
3236 /* If the GPU is snooping the contents of the CPU cache,
3237 * we do not need to manually clear the CPU cache lines. However,
3238 * the caches are only snooped when the render cache is
3239 * flushed/invalidated. As we always have to emit invalidations
3240 * and flushes when moving into and out of the RENDER domain, correct
3241 * snooping behaviour occurs naturally as the result of our domain
3244 if (obj->cache_level != I915_CACHE_NONE)
3247 trace_i915_gem_object_clflush(obj);
3249 drm_clflush_sg(obj->pages);
3252 /** Flushes the GTT write domain for the object if it's dirty. */
3254 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3256 uint32_t old_write_domain;
3258 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3261 /* No actual flushing is required for the GTT write domain. Writes
3262 * to it immediately go to main memory as far as we know, so there's
3263 * no chipset flush. It also doesn't land in render cache.
3265 * However, we do have to enforce the order so that all writes through
3266 * the GTT land before any writes to the device, such as updates to
3271 old_write_domain = obj->base.write_domain;
3272 obj->base.write_domain = 0;
3274 trace_i915_gem_object_change_domain(obj,
3275 obj->base.read_domains,
3279 /** Flushes the CPU write domain for the object if it's dirty. */
3281 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3283 uint32_t old_write_domain;
3285 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3288 i915_gem_clflush_object(obj);
3289 i915_gem_chipset_flush(obj->base.dev);
3290 old_write_domain = obj->base.write_domain;
3291 obj->base.write_domain = 0;
3293 trace_i915_gem_object_change_domain(obj,
3294 obj->base.read_domains,
3299 * Moves a single object to the GTT read, and possibly write domain.
3301 * This function returns when the move is complete, including waiting on
3305 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3307 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3308 uint32_t old_write_domain, old_read_domains;
3311 /* Not valid to be called on unbound objects. */
3312 if (!i915_gem_obj_bound_any(obj))
3315 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3318 ret = i915_gem_object_wait_rendering(obj, !write);
3322 i915_gem_object_flush_cpu_write_domain(obj);
3324 /* Serialise direct access to this object with the barriers for
3325 * coherent writes from the GPU, by effectively invalidating the
3326 * GTT domain upon first access.
3328 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3331 old_write_domain = obj->base.write_domain;
3332 old_read_domains = obj->base.read_domains;
3334 /* It should now be out of any other write domains, and we can update
3335 * the domain values for our changes.
3337 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3338 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3340 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3341 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3345 trace_i915_gem_object_change_domain(obj,
3349 /* And bump the LRU for this access */
3350 if (i915_gem_object_is_inactive(obj)) {
3351 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
3352 &dev_priv->gtt.base);
3354 list_move_tail(&vma->mm_list,
3355 &dev_priv->gtt.base.inactive_list);
3362 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3363 enum i915_cache_level cache_level)
3365 struct drm_device *dev = obj->base.dev;
3366 drm_i915_private_t *dev_priv = dev->dev_private;
3367 struct i915_vma *vma;
3370 if (obj->cache_level == cache_level)
3373 if (obj->pin_count) {
3374 DRM_DEBUG("can not change the cache level of pinned objects\n");
3378 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3379 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3380 ret = i915_vma_unbind(vma);
3388 if (i915_gem_obj_bound_any(obj)) {
3389 ret = i915_gem_object_finish_gpu(obj);
3393 i915_gem_object_finish_gtt(obj);
3395 /* Before SandyBridge, you could not use tiling or fence
3396 * registers with snooped memory, so relinquish any fences
3397 * currently pointing to our region in the aperture.
3399 if (INTEL_INFO(dev)->gen < 6) {
3400 ret = i915_gem_object_put_fence(obj);
3405 if (obj->has_global_gtt_mapping)
3406 i915_gem_gtt_bind_object(obj, cache_level);
3407 if (obj->has_aliasing_ppgtt_mapping)
3408 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3412 if (cache_level == I915_CACHE_NONE) {
3413 u32 old_read_domains, old_write_domain;
3415 /* If we're coming from LLC cached, then we haven't
3416 * actually been tracking whether the data is in the
3417 * CPU cache or not, since we only allow one bit set
3418 * in obj->write_domain and have been skipping the clflushes.
3419 * Just set it to the CPU cache for now.
3421 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3422 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3424 old_read_domains = obj->base.read_domains;
3425 old_write_domain = obj->base.write_domain;
3427 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3428 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3430 trace_i915_gem_object_change_domain(obj,
3435 list_for_each_entry(vma, &obj->vma_list, vma_link)
3436 vma->node.color = cache_level;
3437 obj->cache_level = cache_level;
3438 i915_gem_verify_gtt(dev);
3442 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3443 struct drm_file *file)
3445 struct drm_i915_gem_caching *args = data;
3446 struct drm_i915_gem_object *obj;
3449 ret = i915_mutex_lock_interruptible(dev);
3453 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3454 if (&obj->base == NULL) {
3459 args->caching = obj->cache_level != I915_CACHE_NONE;
3461 drm_gem_object_unreference(&obj->base);
3463 mutex_unlock(&dev->struct_mutex);
3467 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3468 struct drm_file *file)
3470 struct drm_i915_gem_caching *args = data;
3471 struct drm_i915_gem_object *obj;
3472 enum i915_cache_level level;
3475 switch (args->caching) {
3476 case I915_CACHING_NONE:
3477 level = I915_CACHE_NONE;
3479 case I915_CACHING_CACHED:
3480 level = I915_CACHE_LLC;
3486 ret = i915_mutex_lock_interruptible(dev);
3490 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3491 if (&obj->base == NULL) {
3496 ret = i915_gem_object_set_cache_level(obj, level);
3498 drm_gem_object_unreference(&obj->base);
3500 mutex_unlock(&dev->struct_mutex);
3505 * Prepare buffer for display plane (scanout, cursors, etc).
3506 * Can be called from an uninterruptible phase (modesetting) and allows
3507 * any flushes to be pipelined (for pageflips).
3510 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3512 struct intel_ring_buffer *pipelined)
3514 u32 old_read_domains, old_write_domain;
3517 if (pipelined != obj->ring) {
3518 ret = i915_gem_object_sync(obj, pipelined);
3523 /* The display engine is not coherent with the LLC cache on gen6. As
3524 * a result, we make sure that the pinning that is about to occur is
3525 * done with uncached PTEs. This is lowest common denominator for all
3528 * However for gen6+, we could do better by using the GFDT bit instead
3529 * of uncaching, which would allow us to flush all the LLC-cached data
3530 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3532 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3536 /* As the user may map the buffer once pinned in the display plane
3537 * (e.g. libkms for the bootup splash), we have to ensure that we
3538 * always use map_and_fenceable for all scanout buffers.
3540 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3544 i915_gem_object_flush_cpu_write_domain(obj);
3546 old_write_domain = obj->base.write_domain;
3547 old_read_domains = obj->base.read_domains;
3549 /* It should now be out of any other write domains, and we can update
3550 * the domain values for our changes.
3552 obj->base.write_domain = 0;
3553 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3555 trace_i915_gem_object_change_domain(obj,
3563 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3567 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3570 ret = i915_gem_object_wait_rendering(obj, false);
3574 /* Ensure that we invalidate the GPU's caches and TLBs. */
3575 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3580 * Moves a single object to the CPU read, and possibly write domain.
3582 * This function returns when the move is complete, including waiting on
3586 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3588 uint32_t old_write_domain, old_read_domains;
3591 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3594 ret = i915_gem_object_wait_rendering(obj, !write);
3598 i915_gem_object_flush_gtt_write_domain(obj);
3600 old_write_domain = obj->base.write_domain;
3601 old_read_domains = obj->base.read_domains;
3603 /* Flush the CPU cache if it's still invalid. */
3604 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3605 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3606 i915_gem_clflush_object(obj);
3608 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3611 /* It should now be out of any other write domains, and we can update
3612 * the domain values for our changes.
3614 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3616 /* If we're writing through the CPU, then the GPU read domains will
3617 * need to be invalidated at next use.
3620 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3621 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3624 trace_i915_gem_object_change_domain(obj,
3631 /* Throttle our rendering by waiting until the ring has completed our requests
3632 * emitted over 20 msec ago.
3634 * Note that if we were to use the current jiffies each time around the loop,
3635 * we wouldn't escape the function with any frames outstanding if the time to
3636 * render a frame was over 20ms.
3638 * This should get us reasonable parallelism between CPU and GPU but also
3639 * relatively low latency when blocking on a particular request to finish.
3642 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 struct drm_i915_file_private *file_priv = file->driver_priv;
3646 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3647 struct drm_i915_gem_request *request;
3648 struct intel_ring_buffer *ring = NULL;
3649 unsigned reset_counter;
3653 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3657 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3661 spin_lock(&file_priv->mm.lock);
3662 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3663 if (time_after_eq(request->emitted_jiffies, recent_enough))
3666 ring = request->ring;
3667 seqno = request->seqno;
3669 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3670 spin_unlock(&file_priv->mm.lock);
3675 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3677 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3683 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3684 struct i915_address_space *vm,
3686 bool map_and_fenceable,
3689 struct i915_vma *vma;
3692 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3695 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3697 vma = i915_gem_obj_to_vma(obj, vm);
3701 vma->node.start & (alignment - 1)) ||
3702 (map_and_fenceable && !obj->map_and_fenceable)) {
3703 WARN(obj->pin_count,
3704 "bo is already pinned with incorrect alignment:"
3705 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3706 " obj->map_and_fenceable=%d\n",
3707 i915_gem_obj_offset(obj, vm), alignment,
3709 obj->map_and_fenceable);
3710 ret = i915_vma_unbind(vma);
3716 if (!i915_gem_obj_bound(obj, vm)) {
3717 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3719 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
3725 if (!dev_priv->mm.aliasing_ppgtt)
3726 i915_gem_gtt_bind_object(obj, obj->cache_level);
3729 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3730 i915_gem_gtt_bind_object(obj, obj->cache_level);
3733 obj->pin_mappable |= map_and_fenceable;
3739 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3741 BUG_ON(obj->pin_count == 0);
3742 BUG_ON(!i915_gem_obj_bound_any(obj));
3744 if (--obj->pin_count == 0)
3745 obj->pin_mappable = false;
3749 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3750 struct drm_file *file)
3752 struct drm_i915_gem_pin *args = data;
3753 struct drm_i915_gem_object *obj;
3756 ret = i915_mutex_lock_interruptible(dev);
3760 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3761 if (&obj->base == NULL) {
3766 if (obj->madv != I915_MADV_WILLNEED) {
3767 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3772 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3773 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3779 if (obj->user_pin_count == 0) {
3780 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
3785 obj->user_pin_count++;
3786 obj->pin_filp = file;
3788 /* XXX - flush the CPU caches for pinned objects
3789 * as the X server doesn't manage domains yet
3791 i915_gem_object_flush_cpu_write_domain(obj);
3792 args->offset = i915_gem_obj_ggtt_offset(obj);
3794 drm_gem_object_unreference(&obj->base);
3796 mutex_unlock(&dev->struct_mutex);
3801 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3802 struct drm_file *file)
3804 struct drm_i915_gem_pin *args = data;
3805 struct drm_i915_gem_object *obj;
3808 ret = i915_mutex_lock_interruptible(dev);
3812 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3813 if (&obj->base == NULL) {
3818 if (obj->pin_filp != file) {
3819 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3824 obj->user_pin_count--;
3825 if (obj->user_pin_count == 0) {
3826 obj->pin_filp = NULL;
3827 i915_gem_object_unpin(obj);
3831 drm_gem_object_unreference(&obj->base);
3833 mutex_unlock(&dev->struct_mutex);
3838 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3839 struct drm_file *file)
3841 struct drm_i915_gem_busy *args = data;
3842 struct drm_i915_gem_object *obj;
3845 ret = i915_mutex_lock_interruptible(dev);
3849 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3850 if (&obj->base == NULL) {
3855 /* Count all active objects as busy, even if they are currently not used
3856 * by the gpu. Users of this interface expect objects to eventually
3857 * become non-busy without any further actions, therefore emit any
3858 * necessary flushes here.
3860 ret = i915_gem_object_flush_active(obj);
3862 args->busy = obj->active;
3864 BUILD_BUG_ON(I915_NUM_RINGS > 16);
3865 args->busy |= intel_ring_flag(obj->ring) << 16;
3868 drm_gem_object_unreference(&obj->base);
3870 mutex_unlock(&dev->struct_mutex);
3875 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3876 struct drm_file *file_priv)
3878 return i915_gem_ring_throttle(dev, file_priv);
3882 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3883 struct drm_file *file_priv)
3885 struct drm_i915_gem_madvise *args = data;
3886 struct drm_i915_gem_object *obj;
3889 switch (args->madv) {
3890 case I915_MADV_DONTNEED:
3891 case I915_MADV_WILLNEED:
3897 ret = i915_mutex_lock_interruptible(dev);
3901 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3902 if (&obj->base == NULL) {
3907 if (obj->pin_count) {
3912 if (obj->madv != __I915_MADV_PURGED)
3913 obj->madv = args->madv;
3915 /* if the object is no longer attached, discard its backing storage */
3916 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
3917 i915_gem_object_truncate(obj);
3919 args->retained = obj->madv != __I915_MADV_PURGED;
3922 drm_gem_object_unreference(&obj->base);
3924 mutex_unlock(&dev->struct_mutex);
3928 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3929 const struct drm_i915_gem_object_ops *ops)
3931 INIT_LIST_HEAD(&obj->global_list);
3932 INIT_LIST_HEAD(&obj->ring_list);
3933 INIT_LIST_HEAD(&obj->exec_list);
3934 INIT_LIST_HEAD(&obj->vma_list);
3938 obj->fence_reg = I915_FENCE_REG_NONE;
3939 obj->madv = I915_MADV_WILLNEED;
3940 /* Avoid an unnecessary call to unbind on the first bind. */
3941 obj->map_and_fenceable = true;
3943 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
3946 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
3947 .get_pages = i915_gem_object_get_pages_gtt,
3948 .put_pages = i915_gem_object_put_pages_gtt,
3951 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3954 struct drm_i915_gem_object *obj;
3955 struct address_space *mapping;
3958 obj = i915_gem_object_alloc(dev);
3962 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3963 i915_gem_object_free(obj);
3967 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3968 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3969 /* 965gm cannot relocate objects above 4GiB. */
3970 mask &= ~__GFP_HIGHMEM;
3971 mask |= __GFP_DMA32;
3974 mapping = file_inode(obj->base.filp)->i_mapping;
3975 mapping_set_gfp_mask(mapping, mask);
3977 i915_gem_object_init(obj, &i915_gem_object_ops);
3979 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3980 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3983 /* On some devices, we can have the GPU use the LLC (the CPU
3984 * cache) for about a 10% performance improvement
3985 * compared to uncached. Graphics requests other than
3986 * display scanout are coherent with the CPU in
3987 * accessing this cache. This means in this mode we
3988 * don't need to clflush on the CPU side, and on the
3989 * GPU side we only need to flush internal caches to
3990 * get data visible to the CPU.
3992 * However, we maintain the display planes as UC, and so
3993 * need to rebind when first used as such.
3995 obj->cache_level = I915_CACHE_LLC;
3997 obj->cache_level = I915_CACHE_NONE;
3999 trace_i915_gem_object_create(obj);
4004 int i915_gem_init_object(struct drm_gem_object *obj)
4011 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4013 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4014 struct drm_device *dev = obj->base.dev;
4015 drm_i915_private_t *dev_priv = dev->dev_private;
4016 struct i915_vma *vma, *next;
4018 trace_i915_gem_object_destroy(obj);
4021 i915_gem_detach_phys_object(dev, obj);
4024 /* NB: 0 or 1 elements */
4025 WARN_ON(!list_empty(&obj->vma_list) &&
4026 !list_is_singular(&obj->vma_list));
4027 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4028 int ret = i915_vma_unbind(vma);
4029 if (WARN_ON(ret == -ERESTARTSYS)) {
4030 bool was_interruptible;
4032 was_interruptible = dev_priv->mm.interruptible;
4033 dev_priv->mm.interruptible = false;
4035 WARN_ON(i915_vma_unbind(vma));
4037 dev_priv->mm.interruptible = was_interruptible;
4041 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4042 * before progressing. */
4044 i915_gem_object_unpin_pages(obj);
4046 if (WARN_ON(obj->pages_pin_count))
4047 obj->pages_pin_count = 0;
4048 i915_gem_object_put_pages(obj);
4049 i915_gem_object_free_mmap_offset(obj);
4050 i915_gem_object_release_stolen(obj);
4054 if (obj->base.import_attach)
4055 drm_prime_gem_destroy(&obj->base, NULL);
4057 drm_gem_object_release(&obj->base);
4058 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4061 i915_gem_object_free(obj);
4064 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj,
4065 struct i915_address_space *vm)
4067 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4069 return ERR_PTR(-ENOMEM);
4071 INIT_LIST_HEAD(&vma->vma_link);
4072 INIT_LIST_HEAD(&vma->mm_list);
4076 /* Keep GGTT vmas first to make debug easier */
4077 if (i915_is_ggtt(vm))
4078 list_add(&vma->vma_link, &obj->vma_list);
4080 list_add_tail(&vma->vma_link, &obj->vma_list);
4085 void i915_gem_vma_destroy(struct i915_vma *vma)
4087 WARN_ON(vma->node.allocated);
4088 list_del(&vma->vma_link);
4093 i915_gem_idle(struct drm_device *dev)
4095 drm_i915_private_t *dev_priv = dev->dev_private;
4098 if (dev_priv->ums.mm_suspended) {
4099 mutex_unlock(&dev->struct_mutex);
4103 ret = i915_gpu_idle(dev);
4105 mutex_unlock(&dev->struct_mutex);
4108 i915_gem_retire_requests(dev);
4110 /* Under UMS, be paranoid and evict. */
4111 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4112 i915_gem_evict_everything(dev);
4114 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4116 i915_kernel_lost_context(dev);
4117 i915_gem_cleanup_ringbuffer(dev);
4119 /* Cancel the retire work handler, which should be idle now. */
4120 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4125 void i915_gem_l3_remap(struct drm_device *dev)
4127 drm_i915_private_t *dev_priv = dev->dev_private;
4131 if (!HAS_L3_GPU_CACHE(dev))
4134 if (!dev_priv->l3_parity.remap_info)
4137 misccpctl = I915_READ(GEN7_MISCCPCTL);
4138 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
4139 POSTING_READ(GEN7_MISCCPCTL);
4141 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4142 u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
4143 if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
4144 DRM_DEBUG("0x%x was already programmed to %x\n",
4145 GEN7_L3LOG_BASE + i, remap);
4146 if (remap && !dev_priv->l3_parity.remap_info[i/4])
4147 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4148 I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
4151 /* Make sure all the writes land before disabling dop clock gating */
4152 POSTING_READ(GEN7_L3LOG_BASE);
4154 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
4157 void i915_gem_init_swizzling(struct drm_device *dev)
4159 drm_i915_private_t *dev_priv = dev->dev_private;
4161 if (INTEL_INFO(dev)->gen < 5 ||
4162 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4165 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4166 DISP_TILE_SURFACE_SWIZZLING);
4171 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4173 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4174 else if (IS_GEN7(dev))
4175 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4181 intel_enable_blt(struct drm_device *dev)
4186 /* The blitter was dysfunctional on early prototypes */
4187 if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4188 DRM_INFO("BLT not supported on this pre-production hardware;"
4189 " graphics performance will be degraded.\n");
4196 static int i915_gem_init_rings(struct drm_device *dev)
4198 struct drm_i915_private *dev_priv = dev->dev_private;
4201 ret = intel_init_render_ring_buffer(dev);
4206 ret = intel_init_bsd_ring_buffer(dev);
4208 goto cleanup_render_ring;
4211 if (intel_enable_blt(dev)) {
4212 ret = intel_init_blt_ring_buffer(dev);
4214 goto cleanup_bsd_ring;
4217 if (HAS_VEBOX(dev)) {
4218 ret = intel_init_vebox_ring_buffer(dev);
4220 goto cleanup_blt_ring;
4224 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4226 goto cleanup_vebox_ring;
4231 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4233 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4235 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4236 cleanup_render_ring:
4237 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4243 i915_gem_init_hw(struct drm_device *dev)
4245 drm_i915_private_t *dev_priv = dev->dev_private;
4248 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4251 if (dev_priv->ellc_size)
4252 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4254 if (HAS_PCH_NOP(dev)) {
4255 u32 temp = I915_READ(GEN7_MSG_CTL);
4256 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4257 I915_WRITE(GEN7_MSG_CTL, temp);
4260 i915_gem_l3_remap(dev);
4262 i915_gem_init_swizzling(dev);
4264 ret = i915_gem_init_rings(dev);
4269 * XXX: There was some w/a described somewhere suggesting loading
4270 * contexts before PPGTT.
4272 i915_gem_context_init(dev);
4273 if (dev_priv->mm.aliasing_ppgtt) {
4274 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4276 i915_gem_cleanup_aliasing_ppgtt(dev);
4277 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4284 int i915_gem_init(struct drm_device *dev)
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4289 mutex_lock(&dev->struct_mutex);
4291 if (IS_VALLEYVIEW(dev)) {
4292 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4293 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4294 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4295 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4298 i915_gem_init_global_gtt(dev);
4300 ret = i915_gem_init_hw(dev);
4301 mutex_unlock(&dev->struct_mutex);
4303 i915_gem_cleanup_aliasing_ppgtt(dev);
4307 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4308 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4309 dev_priv->dri1.allow_batchbuffer = 1;
4314 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4316 drm_i915_private_t *dev_priv = dev->dev_private;
4317 struct intel_ring_buffer *ring;
4320 for_each_ring(ring, dev_priv, i)
4321 intel_cleanup_ring_buffer(ring);
4325 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4326 struct drm_file *file_priv)
4328 struct drm_i915_private *dev_priv = dev->dev_private;
4331 if (drm_core_check_feature(dev, DRIVER_MODESET))
4334 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4335 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4336 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4339 mutex_lock(&dev->struct_mutex);
4340 dev_priv->ums.mm_suspended = 0;
4342 ret = i915_gem_init_hw(dev);
4344 mutex_unlock(&dev->struct_mutex);
4348 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4349 mutex_unlock(&dev->struct_mutex);
4351 ret = drm_irq_install(dev);
4353 goto cleanup_ringbuffer;
4358 mutex_lock(&dev->struct_mutex);
4359 i915_gem_cleanup_ringbuffer(dev);
4360 dev_priv->ums.mm_suspended = 1;
4361 mutex_unlock(&dev->struct_mutex);
4367 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4368 struct drm_file *file_priv)
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4373 if (drm_core_check_feature(dev, DRIVER_MODESET))
4376 drm_irq_uninstall(dev);
4378 mutex_lock(&dev->struct_mutex);
4379 ret = i915_gem_idle(dev);
4381 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4382 * We need to replace this with a semaphore, or something.
4383 * And not confound ums.mm_suspended!
4386 dev_priv->ums.mm_suspended = 1;
4387 mutex_unlock(&dev->struct_mutex);
4393 i915_gem_lastclose(struct drm_device *dev)
4397 if (drm_core_check_feature(dev, DRIVER_MODESET))
4400 mutex_lock(&dev->struct_mutex);
4401 ret = i915_gem_idle(dev);
4403 DRM_ERROR("failed to idle hardware: %d\n", ret);
4404 mutex_unlock(&dev->struct_mutex);
4408 init_ring_lists(struct intel_ring_buffer *ring)
4410 INIT_LIST_HEAD(&ring->active_list);
4411 INIT_LIST_HEAD(&ring->request_list);
4414 static void i915_init_vm(struct drm_i915_private *dev_priv,
4415 struct i915_address_space *vm)
4417 vm->dev = dev_priv->dev;
4418 INIT_LIST_HEAD(&vm->active_list);
4419 INIT_LIST_HEAD(&vm->inactive_list);
4420 INIT_LIST_HEAD(&vm->global_link);
4421 list_add(&vm->global_link, &dev_priv->vm_list);
4425 i915_gem_load(struct drm_device *dev)
4427 drm_i915_private_t *dev_priv = dev->dev_private;
4431 kmem_cache_create("i915_gem_object",
4432 sizeof(struct drm_i915_gem_object), 0,
4436 INIT_LIST_HEAD(&dev_priv->vm_list);
4437 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4439 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4440 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4441 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4442 for (i = 0; i < I915_NUM_RINGS; i++)
4443 init_ring_lists(&dev_priv->ring[i]);
4444 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4445 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4446 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4447 i915_gem_retire_work_handler);
4448 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4450 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4452 I915_WRITE(MI_ARB_STATE,
4453 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4456 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4458 /* Old X drivers will take 0-2 for front, back, depth buffers */
4459 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4460 dev_priv->fence_reg_start = 3;
4462 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4463 dev_priv->num_fence_regs = 32;
4464 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4465 dev_priv->num_fence_regs = 16;
4467 dev_priv->num_fence_regs = 8;
4469 /* Initialize fence registers to zero */
4470 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4471 i915_gem_restore_fences(dev);
4473 i915_gem_detect_bit_6_swizzle(dev);
4474 init_waitqueue_head(&dev_priv->pending_flip_queue);
4476 dev_priv->mm.interruptible = true;
4478 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4479 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4480 register_shrinker(&dev_priv->mm.inactive_shrinker);
4484 * Create a physically contiguous memory object for this object
4485 * e.g. for cursor + overlay regs
4487 static int i915_gem_init_phys_object(struct drm_device *dev,
4488 int id, int size, int align)
4490 drm_i915_private_t *dev_priv = dev->dev_private;
4491 struct drm_i915_gem_phys_object *phys_obj;
4494 if (dev_priv->mm.phys_objs[id - 1] || !size)
4497 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4503 phys_obj->handle = drm_pci_alloc(dev, size, align);
4504 if (!phys_obj->handle) {
4509 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4512 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4520 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4522 drm_i915_private_t *dev_priv = dev->dev_private;
4523 struct drm_i915_gem_phys_object *phys_obj;
4525 if (!dev_priv->mm.phys_objs[id - 1])
4528 phys_obj = dev_priv->mm.phys_objs[id - 1];
4529 if (phys_obj->cur_obj) {
4530 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4534 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4536 drm_pci_free(dev, phys_obj->handle);
4538 dev_priv->mm.phys_objs[id - 1] = NULL;
4541 void i915_gem_free_all_phys_object(struct drm_device *dev)
4545 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4546 i915_gem_free_phys_object(dev, i);
4549 void i915_gem_detach_phys_object(struct drm_device *dev,
4550 struct drm_i915_gem_object *obj)
4552 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4559 vaddr = obj->phys_obj->handle->vaddr;
4561 page_count = obj->base.size / PAGE_SIZE;
4562 for (i = 0; i < page_count; i++) {
4563 struct page *page = shmem_read_mapping_page(mapping, i);
4564 if (!IS_ERR(page)) {
4565 char *dst = kmap_atomic(page);
4566 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4569 drm_clflush_pages(&page, 1);
4571 set_page_dirty(page);
4572 mark_page_accessed(page);
4573 page_cache_release(page);
4576 i915_gem_chipset_flush(dev);
4578 obj->phys_obj->cur_obj = NULL;
4579 obj->phys_obj = NULL;
4583 i915_gem_attach_phys_object(struct drm_device *dev,
4584 struct drm_i915_gem_object *obj,
4588 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
4589 drm_i915_private_t *dev_priv = dev->dev_private;
4594 if (id > I915_MAX_PHYS_OBJECT)
4597 if (obj->phys_obj) {
4598 if (obj->phys_obj->id == id)
4600 i915_gem_detach_phys_object(dev, obj);
4603 /* create a new object */
4604 if (!dev_priv->mm.phys_objs[id - 1]) {
4605 ret = i915_gem_init_phys_object(dev, id,
4606 obj->base.size, align);
4608 DRM_ERROR("failed to init phys object %d size: %zu\n",
4609 id, obj->base.size);
4614 /* bind to the object */
4615 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4616 obj->phys_obj->cur_obj = obj;
4618 page_count = obj->base.size / PAGE_SIZE;
4620 for (i = 0; i < page_count; i++) {
4624 page = shmem_read_mapping_page(mapping, i);
4626 return PTR_ERR(page);
4628 src = kmap_atomic(page);
4629 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4630 memcpy(dst, src, PAGE_SIZE);
4633 mark_page_accessed(page);
4634 page_cache_release(page);
4641 i915_gem_phys_pwrite(struct drm_device *dev,
4642 struct drm_i915_gem_object *obj,
4643 struct drm_i915_gem_pwrite *args,
4644 struct drm_file *file_priv)
4646 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
4647 char __user *user_data = to_user_ptr(args->data_ptr);
4649 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4650 unsigned long unwritten;
4652 /* The physical object once assigned is fixed for the lifetime
4653 * of the obj, so we can safely drop the lock and continue
4656 mutex_unlock(&dev->struct_mutex);
4657 unwritten = copy_from_user(vaddr, user_data, args->size);
4658 mutex_lock(&dev->struct_mutex);
4663 i915_gem_chipset_flush(dev);
4667 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4669 struct drm_i915_file_private *file_priv = file->driver_priv;
4671 /* Clean up our request list when the client is going away, so that
4672 * later retire_requests won't dereference our soon-to-be-gone
4675 spin_lock(&file_priv->mm.lock);
4676 while (!list_empty(&file_priv->mm.request_list)) {
4677 struct drm_i915_gem_request *request;
4679 request = list_first_entry(&file_priv->mm.request_list,
4680 struct drm_i915_gem_request,
4682 list_del(&request->client_list);
4683 request->file_priv = NULL;
4685 spin_unlock(&file_priv->mm.lock);
4688 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
4690 if (!mutex_is_locked(mutex))
4693 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4694 return mutex->owner == task;
4696 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4702 i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
4704 struct drm_i915_private *dev_priv =
4705 container_of(shrinker,
4706 struct drm_i915_private,
4707 mm.inactive_shrinker);
4708 struct drm_device *dev = dev_priv->dev;
4709 struct drm_i915_gem_object *obj;
4710 int nr_to_scan = sc->nr_to_scan;
4714 if (!mutex_trylock(&dev->struct_mutex)) {
4715 if (!mutex_is_locked_by(&dev->struct_mutex, current))
4718 if (dev_priv->mm.shrinker_no_lock_stealing)
4725 nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan);
4727 nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan,
4730 i915_gem_shrink_all(dev_priv);
4734 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
4735 if (obj->pages_pin_count == 0)
4736 cnt += obj->base.size >> PAGE_SHIFT;
4738 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
4742 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
4743 cnt += obj->base.size >> PAGE_SHIFT;
4747 mutex_unlock(&dev->struct_mutex);
4751 /* All the new VM stuff */
4752 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
4753 struct i915_address_space *vm)
4755 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4756 struct i915_vma *vma;
4758 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4759 vm = &dev_priv->gtt.base;
4761 BUG_ON(list_empty(&o->vma_list));
4762 list_for_each_entry(vma, &o->vma_list, vma_link) {
4764 return vma->node.start;
4770 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
4771 struct i915_address_space *vm)
4773 struct i915_vma *vma;
4775 list_for_each_entry(vma, &o->vma_list, vma_link)
4776 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
4782 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
4784 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4785 struct i915_address_space *vm;
4787 list_for_each_entry(vm, &dev_priv->vm_list, global_link)
4788 if (i915_gem_obj_bound(o, vm))
4794 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
4795 struct i915_address_space *vm)
4797 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
4798 struct i915_vma *vma;
4800 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
4801 vm = &dev_priv->gtt.base;
4803 BUG_ON(list_empty(&o->vma_list));
4805 list_for_each_entry(vma, &o->vma_list, vma_link)
4807 return vma->node.size;
4812 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4813 struct i915_address_space *vm)
4815 struct i915_vma *vma;
4816 list_for_each_entry(vma, &obj->vma_list, vma_link)