1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain {
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct drm_i915_private;
138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
143 #define I915_NUM_PLLS 2
145 struct intel_dpll_hw_state {
151 struct intel_shared_dpll {
152 int refcount; /* count of number of CRTCs sharing this PLL */
153 int active; /* count of number of active CRTCs (i.e. DPMS on) */
154 bool on; /* is the PLL actually active? Disabled during modeset */
156 /* should match the index in the dev_priv->shared_dplls array */
157 enum intel_dpll_id id;
158 struct intel_dpll_hw_state hw_state;
159 void (*enable)(struct drm_i915_private *dev_priv,
160 struct intel_shared_dpll *pll);
161 void (*disable)(struct drm_i915_private *dev_priv,
162 struct intel_shared_dpll *pll);
163 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
164 struct intel_shared_dpll *pll,
165 struct intel_dpll_hw_state *hw_state);
168 /* Used by dp and fdi links */
169 struct intel_link_m_n {
177 void intel_link_compute_m_n(int bpp, int nlanes,
178 int pixel_clock, int link_clock,
179 struct intel_link_m_n *m_n);
181 struct intel_ddi_plls {
187 /* Interface history:
190 * 1.2: Add Power Management
191 * 1.3: Add vblank support
192 * 1.4: Fix cmdbuffer path, add heap destroy
193 * 1.5: Add vblank pipe configuration
194 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
195 * - Support vertical blank on secondary display pipe
197 #define DRIVER_MAJOR 1
198 #define DRIVER_MINOR 6
199 #define DRIVER_PATCHLEVEL 0
201 #define WATCH_COHERENCY 0
202 #define WATCH_LISTS 0
205 #define I915_GEM_PHYS_CURSOR_0 1
206 #define I915_GEM_PHYS_CURSOR_1 2
207 #define I915_GEM_PHYS_OVERLAY_REGS 3
208 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
210 struct drm_i915_gem_phys_object {
212 struct page **page_list;
213 drm_dma_handle_t *handle;
214 struct drm_i915_gem_object *cur_obj;
217 struct opregion_header;
218 struct opregion_acpi;
219 struct opregion_swsci;
220 struct opregion_asle;
222 struct intel_opregion {
223 struct opregion_header __iomem *header;
224 struct opregion_acpi __iomem *acpi;
225 struct opregion_swsci __iomem *swsci;
226 struct opregion_asle __iomem *asle;
228 u32 __iomem *lid_state;
230 #define OPREGION_SIZE (8*1024)
232 struct intel_overlay;
233 struct intel_overlay_error_state;
235 struct drm_i915_master_private {
236 drm_local_map_t *sarea;
237 struct _drm_i915_sarea *sarea_priv;
239 #define I915_FENCE_REG_NONE -1
240 #define I915_MAX_NUM_FENCES 32
241 /* 32 fences + sign bit for FENCE_REG_NONE */
242 #define I915_MAX_NUM_FENCE_BITS 6
244 struct drm_i915_fence_reg {
245 struct list_head lru_list;
246 struct drm_i915_gem_object *obj;
250 struct sdvo_device_mapping {
259 struct intel_display_error_state;
261 struct drm_i915_error_state {
269 bool waiting[I915_NUM_RINGS];
270 u32 pipestat[I915_MAX_PIPES];
271 u32 tail[I915_NUM_RINGS];
272 u32 head[I915_NUM_RINGS];
273 u32 ctl[I915_NUM_RINGS];
274 u32 ipeir[I915_NUM_RINGS];
275 u32 ipehr[I915_NUM_RINGS];
276 u32 instdone[I915_NUM_RINGS];
277 u32 acthd[I915_NUM_RINGS];
278 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
279 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
280 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
281 /* our own tracking of ring head and tail */
282 u32 cpu_ring_head[I915_NUM_RINGS];
283 u32 cpu_ring_tail[I915_NUM_RINGS];
284 u32 error; /* gen6+ */
285 u32 err_int; /* gen7 */
286 u32 instpm[I915_NUM_RINGS];
287 u32 instps[I915_NUM_RINGS];
288 u32 extra_instdone[I915_NUM_INSTDONE_REG];
289 u32 seqno[I915_NUM_RINGS];
291 u32 fault_reg[I915_NUM_RINGS];
293 u32 faddr[I915_NUM_RINGS];
294 u64 fence[I915_MAX_NUM_FENCES];
296 struct drm_i915_error_ring {
297 struct drm_i915_error_object {
301 } *ringbuffer, *batchbuffer, *ctx;
302 struct drm_i915_error_request {
308 } ring[I915_NUM_RINGS];
309 struct drm_i915_error_buffer {
316 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
323 } *active_bo, *pinned_bo;
324 u32 active_bo_count, pinned_bo_count;
325 struct intel_overlay_error_state *overlay;
326 struct intel_display_error_state *display;
329 struct intel_crtc_config;
334 struct drm_i915_display_funcs {
335 bool (*fbc_enabled)(struct drm_device *dev);
336 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
337 void (*disable_fbc)(struct drm_device *dev);
338 int (*get_display_clock_speed)(struct drm_device *dev);
339 int (*get_fifo_size)(struct drm_device *dev, int plane);
341 * find_dpll() - Find the best values for the PLL
342 * @limit: limits for the PLL
343 * @crtc: current CRTC
344 * @target: target frequency in kHz
345 * @refclk: reference clock frequency in kHz
346 * @match_clock: if provided, @best_clock P divider must
347 * match the P divider from @match_clock
348 * used for LVDS downclocking
349 * @best_clock: best PLL values found
351 * Returns true on success, false on failure.
353 bool (*find_dpll)(const struct intel_limit *limit,
354 struct drm_crtc *crtc,
355 int target, int refclk,
356 struct dpll *match_clock,
357 struct dpll *best_clock);
358 void (*update_wm)(struct drm_device *dev);
359 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
360 uint32_t sprite_width, int pixel_size,
362 void (*modeset_global_resources)(struct drm_device *dev);
363 /* Returns the active state of the crtc, and if the crtc is active,
364 * fills out the pipe-config with the hw state. */
365 bool (*get_pipe_config)(struct intel_crtc *,
366 struct intel_crtc_config *);
367 int (*crtc_mode_set)(struct drm_crtc *crtc,
369 struct drm_framebuffer *old_fb);
370 void (*crtc_enable)(struct drm_crtc *crtc);
371 void (*crtc_disable)(struct drm_crtc *crtc);
372 void (*off)(struct drm_crtc *crtc);
373 void (*write_eld)(struct drm_connector *connector,
374 struct drm_crtc *crtc);
375 void (*fdi_link_train)(struct drm_crtc *crtc);
376 void (*init_clock_gating)(struct drm_device *dev);
377 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
378 struct drm_framebuffer *fb,
379 struct drm_i915_gem_object *obj);
380 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
382 void (*hpd_irq_setup)(struct drm_device *dev);
383 /* clock updates for mode set */
385 /* render clock increase/decrease */
386 /* display clock increase/decrease */
387 /* pll clock increase/decrease */
390 struct drm_i915_gt_funcs {
391 void (*force_wake_get)(struct drm_i915_private *dev_priv);
392 void (*force_wake_put)(struct drm_i915_private *dev_priv);
395 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
396 func(is_mobile) sep \
399 func(is_i945gm) sep \
401 func(need_gfx_hws) sep \
403 func(is_pineview) sep \
404 func(is_broadwater) sep \
405 func(is_crestline) sep \
406 func(is_ivybridge) sep \
407 func(is_valleyview) sep \
408 func(is_haswell) sep \
409 func(has_force_wake) sep \
411 func(has_pipe_cxsr) sep \
412 func(has_hotplug) sep \
413 func(cursor_needs_physical) sep \
414 func(has_overlay) sep \
415 func(overlay_needs_physical) sep \
416 func(supports_tv) sep \
417 func(has_bsd_ring) sep \
418 func(has_blt_ring) sep \
419 func(has_vebox_ring) sep \
424 #define DEFINE_FLAG(name) u8 name:1
425 #define SEP_SEMICOLON ;
427 struct intel_device_info {
428 u32 display_mmio_offset;
431 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
437 enum i915_cache_level {
440 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
443 typedef uint32_t gen6_gtt_pte_t;
445 /* The Graphics Translation Table is the way in which GEN hardware translates a
446 * Graphics Virtual Address into a Physical Address. In addition to the normal
447 * collateral associated with any va->pa translations GEN hardware also has a
448 * portion of the GTT which can be mapped by the CPU and remain both coherent
449 * and correct (in cases like swizzling). That region is referred to as GMADR in
453 unsigned long start; /* Start offset of used GTT */
454 size_t total; /* Total size GTT can map */
455 size_t stolen_size; /* Total size of stolen memory */
457 unsigned long mappable_end; /* End offset that we can CPU map */
458 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
459 phys_addr_t mappable_base; /* PA of our GMADR */
461 /** "Graphics Stolen Memory" holds the global PTEs */
465 dma_addr_t scratch_page_dma;
466 struct page *scratch_page;
469 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
470 size_t *stolen, phys_addr_t *mappable_base,
471 unsigned long *mappable_end);
472 void (*gtt_remove)(struct drm_device *dev);
473 void (*gtt_clear_range)(struct drm_device *dev,
474 unsigned int first_entry,
475 unsigned int num_entries);
476 void (*gtt_insert_entries)(struct drm_device *dev,
478 unsigned int pg_start,
479 enum i915_cache_level cache_level);
480 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
482 enum i915_cache_level level);
484 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
486 #define I915_PPGTT_PD_ENTRIES 512
487 #define I915_PPGTT_PT_ENTRIES 1024
488 struct i915_hw_ppgtt {
489 struct drm_device *dev;
490 unsigned num_pd_entries;
491 struct page **pt_pages;
493 dma_addr_t *pt_dma_addr;
494 dma_addr_t scratch_page_dma_addr;
496 /* pte functions, mirroring the interface of the global gtt. */
497 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
498 unsigned int first_entry,
499 unsigned int num_entries);
500 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
502 unsigned int pg_start,
503 enum i915_cache_level cache_level);
504 gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
506 enum i915_cache_level level);
507 int (*enable)(struct drm_device *dev);
508 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
511 struct i915_ctx_hang_stats {
512 /* This context had batch pending when hang was declared */
513 unsigned batch_pending;
515 /* This context had batch active when hang was declared */
516 unsigned batch_active;
519 /* This must match up with the value previously used for execbuf2.rsvd1. */
520 #define DEFAULT_CONTEXT_ID 0
521 struct i915_hw_context {
525 struct drm_i915_file_private *file_priv;
526 struct intel_ring_buffer *ring;
527 struct drm_i915_gem_object *obj;
528 struct i915_ctx_hang_stats hang_stats;
532 FBC_NO_OUTPUT, /* no outputs enabled to compress */
533 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
534 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
535 FBC_MODE_TOO_LARGE, /* mode too large for compression */
536 FBC_BAD_PLANE, /* fbc not supported on plane */
537 FBC_NOT_TILED, /* buffer not tiled */
538 FBC_MULTIPLE_PIPES, /* more than one pipe active */
543 PCH_NONE = 0, /* No PCH present */
544 PCH_IBX, /* Ibexpeak PCH */
545 PCH_CPT, /* Cougarpoint PCH */
546 PCH_LPT, /* Lynxpoint PCH */
550 enum intel_sbi_destination {
555 #define QUIRK_PIPEA_FORCE (1<<0)
556 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
557 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
560 struct intel_fbc_work;
563 struct i2c_adapter adapter;
567 struct i2c_algo_bit_data bit_algo;
568 struct drm_i915_private *dev_priv;
571 struct i915_suspend_saved_registers {
592 u32 saveTRANS_HTOTAL_A;
593 u32 saveTRANS_HBLANK_A;
594 u32 saveTRANS_HSYNC_A;
595 u32 saveTRANS_VTOTAL_A;
596 u32 saveTRANS_VBLANK_A;
597 u32 saveTRANS_VSYNC_A;
605 u32 savePFIT_PGM_RATIOS;
606 u32 saveBLC_HIST_CTL;
608 u32 saveBLC_PWM_CTL2;
609 u32 saveBLC_CPU_PWM_CTL;
610 u32 saveBLC_CPU_PWM_CTL2;
623 u32 saveTRANS_HTOTAL_B;
624 u32 saveTRANS_HBLANK_B;
625 u32 saveTRANS_HSYNC_B;
626 u32 saveTRANS_VTOTAL_B;
627 u32 saveTRANS_VBLANK_B;
628 u32 saveTRANS_VSYNC_B;
642 u32 savePP_ON_DELAYS;
643 u32 savePP_OFF_DELAYS;
651 u32 savePFIT_CONTROL;
652 u32 save_palette_a[256];
653 u32 save_palette_b[256];
654 u32 saveDPFC_CB_BASE;
655 u32 saveFBC_CFB_BASE;
658 u32 saveFBC_CONTROL2;
668 u32 saveCACHE_MODE_0;
669 u32 saveMI_ARB_STATE;
680 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
691 u32 savePIPEA_GMCH_DATA_M;
692 u32 savePIPEB_GMCH_DATA_M;
693 u32 savePIPEA_GMCH_DATA_N;
694 u32 savePIPEB_GMCH_DATA_N;
695 u32 savePIPEA_DP_LINK_M;
696 u32 savePIPEB_DP_LINK_M;
697 u32 savePIPEA_DP_LINK_N;
698 u32 savePIPEB_DP_LINK_N;
709 u32 savePCH_DREF_CONTROL;
710 u32 saveDISP_ARB_CTL;
711 u32 savePIPEA_DATA_M1;
712 u32 savePIPEA_DATA_N1;
713 u32 savePIPEA_LINK_M1;
714 u32 savePIPEA_LINK_N1;
715 u32 savePIPEB_DATA_M1;
716 u32 savePIPEB_DATA_N1;
717 u32 savePIPEB_LINK_M1;
718 u32 savePIPEB_LINK_N1;
719 u32 saveMCHBAR_RENDER_STANDBY;
720 u32 savePCH_PORT_HOTPLUG;
723 struct intel_gen6_power_mgmt {
724 struct work_struct work;
725 struct delayed_work vlv_work;
727 /* lock - irqsave spinlock that protectects the work_struct and
731 /* The below variables an all the rps hw state are protected by
732 * dev->struct mutext. */
739 struct delayed_work delayed_resume_work;
742 * Protects RPS/RC6 register access and PCU communication.
743 * Must be taken after struct_mutex if nested.
745 struct mutex hw_lock;
748 /* defined intel_pm.c */
749 extern spinlock_t mchdev_lock;
751 struct intel_ilk_power_mgmt {
759 unsigned long last_time1;
760 unsigned long chipset_power;
762 struct timespec last_time2;
763 unsigned long gfx_power;
769 struct drm_i915_gem_object *pwrctx;
770 struct drm_i915_gem_object *renderctx;
773 /* Power well structure for haswell */
774 struct i915_power_well {
775 struct drm_device *device;
777 /* power well enable/disable usage count */
782 struct i915_dri1_state {
783 unsigned allow_batchbuffer : 1;
784 u32 __iomem *gfx_hws_cpu_addr;
795 struct intel_l3_parity {
797 struct work_struct error_work;
801 /** Memory allocator for GTT stolen memory */
802 struct drm_mm stolen;
803 /** Memory allocator for GTT */
804 struct drm_mm gtt_space;
805 /** List of all objects in gtt_space. Used to restore gtt
806 * mappings on resume */
807 struct list_head bound_list;
809 * List of objects which are not bound to the GTT (thus
810 * are idle and not used by the GPU) but still have
811 * (presumably uncached) pages still attached.
813 struct list_head unbound_list;
815 /** Usable portion of the GTT for GEM */
816 unsigned long stolen_base; /* limited to low memory (32-bit) */
820 /** PPGTT used for aliasing the PPGTT with the GTT */
821 struct i915_hw_ppgtt *aliasing_ppgtt;
823 struct shrinker inactive_shrinker;
824 bool shrinker_no_lock_stealing;
827 * List of objects currently involved in rendering.
829 * Includes buffers having the contents of their GPU caches
830 * flushed, not necessarily primitives. last_rendering_seqno
831 * represents when the rendering involved will be completed.
833 * A reference is held on the buffer while on this list.
835 struct list_head active_list;
838 * LRU list of objects which are not in the ringbuffer and
839 * are ready to unbind, but are still in the GTT.
841 * last_rendering_seqno is 0 while an object is in this list.
843 * A reference is not held on the buffer while on this list,
844 * as merely being GTT-bound shouldn't prevent its being
845 * freed, and we'll pull it off the list in the free path.
847 struct list_head inactive_list;
849 /** LRU list of objects with fence regs on them. */
850 struct list_head fence_list;
853 * We leave the user IRQ off as much as possible,
854 * but this means that requests will finish and never
855 * be retired once the system goes idle. Set a timer to
856 * fire periodically while the ring is running. When it
857 * fires, go retire requests.
859 struct delayed_work retire_work;
862 * Are we in a non-interruptible section of code like
868 * Flag if the X Server, and thus DRM, is not currently in
869 * control of the device.
871 * This is set between LeaveVT and EnterVT. It needs to be
872 * replaced with a semaphore. It also needs to be
873 * transitioned away from for kernel modesetting.
877 /** Bit 6 swizzling required for X tiling */
878 uint32_t bit_6_swizzle_x;
879 /** Bit 6 swizzling required for Y tiling */
880 uint32_t bit_6_swizzle_y;
882 /* storage for physical objects */
883 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
885 /* accounting, useful for userland debugging */
886 size_t object_memory;
890 struct drm_i915_error_state_buf {
899 struct i915_gpu_error {
900 /* For hangcheck timer */
901 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
902 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
903 struct timer_list hangcheck_timer;
905 /* For reset and error_state handling. */
907 /* Protected by the above dev->gpu_error.lock. */
908 struct drm_i915_error_state *first_error;
909 struct work_struct work;
911 unsigned long last_reset;
914 * State variable and reset counter controlling the reset flow
916 * Upper bits are for the reset counter. This counter is used by the
917 * wait_seqno code to race-free noticed that a reset event happened and
918 * that it needs to restart the entire ioctl (since most likely the
919 * seqno it waited for won't ever signal anytime soon).
921 * This is important for lock-free wait paths, where no contended lock
922 * naturally enforces the correct ordering between the bail-out of the
923 * waiter and the gpu reset work code.
925 * Lowest bit controls the reset state machine: Set means a reset is in
926 * progress. This state will (presuming we don't have any bugs) decay
927 * into either unset (successful reset) or the special WEDGED value (hw
928 * terminally sour). All waiters on the reset_queue will be woken when
931 atomic_t reset_counter;
934 * Special values/flags for reset_counter
936 * Note that the code relies on
937 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
940 #define I915_RESET_IN_PROGRESS_FLAG 1
941 #define I915_WEDGED 0xffffffff
944 * Waitqueue to signal when the reset has completed. Used by clients
945 * that wait for dev_priv->mm.wedged to settle.
947 wait_queue_head_t reset_queue;
949 /* For gpu hang simulation. */
950 unsigned int stop_rings;
953 enum modeset_restore {
959 struct intel_vbt_data {
960 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
961 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
964 unsigned int int_tv_support:1;
965 unsigned int lvds_dither:1;
966 unsigned int lvds_vbt:1;
967 unsigned int int_crt_support:1;
968 unsigned int lvds_use_ssc:1;
969 unsigned int display_clock_mode:1;
970 unsigned int fdi_rx_polarity_inverted:1;
972 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
979 bool edp_initialized;
982 struct edp_power_seq edp_pps;
987 struct child_device_config *child_dev;
990 typedef struct drm_i915_private {
991 struct drm_device *dev;
992 struct kmem_cache *slab;
994 const struct intel_device_info *info;
996 int relative_constants_mode;
1000 struct drm_i915_gt_funcs gt;
1001 /** gt_fifo_count and the subsequent register write are synchronized
1002 * with dev->struct_mutex. */
1003 unsigned gt_fifo_count;
1004 /** forcewake_count is protected by gt_lock */
1005 unsigned forcewake_count;
1006 /** gt_lock is also taken in irq contexts. */
1009 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1012 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1013 * controller on different i2c buses. */
1014 struct mutex gmbus_mutex;
1017 * Base address of the gmbus and gpio block.
1019 uint32_t gpio_mmio_base;
1021 wait_queue_head_t gmbus_wait_queue;
1023 struct pci_dev *bridge_dev;
1024 struct intel_ring_buffer ring[I915_NUM_RINGS];
1025 uint32_t last_seqno, next_seqno;
1027 drm_dma_handle_t *status_page_dmah;
1028 struct resource mch_res;
1030 atomic_t irq_received;
1032 /* protects the irq masks */
1033 spinlock_t irq_lock;
1035 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1036 struct pm_qos_request pm_qos;
1038 /* DPIO indirect register protection */
1039 struct mutex dpio_lock;
1041 /** Cached value of IMR to avoid reads in updating the bitfield */
1045 struct work_struct hotplug_work;
1046 bool enable_hotplug_processing;
1048 unsigned long hpd_last_jiffies;
1053 HPD_MARK_DISABLED = 2
1055 } hpd_stats[HPD_NUM_PINS];
1057 struct timer_list hotplug_reenable_timer;
1061 unsigned long cfb_size;
1062 unsigned int cfb_fb;
1063 enum plane cfb_plane;
1065 struct intel_fbc_work *fbc_work;
1067 struct intel_opregion opregion;
1068 struct intel_vbt_data vbt;
1071 struct intel_overlay *overlay;
1072 unsigned int sprite_scaling_enabled;
1078 spinlock_t lock; /* bl registers and the above bl fields */
1079 struct backlight_device *device;
1083 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1084 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1085 bool no_aux_handshake;
1087 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1088 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1089 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1091 unsigned int fsb_freq, mem_freq, is_ddr3;
1093 struct workqueue_struct *wq;
1095 /* Display functions */
1096 struct drm_i915_display_funcs display;
1098 /* PCH chipset type */
1099 enum intel_pch pch_type;
1100 unsigned short pch_id;
1102 unsigned long quirks;
1104 enum modeset_restore modeset_restore;
1105 struct mutex modeset_restore_lock;
1107 struct i915_gtt gtt;
1109 struct i915_gem_mm mm;
1111 /* Kernel Modesetting */
1113 struct sdvo_device_mapping sdvo_mappings[2];
1115 struct drm_crtc *plane_to_crtc_mapping[3];
1116 struct drm_crtc *pipe_to_crtc_mapping[3];
1117 wait_queue_head_t pending_flip_queue;
1119 int num_shared_dpll;
1120 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1121 struct intel_ddi_plls ddi_plls;
1123 /* Reclocking support */
1124 bool render_reclock_avail;
1125 bool lvds_downclock_avail;
1126 /* indicates the reduced downclock for LVDS*/
1130 bool mchbar_need_disable;
1132 struct intel_l3_parity l3_parity;
1134 /* gen6+ rps state */
1135 struct intel_gen6_power_mgmt rps;
1137 /* ilk-only ips/rps state. Everything in here is protected by the global
1138 * mchdev_lock in intel_pm.c */
1139 struct intel_ilk_power_mgmt ips;
1141 /* Haswell power well */
1142 struct i915_power_well power_well;
1144 enum no_fbc_reason no_fbc_reason;
1146 struct drm_mm_node *compressed_fb;
1147 struct drm_mm_node *compressed_llb;
1149 struct i915_gpu_error gpu_error;
1151 struct drm_i915_gem_object *vlv_pctx;
1153 /* list of fbdev register on this device */
1154 struct intel_fbdev *fbdev;
1157 * The console may be contended at resume, but we don't
1158 * want it to block on it.
1160 struct work_struct console_resume_work;
1162 struct drm_property *broadcast_rgb_property;
1163 struct drm_property *force_audio_property;
1165 bool hw_contexts_disabled;
1166 uint32_t hw_context_size;
1170 struct i915_suspend_saved_registers regfile;
1172 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1174 struct i915_dri1_state dri1;
1175 } drm_i915_private_t;
1177 /* Iterate over initialised rings */
1178 #define for_each_ring(ring__, dev_priv__, i__) \
1179 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1180 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1182 enum hdmi_force_audio {
1183 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1184 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1185 HDMI_AUDIO_AUTO, /* trust EDID */
1186 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1189 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1191 struct drm_i915_gem_object_ops {
1192 /* Interface between the GEM object and its backing storage.
1193 * get_pages() is called once prior to the use of the associated set
1194 * of pages before to binding them into the GTT, and put_pages() is
1195 * called after we no longer need them. As we expect there to be
1196 * associated cost with migrating pages between the backing storage
1197 * and making them available for the GPU (e.g. clflush), we may hold
1198 * onto the pages after they are no longer referenced by the GPU
1199 * in case they may be used again shortly (for example migrating the
1200 * pages to a different memory domain within the GTT). put_pages()
1201 * will therefore most likely be called when the object itself is
1202 * being released or under memory pressure (where we attempt to
1203 * reap pages for the shrinker).
1205 int (*get_pages)(struct drm_i915_gem_object *);
1206 void (*put_pages)(struct drm_i915_gem_object *);
1209 struct drm_i915_gem_object {
1210 struct drm_gem_object base;
1212 const struct drm_i915_gem_object_ops *ops;
1214 /** Current space allocated to this object in the GTT, if any. */
1215 struct drm_mm_node *gtt_space;
1216 /** Stolen memory for this object, instead of being backed by shmem. */
1217 struct drm_mm_node *stolen;
1218 struct list_head global_list;
1220 /** This object's place on the active/inactive lists */
1221 struct list_head ring_list;
1222 struct list_head mm_list;
1223 /** This object's place in the batchbuffer or on the eviction list */
1224 struct list_head exec_list;
1227 * This is set if the object is on the active lists (has pending
1228 * rendering and so a non-zero seqno), and is not set if it i s on
1229 * inactive (ready to be unbound) list.
1231 unsigned int active:1;
1234 * This is set if the object has been written to since last bound
1237 unsigned int dirty:1;
1240 * Fence register bits (if any) for this object. Will be set
1241 * as needed when mapped into the GTT.
1242 * Protected by dev->struct_mutex.
1244 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1247 * Advice: are the backing pages purgeable?
1249 unsigned int madv:2;
1252 * Current tiling mode for the object.
1254 unsigned int tiling_mode:2;
1256 * Whether the tiling parameters for the currently associated fence
1257 * register have changed. Note that for the purposes of tracking
1258 * tiling changes we also treat the unfenced register, the register
1259 * slot that the object occupies whilst it executes a fenced
1260 * command (such as BLT on gen2/3), as a "fence".
1262 unsigned int fence_dirty:1;
1264 /** How many users have pinned this object in GTT space. The following
1265 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1266 * (via user_pin_count), execbuffer (objects are not allowed multiple
1267 * times for the same batchbuffer), and the framebuffer code. When
1268 * switching/pageflipping, the framebuffer code has at most two buffers
1271 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1272 * bits with absolutely no headroom. So use 4 bits. */
1273 unsigned int pin_count:4;
1274 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1277 * Is the object at the current location in the gtt mappable and
1278 * fenceable? Used to avoid costly recalculations.
1280 unsigned int map_and_fenceable:1;
1283 * Whether the current gtt mapping needs to be mappable (and isn't just
1284 * mappable by accident). Track pin and fault separate for a more
1285 * accurate mappable working set.
1287 unsigned int fault_mappable:1;
1288 unsigned int pin_mappable:1;
1291 * Is the GPU currently using a fence to access this buffer,
1293 unsigned int pending_fenced_gpu_access:1;
1294 unsigned int fenced_gpu_access:1;
1296 unsigned int cache_level:2;
1298 unsigned int has_aliasing_ppgtt_mapping:1;
1299 unsigned int has_global_gtt_mapping:1;
1300 unsigned int has_dma_mapping:1;
1302 struct sg_table *pages;
1303 int pages_pin_count;
1305 /* prime dma-buf support */
1306 void *dma_buf_vmapping;
1310 * Used for performing relocations during execbuffer insertion.
1312 struct hlist_node exec_node;
1313 unsigned long exec_handle;
1314 struct drm_i915_gem_exec_object2 *exec_entry;
1317 * Current offset of the object in GTT space.
1319 * This is the same as gtt_space->start
1321 uint32_t gtt_offset;
1323 struct intel_ring_buffer *ring;
1325 /** Breadcrumb of last rendering to the buffer. */
1326 uint32_t last_read_seqno;
1327 uint32_t last_write_seqno;
1328 /** Breadcrumb of last fenced GPU access to the buffer. */
1329 uint32_t last_fenced_seqno;
1331 /** Current tiling stride for the object, if it's tiled. */
1334 /** Record of address bit 17 of each page at last unbind. */
1335 unsigned long *bit_17;
1337 /** User space pin count and filp owning the pin */
1338 uint32_t user_pin_count;
1339 struct drm_file *pin_filp;
1341 /** for phy allocated objects */
1342 struct drm_i915_gem_phys_object *phys_obj;
1344 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1346 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1349 * Request queue structure.
1351 * The request queue allows us to note sequence numbers that have been emitted
1352 * and may be associated with active buffers to be retired.
1354 * By keeping this list, we can avoid having to do questionable
1355 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1356 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1358 struct drm_i915_gem_request {
1359 /** On Which ring this request was generated */
1360 struct intel_ring_buffer *ring;
1362 /** GEM sequence number associated with this request. */
1365 /** Postion in the ringbuffer of the end of the request */
1368 /** Context related to this request */
1369 struct i915_hw_context *ctx;
1371 /** Time at which this request was emitted, in jiffies. */
1372 unsigned long emitted_jiffies;
1374 /** global list entry for this request */
1375 struct list_head list;
1377 struct drm_i915_file_private *file_priv;
1378 /** file_priv list entry for this request */
1379 struct list_head client_list;
1382 struct drm_i915_file_private {
1385 struct list_head request_list;
1387 struct idr context_idr;
1389 struct i915_ctx_hang_stats hang_stats;
1392 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1394 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1395 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1396 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1397 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1398 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1399 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1400 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1401 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1402 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1403 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1404 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1405 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1406 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1407 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1408 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1409 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1410 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1411 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1412 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1413 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1414 (dev)->pci_device == 0x0152 || \
1415 (dev)->pci_device == 0x015a)
1416 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1417 (dev)->pci_device == 0x0106 || \
1418 (dev)->pci_device == 0x010A)
1419 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1420 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1421 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1422 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1423 ((dev)->pci_device & 0xFF00) == 0x0A00)
1426 * The genX designation typically refers to the render engine, so render
1427 * capability related checks should use IS_GEN, while display and other checks
1428 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1431 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1432 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1433 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1434 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1435 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1436 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1438 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1439 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1440 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1441 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1442 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1444 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1445 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1447 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1448 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1450 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1451 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1453 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1454 * rows, which changed the alignment requirements and fence programming.
1456 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1458 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1459 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1460 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1461 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1462 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1463 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1464 /* dsparb controlled by hw only */
1465 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1467 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1468 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1469 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1471 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1473 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1474 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1475 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1477 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1478 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1479 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1480 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1481 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1482 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1484 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1485 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1486 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1487 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1488 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1489 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1491 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1493 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1495 #define GT_FREQUENCY_MULTIPLIER 50
1497 #include "i915_trace.h"
1500 * RC6 is a special power stage which allows the GPU to enter an very
1501 * low-voltage mode when idle, using down to 0V while at this stage. This
1502 * stage is entered automatically when the GPU is idle when RC6 support is
1503 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1505 * There are different RC6 modes available in Intel GPU, which differentiate
1506 * among each other with the latency required to enter and leave RC6 and
1507 * voltage consumed by the GPU in different states.
1509 * The combination of the following flags define which states GPU is allowed
1510 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1511 * RC6pp is deepest RC6. Their support by hardware varies according to the
1512 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1513 * which brings the most power savings; deeper states save more power, but
1514 * require higher latency to switch to and wake up.
1516 #define INTEL_RC6_ENABLE (1<<0)
1517 #define INTEL_RC6p_ENABLE (1<<1)
1518 #define INTEL_RC6pp_ENABLE (1<<2)
1520 extern struct drm_ioctl_desc i915_ioctls[];
1521 extern int i915_max_ioctl;
1522 extern unsigned int i915_fbpercrtc __always_unused;
1523 extern int i915_panel_ignore_lid __read_mostly;
1524 extern unsigned int i915_powersave __read_mostly;
1525 extern int i915_semaphores __read_mostly;
1526 extern unsigned int i915_lvds_downclock __read_mostly;
1527 extern int i915_lvds_channel_mode __read_mostly;
1528 extern int i915_panel_use_ssc __read_mostly;
1529 extern int i915_vbt_sdvo_panel_type __read_mostly;
1530 extern int i915_enable_rc6 __read_mostly;
1531 extern int i915_enable_fbc __read_mostly;
1532 extern bool i915_enable_hangcheck __read_mostly;
1533 extern int i915_enable_ppgtt __read_mostly;
1534 extern unsigned int i915_preliminary_hw_support __read_mostly;
1535 extern int i915_disable_power_well __read_mostly;
1536 extern int i915_enable_ips __read_mostly;
1538 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1539 extern int i915_resume(struct drm_device *dev);
1540 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1541 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1544 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1545 extern void i915_kernel_lost_context(struct drm_device * dev);
1546 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1547 extern int i915_driver_unload(struct drm_device *);
1548 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1549 extern void i915_driver_lastclose(struct drm_device * dev);
1550 extern void i915_driver_preclose(struct drm_device *dev,
1551 struct drm_file *file_priv);
1552 extern void i915_driver_postclose(struct drm_device *dev,
1553 struct drm_file *file_priv);
1554 extern int i915_driver_device_is_agp(struct drm_device * dev);
1555 #ifdef CONFIG_COMPAT
1556 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1559 extern int i915_emit_box(struct drm_device *dev,
1560 struct drm_clip_rect *box,
1562 extern int intel_gpu_reset(struct drm_device *dev);
1563 extern int i915_reset(struct drm_device *dev);
1564 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1565 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1566 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1567 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1569 extern void intel_console_resume(struct work_struct *work);
1572 void i915_hangcheck_elapsed(unsigned long data);
1573 void i915_handle_error(struct drm_device *dev, bool wedged);
1575 extern void intel_irq_init(struct drm_device *dev);
1576 extern void intel_hpd_init(struct drm_device *dev);
1577 extern void intel_gt_init(struct drm_device *dev);
1578 extern void intel_gt_reset(struct drm_device *dev);
1580 void i915_error_state_free(struct kref *error_ref);
1583 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1586 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1588 #ifdef CONFIG_DEBUG_FS
1589 extern void i915_destroy_error_state(struct drm_device *dev);
1591 #define i915_destroy_error_state(x)
1596 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1597 struct drm_file *file_priv);
1598 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1599 struct drm_file *file_priv);
1600 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1601 struct drm_file *file_priv);
1602 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1603 struct drm_file *file_priv);
1604 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1605 struct drm_file *file_priv);
1606 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1607 struct drm_file *file_priv);
1608 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1609 struct drm_file *file_priv);
1610 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1611 struct drm_file *file_priv);
1612 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1613 struct drm_file *file_priv);
1614 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1615 struct drm_file *file_priv);
1616 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1617 struct drm_file *file_priv);
1618 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1619 struct drm_file *file_priv);
1620 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1621 struct drm_file *file_priv);
1622 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1623 struct drm_file *file);
1624 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1625 struct drm_file *file);
1626 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1627 struct drm_file *file_priv);
1628 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1629 struct drm_file *file_priv);
1630 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1631 struct drm_file *file_priv);
1632 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1633 struct drm_file *file_priv);
1634 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1635 struct drm_file *file_priv);
1636 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1637 struct drm_file *file_priv);
1638 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1639 struct drm_file *file_priv);
1640 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1641 struct drm_file *file_priv);
1642 void i915_gem_load(struct drm_device *dev);
1643 void *i915_gem_object_alloc(struct drm_device *dev);
1644 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1645 int i915_gem_init_object(struct drm_gem_object *obj);
1646 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1647 const struct drm_i915_gem_object_ops *ops);
1648 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1650 void i915_gem_free_object(struct drm_gem_object *obj);
1652 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1654 bool map_and_fenceable,
1656 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1657 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1658 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1659 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1660 void i915_gem_lastclose(struct drm_device *dev);
1662 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1663 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1665 struct sg_page_iter sg_iter;
1667 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1668 return sg_page_iter_page(&sg_iter);
1672 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1674 BUG_ON(obj->pages == NULL);
1675 obj->pages_pin_count++;
1677 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1679 BUG_ON(obj->pages_pin_count == 0);
1680 obj->pages_pin_count--;
1683 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1684 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1685 struct intel_ring_buffer *to);
1686 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1687 struct intel_ring_buffer *ring);
1689 int i915_gem_dumb_create(struct drm_file *file_priv,
1690 struct drm_device *dev,
1691 struct drm_mode_create_dumb *args);
1692 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1693 uint32_t handle, uint64_t *offset);
1694 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1697 * Returns true if seq1 is later than seq2.
1700 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1702 return (int32_t)(seq1 - seq2) >= 0;
1705 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1706 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1707 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1708 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1711 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1713 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1714 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1715 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1722 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1724 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1725 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1726 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
1727 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1731 void i915_gem_retire_requests(struct drm_device *dev);
1732 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1733 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1734 bool interruptible);
1735 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1737 return unlikely(atomic_read(&error->reset_counter)
1738 & I915_RESET_IN_PROGRESS_FLAG);
1741 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1743 return atomic_read(&error->reset_counter) == I915_WEDGED;
1746 void i915_gem_reset(struct drm_device *dev);
1747 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1748 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1749 uint32_t read_domains,
1750 uint32_t write_domain);
1751 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1752 int __must_check i915_gem_init(struct drm_device *dev);
1753 int __must_check i915_gem_init_hw(struct drm_device *dev);
1754 void i915_gem_l3_remap(struct drm_device *dev);
1755 void i915_gem_init_swizzling(struct drm_device *dev);
1756 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1757 int __must_check i915_gpu_idle(struct drm_device *dev);
1758 int __must_check i915_gem_idle(struct drm_device *dev);
1759 int i915_add_request(struct intel_ring_buffer *ring,
1760 struct drm_file *file,
1762 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1764 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1766 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1769 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1771 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1773 struct intel_ring_buffer *pipelined);
1774 int i915_gem_attach_phys_object(struct drm_device *dev,
1775 struct drm_i915_gem_object *obj,
1778 void i915_gem_detach_phys_object(struct drm_device *dev,
1779 struct drm_i915_gem_object *obj);
1780 void i915_gem_free_all_phys_object(struct drm_device *dev);
1781 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1784 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1786 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1787 int tiling_mode, bool fenced);
1789 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1790 enum i915_cache_level cache_level);
1792 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1793 struct dma_buf *dma_buf);
1795 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1796 struct drm_gem_object *gem_obj, int flags);
1798 /* i915_gem_context.c */
1799 void i915_gem_context_init(struct drm_device *dev);
1800 void i915_gem_context_fini(struct drm_device *dev);
1801 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1802 int i915_switch_context(struct intel_ring_buffer *ring,
1803 struct drm_file *file, int to_id);
1804 void i915_gem_context_free(struct kref *ctx_ref);
1805 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1807 kref_get(&ctx->ref);
1810 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1812 kref_put(&ctx->ref, i915_gem_context_free);
1815 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1816 struct drm_file *file);
1817 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1818 struct drm_file *file);
1820 /* i915_gem_gtt.c */
1821 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1822 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1823 struct drm_i915_gem_object *obj,
1824 enum i915_cache_level cache_level);
1825 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1826 struct drm_i915_gem_object *obj);
1828 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1829 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1830 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1831 enum i915_cache_level cache_level);
1832 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1833 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1834 void i915_gem_init_global_gtt(struct drm_device *dev);
1835 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1836 unsigned long mappable_end, unsigned long end);
1837 int i915_gem_gtt_init(struct drm_device *dev);
1838 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1840 if (INTEL_INFO(dev)->gen < 6)
1841 intel_gtt_chipset_flush();
1845 /* i915_gem_evict.c */
1846 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1848 unsigned cache_level,
1851 int i915_gem_evict_everything(struct drm_device *dev);
1853 /* i915_gem_stolen.c */
1854 int i915_gem_init_stolen(struct drm_device *dev);
1855 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1856 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1857 void i915_gem_cleanup_stolen(struct drm_device *dev);
1858 struct drm_i915_gem_object *
1859 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1860 struct drm_i915_gem_object *
1861 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1865 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1867 /* i915_gem_tiling.c */
1868 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1870 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1872 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1873 obj->tiling_mode != I915_TILING_NONE;
1876 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1877 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1878 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1880 /* i915_gem_debug.c */
1881 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1882 const char *where, uint32_t mark);
1884 int i915_verify_lists(struct drm_device *dev);
1886 #define i915_verify_lists(dev) 0
1888 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1890 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1891 const char *where, uint32_t mark);
1893 /* i915_debugfs.c */
1894 int i915_debugfs_init(struct drm_minor *minor);
1895 void i915_debugfs_cleanup(struct drm_minor *minor);
1897 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
1899 /* i915_suspend.c */
1900 extern int i915_save_state(struct drm_device *dev);
1901 extern int i915_restore_state(struct drm_device *dev);
1904 void i915_save_display_reg(struct drm_device *dev);
1905 void i915_restore_display_reg(struct drm_device *dev);
1908 void i915_setup_sysfs(struct drm_device *dev_priv);
1909 void i915_teardown_sysfs(struct drm_device *dev_priv);
1912 extern int intel_setup_gmbus(struct drm_device *dev);
1913 extern void intel_teardown_gmbus(struct drm_device *dev);
1914 static inline bool intel_gmbus_is_port_valid(unsigned port)
1916 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1919 extern struct i2c_adapter *intel_gmbus_get_adapter(
1920 struct drm_i915_private *dev_priv, unsigned port);
1921 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1922 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1923 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1925 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1927 extern void intel_i2c_reset(struct drm_device *dev);
1929 /* intel_opregion.c */
1930 extern int intel_opregion_setup(struct drm_device *dev);
1932 extern void intel_opregion_init(struct drm_device *dev);
1933 extern void intel_opregion_fini(struct drm_device *dev);
1934 extern void intel_opregion_asle_intr(struct drm_device *dev);
1936 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1937 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1938 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1943 extern void intel_register_dsm_handler(void);
1944 extern void intel_unregister_dsm_handler(void);
1946 static inline void intel_register_dsm_handler(void) { return; }
1947 static inline void intel_unregister_dsm_handler(void) { return; }
1948 #endif /* CONFIG_ACPI */
1951 extern void intel_modeset_init_hw(struct drm_device *dev);
1952 extern void intel_modeset_suspend_hw(struct drm_device *dev);
1953 extern void intel_modeset_init(struct drm_device *dev);
1954 extern void intel_modeset_gem_init(struct drm_device *dev);
1955 extern void intel_modeset_cleanup(struct drm_device *dev);
1956 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1957 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1958 bool force_restore);
1959 extern void i915_redisable_vga(struct drm_device *dev);
1960 extern bool intel_fbc_enabled(struct drm_device *dev);
1961 extern void intel_disable_fbc(struct drm_device *dev);
1962 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1963 extern void intel_init_pch_refclk(struct drm_device *dev);
1964 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1965 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1966 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
1967 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
1968 extern void intel_detect_pch(struct drm_device *dev);
1969 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1970 extern int intel_enable_rc6(const struct drm_device *dev);
1972 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1973 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1974 struct drm_file *file);
1977 #ifdef CONFIG_DEBUG_FS
1978 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1979 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
1980 struct intel_overlay_error_state *error);
1982 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1983 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
1984 struct drm_device *dev,
1985 struct intel_display_error_state *error);
1988 /* On SNB platform, before reading ring registers forcewake bit
1989 * must be set to prevent GT core from power down and stale values being
1992 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1993 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1994 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1996 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1997 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1999 /* intel_sideband.c */
2000 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2001 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2002 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2003 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
2004 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
2005 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2006 enum intel_sbi_destination destination);
2007 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2008 enum intel_sbi_destination destination);
2010 int vlv_gpu_freq(int ddr_freq, int val);
2011 int vlv_freq_opcode(int ddr_freq, int val);
2013 #define __i915_read(x, y) \
2014 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
2022 #define __i915_write(x, y) \
2023 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
2031 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
2032 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2034 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
2035 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2036 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2037 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2039 #define I915_READ(reg) i915_read32(dev_priv, (reg))
2040 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
2041 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2042 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
2044 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2045 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
2047 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2048 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2050 /* "Broadcast RGB" property */
2051 #define INTEL_BROADCAST_RGB_AUTO 0
2052 #define INTEL_BROADCAST_RGB_FULL 1
2053 #define INTEL_BROADCAST_RGB_LIMITED 2
2055 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2057 if (HAS_PCH_SPLIT(dev))
2058 return CPU_VGACNTRL;
2059 else if (IS_VALLEYVIEW(dev))
2060 return VLV_VGACNTRL;
2065 static inline void __user *to_user_ptr(u64 address)
2067 return (void __user *)(uintptr_t)address;