1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain {
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP,
108 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
110 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
111 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
112 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
113 #define POWER_DOMAIN_TRANSCODER(tran) \
114 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
115 (tran) + POWER_DOMAIN_TRANSCODER_A)
117 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
118 BIT(POWER_DOMAIN_PIPE_A) | \
119 BIT(POWER_DOMAIN_TRANSCODER_EDP))
120 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
121 BIT(POWER_DOMAIN_PIPE_A) | \
122 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
123 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
127 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
128 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
138 #define I915_GEM_GPU_DOMAINS \
139 (I915_GEM_DOMAIN_RENDER | \
140 I915_GEM_DOMAIN_SAMPLER | \
141 I915_GEM_DOMAIN_COMMAND | \
142 I915_GEM_DOMAIN_INSTRUCTION | \
143 I915_GEM_DOMAIN_VERTEX)
145 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
147 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
148 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
149 if ((intel_encoder)->base.crtc == (__crtc))
151 struct drm_i915_private;
154 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
155 /* real shared dpll ids must be >= 0 */
159 #define I915_NUM_PLLS 2
161 struct intel_dpll_hw_state {
168 struct intel_shared_dpll {
169 int refcount; /* count of number of CRTCs sharing this PLL */
170 int active; /* count of number of active CRTCs (i.e. DPMS on) */
171 bool on; /* is the PLL actually active? Disabled during modeset */
173 /* should match the index in the dev_priv->shared_dplls array */
174 enum intel_dpll_id id;
175 struct intel_dpll_hw_state hw_state;
176 void (*mode_set)(struct drm_i915_private *dev_priv,
177 struct intel_shared_dpll *pll);
178 void (*enable)(struct drm_i915_private *dev_priv,
179 struct intel_shared_dpll *pll);
180 void (*disable)(struct drm_i915_private *dev_priv,
181 struct intel_shared_dpll *pll);
182 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
183 struct intel_shared_dpll *pll,
184 struct intel_dpll_hw_state *hw_state);
187 /* Used by dp and fdi links */
188 struct intel_link_m_n {
196 void intel_link_compute_m_n(int bpp, int nlanes,
197 int pixel_clock, int link_clock,
198 struct intel_link_m_n *m_n);
200 struct intel_ddi_plls {
206 /* Interface history:
209 * 1.2: Add Power Management
210 * 1.3: Add vblank support
211 * 1.4: Fix cmdbuffer path, add heap destroy
212 * 1.5: Add vblank pipe configuration
213 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
214 * - Support vertical blank on secondary display pipe
216 #define DRIVER_MAJOR 1
217 #define DRIVER_MINOR 6
218 #define DRIVER_PATCHLEVEL 0
220 #define WATCH_LISTS 0
223 #define I915_GEM_PHYS_CURSOR_0 1
224 #define I915_GEM_PHYS_CURSOR_1 2
225 #define I915_GEM_PHYS_OVERLAY_REGS 3
226 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
228 struct drm_i915_gem_phys_object {
230 struct page **page_list;
231 drm_dma_handle_t *handle;
232 struct drm_i915_gem_object *cur_obj;
235 struct opregion_header;
236 struct opregion_acpi;
237 struct opregion_swsci;
238 struct opregion_asle;
240 struct intel_opregion {
241 struct opregion_header __iomem *header;
242 struct opregion_acpi __iomem *acpi;
243 struct opregion_swsci __iomem *swsci;
244 u32 swsci_gbda_sub_functions;
245 u32 swsci_sbcb_sub_functions;
246 struct opregion_asle __iomem *asle;
248 u32 __iomem *lid_state;
250 #define OPREGION_SIZE (8*1024)
252 struct intel_overlay;
253 struct intel_overlay_error_state;
255 struct drm_i915_master_private {
256 drm_local_map_t *sarea;
257 struct _drm_i915_sarea *sarea_priv;
259 #define I915_FENCE_REG_NONE -1
260 #define I915_MAX_NUM_FENCES 32
261 /* 32 fences + sign bit for FENCE_REG_NONE */
262 #define I915_MAX_NUM_FENCE_BITS 6
264 struct drm_i915_fence_reg {
265 struct list_head lru_list;
266 struct drm_i915_gem_object *obj;
270 struct sdvo_device_mapping {
279 struct intel_display_error_state;
281 struct drm_i915_error_state {
289 bool waiting[I915_NUM_RINGS];
290 u32 pipestat[I915_MAX_PIPES];
291 u32 tail[I915_NUM_RINGS];
292 u32 head[I915_NUM_RINGS];
293 u32 ctl[I915_NUM_RINGS];
294 u32 ipeir[I915_NUM_RINGS];
295 u32 ipehr[I915_NUM_RINGS];
296 u32 instdone[I915_NUM_RINGS];
297 u32 acthd[I915_NUM_RINGS];
298 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
299 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
300 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
301 /* our own tracking of ring head and tail */
302 u32 cpu_ring_head[I915_NUM_RINGS];
303 u32 cpu_ring_tail[I915_NUM_RINGS];
304 u32 error; /* gen6+ */
305 u32 err_int; /* gen7 */
306 u32 bbstate[I915_NUM_RINGS];
307 u32 instpm[I915_NUM_RINGS];
308 u32 instps[I915_NUM_RINGS];
309 u32 extra_instdone[I915_NUM_INSTDONE_REG];
310 u32 seqno[I915_NUM_RINGS];
312 u32 fault_reg[I915_NUM_RINGS];
314 u32 faddr[I915_NUM_RINGS];
315 u64 fence[I915_MAX_NUM_FENCES];
317 struct drm_i915_error_ring {
318 struct drm_i915_error_object {
322 } *ringbuffer, *batchbuffer, *ctx;
323 struct drm_i915_error_request {
329 } ring[I915_NUM_RINGS];
330 struct drm_i915_error_buffer {
337 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
344 } **active_bo, **pinned_bo;
345 u32 *active_bo_count, *pinned_bo_count;
346 struct intel_overlay_error_state *overlay;
347 struct intel_display_error_state *display;
348 int hangcheck_score[I915_NUM_RINGS];
349 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
352 struct intel_crtc_config;
357 struct drm_i915_display_funcs {
358 bool (*fbc_enabled)(struct drm_device *dev);
359 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
360 void (*disable_fbc)(struct drm_device *dev);
361 int (*get_display_clock_speed)(struct drm_device *dev);
362 int (*get_fifo_size)(struct drm_device *dev, int plane);
364 * find_dpll() - Find the best values for the PLL
365 * @limit: limits for the PLL
366 * @crtc: current CRTC
367 * @target: target frequency in kHz
368 * @refclk: reference clock frequency in kHz
369 * @match_clock: if provided, @best_clock P divider must
370 * match the P divider from @match_clock
371 * used for LVDS downclocking
372 * @best_clock: best PLL values found
374 * Returns true on success, false on failure.
376 bool (*find_dpll)(const struct intel_limit *limit,
377 struct drm_crtc *crtc,
378 int target, int refclk,
379 struct dpll *match_clock,
380 struct dpll *best_clock);
381 void (*update_wm)(struct drm_crtc *crtc);
382 void (*update_sprite_wm)(struct drm_plane *plane,
383 struct drm_crtc *crtc,
384 uint32_t sprite_width, int pixel_size,
385 bool enable, bool scaled);
386 void (*modeset_global_resources)(struct drm_device *dev);
387 /* Returns the active state of the crtc, and if the crtc is active,
388 * fills out the pipe-config with the hw state. */
389 bool (*get_pipe_config)(struct intel_crtc *,
390 struct intel_crtc_config *);
391 int (*crtc_mode_set)(struct drm_crtc *crtc,
393 struct drm_framebuffer *old_fb);
394 void (*crtc_enable)(struct drm_crtc *crtc);
395 void (*crtc_disable)(struct drm_crtc *crtc);
396 void (*off)(struct drm_crtc *crtc);
397 void (*write_eld)(struct drm_connector *connector,
398 struct drm_crtc *crtc,
399 struct drm_display_mode *mode);
400 void (*fdi_link_train)(struct drm_crtc *crtc);
401 void (*init_clock_gating)(struct drm_device *dev);
402 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
403 struct drm_framebuffer *fb,
404 struct drm_i915_gem_object *obj,
406 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
408 void (*hpd_irq_setup)(struct drm_device *dev);
409 /* clock updates for mode set */
411 /* render clock increase/decrease */
412 /* display clock increase/decrease */
413 /* pll clock increase/decrease */
416 struct intel_uncore_funcs {
417 void (*force_wake_get)(struct drm_i915_private *dev_priv);
418 void (*force_wake_put)(struct drm_i915_private *dev_priv);
420 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
421 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
422 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
423 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
425 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
426 uint8_t val, bool trace);
427 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
428 uint16_t val, bool trace);
429 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
430 uint32_t val, bool trace);
431 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
432 uint64_t val, bool trace);
435 struct intel_uncore {
436 spinlock_t lock; /** lock is also taken in irq contexts. */
438 struct intel_uncore_funcs funcs;
441 unsigned forcewake_count;
443 struct delayed_work force_wake_work;
446 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
447 func(is_mobile) sep \
450 func(is_i945gm) sep \
452 func(need_gfx_hws) sep \
454 func(is_pineview) sep \
455 func(is_broadwater) sep \
456 func(is_crestline) sep \
457 func(is_ivybridge) sep \
458 func(is_valleyview) sep \
459 func(is_haswell) sep \
460 func(is_preliminary) sep \
462 func(has_pipe_cxsr) sep \
463 func(has_hotplug) sep \
464 func(cursor_needs_physical) sep \
465 func(has_overlay) sep \
466 func(overlay_needs_physical) sep \
467 func(supports_tv) sep \
472 #define DEFINE_FLAG(name) u8 name:1
473 #define SEP_SEMICOLON ;
475 struct intel_device_info {
476 u32 display_mmio_offset;
479 u8 ring_mask; /* Rings supported by the HW */
480 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
486 enum i915_cache_level {
488 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
489 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
490 caches, eg sampler/render caches, and the
491 large Last-Level-Cache. LLC is coherent with
492 the CPU, but L3 is only visible to the GPU. */
493 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
496 typedef uint32_t gen6_gtt_pte_t;
498 struct i915_address_space {
500 struct drm_device *dev;
501 struct list_head global_link;
502 unsigned long start; /* Start offset always 0 for dri2 */
503 size_t total; /* size addr space maps (ex. 2GB for ggtt) */
511 * List of objects currently involved in rendering.
513 * Includes buffers having the contents of their GPU caches
514 * flushed, not necessarily primitives. last_rendering_seqno
515 * represents when the rendering involved will be completed.
517 * A reference is held on the buffer while on this list.
519 struct list_head active_list;
522 * LRU list of objects which are not in the ringbuffer and
523 * are ready to unbind, but are still in the GTT.
525 * last_rendering_seqno is 0 while an object is in this list.
527 * A reference is not held on the buffer while on this list,
528 * as merely being GTT-bound shouldn't prevent its being
529 * freed, and we'll pull it off the list in the free path.
531 struct list_head inactive_list;
533 /* FIXME: Need a more generic return type */
534 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
535 enum i915_cache_level level,
536 bool valid); /* Create a valid PTE */
537 void (*clear_range)(struct i915_address_space *vm,
538 unsigned int first_entry,
539 unsigned int num_entries,
541 void (*insert_entries)(struct i915_address_space *vm,
543 unsigned int first_entry,
544 enum i915_cache_level cache_level);
545 void (*cleanup)(struct i915_address_space *vm);
548 /* The Graphics Translation Table is the way in which GEN hardware translates a
549 * Graphics Virtual Address into a Physical Address. In addition to the normal
550 * collateral associated with any va->pa translations GEN hardware also has a
551 * portion of the GTT which can be mapped by the CPU and remain both coherent
552 * and correct (in cases like swizzling). That region is referred to as GMADR in
556 struct i915_address_space base;
557 size_t stolen_size; /* Total size of stolen memory */
559 unsigned long mappable_end; /* End offset that we can CPU map */
560 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
561 phys_addr_t mappable_base; /* PA of our GMADR */
563 /** "Graphics Stolen Memory" holds the global PTEs */
571 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
572 size_t *stolen, phys_addr_t *mappable_base,
573 unsigned long *mappable_end);
575 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
577 struct i915_hw_ppgtt {
578 struct i915_address_space base;
579 unsigned num_pd_entries;
581 struct page **pt_pages;
582 struct page *gen8_pt_pages;
584 struct page *pd_pages;
589 dma_addr_t pd_dma_addr[4];
592 dma_addr_t *pt_dma_addr;
593 dma_addr_t *gen8_pt_dma_addr[4];
595 int (*enable)(struct drm_device *dev);
599 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
600 * VMA's presence cannot be guaranteed before binding, or after unbinding the
601 * object into/from the address space.
603 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
604 * will always be <= an objects lifetime. So object refcounting should cover us.
607 struct drm_mm_node node;
608 struct drm_i915_gem_object *obj;
609 struct i915_address_space *vm;
611 /** This object's place on the active/inactive lists */
612 struct list_head mm_list;
614 struct list_head vma_link; /* Link in the object's VMA list */
616 /** This vma's place in the batchbuffer or on the eviction list */
617 struct list_head exec_list;
620 * Used for performing relocations during execbuffer insertion.
622 struct hlist_node exec_node;
623 unsigned long exec_handle;
624 struct drm_i915_gem_exec_object2 *exec_entry;
628 struct i915_ctx_hang_stats {
629 /* This context had batch pending when hang was declared */
630 unsigned batch_pending;
632 /* This context had batch active when hang was declared */
633 unsigned batch_active;
635 /* Time when this context was last blamed for a GPU reset */
636 unsigned long guilty_ts;
638 /* This context is banned to submit more work */
642 /* This must match up with the value previously used for execbuf2.rsvd1. */
643 #define DEFAULT_CONTEXT_ID 0
644 struct i915_hw_context {
649 struct drm_i915_file_private *file_priv;
650 struct intel_ring_buffer *ring;
651 struct drm_i915_gem_object *obj;
652 struct i915_ctx_hang_stats hang_stats;
654 struct list_head link;
663 struct drm_mm_node *compressed_fb;
664 struct drm_mm_node *compressed_llb;
666 struct intel_fbc_work {
667 struct delayed_work work;
668 struct drm_crtc *crtc;
669 struct drm_framebuffer *fb;
674 FBC_OK, /* FBC is enabled */
675 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
676 FBC_NO_OUTPUT, /* no outputs enabled to compress */
677 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
678 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
679 FBC_MODE_TOO_LARGE, /* mode too large for compression */
680 FBC_BAD_PLANE, /* fbc not supported on plane */
681 FBC_NOT_TILED, /* buffer not tiled */
682 FBC_MULTIPLE_PIPES, /* more than one pipe active */
684 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
694 PCH_NONE = 0, /* No PCH present */
695 PCH_IBX, /* Ibexpeak PCH */
696 PCH_CPT, /* Cougarpoint PCH */
697 PCH_LPT, /* Lynxpoint PCH */
701 enum intel_sbi_destination {
706 #define QUIRK_PIPEA_FORCE (1<<0)
707 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
708 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
709 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
712 struct intel_fbc_work;
715 struct i2c_adapter adapter;
719 struct i2c_algo_bit_data bit_algo;
720 struct drm_i915_private *dev_priv;
723 struct i915_suspend_saved_registers {
744 u32 saveTRANS_HTOTAL_A;
745 u32 saveTRANS_HBLANK_A;
746 u32 saveTRANS_HSYNC_A;
747 u32 saveTRANS_VTOTAL_A;
748 u32 saveTRANS_VBLANK_A;
749 u32 saveTRANS_VSYNC_A;
757 u32 savePFIT_PGM_RATIOS;
758 u32 saveBLC_HIST_CTL;
760 u32 saveBLC_PWM_CTL2;
761 u32 saveBLC_CPU_PWM_CTL;
762 u32 saveBLC_CPU_PWM_CTL2;
775 u32 saveTRANS_HTOTAL_B;
776 u32 saveTRANS_HBLANK_B;
777 u32 saveTRANS_HSYNC_B;
778 u32 saveTRANS_VTOTAL_B;
779 u32 saveTRANS_VBLANK_B;
780 u32 saveTRANS_VSYNC_B;
794 u32 savePP_ON_DELAYS;
795 u32 savePP_OFF_DELAYS;
803 u32 savePFIT_CONTROL;
804 u32 save_palette_a[256];
805 u32 save_palette_b[256];
806 u32 saveDPFC_CB_BASE;
807 u32 saveFBC_CFB_BASE;
810 u32 saveFBC_CONTROL2;
820 u32 saveCACHE_MODE_0;
821 u32 saveMI_ARB_STATE;
832 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
843 u32 savePIPEA_GMCH_DATA_M;
844 u32 savePIPEB_GMCH_DATA_M;
845 u32 savePIPEA_GMCH_DATA_N;
846 u32 savePIPEB_GMCH_DATA_N;
847 u32 savePIPEA_DP_LINK_M;
848 u32 savePIPEB_DP_LINK_M;
849 u32 savePIPEA_DP_LINK_N;
850 u32 savePIPEB_DP_LINK_N;
861 u32 savePCH_DREF_CONTROL;
862 u32 saveDISP_ARB_CTL;
863 u32 savePIPEA_DATA_M1;
864 u32 savePIPEA_DATA_N1;
865 u32 savePIPEA_LINK_M1;
866 u32 savePIPEA_LINK_N1;
867 u32 savePIPEB_DATA_M1;
868 u32 savePIPEB_DATA_N1;
869 u32 savePIPEB_LINK_M1;
870 u32 savePIPEB_LINK_N1;
871 u32 saveMCHBAR_RENDER_STANDBY;
872 u32 savePCH_PORT_HOTPLUG;
875 struct intel_gen6_power_mgmt {
876 /* work and pm_iir are protected by dev_priv->irq_lock */
877 struct work_struct work;
880 /* The below variables an all the rps hw state are protected by
881 * dev->struct mutext. */
891 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
894 struct delayed_work delayed_resume_work;
897 * Protects RPS/RC6 register access and PCU communication.
898 * Must be taken after struct_mutex if nested.
900 struct mutex hw_lock;
903 /* defined intel_pm.c */
904 extern spinlock_t mchdev_lock;
906 struct intel_ilk_power_mgmt {
914 unsigned long last_time1;
915 unsigned long chipset_power;
917 struct timespec last_time2;
918 unsigned long gfx_power;
924 struct drm_i915_gem_object *pwrctx;
925 struct drm_i915_gem_object *renderctx;
928 /* Power well structure for haswell */
929 struct i915_power_well {
930 /* power well enable/disable usage count */
934 #define I915_MAX_POWER_WELLS 1
936 struct i915_power_domains {
938 * Power wells needed for initialization at driver init and suspend
939 * time are on. They are kept on until after the first modeset.
944 struct i915_power_well power_wells[I915_MAX_POWER_WELLS];
947 struct i915_dri1_state {
948 unsigned allow_batchbuffer : 1;
949 u32 __iomem *gfx_hws_cpu_addr;
960 struct i915_ums_state {
962 * Flag if the X Server, and thus DRM, is not currently in
963 * control of the device.
965 * This is set between LeaveVT and EnterVT. It needs to be
966 * replaced with a semaphore. It also needs to be
967 * transitioned away from for kernel modesetting.
972 #define MAX_L3_SLICES 2
973 struct intel_l3_parity {
974 u32 *remap_info[MAX_L3_SLICES];
975 struct work_struct error_work;
980 /** Memory allocator for GTT stolen memory */
981 struct drm_mm stolen;
982 /** List of all objects in gtt_space. Used to restore gtt
983 * mappings on resume */
984 struct list_head bound_list;
986 * List of objects which are not bound to the GTT (thus
987 * are idle and not used by the GPU) but still have
988 * (presumably uncached) pages still attached.
990 struct list_head unbound_list;
992 /** Usable portion of the GTT for GEM */
993 unsigned long stolen_base; /* limited to low memory (32-bit) */
995 /** PPGTT used for aliasing the PPGTT with the GTT */
996 struct i915_hw_ppgtt *aliasing_ppgtt;
998 struct shrinker inactive_shrinker;
999 bool shrinker_no_lock_stealing;
1001 /** LRU list of objects with fence regs on them. */
1002 struct list_head fence_list;
1005 * We leave the user IRQ off as much as possible,
1006 * but this means that requests will finish and never
1007 * be retired once the system goes idle. Set a timer to
1008 * fire periodically while the ring is running. When it
1009 * fires, go retire requests.
1011 struct delayed_work retire_work;
1014 * When we detect an idle GPU, we want to turn on
1015 * powersaving features. So once we see that there
1016 * are no more requests outstanding and no more
1017 * arrive within a small period of time, we fire
1018 * off the idle_work.
1020 struct delayed_work idle_work;
1023 * Are we in a non-interruptible section of code like
1028 /** Bit 6 swizzling required for X tiling */
1029 uint32_t bit_6_swizzle_x;
1030 /** Bit 6 swizzling required for Y tiling */
1031 uint32_t bit_6_swizzle_y;
1033 /* storage for physical objects */
1034 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1036 /* accounting, useful for userland debugging */
1037 spinlock_t object_stat_lock;
1038 size_t object_memory;
1042 struct drm_i915_error_state_buf {
1051 struct i915_error_state_file_priv {
1052 struct drm_device *dev;
1053 struct drm_i915_error_state *error;
1056 struct i915_gpu_error {
1057 /* For hangcheck timer */
1058 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1059 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1060 /* Hang gpu twice in this window and your context gets banned */
1061 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1063 struct timer_list hangcheck_timer;
1065 /* For reset and error_state handling. */
1067 /* Protected by the above dev->gpu_error.lock. */
1068 struct drm_i915_error_state *first_error;
1069 struct work_struct work;
1072 unsigned long missed_irq_rings;
1075 * State variable and reset counter controlling the reset flow
1077 * Upper bits are for the reset counter. This counter is used by the
1078 * wait_seqno code to race-free noticed that a reset event happened and
1079 * that it needs to restart the entire ioctl (since most likely the
1080 * seqno it waited for won't ever signal anytime soon).
1082 * This is important for lock-free wait paths, where no contended lock
1083 * naturally enforces the correct ordering between the bail-out of the
1084 * waiter and the gpu reset work code.
1086 * Lowest bit controls the reset state machine: Set means a reset is in
1087 * progress. This state will (presuming we don't have any bugs) decay
1088 * into either unset (successful reset) or the special WEDGED value (hw
1089 * terminally sour). All waiters on the reset_queue will be woken when
1092 atomic_t reset_counter;
1095 * Special values/flags for reset_counter
1097 * Note that the code relies on
1098 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1101 #define I915_RESET_IN_PROGRESS_FLAG 1
1102 #define I915_WEDGED 0xffffffff
1105 * Waitqueue to signal when the reset has completed. Used by clients
1106 * that wait for dev_priv->mm.wedged to settle.
1108 wait_queue_head_t reset_queue;
1110 /* For gpu hang simulation. */
1111 unsigned int stop_rings;
1113 /* For missed irq/seqno simulation. */
1114 unsigned int test_irq_rings;
1117 enum modeset_restore {
1118 MODESET_ON_LID_OPEN,
1123 struct ddi_vbt_port_info {
1124 uint8_t hdmi_level_shift;
1126 uint8_t supports_dvi:1;
1127 uint8_t supports_hdmi:1;
1128 uint8_t supports_dp:1;
1131 struct intel_vbt_data {
1132 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1133 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1136 unsigned int int_tv_support:1;
1137 unsigned int lvds_dither:1;
1138 unsigned int lvds_vbt:1;
1139 unsigned int int_crt_support:1;
1140 unsigned int lvds_use_ssc:1;
1141 unsigned int display_clock_mode:1;
1142 unsigned int fdi_rx_polarity_inverted:1;
1144 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1149 int edp_preemphasis;
1151 bool edp_initialized;
1154 struct edp_power_seq edp_pps;
1164 union child_device_config *child_dev;
1166 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1169 enum intel_ddb_partitioning {
1171 INTEL_DDB_PART_5_6, /* IVB+ */
1174 struct intel_wm_level {
1182 struct hsw_wm_values {
1183 uint32_t wm_pipe[3];
1185 uint32_t wm_lp_spr[3];
1186 uint32_t wm_linetime[3];
1188 enum intel_ddb_partitioning partitioning;
1192 * This struct tracks the state needed for the Package C8+ feature.
1194 * Package states C8 and deeper are really deep PC states that can only be
1195 * reached when all the devices on the system allow it, so even if the graphics
1196 * device allows PC8+, it doesn't mean the system will actually get to these
1199 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1200 * is disabled and the GPU is idle. When these conditions are met, we manually
1201 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1204 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1205 * the state of some registers, so when we come back from PC8+ we need to
1206 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1207 * need to take care of the registers kept by RC6.
1209 * The interrupt disabling is part of the requirements. We can only leave the
1210 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1211 * can lock the machine.
1213 * Ideally every piece of our code that needs PC8+ disabled would call
1214 * hsw_disable_package_c8, which would increment disable_count and prevent the
1215 * system from reaching PC8+. But we don't have a symmetric way to do this for
1216 * everything, so we have the requirements_met and gpu_idle variables. When we
1217 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1218 * increase it in the opposite case. The requirements_met variable is true when
1219 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1220 * variable is true when the GPU is idle.
1222 * In addition to everything, we only actually enable PC8+ if disable_count
1223 * stays at zero for at least some seconds. This is implemented with the
1224 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1225 * consecutive times when all screens are disabled and some background app
1226 * queries the state of our connectors, or we have some application constantly
1227 * waking up to use the GPU. Only after the enable_work function actually
1228 * enables PC8+ the "enable" variable will become true, which means that it can
1229 * be false even if disable_count is 0.
1231 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1232 * goes back to false exactly before we reenable the IRQs. We use this variable
1233 * to check if someone is trying to enable/disable IRQs while they're supposed
1234 * to be disabled. This shouldn't happen and we'll print some error messages in
1235 * case it happens, but if it actually happens we'll also update the variables
1236 * inside struct regsave so when we restore the IRQs they will contain the
1237 * latest expected values.
1239 * For more, read "Display Sequences for Package C8" on our documentation.
1241 struct i915_package_c8 {
1242 bool requirements_met;
1245 /* Only true after the delayed work task actually enables it. */
1249 struct delayed_work enable_work;
1256 uint32_t gen6_pmimr;
1260 enum intel_pipe_crc_source {
1261 INTEL_PIPE_CRC_SOURCE_NONE,
1262 INTEL_PIPE_CRC_SOURCE_PLANE1,
1263 INTEL_PIPE_CRC_SOURCE_PLANE2,
1264 INTEL_PIPE_CRC_SOURCE_PF,
1265 INTEL_PIPE_CRC_SOURCE_PIPE,
1266 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1267 INTEL_PIPE_CRC_SOURCE_TV,
1268 INTEL_PIPE_CRC_SOURCE_DP_B,
1269 INTEL_PIPE_CRC_SOURCE_DP_C,
1270 INTEL_PIPE_CRC_SOURCE_DP_D,
1271 INTEL_PIPE_CRC_SOURCE_AUTO,
1272 INTEL_PIPE_CRC_SOURCE_MAX,
1275 struct intel_pipe_crc_entry {
1280 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1281 struct intel_pipe_crc {
1283 bool opened; /* exclusive access to the result file */
1284 struct intel_pipe_crc_entry *entries;
1285 enum intel_pipe_crc_source source;
1287 wait_queue_head_t wq;
1290 typedef struct drm_i915_private {
1291 struct drm_device *dev;
1292 struct kmem_cache *slab;
1294 const struct intel_device_info *info;
1296 int relative_constants_mode;
1300 struct intel_uncore uncore;
1302 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1305 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1306 * controller on different i2c buses. */
1307 struct mutex gmbus_mutex;
1310 * Base address of the gmbus and gpio block.
1312 uint32_t gpio_mmio_base;
1314 wait_queue_head_t gmbus_wait_queue;
1316 struct pci_dev *bridge_dev;
1317 struct intel_ring_buffer ring[I915_NUM_RINGS];
1318 uint32_t last_seqno, next_seqno;
1320 drm_dma_handle_t *status_page_dmah;
1321 struct resource mch_res;
1323 atomic_t irq_received;
1325 /* protects the irq masks */
1326 spinlock_t irq_lock;
1328 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1329 struct pm_qos_request pm_qos;
1331 /* DPIO indirect register protection */
1332 struct mutex dpio_lock;
1334 /** Cached value of IMR to avoid reads in updating the bitfield */
1337 u32 de_irq_mask[I915_MAX_PIPES];
1342 struct work_struct hotplug_work;
1343 bool enable_hotplug_processing;
1345 unsigned long hpd_last_jiffies;
1350 HPD_MARK_DISABLED = 2
1352 } hpd_stats[HPD_NUM_PINS];
1354 struct timer_list hotplug_reenable_timer;
1358 struct i915_fbc fbc;
1359 struct intel_opregion opregion;
1360 struct intel_vbt_data vbt;
1363 struct intel_overlay *overlay;
1364 unsigned int sprite_scaling_enabled;
1370 spinlock_t lock; /* bl registers and the above bl fields */
1371 struct backlight_device *device;
1375 bool no_aux_handshake;
1377 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1378 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1379 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1381 unsigned int fsb_freq, mem_freq, is_ddr3;
1384 * wq - Driver workqueue for GEM.
1386 * NOTE: Work items scheduled here are not allowed to grab any modeset
1387 * locks, for otherwise the flushing done in the pageflip code will
1388 * result in deadlocks.
1390 struct workqueue_struct *wq;
1392 /* Display functions */
1393 struct drm_i915_display_funcs display;
1395 /* PCH chipset type */
1396 enum intel_pch pch_type;
1397 unsigned short pch_id;
1399 unsigned long quirks;
1401 enum modeset_restore modeset_restore;
1402 struct mutex modeset_restore_lock;
1404 struct list_head vm_list; /* Global list of all address spaces */
1405 struct i915_gtt gtt; /* VMA representing the global address space */
1407 struct i915_gem_mm mm;
1409 /* Kernel Modesetting */
1411 struct sdvo_device_mapping sdvo_mappings[2];
1413 struct drm_crtc *plane_to_crtc_mapping[3];
1414 struct drm_crtc *pipe_to_crtc_mapping[3];
1415 wait_queue_head_t pending_flip_queue;
1417 #ifdef CONFIG_DEBUG_FS
1418 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1421 int num_shared_dpll;
1422 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1423 struct intel_ddi_plls ddi_plls;
1425 /* Reclocking support */
1426 bool render_reclock_avail;
1427 bool lvds_downclock_avail;
1428 /* indicates the reduced downclock for LVDS*/
1432 bool mchbar_need_disable;
1434 struct intel_l3_parity l3_parity;
1436 /* Cannot be determined by PCIID. You must always read a register. */
1439 /* gen6+ rps state */
1440 struct intel_gen6_power_mgmt rps;
1442 /* ilk-only ips/rps state. Everything in here is protected by the global
1443 * mchdev_lock in intel_pm.c */
1444 struct intel_ilk_power_mgmt ips;
1446 struct i915_power_domains power_domains;
1448 struct i915_psr psr;
1450 struct i915_gpu_error gpu_error;
1452 struct drm_i915_gem_object *vlv_pctx;
1454 #ifdef CONFIG_DRM_I915_FBDEV
1455 /* list of fbdev register on this device */
1456 struct intel_fbdev *fbdev;
1460 * The console may be contended at resume, but we don't
1461 * want it to block on it.
1463 struct work_struct console_resume_work;
1465 struct drm_property *broadcast_rgb_property;
1466 struct drm_property *force_audio_property;
1468 bool hw_contexts_disabled;
1469 uint32_t hw_context_size;
1470 struct list_head context_list;
1474 struct i915_suspend_saved_registers regfile;
1478 * Raw watermark latency values:
1479 * in 0.1us units for WM0,
1480 * in 0.5us units for WM1+.
1483 uint16_t pri_latency[5];
1485 uint16_t spr_latency[5];
1487 uint16_t cur_latency[5];
1489 /* current hardware state */
1490 struct hsw_wm_values hw;
1493 struct i915_package_c8 pc8;
1495 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1497 struct i915_dri1_state dri1;
1498 /* Old ums support infrastructure, same warning applies. */
1499 struct i915_ums_state ums;
1500 } drm_i915_private_t;
1502 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1504 return dev->dev_private;
1507 /* Iterate over initialised rings */
1508 #define for_each_ring(ring__, dev_priv__, i__) \
1509 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1510 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1512 enum hdmi_force_audio {
1513 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1514 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1515 HDMI_AUDIO_AUTO, /* trust EDID */
1516 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1519 #define I915_GTT_OFFSET_NONE ((u32)-1)
1521 struct drm_i915_gem_object_ops {
1522 /* Interface between the GEM object and its backing storage.
1523 * get_pages() is called once prior to the use of the associated set
1524 * of pages before to binding them into the GTT, and put_pages() is
1525 * called after we no longer need them. As we expect there to be
1526 * associated cost with migrating pages between the backing storage
1527 * and making them available for the GPU (e.g. clflush), we may hold
1528 * onto the pages after they are no longer referenced by the GPU
1529 * in case they may be used again shortly (for example migrating the
1530 * pages to a different memory domain within the GTT). put_pages()
1531 * will therefore most likely be called when the object itself is
1532 * being released or under memory pressure (where we attempt to
1533 * reap pages for the shrinker).
1535 int (*get_pages)(struct drm_i915_gem_object *);
1536 void (*put_pages)(struct drm_i915_gem_object *);
1539 struct drm_i915_gem_object {
1540 struct drm_gem_object base;
1542 const struct drm_i915_gem_object_ops *ops;
1544 /** List of VMAs backed by this object */
1545 struct list_head vma_list;
1547 /** Stolen memory for this object, instead of being backed by shmem. */
1548 struct drm_mm_node *stolen;
1549 struct list_head global_list;
1551 struct list_head ring_list;
1552 /** Used in execbuf to temporarily hold a ref */
1553 struct list_head obj_exec_link;
1556 * This is set if the object is on the active lists (has pending
1557 * rendering and so a non-zero seqno), and is not set if it i s on
1558 * inactive (ready to be unbound) list.
1560 unsigned int active:1;
1563 * This is set if the object has been written to since last bound
1566 unsigned int dirty:1;
1569 * Fence register bits (if any) for this object. Will be set
1570 * as needed when mapped into the GTT.
1571 * Protected by dev->struct_mutex.
1573 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1576 * Advice: are the backing pages purgeable?
1578 unsigned int madv:2;
1581 * Current tiling mode for the object.
1583 unsigned int tiling_mode:2;
1585 * Whether the tiling parameters for the currently associated fence
1586 * register have changed. Note that for the purposes of tracking
1587 * tiling changes we also treat the unfenced register, the register
1588 * slot that the object occupies whilst it executes a fenced
1589 * command (such as BLT on gen2/3), as a "fence".
1591 unsigned int fence_dirty:1;
1593 /** How many users have pinned this object in GTT space. The following
1594 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1595 * (via user_pin_count), execbuffer (objects are not allowed multiple
1596 * times for the same batchbuffer), and the framebuffer code. When
1597 * switching/pageflipping, the framebuffer code has at most two buffers
1600 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1601 * bits with absolutely no headroom. So use 4 bits. */
1602 unsigned int pin_count:4;
1603 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1606 * Is the object at the current location in the gtt mappable and
1607 * fenceable? Used to avoid costly recalculations.
1609 unsigned int map_and_fenceable:1;
1612 * Whether the current gtt mapping needs to be mappable (and isn't just
1613 * mappable by accident). Track pin and fault separate for a more
1614 * accurate mappable working set.
1616 unsigned int fault_mappable:1;
1617 unsigned int pin_mappable:1;
1618 unsigned int pin_display:1;
1621 * Is the GPU currently using a fence to access this buffer,
1623 unsigned int pending_fenced_gpu_access:1;
1624 unsigned int fenced_gpu_access:1;
1626 unsigned int cache_level:3;
1628 unsigned int has_aliasing_ppgtt_mapping:1;
1629 unsigned int has_global_gtt_mapping:1;
1630 unsigned int has_dma_mapping:1;
1632 struct sg_table *pages;
1633 int pages_pin_count;
1635 /* prime dma-buf support */
1636 void *dma_buf_vmapping;
1639 struct intel_ring_buffer *ring;
1641 /** Breadcrumb of last rendering to the buffer. */
1642 uint32_t last_read_seqno;
1643 uint32_t last_write_seqno;
1644 /** Breadcrumb of last fenced GPU access to the buffer. */
1645 uint32_t last_fenced_seqno;
1647 /** Current tiling stride for the object, if it's tiled. */
1650 /** References from framebuffers, locks out tiling changes. */
1651 unsigned long framebuffer_references;
1653 /** Record of address bit 17 of each page at last unbind. */
1654 unsigned long *bit_17;
1656 /** User space pin count and filp owning the pin */
1657 unsigned long user_pin_count;
1658 struct drm_file *pin_filp;
1660 /** for phy allocated objects */
1661 struct drm_i915_gem_phys_object *phys_obj;
1663 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1665 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1668 * Request queue structure.
1670 * The request queue allows us to note sequence numbers that have been emitted
1671 * and may be associated with active buffers to be retired.
1673 * By keeping this list, we can avoid having to do questionable
1674 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1675 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1677 struct drm_i915_gem_request {
1678 /** On Which ring this request was generated */
1679 struct intel_ring_buffer *ring;
1681 /** GEM sequence number associated with this request. */
1684 /** Position in the ringbuffer of the start of the request */
1687 /** Position in the ringbuffer of the end of the request */
1690 /** Context related to this request */
1691 struct i915_hw_context *ctx;
1693 /** Batch buffer related to this request if any */
1694 struct drm_i915_gem_object *batch_obj;
1696 /** Time at which this request was emitted, in jiffies. */
1697 unsigned long emitted_jiffies;
1699 /** global list entry for this request */
1700 struct list_head list;
1702 struct drm_i915_file_private *file_priv;
1703 /** file_priv list entry for this request */
1704 struct list_head client_list;
1707 struct drm_i915_file_private {
1708 struct drm_i915_private *dev_priv;
1712 struct list_head request_list;
1713 struct delayed_work idle_work;
1715 struct idr context_idr;
1717 struct i915_ctx_hang_stats hang_stats;
1718 atomic_t rps_wait_boost;
1721 #define INTEL_INFO(dev) (to_i915(dev)->info)
1723 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1724 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1725 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1726 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1727 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1728 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1729 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1730 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1731 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1732 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1733 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1734 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1735 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1736 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1737 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1738 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1739 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1740 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1741 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1742 (dev)->pdev->device == 0x0152 || \
1743 (dev)->pdev->device == 0x015a)
1744 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1745 (dev)->pdev->device == 0x0106 || \
1746 (dev)->pdev->device == 0x010A)
1747 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1748 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1749 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1750 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1751 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1752 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1753 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1754 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1755 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1756 ((dev)->pdev->device & 0x00F0) == 0x0020)
1757 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1760 * The genX designation typically refers to the render engine, so render
1761 * capability related checks should use IS_GEN, while display and other checks
1762 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1765 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1766 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1767 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1768 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1769 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1770 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1771 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1773 #define RENDER_RING (1<<RCS)
1774 #define BSD_RING (1<<VCS)
1775 #define BLT_RING (1<<BCS)
1776 #define VEBOX_RING (1<<VECS)
1777 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1778 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1779 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1780 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1781 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1782 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1784 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1785 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1787 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1788 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1790 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1791 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1793 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1794 * rows, which changed the alignment requirements and fence programming.
1796 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1798 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1799 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1800 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1801 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1802 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1804 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1805 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1806 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1808 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1810 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1811 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1812 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1813 #define HAS_PSR(dev) (IS_HASWELL(dev))
1815 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1816 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1817 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1818 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1819 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1820 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1822 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1823 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1824 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1825 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1826 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1827 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1829 /* DPF == dynamic parity feature */
1830 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1831 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1833 #define GT_FREQUENCY_MULTIPLIER 50
1835 #include "i915_trace.h"
1837 extern const struct drm_ioctl_desc i915_ioctls[];
1838 extern int i915_max_ioctl;
1839 extern unsigned int i915_fbpercrtc __always_unused;
1840 extern int i915_panel_ignore_lid __read_mostly;
1841 extern unsigned int i915_powersave __read_mostly;
1842 extern int i915_semaphores __read_mostly;
1843 extern unsigned int i915_lvds_downclock __read_mostly;
1844 extern int i915_lvds_channel_mode __read_mostly;
1845 extern int i915_panel_use_ssc __read_mostly;
1846 extern int i915_vbt_sdvo_panel_type __read_mostly;
1847 extern int i915_enable_rc6 __read_mostly;
1848 extern int i915_enable_fbc __read_mostly;
1849 extern bool i915_enable_hangcheck __read_mostly;
1850 extern int i915_enable_ppgtt __read_mostly;
1851 extern int i915_enable_psr __read_mostly;
1852 extern unsigned int i915_preliminary_hw_support __read_mostly;
1853 extern int i915_disable_power_well __read_mostly;
1854 extern int i915_enable_ips __read_mostly;
1855 extern bool i915_fastboot __read_mostly;
1856 extern int i915_enable_pc8 __read_mostly;
1857 extern int i915_pc8_timeout __read_mostly;
1858 extern bool i915_prefault_disable __read_mostly;
1860 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1861 extern int i915_resume(struct drm_device *dev);
1862 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1863 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1866 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1867 extern void i915_kernel_lost_context(struct drm_device * dev);
1868 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1869 extern int i915_driver_unload(struct drm_device *);
1870 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1871 extern void i915_driver_lastclose(struct drm_device * dev);
1872 extern void i915_driver_preclose(struct drm_device *dev,
1873 struct drm_file *file_priv);
1874 extern void i915_driver_postclose(struct drm_device *dev,
1875 struct drm_file *file_priv);
1876 extern int i915_driver_device_is_agp(struct drm_device * dev);
1877 #ifdef CONFIG_COMPAT
1878 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1881 extern int i915_emit_box(struct drm_device *dev,
1882 struct drm_clip_rect *box,
1884 extern int intel_gpu_reset(struct drm_device *dev);
1885 extern int i915_reset(struct drm_device *dev);
1886 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1887 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1888 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1889 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1891 extern void intel_console_resume(struct work_struct *work);
1894 void i915_queue_hangcheck(struct drm_device *dev);
1895 void i915_handle_error(struct drm_device *dev, bool wedged);
1897 extern void intel_irq_init(struct drm_device *dev);
1898 extern void intel_pm_init(struct drm_device *dev);
1899 extern void intel_hpd_init(struct drm_device *dev);
1900 extern void intel_pm_init(struct drm_device *dev);
1902 extern void intel_uncore_sanitize(struct drm_device *dev);
1903 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1904 extern void intel_uncore_init(struct drm_device *dev);
1905 extern void intel_uncore_clear_errors(struct drm_device *dev);
1906 extern void intel_uncore_check_errors(struct drm_device *dev);
1907 extern void intel_uncore_fini(struct drm_device *dev);
1910 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1913 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask);
1916 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1917 struct drm_file *file_priv);
1918 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1919 struct drm_file *file_priv);
1920 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1921 struct drm_file *file_priv);
1922 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1923 struct drm_file *file_priv);
1924 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1925 struct drm_file *file_priv);
1926 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1927 struct drm_file *file_priv);
1928 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1929 struct drm_file *file_priv);
1930 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1931 struct drm_file *file_priv);
1932 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1933 struct drm_file *file_priv);
1934 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1935 struct drm_file *file_priv);
1936 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1937 struct drm_file *file_priv);
1938 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1939 struct drm_file *file_priv);
1940 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1941 struct drm_file *file_priv);
1942 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1943 struct drm_file *file);
1944 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1945 struct drm_file *file);
1946 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1947 struct drm_file *file_priv);
1948 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1949 struct drm_file *file_priv);
1950 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1951 struct drm_file *file_priv);
1952 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1953 struct drm_file *file_priv);
1954 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1955 struct drm_file *file_priv);
1956 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1957 struct drm_file *file_priv);
1958 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1959 struct drm_file *file_priv);
1960 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1961 struct drm_file *file_priv);
1962 void i915_gem_load(struct drm_device *dev);
1963 void *i915_gem_object_alloc(struct drm_device *dev);
1964 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1965 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1966 const struct drm_i915_gem_object_ops *ops);
1967 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1969 void i915_gem_free_object(struct drm_gem_object *obj);
1970 void i915_gem_vma_destroy(struct i915_vma *vma);
1972 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1973 struct i915_address_space *vm,
1975 bool map_and_fenceable,
1977 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1978 int __must_check i915_vma_unbind(struct i915_vma *vma);
1979 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
1980 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1981 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1982 void i915_gem_lastclose(struct drm_device *dev);
1984 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1985 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1987 struct sg_page_iter sg_iter;
1989 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1990 return sg_page_iter_page(&sg_iter);
1994 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1996 BUG_ON(obj->pages == NULL);
1997 obj->pages_pin_count++;
1999 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2001 BUG_ON(obj->pages_pin_count == 0);
2002 obj->pages_pin_count--;
2005 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2006 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2007 struct intel_ring_buffer *to);
2008 void i915_vma_move_to_active(struct i915_vma *vma,
2009 struct intel_ring_buffer *ring);
2010 int i915_gem_dumb_create(struct drm_file *file_priv,
2011 struct drm_device *dev,
2012 struct drm_mode_create_dumb *args);
2013 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2014 uint32_t handle, uint64_t *offset);
2016 * Returns true if seq1 is later than seq2.
2019 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2021 return (int32_t)(seq1 - seq2) >= 0;
2024 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2025 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2026 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2027 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2030 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2032 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2033 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2034 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2041 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2043 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2044 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2045 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2046 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2050 bool i915_gem_retire_requests(struct drm_device *dev);
2051 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2052 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2053 bool interruptible);
2054 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2056 return unlikely(atomic_read(&error->reset_counter)
2057 & I915_RESET_IN_PROGRESS_FLAG);
2060 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2062 return atomic_read(&error->reset_counter) == I915_WEDGED;
2065 void i915_gem_reset(struct drm_device *dev);
2066 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2067 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2068 int __must_check i915_gem_init(struct drm_device *dev);
2069 int __must_check i915_gem_init_hw(struct drm_device *dev);
2070 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2071 void i915_gem_init_swizzling(struct drm_device *dev);
2072 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2073 int __must_check i915_gpu_idle(struct drm_device *dev);
2074 int __must_check i915_gem_suspend(struct drm_device *dev);
2075 int __i915_add_request(struct intel_ring_buffer *ring,
2076 struct drm_file *file,
2077 struct drm_i915_gem_object *batch_obj,
2079 #define i915_add_request(ring, seqno) \
2080 __i915_add_request(ring, NULL, NULL, seqno)
2081 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2083 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2085 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2088 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2090 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2092 struct intel_ring_buffer *pipelined);
2093 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2094 int i915_gem_attach_phys_object(struct drm_device *dev,
2095 struct drm_i915_gem_object *obj,
2098 void i915_gem_detach_phys_object(struct drm_device *dev,
2099 struct drm_i915_gem_object *obj);
2100 void i915_gem_free_all_phys_object(struct drm_device *dev);
2101 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2102 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2105 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2107 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2108 int tiling_mode, bool fenced);
2110 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2111 enum i915_cache_level cache_level);
2113 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2114 struct dma_buf *dma_buf);
2116 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2117 struct drm_gem_object *gem_obj, int flags);
2119 void i915_gem_restore_fences(struct drm_device *dev);
2121 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2122 struct i915_address_space *vm);
2123 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2124 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2125 struct i915_address_space *vm);
2126 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2127 struct i915_address_space *vm);
2128 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2129 struct i915_address_space *vm);
2131 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2132 struct i915_address_space *vm);
2134 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2136 /* Some GGTT VM helpers */
2137 #define obj_to_ggtt(obj) \
2138 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2139 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2141 struct i915_address_space *ggtt =
2142 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2146 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2148 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2151 static inline unsigned long
2152 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2154 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2157 static inline unsigned long
2158 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2160 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2163 static inline int __must_check
2164 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2166 bool map_and_fenceable,
2169 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
2170 map_and_fenceable, nonblocking);
2173 /* i915_gem_context.c */
2174 void i915_gem_context_init(struct drm_device *dev);
2175 void i915_gem_context_fini(struct drm_device *dev);
2176 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2177 int i915_switch_context(struct intel_ring_buffer *ring,
2178 struct drm_file *file, int to_id);
2179 void i915_gem_context_free(struct kref *ctx_ref);
2180 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2182 kref_get(&ctx->ref);
2185 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2187 kref_put(&ctx->ref, i915_gem_context_free);
2190 struct i915_ctx_hang_stats * __must_check
2191 i915_gem_context_get_hang_stats(struct drm_device *dev,
2192 struct drm_file *file,
2194 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2195 struct drm_file *file);
2196 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2197 struct drm_file *file);
2199 /* i915_gem_gtt.c */
2200 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
2201 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
2202 struct drm_i915_gem_object *obj,
2203 enum i915_cache_level cache_level);
2204 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
2205 struct drm_i915_gem_object *obj);
2207 void i915_check_and_clear_faults(struct drm_device *dev);
2208 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
2209 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
2210 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
2211 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
2212 enum i915_cache_level cache_level);
2213 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
2214 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
2215 void i915_gem_init_global_gtt(struct drm_device *dev);
2216 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
2217 unsigned long mappable_end, unsigned long end);
2218 int i915_gem_gtt_init(struct drm_device *dev);
2219 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2221 if (INTEL_INFO(dev)->gen < 6)
2222 intel_gtt_chipset_flush();
2226 /* i915_gem_evict.c */
2227 int __must_check i915_gem_evict_something(struct drm_device *dev,
2228 struct i915_address_space *vm,
2231 unsigned cache_level,
2234 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2235 int i915_gem_evict_everything(struct drm_device *dev);
2237 /* i915_gem_stolen.c */
2238 int i915_gem_init_stolen(struct drm_device *dev);
2239 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2240 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2241 void i915_gem_cleanup_stolen(struct drm_device *dev);
2242 struct drm_i915_gem_object *
2243 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2244 struct drm_i915_gem_object *
2245 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2249 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2251 /* i915_gem_tiling.c */
2252 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2254 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2256 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2257 obj->tiling_mode != I915_TILING_NONE;
2260 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2261 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2262 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2264 /* i915_gem_debug.c */
2266 int i915_verify_lists(struct drm_device *dev);
2268 #define i915_verify_lists(dev) 0
2271 /* i915_debugfs.c */
2272 int i915_debugfs_init(struct drm_minor *minor);
2273 void i915_debugfs_cleanup(struct drm_minor *minor);
2274 #ifdef CONFIG_DEBUG_FS
2275 void intel_display_crc_init(struct drm_device *dev);
2277 static inline void intel_display_crc_init(struct drm_device *dev) {}
2280 /* i915_gpu_error.c */
2282 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2283 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2284 const struct i915_error_state_file_priv *error);
2285 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2286 size_t count, loff_t pos);
2287 static inline void i915_error_state_buf_release(
2288 struct drm_i915_error_state_buf *eb)
2292 void i915_capture_error_state(struct drm_device *dev);
2293 void i915_error_state_get(struct drm_device *dev,
2294 struct i915_error_state_file_priv *error_priv);
2295 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2296 void i915_destroy_error_state(struct drm_device *dev);
2298 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2299 const char *i915_cache_level_str(int type);
2301 /* i915_suspend.c */
2302 extern int i915_save_state(struct drm_device *dev);
2303 extern int i915_restore_state(struct drm_device *dev);
2306 void i915_save_display_reg(struct drm_device *dev);
2307 void i915_restore_display_reg(struct drm_device *dev);
2310 void i915_setup_sysfs(struct drm_device *dev_priv);
2311 void i915_teardown_sysfs(struct drm_device *dev_priv);
2314 extern int intel_setup_gmbus(struct drm_device *dev);
2315 extern void intel_teardown_gmbus(struct drm_device *dev);
2316 static inline bool intel_gmbus_is_port_valid(unsigned port)
2318 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2321 extern struct i2c_adapter *intel_gmbus_get_adapter(
2322 struct drm_i915_private *dev_priv, unsigned port);
2323 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2324 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2325 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2327 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2329 extern void intel_i2c_reset(struct drm_device *dev);
2331 /* intel_opregion.c */
2332 struct intel_encoder;
2333 extern int intel_opregion_setup(struct drm_device *dev);
2335 extern void intel_opregion_init(struct drm_device *dev);
2336 extern void intel_opregion_fini(struct drm_device *dev);
2337 extern void intel_opregion_asle_intr(struct drm_device *dev);
2338 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2340 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2343 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2344 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2345 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2347 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2352 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2360 extern void intel_register_dsm_handler(void);
2361 extern void intel_unregister_dsm_handler(void);
2363 static inline void intel_register_dsm_handler(void) { return; }
2364 static inline void intel_unregister_dsm_handler(void) { return; }
2365 #endif /* CONFIG_ACPI */
2368 extern void intel_modeset_init_hw(struct drm_device *dev);
2369 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2370 extern void intel_modeset_init(struct drm_device *dev);
2371 extern void intel_modeset_gem_init(struct drm_device *dev);
2372 extern void intel_modeset_cleanup(struct drm_device *dev);
2373 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2374 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2375 bool force_restore);
2376 extern void i915_redisable_vga(struct drm_device *dev);
2377 extern bool intel_fbc_enabled(struct drm_device *dev);
2378 extern void intel_disable_fbc(struct drm_device *dev);
2379 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2380 extern void intel_init_pch_refclk(struct drm_device *dev);
2381 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2382 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2383 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2384 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2385 extern void intel_detect_pch(struct drm_device *dev);
2386 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2387 extern int intel_enable_rc6(const struct drm_device *dev);
2389 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2390 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2391 struct drm_file *file);
2394 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2395 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2396 struct intel_overlay_error_state *error);
2398 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2399 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2400 struct drm_device *dev,
2401 struct intel_display_error_state *error);
2403 /* On SNB platform, before reading ring registers forcewake bit
2404 * must be set to prevent GT core from power down and stale values being
2407 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2408 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
2410 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2411 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2413 /* intel_sideband.c */
2414 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2415 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2416 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2417 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2418 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2419 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2420 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2421 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2422 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2423 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2424 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2425 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2426 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2427 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2428 enum intel_sbi_destination destination);
2429 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2430 enum intel_sbi_destination destination);
2432 int vlv_gpu_freq(int ddr_freq, int val);
2433 int vlv_freq_opcode(int ddr_freq, int val);
2435 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2436 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2438 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2439 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2440 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2441 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2443 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2444 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2445 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2446 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2448 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2449 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2451 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2452 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2454 /* "Broadcast RGB" property */
2455 #define INTEL_BROADCAST_RGB_AUTO 0
2456 #define INTEL_BROADCAST_RGB_FULL 1
2457 #define INTEL_BROADCAST_RGB_LIMITED 2
2459 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2461 if (HAS_PCH_SPLIT(dev))
2462 return CPU_VGACNTRL;
2463 else if (IS_VALLEYVIEW(dev))
2464 return VLV_VGACNTRL;
2469 static inline void __user *to_user_ptr(u64 address)
2471 return (void __user *)(uintptr_t)address;
2474 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2476 unsigned long j = msecs_to_jiffies(m);
2478 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2481 static inline unsigned long
2482 timespec_to_jiffies_timeout(const struct timespec *value)
2484 unsigned long j = timespec_to_jiffies(value);
2486 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);