Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158
 159 static const struct intel_device_info intel_i830_info = {
 160         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .ring_mask = RENDER_RING,
 163 };
 164
 165 static const struct intel_device_info intel_845g_info = {
 166         .gen = 2, .num_pipes = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168         .ring_mask = RENDER_RING,
 169 };
 170
 171 static const struct intel_device_info intel_i85x_info = {
 172         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 173         .cursor_needs_physical = 1,
 174         .has_overlay = 1, .overlay_needs_physical = 1,
 175         .ring_mask = RENDER_RING,
 176 };
 177
 178 static const struct intel_device_info intel_i865g_info = {
 179         .gen = 2, .num_pipes = 1,
 180         .has_overlay = 1, .overlay_needs_physical = 1,
 181         .ring_mask = RENDER_RING,
 182 };
 183
 184 static const struct intel_device_info intel_i915g_info = {
 185         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 186         .has_overlay = 1, .overlay_needs_physical = 1,
 187         .ring_mask = RENDER_RING,
 188 };
 189 static const struct intel_device_info intel_i915gm_info = {
 190         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 191         .cursor_needs_physical = 1,
 192         .has_overlay = 1, .overlay_needs_physical = 1,
 193         .supports_tv = 1,
 194         .ring_mask = RENDER_RING,
 195 };
 196 static const struct intel_device_info intel_i945g_info = {
 197         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 198         .has_overlay = 1, .overlay_needs_physical = 1,
 199         .ring_mask = RENDER_RING,
 200 };
 201 static const struct intel_device_info intel_i945gm_info = {
 202         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 203         .has_hotplug = 1, .cursor_needs_physical = 1,
 204         .has_overlay = 1, .overlay_needs_physical = 1,
 205         .supports_tv = 1,
 206         .ring_mask = RENDER_RING,
 207 };
 208
 209 static const struct intel_device_info intel_i965g_info = {
 210         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 211         .has_hotplug = 1,
 212         .has_overlay = 1,
 213         .ring_mask = RENDER_RING,
 214 };
 215
 216 static const struct intel_device_info intel_i965gm_info = {
 217         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 218         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 219         .has_overlay = 1,
 220         .supports_tv = 1,
 221         .ring_mask = RENDER_RING,
 222 };
 223
 224 static const struct intel_device_info intel_g33_info = {
 225         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 226         .need_gfx_hws = 1, .has_hotplug = 1,
 227         .has_overlay = 1,
 228         .ring_mask = RENDER_RING,
 229 };
 230
 231 static const struct intel_device_info intel_g45_info = {
 232         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 233         .has_pipe_cxsr = 1, .has_hotplug = 1,
 234         .ring_mask = RENDER_RING | BSD_RING,
 235 };
 236
 237 static const struct intel_device_info intel_gm45_info = {
 238         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 239         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 240         .has_pipe_cxsr = 1, .has_hotplug = 1,
 241         .supports_tv = 1,
 242         .ring_mask = RENDER_RING | BSD_RING,
 243 };
 244
 245 static const struct intel_device_info intel_pineview_info = {
 246         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 247         .need_gfx_hws = 1, .has_hotplug = 1,
 248         .has_overlay = 1,
 249 };
 250
 251 static const struct intel_device_info intel_ironlake_d_info = {
 252         .gen = 5, .num_pipes = 2,
 253         .need_gfx_hws = 1, .has_hotplug = 1,
 254         .ring_mask = RENDER_RING | BSD_RING,
 255 };
 256
 257 static const struct intel_device_info intel_ironlake_m_info = {
 258         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 259         .need_gfx_hws = 1, .has_hotplug = 1,
 260         .has_fbc = 1,
 261         .ring_mask = RENDER_RING | BSD_RING,
 262 };
 263
 264 static const struct intel_device_info intel_sandybridge_d_info = {
 265         .gen = 6, .num_pipes = 2,
 266         .need_gfx_hws = 1, .has_hotplug = 1,
 267         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 268         .has_llc = 1,
 269 };
 270
 271 static const struct intel_device_info intel_sandybridge_m_info = {
 272         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 273         .need_gfx_hws = 1, .has_hotplug = 1,
 274         .has_fbc = 1,
 275         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 276         .has_llc = 1,
 277 };
 278
 279 #define GEN7_FEATURES  \
 280         .gen = 7, .num_pipes = 3, \
 281         .need_gfx_hws = 1, .has_hotplug = 1, \
 282         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 283         .has_llc = 1
 284
 285 static const struct intel_device_info intel_ivybridge_d_info = {
 286         GEN7_FEATURES,
 287         .is_ivybridge = 1,
 288 };
 289
 290 static const struct intel_device_info intel_ivybridge_m_info = {
 291         GEN7_FEATURES,
 292         .is_ivybridge = 1,
 293         .is_mobile = 1,
 294         .has_fbc = 1,
 295 };
 296
 297 static const struct intel_device_info intel_ivybridge_q_info = {
 298         GEN7_FEATURES,
 299         .is_ivybridge = 1,
 300         .num_pipes = 0, /* legal, last one wins */
 301 };
 302
 303 static const struct intel_device_info intel_valleyview_m_info = {
 304         GEN7_FEATURES,
 305         .is_mobile = 1,
 306         .num_pipes = 2,
 307         .is_valleyview = 1,
 308         .display_mmio_offset = VLV_DISPLAY_BASE,
 309         .has_llc = 0, /* legal, last one wins */
 310 };
 311
 312 static const struct intel_device_info intel_valleyview_d_info = {
 313         GEN7_FEATURES,
 314         .num_pipes = 2,
 315         .is_valleyview = 1,
 316         .display_mmio_offset = VLV_DISPLAY_BASE,
 317         .has_llc = 0, /* legal, last one wins */
 318 };
 319
 320 static const struct intel_device_info intel_haswell_d_info = {
 321         GEN7_FEATURES,
 322         .is_haswell = 1,
 323         .has_ddi = 1,
 324         .has_fpga_dbg = 1,
 325         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 326 };
 327
 328 static const struct intel_device_info intel_haswell_m_info = {
 329         GEN7_FEATURES,
 330         .is_haswell = 1,
 331         .is_mobile = 1,
 332         .has_ddi = 1,
 333         .has_fpga_dbg = 1,
 334         .has_fbc = 1,
 335         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 336 };
 337
 338 static const struct intel_device_info intel_broadwell_d_info = {
 339         .is_preliminary = 1,
 340         .gen = 8, .num_pipes = 3,
 341         .need_gfx_hws = 1, .has_hotplug = 1,
 342         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 343         .has_llc = 1,
 344         .has_ddi = 1,
 345 };
 346
 347 static const struct intel_device_info intel_broadwell_m_info = {
 348         .is_preliminary = 1,
 349         .gen = 8, .is_mobile = 1, .num_pipes = 3,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .has_llc = 1,
 353         .has_ddi = 1,
 354 };
 355
 356 /*
 357  * Make sure any device matches here are from most specific to most
 358  * general.  For example, since the Quanta match is based on the subsystem
 359  * and subvendor IDs, we need it to come before the more general IVB
 360  * PCI ID matches, otherwise we'll use the wrong info struct above.
 361  */
 362 #define INTEL_PCI_IDS \
 363         INTEL_I830_IDS(&intel_i830_info),       \
 364         INTEL_I845G_IDS(&intel_845g_info),      \
 365         INTEL_I85X_IDS(&intel_i85x_info),       \
 366         INTEL_I865G_IDS(&intel_i865g_info),     \
 367         INTEL_I915G_IDS(&intel_i915g_info),     \
 368         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 369         INTEL_I945G_IDS(&intel_i945g_info),     \
 370         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 371         INTEL_I965G_IDS(&intel_i965g_info),     \
 372         INTEL_G33_IDS(&intel_g33_info),         \
 373         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 374         INTEL_GM45_IDS(&intel_gm45_info),       \
 375         INTEL_G45_IDS(&intel_g45_info),         \
 376         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 377         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 378         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 379         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 380         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 381         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 382         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 383         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 384         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 385         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 386         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 387         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
 388         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
 389         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
 390
 391 static const struct pci_device_id pciidlist[] = {               /* aka */
 392         INTEL_PCI_IDS,
 393         {0, 0, 0}
 394 };
 395
 396 #if defined(CONFIG_DRM_I915_KMS)
 397 MODULE_DEVICE_TABLE(pci, pciidlist);
 398 #endif
 399
 400 void intel_detect_pch(struct drm_device *dev)
 401 {
 402         struct drm_i915_private *dev_priv = dev->dev_private;
 403         struct pci_dev *pch;
 404
 405         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 406          * (which really amounts to a PCH but no South Display).
 407          */
 408         if (INTEL_INFO(dev)->num_pipes == 0) {
 409                 dev_priv->pch_type = PCH_NOP;
 410                 return;
 411         }
 412
 413         /*
 414          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 415          * make graphics device passthrough work easy for VMM, that only
 416          * need to expose ISA bridge to let driver know the real hardware
 417          * underneath. This is a requirement from virtualization team.
 418          *
 419          * In some virtualized environments (e.g. XEN), there is irrelevant
 420          * ISA bridge in the system. To work reliably, we should scan trhough
 421          * all the ISA bridge devices and check for the first match, instead
 422          * of only checking the first one.
 423          */
 424         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 425         while (pch) {
 426                 struct pci_dev *curr = pch;
 427                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 428                         unsigned short id;
 429                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 430                         dev_priv->pch_id = id;
 431
 432                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 433                                 dev_priv->pch_type = PCH_IBX;
 434                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 435                                 WARN_ON(!IS_GEN5(dev));
 436                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 437                                 dev_priv->pch_type = PCH_CPT;
 438                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 439                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 440                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 441                                 /* PantherPoint is CPT compatible */
 442                                 dev_priv->pch_type = PCH_CPT;
 443                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 444                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 445                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 446                                 dev_priv->pch_type = PCH_LPT;
 447                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 448                                 WARN_ON(!IS_HASWELL(dev));
 449                                 WARN_ON(IS_ULT(dev));
 450                         } else if (IS_BROADWELL(dev)) {
 451                                 dev_priv->pch_type = PCH_LPT;
 452                                 dev_priv->pch_id =
 453                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 454                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
 455                                               "LynxPoint LP PCH\n");
 456                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 457                                 dev_priv->pch_type = PCH_LPT;
 458                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 459                                 WARN_ON(!IS_HASWELL(dev));
 460                                 WARN_ON(!IS_ULT(dev));
 461                         } else {
 462                                 goto check_next;
 463                         }
 464                         pci_dev_put(pch);
 465                         break;
 466                 }
 467 check_next:
 468                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
 469                 pci_dev_put(curr);
 470         }
 471         if (!pch)
 472                 DRM_DEBUG_KMS("No PCH found?\n");
 473 }
 474
 475 bool i915_semaphore_is_enabled(struct drm_device *dev)
 476 {
 477         if (INTEL_INFO(dev)->gen < 6)
 478                 return 0;
 479
 480         /* Until we get further testing... */
 481         if (IS_GEN8(dev)) {
 482                 WARN_ON(!i915_preliminary_hw_support);
 483                 return 0;
 484         }
 485
 486         if (i915_semaphores >= 0)
 487                 return i915_semaphores;
 488
 489 #ifdef CONFIG_INTEL_IOMMU
 490         /* Enable semaphores on SNB when IO remapping is off */
 491         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 492                 return false;
 493 #endif
 494
 495         return 1;
 496 }
 497
 498 static int i915_drm_freeze(struct drm_device *dev)
 499 {
 500         struct drm_i915_private *dev_priv = dev->dev_private;
 501         struct drm_crtc *crtc;
 502
 503         /* ignore lid events during suspend */
 504         mutex_lock(&dev_priv->modeset_restore_lock);
 505         dev_priv->modeset_restore = MODESET_SUSPENDED;
 506         mutex_unlock(&dev_priv->modeset_restore_lock);
 507
 508         /* We do a lot of poking in a lot of registers, make sure they work
 509          * properly. */
 510         hsw_disable_package_c8(dev_priv);
 511         intel_display_set_init_power(dev, true);
 512
 513         drm_kms_helper_poll_disable(dev);
 514
 515         pci_save_state(dev->pdev);
 516
 517         /* If KMS is active, we do the leavevt stuff here */
 518         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 519                 int error;
 520
 521                 error = i915_gem_suspend(dev);
 522                 if (error) {
 523                         dev_err(&dev->pdev->dev,
 524                                 "GEM idle failed, resume might fail\n");
 525                         return error;
 526                 }
 527
 528                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 529
 530                 drm_irq_uninstall(dev);
 531                 dev_priv->enable_hotplug_processing = false;
 532                 /*
 533                  * Disable CRTCs directly since we want to preserve sw state
 534                  * for _thaw.
 535                  */
 536                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 537                         dev_priv->display.crtc_disable(crtc);
 538
 539                 intel_modeset_suspend_hw(dev);
 540         }
 541
 542         i915_gem_suspend_gtt_mappings(dev);
 543
 544         i915_save_state(dev);
 545
 546         intel_opregion_fini(dev);
 547
 548         console_lock();
 549         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 550         console_unlock();
 551
 552         return 0;
 553 }
 554
 555 int i915_suspend(struct drm_device *dev, pm_message_t state)
 556 {
 557         int error;
 558
 559         if (!dev || !dev->dev_private) {
 560                 DRM_ERROR("dev: %p\n", dev);
 561                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 562                 return -ENODEV;
 563         }
 564
 565         if (state.event == PM_EVENT_PRETHAW)
 566                 return 0;
 567
 568
 569         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 570                 return 0;
 571
 572         error = i915_drm_freeze(dev);
 573         if (error)
 574                 return error;
 575
 576         if (state.event == PM_EVENT_SUSPEND) {
 577                 /* Shut down the device */
 578                 pci_disable_device(dev->pdev);
 579                 pci_set_power_state(dev->pdev, PCI_D3hot);
 580         }
 581
 582         return 0;
 583 }
 584
 585 void intel_console_resume(struct work_struct *work)
 586 {
 587         struct drm_i915_private *dev_priv =
 588                 container_of(work, struct drm_i915_private,
 589                              console_resume_work);
 590         struct drm_device *dev = dev_priv->dev;
 591
 592         console_lock();
 593         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 594         console_unlock();
 595 }
 596
 597 static void intel_resume_hotplug(struct drm_device *dev)
 598 {
 599         struct drm_mode_config *mode_config = &dev->mode_config;
 600         struct intel_encoder *encoder;
 601
 602         mutex_lock(&mode_config->mutex);
 603         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 604
 605         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 606                 if (encoder->hot_plug)
 607                         encoder->hot_plug(encoder);
 608
 609         mutex_unlock(&mode_config->mutex);
 610
 611         /* Just fire off a uevent and let userspace tell us what to do */
 612         drm_helper_hpd_irq_event(dev);
 613 }
 614
 615 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
 616 {
 617         struct drm_i915_private *dev_priv = dev->dev_private;
 618         int error = 0;
 619
 620         intel_uncore_early_sanitize(dev);
 621
 622         intel_uncore_sanitize(dev);
 623
 624         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 625             restore_gtt_mappings) {
 626                 mutex_lock(&dev->struct_mutex);
 627                 i915_gem_restore_gtt_mappings(dev);
 628                 mutex_unlock(&dev->struct_mutex);
 629         }
 630
 631         intel_power_domains_init_hw(dev);
 632
 633         i915_restore_state(dev);
 634         intel_opregion_setup(dev);
 635
 636         /* KMS EnterVT equivalent */
 637         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 638                 intel_init_pch_refclk(dev);
 639
 640                 mutex_lock(&dev->struct_mutex);
 641
 642                 error = i915_gem_init_hw(dev);
 643                 mutex_unlock(&dev->struct_mutex);
 644
 645                 /* We need working interrupts for modeset enabling ... */
 646                 drm_irq_install(dev);
 647
 648                 intel_modeset_init_hw(dev);
 649
 650                 drm_modeset_lock_all(dev);
 651                 intel_modeset_setup_hw_state(dev, true);
 652                 drm_modeset_unlock_all(dev);
 653
 654                 /*
 655                  * ... but also need to make sure that hotplug processing
 656                  * doesn't cause havoc. Like in the driver load code we don't
 657                  * bother with the tiny race here where we might loose hotplug
 658                  * notifications.
 659                  * */
 660                 intel_hpd_init(dev);
 661                 dev_priv->enable_hotplug_processing = true;
 662                 /* Config may have changed between suspend and resume */
 663                 intel_resume_hotplug(dev);
 664         }
 665
 666         intel_opregion_init(dev);
 667
 668         /*
 669          * The console lock can be pretty contented on resume due
 670          * to all the printk activity.  Try to keep it out of the hot
 671          * path of resume if possible.
 672          */
 673         if (console_trylock()) {
 674                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 675                 console_unlock();
 676         } else {
 677                 schedule_work(&dev_priv->console_resume_work);
 678         }
 679
 680         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 681          * expected level. */
 682         hsw_enable_package_c8(dev_priv);
 683
 684         mutex_lock(&dev_priv->modeset_restore_lock);
 685         dev_priv->modeset_restore = MODESET_DONE;
 686         mutex_unlock(&dev_priv->modeset_restore_lock);
 687         return error;
 688 }
 689
 690 static int i915_drm_thaw(struct drm_device *dev)
 691 {
 692         if (drm_core_check_feature(dev, DRIVER_MODESET))
 693                 i915_check_and_clear_faults(dev);
 694
 695         return __i915_drm_thaw(dev, true);
 696 }
 697
 698 int i915_resume(struct drm_device *dev)
 699 {
 700         struct drm_i915_private *dev_priv = dev->dev_private;
 701         int ret;
 702
 703         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 704                 return 0;
 705
 706         if (pci_enable_device(dev->pdev))
 707                 return -EIO;
 708
 709         pci_set_master(dev->pdev);
 710
 711         /*
 712          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 713          * earlier) need to restore the GTT mappings since the BIOS might clear
 714          * all our scratch PTEs.
 715          */
 716         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
 717         if (ret)
 718                 return ret;
 719
 720         drm_kms_helper_poll_enable(dev);
 721         return 0;
 722 }
 723
 724 /**
 725  * i915_reset - reset chip after a hang
 726  * @dev: drm device to reset
 727  *
 728  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 729  * reset or otherwise an error code.
 730  *
 731  * Procedure is fairly simple:
 732  *   - reset the chip using the reset reg
 733  *   - re-init context state
 734  *   - re-init hardware status page
 735  *   - re-init ring buffer
 736  *   - re-init interrupt state
 737  *   - re-init display
 738  */
 739 int i915_reset(struct drm_device *dev)
 740 {
 741         drm_i915_private_t *dev_priv = dev->dev_private;
 742         bool simulated;
 743         int ret;
 744
 745         if (!i915_try_reset)
 746                 return 0;
 747
 748         mutex_lock(&dev->struct_mutex);
 749
 750         i915_gem_reset(dev);
 751
 752         simulated = dev_priv->gpu_error.stop_rings != 0;
 753
 754         ret = intel_gpu_reset(dev);
 755
 756         /* Also reset the gpu hangman. */
 757         if (simulated) {
 758                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 759                 dev_priv->gpu_error.stop_rings = 0;
 760                 if (ret == -ENODEV) {
 761                         DRM_INFO("Reset not implemented, but ignoring "
 762                                  "error for simulated gpu hangs\n");
 763                         ret = 0;
 764                 }
 765         }
 766
 767         if (ret) {
 768                 DRM_ERROR("Failed to reset chip: %i\n", ret);
 769                 mutex_unlock(&dev->struct_mutex);
 770                 return ret;
 771         }
 772
 773         /* Ok, now get things going again... */
 774
 775         /*
 776          * Everything depends on having the GTT running, so we need to start
 777          * there.  Fortunately we don't need to do this unless we reset the
 778          * chip at a PCI level.
 779          *
 780          * Next we need to restore the context, but we don't use those
 781          * yet either...
 782          *
 783          * Ring buffer needs to be re-initialized in the KMS case, or if X
 784          * was running at the time of the reset (i.e. we weren't VT
 785          * switched away).
 786          */
 787         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 788                         !dev_priv->ums.mm_suspended) {
 789                 dev_priv->ums.mm_suspended = 0;
 790
 791                 ret = i915_gem_init_hw(dev);
 792                 mutex_unlock(&dev->struct_mutex);
 793                 if (ret) {
 794                         DRM_ERROR("Failed hw init on reset %d\n", ret);
 795                         return ret;
 796                 }
 797
 798                 drm_irq_uninstall(dev);
 799                 drm_irq_install(dev);
 800                 intel_hpd_init(dev);
 801         } else {
 802                 mutex_unlock(&dev->struct_mutex);
 803         }
 804
 805         return 0;
 806 }
 807
 808 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 809 {
 810         struct intel_device_info *intel_info =
 811                 (struct intel_device_info *) ent->driver_data;
 812
 813         if (IS_PRELIMINARY_HW(intel_info) && !i915_preliminary_hw_support) {
 814                 DRM_INFO("This hardware requires preliminary hardware support.\n"
 815                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
 816                 return -ENODEV;
 817         }
 818
 819         /* Only bind to function 0 of the device. Early generations
 820          * used function 1 as a placeholder for multi-head. This causes
 821          * us confusion instead, especially on the systems where both
 822          * functions have the same PCI-ID!
 823          */
 824         if (PCI_FUNC(pdev->devfn))
 825                 return -ENODEV;
 826
 827         driver.driver_features &= ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 828
 829         return drm_get_pci_dev(pdev, ent, &driver);
 830 }
 831
 832 static void
 833 i915_pci_remove(struct pci_dev *pdev)
 834 {
 835         struct drm_device *dev = pci_get_drvdata(pdev);
 836
 837         drm_put_dev(dev);
 838 }
 839
 840 static int i915_pm_suspend(struct device *dev)
 841 {
 842         struct pci_dev *pdev = to_pci_dev(dev);
 843         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 844         int error;
 845
 846         if (!drm_dev || !drm_dev->dev_private) {
 847                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 848                 return -ENODEV;
 849         }
 850
 851         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 852                 return 0;
 853
 854         error = i915_drm_freeze(drm_dev);
 855         if (error)
 856                 return error;
 857
 858         pci_disable_device(pdev);
 859         pci_set_power_state(pdev, PCI_D3hot);
 860
 861         return 0;
 862 }
 863
 864 static int i915_pm_resume(struct device *dev)
 865 {
 866         struct pci_dev *pdev = to_pci_dev(dev);
 867         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 868
 869         return i915_resume(drm_dev);
 870 }
 871
 872 static int i915_pm_freeze(struct device *dev)
 873 {
 874         struct pci_dev *pdev = to_pci_dev(dev);
 875         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 876
 877         if (!drm_dev || !drm_dev->dev_private) {
 878                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 879                 return -ENODEV;
 880         }
 881
 882         return i915_drm_freeze(drm_dev);
 883 }
 884
 885 static int i915_pm_thaw(struct device *dev)
 886 {
 887         struct pci_dev *pdev = to_pci_dev(dev);
 888         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 889
 890         return i915_drm_thaw(drm_dev);
 891 }
 892
 893 static int i915_pm_poweroff(struct device *dev)
 894 {
 895         struct pci_dev *pdev = to_pci_dev(dev);
 896         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 897
 898         return i915_drm_freeze(drm_dev);
 899 }
 900
 901 static const struct dev_pm_ops i915_pm_ops = {
 902         .suspend = i915_pm_suspend,
 903         .resume = i915_pm_resume,
 904         .freeze = i915_pm_freeze,
 905         .thaw = i915_pm_thaw,
 906         .poweroff = i915_pm_poweroff,
 907         .restore = i915_pm_resume,
 908 };
 909
 910 static const struct vm_operations_struct i915_gem_vm_ops = {
 911         .fault = i915_gem_fault,
 912         .open = drm_gem_vm_open,
 913         .close = drm_gem_vm_close,
 914 };
 915
 916 static const struct file_operations i915_driver_fops = {
 917         .owner = THIS_MODULE,
 918         .open = drm_open,
 919         .release = drm_release,
 920         .unlocked_ioctl = drm_ioctl,
 921         .mmap = drm_gem_mmap,
 922         .poll = drm_poll,
 923         .read = drm_read,
 924 #ifdef CONFIG_COMPAT
 925         .compat_ioctl = i915_compat_ioctl,
 926 #endif
 927         .llseek = noop_llseek,
 928 };
 929
 930 static struct drm_driver driver = {
 931         /* Don't use MTRRs here; the Xserver or userspace app should
 932          * deal with them for Intel hardware.
 933          */
 934         .driver_features =
 935             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 936             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 937             DRIVER_RENDER,
 938         .load = i915_driver_load,
 939         .unload = i915_driver_unload,
 940         .open = i915_driver_open,
 941         .lastclose = i915_driver_lastclose,
 942         .preclose = i915_driver_preclose,
 943         .postclose = i915_driver_postclose,
 944
 945         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 946         .suspend = i915_suspend,
 947         .resume = i915_resume,
 948
 949         .device_is_agp = i915_driver_device_is_agp,
 950         .master_create = i915_master_create,
 951         .master_destroy = i915_master_destroy,
 952 #if defined(CONFIG_DEBUG_FS)
 953         .debugfs_init = i915_debugfs_init,
 954         .debugfs_cleanup = i915_debugfs_cleanup,
 955 #endif
 956         .gem_free_object = i915_gem_free_object,
 957         .gem_vm_ops = &i915_gem_vm_ops,
 958
 959         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 960         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 961         .gem_prime_export = i915_gem_prime_export,
 962         .gem_prime_import = i915_gem_prime_import,
 963
 964         .dumb_create = i915_gem_dumb_create,
 965         .dumb_map_offset = i915_gem_mmap_gtt,
 966         .dumb_destroy = drm_gem_dumb_destroy,
 967         .ioctls = i915_ioctls,
 968         .fops = &i915_driver_fops,
 969         .name = DRIVER_NAME,
 970         .desc = DRIVER_DESC,
 971         .date = DRIVER_DATE,
 972         .major = DRIVER_MAJOR,
 973         .minor = DRIVER_MINOR,
 974         .patchlevel = DRIVER_PATCHLEVEL,
 975 };
 976
 977 static struct pci_driver i915_pci_driver = {
 978         .name = DRIVER_NAME,
 979         .id_table = pciidlist,
 980         .probe = i915_pci_probe,
 981         .remove = i915_pci_remove,
 982         .driver.pm = &i915_pm_ops,
 983 };
 984
 985 static int __init i915_init(void)
 986 {
 987         driver.num_ioctls = i915_max_ioctl;
 988
 989         /*
 990          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 991          * explicitly disabled with the module pararmeter.
 992          *
 993          * Otherwise, just follow the parameter (defaulting to off).
 994          *
 995          * Allow optional vga_text_mode_force boot option to override
 996          * the default behavior.
 997          */
 998 #if defined(CONFIG_DRM_I915_KMS)
 999         if (i915_modeset != 0)
1000                 driver.driver_features |= DRIVER_MODESET;
1001 #endif
1002         if (i915_modeset == 1)
1003                 driver.driver_features |= DRIVER_MODESET;
1004
1005 #ifdef CONFIG_VGA_CONSOLE
1006         if (vgacon_text_force() && i915_modeset == -1)
1007                 driver.driver_features &= ~DRIVER_MODESET;
1008 #endif
1009
1010         if (!(driver.driver_features & DRIVER_MODESET)) {
1011                 driver.get_vblank_timestamp = NULL;
1012 #ifndef CONFIG_DRM_I915_UMS
1013                 /* Silently fail loading to not upset userspace. */
1014                 return 0;
1015 #endif
1016         }
1017
1018         return drm_pci_init(&driver, &i915_pci_driver);
1019 }
1020
1021 static void __exit i915_exit(void)
1022 {
1023         drm_pci_exit(&driver, &i915_pci_driver);
1024 }
1025
1026 module_init(i915_init);
1027 module_exit(i915_exit);
1028
1029 MODULE_AUTHOR(DRIVER_AUTHOR);
1030 MODULE_DESCRIPTION(DRIVER_DESC);
1031 MODULE_LICENSE("GPL and additional rights");