Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
 122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 123 MODULE_PARM_DESC(preliminary_hw_support,
 124                 "Enable preliminary hardware support. (default: false)");
 125
 126 static struct drm_driver driver;
 127 extern int intel_agp_enabled;
 128
 129 #define INTEL_VGA_DEVICE(id, info) {            \
 130         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 131         .class_mask = 0xff0000,                 \
 132         .vendor = 0x8086,                       \
 133         .device = id,                           \
 134         .subvendor = PCI_ANY_ID,                \
 135         .subdevice = PCI_ANY_ID,                \
 136         .driver_data = (unsigned long) info }
 137
 138 static const struct intel_device_info intel_i830_info = {
 139         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 140         .has_overlay = 1, .overlay_needs_physical = 1,
 141 };
 142
 143 static const struct intel_device_info intel_845g_info = {
 144         .gen = 2, .num_pipes = 1,
 145         .has_overlay = 1, .overlay_needs_physical = 1,
 146 };
 147
 148 static const struct intel_device_info intel_i85x_info = {
 149         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 150         .cursor_needs_physical = 1,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152 };
 153
 154 static const struct intel_device_info intel_i865g_info = {
 155         .gen = 2, .num_pipes = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157 };
 158
 159 static const struct intel_device_info intel_i915g_info = {
 160         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162 };
 163 static const struct intel_device_info intel_i915gm_info = {
 164         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 165         .cursor_needs_physical = 1,
 166         .has_overlay = 1, .overlay_needs_physical = 1,
 167         .supports_tv = 1,
 168 };
 169 static const struct intel_device_info intel_i945g_info = {
 170         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 171         .has_overlay = 1, .overlay_needs_physical = 1,
 172 };
 173 static const struct intel_device_info intel_i945gm_info = {
 174         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 175         .has_hotplug = 1, .cursor_needs_physical = 1,
 176         .has_overlay = 1, .overlay_needs_physical = 1,
 177         .supports_tv = 1,
 178 };
 179
 180 static const struct intel_device_info intel_i965g_info = {
 181         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 182         .has_hotplug = 1,
 183         .has_overlay = 1,
 184 };
 185
 186 static const struct intel_device_info intel_i965gm_info = {
 187         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 188         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 189         .has_overlay = 1,
 190         .supports_tv = 1,
 191 };
 192
 193 static const struct intel_device_info intel_g33_info = {
 194         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 195         .need_gfx_hws = 1, .has_hotplug = 1,
 196         .has_overlay = 1,
 197 };
 198
 199 static const struct intel_device_info intel_g45_info = {
 200         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 201         .has_pipe_cxsr = 1, .has_hotplug = 1,
 202         .has_bsd_ring = 1,
 203 };
 204
 205 static const struct intel_device_info intel_gm45_info = {
 206         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 207         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 208         .has_pipe_cxsr = 1, .has_hotplug = 1,
 209         .supports_tv = 1,
 210         .has_bsd_ring = 1,
 211 };
 212
 213 static const struct intel_device_info intel_pineview_info = {
 214         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 215         .need_gfx_hws = 1, .has_hotplug = 1,
 216         .has_overlay = 1,
 217 };
 218
 219 static const struct intel_device_info intel_ironlake_d_info = {
 220         .gen = 5, .num_pipes = 2,
 221         .need_gfx_hws = 1, .has_hotplug = 1,
 222         .has_bsd_ring = 1,
 223 };
 224
 225 static const struct intel_device_info intel_ironlake_m_info = {
 226         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 227         .need_gfx_hws = 1, .has_hotplug = 1,
 228         .has_fbc = 1,
 229         .has_bsd_ring = 1,
 230 };
 231
 232 static const struct intel_device_info intel_sandybridge_d_info = {
 233         .gen = 6, .num_pipes = 2,
 234         .need_gfx_hws = 1, .has_hotplug = 1,
 235         .has_bsd_ring = 1,
 236         .has_blt_ring = 1,
 237         .has_llc = 1,
 238         .has_force_wake = 1,
 239 };
 240
 241 static const struct intel_device_info intel_sandybridge_m_info = {
 242         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 243         .need_gfx_hws = 1, .has_hotplug = 1,
 244         .has_fbc = 1,
 245         .has_bsd_ring = 1,
 246         .has_blt_ring = 1,
 247         .has_llc = 1,
 248         .has_force_wake = 1,
 249 };
 250
 251 #define GEN7_FEATURES  \
 252         .gen = 7, .num_pipes = 3, \
 253         .need_gfx_hws = 1, .has_hotplug = 1, \
 254         .has_bsd_ring = 1, \
 255         .has_blt_ring = 1, \
 256         .has_llc = 1, \
 257         .has_force_wake = 1
 258
 259 static const struct intel_device_info intel_ivybridge_d_info = {
 260         GEN7_FEATURES,
 261         .is_ivybridge = 1,
 262 };
 263
 264 static const struct intel_device_info intel_ivybridge_m_info = {
 265         GEN7_FEATURES,
 266         .is_ivybridge = 1,
 267         .is_mobile = 1,
 268 };
 269
 270 static const struct intel_device_info intel_valleyview_m_info = {
 271         GEN7_FEATURES,
 272         .is_mobile = 1,
 273         .num_pipes = 2,
 274         .is_valleyview = 1,
 275         .display_mmio_offset = VLV_DISPLAY_BASE,
 276 };
 277
 278 static const struct intel_device_info intel_valleyview_d_info = {
 279         GEN7_FEATURES,
 280         .num_pipes = 2,
 281         .is_valleyview = 1,
 282         .display_mmio_offset = VLV_DISPLAY_BASE,
 283 };
 284
 285 static const struct intel_device_info intel_haswell_d_info = {
 286         GEN7_FEATURES,
 287         .is_haswell = 1,
 288 };
 289
 290 static const struct intel_device_info intel_haswell_m_info = {
 291         GEN7_FEATURES,
 292         .is_haswell = 1,
 293         .is_mobile = 1,
 294 };
 295
 296 static const struct pci_device_id pciidlist[] = {               /* aka */
 297         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 298         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 299         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 300         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 301         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 302         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 303         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 304         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 305         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 306         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 307         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 308         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 309         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 310         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 311         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 312         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 313         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 314         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 315         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 316         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 317         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 318         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 319         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 320         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 321         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 322         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 323         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 324         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 325         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 326         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 327         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 328         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 329         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 330         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 331         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 332         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 333         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 334         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 335         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 336         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 337         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 338         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 339         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 340         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 341         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 342         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 343         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 344         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 345         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 346         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 347         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 348         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 349         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 350         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 351         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 352         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 353         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 354         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 355         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 356         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 357         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 358         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 359         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 360         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 361         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 362         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 363         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 364         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 365         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 366         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 367         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 368         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 369         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 370         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 371         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 372         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 373         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 374         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 375         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 376         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 377         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 378         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
 379         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
 380         INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 381         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 382         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 383         {0, 0, 0}
 384 };
 385
 386 #if defined(CONFIG_DRM_I915_KMS)
 387 MODULE_DEVICE_TABLE(pci, pciidlist);
 388 #endif
 389
 390 void intel_detect_pch(struct drm_device *dev)
 391 {
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         struct pci_dev *pch;
 394
 395         /*
 396          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 397          * make graphics device passthrough work easy for VMM, that only
 398          * need to expose ISA bridge to let driver know the real hardware
 399          * underneath. This is a requirement from virtualization team.
 400          */
 401         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 402         if (pch) {
 403                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 404                         unsigned short id;
 405                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 406                         dev_priv->pch_id = id;
 407
 408                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 409                                 dev_priv->pch_type = PCH_IBX;
 410                                 dev_priv->num_pch_pll = 2;
 411                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 412                                 WARN_ON(!IS_GEN5(dev));
 413                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 414                                 dev_priv->pch_type = PCH_CPT;
 415                                 dev_priv->num_pch_pll = 2;
 416                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 417                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 418                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 419                                 /* PantherPoint is CPT compatible */
 420                                 dev_priv->pch_type = PCH_CPT;
 421                                 dev_priv->num_pch_pll = 2;
 422                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 423                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 424                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 425                                 dev_priv->pch_type = PCH_LPT;
 426                                 dev_priv->num_pch_pll = 0;
 427                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 428                                 WARN_ON(!IS_HASWELL(dev));
 429                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 430                                 dev_priv->pch_type = PCH_LPT;
 431                                 dev_priv->num_pch_pll = 0;
 432                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 433                                 WARN_ON(!IS_HASWELL(dev));
 434                         }
 435                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 436                 }
 437                 pci_dev_put(pch);
 438         }
 439 }
 440
 441 bool i915_semaphore_is_enabled(struct drm_device *dev)
 442 {
 443         if (INTEL_INFO(dev)->gen < 6)
 444                 return 0;
 445
 446         if (i915_semaphores >= 0)
 447                 return i915_semaphores;
 448
 449 #ifdef CONFIG_INTEL_IOMMU
 450         /* Enable semaphores on SNB when IO remapping is off */
 451         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 452                 return false;
 453 #endif
 454
 455         return 1;
 456 }
 457
 458 static int i915_drm_freeze(struct drm_device *dev)
 459 {
 460         struct drm_i915_private *dev_priv = dev->dev_private;
 461         struct drm_crtc *crtc;
 462
 463         /* ignore lid events during suspend */
 464         mutex_lock(&dev_priv->modeset_restore_lock);
 465         dev_priv->modeset_restore = MODESET_SUSPENDED;
 466         mutex_unlock(&dev_priv->modeset_restore_lock);
 467
 468         intel_set_power_well(dev, true);
 469
 470         drm_kms_helper_poll_disable(dev);
 471
 472         pci_save_state(dev->pdev);
 473
 474         /* If KMS is active, we do the leavevt stuff here */
 475         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 476                 int error = i915_gem_idle(dev);
 477                 if (error) {
 478                         dev_err(&dev->pdev->dev,
 479                                 "GEM idle failed, resume might fail\n");
 480                         return error;
 481                 }
 482
 483                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 484
 485                 drm_irq_uninstall(dev);
 486                 dev_priv->enable_hotplug_processing = false;
 487                 /*
 488                  * Disable CRTCs directly since we want to preserve sw state
 489                  * for _thaw.
 490                  */
 491                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 492                         dev_priv->display.crtc_disable(crtc);
 493         }
 494
 495         i915_save_state(dev);
 496
 497         intel_opregion_fini(dev);
 498
 499         console_lock();
 500         intel_fbdev_set_suspend(dev, 1);
 501         console_unlock();
 502
 503         return 0;
 504 }
 505
 506 int i915_suspend(struct drm_device *dev, pm_message_t state)
 507 {
 508         int error;
 509
 510         if (!dev || !dev->dev_private) {
 511                 DRM_ERROR("dev: %p\n", dev);
 512                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 513                 return -ENODEV;
 514         }
 515
 516         if (state.event == PM_EVENT_PRETHAW)
 517                 return 0;
 518
 519
 520         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 521                 return 0;
 522
 523         error = i915_drm_freeze(dev);
 524         if (error)
 525                 return error;
 526
 527         if (state.event == PM_EVENT_SUSPEND) {
 528                 /* Shut down the device */
 529                 pci_disable_device(dev->pdev);
 530                 pci_set_power_state(dev->pdev, PCI_D3hot);
 531         }
 532
 533         return 0;
 534 }
 535
 536 void intel_console_resume(struct work_struct *work)
 537 {
 538         struct drm_i915_private *dev_priv =
 539                 container_of(work, struct drm_i915_private,
 540                              console_resume_work);
 541         struct drm_device *dev = dev_priv->dev;
 542
 543         console_lock();
 544         intel_fbdev_set_suspend(dev, 0);
 545         console_unlock();
 546 }
 547
 548 static void intel_resume_hotplug(struct drm_device *dev)
 549 {
 550         struct drm_mode_config *mode_config = &dev->mode_config;
 551         struct intel_encoder *encoder;
 552
 553         mutex_lock(&mode_config->mutex);
 554         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 555
 556         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 557                 if (encoder->hot_plug)
 558                         encoder->hot_plug(encoder);
 559
 560         mutex_unlock(&mode_config->mutex);
 561
 562         /* Just fire off a uevent and let userspace tell us what to do */
 563         drm_helper_hpd_irq_event(dev);
 564 }
 565
 566 static int __i915_drm_thaw(struct drm_device *dev)
 567 {
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569         int error = 0;
 570
 571         i915_restore_state(dev);
 572         intel_opregion_setup(dev);
 573
 574         /* KMS EnterVT equivalent */
 575         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 576                 intel_init_pch_refclk(dev);
 577
 578                 mutex_lock(&dev->struct_mutex);
 579                 dev_priv->mm.suspended = 0;
 580
 581                 error = i915_gem_init_hw(dev);
 582                 mutex_unlock(&dev->struct_mutex);
 583
 584                 /* We need working interrupts for modeset enabling ... */
 585                 drm_irq_install(dev);
 586
 587                 intel_modeset_init_hw(dev);
 588
 589                 drm_modeset_lock_all(dev);
 590                 intel_modeset_setup_hw_state(dev, true);
 591                 drm_modeset_unlock_all(dev);
 592
 593                 /*
 594                  * ... but also need to make sure that hotplug processing
 595                  * doesn't cause havoc. Like in the driver load code we don't
 596                  * bother with the tiny race here where we might loose hotplug
 597                  * notifications.
 598                  * */
 599                 intel_hpd_init(dev);
 600                 dev_priv->enable_hotplug_processing = true;
 601                 /* Config may have changed between suspend and resume */
 602                 intel_resume_hotplug(dev);
 603         }
 604
 605         intel_opregion_init(dev);
 606
 607         /*
 608          * The console lock can be pretty contented on resume due
 609          * to all the printk activity.  Try to keep it out of the hot
 610          * path of resume if possible.
 611          */
 612         if (console_trylock()) {
 613                 intel_fbdev_set_suspend(dev, 0);
 614                 console_unlock();
 615         } else {
 616                 schedule_work(&dev_priv->console_resume_work);
 617         }
 618
 619         mutex_lock(&dev_priv->modeset_restore_lock);
 620         dev_priv->modeset_restore = MODESET_DONE;
 621         mutex_unlock(&dev_priv->modeset_restore_lock);
 622         return error;
 623 }
 624
 625 static int i915_drm_thaw(struct drm_device *dev)
 626 {
 627         int error = 0;
 628
 629         intel_gt_reset(dev);
 630
 631         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 632                 mutex_lock(&dev->struct_mutex);
 633                 i915_gem_restore_gtt_mappings(dev);
 634                 mutex_unlock(&dev->struct_mutex);
 635         }
 636
 637         __i915_drm_thaw(dev);
 638
 639         return error;
 640 }
 641
 642 int i915_resume(struct drm_device *dev)
 643 {
 644         struct drm_i915_private *dev_priv = dev->dev_private;
 645         int ret;
 646
 647         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 648                 return 0;
 649
 650         if (pci_enable_device(dev->pdev))
 651                 return -EIO;
 652
 653         pci_set_master(dev->pdev);
 654
 655         intel_gt_reset(dev);
 656
 657         /*
 658          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 659          * earlier) need this since the BIOS might clear all our scratch PTEs.
 660          */
 661         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 662             !dev_priv->opregion.header) {
 663                 mutex_lock(&dev->struct_mutex);
 664                 i915_gem_restore_gtt_mappings(dev);
 665                 mutex_unlock(&dev->struct_mutex);
 666         }
 667
 668         ret = __i915_drm_thaw(dev);
 669         if (ret)
 670                 return ret;
 671
 672         drm_kms_helper_poll_enable(dev);
 673         return 0;
 674 }
 675
 676 static int i8xx_do_reset(struct drm_device *dev)
 677 {
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679
 680         if (IS_I85X(dev))
 681                 return -ENODEV;
 682
 683         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 684         POSTING_READ(D_STATE);
 685
 686         if (IS_I830(dev) || IS_845G(dev)) {
 687                 I915_WRITE(DEBUG_RESET_I830,
 688                            DEBUG_RESET_DISPLAY |
 689                            DEBUG_RESET_RENDER |
 690                            DEBUG_RESET_FULL);
 691                 POSTING_READ(DEBUG_RESET_I830);
 692                 msleep(1);
 693
 694                 I915_WRITE(DEBUG_RESET_I830, 0);
 695                 POSTING_READ(DEBUG_RESET_I830);
 696         }
 697
 698         msleep(1);
 699
 700         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 701         POSTING_READ(D_STATE);
 702
 703         return 0;
 704 }
 705
 706 static int i965_reset_complete(struct drm_device *dev)
 707 {
 708         u8 gdrst;
 709         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 710         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 711 }
 712
 713 static int i965_do_reset(struct drm_device *dev)
 714 {
 715         int ret;
 716         u8 gdrst;
 717
 718         /*
 719          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 720          * well as the reset bit (GR/bit 0).  Setting the GR bit
 721          * triggers the reset; when done, the hardware will clear it.
 722          */
 723         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 724         pci_write_config_byte(dev->pdev, I965_GDRST,
 725                               gdrst | GRDOM_RENDER |
 726                               GRDOM_RESET_ENABLE);
 727         ret =  wait_for(i965_reset_complete(dev), 500);
 728         if (ret)
 729                 return ret;
 730
 731         /* We can't reset render&media without also resetting display ... */
 732         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 733         pci_write_config_byte(dev->pdev, I965_GDRST,
 734                               gdrst | GRDOM_MEDIA |
 735                               GRDOM_RESET_ENABLE);
 736
 737         return wait_for(i965_reset_complete(dev), 500);
 738 }
 739
 740 static int ironlake_do_reset(struct drm_device *dev)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         u32 gdrst;
 744         int ret;
 745
 746         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 747         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 748                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 749         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 750         if (ret)
 751                 return ret;
 752
 753         /* We can't reset render&media without also resetting display ... */
 754         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 755         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 756                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 757         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 758 }
 759
 760 static int gen6_do_reset(struct drm_device *dev)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         int     ret;
 764         unsigned long irqflags;
 765
 766         /* Hold gt_lock across reset to prevent any register access
 767          * with forcewake not set correctly
 768          */
 769         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 770
 771         /* Reset the chip */
 772
 773         /* GEN6_GDRST is not in the gt power well, no need to check
 774          * for fifo space for the write or forcewake the chip for
 775          * the read
 776          */
 777         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 778
 779         /* Spin waiting for the device to ack the reset request */
 780         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 781
 782         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 783         if (dev_priv->forcewake_count)
 784                 dev_priv->gt.force_wake_get(dev_priv);
 785         else
 786                 dev_priv->gt.force_wake_put(dev_priv);
 787
 788         /* Restore fifo count */
 789         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 790
 791         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 792         return ret;
 793 }
 794
 795 int intel_gpu_reset(struct drm_device *dev)
 796 {
 797         struct drm_i915_private *dev_priv = dev->dev_private;
 798         int ret = -ENODEV;
 799
 800         switch (INTEL_INFO(dev)->gen) {
 801         case 7:
 802         case 6:
 803                 ret = gen6_do_reset(dev);
 804                 break;
 805         case 5:
 806                 ret = ironlake_do_reset(dev);
 807                 break;
 808         case 4:
 809                 ret = i965_do_reset(dev);
 810                 break;
 811         case 2:
 812                 ret = i8xx_do_reset(dev);
 813                 break;
 814         }
 815
 816         /* Also reset the gpu hangman. */
 817         if (dev_priv->gpu_error.stop_rings) {
 818                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 819                 dev_priv->gpu_error.stop_rings = 0;
 820                 if (ret == -ENODEV) {
 821                         DRM_ERROR("Reset not implemented, but ignoring "
 822                                   "error for simulated gpu hangs\n");
 823                         ret = 0;
 824                 }
 825         }
 826
 827         return ret;
 828 }
 829
 830 /**
 831  * i915_reset - reset chip after a hang
 832  * @dev: drm device to reset
 833  *
 834  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 835  * reset or otherwise an error code.
 836  *
 837  * Procedure is fairly simple:
 838  *   - reset the chip using the reset reg
 839  *   - re-init context state
 840  *   - re-init hardware status page
 841  *   - re-init ring buffer
 842  *   - re-init interrupt state
 843  *   - re-init display
 844  */
 845 int i915_reset(struct drm_device *dev)
 846 {
 847         drm_i915_private_t *dev_priv = dev->dev_private;
 848         int ret;
 849
 850         if (!i915_try_reset)
 851                 return 0;
 852
 853         mutex_lock(&dev->struct_mutex);
 854
 855         i915_gem_reset(dev);
 856
 857         ret = -ENODEV;
 858         if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
 859                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 860         else
 861                 ret = intel_gpu_reset(dev);
 862
 863         dev_priv->gpu_error.last_reset = get_seconds();
 864         if (ret) {
 865                 DRM_ERROR("Failed to reset chip.\n");
 866                 mutex_unlock(&dev->struct_mutex);
 867                 return ret;
 868         }
 869
 870         /* Ok, now get things going again... */
 871
 872         /*
 873          * Everything depends on having the GTT running, so we need to start
 874          * there.  Fortunately we don't need to do this unless we reset the
 875          * chip at a PCI level.
 876          *
 877          * Next we need to restore the context, but we don't use those
 878          * yet either...
 879          *
 880          * Ring buffer needs to be re-initialized in the KMS case, or if X
 881          * was running at the time of the reset (i.e. we weren't VT
 882          * switched away).
 883          */
 884         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 885                         !dev_priv->mm.suspended) {
 886                 struct intel_ring_buffer *ring;
 887                 int i;
 888
 889                 dev_priv->mm.suspended = 0;
 890
 891                 i915_gem_init_swizzling(dev);
 892
 893                 for_each_ring(ring, dev_priv, i)
 894                         ring->init(ring);
 895
 896                 i915_gem_context_init(dev);
 897                 i915_gem_init_ppgtt(dev);
 898
 899                 /*
 900                  * It would make sense to re-init all the other hw state, at
 901                  * least the rps/rc6/emon init done within modeset_init_hw. For
 902                  * some unknown reason, this blows up my ilk, so don't.
 903                  */
 904
 905                 mutex_unlock(&dev->struct_mutex);
 906
 907                 drm_irq_uninstall(dev);
 908                 drm_irq_install(dev);
 909                 intel_hpd_init(dev);
 910         } else {
 911                 mutex_unlock(&dev->struct_mutex);
 912         }
 913
 914         return 0;
 915 }
 916
 917 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 918 {
 919         struct intel_device_info *intel_info =
 920                 (struct intel_device_info *) ent->driver_data;
 921
 922         if (intel_info->is_valleyview)
 923                 if(!i915_preliminary_hw_support) {
 924                         DRM_ERROR("Preliminary hardware support disabled\n");
 925                         return -ENODEV;
 926                 }
 927
 928         /* Only bind to function 0 of the device. Early generations
 929          * used function 1 as a placeholder for multi-head. This causes
 930          * us confusion instead, especially on the systems where both
 931          * functions have the same PCI-ID!
 932          */
 933         if (PCI_FUNC(pdev->devfn))
 934                 return -ENODEV;
 935
 936         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 937          * implementation for gen3 (and only gen3) that used legacy drm maps
 938          * (gasp!) to share buffers between X and the client. Hence we need to
 939          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 940         if (intel_info->gen != 3) {
 941                 driver.driver_features &=
 942                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 943         } else if (!intel_agp_enabled) {
 944                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 945                 return -ENODEV;
 946         }
 947
 948         return drm_get_pci_dev(pdev, ent, &driver);
 949 }
 950
 951 static void
 952 i915_pci_remove(struct pci_dev *pdev)
 953 {
 954         struct drm_device *dev = pci_get_drvdata(pdev);
 955
 956         drm_put_dev(dev);
 957 }
 958
 959 static int i915_pm_suspend(struct device *dev)
 960 {
 961         struct pci_dev *pdev = to_pci_dev(dev);
 962         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 963         int error;
 964
 965         if (!drm_dev || !drm_dev->dev_private) {
 966                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 967                 return -ENODEV;
 968         }
 969
 970         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 971                 return 0;
 972
 973         error = i915_drm_freeze(drm_dev);
 974         if (error)
 975                 return error;
 976
 977         pci_disable_device(pdev);
 978         pci_set_power_state(pdev, PCI_D3hot);
 979
 980         return 0;
 981 }
 982
 983 static int i915_pm_resume(struct device *dev)
 984 {
 985         struct pci_dev *pdev = to_pci_dev(dev);
 986         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 987
 988         return i915_resume(drm_dev);
 989 }
 990
 991 static int i915_pm_freeze(struct device *dev)
 992 {
 993         struct pci_dev *pdev = to_pci_dev(dev);
 994         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 995
 996         if (!drm_dev || !drm_dev->dev_private) {
 997                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 998                 return -ENODEV;
 999         }
1000
1001         return i915_drm_freeze(drm_dev);
1002 }
1003
1004 static int i915_pm_thaw(struct device *dev)
1005 {
1006         struct pci_dev *pdev = to_pci_dev(dev);
1007         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1008
1009         return i915_drm_thaw(drm_dev);
1010 }
1011
1012 static int i915_pm_poweroff(struct device *dev)
1013 {
1014         struct pci_dev *pdev = to_pci_dev(dev);
1015         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1016
1017         return i915_drm_freeze(drm_dev);
1018 }
1019
1020 static const struct dev_pm_ops i915_pm_ops = {
1021         .suspend = i915_pm_suspend,
1022         .resume = i915_pm_resume,
1023         .freeze = i915_pm_freeze,
1024         .thaw = i915_pm_thaw,
1025         .poweroff = i915_pm_poweroff,
1026         .restore = i915_pm_resume,
1027 };
1028
1029 static const struct vm_operations_struct i915_gem_vm_ops = {
1030         .fault = i915_gem_fault,
1031         .open = drm_gem_vm_open,
1032         .close = drm_gem_vm_close,
1033 };
1034
1035 static const struct file_operations i915_driver_fops = {
1036         .owner = THIS_MODULE,
1037         .open = drm_open,
1038         .release = drm_release,
1039         .unlocked_ioctl = drm_ioctl,
1040         .mmap = drm_gem_mmap,
1041         .poll = drm_poll,
1042         .fasync = drm_fasync,
1043         .read = drm_read,
1044 #ifdef CONFIG_COMPAT
1045         .compat_ioctl = i915_compat_ioctl,
1046 #endif
1047         .llseek = noop_llseek,
1048 };
1049
1050 static struct drm_driver driver = {
1051         /* Don't use MTRRs here; the Xserver or userspace app should
1052          * deal with them for Intel hardware.
1053          */
1054         .driver_features =
1055             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1056             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1057         .load = i915_driver_load,
1058         .unload = i915_driver_unload,
1059         .open = i915_driver_open,
1060         .lastclose = i915_driver_lastclose,
1061         .preclose = i915_driver_preclose,
1062         .postclose = i915_driver_postclose,
1063
1064         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1065         .suspend = i915_suspend,
1066         .resume = i915_resume,
1067
1068         .device_is_agp = i915_driver_device_is_agp,
1069         .master_create = i915_master_create,
1070         .master_destroy = i915_master_destroy,
1071 #if defined(CONFIG_DEBUG_FS)
1072         .debugfs_init = i915_debugfs_init,
1073         .debugfs_cleanup = i915_debugfs_cleanup,
1074 #endif
1075         .gem_init_object = i915_gem_init_object,
1076         .gem_free_object = i915_gem_free_object,
1077         .gem_vm_ops = &i915_gem_vm_ops,
1078
1079         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1080         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1081         .gem_prime_export = i915_gem_prime_export,
1082         .gem_prime_import = i915_gem_prime_import,
1083
1084         .dumb_create = i915_gem_dumb_create,
1085         .dumb_map_offset = i915_gem_mmap_gtt,
1086         .dumb_destroy = i915_gem_dumb_destroy,
1087         .ioctls = i915_ioctls,
1088         .fops = &i915_driver_fops,
1089         .name = DRIVER_NAME,
1090         .desc = DRIVER_DESC,
1091         .date = DRIVER_DATE,
1092         .major = DRIVER_MAJOR,
1093         .minor = DRIVER_MINOR,
1094         .patchlevel = DRIVER_PATCHLEVEL,
1095 };
1096
1097 static struct pci_driver i915_pci_driver = {
1098         .name = DRIVER_NAME,
1099         .id_table = pciidlist,
1100         .probe = i915_pci_probe,
1101         .remove = i915_pci_remove,
1102         .driver.pm = &i915_pm_ops,
1103 };
1104
1105 static int __init i915_init(void)
1106 {
1107         driver.num_ioctls = i915_max_ioctl;
1108
1109         /*
1110          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1111          * explicitly disabled with the module pararmeter.
1112          *
1113          * Otherwise, just follow the parameter (defaulting to off).
1114          *
1115          * Allow optional vga_text_mode_force boot option to override
1116          * the default behavior.
1117          */
1118 #if defined(CONFIG_DRM_I915_KMS)
1119         if (i915_modeset != 0)
1120                 driver.driver_features |= DRIVER_MODESET;
1121 #endif
1122         if (i915_modeset == 1)
1123                 driver.driver_features |= DRIVER_MODESET;
1124
1125 #ifdef CONFIG_VGA_CONSOLE
1126         if (vgacon_text_force() && i915_modeset == -1)
1127                 driver.driver_features &= ~DRIVER_MODESET;
1128 #endif
1129
1130         if (!(driver.driver_features & DRIVER_MODESET))
1131                 driver.get_vblank_timestamp = NULL;
1132
1133         return drm_pci_init(&driver, &i915_pci_driver);
1134 }
1135
1136 static void __exit i915_exit(void)
1137 {
1138         drm_pci_exit(&driver, &i915_pci_driver);
1139 }
1140
1141 module_init(i915_init);
1142 module_exit(i915_exit);
1143
1144 MODULE_AUTHOR(DRIVER_AUTHOR);
1145 MODULE_DESCRIPTION(DRIVER_DESC);
1146 MODULE_LICENSE("GPL and additional rights");
1147
1148 /* We give fast paths for the really cool registers */
1149 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1150         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1151          ((reg) < 0x40000) &&            \
1152          ((reg) != FORCEWAKE))
1153 static void
1154 ilk_dummy_write(struct drm_i915_private *dev_priv)
1155 {
1156         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1157          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1158          * harmless to write 0 into. */
1159         I915_WRITE_NOTRACE(MI_MODE, 0);
1160 }
1161
1162 static void
1163 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1164 {
1165         if (IS_HASWELL(dev_priv->dev) &&
1166             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1167                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1168                           reg);
1169                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1170         }
1171 }
1172
1173 static void
1174 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1175 {
1176         if (IS_HASWELL(dev_priv->dev) &&
1177             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1178                 DRM_ERROR("Unclaimed write to %x\n", reg);
1179                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1180         }
1181 }
1182
1183 #define __i915_read(x, y) \
1184 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1185         u##x val = 0; \
1186         if (IS_GEN5(dev_priv->dev)) \
1187                 ilk_dummy_write(dev_priv); \
1188         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1189                 unsigned long irqflags; \
1190                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1191                 if (dev_priv->forcewake_count == 0) \
1192                         dev_priv->gt.force_wake_get(dev_priv); \
1193                 val = read##y(dev_priv->regs + reg); \
1194                 if (dev_priv->forcewake_count == 0) \
1195                         dev_priv->gt.force_wake_put(dev_priv); \
1196                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1197         } else { \
1198                 val = read##y(dev_priv->regs + reg); \
1199         } \
1200         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1201         return val; \
1202 }
1203
1204 __i915_read(8, b)
1205 __i915_read(16, w)
1206 __i915_read(32, l)
1207 __i915_read(64, q)
1208 #undef __i915_read
1209
1210 #define __i915_write(x, y) \
1211 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1212         u32 __fifo_ret = 0; \
1213         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1214         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1215                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1216         } \
1217         if (IS_GEN5(dev_priv->dev)) \
1218                 ilk_dummy_write(dev_priv); \
1219         hsw_unclaimed_reg_clear(dev_priv, reg); \
1220         write##y(val, dev_priv->regs + reg); \
1221         if (unlikely(__fifo_ret)) { \
1222                 gen6_gt_check_fifodbg(dev_priv); \
1223         } \
1224         hsw_unclaimed_reg_check(dev_priv, reg); \
1225 }
1226 __i915_write(8, b)
1227 __i915_write(16, w)
1228 __i915_write(32, l)
1229 __i915_write(64, q)
1230 #undef __i915_write
1231
1232 static const struct register_whitelist {
1233         uint64_t offset;
1234         uint32_t size;
1235         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1236 } whitelist[] = {
1237         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1238 };
1239
1240 int i915_reg_read_ioctl(struct drm_device *dev,
1241                         void *data, struct drm_file *file)
1242 {
1243         struct drm_i915_private *dev_priv = dev->dev_private;
1244         struct drm_i915_reg_read *reg = data;
1245         struct register_whitelist const *entry = whitelist;
1246         int i;
1247
1248         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1249                 if (entry->offset == reg->offset &&
1250                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1251                         break;
1252         }
1253
1254         if (i == ARRAY_SIZE(whitelist))
1255                 return -EINVAL;
1256
1257         switch (entry->size) {
1258         case 8:
1259                 reg->val = I915_READ64(reg->offset);
1260                 break;
1261         case 4:
1262                 reg->val = I915_READ(reg->offset);
1263                 break;
1264         case 2:
1265                 reg->val = I915_READ16(reg->offset);
1266                 break;
1267         case 1:
1268                 reg->val = I915_READ8(reg->offset);
1269                 break;
1270         default:
1271                 WARN_ON(1);
1272                 return -EINVAL;
1273         }
1274
1275         return 0;
1276 }