Pileus Git - ~andy/linux/blob - drivers/gpio/gpio-lpc32xx.c

   1 /*
   2  * GPIO driver for LPC32xx SoC
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/errno.h>
  23 #include <linux/gpio.h>
  24 #include <linux/of_gpio.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/module.h>
  27
  28 #include <mach/hardware.h>
  29 #include <mach/platform.h>
  30 #include <mach/gpio-lpc32xx.h>
  31 #include <mach/irqs.h>
  32
  33 #define LPC32XX_GPIO_P3_INP_STATE               _GPREG(0x000)
  34 #define LPC32XX_GPIO_P3_OUTP_SET                _GPREG(0x004)
  35 #define LPC32XX_GPIO_P3_OUTP_CLR                _GPREG(0x008)
  36 #define LPC32XX_GPIO_P3_OUTP_STATE              _GPREG(0x00C)
  37 #define LPC32XX_GPIO_P2_DIR_SET                 _GPREG(0x010)
  38 #define LPC32XX_GPIO_P2_DIR_CLR                 _GPREG(0x014)
  39 #define LPC32XX_GPIO_P2_DIR_STATE               _GPREG(0x018)
  40 #define LPC32XX_GPIO_P2_INP_STATE               _GPREG(0x01C)
  41 #define LPC32XX_GPIO_P2_OUTP_SET                _GPREG(0x020)
  42 #define LPC32XX_GPIO_P2_OUTP_CLR                _GPREG(0x024)
  43 #define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
  44 #define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
  45 #define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
  46 #define LPC32XX_GPIO_P0_INP_STATE               _GPREG(0x040)
  47 #define LPC32XX_GPIO_P0_OUTP_SET                _GPREG(0x044)
  48 #define LPC32XX_GPIO_P0_OUTP_CLR                _GPREG(0x048)
  49 #define LPC32XX_GPIO_P0_OUTP_STATE              _GPREG(0x04C)
  50 #define LPC32XX_GPIO_P0_DIR_SET                 _GPREG(0x050)
  51 #define LPC32XX_GPIO_P0_DIR_CLR                 _GPREG(0x054)
  52 #define LPC32XX_GPIO_P0_DIR_STATE               _GPREG(0x058)
  53 #define LPC32XX_GPIO_P1_INP_STATE               _GPREG(0x060)
  54 #define LPC32XX_GPIO_P1_OUTP_SET                _GPREG(0x064)
  55 #define LPC32XX_GPIO_P1_OUTP_CLR                _GPREG(0x068)
  56 #define LPC32XX_GPIO_P1_OUTP_STATE              _GPREG(0x06C)
  57 #define LPC32XX_GPIO_P1_DIR_SET                 _GPREG(0x070)
  58 #define LPC32XX_GPIO_P1_DIR_CLR                 _GPREG(0x074)
  59 #define LPC32XX_GPIO_P1_DIR_STATE               _GPREG(0x078)
  60
  61 #define GPIO012_PIN_TO_BIT(x)                   (1 << (x))
  62 #define GPIO3_PIN_TO_BIT(x)                     (1 << ((x) + 25))
  63 #define GPO3_PIN_TO_BIT(x)                      (1 << (x))
  64 #define GPIO012_PIN_IN_SEL(x, y)                (((x) >> (y)) & 1)
  65 #define GPIO3_PIN_IN_SHIFT(x)                   ((x) == 5 ? 24 : 10 + (x))
  66 #define GPIO3_PIN_IN_SEL(x, y)                  (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
  67 #define GPIO3_PIN5_IN_SEL(x)                    (((x) >> 24) & 1)
  68 #define GPI3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
  69 #define GPO3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
  70
  71 struct gpio_regs {
  72         void __iomem *inp_state;
  73         void __iomem *outp_state;
  74         void __iomem *outp_set;
  75         void __iomem *outp_clr;
  76         void __iomem *dir_set;
  77         void __iomem *dir_clr;
  78 };
  79
  80 /*
  81  * GPIO names
  82  */
  83 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
  84         "p0.0", "p0.1", "p0.2", "p0.3",
  85         "p0.4", "p0.5", "p0.6", "p0.7"
  86 };
  87
  88 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
  89         "p1.0", "p1.1", "p1.2", "p1.3",
  90         "p1.4", "p1.5", "p1.6", "p1.7",
  91         "p1.8", "p1.9", "p1.10", "p1.11",
  92         "p1.12", "p1.13", "p1.14", "p1.15",
  93         "p1.16", "p1.17", "p1.18", "p1.19",
  94         "p1.20", "p1.21", "p1.22", "p1.23",
  95 };
  96
  97 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
  98         "p2.0", "p2.1", "p2.2", "p2.3",
  99         "p2.4", "p2.5", "p2.6", "p2.7",
 100         "p2.8", "p2.9", "p2.10", "p2.11",
 101         "p2.12"
 102 };
 103
 104 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
 105         "gpio00", "gpio01", "gpio02", "gpio03",
 106         "gpio04", "gpio05"
 107 };
 108
 109 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
 110         "gpi00", "gpi01", "gpi02", "gpi03",
 111         "gpi04", "gpi05", "gpi06", "gpi07",
 112         "gpi08", "gpi09",  NULL,    NULL,
 113          NULL,    NULL,    NULL,   "gpi15",
 114         "gpi16", "gpi17", "gpi18", "gpi19",
 115         "gpi20", "gpi21", "gpi22", "gpi23",
 116         "gpi24", "gpi25", "gpi26", "gpi27"
 117 };
 118
 119 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
 120         "gpo00", "gpo01", "gpo02", "gpo03",
 121         "gpo04", "gpo05", "gpo06", "gpo07",
 122         "gpo08", "gpo09", "gpo10", "gpo11",
 123         "gpo12", "gpo13", "gpo14", "gpo15",
 124         "gpo16", "gpo17", "gpo18", "gpo19",
 125         "gpo20", "gpo21", "gpo22", "gpo23"
 126 };
 127
 128 static struct gpio_regs gpio_grp_regs_p0 = {
 129         .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
 130         .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
 131         .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
 132         .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
 133         .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
 134 };
 135
 136 static struct gpio_regs gpio_grp_regs_p1 = {
 137         .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
 138         .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
 139         .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
 140         .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
 141         .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
 142 };
 143
 144 static struct gpio_regs gpio_grp_regs_p2 = {
 145         .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
 146         .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
 147         .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
 148         .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
 149         .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
 150 };
 151
 152 static struct gpio_regs gpio_grp_regs_p3 = {
 153         .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
 154         .outp_state     = LPC32XX_GPIO_P3_OUTP_STATE,
 155         .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
 156         .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
 157         .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
 158         .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
 159 };
 160
 161 struct lpc32xx_gpio_chip {
 162         struct gpio_chip        chip;
 163         struct gpio_regs        *gpio_grp;
 164 };
 165
 166 static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
 167         struct gpio_chip *gpc)
 168 {
 169         return container_of(gpc, struct lpc32xx_gpio_chip, chip);
 170 }
 171
 172 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
 173         unsigned pin, int input)
 174 {
 175         if (input)
 176                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
 177                         group->gpio_grp->dir_clr);
 178         else
 179                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
 180                         group->gpio_grp->dir_set);
 181 }
 182
 183 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
 184         unsigned pin, int input)
 185 {
 186         u32 u = GPIO3_PIN_TO_BIT(pin);
 187
 188         if (input)
 189                 __raw_writel(u, group->gpio_grp->dir_clr);
 190         else
 191                 __raw_writel(u, group->gpio_grp->dir_set);
 192 }
 193
 194 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
 195         unsigned pin, int high)
 196 {
 197         if (high)
 198                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
 199                         group->gpio_grp->outp_set);
 200         else
 201                 __raw_writel(GPIO012_PIN_TO_BIT(pin),
 202                         group->gpio_grp->outp_clr);
 203 }
 204
 205 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
 206         unsigned pin, int high)
 207 {
 208         u32 u = GPIO3_PIN_TO_BIT(pin);
 209
 210         if (high)
 211                 __raw_writel(u, group->gpio_grp->outp_set);
 212         else
 213                 __raw_writel(u, group->gpio_grp->outp_clr);
 214 }
 215
 216 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
 217         unsigned pin, int high)
 218 {
 219         if (high)
 220                 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
 221         else
 222                 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
 223 }
 224
 225 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
 226         unsigned pin)
 227 {
 228         return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
 229                 pin);
 230 }
 231
 232 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
 233         unsigned pin)
 234 {
 235         int state = __raw_readl(group->gpio_grp->inp_state);
 236
 237         /*
 238          * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
 239          * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
 240          */
 241         return GPIO3_PIN_IN_SEL(state, pin);
 242 }
 243
 244 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
 245         unsigned pin)
 246 {
 247         return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
 248 }
 249
 250 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
 251         unsigned pin)
 252 {
 253         return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
 254 }
 255
 256 /*
 257  * GENERIC_GPIO primitives.
 258  */
 259 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
 260         unsigned pin)
 261 {
 262         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 263
 264         __set_gpio_dir_p012(group, pin, 1);
 265
 266         return 0;
 267 }
 268
 269 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
 270         unsigned pin)
 271 {
 272         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 273
 274         __set_gpio_dir_p3(group, pin, 1);
 275
 276         return 0;
 277 }
 278
 279 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
 280         unsigned pin)
 281 {
 282         return 0;
 283 }
 284
 285 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
 286 {
 287         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 288
 289         return __get_gpio_state_p012(group, pin);
 290 }
 291
 292 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
 293 {
 294         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 295
 296         return __get_gpio_state_p3(group, pin);
 297 }
 298
 299 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
 300 {
 301         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 302
 303         return __get_gpi_state_p3(group, pin);
 304 }
 305
 306 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
 307         int value)
 308 {
 309         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 310
 311         __set_gpio_dir_p012(group, pin, 0);
 312
 313         return 0;
 314 }
 315
 316 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
 317         int value)
 318 {
 319         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 320
 321         __set_gpio_dir_p3(group, pin, 0);
 322
 323         return 0;
 324 }
 325
 326 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
 327         int value)
 328 {
 329         return 0;
 330 }
 331
 332 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
 333         int value)
 334 {
 335         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 336
 337         __set_gpio_level_p012(group, pin, value);
 338 }
 339
 340 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
 341         int value)
 342 {
 343         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 344
 345         __set_gpio_level_p3(group, pin, value);
 346 }
 347
 348 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
 349         int value)
 350 {
 351         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 352
 353         __set_gpo_level_p3(group, pin, value);
 354 }
 355
 356 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
 357 {
 358         struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
 359
 360         return __get_gpo_state_p3(group, pin);
 361 }
 362
 363 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
 364 {
 365         if (pin < chip->ngpio)
 366                 return 0;
 367
 368         return -EINVAL;
 369 }
 370
 371 static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
 372 {
 373         return IRQ_LPC32XX_P0_P1_IRQ;
 374 }
 375
 376 static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = {
 377         IRQ_LPC32XX_GPIO_00,
 378         IRQ_LPC32XX_GPIO_01,
 379         IRQ_LPC32XX_GPIO_02,
 380         IRQ_LPC32XX_GPIO_03,
 381         IRQ_LPC32XX_GPIO_04,
 382         IRQ_LPC32XX_GPIO_05,
 383 };
 384
 385 static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
 386 {
 387         if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table))
 388                 return lpc32xx_gpio_to_irq_gpio_p3_table[offset];
 389         return -ENXIO;
 390 }
 391
 392 static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = {
 393         IRQ_LPC32XX_GPI_00,
 394         IRQ_LPC32XX_GPI_01,
 395         IRQ_LPC32XX_GPI_02,
 396         IRQ_LPC32XX_GPI_03,
 397         IRQ_LPC32XX_GPI_04,
 398         IRQ_LPC32XX_GPI_05,
 399         IRQ_LPC32XX_GPI_06,
 400         IRQ_LPC32XX_GPI_07,
 401         IRQ_LPC32XX_GPI_08,
 402         IRQ_LPC32XX_GPI_09,
 403         -ENXIO, /* 10 */
 404         -ENXIO, /* 11 */
 405         -ENXIO, /* 12 */
 406         -ENXIO, /* 13 */
 407         -ENXIO, /* 14 */
 408         -ENXIO, /* 15 */
 409         -ENXIO, /* 16 */
 410         -ENXIO, /* 17 */
 411         -ENXIO, /* 18 */
 412         IRQ_LPC32XX_GPI_19,
 413         -ENXIO, /* 20 */
 414         -ENXIO, /* 21 */
 415         -ENXIO, /* 22 */
 416         -ENXIO, /* 23 */
 417         -ENXIO, /* 24 */
 418         -ENXIO, /* 25 */
 419         -ENXIO, /* 26 */
 420         -ENXIO, /* 27 */
 421         IRQ_LPC32XX_GPI_28,
 422 };
 423
 424 static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
 425 {
 426         if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table))
 427                 return lpc32xx_gpio_to_irq_gpi_p3_table[offset];
 428         return -ENXIO;
 429 }
 430
 431 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 432         {
 433                 .chip = {
 434                         .label                  = "gpio_p0",
 435                         .direction_input        = lpc32xx_gpio_dir_input_p012,
 436                         .get                    = lpc32xx_gpio_get_value_p012,
 437                         .direction_output       = lpc32xx_gpio_dir_output_p012,
 438                         .set                    = lpc32xx_gpio_set_value_p012,
 439                         .request                = lpc32xx_gpio_request,
 440                         .to_irq                 = lpc32xx_gpio_to_irq_p01,
 441                         .base                   = LPC32XX_GPIO_P0_GRP,
 442                         .ngpio                  = LPC32XX_GPIO_P0_MAX,
 443                         .names                  = gpio_p0_names,
 444                         .can_sleep              = 0,
 445                 },
 446                 .gpio_grp = &gpio_grp_regs_p0,
 447         },
 448         {
 449                 .chip = {
 450                         .label                  = "gpio_p1",
 451                         .direction_input        = lpc32xx_gpio_dir_input_p012,
 452                         .get                    = lpc32xx_gpio_get_value_p012,
 453                         .direction_output       = lpc32xx_gpio_dir_output_p012,
 454                         .set                    = lpc32xx_gpio_set_value_p012,
 455                         .request                = lpc32xx_gpio_request,
 456                         .to_irq                 = lpc32xx_gpio_to_irq_p01,
 457                         .base                   = LPC32XX_GPIO_P1_GRP,
 458                         .ngpio                  = LPC32XX_GPIO_P1_MAX,
 459                         .names                  = gpio_p1_names,
 460                         .can_sleep              = 0,
 461                 },
 462                 .gpio_grp = &gpio_grp_regs_p1,
 463         },
 464         {
 465                 .chip = {
 466                         .label                  = "gpio_p2",
 467                         .direction_input        = lpc32xx_gpio_dir_input_p012,
 468                         .get                    = lpc32xx_gpio_get_value_p012,
 469                         .direction_output       = lpc32xx_gpio_dir_output_p012,
 470                         .set                    = lpc32xx_gpio_set_value_p012,
 471                         .request                = lpc32xx_gpio_request,
 472                         .base                   = LPC32XX_GPIO_P2_GRP,
 473                         .ngpio                  = LPC32XX_GPIO_P2_MAX,
 474                         .names                  = gpio_p2_names,
 475                         .can_sleep              = 0,
 476                 },
 477                 .gpio_grp = &gpio_grp_regs_p2,
 478         },
 479         {
 480                 .chip = {
 481                         .label                  = "gpio_p3",
 482                         .direction_input        = lpc32xx_gpio_dir_input_p3,
 483                         .get                    = lpc32xx_gpio_get_value_p3,
 484                         .direction_output       = lpc32xx_gpio_dir_output_p3,
 485                         .set                    = lpc32xx_gpio_set_value_p3,
 486                         .request                = lpc32xx_gpio_request,
 487                         .to_irq                 = lpc32xx_gpio_to_irq_gpio_p3,
 488                         .base                   = LPC32XX_GPIO_P3_GRP,
 489                         .ngpio                  = LPC32XX_GPIO_P3_MAX,
 490                         .names                  = gpio_p3_names,
 491                         .can_sleep              = 0,
 492                 },
 493                 .gpio_grp = &gpio_grp_regs_p3,
 494         },
 495         {
 496                 .chip = {
 497                         .label                  = "gpi_p3",
 498                         .direction_input        = lpc32xx_gpio_dir_in_always,
 499                         .get                    = lpc32xx_gpi_get_value,
 500                         .request                = lpc32xx_gpio_request,
 501                         .to_irq                 = lpc32xx_gpio_to_irq_gpi_p3,
 502                         .base                   = LPC32XX_GPI_P3_GRP,
 503                         .ngpio                  = LPC32XX_GPI_P3_MAX,
 504                         .names                  = gpi_p3_names,
 505                         .can_sleep              = 0,
 506                 },
 507                 .gpio_grp = &gpio_grp_regs_p3,
 508         },
 509         {
 510                 .chip = {
 511                         .label                  = "gpo_p3",
 512                         .direction_output       = lpc32xx_gpio_dir_out_always,
 513                         .set                    = lpc32xx_gpo_set_value,
 514                         .get                    = lpc32xx_gpo_get_value,
 515                         .request                = lpc32xx_gpio_request,
 516                         .base                   = LPC32XX_GPO_P3_GRP,
 517                         .ngpio                  = LPC32XX_GPO_P3_MAX,
 518                         .names                  = gpo_p3_names,
 519                         .can_sleep              = 0,
 520                 },
 521                 .gpio_grp = &gpio_grp_regs_p3,
 522         },
 523 };
 524
 525 static int lpc32xx_of_xlate(struct gpio_chip *gc,
 526                             const struct of_phandle_args *gpiospec, u32 *flags)
 527 {
 528         /* Is this the correct bank? */
 529         u32 bank = gpiospec->args[0];
 530         if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) ||
 531             (gc != &lpc32xx_gpiochip[bank].chip)))
 532                 return -EINVAL;
 533
 534         if (flags)
 535                 *flags = gpiospec->args[2];
 536         return gpiospec->args[1];
 537 }
 538
 539 static int __devinit lpc32xx_gpio_probe(struct platform_device *pdev)
 540 {
 541         int i;
 542
 543         for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
 544                 if (pdev->dev.of_node) {
 545                         lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
 546                         lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
 547                         lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
 548                 }
 549                 gpiochip_add(&lpc32xx_gpiochip[i].chip);
 550         }
 551
 552         return 0;
 553 }
 554
 555 #ifdef CONFIG_OF
 556 static struct of_device_id lpc32xx_gpio_of_match[] __devinitdata = {
 557         { .compatible = "nxp,lpc3220-gpio", },
 558         { },
 559 };
 560 #endif
 561
 562 static struct platform_driver lpc32xx_gpio_driver = {
 563         .driver         = {
 564                 .name   = "lpc32xx-gpio",
 565                 .owner  = THIS_MODULE,
 566                 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
 567         },
 568         .probe          = lpc32xx_gpio_probe,
 569 };
 570
 571 module_platform_driver(lpc32xx_gpio_driver);