Pileus Git - ~andy/linux/blob - drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49 #include <asm/system.h>
  50
  51 #ifdef CONFIG_PPC_PMAC
  52 #include <asm/pmac_feature.h>
  53 #endif
  54
  55 #include "core.h"
  56 #include "ohci.h"
  57
  58 #define DESCRIPTOR_OUTPUT_MORE          0
  59 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  60 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  61 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  62 #define DESCRIPTOR_STATUS               (1 << 11)
  63 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  64 #define DESCRIPTOR_PING                 (1 << 7)
  65 #define DESCRIPTOR_YY                   (1 << 6)
  66 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  67 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  68 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  69 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  70 #define DESCRIPTOR_WAIT                 (3 << 0)
  71
  72 struct descriptor {
  73         __le16 req_count;
  74         __le16 control;
  75         __le32 data_address;
  76         __le32 branch_address;
  77         __le16 res_count;
  78         __le16 transfer_status;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 #define AR_BUFFER_SIZE  (32*1024)
  87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  88 /* we need at least two pages for proper list management */
  89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  90
  91 #define MAX_ASYNC_PAYLOAD       4096
  92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  94
  95 struct ar_context {
  96         struct fw_ohci *ohci;
  97         struct page *pages[AR_BUFFERS];
  98         void *buffer;
  99         struct descriptor *descriptors;
 100         dma_addr_t descriptors_bus;
 101         void *pointer;
 102         unsigned int last_buffer_index;
 103         u32 regs;
 104         struct tasklet_struct tasklet;
 105 };
 106
 107 struct context;
 108
 109 typedef int (*descriptor_callback_t)(struct context *ctx,
 110                                      struct descriptor *d,
 111                                      struct descriptor *last);
 112
 113 /*
 114  * A buffer that contains a block of DMA-able coherent memory used for
 115  * storing a portion of a DMA descriptor program.
 116  */
 117 struct descriptor_buffer {
 118         struct list_head list;
 119         dma_addr_t buffer_bus;
 120         size_t buffer_size;
 121         size_t used;
 122         struct descriptor buffer[0];
 123 };
 124
 125 struct context {
 126         struct fw_ohci *ohci;
 127         u32 regs;
 128         int total_allocation;
 129         u32 current_bus;
 130         bool running;
 131         bool flushing;
 132
 133         /*
 134          * List of page-sized buffers for storing DMA descriptors.
 135          * Head of list contains buffers in use and tail of list contains
 136          * free buffers.
 137          */
 138         struct list_head buffer_list;
 139
 140         /*
 141          * Pointer to a buffer inside buffer_list that contains the tail
 142          * end of the current DMA program.
 143          */
 144         struct descriptor_buffer *buffer_tail;
 145
 146         /*
 147          * The descriptor containing the branch address of the first
 148          * descriptor that has not yet been filled by the device.
 149          */
 150         struct descriptor *last;
 151
 152         /*
 153          * The last descriptor in the DMA program.  It contains the branch
 154          * address that must be updated upon appending a new descriptor.
 155          */
 156         struct descriptor *prev;
 157
 158         descriptor_callback_t callback;
 159
 160         struct tasklet_struct tasklet;
 161 };
 162
 163 #define IT_HEADER_SY(v)          ((v) <<  0)
 164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 166 #define IT_HEADER_TAG(v)         ((v) << 14)
 167 #define IT_HEADER_SPEED(v)       ((v) << 16)
 168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 169
 170 struct iso_context {
 171         struct fw_iso_context base;
 172         struct context context;
 173         void *header;
 174         size_t header_length;
 175         unsigned long flushing_completions;
 176         u32 mc_buffer_bus;
 177         u16 mc_completed;
 178         u16 last_timestamp;
 179         u8 sync;
 180         u8 tags;
 181 };
 182
 183 #define CONFIG_ROM_SIZE 1024
 184
 185 struct fw_ohci {
 186         struct fw_card card;
 187
 188         __iomem char *registers;
 189         int node_id;
 190         int generation;
 191         int request_generation; /* for timestamping incoming requests */
 192         unsigned quirks;
 193         unsigned int pri_req_max;
 194         u32 bus_time;
 195         bool is_root;
 196         bool csr_state_setclear_abdicate;
 197         int n_ir;
 198         int n_it;
 199         /*
 200          * Spinlock for accessing fw_ohci data.  Never call out of
 201          * this driver with this lock held.
 202          */
 203         spinlock_t lock;
 204
 205         struct mutex phy_reg_mutex;
 206
 207         void *misc_buffer;
 208         dma_addr_t misc_buffer_bus;
 209
 210         struct ar_context ar_request_ctx;
 211         struct ar_context ar_response_ctx;
 212         struct context at_request_ctx;
 213         struct context at_response_ctx;
 214
 215         u32 it_context_support;
 216         u32 it_context_mask;     /* unoccupied IT contexts */
 217         struct iso_context *it_context_list;
 218         u64 ir_context_channels; /* unoccupied channels */
 219         u32 ir_context_support;
 220         u32 ir_context_mask;     /* unoccupied IR contexts */
 221         struct iso_context *ir_context_list;
 222         u64 mc_channels; /* channels in use by the multichannel IR context */
 223         bool mc_allocated;
 224
 225         __be32    *config_rom;
 226         dma_addr_t config_rom_bus;
 227         __be32    *next_config_rom;
 228         dma_addr_t next_config_rom_bus;
 229         __be32     next_header;
 230
 231         __le32    *self_id_cpu;
 232         dma_addr_t self_id_bus;
 233         struct work_struct bus_reset_work;
 234
 235         u32 self_id_buffer[512];
 236 };
 237
 238 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 239 {
 240         return container_of(card, struct fw_ohci, card);
 241 }
 242
 243 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 244 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 245 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 246 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 247 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 248 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 249
 250 #define CONTEXT_RUN     0x8000
 251 #define CONTEXT_WAKE    0x1000
 252 #define CONTEXT_DEAD    0x0800
 253 #define CONTEXT_ACTIVE  0x0400
 254
 255 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 256 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 257 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 258
 259 #define OHCI1394_REGISTER_SIZE          0x800
 260 #define OHCI1394_PCI_HCI_Control        0x40
 261 #define SELF_ID_BUF_SIZE                0x800
 262 #define OHCI_TCODE_PHY_PACKET           0x0e
 263 #define OHCI_VERSION_1_1                0x010010
 264
 265 static char ohci_driver_name[] = KBUILD_MODNAME;
 266
 267 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 268 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 269 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 270 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 271 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 272 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 273
 274 #define QUIRK_CYCLE_TIMER               1
 275 #define QUIRK_RESET_PACKET              2
 276 #define QUIRK_BE_HEADERS                4
 277 #define QUIRK_NO_1394A                  8
 278 #define QUIRK_NO_MSI                    16
 279 #define QUIRK_TI_SLLZ059                32
 280
 281 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 282 static const struct {
 283         unsigned short vendor, device, revision, flags;
 284 } ohci_quirks[] = {
 285         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 286                 QUIRK_CYCLE_TIMER},
 287
 288         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 289                 QUIRK_BE_HEADERS},
 290
 291         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 292                 QUIRK_NO_MSI},
 293
 294         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 295                 QUIRK_NO_MSI},
 296
 297         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 298                 QUIRK_CYCLE_TIMER},
 299
 300         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 301                 QUIRK_NO_MSI},
 302
 303         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 304                 QUIRK_CYCLE_TIMER},
 305
 306         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 307                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 308
 309         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 310                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 311
 312         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 313                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 314
 315         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 316                 QUIRK_RESET_PACKET},
 317
 318         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 319                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 320 };
 321
 322 /* This overrides anything that was found in ohci_quirks[]. */
 323 static int param_quirks;
 324 module_param_named(quirks, param_quirks, int, 0644);
 325 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 326         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 327         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 328         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 329         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 330         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 331         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 332         ")");
 333
 334 #define OHCI_PARAM_DEBUG_AT_AR          1
 335 #define OHCI_PARAM_DEBUG_SELFIDS        2
 336 #define OHCI_PARAM_DEBUG_IRQS           4
 337 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 338
 339 static int param_debug;
 340 module_param_named(debug, param_debug, int, 0644);
 341 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 342         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 343         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 344         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 345         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 346         ", or a combination, or all = -1)");
 347
 348 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 349 {
 350         if (likely(!(param_debug &
 351                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 352                 return;
 353
 354         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 355             !(evt & OHCI1394_busReset))
 356                 return;
 357
 358         dev_notice(ohci->card.device,
 359             "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 360             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 361             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 362             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 363             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 364             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 365             evt & OHCI1394_isochRx              ? " IR"                 : "",
 366             evt & OHCI1394_isochTx              ? " IT"                 : "",
 367             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 368             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 369             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 370             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 371             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 372             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 373             evt & OHCI1394_busReset             ? " busReset"           : "",
 374             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 375                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 376                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 377                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 378                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 379                     OHCI1394_cycleInconsistent |
 380                     OHCI1394_regAccessFail | OHCI1394_busReset)
 381                                                 ? " ?"                  : "");
 382 }
 383
 384 static const char *speed[] = {
 385         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 386 };
 387 static const char *power[] = {
 388         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 389         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 390 };
 391 static const char port[] = { '.', '-', 'p', 'c', };
 392
 393 static char _p(u32 *s, int shift)
 394 {
 395         return port[*s >> shift & 3];
 396 }
 397
 398 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 399 {
 400         u32 *s;
 401
 402         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 403                 return;
 404
 405         dev_notice(ohci->card.device,
 406                    "%d selfIDs, generation %d, local node ID %04x\n",
 407                    self_id_count, generation, ohci->node_id);
 408
 409         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 410                 if ((*s & 1 << 23) == 0)
 411                         dev_notice(ohci->card.device,
 412                             "selfID 0: %08x, phy %d [%c%c%c] "
 413                             "%s gc=%d %s %s%s%s\n",
 414                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 415                             speed[*s >> 14 & 3], *s >> 16 & 63,
 416                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 417                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 418                 else
 419                         dev_notice(ohci->card.device,
 420                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 421                             *s, *s >> 24 & 63,
 422                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 423                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 424 }
 425
 426 static const char *evts[] = {
 427         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 428         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 429         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 430         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 431         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 432         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 433         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 434         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 435         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 436         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 437         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 438         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 439         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 440         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 441         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 442         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 443         [0x20] = "pending/cancelled",
 444 };
 445 static const char *tcodes[] = {
 446         [0x0] = "QW req",               [0x1] = "BW req",
 447         [0x2] = "W resp",               [0x3] = "-reserved-",
 448         [0x4] = "QR req",               [0x5] = "BR req",
 449         [0x6] = "QR resp",              [0x7] = "BR resp",
 450         [0x8] = "cycle start",          [0x9] = "Lk req",
 451         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 452         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 453         [0xe] = "link internal",        [0xf] = "-reserved-",
 454 };
 455
 456 static void log_ar_at_event(struct fw_ohci *ohci,
 457                             char dir, int speed, u32 *header, int evt)
 458 {
 459         int tcode = header[0] >> 4 & 0xf;
 460         char specific[12];
 461
 462         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 463                 return;
 464
 465         if (unlikely(evt >= ARRAY_SIZE(evts)))
 466                         evt = 0x1f;
 467
 468         if (evt == OHCI1394_evt_bus_reset) {
 469                 dev_notice(ohci->card.device,
 470                            "A%c evt_bus_reset, generation %d\n",
 471                            dir, (header[2] >> 16) & 0xff);
 472                 return;
 473         }
 474
 475         switch (tcode) {
 476         case 0x0: case 0x6: case 0x8:
 477                 snprintf(specific, sizeof(specific), " = %08x",
 478                          be32_to_cpu((__force __be32)header[3]));
 479                 break;
 480         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 481                 snprintf(specific, sizeof(specific), " %x,%x",
 482                          header[3] >> 16, header[3] & 0xffff);
 483                 break;
 484         default:
 485                 specific[0] = '\0';
 486         }
 487
 488         switch (tcode) {
 489         case 0xa:
 490                 dev_notice(ohci->card.device,
 491                            "A%c %s, %s\n",
 492                            dir, evts[evt], tcodes[tcode]);
 493                 break;
 494         case 0xe:
 495                 dev_notice(ohci->card.device,
 496                            "A%c %s, PHY %08x %08x\n",
 497                            dir, evts[evt], header[1], header[2]);
 498                 break;
 499         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 500                 dev_notice(ohci->card.device,
 501                            "A%c spd %x tl %02x, "
 502                            "%04x -> %04x, %s, "
 503                            "%s, %04x%08x%s\n",
 504                            dir, speed, header[0] >> 10 & 0x3f,
 505                            header[1] >> 16, header[0] >> 16, evts[evt],
 506                            tcodes[tcode], header[1] & 0xffff, header[2], specific);
 507                 break;
 508         default:
 509                 dev_notice(ohci->card.device,
 510                            "A%c spd %x tl %02x, "
 511                            "%04x -> %04x, %s, "
 512                            "%s%s\n",
 513                            dir, speed, header[0] >> 10 & 0x3f,
 514                            header[1] >> 16, header[0] >> 16, evts[evt],
 515                            tcodes[tcode], specific);
 516         }
 517 }
 518
 519 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 520 {
 521         writel(data, ohci->registers + offset);
 522 }
 523
 524 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 525 {
 526         return readl(ohci->registers + offset);
 527 }
 528
 529 static inline void flush_writes(const struct fw_ohci *ohci)
 530 {
 531         /* Do a dummy read to flush writes. */
 532         reg_read(ohci, OHCI1394_Version);
 533 }
 534
 535 /*
 536  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 537  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 538  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 539  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 540  */
 541 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 542 {
 543         u32 val;
 544         int i;
 545
 546         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 547         for (i = 0; i < 3 + 100; i++) {
 548                 val = reg_read(ohci, OHCI1394_PhyControl);
 549                 if (!~val)
 550                         return -ENODEV; /* Card was ejected. */
 551
 552                 if (val & OHCI1394_PhyControl_ReadDone)
 553                         return OHCI1394_PhyControl_ReadData(val);
 554
 555                 /*
 556                  * Try a few times without waiting.  Sleeping is necessary
 557                  * only when the link/PHY interface is busy.
 558                  */
 559                 if (i >= 3)
 560                         msleep(1);
 561         }
 562         dev_err(ohci->card.device, "failed to read phy reg\n");
 563
 564         return -EBUSY;
 565 }
 566
 567 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 568 {
 569         int i;
 570
 571         reg_write(ohci, OHCI1394_PhyControl,
 572                   OHCI1394_PhyControl_Write(addr, val));
 573         for (i = 0; i < 3 + 100; i++) {
 574                 val = reg_read(ohci, OHCI1394_PhyControl);
 575                 if (!~val)
 576                         return -ENODEV; /* Card was ejected. */
 577
 578                 if (!(val & OHCI1394_PhyControl_WritePending))
 579                         return 0;
 580
 581                 if (i >= 3)
 582                         msleep(1);
 583         }
 584         dev_err(ohci->card.device, "failed to write phy reg\n");
 585
 586         return -EBUSY;
 587 }
 588
 589 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 590                           int clear_bits, int set_bits)
 591 {
 592         int ret = read_phy_reg(ohci, addr);
 593         if (ret < 0)
 594                 return ret;
 595
 596         /*
 597          * The interrupt status bits are cleared by writing a one bit.
 598          * Avoid clearing them unless explicitly requested in set_bits.
 599          */
 600         if (addr == 5)
 601                 clear_bits |= PHY_INT_STATUS_BITS;
 602
 603         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 604 }
 605
 606 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 607 {
 608         int ret;
 609
 610         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 611         if (ret < 0)
 612                 return ret;
 613
 614         return read_phy_reg(ohci, addr);
 615 }
 616
 617 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 618 {
 619         struct fw_ohci *ohci = fw_ohci(card);
 620         int ret;
 621
 622         mutex_lock(&ohci->phy_reg_mutex);
 623         ret = read_phy_reg(ohci, addr);
 624         mutex_unlock(&ohci->phy_reg_mutex);
 625
 626         return ret;
 627 }
 628
 629 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 630                                int clear_bits, int set_bits)
 631 {
 632         struct fw_ohci *ohci = fw_ohci(card);
 633         int ret;
 634
 635         mutex_lock(&ohci->phy_reg_mutex);
 636         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 637         mutex_unlock(&ohci->phy_reg_mutex);
 638
 639         return ret;
 640 }
 641
 642 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 643 {
 644         return page_private(ctx->pages[i]);
 645 }
 646
 647 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 648 {
 649         struct descriptor *d;
 650
 651         d = &ctx->descriptors[index];
 652         d->branch_address  &= cpu_to_le32(~0xf);
 653         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 654         d->transfer_status =  0;
 655
 656         wmb(); /* finish init of new descriptors before branch_address update */
 657         d = &ctx->descriptors[ctx->last_buffer_index];
 658         d->branch_address  |= cpu_to_le32(1);
 659
 660         ctx->last_buffer_index = index;
 661
 662         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 663 }
 664
 665 static void ar_context_release(struct ar_context *ctx)
 666 {
 667         unsigned int i;
 668
 669         if (ctx->buffer)
 670                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 671
 672         for (i = 0; i < AR_BUFFERS; i++)
 673                 if (ctx->pages[i]) {
 674                         dma_unmap_page(ctx->ohci->card.device,
 675                                        ar_buffer_bus(ctx, i),
 676                                        PAGE_SIZE, DMA_FROM_DEVICE);
 677                         __free_page(ctx->pages[i]);
 678                 }
 679 }
 680
 681 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 682 {
 683         struct fw_ohci *ohci = ctx->ohci;
 684
 685         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 686                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 687                 flush_writes(ohci);
 688
 689                 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
 690                         error_msg);
 691         }
 692         /* FIXME: restart? */
 693 }
 694
 695 static inline unsigned int ar_next_buffer_index(unsigned int index)
 696 {
 697         return (index + 1) % AR_BUFFERS;
 698 }
 699
 700 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 701 {
 702         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 703 }
 704
 705 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 706 {
 707         return ar_next_buffer_index(ctx->last_buffer_index);
 708 }
 709
 710 /*
 711  * We search for the buffer that contains the last AR packet DMA data written
 712  * by the controller.
 713  */
 714 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 715                                                  unsigned int *buffer_offset)
 716 {
 717         unsigned int i, next_i, last = ctx->last_buffer_index;
 718         __le16 res_count, next_res_count;
 719
 720         i = ar_first_buffer_index(ctx);
 721         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 722
 723         /* A buffer that is not yet completely filled must be the last one. */
 724         while (i != last && res_count == 0) {
 725
 726                 /* Peek at the next descriptor. */
 727                 next_i = ar_next_buffer_index(i);
 728                 rmb(); /* read descriptors in order */
 729                 next_res_count = ACCESS_ONCE(
 730                                 ctx->descriptors[next_i].res_count);
 731                 /*
 732                  * If the next descriptor is still empty, we must stop at this
 733                  * descriptor.
 734                  */
 735                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 736                         /*
 737                          * The exception is when the DMA data for one packet is
 738                          * split over three buffers; in this case, the middle
 739                          * buffer's descriptor might be never updated by the
 740                          * controller and look still empty, and we have to peek
 741                          * at the third one.
 742                          */
 743                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 744                                 next_i = ar_next_buffer_index(next_i);
 745                                 rmb();
 746                                 next_res_count = ACCESS_ONCE(
 747                                         ctx->descriptors[next_i].res_count);
 748                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 749                                         goto next_buffer_is_active;
 750                         }
 751
 752                         break;
 753                 }
 754
 755 next_buffer_is_active:
 756                 i = next_i;
 757                 res_count = next_res_count;
 758         }
 759
 760         rmb(); /* read res_count before the DMA data */
 761
 762         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 763         if (*buffer_offset > PAGE_SIZE) {
 764                 *buffer_offset = 0;
 765                 ar_context_abort(ctx, "corrupted descriptor");
 766         }
 767
 768         return i;
 769 }
 770
 771 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 772                                     unsigned int end_buffer_index,
 773                                     unsigned int end_buffer_offset)
 774 {
 775         unsigned int i;
 776
 777         i = ar_first_buffer_index(ctx);
 778         while (i != end_buffer_index) {
 779                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 780                                         ar_buffer_bus(ctx, i),
 781                                         PAGE_SIZE, DMA_FROM_DEVICE);
 782                 i = ar_next_buffer_index(i);
 783         }
 784         if (end_buffer_offset > 0)
 785                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 786                                         ar_buffer_bus(ctx, i),
 787                                         end_buffer_offset, DMA_FROM_DEVICE);
 788 }
 789
 790 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 791 #define cond_le32_to_cpu(v) \
 792         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 793 #else
 794 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 795 #endif
 796
 797 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 798 {
 799         struct fw_ohci *ohci = ctx->ohci;
 800         struct fw_packet p;
 801         u32 status, length, tcode;
 802         int evt;
 803
 804         p.header[0] = cond_le32_to_cpu(buffer[0]);
 805         p.header[1] = cond_le32_to_cpu(buffer[1]);
 806         p.header[2] = cond_le32_to_cpu(buffer[2]);
 807
 808         tcode = (p.header[0] >> 4) & 0x0f;
 809         switch (tcode) {
 810         case TCODE_WRITE_QUADLET_REQUEST:
 811         case TCODE_READ_QUADLET_RESPONSE:
 812                 p.header[3] = (__force __u32) buffer[3];
 813                 p.header_length = 16;
 814                 p.payload_length = 0;
 815                 break;
 816
 817         case TCODE_READ_BLOCK_REQUEST :
 818                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 819                 p.header_length = 16;
 820                 p.payload_length = 0;
 821                 break;
 822
 823         case TCODE_WRITE_BLOCK_REQUEST:
 824         case TCODE_READ_BLOCK_RESPONSE:
 825         case TCODE_LOCK_REQUEST:
 826         case TCODE_LOCK_RESPONSE:
 827                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 828                 p.header_length = 16;
 829                 p.payload_length = p.header[3] >> 16;
 830                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 831                         ar_context_abort(ctx, "invalid packet length");
 832                         return NULL;
 833                 }
 834                 break;
 835
 836         case TCODE_WRITE_RESPONSE:
 837         case TCODE_READ_QUADLET_REQUEST:
 838         case OHCI_TCODE_PHY_PACKET:
 839                 p.header_length = 12;
 840                 p.payload_length = 0;
 841                 break;
 842
 843         default:
 844                 ar_context_abort(ctx, "invalid tcode");
 845                 return NULL;
 846         }
 847
 848         p.payload = (void *) buffer + p.header_length;
 849
 850         /* FIXME: What to do about evt_* errors? */
 851         length = (p.header_length + p.payload_length + 3) / 4;
 852         status = cond_le32_to_cpu(buffer[length]);
 853         evt    = (status >> 16) & 0x1f;
 854
 855         p.ack        = evt - 16;
 856         p.speed      = (status >> 21) & 0x7;
 857         p.timestamp  = status & 0xffff;
 858         p.generation = ohci->request_generation;
 859
 860         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 861
 862         /*
 863          * Several controllers, notably from NEC and VIA, forget to
 864          * write ack_complete status at PHY packet reception.
 865          */
 866         if (evt == OHCI1394_evt_no_status &&
 867             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 868                 p.ack = ACK_COMPLETE;
 869
 870         /*
 871          * The OHCI bus reset handler synthesizes a PHY packet with
 872          * the new generation number when a bus reset happens (see
 873          * section 8.4.2.3).  This helps us determine when a request
 874          * was received and make sure we send the response in the same
 875          * generation.  We only need this for requests; for responses
 876          * we use the unique tlabel for finding the matching
 877          * request.
 878          *
 879          * Alas some chips sometimes emit bus reset packets with a
 880          * wrong generation.  We set the correct generation for these
 881          * at a slightly incorrect time (in bus_reset_work).
 882          */
 883         if (evt == OHCI1394_evt_bus_reset) {
 884                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 885                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 886         } else if (ctx == &ohci->ar_request_ctx) {
 887                 fw_core_handle_request(&ohci->card, &p);
 888         } else {
 889                 fw_core_handle_response(&ohci->card, &p);
 890         }
 891
 892         return buffer + length + 1;
 893 }
 894
 895 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 896 {
 897         void *next;
 898
 899         while (p < end) {
 900                 next = handle_ar_packet(ctx, p);
 901                 if (!next)
 902                         return p;
 903                 p = next;
 904         }
 905
 906         return p;
 907 }
 908
 909 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 910 {
 911         unsigned int i;
 912
 913         i = ar_first_buffer_index(ctx);
 914         while (i != end_buffer) {
 915                 dma_sync_single_for_device(ctx->ohci->card.device,
 916                                            ar_buffer_bus(ctx, i),
 917                                            PAGE_SIZE, DMA_FROM_DEVICE);
 918                 ar_context_link_page(ctx, i);
 919                 i = ar_next_buffer_index(i);
 920         }
 921 }
 922
 923 static void ar_context_tasklet(unsigned long data)
 924 {
 925         struct ar_context *ctx = (struct ar_context *)data;
 926         unsigned int end_buffer_index, end_buffer_offset;
 927         void *p, *end;
 928
 929         p = ctx->pointer;
 930         if (!p)
 931                 return;
 932
 933         end_buffer_index = ar_search_last_active_buffer(ctx,
 934                                                         &end_buffer_offset);
 935         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 936         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 937
 938         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 939                 /*
 940                  * The filled part of the overall buffer wraps around; handle
 941                  * all packets up to the buffer end here.  If the last packet
 942                  * wraps around, its tail will be visible after the buffer end
 943                  * because the buffer start pages are mapped there again.
 944                  */
 945                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 946                 p = handle_ar_packets(ctx, p, buffer_end);
 947                 if (p < buffer_end)
 948                         goto error;
 949                 /* adjust p to point back into the actual buffer */
 950                 p -= AR_BUFFERS * PAGE_SIZE;
 951         }
 952
 953         p = handle_ar_packets(ctx, p, end);
 954         if (p != end) {
 955                 if (p > end)
 956                         ar_context_abort(ctx, "inconsistent descriptor");
 957                 goto error;
 958         }
 959
 960         ctx->pointer = p;
 961         ar_recycle_buffers(ctx, end_buffer_index);
 962
 963         return;
 964
 965 error:
 966         ctx->pointer = NULL;
 967 }
 968
 969 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 970                            unsigned int descriptors_offset, u32 regs)
 971 {
 972         unsigned int i;
 973         dma_addr_t dma_addr;
 974         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 975         struct descriptor *d;
 976
 977         ctx->regs        = regs;
 978         ctx->ohci        = ohci;
 979         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 980
 981         for (i = 0; i < AR_BUFFERS; i++) {
 982                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 983                 if (!ctx->pages[i])
 984                         goto out_of_memory;
 985                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 986                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 987                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 988                         __free_page(ctx->pages[i]);
 989                         ctx->pages[i] = NULL;
 990                         goto out_of_memory;
 991                 }
 992                 set_page_private(ctx->pages[i], dma_addr);
 993         }
 994
 995         for (i = 0; i < AR_BUFFERS; i++)
 996                 pages[i]              = ctx->pages[i];
 997         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 998                 pages[AR_BUFFERS + i] = ctx->pages[i];
 999         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1000                                  -1, PAGE_KERNEL);
1001         if (!ctx->buffer)
1002                 goto out_of_memory;
1003
1004         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1005         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1006
1007         for (i = 0; i < AR_BUFFERS; i++) {
1008                 d = &ctx->descriptors[i];
1009                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1010                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1011                                                 DESCRIPTOR_STATUS |
1012                                                 DESCRIPTOR_BRANCH_ALWAYS);
1013                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1014                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1015                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1016         }
1017
1018         return 0;
1019
1020 out_of_memory:
1021         ar_context_release(ctx);
1022
1023         return -ENOMEM;
1024 }
1025
1026 static void ar_context_run(struct ar_context *ctx)
1027 {
1028         unsigned int i;
1029
1030         for (i = 0; i < AR_BUFFERS; i++)
1031                 ar_context_link_page(ctx, i);
1032
1033         ctx->pointer = ctx->buffer;
1034
1035         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1036         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1037 }
1038
1039 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1040 {
1041         __le16 branch;
1042
1043         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1044
1045         /* figure out which descriptor the branch address goes in */
1046         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1047                 return d;
1048         else
1049                 return d + z - 1;
1050 }
1051
1052 static void context_tasklet(unsigned long data)
1053 {
1054         struct context *ctx = (struct context *) data;
1055         struct descriptor *d, *last;
1056         u32 address;
1057         int z;
1058         struct descriptor_buffer *desc;
1059
1060         desc = list_entry(ctx->buffer_list.next,
1061                         struct descriptor_buffer, list);
1062         last = ctx->last;
1063         while (last->branch_address != 0) {
1064                 struct descriptor_buffer *old_desc = desc;
1065                 address = le32_to_cpu(last->branch_address);
1066                 z = address & 0xf;
1067                 address &= ~0xf;
1068                 ctx->current_bus = address;
1069
1070                 /* If the branch address points to a buffer outside of the
1071                  * current buffer, advance to the next buffer. */
1072                 if (address < desc->buffer_bus ||
1073                                 address >= desc->buffer_bus + desc->used)
1074                         desc = list_entry(desc->list.next,
1075                                         struct descriptor_buffer, list);
1076                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1077                 last = find_branch_descriptor(d, z);
1078
1079                 if (!ctx->callback(ctx, d, last))
1080                         break;
1081
1082                 if (old_desc != desc) {
1083                         /* If we've advanced to the next buffer, move the
1084                          * previous buffer to the free list. */
1085                         unsigned long flags;
1086                         old_desc->used = 0;
1087                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1088                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1089                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1090                 }
1091                 ctx->last = last;
1092         }
1093 }
1094
1095 /*
1096  * Allocate a new buffer and add it to the list of free buffers for this
1097  * context.  Must be called with ohci->lock held.
1098  */
1099 static int context_add_buffer(struct context *ctx)
1100 {
1101         struct descriptor_buffer *desc;
1102         dma_addr_t uninitialized_var(bus_addr);
1103         int offset;
1104
1105         /*
1106          * 16MB of descriptors should be far more than enough for any DMA
1107          * program.  This will catch run-away userspace or DoS attacks.
1108          */
1109         if (ctx->total_allocation >= 16*1024*1024)
1110                 return -ENOMEM;
1111
1112         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1113                         &bus_addr, GFP_ATOMIC);
1114         if (!desc)
1115                 return -ENOMEM;
1116
1117         offset = (void *)&desc->buffer - (void *)desc;
1118         desc->buffer_size = PAGE_SIZE - offset;
1119         desc->buffer_bus = bus_addr + offset;
1120         desc->used = 0;
1121
1122         list_add_tail(&desc->list, &ctx->buffer_list);
1123         ctx->total_allocation += PAGE_SIZE;
1124
1125         return 0;
1126 }
1127
1128 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1129                         u32 regs, descriptor_callback_t callback)
1130 {
1131         ctx->ohci = ohci;
1132         ctx->regs = regs;
1133         ctx->total_allocation = 0;
1134
1135         INIT_LIST_HEAD(&ctx->buffer_list);
1136         if (context_add_buffer(ctx) < 0)
1137                 return -ENOMEM;
1138
1139         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1140                         struct descriptor_buffer, list);
1141
1142         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1143         ctx->callback = callback;
1144
1145         /*
1146          * We put a dummy descriptor in the buffer that has a NULL
1147          * branch address and looks like it's been sent.  That way we
1148          * have a descriptor to append DMA programs to.
1149          */
1150         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1151         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1152         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1153         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1154         ctx->last = ctx->buffer_tail->buffer;
1155         ctx->prev = ctx->buffer_tail->buffer;
1156
1157         return 0;
1158 }
1159
1160 static void context_release(struct context *ctx)
1161 {
1162         struct fw_card *card = &ctx->ohci->card;
1163         struct descriptor_buffer *desc, *tmp;
1164
1165         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1166                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1167                         desc->buffer_bus -
1168                         ((void *)&desc->buffer - (void *)desc));
1169 }
1170
1171 /* Must be called with ohci->lock held */
1172 static struct descriptor *context_get_descriptors(struct context *ctx,
1173                                                   int z, dma_addr_t *d_bus)
1174 {
1175         struct descriptor *d = NULL;
1176         struct descriptor_buffer *desc = ctx->buffer_tail;
1177
1178         if (z * sizeof(*d) > desc->buffer_size)
1179                 return NULL;
1180
1181         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1182                 /* No room for the descriptor in this buffer, so advance to the
1183                  * next one. */
1184
1185                 if (desc->list.next == &ctx->buffer_list) {
1186                         /* If there is no free buffer next in the list,
1187                          * allocate one. */
1188                         if (context_add_buffer(ctx) < 0)
1189                                 return NULL;
1190                 }
1191                 desc = list_entry(desc->list.next,
1192                                 struct descriptor_buffer, list);
1193                 ctx->buffer_tail = desc;
1194         }
1195
1196         d = desc->buffer + desc->used / sizeof(*d);
1197         memset(d, 0, z * sizeof(*d));
1198         *d_bus = desc->buffer_bus + desc->used;
1199
1200         return d;
1201 }
1202
1203 static void context_run(struct context *ctx, u32 extra)
1204 {
1205         struct fw_ohci *ohci = ctx->ohci;
1206
1207         reg_write(ohci, COMMAND_PTR(ctx->regs),
1208                   le32_to_cpu(ctx->last->branch_address));
1209         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1210         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1211         ctx->running = true;
1212         flush_writes(ohci);
1213 }
1214
1215 static void context_append(struct context *ctx,
1216                            struct descriptor *d, int z, int extra)
1217 {
1218         dma_addr_t d_bus;
1219         struct descriptor_buffer *desc = ctx->buffer_tail;
1220
1221         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1222
1223         desc->used += (z + extra) * sizeof(*d);
1224
1225         wmb(); /* finish init of new descriptors before branch_address update */
1226         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1227         ctx->prev = find_branch_descriptor(d, z);
1228 }
1229
1230 static void context_stop(struct context *ctx)
1231 {
1232         struct fw_ohci *ohci = ctx->ohci;
1233         u32 reg;
1234         int i;
1235
1236         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1237         ctx->running = false;
1238
1239         for (i = 0; i < 1000; i++) {
1240                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1241                 if ((reg & CONTEXT_ACTIVE) == 0)
1242                         return;
1243
1244                 if (i)
1245                         udelay(10);
1246         }
1247         dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
1248 }
1249
1250 struct driver_data {
1251         u8 inline_data[8];
1252         struct fw_packet *packet;
1253 };
1254
1255 /*
1256  * This function apppends a packet to the DMA queue for transmission.
1257  * Must always be called with the ochi->lock held to ensure proper
1258  * generation handling and locking around packet queue manipulation.
1259  */
1260 static int at_context_queue_packet(struct context *ctx,
1261                                    struct fw_packet *packet)
1262 {
1263         struct fw_ohci *ohci = ctx->ohci;
1264         dma_addr_t d_bus, uninitialized_var(payload_bus);
1265         struct driver_data *driver_data;
1266         struct descriptor *d, *last;
1267         __le32 *header;
1268         int z, tcode;
1269
1270         d = context_get_descriptors(ctx, 4, &d_bus);
1271         if (d == NULL) {
1272                 packet->ack = RCODE_SEND_ERROR;
1273                 return -1;
1274         }
1275
1276         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1277         d[0].res_count = cpu_to_le16(packet->timestamp);
1278
1279         /*
1280          * The DMA format for asyncronous link packets is different
1281          * from the IEEE1394 layout, so shift the fields around
1282          * accordingly.
1283          */
1284
1285         tcode = (packet->header[0] >> 4) & 0x0f;
1286         header = (__le32 *) &d[1];
1287         switch (tcode) {
1288         case TCODE_WRITE_QUADLET_REQUEST:
1289         case TCODE_WRITE_BLOCK_REQUEST:
1290         case TCODE_WRITE_RESPONSE:
1291         case TCODE_READ_QUADLET_REQUEST:
1292         case TCODE_READ_BLOCK_REQUEST:
1293         case TCODE_READ_QUADLET_RESPONSE:
1294         case TCODE_READ_BLOCK_RESPONSE:
1295         case TCODE_LOCK_REQUEST:
1296         case TCODE_LOCK_RESPONSE:
1297                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1298                                         (packet->speed << 16));
1299                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1300                                         (packet->header[0] & 0xffff0000));
1301                 header[2] = cpu_to_le32(packet->header[2]);
1302
1303                 if (TCODE_IS_BLOCK_PACKET(tcode))
1304                         header[3] = cpu_to_le32(packet->header[3]);
1305                 else
1306                         header[3] = (__force __le32) packet->header[3];
1307
1308                 d[0].req_count = cpu_to_le16(packet->header_length);
1309                 break;
1310
1311         case TCODE_LINK_INTERNAL:
1312                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1313                                         (packet->speed << 16));
1314                 header[1] = cpu_to_le32(packet->header[1]);
1315                 header[2] = cpu_to_le32(packet->header[2]);
1316                 d[0].req_count = cpu_to_le16(12);
1317
1318                 if (is_ping_packet(&packet->header[1]))
1319                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1320                 break;
1321
1322         case TCODE_STREAM_DATA:
1323                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1324                                         (packet->speed << 16));
1325                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1326                 d[0].req_count = cpu_to_le16(8);
1327                 break;
1328
1329         default:
1330                 /* BUG(); */
1331                 packet->ack = RCODE_SEND_ERROR;
1332                 return -1;
1333         }
1334
1335         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1336         driver_data = (struct driver_data *) &d[3];
1337         driver_data->packet = packet;
1338         packet->driver_data = driver_data;
1339
1340         if (packet->payload_length > 0) {
1341                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1342                         payload_bus = dma_map_single(ohci->card.device,
1343                                                      packet->payload,
1344                                                      packet->payload_length,
1345                                                      DMA_TO_DEVICE);
1346                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1347                                 packet->ack = RCODE_SEND_ERROR;
1348                                 return -1;
1349                         }
1350                         packet->payload_bus     = payload_bus;
1351                         packet->payload_mapped  = true;
1352                 } else {
1353                         memcpy(driver_data->inline_data, packet->payload,
1354                                packet->payload_length);
1355                         payload_bus = d_bus + 3 * sizeof(*d);
1356                 }
1357
1358                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1359                 d[2].data_address = cpu_to_le32(payload_bus);
1360                 last = &d[2];
1361                 z = 3;
1362         } else {
1363                 last = &d[0];
1364                 z = 2;
1365         }
1366
1367         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1368                                      DESCRIPTOR_IRQ_ALWAYS |
1369                                      DESCRIPTOR_BRANCH_ALWAYS);
1370
1371         /* FIXME: Document how the locking works. */
1372         if (ohci->generation != packet->generation) {
1373                 if (packet->payload_mapped)
1374                         dma_unmap_single(ohci->card.device, payload_bus,
1375                                          packet->payload_length, DMA_TO_DEVICE);
1376                 packet->ack = RCODE_GENERATION;
1377                 return -1;
1378         }
1379
1380         context_append(ctx, d, z, 4 - z);
1381
1382         if (ctx->running)
1383                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1384         else
1385                 context_run(ctx, 0);
1386
1387         return 0;
1388 }
1389
1390 static void at_context_flush(struct context *ctx)
1391 {
1392         tasklet_disable(&ctx->tasklet);
1393
1394         ctx->flushing = true;
1395         context_tasklet((unsigned long)ctx);
1396         ctx->flushing = false;
1397
1398         tasklet_enable(&ctx->tasklet);
1399 }
1400
1401 static int handle_at_packet(struct context *context,
1402                             struct descriptor *d,
1403                             struct descriptor *last)
1404 {
1405         struct driver_data *driver_data;
1406         struct fw_packet *packet;
1407         struct fw_ohci *ohci = context->ohci;
1408         int evt;
1409
1410         if (last->transfer_status == 0 && !context->flushing)
1411                 /* This descriptor isn't done yet, stop iteration. */
1412                 return 0;
1413
1414         driver_data = (struct driver_data *) &d[3];
1415         packet = driver_data->packet;
1416         if (packet == NULL)
1417                 /* This packet was cancelled, just continue. */
1418                 return 1;
1419
1420         if (packet->payload_mapped)
1421                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1422                                  packet->payload_length, DMA_TO_DEVICE);
1423
1424         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1425         packet->timestamp = le16_to_cpu(last->res_count);
1426
1427         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1428
1429         switch (evt) {
1430         case OHCI1394_evt_timeout:
1431                 /* Async response transmit timed out. */
1432                 packet->ack = RCODE_CANCELLED;
1433                 break;
1434
1435         case OHCI1394_evt_flushed:
1436                 /*
1437                  * The packet was flushed should give same error as
1438                  * when we try to use a stale generation count.
1439                  */
1440                 packet->ack = RCODE_GENERATION;
1441                 break;
1442
1443         case OHCI1394_evt_missing_ack:
1444                 if (context->flushing)
1445                         packet->ack = RCODE_GENERATION;
1446                 else {
1447                         /*
1448                          * Using a valid (current) generation count, but the
1449                          * node is not on the bus or not sending acks.
1450                          */
1451                         packet->ack = RCODE_NO_ACK;
1452                 }
1453                 break;
1454
1455         case ACK_COMPLETE + 0x10:
1456         case ACK_PENDING + 0x10:
1457         case ACK_BUSY_X + 0x10:
1458         case ACK_BUSY_A + 0x10:
1459         case ACK_BUSY_B + 0x10:
1460         case ACK_DATA_ERROR + 0x10:
1461         case ACK_TYPE_ERROR + 0x10:
1462                 packet->ack = evt - 0x10;
1463                 break;
1464
1465         case OHCI1394_evt_no_status:
1466                 if (context->flushing) {
1467                         packet->ack = RCODE_GENERATION;
1468                         break;
1469                 }
1470                 /* fall through */
1471
1472         default:
1473                 packet->ack = RCODE_SEND_ERROR;
1474                 break;
1475         }
1476
1477         packet->callback(packet, &ohci->card, packet->ack);
1478
1479         return 1;
1480 }
1481
1482 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1483 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1484 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1485 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1486 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1487
1488 static void handle_local_rom(struct fw_ohci *ohci,
1489                              struct fw_packet *packet, u32 csr)
1490 {
1491         struct fw_packet response;
1492         int tcode, length, i;
1493
1494         tcode = HEADER_GET_TCODE(packet->header[0]);
1495         if (TCODE_IS_BLOCK_PACKET(tcode))
1496                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1497         else
1498                 length = 4;
1499
1500         i = csr - CSR_CONFIG_ROM;
1501         if (i + length > CONFIG_ROM_SIZE) {
1502                 fw_fill_response(&response, packet->header,
1503                                  RCODE_ADDRESS_ERROR, NULL, 0);
1504         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1505                 fw_fill_response(&response, packet->header,
1506                                  RCODE_TYPE_ERROR, NULL, 0);
1507         } else {
1508                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1509                                  (void *) ohci->config_rom + i, length);
1510         }
1511
1512         fw_core_handle_response(&ohci->card, &response);
1513 }
1514
1515 static void handle_local_lock(struct fw_ohci *ohci,
1516                               struct fw_packet *packet, u32 csr)
1517 {
1518         struct fw_packet response;
1519         int tcode, length, ext_tcode, sel, try;
1520         __be32 *payload, lock_old;
1521         u32 lock_arg, lock_data;
1522
1523         tcode = HEADER_GET_TCODE(packet->header[0]);
1524         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1525         payload = packet->payload;
1526         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1527
1528         if (tcode == TCODE_LOCK_REQUEST &&
1529             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1530                 lock_arg = be32_to_cpu(payload[0]);
1531                 lock_data = be32_to_cpu(payload[1]);
1532         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1533                 lock_arg = 0;
1534                 lock_data = 0;
1535         } else {
1536                 fw_fill_response(&response, packet->header,
1537                                  RCODE_TYPE_ERROR, NULL, 0);
1538                 goto out;
1539         }
1540
1541         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1542         reg_write(ohci, OHCI1394_CSRData, lock_data);
1543         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1544         reg_write(ohci, OHCI1394_CSRControl, sel);
1545
1546         for (try = 0; try < 20; try++)
1547                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1548                         lock_old = cpu_to_be32(reg_read(ohci,
1549                                                         OHCI1394_CSRData));
1550                         fw_fill_response(&response, packet->header,
1551                                          RCODE_COMPLETE,
1552                                          &lock_old, sizeof(lock_old));
1553                         goto out;
1554                 }
1555
1556         dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
1557         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1558
1559  out:
1560         fw_core_handle_response(&ohci->card, &response);
1561 }
1562
1563 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1564 {
1565         u64 offset, csr;
1566
1567         if (ctx == &ctx->ohci->at_request_ctx) {
1568                 packet->ack = ACK_PENDING;
1569                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1570         }
1571
1572         offset =
1573                 ((unsigned long long)
1574                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1575                 packet->header[2];
1576         csr = offset - CSR_REGISTER_BASE;
1577
1578         /* Handle config rom reads. */
1579         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1580                 handle_local_rom(ctx->ohci, packet, csr);
1581         else switch (csr) {
1582         case CSR_BUS_MANAGER_ID:
1583         case CSR_BANDWIDTH_AVAILABLE:
1584         case CSR_CHANNELS_AVAILABLE_HI:
1585         case CSR_CHANNELS_AVAILABLE_LO:
1586                 handle_local_lock(ctx->ohci, packet, csr);
1587                 break;
1588         default:
1589                 if (ctx == &ctx->ohci->at_request_ctx)
1590                         fw_core_handle_request(&ctx->ohci->card, packet);
1591                 else
1592                         fw_core_handle_response(&ctx->ohci->card, packet);
1593                 break;
1594         }
1595
1596         if (ctx == &ctx->ohci->at_response_ctx) {
1597                 packet->ack = ACK_COMPLETE;
1598                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1599         }
1600 }
1601
1602 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1603 {
1604         unsigned long flags;
1605         int ret;
1606
1607         spin_lock_irqsave(&ctx->ohci->lock, flags);
1608
1609         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1610             ctx->ohci->generation == packet->generation) {
1611                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1612                 handle_local_request(ctx, packet);
1613                 return;
1614         }
1615
1616         ret = at_context_queue_packet(ctx, packet);
1617         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1618
1619         if (ret < 0)
1620                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1621
1622 }
1623
1624 static void detect_dead_context(struct fw_ohci *ohci,
1625                                 const char *name, unsigned int regs)
1626 {
1627         u32 ctl;
1628
1629         ctl = reg_read(ohci, CONTROL_SET(regs));
1630         if (ctl & CONTEXT_DEAD)
1631                 dev_err(ohci->card.device,
1632                         "DMA context %s has stopped, error code: %s\n",
1633                         name, evts[ctl & 0x1f]);
1634 }
1635
1636 static void handle_dead_contexts(struct fw_ohci *ohci)
1637 {
1638         unsigned int i;
1639         char name[8];
1640
1641         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1642         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1643         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1644         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1645         for (i = 0; i < 32; ++i) {
1646                 if (!(ohci->it_context_support & (1 << i)))
1647                         continue;
1648                 sprintf(name, "IT%u", i);
1649                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1650         }
1651         for (i = 0; i < 32; ++i) {
1652                 if (!(ohci->ir_context_support & (1 << i)))
1653                         continue;
1654                 sprintf(name, "IR%u", i);
1655                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1656         }
1657         /* TODO: maybe try to flush and restart the dead contexts */
1658 }
1659
1660 static u32 cycle_timer_ticks(u32 cycle_timer)
1661 {
1662         u32 ticks;
1663
1664         ticks = cycle_timer & 0xfff;
1665         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1666         ticks += (3072 * 8000) * (cycle_timer >> 25);
1667
1668         return ticks;
1669 }
1670
1671 /*
1672  * Some controllers exhibit one or more of the following bugs when updating the
1673  * iso cycle timer register:
1674  *  - When the lowest six bits are wrapping around to zero, a read that happens
1675  *    at the same time will return garbage in the lowest ten bits.
1676  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1677  *    not incremented for about 60 ns.
1678  *  - Occasionally, the entire register reads zero.
1679  *
1680  * To catch these, we read the register three times and ensure that the
1681  * difference between each two consecutive reads is approximately the same, i.e.
1682  * less than twice the other.  Furthermore, any negative difference indicates an
1683  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1684  * execute, so we have enough precision to compute the ratio of the differences.)
1685  */
1686 static u32 get_cycle_time(struct fw_ohci *ohci)
1687 {
1688         u32 c0, c1, c2;
1689         u32 t0, t1, t2;
1690         s32 diff01, diff12;
1691         int i;
1692
1693         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1694
1695         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1696                 i = 0;
1697                 c1 = c2;
1698                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1699                 do {
1700                         c0 = c1;
1701                         c1 = c2;
1702                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1703                         t0 = cycle_timer_ticks(c0);
1704                         t1 = cycle_timer_ticks(c1);
1705                         t2 = cycle_timer_ticks(c2);
1706                         diff01 = t1 - t0;
1707                         diff12 = t2 - t1;
1708                 } while ((diff01 <= 0 || diff12 <= 0 ||
1709                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1710                          && i++ < 20);
1711         }
1712
1713         return c2;
1714 }
1715
1716 /*
1717  * This function has to be called at least every 64 seconds.  The bus_time
1718  * field stores not only the upper 25 bits of the BUS_TIME register but also
1719  * the most significant bit of the cycle timer in bit 6 so that we can detect
1720  * changes in this bit.
1721  */
1722 static u32 update_bus_time(struct fw_ohci *ohci)
1723 {
1724         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1725
1726         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1727                 ohci->bus_time += 0x40;
1728
1729         return ohci->bus_time | cycle_time_seconds;
1730 }
1731
1732 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1733 {
1734         int reg;
1735
1736         mutex_lock(&ohci->phy_reg_mutex);
1737         reg = write_phy_reg(ohci, 7, port_index);
1738         if (reg >= 0)
1739                 reg = read_phy_reg(ohci, 8);
1740         mutex_unlock(&ohci->phy_reg_mutex);
1741         if (reg < 0)
1742                 return reg;
1743
1744         switch (reg & 0x0f) {
1745         case 0x06:
1746                 return 2;       /* is child node (connected to parent node) */
1747         case 0x0e:
1748                 return 3;       /* is parent node (connected to child node) */
1749         }
1750         return 1;               /* not connected */
1751 }
1752
1753 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1754         int self_id_count)
1755 {
1756         int i;
1757         u32 entry;
1758
1759         for (i = 0; i < self_id_count; i++) {
1760                 entry = ohci->self_id_buffer[i];
1761                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1762                         return -1;
1763                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1764                         return i;
1765         }
1766         return i;
1767 }
1768
1769 /*
1770  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1771  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1772  * Construct the selfID from phy register contents.
1773  * FIXME:  How to determine the selfID.i flag?
1774  */
1775 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1776 {
1777         int reg, i, pos, status;
1778         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1779         u32 self_id = 0x8040c800;
1780
1781         reg = reg_read(ohci, OHCI1394_NodeID);
1782         if (!(reg & OHCI1394_NodeID_idValid)) {
1783                 dev_notice(ohci->card.device,
1784                            "node ID not valid, new bus reset in progress\n");
1785                 return -EBUSY;
1786         }
1787         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1788
1789         reg = ohci_read_phy_reg(&ohci->card, 4);
1790         if (reg < 0)
1791                 return reg;
1792         self_id |= ((reg & 0x07) << 8); /* power class */
1793
1794         reg = ohci_read_phy_reg(&ohci->card, 1);
1795         if (reg < 0)
1796                 return reg;
1797         self_id |= ((reg & 0x3f) << 16); /* gap count */
1798
1799         for (i = 0; i < 3; i++) {
1800                 status = get_status_for_port(ohci, i);
1801                 if (status < 0)
1802                         return status;
1803                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1804         }
1805
1806         pos = get_self_id_pos(ohci, self_id, self_id_count);
1807         if (pos >= 0) {
1808                 memmove(&(ohci->self_id_buffer[pos+1]),
1809                         &(ohci->self_id_buffer[pos]),
1810                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1811                 ohci->self_id_buffer[pos] = self_id;
1812                 self_id_count++;
1813         }
1814         return self_id_count;
1815 }
1816
1817 static void bus_reset_work(struct work_struct *work)
1818 {
1819         struct fw_ohci *ohci =
1820                 container_of(work, struct fw_ohci, bus_reset_work);
1821         int self_id_count, i, j, reg;
1822         int generation, new_generation;
1823         unsigned long flags;
1824         void *free_rom = NULL;
1825         dma_addr_t free_rom_bus = 0;
1826         bool is_new_root;
1827
1828         reg = reg_read(ohci, OHCI1394_NodeID);
1829         if (!(reg & OHCI1394_NodeID_idValid)) {
1830                 dev_notice(ohci->card.device,
1831                            "node ID not valid, new bus reset in progress\n");
1832                 return;
1833         }
1834         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1835                 dev_notice(ohci->card.device, "malconfigured bus\n");
1836                 return;
1837         }
1838         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1839                                OHCI1394_NodeID_nodeNumber);
1840
1841         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1842         if (!(ohci->is_root && is_new_root))
1843                 reg_write(ohci, OHCI1394_LinkControlSet,
1844                           OHCI1394_LinkControl_cycleMaster);
1845         ohci->is_root = is_new_root;
1846
1847         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1848         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1849                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1850                 return;
1851         }
1852         /*
1853          * The count in the SelfIDCount register is the number of
1854          * bytes in the self ID receive buffer.  Since we also receive
1855          * the inverted quadlets and a header quadlet, we shift one
1856          * bit extra to get the actual number of self IDs.
1857          */
1858         self_id_count = (reg >> 3) & 0xff;
1859
1860         if (self_id_count > 252) {
1861                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1862                 return;
1863         }
1864
1865         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1866         rmb();
1867
1868         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1869                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1870                         /*
1871                          * If the invalid data looks like a cycle start packet,
1872                          * it's likely to be the result of the cycle master
1873                          * having a wrong gap count.  In this case, the self IDs
1874                          * so far are valid and should be processed so that the
1875                          * bus manager can then correct the gap count.
1876                          */
1877                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1878                                                         == 0xffff008f) {
1879                                 dev_notice(ohci->card.device,
1880                                            "ignoring spurious self IDs\n");
1881                                 self_id_count = j;
1882                                 break;
1883                         } else {
1884                                 dev_notice(ohci->card.device,
1885                                            "inconsistent self IDs\n");
1886                                 return;
1887                         }
1888                 }
1889                 ohci->self_id_buffer[j] =
1890                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1891         }
1892
1893         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1894                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1895                 if (self_id_count < 0) {
1896                         dev_notice(ohci->card.device,
1897                                    "could not construct local self ID\n");
1898                         return;
1899                 }
1900         }
1901
1902         if (self_id_count == 0) {
1903                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1904                 return;
1905         }
1906         rmb();
1907
1908         /*
1909          * Check the consistency of the self IDs we just read.  The
1910          * problem we face is that a new bus reset can start while we
1911          * read out the self IDs from the DMA buffer. If this happens,
1912          * the DMA buffer will be overwritten with new self IDs and we
1913          * will read out inconsistent data.  The OHCI specification
1914          * (section 11.2) recommends a technique similar to
1915          * linux/seqlock.h, where we remember the generation of the
1916          * self IDs in the buffer before reading them out and compare
1917          * it to the current generation after reading them out.  If
1918          * the two generations match we know we have a consistent set
1919          * of self IDs.
1920          */
1921
1922         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1923         if (new_generation != generation) {
1924                 dev_notice(ohci->card.device,
1925                            "new bus reset, discarding self ids\n");
1926                 return;
1927         }
1928
1929         /* FIXME: Document how the locking works. */
1930         spin_lock_irqsave(&ohci->lock, flags);
1931
1932         ohci->generation = -1; /* prevent AT packet queueing */
1933         context_stop(&ohci->at_request_ctx);
1934         context_stop(&ohci->at_response_ctx);
1935
1936         spin_unlock_irqrestore(&ohci->lock, flags);
1937
1938         /*
1939          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1940          * packets in the AT queues and software needs to drain them.
1941          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1942          */
1943         at_context_flush(&ohci->at_request_ctx);
1944         at_context_flush(&ohci->at_response_ctx);
1945
1946         spin_lock_irqsave(&ohci->lock, flags);
1947
1948         ohci->generation = generation;
1949         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1950
1951         if (ohci->quirks & QUIRK_RESET_PACKET)
1952                 ohci->request_generation = generation;
1953
1954         /*
1955          * This next bit is unrelated to the AT context stuff but we
1956          * have to do it under the spinlock also.  If a new config rom
1957          * was set up before this reset, the old one is now no longer
1958          * in use and we can free it. Update the config rom pointers
1959          * to point to the current config rom and clear the
1960          * next_config_rom pointer so a new update can take place.
1961          */
1962
1963         if (ohci->next_config_rom != NULL) {
1964                 if (ohci->next_config_rom != ohci->config_rom) {
1965                         free_rom      = ohci->config_rom;
1966                         free_rom_bus  = ohci->config_rom_bus;
1967                 }
1968                 ohci->config_rom      = ohci->next_config_rom;
1969                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1970                 ohci->next_config_rom = NULL;
1971
1972                 /*
1973                  * Restore config_rom image and manually update
1974                  * config_rom registers.  Writing the header quadlet
1975                  * will indicate that the config rom is ready, so we
1976                  * do that last.
1977                  */
1978                 reg_write(ohci, OHCI1394_BusOptions,
1979                           be32_to_cpu(ohci->config_rom[2]));
1980                 ohci->config_rom[0] = ohci->next_header;
1981                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1982                           be32_to_cpu(ohci->next_header));
1983         }
1984
1985 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1986         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1987         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1988 #endif
1989
1990         spin_unlock_irqrestore(&ohci->lock, flags);
1991
1992         if (free_rom)
1993                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1994                                   free_rom, free_rom_bus);
1995
1996         log_selfids(ohci, generation, self_id_count);
1997
1998         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1999                                  self_id_count, ohci->self_id_buffer,
2000                                  ohci->csr_state_setclear_abdicate);
2001         ohci->csr_state_setclear_abdicate = false;
2002 }
2003
2004 static irqreturn_t irq_handler(int irq, void *data)
2005 {
2006         struct fw_ohci *ohci = data;
2007         u32 event, iso_event;
2008         int i;
2009
2010         event = reg_read(ohci, OHCI1394_IntEventClear);
2011
2012         if (!event || !~event)
2013                 return IRQ_NONE;
2014
2015         /*
2016          * busReset and postedWriteErr must not be cleared yet
2017          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2018          */
2019         reg_write(ohci, OHCI1394_IntEventClear,
2020                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2021         log_irqs(ohci, event);
2022
2023         if (event & OHCI1394_selfIDComplete)
2024                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2025
2026         if (event & OHCI1394_RQPkt)
2027                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2028
2029         if (event & OHCI1394_RSPkt)
2030                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2031
2032         if (event & OHCI1394_reqTxComplete)
2033                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2034
2035         if (event & OHCI1394_respTxComplete)
2036                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2037
2038         if (event & OHCI1394_isochRx) {
2039                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2040                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2041
2042                 while (iso_event) {
2043                         i = ffs(iso_event) - 1;
2044                         tasklet_schedule(
2045                                 &ohci->ir_context_list[i].context.tasklet);
2046                         iso_event &= ~(1 << i);
2047                 }
2048         }
2049
2050         if (event & OHCI1394_isochTx) {
2051                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2052                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2053
2054                 while (iso_event) {
2055                         i = ffs(iso_event) - 1;
2056                         tasklet_schedule(
2057                                 &ohci->it_context_list[i].context.tasklet);
2058                         iso_event &= ~(1 << i);
2059                 }
2060         }
2061
2062         if (unlikely(event & OHCI1394_regAccessFail))
2063                 dev_err(ohci->card.device, "register access failure\n");
2064
2065         if (unlikely(event & OHCI1394_postedWriteErr)) {
2066                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2067                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2068                 reg_write(ohci, OHCI1394_IntEventClear,
2069                           OHCI1394_postedWriteErr);
2070                 if (printk_ratelimit())
2071                         dev_err(ohci->card.device, "PCI posted write error\n");
2072         }
2073
2074         if (unlikely(event & OHCI1394_cycleTooLong)) {
2075                 if (printk_ratelimit())
2076                         dev_notice(ohci->card.device,
2077                                    "isochronous cycle too long\n");
2078                 reg_write(ohci, OHCI1394_LinkControlSet,
2079                           OHCI1394_LinkControl_cycleMaster);
2080         }
2081
2082         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2083                 /*
2084                  * We need to clear this event bit in order to make
2085                  * cycleMatch isochronous I/O work.  In theory we should
2086                  * stop active cycleMatch iso contexts now and restart
2087                  * them at least two cycles later.  (FIXME?)
2088                  */
2089                 if (printk_ratelimit())
2090                         dev_notice(ohci->card.device,
2091                                    "isochronous cycle inconsistent\n");
2092         }
2093
2094         if (unlikely(event & OHCI1394_unrecoverableError))
2095                 handle_dead_contexts(ohci);
2096
2097         if (event & OHCI1394_cycle64Seconds) {
2098                 spin_lock(&ohci->lock);
2099                 update_bus_time(ohci);
2100                 spin_unlock(&ohci->lock);
2101         } else
2102                 flush_writes(ohci);
2103
2104         return IRQ_HANDLED;
2105 }
2106
2107 static int software_reset(struct fw_ohci *ohci)
2108 {
2109         u32 val;
2110         int i;
2111
2112         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2113         for (i = 0; i < 500; i++) {
2114                 val = reg_read(ohci, OHCI1394_HCControlSet);
2115                 if (!~val)
2116                         return -ENODEV; /* Card was ejected. */
2117
2118                 if (!(val & OHCI1394_HCControl_softReset))
2119                         return 0;
2120
2121                 msleep(1);
2122         }
2123
2124         return -EBUSY;
2125 }
2126
2127 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2128 {
2129         size_t size = length * 4;
2130
2131         memcpy(dest, src, size);
2132         if (size < CONFIG_ROM_SIZE)
2133                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2134 }
2135
2136 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2137 {
2138         bool enable_1394a;
2139         int ret, clear, set, offset;
2140
2141         /* Check if the driver should configure link and PHY. */
2142         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2143               OHCI1394_HCControl_programPhyEnable))
2144                 return 0;
2145
2146         /* Paranoia: check whether the PHY supports 1394a, too. */
2147         enable_1394a = false;
2148         ret = read_phy_reg(ohci, 2);
2149         if (ret < 0)
2150                 return ret;
2151         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2152                 ret = read_paged_phy_reg(ohci, 1, 8);
2153                 if (ret < 0)
2154                         return ret;
2155                 if (ret >= 1)
2156                         enable_1394a = true;
2157         }
2158
2159         if (ohci->quirks & QUIRK_NO_1394A)
2160                 enable_1394a = false;
2161
2162         /* Configure PHY and link consistently. */
2163         if (enable_1394a) {
2164                 clear = 0;
2165                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2166         } else {
2167                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2168                 set = 0;
2169         }
2170         ret = update_phy_reg(ohci, 5, clear, set);
2171         if (ret < 0)
2172                 return ret;
2173
2174         if (enable_1394a)
2175                 offset = OHCI1394_HCControlSet;
2176         else
2177                 offset = OHCI1394_HCControlClear;
2178         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2179
2180         /* Clean up: configuration has been taken care of. */
2181         reg_write(ohci, OHCI1394_HCControlClear,
2182                   OHCI1394_HCControl_programPhyEnable);
2183
2184         return 0;
2185 }
2186
2187 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2188 {
2189         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2190         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2191         int reg, i;
2192
2193         reg = read_phy_reg(ohci, 2);
2194         if (reg < 0)
2195                 return reg;
2196         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2197                 return 0;
2198
2199         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2200                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2201                 if (reg < 0)
2202                         return reg;
2203                 if (reg != id[i])
2204                         return 0;
2205         }
2206         return 1;
2207 }
2208
2209 static int ohci_enable(struct fw_card *card,
2210                        const __be32 *config_rom, size_t length)
2211 {
2212         struct fw_ohci *ohci = fw_ohci(card);
2213         struct pci_dev *dev = to_pci_dev(card->device);
2214         u32 lps, seconds, version, irqs;
2215         int i, ret;
2216
2217         if (software_reset(ohci)) {
2218                 dev_err(card->device, "failed to reset ohci card\n");
2219                 return -EBUSY;
2220         }
2221
2222         /*
2223          * Now enable LPS, which we need in order to start accessing
2224          * most of the registers.  In fact, on some cards (ALI M5251),
2225          * accessing registers in the SClk domain without LPS enabled
2226          * will lock up the machine.  Wait 50msec to make sure we have
2227          * full link enabled.  However, with some cards (well, at least
2228          * a JMicron PCIe card), we have to try again sometimes.
2229          */
2230         reg_write(ohci, OHCI1394_HCControlSet,
2231                   OHCI1394_HCControl_LPS |
2232                   OHCI1394_HCControl_postedWriteEnable);
2233         flush_writes(ohci);
2234
2235         for (lps = 0, i = 0; !lps && i < 3; i++) {
2236                 msleep(50);
2237                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2238                       OHCI1394_HCControl_LPS;
2239         }
2240
2241         if (!lps) {
2242                 dev_err(card->device, "failed to set Link Power Status\n");
2243                 return -EIO;
2244         }
2245
2246         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2247                 ret = probe_tsb41ba3d(ohci);
2248                 if (ret < 0)
2249                         return ret;
2250                 if (ret)
2251                         dev_notice(card->device, "local TSB41BA3D phy\n");
2252                 else
2253                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2254         }
2255
2256         reg_write(ohci, OHCI1394_HCControlClear,
2257                   OHCI1394_HCControl_noByteSwapData);
2258
2259         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2260         reg_write(ohci, OHCI1394_LinkControlSet,
2261                   OHCI1394_LinkControl_cycleTimerEnable |
2262                   OHCI1394_LinkControl_cycleMaster);
2263
2264         reg_write(ohci, OHCI1394_ATRetries,
2265                   OHCI1394_MAX_AT_REQ_RETRIES |
2266                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2267                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2268                   (200 << 16));
2269
2270         seconds = lower_32_bits(get_seconds());
2271         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2272         ohci->bus_time = seconds & ~0x3f;
2273
2274         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2275         if (version >= OHCI_VERSION_1_1) {
2276                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2277                           0xfffffffe);
2278                 card->broadcast_channel_auto_allocated = true;
2279         }
2280
2281         /* Get implemented bits of the priority arbitration request counter. */
2282         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2283         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2284         reg_write(ohci, OHCI1394_FairnessControl, 0);
2285         card->priority_budget_implemented = ohci->pri_req_max != 0;
2286
2287         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2288         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2289         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2290
2291         ret = configure_1394a_enhancements(ohci);
2292         if (ret < 0)
2293                 return ret;
2294
2295         /* Activate link_on bit and contender bit in our self ID packets.*/
2296         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2297         if (ret < 0)
2298                 return ret;
2299
2300         /*
2301          * When the link is not yet enabled, the atomic config rom
2302          * update mechanism described below in ohci_set_config_rom()
2303          * is not active.  We have to update ConfigRomHeader and
2304          * BusOptions manually, and the write to ConfigROMmap takes
2305          * effect immediately.  We tie this to the enabling of the
2306          * link, so we have a valid config rom before enabling - the
2307          * OHCI requires that ConfigROMhdr and BusOptions have valid
2308          * values before enabling.
2309          *
2310          * However, when the ConfigROMmap is written, some controllers
2311          * always read back quadlets 0 and 2 from the config rom to
2312          * the ConfigRomHeader and BusOptions registers on bus reset.
2313          * They shouldn't do that in this initial case where the link
2314          * isn't enabled.  This means we have to use the same
2315          * workaround here, setting the bus header to 0 and then write
2316          * the right values in the bus reset tasklet.
2317          */
2318
2319         if (config_rom) {
2320                 ohci->next_config_rom =
2321                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2322                                            &ohci->next_config_rom_bus,
2323                                            GFP_KERNEL);
2324                 if (ohci->next_config_rom == NULL)
2325                         return -ENOMEM;
2326
2327                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2328         } else {
2329                 /*
2330                  * In the suspend case, config_rom is NULL, which
2331                  * means that we just reuse the old config rom.
2332                  */
2333                 ohci->next_config_rom = ohci->config_rom;
2334                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2335         }
2336
2337         ohci->next_header = ohci->next_config_rom[0];
2338         ohci->next_config_rom[0] = 0;
2339         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2340         reg_write(ohci, OHCI1394_BusOptions,
2341                   be32_to_cpu(ohci->next_config_rom[2]));
2342         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2343
2344         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2345
2346         if (!(ohci->quirks & QUIRK_NO_MSI))
2347                 pci_enable_msi(dev);
2348         if (request_irq(dev->irq, irq_handler,
2349                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2350                         ohci_driver_name, ohci)) {
2351                 dev_err(card->device, "failed to allocate interrupt %d\n",
2352                         dev->irq);
2353                 pci_disable_msi(dev);
2354
2355                 if (config_rom) {
2356                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2357                                           ohci->next_config_rom,
2358                                           ohci->next_config_rom_bus);
2359                         ohci->next_config_rom = NULL;
2360                 }
2361                 return -EIO;
2362         }
2363
2364         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2365                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2366                 OHCI1394_isochTx | OHCI1394_isochRx |
2367                 OHCI1394_postedWriteErr |
2368                 OHCI1394_selfIDComplete |
2369                 OHCI1394_regAccessFail |
2370                 OHCI1394_cycle64Seconds |
2371                 OHCI1394_cycleInconsistent |
2372                 OHCI1394_unrecoverableError |
2373                 OHCI1394_cycleTooLong |
2374                 OHCI1394_masterIntEnable;
2375         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2376                 irqs |= OHCI1394_busReset;
2377         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2378
2379         reg_write(ohci, OHCI1394_HCControlSet,
2380                   OHCI1394_HCControl_linkEnable |
2381                   OHCI1394_HCControl_BIBimageValid);
2382
2383         reg_write(ohci, OHCI1394_LinkControlSet,
2384                   OHCI1394_LinkControl_rcvSelfID |
2385                   OHCI1394_LinkControl_rcvPhyPkt);
2386
2387         ar_context_run(&ohci->ar_request_ctx);
2388         ar_context_run(&ohci->ar_response_ctx);
2389
2390         flush_writes(ohci);
2391
2392         /* We are ready to go, reset bus to finish initialization. */
2393         fw_schedule_bus_reset(&ohci->card, false, true);
2394
2395         return 0;
2396 }
2397
2398 static int ohci_set_config_rom(struct fw_card *card,
2399                                const __be32 *config_rom, size_t length)
2400 {
2401         struct fw_ohci *ohci;
2402         unsigned long flags;
2403         __be32 *next_config_rom;
2404         dma_addr_t uninitialized_var(next_config_rom_bus);
2405
2406         ohci = fw_ohci(card);
2407
2408         /*
2409          * When the OHCI controller is enabled, the config rom update
2410          * mechanism is a bit tricky, but easy enough to use.  See
2411          * section 5.5.6 in the OHCI specification.
2412          *
2413          * The OHCI controller caches the new config rom address in a
2414          * shadow register (ConfigROMmapNext) and needs a bus reset
2415          * for the changes to take place.  When the bus reset is
2416          * detected, the controller loads the new values for the
2417          * ConfigRomHeader and BusOptions registers from the specified
2418          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2419          * shadow register. All automatically and atomically.
2420          *
2421          * Now, there's a twist to this story.  The automatic load of
2422          * ConfigRomHeader and BusOptions doesn't honor the
2423          * noByteSwapData bit, so with a be32 config rom, the
2424          * controller will load be32 values in to these registers
2425          * during the atomic update, even on litte endian
2426          * architectures.  The workaround we use is to put a 0 in the
2427          * header quadlet; 0 is endian agnostic and means that the
2428          * config rom isn't ready yet.  In the bus reset tasklet we
2429          * then set up the real values for the two registers.
2430          *
2431          * We use ohci->lock to avoid racing with the code that sets
2432          * ohci->next_config_rom to NULL (see bus_reset_work).
2433          */
2434
2435         next_config_rom =
2436                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2437                                    &next_config_rom_bus, GFP_KERNEL);
2438         if (next_config_rom == NULL)
2439                 return -ENOMEM;
2440
2441         spin_lock_irqsave(&ohci->lock, flags);
2442
2443         /*
2444          * If there is not an already pending config_rom update,
2445          * push our new allocation into the ohci->next_config_rom
2446          * and then mark the local variable as null so that we
2447          * won't deallocate the new buffer.
2448          *
2449          * OTOH, if there is a pending config_rom update, just
2450          * use that buffer with the new config_rom data, and
2451          * let this routine free the unused DMA allocation.
2452          */
2453
2454         if (ohci->next_config_rom == NULL) {
2455                 ohci->next_config_rom = next_config_rom;
2456                 ohci->next_config_rom_bus = next_config_rom_bus;
2457                 next_config_rom = NULL;
2458         }
2459
2460         copy_config_rom(ohci->next_config_rom, config_rom, length);
2461
2462         ohci->next_header = config_rom[0];
2463         ohci->next_config_rom[0] = 0;
2464
2465         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2466
2467         spin_unlock_irqrestore(&ohci->lock, flags);
2468
2469         /* If we didn't use the DMA allocation, delete it. */
2470         if (next_config_rom != NULL)
2471                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2472                                   next_config_rom, next_config_rom_bus);
2473
2474         /*
2475          * Now initiate a bus reset to have the changes take
2476          * effect. We clean up the old config rom memory and DMA
2477          * mappings in the bus reset tasklet, since the OHCI
2478          * controller could need to access it before the bus reset
2479          * takes effect.
2480          */
2481
2482         fw_schedule_bus_reset(&ohci->card, true, true);
2483
2484         return 0;
2485 }
2486
2487 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2488 {
2489         struct fw_ohci *ohci = fw_ohci(card);
2490
2491         at_context_transmit(&ohci->at_request_ctx, packet);
2492 }
2493
2494 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2495 {
2496         struct fw_ohci *ohci = fw_ohci(card);
2497
2498         at_context_transmit(&ohci->at_response_ctx, packet);
2499 }
2500
2501 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2502 {
2503         struct fw_ohci *ohci = fw_ohci(card);
2504         struct context *ctx = &ohci->at_request_ctx;
2505         struct driver_data *driver_data = packet->driver_data;
2506         int ret = -ENOENT;
2507
2508         tasklet_disable(&ctx->tasklet);
2509
2510         if (packet->ack != 0)
2511                 goto out;
2512
2513         if (packet->payload_mapped)
2514                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2515                                  packet->payload_length, DMA_TO_DEVICE);
2516
2517         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2518         driver_data->packet = NULL;
2519         packet->ack = RCODE_CANCELLED;
2520         packet->callback(packet, &ohci->card, packet->ack);
2521         ret = 0;
2522  out:
2523         tasklet_enable(&ctx->tasklet);
2524
2525         return ret;
2526 }
2527
2528 static int ohci_enable_phys_dma(struct fw_card *card,
2529                                 int node_id, int generation)
2530 {
2531 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2532         return 0;
2533 #else
2534         struct fw_ohci *ohci = fw_ohci(card);
2535         unsigned long flags;
2536         int n, ret = 0;
2537
2538         /*
2539          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2540          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2541          */
2542
2543         spin_lock_irqsave(&ohci->lock, flags);
2544
2545         if (ohci->generation != generation) {
2546                 ret = -ESTALE;
2547                 goto out;
2548         }
2549
2550         /*
2551          * Note, if the node ID contains a non-local bus ID, physical DMA is
2552          * enabled for _all_ nodes on remote buses.
2553          */
2554
2555         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2556         if (n < 32)
2557                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2558         else
2559                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2560
2561         flush_writes(ohci);
2562  out:
2563         spin_unlock_irqrestore(&ohci->lock, flags);
2564
2565         return ret;
2566 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2567 }
2568
2569 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2570 {
2571         struct fw_ohci *ohci = fw_ohci(card);
2572         unsigned long flags;
2573         u32 value;
2574
2575         switch (csr_offset) {
2576         case CSR_STATE_CLEAR:
2577         case CSR_STATE_SET:
2578                 if (ohci->is_root &&
2579                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2580                      OHCI1394_LinkControl_cycleMaster))
2581                         value = CSR_STATE_BIT_CMSTR;
2582                 else
2583                         value = 0;
2584                 if (ohci->csr_state_setclear_abdicate)
2585                         value |= CSR_STATE_BIT_ABDICATE;
2586
2587                 return value;
2588
2589         case CSR_NODE_IDS:
2590                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2591
2592         case CSR_CYCLE_TIME:
2593                 return get_cycle_time(ohci);
2594
2595         case CSR_BUS_TIME:
2596                 /*
2597                  * We might be called just after the cycle timer has wrapped
2598                  * around but just before the cycle64Seconds handler, so we
2599                  * better check here, too, if the bus time needs to be updated.
2600                  */
2601                 spin_lock_irqsave(&ohci->lock, flags);
2602                 value = update_bus_time(ohci);
2603                 spin_unlock_irqrestore(&ohci->lock, flags);
2604                 return value;
2605
2606         case CSR_BUSY_TIMEOUT:
2607                 value = reg_read(ohci, OHCI1394_ATRetries);
2608                 return (value >> 4) & 0x0ffff00f;
2609
2610         case CSR_PRIORITY_BUDGET:
2611                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2612                         (ohci->pri_req_max << 8);
2613
2614         default:
2615                 WARN_ON(1);
2616                 return 0;
2617         }
2618 }
2619
2620 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2621 {
2622         struct fw_ohci *ohci = fw_ohci(card);
2623         unsigned long flags;
2624
2625         switch (csr_offset) {
2626         case CSR_STATE_CLEAR:
2627                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2628                         reg_write(ohci, OHCI1394_LinkControlClear,
2629                                   OHCI1394_LinkControl_cycleMaster);
2630                         flush_writes(ohci);
2631                 }
2632                 if (value & CSR_STATE_BIT_ABDICATE)
2633                         ohci->csr_state_setclear_abdicate = false;
2634                 break;
2635
2636         case CSR_STATE_SET:
2637                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2638                         reg_write(ohci, OHCI1394_LinkControlSet,
2639                                   OHCI1394_LinkControl_cycleMaster);
2640                         flush_writes(ohci);
2641                 }
2642                 if (value & CSR_STATE_BIT_ABDICATE)
2643                         ohci->csr_state_setclear_abdicate = true;
2644                 break;
2645
2646         case CSR_NODE_IDS:
2647                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2648                 flush_writes(ohci);
2649                 break;
2650
2651         case CSR_CYCLE_TIME:
2652                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2653                 reg_write(ohci, OHCI1394_IntEventSet,
2654                           OHCI1394_cycleInconsistent);
2655                 flush_writes(ohci);
2656                 break;
2657
2658         case CSR_BUS_TIME:
2659                 spin_lock_irqsave(&ohci->lock, flags);
2660                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2661                 spin_unlock_irqrestore(&ohci->lock, flags);
2662                 break;
2663
2664         case CSR_BUSY_TIMEOUT:
2665                 value = (value & 0xf) | ((value & 0xf) << 4) |
2666                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2667                 reg_write(ohci, OHCI1394_ATRetries, value);
2668                 flush_writes(ohci);
2669                 break;
2670
2671         case CSR_PRIORITY_BUDGET:
2672                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2673                 flush_writes(ohci);
2674                 break;
2675
2676         default:
2677                 WARN_ON(1);
2678                 break;
2679         }
2680 }
2681
2682 static void flush_iso_completions(struct iso_context *ctx)
2683 {
2684         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2685                               ctx->header_length, ctx->header,
2686                               ctx->base.callback_data);
2687         ctx->header_length = 0;
2688 }
2689
2690 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2691 {
2692         u32 *ctx_hdr;
2693
2694         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
2695                 flush_iso_completions(ctx);
2696
2697         ctx_hdr = ctx->header + ctx->header_length;
2698         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2699
2700         /*
2701          * The two iso header quadlets are byteswapped to little
2702          * endian by the controller, but we want to present them
2703          * as big endian for consistency with the bus endianness.
2704          */
2705         if (ctx->base.header_size > 0)
2706                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2707         if (ctx->base.header_size > 4)
2708                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2709         if (ctx->base.header_size > 8)
2710                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2711         ctx->header_length += ctx->base.header_size;
2712 }
2713
2714 static int handle_ir_packet_per_buffer(struct context *context,
2715                                        struct descriptor *d,
2716                                        struct descriptor *last)
2717 {
2718         struct iso_context *ctx =
2719                 container_of(context, struct iso_context, context);
2720         struct descriptor *pd;
2721         u32 buffer_dma;
2722
2723         for (pd = d; pd <= last; pd++)
2724                 if (pd->transfer_status)
2725                         break;
2726         if (pd > last)
2727                 /* Descriptor(s) not done yet, stop iteration */
2728                 return 0;
2729
2730         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2731                 d++;
2732                 buffer_dma = le32_to_cpu(d->data_address);
2733                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2734                                               buffer_dma & PAGE_MASK,
2735                                               buffer_dma & ~PAGE_MASK,
2736                                               le16_to_cpu(d->req_count),
2737                                               DMA_FROM_DEVICE);
2738         }
2739
2740         copy_iso_headers(ctx, (u32 *) (last + 1));
2741
2742         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2743                 flush_iso_completions(ctx);
2744
2745         return 1;
2746 }
2747
2748 /* d == last because each descriptor block is only a single descriptor. */
2749 static int handle_ir_buffer_fill(struct context *context,
2750                                  struct descriptor *d,
2751                                  struct descriptor *last)
2752 {
2753         struct iso_context *ctx =
2754                 container_of(context, struct iso_context, context);
2755         unsigned int req_count, res_count, completed;
2756         u32 buffer_dma;
2757
2758         req_count = le16_to_cpu(last->req_count);
2759         res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2760         completed = req_count - res_count;
2761         buffer_dma = le32_to_cpu(last->data_address);
2762
2763         if (completed > 0) {
2764                 ctx->mc_buffer_bus = buffer_dma;
2765                 ctx->mc_completed = completed;
2766         }
2767
2768         if (res_count != 0)
2769                 /* Descriptor(s) not done yet, stop iteration */
2770                 return 0;
2771
2772         dma_sync_single_range_for_cpu(context->ohci->card.device,
2773                                       buffer_dma & PAGE_MASK,
2774                                       buffer_dma & ~PAGE_MASK,
2775                                       completed, DMA_FROM_DEVICE);
2776
2777         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2778                 ctx->base.callback.mc(&ctx->base,
2779                                       buffer_dma + completed,
2780                                       ctx->base.callback_data);
2781                 ctx->mc_completed = 0;
2782         }
2783
2784         return 1;
2785 }
2786
2787 static void flush_ir_buffer_fill(struct iso_context *ctx)
2788 {
2789         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2790                                       ctx->mc_buffer_bus & PAGE_MASK,
2791                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2792                                       ctx->mc_completed, DMA_FROM_DEVICE);
2793
2794         ctx->base.callback.mc(&ctx->base,
2795                               ctx->mc_buffer_bus + ctx->mc_completed,
2796                               ctx->base.callback_data);
2797         ctx->mc_completed = 0;
2798 }
2799
2800 static inline void sync_it_packet_for_cpu(struct context *context,
2801                                           struct descriptor *pd)
2802 {
2803         __le16 control;
2804         u32 buffer_dma;
2805
2806         /* only packets beginning with OUTPUT_MORE* have data buffers */
2807         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2808                 return;
2809
2810         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2811         pd += 2;
2812
2813         /*
2814          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2815          * data buffer is in the context program's coherent page and must not
2816          * be synced.
2817          */
2818         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2819             (context->current_bus          & PAGE_MASK)) {
2820                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2821                         return;
2822                 pd++;
2823         }
2824
2825         do {
2826                 buffer_dma = le32_to_cpu(pd->data_address);
2827                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2828                                               buffer_dma & PAGE_MASK,
2829                                               buffer_dma & ~PAGE_MASK,
2830                                               le16_to_cpu(pd->req_count),
2831                                               DMA_TO_DEVICE);
2832                 control = pd->control;
2833                 pd++;
2834         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2835 }
2836
2837 static int handle_it_packet(struct context *context,
2838                             struct descriptor *d,
2839                             struct descriptor *last)
2840 {
2841         struct iso_context *ctx =
2842                 container_of(context, struct iso_context, context);
2843         struct descriptor *pd;
2844         __be32 *ctx_hdr;
2845
2846         for (pd = d; pd <= last; pd++)
2847                 if (pd->transfer_status)
2848                         break;
2849         if (pd > last)
2850                 /* Descriptor(s) not done yet, stop iteration */
2851                 return 0;
2852
2853         sync_it_packet_for_cpu(context, d);
2854
2855         if (ctx->header_length + 4 > PAGE_SIZE)
2856                 flush_iso_completions(ctx);
2857
2858         ctx_hdr = ctx->header + ctx->header_length;
2859         ctx->last_timestamp = le16_to_cpu(last->res_count);
2860         /* Present this value as big-endian to match the receive code */
2861         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2862                                le16_to_cpu(pd->res_count));
2863         ctx->header_length += 4;
2864
2865         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2866                 flush_iso_completions(ctx);
2867
2868         return 1;
2869 }
2870
2871 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2872 {
2873         u32 hi = channels >> 32, lo = channels;
2874
2875         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2876         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2877         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2878         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2879         mmiowb();
2880         ohci->mc_channels = channels;
2881 }
2882
2883 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2884                                 int type, int channel, size_t header_size)
2885 {
2886         struct fw_ohci *ohci = fw_ohci(card);
2887         struct iso_context *uninitialized_var(ctx);
2888         descriptor_callback_t uninitialized_var(callback);
2889         u64 *uninitialized_var(channels);
2890         u32 *uninitialized_var(mask), uninitialized_var(regs);
2891         unsigned long flags;
2892         int index, ret = -EBUSY;
2893
2894         spin_lock_irqsave(&ohci->lock, flags);
2895
2896         switch (type) {
2897         case FW_ISO_CONTEXT_TRANSMIT:
2898                 mask     = &ohci->it_context_mask;
2899                 callback = handle_it_packet;
2900                 index    = ffs(*mask) - 1;
2901                 if (index >= 0) {
2902                         *mask &= ~(1 << index);
2903                         regs = OHCI1394_IsoXmitContextBase(index);
2904                         ctx  = &ohci->it_context_list[index];
2905                 }
2906                 break;
2907
2908         case FW_ISO_CONTEXT_RECEIVE:
2909                 channels = &ohci->ir_context_channels;
2910                 mask     = &ohci->ir_context_mask;
2911                 callback = handle_ir_packet_per_buffer;
2912                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2913                 if (index >= 0) {
2914                         *channels &= ~(1ULL << channel);
2915                         *mask     &= ~(1 << index);
2916                         regs = OHCI1394_IsoRcvContextBase(index);
2917                         ctx  = &ohci->ir_context_list[index];
2918                 }
2919                 break;
2920
2921         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2922                 mask     = &ohci->ir_context_mask;
2923                 callback = handle_ir_buffer_fill;
2924                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2925                 if (index >= 0) {
2926                         ohci->mc_allocated = true;
2927                         *mask &= ~(1 << index);
2928                         regs = OHCI1394_IsoRcvContextBase(index);
2929                         ctx  = &ohci->ir_context_list[index];
2930                 }
2931                 break;
2932
2933         default:
2934                 index = -1;
2935                 ret = -ENOSYS;
2936         }
2937
2938         spin_unlock_irqrestore(&ohci->lock, flags);
2939
2940         if (index < 0)
2941                 return ERR_PTR(ret);
2942
2943         memset(ctx, 0, sizeof(*ctx));
2944         ctx->header_length = 0;
2945         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2946         if (ctx->header == NULL) {
2947                 ret = -ENOMEM;
2948                 goto out;
2949         }
2950         ret = context_init(&ctx->context, ohci, regs, callback);
2951         if (ret < 0)
2952                 goto out_with_header;
2953
2954         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
2955                 set_multichannel_mask(ohci, 0);
2956                 ctx->mc_completed = 0;
2957         }
2958
2959         return &ctx->base;
2960
2961  out_with_header:
2962         free_page((unsigned long)ctx->header);
2963  out:
2964         spin_lock_irqsave(&ohci->lock, flags);
2965
2966         switch (type) {
2967         case FW_ISO_CONTEXT_RECEIVE:
2968                 *channels |= 1ULL << channel;
2969                 break;
2970
2971         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2972                 ohci->mc_allocated = false;
2973                 break;
2974         }
2975         *mask |= 1 << index;
2976
2977         spin_unlock_irqrestore(&ohci->lock, flags);
2978
2979         return ERR_PTR(ret);
2980 }
2981
2982 static int ohci_start_iso(struct fw_iso_context *base,
2983                           s32 cycle, u32 sync, u32 tags)
2984 {
2985         struct iso_context *ctx = container_of(base, struct iso_context, base);
2986         struct fw_ohci *ohci = ctx->context.ohci;
2987         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2988         int index;
2989
2990         /* the controller cannot start without any queued packets */
2991         if (ctx->context.last->branch_address == 0)
2992                 return -ENODATA;
2993
2994         switch (ctx->base.type) {
2995         case FW_ISO_CONTEXT_TRANSMIT:
2996                 index = ctx - ohci->it_context_list;
2997                 match = 0;
2998                 if (cycle >= 0)
2999                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3000                                 (cycle & 0x7fff) << 16;
3001
3002                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3003                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3004                 context_run(&ctx->context, match);
3005                 break;
3006
3007         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3008                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3009                 /* fall through */
3010         case FW_ISO_CONTEXT_RECEIVE:
3011                 index = ctx - ohci->ir_context_list;
3012                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3013                 if (cycle >= 0) {
3014                         match |= (cycle & 0x07fff) << 12;
3015                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3016                 }
3017
3018                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3019                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3020                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3021                 context_run(&ctx->context, control);
3022
3023                 ctx->sync = sync;
3024                 ctx->tags = tags;
3025
3026                 break;
3027         }
3028
3029         return 0;
3030 }
3031
3032 static int ohci_stop_iso(struct fw_iso_context *base)
3033 {
3034         struct fw_ohci *ohci = fw_ohci(base->card);
3035         struct iso_context *ctx = container_of(base, struct iso_context, base);
3036         int index;
3037
3038         switch (ctx->base.type) {
3039         case FW_ISO_CONTEXT_TRANSMIT:
3040                 index = ctx - ohci->it_context_list;
3041                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3042                 break;
3043
3044         case FW_ISO_CONTEXT_RECEIVE:
3045         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3046                 index = ctx - ohci->ir_context_list;
3047                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3048                 break;
3049         }
3050         flush_writes(ohci);
3051         context_stop(&ctx->context);
3052         tasklet_kill(&ctx->context.tasklet);
3053
3054         return 0;
3055 }
3056
3057 static void ohci_free_iso_context(struct fw_iso_context *base)
3058 {
3059         struct fw_ohci *ohci = fw_ohci(base->card);
3060         struct iso_context *ctx = container_of(base, struct iso_context, base);
3061         unsigned long flags;
3062         int index;
3063
3064         ohci_stop_iso(base);
3065         context_release(&ctx->context);
3066         free_page((unsigned long)ctx->header);
3067
3068         spin_lock_irqsave(&ohci->lock, flags);
3069
3070         switch (base->type) {
3071         case FW_ISO_CONTEXT_TRANSMIT:
3072                 index = ctx - ohci->it_context_list;
3073                 ohci->it_context_mask |= 1 << index;
3074                 break;
3075
3076         case FW_ISO_CONTEXT_RECEIVE:
3077                 index = ctx - ohci->ir_context_list;
3078                 ohci->ir_context_mask |= 1 << index;
3079                 ohci->ir_context_channels |= 1ULL << base->channel;
3080                 break;
3081
3082         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3083                 index = ctx - ohci->ir_context_list;
3084                 ohci->ir_context_mask |= 1 << index;
3085                 ohci->ir_context_channels |= ohci->mc_channels;
3086                 ohci->mc_channels = 0;
3087                 ohci->mc_allocated = false;
3088                 break;
3089         }
3090
3091         spin_unlock_irqrestore(&ohci->lock, flags);
3092 }
3093
3094 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3095 {
3096         struct fw_ohci *ohci = fw_ohci(base->card);
3097         unsigned long flags;
3098         int ret;
3099
3100         switch (base->type) {
3101         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3102
3103                 spin_lock_irqsave(&ohci->lock, flags);
3104
3105                 /* Don't allow multichannel to grab other contexts' channels. */
3106                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3107                         *channels = ohci->ir_context_channels;
3108                         ret = -EBUSY;
3109                 } else {
3110                         set_multichannel_mask(ohci, *channels);
3111                         ret = 0;
3112                 }
3113
3114                 spin_unlock_irqrestore(&ohci->lock, flags);
3115
3116                 break;
3117         default:
3118                 ret = -EINVAL;
3119         }
3120
3121         return ret;
3122 }
3123
3124 #ifdef CONFIG_PM
3125 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3126 {
3127         int i;
3128         struct iso_context *ctx;
3129
3130         for (i = 0 ; i < ohci->n_ir ; i++) {
3131                 ctx = &ohci->ir_context_list[i];
3132                 if (ctx->context.running)
3133                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3134         }
3135
3136         for (i = 0 ; i < ohci->n_it ; i++) {
3137                 ctx = &ohci->it_context_list[i];
3138                 if (ctx->context.running)
3139                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3140         }
3141 }
3142 #endif
3143
3144 static int queue_iso_transmit(struct iso_context *ctx,
3145                               struct fw_iso_packet *packet,
3146                               struct fw_iso_buffer *buffer,
3147                               unsigned long payload)
3148 {
3149         struct descriptor *d, *last, *pd;
3150         struct fw_iso_packet *p;
3151         __le32 *header;
3152         dma_addr_t d_bus, page_bus;
3153         u32 z, header_z, payload_z, irq;
3154         u32 payload_index, payload_end_index, next_page_index;
3155         int page, end_page, i, length, offset;
3156
3157         p = packet;
3158         payload_index = payload;
3159
3160         if (p->skip)
3161                 z = 1;
3162         else
3163                 z = 2;
3164         if (p->header_length > 0)
3165                 z++;
3166
3167         /* Determine the first page the payload isn't contained in. */
3168         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3169         if (p->payload_length > 0)
3170                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3171         else
3172                 payload_z = 0;
3173
3174         z += payload_z;
3175
3176         /* Get header size in number of descriptors. */
3177         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3178
3179         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3180         if (d == NULL)
3181                 return -ENOMEM;
3182
3183         if (!p->skip) {
3184                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3185                 d[0].req_count = cpu_to_le16(8);
3186                 /*
3187                  * Link the skip address to this descriptor itself.  This causes
3188                  * a context to skip a cycle whenever lost cycles or FIFO
3189                  * overruns occur, without dropping the data.  The application
3190                  * should then decide whether this is an error condition or not.
3191                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3192                  */
3193                 d[0].branch_address = cpu_to_le32(d_bus | z);
3194
3195                 header = (__le32 *) &d[1];
3196                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3197                                         IT_HEADER_TAG(p->tag) |
3198                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3199                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3200                                         IT_HEADER_SPEED(ctx->base.speed));
3201                 header[1] =
3202                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3203                                                           p->payload_length));
3204         }
3205
3206         if (p->header_length > 0) {
3207                 d[2].req_count    = cpu_to_le16(p->header_length);
3208                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3209                 memcpy(&d[z], p->header, p->header_length);
3210         }
3211
3212         pd = d + z - payload_z;
3213         payload_end_index = payload_index + p->payload_length;
3214         for (i = 0; i < payload_z; i++) {
3215                 page               = payload_index >> PAGE_SHIFT;
3216                 offset             = payload_index & ~PAGE_MASK;
3217                 next_page_index    = (page + 1) << PAGE_SHIFT;
3218                 length             =
3219                         min(next_page_index, payload_end_index) - payload_index;
3220                 pd[i].req_count    = cpu_to_le16(length);
3221
3222                 page_bus = page_private(buffer->pages[page]);
3223                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3224
3225                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3226                                                  page_bus, offset, length,
3227                                                  DMA_TO_DEVICE);
3228
3229                 payload_index += length;
3230         }
3231
3232         if (p->interrupt)
3233                 irq = DESCRIPTOR_IRQ_ALWAYS;
3234         else
3235                 irq = DESCRIPTOR_NO_IRQ;
3236
3237         last = z == 2 ? d : d + z - 1;
3238         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3239                                      DESCRIPTOR_STATUS |
3240                                      DESCRIPTOR_BRANCH_ALWAYS |
3241                                      irq);
3242
3243         context_append(&ctx->context, d, z, header_z);
3244
3245         return 0;
3246 }
3247
3248 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3249                                        struct fw_iso_packet *packet,
3250                                        struct fw_iso_buffer *buffer,
3251                                        unsigned long payload)
3252 {
3253         struct device *device = ctx->context.ohci->card.device;
3254         struct descriptor *d, *pd;
3255         dma_addr_t d_bus, page_bus;
3256         u32 z, header_z, rest;
3257         int i, j, length;
3258         int page, offset, packet_count, header_size, payload_per_buffer;
3259
3260         /*
3261          * The OHCI controller puts the isochronous header and trailer in the
3262          * buffer, so we need at least 8 bytes.
3263          */
3264         packet_count = packet->header_length / ctx->base.header_size;
3265         header_size  = max(ctx->base.header_size, (size_t)8);
3266
3267         /* Get header size in number of descriptors. */
3268         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3269         page     = payload >> PAGE_SHIFT;
3270         offset   = payload & ~PAGE_MASK;
3271         payload_per_buffer = packet->payload_length / packet_count;
3272
3273         for (i = 0; i < packet_count; i++) {
3274                 /* d points to the header descriptor */
3275                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3276                 d = context_get_descriptors(&ctx->context,
3277                                 z + header_z, &d_bus);
3278                 if (d == NULL)
3279                         return -ENOMEM;
3280
3281                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3282                                               DESCRIPTOR_INPUT_MORE);
3283                 if (packet->skip && i == 0)
3284                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3285                 d->req_count    = cpu_to_le16(header_size);
3286                 d->res_count    = d->req_count;
3287                 d->transfer_status = 0;
3288                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3289
3290                 rest = payload_per_buffer;
3291                 pd = d;
3292                 for (j = 1; j < z; j++) {
3293                         pd++;
3294                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3295                                                   DESCRIPTOR_INPUT_MORE);
3296
3297                         if (offset + rest < PAGE_SIZE)
3298                                 length = rest;
3299                         else
3300                                 length = PAGE_SIZE - offset;
3301                         pd->req_count = cpu_to_le16(length);
3302                         pd->res_count = pd->req_count;
3303                         pd->transfer_status = 0;
3304
3305                         page_bus = page_private(buffer->pages[page]);
3306                         pd->data_address = cpu_to_le32(page_bus + offset);
3307
3308                         dma_sync_single_range_for_device(device, page_bus,
3309                                                          offset, length,
3310                                                          DMA_FROM_DEVICE);
3311
3312                         offset = (offset + length) & ~PAGE_MASK;
3313                         rest -= length;
3314                         if (offset == 0)
3315                                 page++;
3316                 }
3317                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3318                                           DESCRIPTOR_INPUT_LAST |
3319                                           DESCRIPTOR_BRANCH_ALWAYS);
3320                 if (packet->interrupt && i == packet_count - 1)
3321                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3322
3323                 context_append(&ctx->context, d, z, header_z);
3324         }
3325
3326         return 0;
3327 }
3328
3329 static int queue_iso_buffer_fill(struct iso_context *ctx,
3330                                  struct fw_iso_packet *packet,
3331                                  struct fw_iso_buffer *buffer,
3332                                  unsigned long payload)
3333 {
3334         struct descriptor *d;
3335         dma_addr_t d_bus, page_bus;
3336         int page, offset, rest, z, i, length;
3337
3338         page   = payload >> PAGE_SHIFT;
3339         offset = payload & ~PAGE_MASK;
3340         rest   = packet->payload_length;
3341
3342         /* We need one descriptor for each page in the buffer. */
3343         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3344
3345         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3346                 return -EFAULT;
3347
3348         for (i = 0; i < z; i++) {
3349                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3350                 if (d == NULL)
3351                         return -ENOMEM;
3352
3353                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3354                                          DESCRIPTOR_BRANCH_ALWAYS);
3355                 if (packet->skip && i == 0)
3356                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3357                 if (packet->interrupt && i == z - 1)
3358                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3359
3360                 if (offset + rest < PAGE_SIZE)
3361                         length = rest;
3362                 else
3363                         length = PAGE_SIZE - offset;
3364                 d->req_count = cpu_to_le16(length);
3365                 d->res_count = d->req_count;
3366                 d->transfer_status = 0;
3367
3368                 page_bus = page_private(buffer->pages[page]);
3369                 d->data_address = cpu_to_le32(page_bus + offset);
3370
3371                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3372                                                  page_bus, offset, length,
3373                                                  DMA_FROM_DEVICE);
3374
3375                 rest -= length;
3376                 offset = 0;
3377                 page++;
3378
3379                 context_append(&ctx->context, d, 1, 0);
3380         }
3381
3382         return 0;
3383 }
3384
3385 static int ohci_queue_iso(struct fw_iso_context *base,
3386                           struct fw_iso_packet *packet,
3387                           struct fw_iso_buffer *buffer,
3388                           unsigned long payload)
3389 {
3390         struct iso_context *ctx = container_of(base, struct iso_context, base);
3391         unsigned long flags;
3392         int ret = -ENOSYS;
3393
3394         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3395         switch (base->type) {
3396         case FW_ISO_CONTEXT_TRANSMIT:
3397                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3398                 break;
3399         case FW_ISO_CONTEXT_RECEIVE:
3400                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3401                 break;
3402         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3403                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3404                 break;
3405         }
3406         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3407
3408         return ret;
3409 }
3410
3411 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3412 {
3413         struct context *ctx =
3414                         &container_of(base, struct iso_context, base)->context;
3415
3416         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3417 }
3418
3419 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3420 {
3421         struct iso_context *ctx = container_of(base, struct iso_context, base);
3422         int ret = 0;
3423
3424         tasklet_disable(&ctx->context.tasklet);
3425
3426         if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3427                 context_tasklet((unsigned long)&ctx->context);
3428
3429                 switch (base->type) {
3430                 case FW_ISO_CONTEXT_TRANSMIT:
3431                 case FW_ISO_CONTEXT_RECEIVE:
3432                         if (ctx->header_length != 0)
3433                                 flush_iso_completions(ctx);
3434                         break;
3435                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3436                         if (ctx->mc_completed != 0)
3437                                 flush_ir_buffer_fill(ctx);
3438                         break;
3439                 default:
3440                         ret = -ENOSYS;
3441                 }
3442
3443                 clear_bit_unlock(0, &ctx->flushing_completions);
3444                 smp_mb__after_clear_bit();
3445         }
3446
3447         tasklet_enable(&ctx->context.tasklet);
3448
3449         return ret;
3450 }
3451
3452 static const struct fw_card_driver ohci_driver = {
3453         .enable                 = ohci_enable,
3454         .read_phy_reg           = ohci_read_phy_reg,
3455         .update_phy_reg         = ohci_update_phy_reg,
3456         .set_config_rom         = ohci_set_config_rom,
3457         .send_request           = ohci_send_request,
3458         .send_response          = ohci_send_response,
3459         .cancel_packet          = ohci_cancel_packet,
3460         .enable_phys_dma        = ohci_enable_phys_dma,
3461         .read_csr               = ohci_read_csr,
3462         .write_csr              = ohci_write_csr,
3463
3464         .allocate_iso_context   = ohci_allocate_iso_context,
3465         .free_iso_context       = ohci_free_iso_context,
3466         .set_iso_channels       = ohci_set_iso_channels,
3467         .queue_iso              = ohci_queue_iso,
3468         .flush_queue_iso        = ohci_flush_queue_iso,
3469         .flush_iso_completions  = ohci_flush_iso_completions,
3470         .start_iso              = ohci_start_iso,
3471         .stop_iso               = ohci_stop_iso,
3472 };
3473
3474 #ifdef CONFIG_PPC_PMAC
3475 static void pmac_ohci_on(struct pci_dev *dev)
3476 {
3477         if (machine_is(powermac)) {
3478                 struct device_node *ofn = pci_device_to_OF_node(dev);
3479
3480                 if (ofn) {
3481                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3482                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3483                 }
3484         }
3485 }
3486
3487 static void pmac_ohci_off(struct pci_dev *dev)
3488 {
3489         if (machine_is(powermac)) {
3490                 struct device_node *ofn = pci_device_to_OF_node(dev);
3491
3492                 if (ofn) {
3493                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3494                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3495                 }
3496         }
3497 }
3498 #else
3499 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3500 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3501 #endif /* CONFIG_PPC_PMAC */
3502
3503 static int __devinit pci_probe(struct pci_dev *dev,
3504                                const struct pci_device_id *ent)
3505 {
3506         struct fw_ohci *ohci;
3507         u32 bus_options, max_receive, link_speed, version;
3508         u64 guid;
3509         int i, err;
3510         size_t size;
3511
3512         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3513                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3514                 return -ENOSYS;
3515         }
3516
3517         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3518         if (ohci == NULL) {
3519                 err = -ENOMEM;
3520                 goto fail;
3521         }
3522
3523         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3524
3525         pmac_ohci_on(dev);
3526
3527         err = pci_enable_device(dev);
3528         if (err) {
3529                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3530                 goto fail_free;
3531         }
3532
3533         pci_set_master(dev);
3534         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3535         pci_set_drvdata(dev, ohci);
3536
3537         spin_lock_init(&ohci->lock);
3538         mutex_init(&ohci->phy_reg_mutex);
3539
3540         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3541
3542         err = pci_request_region(dev, 0, ohci_driver_name);
3543         if (err) {
3544                 dev_err(&dev->dev, "MMIO resource unavailable\n");
3545                 goto fail_disable;
3546         }
3547
3548         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3549         if (ohci->registers == NULL) {
3550                 dev_err(&dev->dev, "failed to remap registers\n");
3551                 err = -ENXIO;
3552                 goto fail_iomem;
3553         }
3554
3555         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3556                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3557                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3558                      ohci_quirks[i].device == dev->device) &&
3559                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3560                      ohci_quirks[i].revision >= dev->revision)) {
3561                         ohci->quirks = ohci_quirks[i].flags;
3562                         break;
3563                 }
3564         if (param_quirks)
3565                 ohci->quirks = param_quirks;
3566
3567         /*
3568          * Because dma_alloc_coherent() allocates at least one page,
3569          * we save space by using a common buffer for the AR request/
3570          * response descriptors and the self IDs buffer.
3571          */
3572         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3573         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3574         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3575                                                PAGE_SIZE,
3576                                                &ohci->misc_buffer_bus,
3577                                                GFP_KERNEL);
3578         if (!ohci->misc_buffer) {
3579                 err = -ENOMEM;
3580                 goto fail_iounmap;
3581         }
3582
3583         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3584                               OHCI1394_AsReqRcvContextControlSet);
3585         if (err < 0)
3586                 goto fail_misc_buf;
3587
3588         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3589                               OHCI1394_AsRspRcvContextControlSet);
3590         if (err < 0)
3591                 goto fail_arreq_ctx;
3592
3593         err = context_init(&ohci->at_request_ctx, ohci,
3594                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3595         if (err < 0)
3596                 goto fail_arrsp_ctx;
3597
3598         err = context_init(&ohci->at_response_ctx, ohci,
3599                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3600         if (err < 0)
3601                 goto fail_atreq_ctx;
3602
3603         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3604         ohci->ir_context_channels = ~0ULL;
3605         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3606         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3607         ohci->ir_context_mask = ohci->ir_context_support;
3608         ohci->n_ir = hweight32(ohci->ir_context_mask);
3609         size = sizeof(struct iso_context) * ohci->n_ir;
3610         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3611
3612         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3613         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3614         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3615         ohci->it_context_mask = ohci->it_context_support;
3616         ohci->n_it = hweight32(ohci->it_context_mask);
3617         size = sizeof(struct iso_context) * ohci->n_it;
3618         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3619
3620         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3621                 err = -ENOMEM;
3622                 goto fail_contexts;
3623         }
3624
3625         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3626         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3627
3628         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3629         max_receive = (bus_options >> 12) & 0xf;
3630         link_speed = bus_options & 0x7;
3631         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3632                 reg_read(ohci, OHCI1394_GUIDLo);
3633
3634         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3635         if (err)
3636                 goto fail_contexts;
3637
3638         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3639         dev_notice(&dev->dev,
3640                   "added OHCI v%x.%x device as card %d, "
3641                   "%d IR + %d IT contexts, quirks 0x%x\n",
3642                   version >> 16, version & 0xff, ohci->card.index,
3643                   ohci->n_ir, ohci->n_it, ohci->quirks);
3644
3645         return 0;
3646
3647  fail_contexts:
3648         kfree(ohci->ir_context_list);
3649         kfree(ohci->it_context_list);
3650         context_release(&ohci->at_response_ctx);
3651  fail_atreq_ctx:
3652         context_release(&ohci->at_request_ctx);
3653  fail_arrsp_ctx:
3654         ar_context_release(&ohci->ar_response_ctx);
3655  fail_arreq_ctx:
3656         ar_context_release(&ohci->ar_request_ctx);
3657  fail_misc_buf:
3658         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3659                           ohci->misc_buffer, ohci->misc_buffer_bus);
3660  fail_iounmap:
3661         pci_iounmap(dev, ohci->registers);
3662  fail_iomem:
3663         pci_release_region(dev, 0);
3664  fail_disable:
3665         pci_disable_device(dev);
3666  fail_free:
3667         kfree(ohci);
3668         pmac_ohci_off(dev);
3669  fail:
3670         if (err == -ENOMEM)
3671                 dev_err(&dev->dev, "out of memory\n");
3672
3673         return err;
3674 }
3675
3676 static void pci_remove(struct pci_dev *dev)
3677 {
3678         struct fw_ohci *ohci;
3679
3680         ohci = pci_get_drvdata(dev);
3681         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3682         flush_writes(ohci);
3683         cancel_work_sync(&ohci->bus_reset_work);
3684         fw_core_remove_card(&ohci->card);
3685
3686         /*
3687          * FIXME: Fail all pending packets here, now that the upper
3688          * layers can't queue any more.
3689          */
3690
3691         software_reset(ohci);
3692         free_irq(dev->irq, ohci);
3693
3694         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3695                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3696                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3697         if (ohci->config_rom)
3698                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3699                                   ohci->config_rom, ohci->config_rom_bus);
3700         ar_context_release(&ohci->ar_request_ctx);
3701         ar_context_release(&ohci->ar_response_ctx);
3702         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3703                           ohci->misc_buffer, ohci->misc_buffer_bus);
3704         context_release(&ohci->at_request_ctx);
3705         context_release(&ohci->at_response_ctx);
3706         kfree(ohci->it_context_list);
3707         kfree(ohci->ir_context_list);
3708         pci_disable_msi(dev);
3709         pci_iounmap(dev, ohci->registers);
3710         pci_release_region(dev, 0);
3711         pci_disable_device(dev);
3712         kfree(ohci);
3713         pmac_ohci_off(dev);
3714
3715         dev_notice(&dev->dev, "removed fw-ohci device\n");
3716 }
3717
3718 #ifdef CONFIG_PM
3719 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3720 {
3721         struct fw_ohci *ohci = pci_get_drvdata(dev);
3722         int err;
3723
3724         software_reset(ohci);
3725         free_irq(dev->irq, ohci);
3726         pci_disable_msi(dev);
3727         err = pci_save_state(dev);
3728         if (err) {
3729                 dev_err(&dev->dev, "pci_save_state failed\n");
3730                 return err;
3731         }
3732         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3733         if (err)
3734                 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
3735         pmac_ohci_off(dev);
3736
3737         return 0;
3738 }
3739
3740 static int pci_resume(struct pci_dev *dev)
3741 {
3742         struct fw_ohci *ohci = pci_get_drvdata(dev);
3743         int err;
3744
3745         pmac_ohci_on(dev);
3746         pci_set_power_state(dev, PCI_D0);
3747         pci_restore_state(dev);
3748         err = pci_enable_device(dev);
3749         if (err) {
3750                 dev_err(&dev->dev, "pci_enable_device failed\n");
3751                 return err;
3752         }
3753
3754         /* Some systems don't setup GUID register on resume from ram  */
3755         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3756                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3757                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3758                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3759         }
3760
3761         err = ohci_enable(&ohci->card, NULL, 0);
3762         if (err)
3763                 return err;
3764
3765         ohci_resume_iso_dma(ohci);
3766
3767         return 0;
3768 }
3769 #endif
3770
3771 static const struct pci_device_id pci_table[] = {
3772         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3773         { }
3774 };
3775
3776 MODULE_DEVICE_TABLE(pci, pci_table);
3777
3778 static struct pci_driver fw_ohci_pci_driver = {
3779         .name           = ohci_driver_name,
3780         .id_table       = pci_table,
3781         .probe          = pci_probe,
3782         .remove         = pci_remove,
3783 #ifdef CONFIG_PM
3784         .resume         = pci_resume,
3785         .suspend        = pci_suspend,
3786 #endif
3787 };
3788
3789 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3790 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3791 MODULE_LICENSE("GPL");
3792
3793 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3794 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3795 MODULE_ALIAS("ohci1394");
3796 #endif
3797
3798 static int __init fw_ohci_init(void)
3799 {
3800         return pci_register_driver(&fw_ohci_pci_driver);
3801 }
3802
3803 static void __exit fw_ohci_cleanup(void)
3804 {
3805         pci_unregister_driver(&fw_ohci_pci_driver);
3806 }
3807
3808 module_init(fw_ohci_init);
3809 module_exit(fw_ohci_cleanup);