Pileus Git - ~andy/linux/blob - drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49 #include <asm/system.h>
  50
  51 #ifdef CONFIG_PPC_PMAC
  52 #include <asm/pmac_feature.h>
  53 #endif
  54
  55 #include "core.h"
  56 #include "ohci.h"
  57
  58 #define DESCRIPTOR_OUTPUT_MORE          0
  59 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  60 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  61 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  62 #define DESCRIPTOR_STATUS               (1 << 11)
  63 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  64 #define DESCRIPTOR_PING                 (1 << 7)
  65 #define DESCRIPTOR_YY                   (1 << 6)
  66 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  67 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  68 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  69 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  70 #define DESCRIPTOR_WAIT                 (3 << 0)
  71
  72 struct descriptor {
  73         __le16 req_count;
  74         __le16 control;
  75         __le32 data_address;
  76         __le32 branch_address;
  77         __le16 res_count;
  78         __le16 transfer_status;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 #define AR_BUFFER_SIZE  (32*1024)
  87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  88 /* we need at least two pages for proper list management */
  89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  90
  91 #define MAX_ASYNC_PAYLOAD       4096
  92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  94
  95 struct ar_context {
  96         struct fw_ohci *ohci;
  97         struct page *pages[AR_BUFFERS];
  98         void *buffer;
  99         struct descriptor *descriptors;
 100         dma_addr_t descriptors_bus;
 101         void *pointer;
 102         unsigned int last_buffer_index;
 103         u32 regs;
 104         struct tasklet_struct tasklet;
 105 };
 106
 107 struct context;
 108
 109 typedef int (*descriptor_callback_t)(struct context *ctx,
 110                                      struct descriptor *d,
 111                                      struct descriptor *last);
 112
 113 /*
 114  * A buffer that contains a block of DMA-able coherent memory used for
 115  * storing a portion of a DMA descriptor program.
 116  */
 117 struct descriptor_buffer {
 118         struct list_head list;
 119         dma_addr_t buffer_bus;
 120         size_t buffer_size;
 121         size_t used;
 122         struct descriptor buffer[0];
 123 };
 124
 125 struct context {
 126         struct fw_ohci *ohci;
 127         u32 regs;
 128         int total_allocation;
 129         u32 current_bus;
 130         bool running;
 131         bool flushing;
 132
 133         /*
 134          * List of page-sized buffers for storing DMA descriptors.
 135          * Head of list contains buffers in use and tail of list contains
 136          * free buffers.
 137          */
 138         struct list_head buffer_list;
 139
 140         /*
 141          * Pointer to a buffer inside buffer_list that contains the tail
 142          * end of the current DMA program.
 143          */
 144         struct descriptor_buffer *buffer_tail;
 145
 146         /*
 147          * The descriptor containing the branch address of the first
 148          * descriptor that has not yet been filled by the device.
 149          */
 150         struct descriptor *last;
 151
 152         /*
 153          * The last descriptor in the DMA program.  It contains the branch
 154          * address that must be updated upon appending a new descriptor.
 155          */
 156         struct descriptor *prev;
 157
 158         descriptor_callback_t callback;
 159
 160         struct tasklet_struct tasklet;
 161 };
 162
 163 #define IT_HEADER_SY(v)          ((v) <<  0)
 164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 166 #define IT_HEADER_TAG(v)         ((v) << 14)
 167 #define IT_HEADER_SPEED(v)       ((v) << 16)
 168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 169
 170 struct iso_context {
 171         struct fw_iso_context base;
 172         struct context context;
 173         int excess_bytes;
 174         void *header;
 175         size_t header_length;
 176
 177         u8 sync;
 178         u8 tags;
 179 };
 180
 181 #define CONFIG_ROM_SIZE 1024
 182
 183 struct fw_ohci {
 184         struct fw_card card;
 185
 186         __iomem char *registers;
 187         int node_id;
 188         int generation;
 189         int request_generation; /* for timestamping incoming requests */
 190         unsigned quirks;
 191         unsigned int pri_req_max;
 192         u32 bus_time;
 193         bool is_root;
 194         bool csr_state_setclear_abdicate;
 195         int n_ir;
 196         int n_it;
 197         /*
 198          * Spinlock for accessing fw_ohci data.  Never call out of
 199          * this driver with this lock held.
 200          */
 201         spinlock_t lock;
 202
 203         struct mutex phy_reg_mutex;
 204
 205         void *misc_buffer;
 206         dma_addr_t misc_buffer_bus;
 207
 208         struct ar_context ar_request_ctx;
 209         struct ar_context ar_response_ctx;
 210         struct context at_request_ctx;
 211         struct context at_response_ctx;
 212
 213         u32 it_context_support;
 214         u32 it_context_mask;     /* unoccupied IT contexts */
 215         struct iso_context *it_context_list;
 216         u64 ir_context_channels; /* unoccupied channels */
 217         u32 ir_context_support;
 218         u32 ir_context_mask;     /* unoccupied IR contexts */
 219         struct iso_context *ir_context_list;
 220         u64 mc_channels; /* channels in use by the multichannel IR context */
 221         bool mc_allocated;
 222
 223         __be32    *config_rom;
 224         dma_addr_t config_rom_bus;
 225         __be32    *next_config_rom;
 226         dma_addr_t next_config_rom_bus;
 227         __be32     next_header;
 228
 229         __le32    *self_id_cpu;
 230         dma_addr_t self_id_bus;
 231         struct work_struct bus_reset_work;
 232
 233         u32 self_id_buffer[512];
 234 };
 235
 236 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 237 {
 238         return container_of(card, struct fw_ohci, card);
 239 }
 240
 241 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 242 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 243 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 244 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 245 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 246 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 247
 248 #define CONTEXT_RUN     0x8000
 249 #define CONTEXT_WAKE    0x1000
 250 #define CONTEXT_DEAD    0x0800
 251 #define CONTEXT_ACTIVE  0x0400
 252
 253 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 254 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 255 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 256
 257 #define OHCI1394_REGISTER_SIZE          0x800
 258 #define OHCI1394_PCI_HCI_Control        0x40
 259 #define SELF_ID_BUF_SIZE                0x800
 260 #define OHCI_TCODE_PHY_PACKET           0x0e
 261 #define OHCI_VERSION_1_1                0x010010
 262
 263 static char ohci_driver_name[] = KBUILD_MODNAME;
 264
 265 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 267 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 268 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 269 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 270 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 271
 272 #define QUIRK_CYCLE_TIMER               1
 273 #define QUIRK_RESET_PACKET              2
 274 #define QUIRK_BE_HEADERS                4
 275 #define QUIRK_NO_1394A                  8
 276 #define QUIRK_NO_MSI                    16
 277 #define QUIRK_TI_SLLZ059                32
 278
 279 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 280 static const struct {
 281         unsigned short vendor, device, revision, flags;
 282 } ohci_quirks[] = {
 283         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 284                 QUIRK_CYCLE_TIMER},
 285
 286         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 287                 QUIRK_BE_HEADERS},
 288
 289         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 290                 QUIRK_NO_MSI},
 291
 292         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 293                 QUIRK_NO_MSI},
 294
 295         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 296                 QUIRK_CYCLE_TIMER},
 297
 298         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 299                 QUIRK_NO_MSI},
 300
 301         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 302                 QUIRK_CYCLE_TIMER},
 303
 304         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 305                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 306
 307         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 308                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 309
 310         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 311                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 312
 313         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 314                 QUIRK_RESET_PACKET},
 315
 316         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 317                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 318 };
 319
 320 /* This overrides anything that was found in ohci_quirks[]. */
 321 static int param_quirks;
 322 module_param_named(quirks, param_quirks, int, 0644);
 323 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 324         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 325         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 326         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 327         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 328         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 329         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 330         ")");
 331
 332 #define OHCI_PARAM_DEBUG_AT_AR          1
 333 #define OHCI_PARAM_DEBUG_SELFIDS        2
 334 #define OHCI_PARAM_DEBUG_IRQS           4
 335 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 336
 337 static int param_debug;
 338 module_param_named(debug, param_debug, int, 0644);
 339 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 340         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 341         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 342         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 343         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 344         ", or a combination, or all = -1)");
 345
 346 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 347 {
 348         if (likely(!(param_debug &
 349                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 350                 return;
 351
 352         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 353             !(evt & OHCI1394_busReset))
 354                 return;
 355
 356         dev_notice(ohci->card.device,
 357             "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 358             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 359             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 360             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 361             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 362             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 363             evt & OHCI1394_isochRx              ? " IR"                 : "",
 364             evt & OHCI1394_isochTx              ? " IT"                 : "",
 365             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 366             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 367             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 368             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 369             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 370             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 371             evt & OHCI1394_busReset             ? " busReset"           : "",
 372             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 373                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 374                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 375                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 376                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 377                     OHCI1394_cycleInconsistent |
 378                     OHCI1394_regAccessFail | OHCI1394_busReset)
 379                                                 ? " ?"                  : "");
 380 }
 381
 382 static const char *speed[] = {
 383         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 384 };
 385 static const char *power[] = {
 386         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 387         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 388 };
 389 static const char port[] = { '.', '-', 'p', 'c', };
 390
 391 static char _p(u32 *s, int shift)
 392 {
 393         return port[*s >> shift & 3];
 394 }
 395
 396 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 397 {
 398         u32 *s;
 399
 400         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 401                 return;
 402
 403         dev_notice(ohci->card.device,
 404                    "%d selfIDs, generation %d, local node ID %04x\n",
 405                    self_id_count, generation, ohci->node_id);
 406
 407         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 408                 if ((*s & 1 << 23) == 0)
 409                         dev_notice(ohci->card.device,
 410                             "selfID 0: %08x, phy %d [%c%c%c] "
 411                             "%s gc=%d %s %s%s%s\n",
 412                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 413                             speed[*s >> 14 & 3], *s >> 16 & 63,
 414                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 415                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 416                 else
 417                         dev_notice(ohci->card.device,
 418                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 419                             *s, *s >> 24 & 63,
 420                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 421                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 422 }
 423
 424 static const char *evts[] = {
 425         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 426         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 427         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 428         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 429         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 430         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 431         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 432         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 433         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 434         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 435         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 436         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 437         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 438         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 439         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 440         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 441         [0x20] = "pending/cancelled",
 442 };
 443 static const char *tcodes[] = {
 444         [0x0] = "QW req",               [0x1] = "BW req",
 445         [0x2] = "W resp",               [0x3] = "-reserved-",
 446         [0x4] = "QR req",               [0x5] = "BR req",
 447         [0x6] = "QR resp",              [0x7] = "BR resp",
 448         [0x8] = "cycle start",          [0x9] = "Lk req",
 449         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 450         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 451         [0xe] = "link internal",        [0xf] = "-reserved-",
 452 };
 453
 454 static void log_ar_at_event(struct fw_ohci *ohci,
 455                             char dir, int speed, u32 *header, int evt)
 456 {
 457         int tcode = header[0] >> 4 & 0xf;
 458         char specific[12];
 459
 460         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 461                 return;
 462
 463         if (unlikely(evt >= ARRAY_SIZE(evts)))
 464                         evt = 0x1f;
 465
 466         if (evt == OHCI1394_evt_bus_reset) {
 467                 dev_notice(ohci->card.device,
 468                            "A%c evt_bus_reset, generation %d\n",
 469                            dir, (header[2] >> 16) & 0xff);
 470                 return;
 471         }
 472
 473         switch (tcode) {
 474         case 0x0: case 0x6: case 0x8:
 475                 snprintf(specific, sizeof(specific), " = %08x",
 476                          be32_to_cpu((__force __be32)header[3]));
 477                 break;
 478         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 479                 snprintf(specific, sizeof(specific), " %x,%x",
 480                          header[3] >> 16, header[3] & 0xffff);
 481                 break;
 482         default:
 483                 specific[0] = '\0';
 484         }
 485
 486         switch (tcode) {
 487         case 0xa:
 488                 dev_notice(ohci->card.device,
 489                            "A%c %s, %s\n",
 490                            dir, evts[evt], tcodes[tcode]);
 491                 break;
 492         case 0xe:
 493                 dev_notice(ohci->card.device,
 494                            "A%c %s, PHY %08x %08x\n",
 495                            dir, evts[evt], header[1], header[2]);
 496                 break;
 497         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 498                 dev_notice(ohci->card.device,
 499                            "A%c spd %x tl %02x, "
 500                            "%04x -> %04x, %s, "
 501                            "%s, %04x%08x%s\n",
 502                            dir, speed, header[0] >> 10 & 0x3f,
 503                            header[1] >> 16, header[0] >> 16, evts[evt],
 504                            tcodes[tcode], header[1] & 0xffff, header[2], specific);
 505                 break;
 506         default:
 507                 dev_notice(ohci->card.device,
 508                            "A%c spd %x tl %02x, "
 509                            "%04x -> %04x, %s, "
 510                            "%s%s\n",
 511                            dir, speed, header[0] >> 10 & 0x3f,
 512                            header[1] >> 16, header[0] >> 16, evts[evt],
 513                            tcodes[tcode], specific);
 514         }
 515 }
 516
 517 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 518 {
 519         writel(data, ohci->registers + offset);
 520 }
 521
 522 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 523 {
 524         return readl(ohci->registers + offset);
 525 }
 526
 527 static inline void flush_writes(const struct fw_ohci *ohci)
 528 {
 529         /* Do a dummy read to flush writes. */
 530         reg_read(ohci, OHCI1394_Version);
 531 }
 532
 533 /*
 534  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 535  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 536  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 537  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 538  */
 539 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 540 {
 541         u32 val;
 542         int i;
 543
 544         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 545         for (i = 0; i < 3 + 100; i++) {
 546                 val = reg_read(ohci, OHCI1394_PhyControl);
 547                 if (!~val)
 548                         return -ENODEV; /* Card was ejected. */
 549
 550                 if (val & OHCI1394_PhyControl_ReadDone)
 551                         return OHCI1394_PhyControl_ReadData(val);
 552
 553                 /*
 554                  * Try a few times without waiting.  Sleeping is necessary
 555                  * only when the link/PHY interface is busy.
 556                  */
 557                 if (i >= 3)
 558                         msleep(1);
 559         }
 560         dev_err(ohci->card.device, "failed to read phy reg\n");
 561
 562         return -EBUSY;
 563 }
 564
 565 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 566 {
 567         int i;
 568
 569         reg_write(ohci, OHCI1394_PhyControl,
 570                   OHCI1394_PhyControl_Write(addr, val));
 571         for (i = 0; i < 3 + 100; i++) {
 572                 val = reg_read(ohci, OHCI1394_PhyControl);
 573                 if (!~val)
 574                         return -ENODEV; /* Card was ejected. */
 575
 576                 if (!(val & OHCI1394_PhyControl_WritePending))
 577                         return 0;
 578
 579                 if (i >= 3)
 580                         msleep(1);
 581         }
 582         dev_err(ohci->card.device, "failed to write phy reg\n");
 583
 584         return -EBUSY;
 585 }
 586
 587 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 588                           int clear_bits, int set_bits)
 589 {
 590         int ret = read_phy_reg(ohci, addr);
 591         if (ret < 0)
 592                 return ret;
 593
 594         /*
 595          * The interrupt status bits are cleared by writing a one bit.
 596          * Avoid clearing them unless explicitly requested in set_bits.
 597          */
 598         if (addr == 5)
 599                 clear_bits |= PHY_INT_STATUS_BITS;
 600
 601         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 602 }
 603
 604 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 605 {
 606         int ret;
 607
 608         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 609         if (ret < 0)
 610                 return ret;
 611
 612         return read_phy_reg(ohci, addr);
 613 }
 614
 615 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 616 {
 617         struct fw_ohci *ohci = fw_ohci(card);
 618         int ret;
 619
 620         mutex_lock(&ohci->phy_reg_mutex);
 621         ret = read_phy_reg(ohci, addr);
 622         mutex_unlock(&ohci->phy_reg_mutex);
 623
 624         return ret;
 625 }
 626
 627 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 628                                int clear_bits, int set_bits)
 629 {
 630         struct fw_ohci *ohci = fw_ohci(card);
 631         int ret;
 632
 633         mutex_lock(&ohci->phy_reg_mutex);
 634         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 635         mutex_unlock(&ohci->phy_reg_mutex);
 636
 637         return ret;
 638 }
 639
 640 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 641 {
 642         return page_private(ctx->pages[i]);
 643 }
 644
 645 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 646 {
 647         struct descriptor *d;
 648
 649         d = &ctx->descriptors[index];
 650         d->branch_address  &= cpu_to_le32(~0xf);
 651         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 652         d->transfer_status =  0;
 653
 654         wmb(); /* finish init of new descriptors before branch_address update */
 655         d = &ctx->descriptors[ctx->last_buffer_index];
 656         d->branch_address  |= cpu_to_le32(1);
 657
 658         ctx->last_buffer_index = index;
 659
 660         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 661 }
 662
 663 static void ar_context_release(struct ar_context *ctx)
 664 {
 665         unsigned int i;
 666
 667         if (ctx->buffer)
 668                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 669
 670         for (i = 0; i < AR_BUFFERS; i++)
 671                 if (ctx->pages[i]) {
 672                         dma_unmap_page(ctx->ohci->card.device,
 673                                        ar_buffer_bus(ctx, i),
 674                                        PAGE_SIZE, DMA_FROM_DEVICE);
 675                         __free_page(ctx->pages[i]);
 676                 }
 677 }
 678
 679 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 680 {
 681         struct fw_ohci *ohci = ctx->ohci;
 682
 683         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 684                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 685                 flush_writes(ohci);
 686
 687                 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
 688                         error_msg);
 689         }
 690         /* FIXME: restart? */
 691 }
 692
 693 static inline unsigned int ar_next_buffer_index(unsigned int index)
 694 {
 695         return (index + 1) % AR_BUFFERS;
 696 }
 697
 698 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 699 {
 700         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 701 }
 702
 703 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 704 {
 705         return ar_next_buffer_index(ctx->last_buffer_index);
 706 }
 707
 708 /*
 709  * We search for the buffer that contains the last AR packet DMA data written
 710  * by the controller.
 711  */
 712 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 713                                                  unsigned int *buffer_offset)
 714 {
 715         unsigned int i, next_i, last = ctx->last_buffer_index;
 716         __le16 res_count, next_res_count;
 717
 718         i = ar_first_buffer_index(ctx);
 719         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 720
 721         /* A buffer that is not yet completely filled must be the last one. */
 722         while (i != last && res_count == 0) {
 723
 724                 /* Peek at the next descriptor. */
 725                 next_i = ar_next_buffer_index(i);
 726                 rmb(); /* read descriptors in order */
 727                 next_res_count = ACCESS_ONCE(
 728                                 ctx->descriptors[next_i].res_count);
 729                 /*
 730                  * If the next descriptor is still empty, we must stop at this
 731                  * descriptor.
 732                  */
 733                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 734                         /*
 735                          * The exception is when the DMA data for one packet is
 736                          * split over three buffers; in this case, the middle
 737                          * buffer's descriptor might be never updated by the
 738                          * controller and look still empty, and we have to peek
 739                          * at the third one.
 740                          */
 741                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 742                                 next_i = ar_next_buffer_index(next_i);
 743                                 rmb();
 744                                 next_res_count = ACCESS_ONCE(
 745                                         ctx->descriptors[next_i].res_count);
 746                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 747                                         goto next_buffer_is_active;
 748                         }
 749
 750                         break;
 751                 }
 752
 753 next_buffer_is_active:
 754                 i = next_i;
 755                 res_count = next_res_count;
 756         }
 757
 758         rmb(); /* read res_count before the DMA data */
 759
 760         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 761         if (*buffer_offset > PAGE_SIZE) {
 762                 *buffer_offset = 0;
 763                 ar_context_abort(ctx, "corrupted descriptor");
 764         }
 765
 766         return i;
 767 }
 768
 769 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 770                                     unsigned int end_buffer_index,
 771                                     unsigned int end_buffer_offset)
 772 {
 773         unsigned int i;
 774
 775         i = ar_first_buffer_index(ctx);
 776         while (i != end_buffer_index) {
 777                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 778                                         ar_buffer_bus(ctx, i),
 779                                         PAGE_SIZE, DMA_FROM_DEVICE);
 780                 i = ar_next_buffer_index(i);
 781         }
 782         if (end_buffer_offset > 0)
 783                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 784                                         ar_buffer_bus(ctx, i),
 785                                         end_buffer_offset, DMA_FROM_DEVICE);
 786 }
 787
 788 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 789 #define cond_le32_to_cpu(v) \
 790         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 791 #else
 792 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 793 #endif
 794
 795 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 796 {
 797         struct fw_ohci *ohci = ctx->ohci;
 798         struct fw_packet p;
 799         u32 status, length, tcode;
 800         int evt;
 801
 802         p.header[0] = cond_le32_to_cpu(buffer[0]);
 803         p.header[1] = cond_le32_to_cpu(buffer[1]);
 804         p.header[2] = cond_le32_to_cpu(buffer[2]);
 805
 806         tcode = (p.header[0] >> 4) & 0x0f;
 807         switch (tcode) {
 808         case TCODE_WRITE_QUADLET_REQUEST:
 809         case TCODE_READ_QUADLET_RESPONSE:
 810                 p.header[3] = (__force __u32) buffer[3];
 811                 p.header_length = 16;
 812                 p.payload_length = 0;
 813                 break;
 814
 815         case TCODE_READ_BLOCK_REQUEST :
 816                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 817                 p.header_length = 16;
 818                 p.payload_length = 0;
 819                 break;
 820
 821         case TCODE_WRITE_BLOCK_REQUEST:
 822         case TCODE_READ_BLOCK_RESPONSE:
 823         case TCODE_LOCK_REQUEST:
 824         case TCODE_LOCK_RESPONSE:
 825                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 826                 p.header_length = 16;
 827                 p.payload_length = p.header[3] >> 16;
 828                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 829                         ar_context_abort(ctx, "invalid packet length");
 830                         return NULL;
 831                 }
 832                 break;
 833
 834         case TCODE_WRITE_RESPONSE:
 835         case TCODE_READ_QUADLET_REQUEST:
 836         case OHCI_TCODE_PHY_PACKET:
 837                 p.header_length = 12;
 838                 p.payload_length = 0;
 839                 break;
 840
 841         default:
 842                 ar_context_abort(ctx, "invalid tcode");
 843                 return NULL;
 844         }
 845
 846         p.payload = (void *) buffer + p.header_length;
 847
 848         /* FIXME: What to do about evt_* errors? */
 849         length = (p.header_length + p.payload_length + 3) / 4;
 850         status = cond_le32_to_cpu(buffer[length]);
 851         evt    = (status >> 16) & 0x1f;
 852
 853         p.ack        = evt - 16;
 854         p.speed      = (status >> 21) & 0x7;
 855         p.timestamp  = status & 0xffff;
 856         p.generation = ohci->request_generation;
 857
 858         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 859
 860         /*
 861          * Several controllers, notably from NEC and VIA, forget to
 862          * write ack_complete status at PHY packet reception.
 863          */
 864         if (evt == OHCI1394_evt_no_status &&
 865             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 866                 p.ack = ACK_COMPLETE;
 867
 868         /*
 869          * The OHCI bus reset handler synthesizes a PHY packet with
 870          * the new generation number when a bus reset happens (see
 871          * section 8.4.2.3).  This helps us determine when a request
 872          * was received and make sure we send the response in the same
 873          * generation.  We only need this for requests; for responses
 874          * we use the unique tlabel for finding the matching
 875          * request.
 876          *
 877          * Alas some chips sometimes emit bus reset packets with a
 878          * wrong generation.  We set the correct generation for these
 879          * at a slightly incorrect time (in bus_reset_work).
 880          */
 881         if (evt == OHCI1394_evt_bus_reset) {
 882                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 883                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 884         } else if (ctx == &ohci->ar_request_ctx) {
 885                 fw_core_handle_request(&ohci->card, &p);
 886         } else {
 887                 fw_core_handle_response(&ohci->card, &p);
 888         }
 889
 890         return buffer + length + 1;
 891 }
 892
 893 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 894 {
 895         void *next;
 896
 897         while (p < end) {
 898                 next = handle_ar_packet(ctx, p);
 899                 if (!next)
 900                         return p;
 901                 p = next;
 902         }
 903
 904         return p;
 905 }
 906
 907 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 908 {
 909         unsigned int i;
 910
 911         i = ar_first_buffer_index(ctx);
 912         while (i != end_buffer) {
 913                 dma_sync_single_for_device(ctx->ohci->card.device,
 914                                            ar_buffer_bus(ctx, i),
 915                                            PAGE_SIZE, DMA_FROM_DEVICE);
 916                 ar_context_link_page(ctx, i);
 917                 i = ar_next_buffer_index(i);
 918         }
 919 }
 920
 921 static void ar_context_tasklet(unsigned long data)
 922 {
 923         struct ar_context *ctx = (struct ar_context *)data;
 924         unsigned int end_buffer_index, end_buffer_offset;
 925         void *p, *end;
 926
 927         p = ctx->pointer;
 928         if (!p)
 929                 return;
 930
 931         end_buffer_index = ar_search_last_active_buffer(ctx,
 932                                                         &end_buffer_offset);
 933         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 934         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 935
 936         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 937                 /*
 938                  * The filled part of the overall buffer wraps around; handle
 939                  * all packets up to the buffer end here.  If the last packet
 940                  * wraps around, its tail will be visible after the buffer end
 941                  * because the buffer start pages are mapped there again.
 942                  */
 943                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 944                 p = handle_ar_packets(ctx, p, buffer_end);
 945                 if (p < buffer_end)
 946                         goto error;
 947                 /* adjust p to point back into the actual buffer */
 948                 p -= AR_BUFFERS * PAGE_SIZE;
 949         }
 950
 951         p = handle_ar_packets(ctx, p, end);
 952         if (p != end) {
 953                 if (p > end)
 954                         ar_context_abort(ctx, "inconsistent descriptor");
 955                 goto error;
 956         }
 957
 958         ctx->pointer = p;
 959         ar_recycle_buffers(ctx, end_buffer_index);
 960
 961         return;
 962
 963 error:
 964         ctx->pointer = NULL;
 965 }
 966
 967 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 968                            unsigned int descriptors_offset, u32 regs)
 969 {
 970         unsigned int i;
 971         dma_addr_t dma_addr;
 972         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 973         struct descriptor *d;
 974
 975         ctx->regs        = regs;
 976         ctx->ohci        = ohci;
 977         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 978
 979         for (i = 0; i < AR_BUFFERS; i++) {
 980                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 981                 if (!ctx->pages[i])
 982                         goto out_of_memory;
 983                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 984                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 985                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 986                         __free_page(ctx->pages[i]);
 987                         ctx->pages[i] = NULL;
 988                         goto out_of_memory;
 989                 }
 990                 set_page_private(ctx->pages[i], dma_addr);
 991         }
 992
 993         for (i = 0; i < AR_BUFFERS; i++)
 994                 pages[i]              = ctx->pages[i];
 995         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 996                 pages[AR_BUFFERS + i] = ctx->pages[i];
 997         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 998                                  -1, PAGE_KERNEL);
 999         if (!ctx->buffer)
1000                 goto out_of_memory;
1001
1002         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1003         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1004
1005         for (i = 0; i < AR_BUFFERS; i++) {
1006                 d = &ctx->descriptors[i];
1007                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1008                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1009                                                 DESCRIPTOR_STATUS |
1010                                                 DESCRIPTOR_BRANCH_ALWAYS);
1011                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1012                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1013                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1014         }
1015
1016         return 0;
1017
1018 out_of_memory:
1019         ar_context_release(ctx);
1020
1021         return -ENOMEM;
1022 }
1023
1024 static void ar_context_run(struct ar_context *ctx)
1025 {
1026         unsigned int i;
1027
1028         for (i = 0; i < AR_BUFFERS; i++)
1029                 ar_context_link_page(ctx, i);
1030
1031         ctx->pointer = ctx->buffer;
1032
1033         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1034         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1035 }
1036
1037 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1038 {
1039         __le16 branch;
1040
1041         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1042
1043         /* figure out which descriptor the branch address goes in */
1044         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1045                 return d;
1046         else
1047                 return d + z - 1;
1048 }
1049
1050 static void context_tasklet(unsigned long data)
1051 {
1052         struct context *ctx = (struct context *) data;
1053         struct descriptor *d, *last;
1054         u32 address;
1055         int z;
1056         struct descriptor_buffer *desc;
1057
1058         desc = list_entry(ctx->buffer_list.next,
1059                         struct descriptor_buffer, list);
1060         last = ctx->last;
1061         while (last->branch_address != 0) {
1062                 struct descriptor_buffer *old_desc = desc;
1063                 address = le32_to_cpu(last->branch_address);
1064                 z = address & 0xf;
1065                 address &= ~0xf;
1066                 ctx->current_bus = address;
1067
1068                 /* If the branch address points to a buffer outside of the
1069                  * current buffer, advance to the next buffer. */
1070                 if (address < desc->buffer_bus ||
1071                                 address >= desc->buffer_bus + desc->used)
1072                         desc = list_entry(desc->list.next,
1073                                         struct descriptor_buffer, list);
1074                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1075                 last = find_branch_descriptor(d, z);
1076
1077                 if (!ctx->callback(ctx, d, last))
1078                         break;
1079
1080                 if (old_desc != desc) {
1081                         /* If we've advanced to the next buffer, move the
1082                          * previous buffer to the free list. */
1083                         unsigned long flags;
1084                         old_desc->used = 0;
1085                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1086                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1087                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1088                 }
1089                 ctx->last = last;
1090         }
1091 }
1092
1093 /*
1094  * Allocate a new buffer and add it to the list of free buffers for this
1095  * context.  Must be called with ohci->lock held.
1096  */
1097 static int context_add_buffer(struct context *ctx)
1098 {
1099         struct descriptor_buffer *desc;
1100         dma_addr_t uninitialized_var(bus_addr);
1101         int offset;
1102
1103         /*
1104          * 16MB of descriptors should be far more than enough for any DMA
1105          * program.  This will catch run-away userspace or DoS attacks.
1106          */
1107         if (ctx->total_allocation >= 16*1024*1024)
1108                 return -ENOMEM;
1109
1110         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1111                         &bus_addr, GFP_ATOMIC);
1112         if (!desc)
1113                 return -ENOMEM;
1114
1115         offset = (void *)&desc->buffer - (void *)desc;
1116         desc->buffer_size = PAGE_SIZE - offset;
1117         desc->buffer_bus = bus_addr + offset;
1118         desc->used = 0;
1119
1120         list_add_tail(&desc->list, &ctx->buffer_list);
1121         ctx->total_allocation += PAGE_SIZE;
1122
1123         return 0;
1124 }
1125
1126 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1127                         u32 regs, descriptor_callback_t callback)
1128 {
1129         ctx->ohci = ohci;
1130         ctx->regs = regs;
1131         ctx->total_allocation = 0;
1132
1133         INIT_LIST_HEAD(&ctx->buffer_list);
1134         if (context_add_buffer(ctx) < 0)
1135                 return -ENOMEM;
1136
1137         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1138                         struct descriptor_buffer, list);
1139
1140         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1141         ctx->callback = callback;
1142
1143         /*
1144          * We put a dummy descriptor in the buffer that has a NULL
1145          * branch address and looks like it's been sent.  That way we
1146          * have a descriptor to append DMA programs to.
1147          */
1148         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1149         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1150         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1151         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1152         ctx->last = ctx->buffer_tail->buffer;
1153         ctx->prev = ctx->buffer_tail->buffer;
1154
1155         return 0;
1156 }
1157
1158 static void context_release(struct context *ctx)
1159 {
1160         struct fw_card *card = &ctx->ohci->card;
1161         struct descriptor_buffer *desc, *tmp;
1162
1163         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1164                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1165                         desc->buffer_bus -
1166                         ((void *)&desc->buffer - (void *)desc));
1167 }
1168
1169 /* Must be called with ohci->lock held */
1170 static struct descriptor *context_get_descriptors(struct context *ctx,
1171                                                   int z, dma_addr_t *d_bus)
1172 {
1173         struct descriptor *d = NULL;
1174         struct descriptor_buffer *desc = ctx->buffer_tail;
1175
1176         if (z * sizeof(*d) > desc->buffer_size)
1177                 return NULL;
1178
1179         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1180                 /* No room for the descriptor in this buffer, so advance to the
1181                  * next one. */
1182
1183                 if (desc->list.next == &ctx->buffer_list) {
1184                         /* If there is no free buffer next in the list,
1185                          * allocate one. */
1186                         if (context_add_buffer(ctx) < 0)
1187                                 return NULL;
1188                 }
1189                 desc = list_entry(desc->list.next,
1190                                 struct descriptor_buffer, list);
1191                 ctx->buffer_tail = desc;
1192         }
1193
1194         d = desc->buffer + desc->used / sizeof(*d);
1195         memset(d, 0, z * sizeof(*d));
1196         *d_bus = desc->buffer_bus + desc->used;
1197
1198         return d;
1199 }
1200
1201 static void context_run(struct context *ctx, u32 extra)
1202 {
1203         struct fw_ohci *ohci = ctx->ohci;
1204
1205         reg_write(ohci, COMMAND_PTR(ctx->regs),
1206                   le32_to_cpu(ctx->last->branch_address));
1207         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1208         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1209         ctx->running = true;
1210         flush_writes(ohci);
1211 }
1212
1213 static void context_append(struct context *ctx,
1214                            struct descriptor *d, int z, int extra)
1215 {
1216         dma_addr_t d_bus;
1217         struct descriptor_buffer *desc = ctx->buffer_tail;
1218
1219         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1220
1221         desc->used += (z + extra) * sizeof(*d);
1222
1223         wmb(); /* finish init of new descriptors before branch_address update */
1224         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1225         ctx->prev = find_branch_descriptor(d, z);
1226 }
1227
1228 static void context_stop(struct context *ctx)
1229 {
1230         struct fw_ohci *ohci = ctx->ohci;
1231         u32 reg;
1232         int i;
1233
1234         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1235         ctx->running = false;
1236
1237         for (i = 0; i < 1000; i++) {
1238                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1239                 if ((reg & CONTEXT_ACTIVE) == 0)
1240                         return;
1241
1242                 if (i)
1243                         udelay(10);
1244         }
1245         dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
1246 }
1247
1248 struct driver_data {
1249         u8 inline_data[8];
1250         struct fw_packet *packet;
1251 };
1252
1253 /*
1254  * This function apppends a packet to the DMA queue for transmission.
1255  * Must always be called with the ochi->lock held to ensure proper
1256  * generation handling and locking around packet queue manipulation.
1257  */
1258 static int at_context_queue_packet(struct context *ctx,
1259                                    struct fw_packet *packet)
1260 {
1261         struct fw_ohci *ohci = ctx->ohci;
1262         dma_addr_t d_bus, uninitialized_var(payload_bus);
1263         struct driver_data *driver_data;
1264         struct descriptor *d, *last;
1265         __le32 *header;
1266         int z, tcode;
1267
1268         d = context_get_descriptors(ctx, 4, &d_bus);
1269         if (d == NULL) {
1270                 packet->ack = RCODE_SEND_ERROR;
1271                 return -1;
1272         }
1273
1274         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1275         d[0].res_count = cpu_to_le16(packet->timestamp);
1276
1277         /*
1278          * The DMA format for asyncronous link packets is different
1279          * from the IEEE1394 layout, so shift the fields around
1280          * accordingly.
1281          */
1282
1283         tcode = (packet->header[0] >> 4) & 0x0f;
1284         header = (__le32 *) &d[1];
1285         switch (tcode) {
1286         case TCODE_WRITE_QUADLET_REQUEST:
1287         case TCODE_WRITE_BLOCK_REQUEST:
1288         case TCODE_WRITE_RESPONSE:
1289         case TCODE_READ_QUADLET_REQUEST:
1290         case TCODE_READ_BLOCK_REQUEST:
1291         case TCODE_READ_QUADLET_RESPONSE:
1292         case TCODE_READ_BLOCK_RESPONSE:
1293         case TCODE_LOCK_REQUEST:
1294         case TCODE_LOCK_RESPONSE:
1295                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1296                                         (packet->speed << 16));
1297                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1298                                         (packet->header[0] & 0xffff0000));
1299                 header[2] = cpu_to_le32(packet->header[2]);
1300
1301                 if (TCODE_IS_BLOCK_PACKET(tcode))
1302                         header[3] = cpu_to_le32(packet->header[3]);
1303                 else
1304                         header[3] = (__force __le32) packet->header[3];
1305
1306                 d[0].req_count = cpu_to_le16(packet->header_length);
1307                 break;
1308
1309         case TCODE_LINK_INTERNAL:
1310                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1311                                         (packet->speed << 16));
1312                 header[1] = cpu_to_le32(packet->header[1]);
1313                 header[2] = cpu_to_le32(packet->header[2]);
1314                 d[0].req_count = cpu_to_le16(12);
1315
1316                 if (is_ping_packet(&packet->header[1]))
1317                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1318                 break;
1319
1320         case TCODE_STREAM_DATA:
1321                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1322                                         (packet->speed << 16));
1323                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1324                 d[0].req_count = cpu_to_le16(8);
1325                 break;
1326
1327         default:
1328                 /* BUG(); */
1329                 packet->ack = RCODE_SEND_ERROR;
1330                 return -1;
1331         }
1332
1333         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1334         driver_data = (struct driver_data *) &d[3];
1335         driver_data->packet = packet;
1336         packet->driver_data = driver_data;
1337
1338         if (packet->payload_length > 0) {
1339                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1340                         payload_bus = dma_map_single(ohci->card.device,
1341                                                      packet->payload,
1342                                                      packet->payload_length,
1343                                                      DMA_TO_DEVICE);
1344                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1345                                 packet->ack = RCODE_SEND_ERROR;
1346                                 return -1;
1347                         }
1348                         packet->payload_bus     = payload_bus;
1349                         packet->payload_mapped  = true;
1350                 } else {
1351                         memcpy(driver_data->inline_data, packet->payload,
1352                                packet->payload_length);
1353                         payload_bus = d_bus + 3 * sizeof(*d);
1354                 }
1355
1356                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1357                 d[2].data_address = cpu_to_le32(payload_bus);
1358                 last = &d[2];
1359                 z = 3;
1360         } else {
1361                 last = &d[0];
1362                 z = 2;
1363         }
1364
1365         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1366                                      DESCRIPTOR_IRQ_ALWAYS |
1367                                      DESCRIPTOR_BRANCH_ALWAYS);
1368
1369         /* FIXME: Document how the locking works. */
1370         if (ohci->generation != packet->generation) {
1371                 if (packet->payload_mapped)
1372                         dma_unmap_single(ohci->card.device, payload_bus,
1373                                          packet->payload_length, DMA_TO_DEVICE);
1374                 packet->ack = RCODE_GENERATION;
1375                 return -1;
1376         }
1377
1378         context_append(ctx, d, z, 4 - z);
1379
1380         if (ctx->running)
1381                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1382         else
1383                 context_run(ctx, 0);
1384
1385         return 0;
1386 }
1387
1388 static void at_context_flush(struct context *ctx)
1389 {
1390         tasklet_disable(&ctx->tasklet);
1391
1392         ctx->flushing = true;
1393         context_tasklet((unsigned long)ctx);
1394         ctx->flushing = false;
1395
1396         tasklet_enable(&ctx->tasklet);
1397 }
1398
1399 static int handle_at_packet(struct context *context,
1400                             struct descriptor *d,
1401                             struct descriptor *last)
1402 {
1403         struct driver_data *driver_data;
1404         struct fw_packet *packet;
1405         struct fw_ohci *ohci = context->ohci;
1406         int evt;
1407
1408         if (last->transfer_status == 0 && !context->flushing)
1409                 /* This descriptor isn't done yet, stop iteration. */
1410                 return 0;
1411
1412         driver_data = (struct driver_data *) &d[3];
1413         packet = driver_data->packet;
1414         if (packet == NULL)
1415                 /* This packet was cancelled, just continue. */
1416                 return 1;
1417
1418         if (packet->payload_mapped)
1419                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1420                                  packet->payload_length, DMA_TO_DEVICE);
1421
1422         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1423         packet->timestamp = le16_to_cpu(last->res_count);
1424
1425         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1426
1427         switch (evt) {
1428         case OHCI1394_evt_timeout:
1429                 /* Async response transmit timed out. */
1430                 packet->ack = RCODE_CANCELLED;
1431                 break;
1432
1433         case OHCI1394_evt_flushed:
1434                 /*
1435                  * The packet was flushed should give same error as
1436                  * when we try to use a stale generation count.
1437                  */
1438                 packet->ack = RCODE_GENERATION;
1439                 break;
1440
1441         case OHCI1394_evt_missing_ack:
1442                 if (context->flushing)
1443                         packet->ack = RCODE_GENERATION;
1444                 else {
1445                         /*
1446                          * Using a valid (current) generation count, but the
1447                          * node is not on the bus or not sending acks.
1448                          */
1449                         packet->ack = RCODE_NO_ACK;
1450                 }
1451                 break;
1452
1453         case ACK_COMPLETE + 0x10:
1454         case ACK_PENDING + 0x10:
1455         case ACK_BUSY_X + 0x10:
1456         case ACK_BUSY_A + 0x10:
1457         case ACK_BUSY_B + 0x10:
1458         case ACK_DATA_ERROR + 0x10:
1459         case ACK_TYPE_ERROR + 0x10:
1460                 packet->ack = evt - 0x10;
1461                 break;
1462
1463         case OHCI1394_evt_no_status:
1464                 if (context->flushing) {
1465                         packet->ack = RCODE_GENERATION;
1466                         break;
1467                 }
1468                 /* fall through */
1469
1470         default:
1471                 packet->ack = RCODE_SEND_ERROR;
1472                 break;
1473         }
1474
1475         packet->callback(packet, &ohci->card, packet->ack);
1476
1477         return 1;
1478 }
1479
1480 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1481 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1482 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1483 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1484 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1485
1486 static void handle_local_rom(struct fw_ohci *ohci,
1487                              struct fw_packet *packet, u32 csr)
1488 {
1489         struct fw_packet response;
1490         int tcode, length, i;
1491
1492         tcode = HEADER_GET_TCODE(packet->header[0]);
1493         if (TCODE_IS_BLOCK_PACKET(tcode))
1494                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1495         else
1496                 length = 4;
1497
1498         i = csr - CSR_CONFIG_ROM;
1499         if (i + length > CONFIG_ROM_SIZE) {
1500                 fw_fill_response(&response, packet->header,
1501                                  RCODE_ADDRESS_ERROR, NULL, 0);
1502         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1503                 fw_fill_response(&response, packet->header,
1504                                  RCODE_TYPE_ERROR, NULL, 0);
1505         } else {
1506                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1507                                  (void *) ohci->config_rom + i, length);
1508         }
1509
1510         fw_core_handle_response(&ohci->card, &response);
1511 }
1512
1513 static void handle_local_lock(struct fw_ohci *ohci,
1514                               struct fw_packet *packet, u32 csr)
1515 {
1516         struct fw_packet response;
1517         int tcode, length, ext_tcode, sel, try;
1518         __be32 *payload, lock_old;
1519         u32 lock_arg, lock_data;
1520
1521         tcode = HEADER_GET_TCODE(packet->header[0]);
1522         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1523         payload = packet->payload;
1524         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1525
1526         if (tcode == TCODE_LOCK_REQUEST &&
1527             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1528                 lock_arg = be32_to_cpu(payload[0]);
1529                 lock_data = be32_to_cpu(payload[1]);
1530         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1531                 lock_arg = 0;
1532                 lock_data = 0;
1533         } else {
1534                 fw_fill_response(&response, packet->header,
1535                                  RCODE_TYPE_ERROR, NULL, 0);
1536                 goto out;
1537         }
1538
1539         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1540         reg_write(ohci, OHCI1394_CSRData, lock_data);
1541         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1542         reg_write(ohci, OHCI1394_CSRControl, sel);
1543
1544         for (try = 0; try < 20; try++)
1545                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1546                         lock_old = cpu_to_be32(reg_read(ohci,
1547                                                         OHCI1394_CSRData));
1548                         fw_fill_response(&response, packet->header,
1549                                          RCODE_COMPLETE,
1550                                          &lock_old, sizeof(lock_old));
1551                         goto out;
1552                 }
1553
1554         dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
1555         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1556
1557  out:
1558         fw_core_handle_response(&ohci->card, &response);
1559 }
1560
1561 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1562 {
1563         u64 offset, csr;
1564
1565         if (ctx == &ctx->ohci->at_request_ctx) {
1566                 packet->ack = ACK_PENDING;
1567                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1568         }
1569
1570         offset =
1571                 ((unsigned long long)
1572                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1573                 packet->header[2];
1574         csr = offset - CSR_REGISTER_BASE;
1575
1576         /* Handle config rom reads. */
1577         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1578                 handle_local_rom(ctx->ohci, packet, csr);
1579         else switch (csr) {
1580         case CSR_BUS_MANAGER_ID:
1581         case CSR_BANDWIDTH_AVAILABLE:
1582         case CSR_CHANNELS_AVAILABLE_HI:
1583         case CSR_CHANNELS_AVAILABLE_LO:
1584                 handle_local_lock(ctx->ohci, packet, csr);
1585                 break;
1586         default:
1587                 if (ctx == &ctx->ohci->at_request_ctx)
1588                         fw_core_handle_request(&ctx->ohci->card, packet);
1589                 else
1590                         fw_core_handle_response(&ctx->ohci->card, packet);
1591                 break;
1592         }
1593
1594         if (ctx == &ctx->ohci->at_response_ctx) {
1595                 packet->ack = ACK_COMPLETE;
1596                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1597         }
1598 }
1599
1600 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1601 {
1602         unsigned long flags;
1603         int ret;
1604
1605         spin_lock_irqsave(&ctx->ohci->lock, flags);
1606
1607         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1608             ctx->ohci->generation == packet->generation) {
1609                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1610                 handle_local_request(ctx, packet);
1611                 return;
1612         }
1613
1614         ret = at_context_queue_packet(ctx, packet);
1615         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1616
1617         if (ret < 0)
1618                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1619
1620 }
1621
1622 static void detect_dead_context(struct fw_ohci *ohci,
1623                                 const char *name, unsigned int regs)
1624 {
1625         u32 ctl;
1626
1627         ctl = reg_read(ohci, CONTROL_SET(regs));
1628         if (ctl & CONTEXT_DEAD)
1629                 dev_err(ohci->card.device,
1630                         "DMA context %s has stopped, error code: %s\n",
1631                         name, evts[ctl & 0x1f]);
1632 }
1633
1634 static void handle_dead_contexts(struct fw_ohci *ohci)
1635 {
1636         unsigned int i;
1637         char name[8];
1638
1639         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1640         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1641         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1642         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1643         for (i = 0; i < 32; ++i) {
1644                 if (!(ohci->it_context_support & (1 << i)))
1645                         continue;
1646                 sprintf(name, "IT%u", i);
1647                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1648         }
1649         for (i = 0; i < 32; ++i) {
1650                 if (!(ohci->ir_context_support & (1 << i)))
1651                         continue;
1652                 sprintf(name, "IR%u", i);
1653                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1654         }
1655         /* TODO: maybe try to flush and restart the dead contexts */
1656 }
1657
1658 static u32 cycle_timer_ticks(u32 cycle_timer)
1659 {
1660         u32 ticks;
1661
1662         ticks = cycle_timer & 0xfff;
1663         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1664         ticks += (3072 * 8000) * (cycle_timer >> 25);
1665
1666         return ticks;
1667 }
1668
1669 /*
1670  * Some controllers exhibit one or more of the following bugs when updating the
1671  * iso cycle timer register:
1672  *  - When the lowest six bits are wrapping around to zero, a read that happens
1673  *    at the same time will return garbage in the lowest ten bits.
1674  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1675  *    not incremented for about 60 ns.
1676  *  - Occasionally, the entire register reads zero.
1677  *
1678  * To catch these, we read the register three times and ensure that the
1679  * difference between each two consecutive reads is approximately the same, i.e.
1680  * less than twice the other.  Furthermore, any negative difference indicates an
1681  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1682  * execute, so we have enough precision to compute the ratio of the differences.)
1683  */
1684 static u32 get_cycle_time(struct fw_ohci *ohci)
1685 {
1686         u32 c0, c1, c2;
1687         u32 t0, t1, t2;
1688         s32 diff01, diff12;
1689         int i;
1690
1691         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1692
1693         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1694                 i = 0;
1695                 c1 = c2;
1696                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1697                 do {
1698                         c0 = c1;
1699                         c1 = c2;
1700                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1701                         t0 = cycle_timer_ticks(c0);
1702                         t1 = cycle_timer_ticks(c1);
1703                         t2 = cycle_timer_ticks(c2);
1704                         diff01 = t1 - t0;
1705                         diff12 = t2 - t1;
1706                 } while ((diff01 <= 0 || diff12 <= 0 ||
1707                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1708                          && i++ < 20);
1709         }
1710
1711         return c2;
1712 }
1713
1714 /*
1715  * This function has to be called at least every 64 seconds.  The bus_time
1716  * field stores not only the upper 25 bits of the BUS_TIME register but also
1717  * the most significant bit of the cycle timer in bit 6 so that we can detect
1718  * changes in this bit.
1719  */
1720 static u32 update_bus_time(struct fw_ohci *ohci)
1721 {
1722         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1723
1724         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1725                 ohci->bus_time += 0x40;
1726
1727         return ohci->bus_time | cycle_time_seconds;
1728 }
1729
1730 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1731 {
1732         int reg;
1733
1734         mutex_lock(&ohci->phy_reg_mutex);
1735         reg = write_phy_reg(ohci, 7, port_index);
1736         if (reg >= 0)
1737                 reg = read_phy_reg(ohci, 8);
1738         mutex_unlock(&ohci->phy_reg_mutex);
1739         if (reg < 0)
1740                 return reg;
1741
1742         switch (reg & 0x0f) {
1743         case 0x06:
1744                 return 2;       /* is child node (connected to parent node) */
1745         case 0x0e:
1746                 return 3;       /* is parent node (connected to child node) */
1747         }
1748         return 1;               /* not connected */
1749 }
1750
1751 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1752         int self_id_count)
1753 {
1754         int i;
1755         u32 entry;
1756
1757         for (i = 0; i < self_id_count; i++) {
1758                 entry = ohci->self_id_buffer[i];
1759                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1760                         return -1;
1761                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1762                         return i;
1763         }
1764         return i;
1765 }
1766
1767 /*
1768  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1769  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1770  * Construct the selfID from phy register contents.
1771  * FIXME:  How to determine the selfID.i flag?
1772  */
1773 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1774 {
1775         int reg, i, pos, status;
1776         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1777         u32 self_id = 0x8040c800;
1778
1779         reg = reg_read(ohci, OHCI1394_NodeID);
1780         if (!(reg & OHCI1394_NodeID_idValid)) {
1781                 dev_notice(ohci->card.device,
1782                            "node ID not valid, new bus reset in progress\n");
1783                 return -EBUSY;
1784         }
1785         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1786
1787         reg = ohci_read_phy_reg(&ohci->card, 4);
1788         if (reg < 0)
1789                 return reg;
1790         self_id |= ((reg & 0x07) << 8); /* power class */
1791
1792         reg = ohci_read_phy_reg(&ohci->card, 1);
1793         if (reg < 0)
1794                 return reg;
1795         self_id |= ((reg & 0x3f) << 16); /* gap count */
1796
1797         for (i = 0; i < 3; i++) {
1798                 status = get_status_for_port(ohci, i);
1799                 if (status < 0)
1800                         return status;
1801                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1802         }
1803
1804         pos = get_self_id_pos(ohci, self_id, self_id_count);
1805         if (pos >= 0) {
1806                 memmove(&(ohci->self_id_buffer[pos+1]),
1807                         &(ohci->self_id_buffer[pos]),
1808                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1809                 ohci->self_id_buffer[pos] = self_id;
1810                 self_id_count++;
1811         }
1812         return self_id_count;
1813 }
1814
1815 static void bus_reset_work(struct work_struct *work)
1816 {
1817         struct fw_ohci *ohci =
1818                 container_of(work, struct fw_ohci, bus_reset_work);
1819         int self_id_count, i, j, reg;
1820         int generation, new_generation;
1821         unsigned long flags;
1822         void *free_rom = NULL;
1823         dma_addr_t free_rom_bus = 0;
1824         bool is_new_root;
1825
1826         reg = reg_read(ohci, OHCI1394_NodeID);
1827         if (!(reg & OHCI1394_NodeID_idValid)) {
1828                 dev_notice(ohci->card.device,
1829                            "node ID not valid, new bus reset in progress\n");
1830                 return;
1831         }
1832         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1833                 dev_notice(ohci->card.device, "malconfigured bus\n");
1834                 return;
1835         }
1836         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1837                                OHCI1394_NodeID_nodeNumber);
1838
1839         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1840         if (!(ohci->is_root && is_new_root))
1841                 reg_write(ohci, OHCI1394_LinkControlSet,
1842                           OHCI1394_LinkControl_cycleMaster);
1843         ohci->is_root = is_new_root;
1844
1845         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1846         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1847                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1848                 return;
1849         }
1850         /*
1851          * The count in the SelfIDCount register is the number of
1852          * bytes in the self ID receive buffer.  Since we also receive
1853          * the inverted quadlets and a header quadlet, we shift one
1854          * bit extra to get the actual number of self IDs.
1855          */
1856         self_id_count = (reg >> 3) & 0xff;
1857
1858         if (self_id_count > 252) {
1859                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1860                 return;
1861         }
1862
1863         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1864         rmb();
1865
1866         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1867                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1868                         /*
1869                          * If the invalid data looks like a cycle start packet,
1870                          * it's likely to be the result of the cycle master
1871                          * having a wrong gap count.  In this case, the self IDs
1872                          * so far are valid and should be processed so that the
1873                          * bus manager can then correct the gap count.
1874                          */
1875                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1876                                                         == 0xffff008f) {
1877                                 dev_notice(ohci->card.device,
1878                                            "ignoring spurious self IDs\n");
1879                                 self_id_count = j;
1880                                 break;
1881                         } else {
1882                                 dev_notice(ohci->card.device,
1883                                            "inconsistent self IDs\n");
1884                                 return;
1885                         }
1886                 }
1887                 ohci->self_id_buffer[j] =
1888                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1889         }
1890
1891         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1892                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1893                 if (self_id_count < 0) {
1894                         dev_notice(ohci->card.device,
1895                                    "could not construct local self ID\n");
1896                         return;
1897                 }
1898         }
1899
1900         if (self_id_count == 0) {
1901                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1902                 return;
1903         }
1904         rmb();
1905
1906         /*
1907          * Check the consistency of the self IDs we just read.  The
1908          * problem we face is that a new bus reset can start while we
1909          * read out the self IDs from the DMA buffer. If this happens,
1910          * the DMA buffer will be overwritten with new self IDs and we
1911          * will read out inconsistent data.  The OHCI specification
1912          * (section 11.2) recommends a technique similar to
1913          * linux/seqlock.h, where we remember the generation of the
1914          * self IDs in the buffer before reading them out and compare
1915          * it to the current generation after reading them out.  If
1916          * the two generations match we know we have a consistent set
1917          * of self IDs.
1918          */
1919
1920         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1921         if (new_generation != generation) {
1922                 dev_notice(ohci->card.device,
1923                            "new bus reset, discarding self ids\n");
1924                 return;
1925         }
1926
1927         /* FIXME: Document how the locking works. */
1928         spin_lock_irqsave(&ohci->lock, flags);
1929
1930         ohci->generation = -1; /* prevent AT packet queueing */
1931         context_stop(&ohci->at_request_ctx);
1932         context_stop(&ohci->at_response_ctx);
1933
1934         spin_unlock_irqrestore(&ohci->lock, flags);
1935
1936         /*
1937          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1938          * packets in the AT queues and software needs to drain them.
1939          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1940          */
1941         at_context_flush(&ohci->at_request_ctx);
1942         at_context_flush(&ohci->at_response_ctx);
1943
1944         spin_lock_irqsave(&ohci->lock, flags);
1945
1946         ohci->generation = generation;
1947         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1948
1949         if (ohci->quirks & QUIRK_RESET_PACKET)
1950                 ohci->request_generation = generation;
1951
1952         /*
1953          * This next bit is unrelated to the AT context stuff but we
1954          * have to do it under the spinlock also.  If a new config rom
1955          * was set up before this reset, the old one is now no longer
1956          * in use and we can free it. Update the config rom pointers
1957          * to point to the current config rom and clear the
1958          * next_config_rom pointer so a new update can take place.
1959          */
1960
1961         if (ohci->next_config_rom != NULL) {
1962                 if (ohci->next_config_rom != ohci->config_rom) {
1963                         free_rom      = ohci->config_rom;
1964                         free_rom_bus  = ohci->config_rom_bus;
1965                 }
1966                 ohci->config_rom      = ohci->next_config_rom;
1967                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1968                 ohci->next_config_rom = NULL;
1969
1970                 /*
1971                  * Restore config_rom image and manually update
1972                  * config_rom registers.  Writing the header quadlet
1973                  * will indicate that the config rom is ready, so we
1974                  * do that last.
1975                  */
1976                 reg_write(ohci, OHCI1394_BusOptions,
1977                           be32_to_cpu(ohci->config_rom[2]));
1978                 ohci->config_rom[0] = ohci->next_header;
1979                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1980                           be32_to_cpu(ohci->next_header));
1981         }
1982
1983 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1984         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1985         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1986 #endif
1987
1988         spin_unlock_irqrestore(&ohci->lock, flags);
1989
1990         if (free_rom)
1991                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1992                                   free_rom, free_rom_bus);
1993
1994         log_selfids(ohci, generation, self_id_count);
1995
1996         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1997                                  self_id_count, ohci->self_id_buffer,
1998                                  ohci->csr_state_setclear_abdicate);
1999         ohci->csr_state_setclear_abdicate = false;
2000 }
2001
2002 static irqreturn_t irq_handler(int irq, void *data)
2003 {
2004         struct fw_ohci *ohci = data;
2005         u32 event, iso_event;
2006         int i;
2007
2008         event = reg_read(ohci, OHCI1394_IntEventClear);
2009
2010         if (!event || !~event)
2011                 return IRQ_NONE;
2012
2013         /*
2014          * busReset and postedWriteErr must not be cleared yet
2015          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2016          */
2017         reg_write(ohci, OHCI1394_IntEventClear,
2018                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2019         log_irqs(ohci, event);
2020
2021         if (event & OHCI1394_selfIDComplete)
2022                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2023
2024         if (event & OHCI1394_RQPkt)
2025                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2026
2027         if (event & OHCI1394_RSPkt)
2028                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2029
2030         if (event & OHCI1394_reqTxComplete)
2031                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2032
2033         if (event & OHCI1394_respTxComplete)
2034                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2035
2036         if (event & OHCI1394_isochRx) {
2037                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2038                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2039
2040                 while (iso_event) {
2041                         i = ffs(iso_event) - 1;
2042                         tasklet_schedule(
2043                                 &ohci->ir_context_list[i].context.tasklet);
2044                         iso_event &= ~(1 << i);
2045                 }
2046         }
2047
2048         if (event & OHCI1394_isochTx) {
2049                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2050                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2051
2052                 while (iso_event) {
2053                         i = ffs(iso_event) - 1;
2054                         tasklet_schedule(
2055                                 &ohci->it_context_list[i].context.tasklet);
2056                         iso_event &= ~(1 << i);
2057                 }
2058         }
2059
2060         if (unlikely(event & OHCI1394_regAccessFail))
2061                 dev_err(ohci->card.device, "register access failure\n");
2062
2063         if (unlikely(event & OHCI1394_postedWriteErr)) {
2064                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2065                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2066                 reg_write(ohci, OHCI1394_IntEventClear,
2067                           OHCI1394_postedWriteErr);
2068                 if (printk_ratelimit())
2069                         dev_err(ohci->card.device, "PCI posted write error\n");
2070         }
2071
2072         if (unlikely(event & OHCI1394_cycleTooLong)) {
2073                 if (printk_ratelimit())
2074                         dev_notice(ohci->card.device,
2075                                    "isochronous cycle too long\n");
2076                 reg_write(ohci, OHCI1394_LinkControlSet,
2077                           OHCI1394_LinkControl_cycleMaster);
2078         }
2079
2080         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2081                 /*
2082                  * We need to clear this event bit in order to make
2083                  * cycleMatch isochronous I/O work.  In theory we should
2084                  * stop active cycleMatch iso contexts now and restart
2085                  * them at least two cycles later.  (FIXME?)
2086                  */
2087                 if (printk_ratelimit())
2088                         dev_notice(ohci->card.device,
2089                                    "isochronous cycle inconsistent\n");
2090         }
2091
2092         if (unlikely(event & OHCI1394_unrecoverableError))
2093                 handle_dead_contexts(ohci);
2094
2095         if (event & OHCI1394_cycle64Seconds) {
2096                 spin_lock(&ohci->lock);
2097                 update_bus_time(ohci);
2098                 spin_unlock(&ohci->lock);
2099         } else
2100                 flush_writes(ohci);
2101
2102         return IRQ_HANDLED;
2103 }
2104
2105 static int software_reset(struct fw_ohci *ohci)
2106 {
2107         u32 val;
2108         int i;
2109
2110         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2111         for (i = 0; i < 500; i++) {
2112                 val = reg_read(ohci, OHCI1394_HCControlSet);
2113                 if (!~val)
2114                         return -ENODEV; /* Card was ejected. */
2115
2116                 if (!(val & OHCI1394_HCControl_softReset))
2117                         return 0;
2118
2119                 msleep(1);
2120         }
2121
2122         return -EBUSY;
2123 }
2124
2125 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2126 {
2127         size_t size = length * 4;
2128
2129         memcpy(dest, src, size);
2130         if (size < CONFIG_ROM_SIZE)
2131                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2132 }
2133
2134 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2135 {
2136         bool enable_1394a;
2137         int ret, clear, set, offset;
2138
2139         /* Check if the driver should configure link and PHY. */
2140         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2141               OHCI1394_HCControl_programPhyEnable))
2142                 return 0;
2143
2144         /* Paranoia: check whether the PHY supports 1394a, too. */
2145         enable_1394a = false;
2146         ret = read_phy_reg(ohci, 2);
2147         if (ret < 0)
2148                 return ret;
2149         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2150                 ret = read_paged_phy_reg(ohci, 1, 8);
2151                 if (ret < 0)
2152                         return ret;
2153                 if (ret >= 1)
2154                         enable_1394a = true;
2155         }
2156
2157         if (ohci->quirks & QUIRK_NO_1394A)
2158                 enable_1394a = false;
2159
2160         /* Configure PHY and link consistently. */
2161         if (enable_1394a) {
2162                 clear = 0;
2163                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2164         } else {
2165                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2166                 set = 0;
2167         }
2168         ret = update_phy_reg(ohci, 5, clear, set);
2169         if (ret < 0)
2170                 return ret;
2171
2172         if (enable_1394a)
2173                 offset = OHCI1394_HCControlSet;
2174         else
2175                 offset = OHCI1394_HCControlClear;
2176         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2177
2178         /* Clean up: configuration has been taken care of. */
2179         reg_write(ohci, OHCI1394_HCControlClear,
2180                   OHCI1394_HCControl_programPhyEnable);
2181
2182         return 0;
2183 }
2184
2185 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2186 {
2187         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2188         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2189         int reg, i;
2190
2191         reg = read_phy_reg(ohci, 2);
2192         if (reg < 0)
2193                 return reg;
2194         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2195                 return 0;
2196
2197         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2198                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2199                 if (reg < 0)
2200                         return reg;
2201                 if (reg != id[i])
2202                         return 0;
2203         }
2204         return 1;
2205 }
2206
2207 static int ohci_enable(struct fw_card *card,
2208                        const __be32 *config_rom, size_t length)
2209 {
2210         struct fw_ohci *ohci = fw_ohci(card);
2211         struct pci_dev *dev = to_pci_dev(card->device);
2212         u32 lps, seconds, version, irqs;
2213         int i, ret;
2214
2215         if (software_reset(ohci)) {
2216                 dev_err(card->device, "failed to reset ohci card\n");
2217                 return -EBUSY;
2218         }
2219
2220         /*
2221          * Now enable LPS, which we need in order to start accessing
2222          * most of the registers.  In fact, on some cards (ALI M5251),
2223          * accessing registers in the SClk domain without LPS enabled
2224          * will lock up the machine.  Wait 50msec to make sure we have
2225          * full link enabled.  However, with some cards (well, at least
2226          * a JMicron PCIe card), we have to try again sometimes.
2227          */
2228         reg_write(ohci, OHCI1394_HCControlSet,
2229                   OHCI1394_HCControl_LPS |
2230                   OHCI1394_HCControl_postedWriteEnable);
2231         flush_writes(ohci);
2232
2233         for (lps = 0, i = 0; !lps && i < 3; i++) {
2234                 msleep(50);
2235                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2236                       OHCI1394_HCControl_LPS;
2237         }
2238
2239         if (!lps) {
2240                 dev_err(card->device, "failed to set Link Power Status\n");
2241                 return -EIO;
2242         }
2243
2244         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2245                 ret = probe_tsb41ba3d(ohci);
2246                 if (ret < 0)
2247                         return ret;
2248                 if (ret)
2249                         dev_notice(card->device, "local TSB41BA3D phy\n");
2250                 else
2251                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2252         }
2253
2254         reg_write(ohci, OHCI1394_HCControlClear,
2255                   OHCI1394_HCControl_noByteSwapData);
2256
2257         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2258         reg_write(ohci, OHCI1394_LinkControlSet,
2259                   OHCI1394_LinkControl_cycleTimerEnable |
2260                   OHCI1394_LinkControl_cycleMaster);
2261
2262         reg_write(ohci, OHCI1394_ATRetries,
2263                   OHCI1394_MAX_AT_REQ_RETRIES |
2264                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2265                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2266                   (200 << 16));
2267
2268         seconds = lower_32_bits(get_seconds());
2269         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2270         ohci->bus_time = seconds & ~0x3f;
2271
2272         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2273         if (version >= OHCI_VERSION_1_1) {
2274                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2275                           0xfffffffe);
2276                 card->broadcast_channel_auto_allocated = true;
2277         }
2278
2279         /* Get implemented bits of the priority arbitration request counter. */
2280         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2281         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2282         reg_write(ohci, OHCI1394_FairnessControl, 0);
2283         card->priority_budget_implemented = ohci->pri_req_max != 0;
2284
2285         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2286         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2287         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2288
2289         ret = configure_1394a_enhancements(ohci);
2290         if (ret < 0)
2291                 return ret;
2292
2293         /* Activate link_on bit and contender bit in our self ID packets.*/
2294         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2295         if (ret < 0)
2296                 return ret;
2297
2298         /*
2299          * When the link is not yet enabled, the atomic config rom
2300          * update mechanism described below in ohci_set_config_rom()
2301          * is not active.  We have to update ConfigRomHeader and
2302          * BusOptions manually, and the write to ConfigROMmap takes
2303          * effect immediately.  We tie this to the enabling of the
2304          * link, so we have a valid config rom before enabling - the
2305          * OHCI requires that ConfigROMhdr and BusOptions have valid
2306          * values before enabling.
2307          *
2308          * However, when the ConfigROMmap is written, some controllers
2309          * always read back quadlets 0 and 2 from the config rom to
2310          * the ConfigRomHeader and BusOptions registers on bus reset.
2311          * They shouldn't do that in this initial case where the link
2312          * isn't enabled.  This means we have to use the same
2313          * workaround here, setting the bus header to 0 and then write
2314          * the right values in the bus reset tasklet.
2315          */
2316
2317         if (config_rom) {
2318                 ohci->next_config_rom =
2319                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2320                                            &ohci->next_config_rom_bus,
2321                                            GFP_KERNEL);
2322                 if (ohci->next_config_rom == NULL)
2323                         return -ENOMEM;
2324
2325                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2326         } else {
2327                 /*
2328                  * In the suspend case, config_rom is NULL, which
2329                  * means that we just reuse the old config rom.
2330                  */
2331                 ohci->next_config_rom = ohci->config_rom;
2332                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2333         }
2334
2335         ohci->next_header = ohci->next_config_rom[0];
2336         ohci->next_config_rom[0] = 0;
2337         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2338         reg_write(ohci, OHCI1394_BusOptions,
2339                   be32_to_cpu(ohci->next_config_rom[2]));
2340         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2341
2342         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2343
2344         if (!(ohci->quirks & QUIRK_NO_MSI))
2345                 pci_enable_msi(dev);
2346         if (request_irq(dev->irq, irq_handler,
2347                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2348                         ohci_driver_name, ohci)) {
2349                 dev_err(card->device, "failed to allocate interrupt %d\n",
2350                         dev->irq);
2351                 pci_disable_msi(dev);
2352
2353                 if (config_rom) {
2354                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2355                                           ohci->next_config_rom,
2356                                           ohci->next_config_rom_bus);
2357                         ohci->next_config_rom = NULL;
2358                 }
2359                 return -EIO;
2360         }
2361
2362         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2363                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2364                 OHCI1394_isochTx | OHCI1394_isochRx |
2365                 OHCI1394_postedWriteErr |
2366                 OHCI1394_selfIDComplete |
2367                 OHCI1394_regAccessFail |
2368                 OHCI1394_cycle64Seconds |
2369                 OHCI1394_cycleInconsistent |
2370                 OHCI1394_unrecoverableError |
2371                 OHCI1394_cycleTooLong |
2372                 OHCI1394_masterIntEnable;
2373         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2374                 irqs |= OHCI1394_busReset;
2375         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2376
2377         reg_write(ohci, OHCI1394_HCControlSet,
2378                   OHCI1394_HCControl_linkEnable |
2379                   OHCI1394_HCControl_BIBimageValid);
2380
2381         reg_write(ohci, OHCI1394_LinkControlSet,
2382                   OHCI1394_LinkControl_rcvSelfID |
2383                   OHCI1394_LinkControl_rcvPhyPkt);
2384
2385         ar_context_run(&ohci->ar_request_ctx);
2386         ar_context_run(&ohci->ar_response_ctx);
2387
2388         flush_writes(ohci);
2389
2390         /* We are ready to go, reset bus to finish initialization. */
2391         fw_schedule_bus_reset(&ohci->card, false, true);
2392
2393         return 0;
2394 }
2395
2396 static int ohci_set_config_rom(struct fw_card *card,
2397                                const __be32 *config_rom, size_t length)
2398 {
2399         struct fw_ohci *ohci;
2400         unsigned long flags;
2401         __be32 *next_config_rom;
2402         dma_addr_t uninitialized_var(next_config_rom_bus);
2403
2404         ohci = fw_ohci(card);
2405
2406         /*
2407          * When the OHCI controller is enabled, the config rom update
2408          * mechanism is a bit tricky, but easy enough to use.  See
2409          * section 5.5.6 in the OHCI specification.
2410          *
2411          * The OHCI controller caches the new config rom address in a
2412          * shadow register (ConfigROMmapNext) and needs a bus reset
2413          * for the changes to take place.  When the bus reset is
2414          * detected, the controller loads the new values for the
2415          * ConfigRomHeader and BusOptions registers from the specified
2416          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2417          * shadow register. All automatically and atomically.
2418          *
2419          * Now, there's a twist to this story.  The automatic load of
2420          * ConfigRomHeader and BusOptions doesn't honor the
2421          * noByteSwapData bit, so with a be32 config rom, the
2422          * controller will load be32 values in to these registers
2423          * during the atomic update, even on litte endian
2424          * architectures.  The workaround we use is to put a 0 in the
2425          * header quadlet; 0 is endian agnostic and means that the
2426          * config rom isn't ready yet.  In the bus reset tasklet we
2427          * then set up the real values for the two registers.
2428          *
2429          * We use ohci->lock to avoid racing with the code that sets
2430          * ohci->next_config_rom to NULL (see bus_reset_work).
2431          */
2432
2433         next_config_rom =
2434                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2435                                    &next_config_rom_bus, GFP_KERNEL);
2436         if (next_config_rom == NULL)
2437                 return -ENOMEM;
2438
2439         spin_lock_irqsave(&ohci->lock, flags);
2440
2441         /*
2442          * If there is not an already pending config_rom update,
2443          * push our new allocation into the ohci->next_config_rom
2444          * and then mark the local variable as null so that we
2445          * won't deallocate the new buffer.
2446          *
2447          * OTOH, if there is a pending config_rom update, just
2448          * use that buffer with the new config_rom data, and
2449          * let this routine free the unused DMA allocation.
2450          */
2451
2452         if (ohci->next_config_rom == NULL) {
2453                 ohci->next_config_rom = next_config_rom;
2454                 ohci->next_config_rom_bus = next_config_rom_bus;
2455                 next_config_rom = NULL;
2456         }
2457
2458         copy_config_rom(ohci->next_config_rom, config_rom, length);
2459
2460         ohci->next_header = config_rom[0];
2461         ohci->next_config_rom[0] = 0;
2462
2463         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2464
2465         spin_unlock_irqrestore(&ohci->lock, flags);
2466
2467         /* If we didn't use the DMA allocation, delete it. */
2468         if (next_config_rom != NULL)
2469                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2470                                   next_config_rom, next_config_rom_bus);
2471
2472         /*
2473          * Now initiate a bus reset to have the changes take
2474          * effect. We clean up the old config rom memory and DMA
2475          * mappings in the bus reset tasklet, since the OHCI
2476          * controller could need to access it before the bus reset
2477          * takes effect.
2478          */
2479
2480         fw_schedule_bus_reset(&ohci->card, true, true);
2481
2482         return 0;
2483 }
2484
2485 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2486 {
2487         struct fw_ohci *ohci = fw_ohci(card);
2488
2489         at_context_transmit(&ohci->at_request_ctx, packet);
2490 }
2491
2492 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2493 {
2494         struct fw_ohci *ohci = fw_ohci(card);
2495
2496         at_context_transmit(&ohci->at_response_ctx, packet);
2497 }
2498
2499 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2500 {
2501         struct fw_ohci *ohci = fw_ohci(card);
2502         struct context *ctx = &ohci->at_request_ctx;
2503         struct driver_data *driver_data = packet->driver_data;
2504         int ret = -ENOENT;
2505
2506         tasklet_disable(&ctx->tasklet);
2507
2508         if (packet->ack != 0)
2509                 goto out;
2510
2511         if (packet->payload_mapped)
2512                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2513                                  packet->payload_length, DMA_TO_DEVICE);
2514
2515         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2516         driver_data->packet = NULL;
2517         packet->ack = RCODE_CANCELLED;
2518         packet->callback(packet, &ohci->card, packet->ack);
2519         ret = 0;
2520  out:
2521         tasklet_enable(&ctx->tasklet);
2522
2523         return ret;
2524 }
2525
2526 static int ohci_enable_phys_dma(struct fw_card *card,
2527                                 int node_id, int generation)
2528 {
2529 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2530         return 0;
2531 #else
2532         struct fw_ohci *ohci = fw_ohci(card);
2533         unsigned long flags;
2534         int n, ret = 0;
2535
2536         /*
2537          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2538          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2539          */
2540
2541         spin_lock_irqsave(&ohci->lock, flags);
2542
2543         if (ohci->generation != generation) {
2544                 ret = -ESTALE;
2545                 goto out;
2546         }
2547
2548         /*
2549          * Note, if the node ID contains a non-local bus ID, physical DMA is
2550          * enabled for _all_ nodes on remote buses.
2551          */
2552
2553         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2554         if (n < 32)
2555                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2556         else
2557                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2558
2559         flush_writes(ohci);
2560  out:
2561         spin_unlock_irqrestore(&ohci->lock, flags);
2562
2563         return ret;
2564 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2565 }
2566
2567 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2568 {
2569         struct fw_ohci *ohci = fw_ohci(card);
2570         unsigned long flags;
2571         u32 value;
2572
2573         switch (csr_offset) {
2574         case CSR_STATE_CLEAR:
2575         case CSR_STATE_SET:
2576                 if (ohci->is_root &&
2577                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2578                      OHCI1394_LinkControl_cycleMaster))
2579                         value = CSR_STATE_BIT_CMSTR;
2580                 else
2581                         value = 0;
2582                 if (ohci->csr_state_setclear_abdicate)
2583                         value |= CSR_STATE_BIT_ABDICATE;
2584
2585                 return value;
2586
2587         case CSR_NODE_IDS:
2588                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2589
2590         case CSR_CYCLE_TIME:
2591                 return get_cycle_time(ohci);
2592
2593         case CSR_BUS_TIME:
2594                 /*
2595                  * We might be called just after the cycle timer has wrapped
2596                  * around but just before the cycle64Seconds handler, so we
2597                  * better check here, too, if the bus time needs to be updated.
2598                  */
2599                 spin_lock_irqsave(&ohci->lock, flags);
2600                 value = update_bus_time(ohci);
2601                 spin_unlock_irqrestore(&ohci->lock, flags);
2602                 return value;
2603
2604         case CSR_BUSY_TIMEOUT:
2605                 value = reg_read(ohci, OHCI1394_ATRetries);
2606                 return (value >> 4) & 0x0ffff00f;
2607
2608         case CSR_PRIORITY_BUDGET:
2609                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2610                         (ohci->pri_req_max << 8);
2611
2612         default:
2613                 WARN_ON(1);
2614                 return 0;
2615         }
2616 }
2617
2618 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2619 {
2620         struct fw_ohci *ohci = fw_ohci(card);
2621         unsigned long flags;
2622
2623         switch (csr_offset) {
2624         case CSR_STATE_CLEAR:
2625                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2626                         reg_write(ohci, OHCI1394_LinkControlClear,
2627                                   OHCI1394_LinkControl_cycleMaster);
2628                         flush_writes(ohci);
2629                 }
2630                 if (value & CSR_STATE_BIT_ABDICATE)
2631                         ohci->csr_state_setclear_abdicate = false;
2632                 break;
2633
2634         case CSR_STATE_SET:
2635                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2636                         reg_write(ohci, OHCI1394_LinkControlSet,
2637                                   OHCI1394_LinkControl_cycleMaster);
2638                         flush_writes(ohci);
2639                 }
2640                 if (value & CSR_STATE_BIT_ABDICATE)
2641                         ohci->csr_state_setclear_abdicate = true;
2642                 break;
2643
2644         case CSR_NODE_IDS:
2645                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2646                 flush_writes(ohci);
2647                 break;
2648
2649         case CSR_CYCLE_TIME:
2650                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2651                 reg_write(ohci, OHCI1394_IntEventSet,
2652                           OHCI1394_cycleInconsistent);
2653                 flush_writes(ohci);
2654                 break;
2655
2656         case CSR_BUS_TIME:
2657                 spin_lock_irqsave(&ohci->lock, flags);
2658                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2659                 spin_unlock_irqrestore(&ohci->lock, flags);
2660                 break;
2661
2662         case CSR_BUSY_TIMEOUT:
2663                 value = (value & 0xf) | ((value & 0xf) << 4) |
2664                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2665                 reg_write(ohci, OHCI1394_ATRetries, value);
2666                 flush_writes(ohci);
2667                 break;
2668
2669         case CSR_PRIORITY_BUDGET:
2670                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2671                 flush_writes(ohci);
2672                 break;
2673
2674         default:
2675                 WARN_ON(1);
2676                 break;
2677         }
2678 }
2679
2680 static void copy_iso_headers(struct iso_context *ctx, void *p)
2681 {
2682         int i = ctx->header_length;
2683
2684         if (i + ctx->base.header_size > PAGE_SIZE)
2685                 return;
2686
2687         /*
2688          * The iso header is byteswapped to little endian by
2689          * the controller, but the remaining header quadlets
2690          * are big endian.  We want to present all the headers
2691          * as big endian, so we have to swap the first quadlet.
2692          */
2693         if (ctx->base.header_size > 0)
2694                 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2695         if (ctx->base.header_size > 4)
2696                 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2697         if (ctx->base.header_size > 8)
2698                 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2699         ctx->header_length += ctx->base.header_size;
2700 }
2701
2702 static int handle_ir_packet_per_buffer(struct context *context,
2703                                        struct descriptor *d,
2704                                        struct descriptor *last)
2705 {
2706         struct iso_context *ctx =
2707                 container_of(context, struct iso_context, context);
2708         struct descriptor *pd;
2709         u32 buffer_dma;
2710         __le32 *ir_header;
2711         void *p;
2712
2713         for (pd = d; pd <= last; pd++)
2714                 if (pd->transfer_status)
2715                         break;
2716         if (pd > last)
2717                 /* Descriptor(s) not done yet, stop iteration */
2718                 return 0;
2719
2720         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2721                 d++;
2722                 buffer_dma = le32_to_cpu(d->data_address);
2723                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2724                                               buffer_dma & PAGE_MASK,
2725                                               buffer_dma & ~PAGE_MASK,
2726                                               le16_to_cpu(d->req_count),
2727                                               DMA_FROM_DEVICE);
2728         }
2729
2730         p = last + 1;
2731         copy_iso_headers(ctx, p);
2732
2733         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2734                 ir_header = (__le32 *) p;
2735                 ctx->base.callback.sc(&ctx->base,
2736                                       le32_to_cpu(ir_header[0]) & 0xffff,
2737                                       ctx->header_length, ctx->header,
2738                                       ctx->base.callback_data);
2739                 ctx->header_length = 0;
2740         }
2741
2742         return 1;
2743 }
2744
2745 /* d == last because each descriptor block is only a single descriptor. */
2746 static int handle_ir_buffer_fill(struct context *context,
2747                                  struct descriptor *d,
2748                                  struct descriptor *last)
2749 {
2750         struct iso_context *ctx =
2751                 container_of(context, struct iso_context, context);
2752         u32 buffer_dma;
2753
2754         if (!last->transfer_status)
2755                 /* Descriptor(s) not done yet, stop iteration */
2756                 return 0;
2757
2758         buffer_dma = le32_to_cpu(last->data_address);
2759         dma_sync_single_range_for_cpu(context->ohci->card.device,
2760                                       buffer_dma & PAGE_MASK,
2761                                       buffer_dma & ~PAGE_MASK,
2762                                       le16_to_cpu(last->req_count),
2763                                       DMA_FROM_DEVICE);
2764
2765         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2766                 ctx->base.callback.mc(&ctx->base,
2767                                       le32_to_cpu(last->data_address) +
2768                                       le16_to_cpu(last->req_count) -
2769                                       le16_to_cpu(last->res_count),
2770                                       ctx->base.callback_data);
2771
2772         return 1;
2773 }
2774
2775 static inline void sync_it_packet_for_cpu(struct context *context,
2776                                           struct descriptor *pd)
2777 {
2778         __le16 control;
2779         u32 buffer_dma;
2780
2781         /* only packets beginning with OUTPUT_MORE* have data buffers */
2782         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2783                 return;
2784
2785         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2786         pd += 2;
2787
2788         /*
2789          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2790          * data buffer is in the context program's coherent page and must not
2791          * be synced.
2792          */
2793         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2794             (context->current_bus          & PAGE_MASK)) {
2795                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2796                         return;
2797                 pd++;
2798         }
2799
2800         do {
2801                 buffer_dma = le32_to_cpu(pd->data_address);
2802                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2803                                               buffer_dma & PAGE_MASK,
2804                                               buffer_dma & ~PAGE_MASK,
2805                                               le16_to_cpu(pd->req_count),
2806                                               DMA_TO_DEVICE);
2807                 control = pd->control;
2808                 pd++;
2809         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2810 }
2811
2812 static int handle_it_packet(struct context *context,
2813                             struct descriptor *d,
2814                             struct descriptor *last)
2815 {
2816         struct iso_context *ctx =
2817                 container_of(context, struct iso_context, context);
2818         int i;
2819         struct descriptor *pd;
2820
2821         for (pd = d; pd <= last; pd++)
2822                 if (pd->transfer_status)
2823                         break;
2824         if (pd > last)
2825                 /* Descriptor(s) not done yet, stop iteration */
2826                 return 0;
2827
2828         sync_it_packet_for_cpu(context, d);
2829
2830         i = ctx->header_length;
2831         if (i + 4 < PAGE_SIZE) {
2832                 /* Present this value as big-endian to match the receive code */
2833                 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2834                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2835                                 le16_to_cpu(pd->res_count));
2836                 ctx->header_length += 4;
2837         }
2838         if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2839                 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2840                                       ctx->header_length, ctx->header,
2841                                       ctx->base.callback_data);
2842                 ctx->header_length = 0;
2843         }
2844         return 1;
2845 }
2846
2847 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2848 {
2849         u32 hi = channels >> 32, lo = channels;
2850
2851         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2852         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2853         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2854         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2855         mmiowb();
2856         ohci->mc_channels = channels;
2857 }
2858
2859 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2860                                 int type, int channel, size_t header_size)
2861 {
2862         struct fw_ohci *ohci = fw_ohci(card);
2863         struct iso_context *uninitialized_var(ctx);
2864         descriptor_callback_t uninitialized_var(callback);
2865         u64 *uninitialized_var(channels);
2866         u32 *uninitialized_var(mask), uninitialized_var(regs);
2867         unsigned long flags;
2868         int index, ret = -EBUSY;
2869
2870         spin_lock_irqsave(&ohci->lock, flags);
2871
2872         switch (type) {
2873         case FW_ISO_CONTEXT_TRANSMIT:
2874                 mask     = &ohci->it_context_mask;
2875                 callback = handle_it_packet;
2876                 index    = ffs(*mask) - 1;
2877                 if (index >= 0) {
2878                         *mask &= ~(1 << index);
2879                         regs = OHCI1394_IsoXmitContextBase(index);
2880                         ctx  = &ohci->it_context_list[index];
2881                 }
2882                 break;
2883
2884         case FW_ISO_CONTEXT_RECEIVE:
2885                 channels = &ohci->ir_context_channels;
2886                 mask     = &ohci->ir_context_mask;
2887                 callback = handle_ir_packet_per_buffer;
2888                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2889                 if (index >= 0) {
2890                         *channels &= ~(1ULL << channel);
2891                         *mask     &= ~(1 << index);
2892                         regs = OHCI1394_IsoRcvContextBase(index);
2893                         ctx  = &ohci->ir_context_list[index];
2894                 }
2895                 break;
2896
2897         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2898                 mask     = &ohci->ir_context_mask;
2899                 callback = handle_ir_buffer_fill;
2900                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2901                 if (index >= 0) {
2902                         ohci->mc_allocated = true;
2903                         *mask &= ~(1 << index);
2904                         regs = OHCI1394_IsoRcvContextBase(index);
2905                         ctx  = &ohci->ir_context_list[index];
2906                 }
2907                 break;
2908
2909         default:
2910                 index = -1;
2911                 ret = -ENOSYS;
2912         }
2913
2914         spin_unlock_irqrestore(&ohci->lock, flags);
2915
2916         if (index < 0)
2917                 return ERR_PTR(ret);
2918
2919         memset(ctx, 0, sizeof(*ctx));
2920         ctx->header_length = 0;
2921         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2922         if (ctx->header == NULL) {
2923                 ret = -ENOMEM;
2924                 goto out;
2925         }
2926         ret = context_init(&ctx->context, ohci, regs, callback);
2927         if (ret < 0)
2928                 goto out_with_header;
2929
2930         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2931                 set_multichannel_mask(ohci, 0);
2932
2933         return &ctx->base;
2934
2935  out_with_header:
2936         free_page((unsigned long)ctx->header);
2937  out:
2938         spin_lock_irqsave(&ohci->lock, flags);
2939
2940         switch (type) {
2941         case FW_ISO_CONTEXT_RECEIVE:
2942                 *channels |= 1ULL << channel;
2943                 break;
2944
2945         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2946                 ohci->mc_allocated = false;
2947                 break;
2948         }
2949         *mask |= 1 << index;
2950
2951         spin_unlock_irqrestore(&ohci->lock, flags);
2952
2953         return ERR_PTR(ret);
2954 }
2955
2956 static int ohci_start_iso(struct fw_iso_context *base,
2957                           s32 cycle, u32 sync, u32 tags)
2958 {
2959         struct iso_context *ctx = container_of(base, struct iso_context, base);
2960         struct fw_ohci *ohci = ctx->context.ohci;
2961         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2962         int index;
2963
2964         /* the controller cannot start without any queued packets */
2965         if (ctx->context.last->branch_address == 0)
2966                 return -ENODATA;
2967
2968         switch (ctx->base.type) {
2969         case FW_ISO_CONTEXT_TRANSMIT:
2970                 index = ctx - ohci->it_context_list;
2971                 match = 0;
2972                 if (cycle >= 0)
2973                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2974                                 (cycle & 0x7fff) << 16;
2975
2976                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2977                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2978                 context_run(&ctx->context, match);
2979                 break;
2980
2981         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2982                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2983                 /* fall through */
2984         case FW_ISO_CONTEXT_RECEIVE:
2985                 index = ctx - ohci->ir_context_list;
2986                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2987                 if (cycle >= 0) {
2988                         match |= (cycle & 0x07fff) << 12;
2989                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2990                 }
2991
2992                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2993                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2994                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2995                 context_run(&ctx->context, control);
2996
2997                 ctx->sync = sync;
2998                 ctx->tags = tags;
2999
3000                 break;
3001         }
3002
3003         return 0;
3004 }
3005
3006 static int ohci_stop_iso(struct fw_iso_context *base)
3007 {
3008         struct fw_ohci *ohci = fw_ohci(base->card);
3009         struct iso_context *ctx = container_of(base, struct iso_context, base);
3010         int index;
3011
3012         switch (ctx->base.type) {
3013         case FW_ISO_CONTEXT_TRANSMIT:
3014                 index = ctx - ohci->it_context_list;
3015                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3016                 break;
3017
3018         case FW_ISO_CONTEXT_RECEIVE:
3019         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3020                 index = ctx - ohci->ir_context_list;
3021                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3022                 break;
3023         }
3024         flush_writes(ohci);
3025         context_stop(&ctx->context);
3026         tasklet_kill(&ctx->context.tasklet);
3027
3028         return 0;
3029 }
3030
3031 static void ohci_free_iso_context(struct fw_iso_context *base)
3032 {
3033         struct fw_ohci *ohci = fw_ohci(base->card);
3034         struct iso_context *ctx = container_of(base, struct iso_context, base);
3035         unsigned long flags;
3036         int index;
3037
3038         ohci_stop_iso(base);
3039         context_release(&ctx->context);
3040         free_page((unsigned long)ctx->header);
3041
3042         spin_lock_irqsave(&ohci->lock, flags);
3043
3044         switch (base->type) {
3045         case FW_ISO_CONTEXT_TRANSMIT:
3046                 index = ctx - ohci->it_context_list;
3047                 ohci->it_context_mask |= 1 << index;
3048                 break;
3049
3050         case FW_ISO_CONTEXT_RECEIVE:
3051                 index = ctx - ohci->ir_context_list;
3052                 ohci->ir_context_mask |= 1 << index;
3053                 ohci->ir_context_channels |= 1ULL << base->channel;
3054                 break;
3055
3056         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3057                 index = ctx - ohci->ir_context_list;
3058                 ohci->ir_context_mask |= 1 << index;
3059                 ohci->ir_context_channels |= ohci->mc_channels;
3060                 ohci->mc_channels = 0;
3061                 ohci->mc_allocated = false;
3062                 break;
3063         }
3064
3065         spin_unlock_irqrestore(&ohci->lock, flags);
3066 }
3067
3068 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3069 {
3070         struct fw_ohci *ohci = fw_ohci(base->card);
3071         unsigned long flags;
3072         int ret;
3073
3074         switch (base->type) {
3075         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3076
3077                 spin_lock_irqsave(&ohci->lock, flags);
3078
3079                 /* Don't allow multichannel to grab other contexts' channels. */
3080                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3081                         *channels = ohci->ir_context_channels;
3082                         ret = -EBUSY;
3083                 } else {
3084                         set_multichannel_mask(ohci, *channels);
3085                         ret = 0;
3086                 }
3087
3088                 spin_unlock_irqrestore(&ohci->lock, flags);
3089
3090                 break;
3091         default:
3092                 ret = -EINVAL;
3093         }
3094
3095         return ret;
3096 }
3097
3098 #ifdef CONFIG_PM
3099 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3100 {
3101         int i;
3102         struct iso_context *ctx;
3103
3104         for (i = 0 ; i < ohci->n_ir ; i++) {
3105                 ctx = &ohci->ir_context_list[i];
3106                 if (ctx->context.running)
3107                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3108         }
3109
3110         for (i = 0 ; i < ohci->n_it ; i++) {
3111                 ctx = &ohci->it_context_list[i];
3112                 if (ctx->context.running)
3113                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3114         }
3115 }
3116 #endif
3117
3118 static int queue_iso_transmit(struct iso_context *ctx,
3119                               struct fw_iso_packet *packet,
3120                               struct fw_iso_buffer *buffer,
3121                               unsigned long payload)
3122 {
3123         struct descriptor *d, *last, *pd;
3124         struct fw_iso_packet *p;
3125         __le32 *header;
3126         dma_addr_t d_bus, page_bus;
3127         u32 z, header_z, payload_z, irq;
3128         u32 payload_index, payload_end_index, next_page_index;
3129         int page, end_page, i, length, offset;
3130
3131         p = packet;
3132         payload_index = payload;
3133
3134         if (p->skip)
3135                 z = 1;
3136         else
3137                 z = 2;
3138         if (p->header_length > 0)
3139                 z++;
3140
3141         /* Determine the first page the payload isn't contained in. */
3142         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3143         if (p->payload_length > 0)
3144                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3145         else
3146                 payload_z = 0;
3147
3148         z += payload_z;
3149
3150         /* Get header size in number of descriptors. */
3151         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3152
3153         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3154         if (d == NULL)
3155                 return -ENOMEM;
3156
3157         if (!p->skip) {
3158                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3159                 d[0].req_count = cpu_to_le16(8);
3160                 /*
3161                  * Link the skip address to this descriptor itself.  This causes
3162                  * a context to skip a cycle whenever lost cycles or FIFO
3163                  * overruns occur, without dropping the data.  The application
3164                  * should then decide whether this is an error condition or not.
3165                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3166                  */
3167                 d[0].branch_address = cpu_to_le32(d_bus | z);
3168
3169                 header = (__le32 *) &d[1];
3170                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3171                                         IT_HEADER_TAG(p->tag) |
3172                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3173                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3174                                         IT_HEADER_SPEED(ctx->base.speed));
3175                 header[1] =
3176                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3177                                                           p->payload_length));
3178         }
3179
3180         if (p->header_length > 0) {
3181                 d[2].req_count    = cpu_to_le16(p->header_length);
3182                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3183                 memcpy(&d[z], p->header, p->header_length);
3184         }
3185
3186         pd = d + z - payload_z;
3187         payload_end_index = payload_index + p->payload_length;
3188         for (i = 0; i < payload_z; i++) {
3189                 page               = payload_index >> PAGE_SHIFT;
3190                 offset             = payload_index & ~PAGE_MASK;
3191                 next_page_index    = (page + 1) << PAGE_SHIFT;
3192                 length             =
3193                         min(next_page_index, payload_end_index) - payload_index;
3194                 pd[i].req_count    = cpu_to_le16(length);
3195
3196                 page_bus = page_private(buffer->pages[page]);
3197                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3198
3199                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3200                                                  page_bus, offset, length,
3201                                                  DMA_TO_DEVICE);
3202
3203                 payload_index += length;
3204         }
3205
3206         if (p->interrupt)
3207                 irq = DESCRIPTOR_IRQ_ALWAYS;
3208         else
3209                 irq = DESCRIPTOR_NO_IRQ;
3210
3211         last = z == 2 ? d : d + z - 1;
3212         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3213                                      DESCRIPTOR_STATUS |
3214                                      DESCRIPTOR_BRANCH_ALWAYS |
3215                                      irq);
3216
3217         context_append(&ctx->context, d, z, header_z);
3218
3219         return 0;
3220 }
3221
3222 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3223                                        struct fw_iso_packet *packet,
3224                                        struct fw_iso_buffer *buffer,
3225                                        unsigned long payload)
3226 {
3227         struct device *device = ctx->context.ohci->card.device;
3228         struct descriptor *d, *pd;
3229         dma_addr_t d_bus, page_bus;
3230         u32 z, header_z, rest;
3231         int i, j, length;
3232         int page, offset, packet_count, header_size, payload_per_buffer;
3233
3234         /*
3235          * The OHCI controller puts the isochronous header and trailer in the
3236          * buffer, so we need at least 8 bytes.
3237          */
3238         packet_count = packet->header_length / ctx->base.header_size;
3239         header_size  = max(ctx->base.header_size, (size_t)8);
3240
3241         /* Get header size in number of descriptors. */
3242         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3243         page     = payload >> PAGE_SHIFT;
3244         offset   = payload & ~PAGE_MASK;
3245         payload_per_buffer = packet->payload_length / packet_count;
3246
3247         for (i = 0; i < packet_count; i++) {
3248                 /* d points to the header descriptor */
3249                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3250                 d = context_get_descriptors(&ctx->context,
3251                                 z + header_z, &d_bus);
3252                 if (d == NULL)
3253                         return -ENOMEM;
3254
3255                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3256                                               DESCRIPTOR_INPUT_MORE);
3257                 if (packet->skip && i == 0)
3258                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3259                 d->req_count    = cpu_to_le16(header_size);
3260                 d->res_count    = d->req_count;
3261                 d->transfer_status = 0;
3262                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3263
3264                 rest = payload_per_buffer;
3265                 pd = d;
3266                 for (j = 1; j < z; j++) {
3267                         pd++;
3268                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3269                                                   DESCRIPTOR_INPUT_MORE);
3270
3271                         if (offset + rest < PAGE_SIZE)
3272                                 length = rest;
3273                         else
3274                                 length = PAGE_SIZE - offset;
3275                         pd->req_count = cpu_to_le16(length);
3276                         pd->res_count = pd->req_count;
3277                         pd->transfer_status = 0;
3278
3279                         page_bus = page_private(buffer->pages[page]);
3280                         pd->data_address = cpu_to_le32(page_bus + offset);
3281
3282                         dma_sync_single_range_for_device(device, page_bus,
3283                                                          offset, length,
3284                                                          DMA_FROM_DEVICE);
3285
3286                         offset = (offset + length) & ~PAGE_MASK;
3287                         rest -= length;
3288                         if (offset == 0)
3289                                 page++;
3290                 }
3291                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3292                                           DESCRIPTOR_INPUT_LAST |
3293                                           DESCRIPTOR_BRANCH_ALWAYS);
3294                 if (packet->interrupt && i == packet_count - 1)
3295                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3296
3297                 context_append(&ctx->context, d, z, header_z);
3298         }
3299
3300         return 0;
3301 }
3302
3303 static int queue_iso_buffer_fill(struct iso_context *ctx,
3304                                  struct fw_iso_packet *packet,
3305                                  struct fw_iso_buffer *buffer,
3306                                  unsigned long payload)
3307 {
3308         struct descriptor *d;
3309         dma_addr_t d_bus, page_bus;
3310         int page, offset, rest, z, i, length;
3311
3312         page   = payload >> PAGE_SHIFT;
3313         offset = payload & ~PAGE_MASK;
3314         rest   = packet->payload_length;
3315
3316         /* We need one descriptor for each page in the buffer. */
3317         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3318
3319         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3320                 return -EFAULT;
3321
3322         for (i = 0; i < z; i++) {
3323                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3324                 if (d == NULL)
3325                         return -ENOMEM;
3326
3327                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3328                                          DESCRIPTOR_BRANCH_ALWAYS);
3329                 if (packet->skip && i == 0)
3330                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3331                 if (packet->interrupt && i == z - 1)
3332                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3333
3334                 if (offset + rest < PAGE_SIZE)
3335                         length = rest;
3336                 else
3337                         length = PAGE_SIZE - offset;
3338                 d->req_count = cpu_to_le16(length);
3339                 d->res_count = d->req_count;
3340                 d->transfer_status = 0;
3341
3342                 page_bus = page_private(buffer->pages[page]);
3343                 d->data_address = cpu_to_le32(page_bus + offset);
3344
3345                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3346                                                  page_bus, offset, length,
3347                                                  DMA_FROM_DEVICE);
3348
3349                 rest -= length;
3350                 offset = 0;
3351                 page++;
3352
3353                 context_append(&ctx->context, d, 1, 0);
3354         }
3355
3356         return 0;
3357 }
3358
3359 static int ohci_queue_iso(struct fw_iso_context *base,
3360                           struct fw_iso_packet *packet,
3361                           struct fw_iso_buffer *buffer,
3362                           unsigned long payload)
3363 {
3364         struct iso_context *ctx = container_of(base, struct iso_context, base);
3365         unsigned long flags;
3366         int ret = -ENOSYS;
3367
3368         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3369         switch (base->type) {
3370         case FW_ISO_CONTEXT_TRANSMIT:
3371                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3372                 break;
3373         case FW_ISO_CONTEXT_RECEIVE:
3374                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3375                 break;
3376         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3377                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3378                 break;
3379         }
3380         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3381
3382         return ret;
3383 }
3384
3385 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3386 {
3387         struct context *ctx =
3388                         &container_of(base, struct iso_context, base)->context;
3389
3390         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3391 }
3392
3393 static const struct fw_card_driver ohci_driver = {
3394         .enable                 = ohci_enable,
3395         .read_phy_reg           = ohci_read_phy_reg,
3396         .update_phy_reg         = ohci_update_phy_reg,
3397         .set_config_rom         = ohci_set_config_rom,
3398         .send_request           = ohci_send_request,
3399         .send_response          = ohci_send_response,
3400         .cancel_packet          = ohci_cancel_packet,
3401         .enable_phys_dma        = ohci_enable_phys_dma,
3402         .read_csr               = ohci_read_csr,
3403         .write_csr              = ohci_write_csr,
3404
3405         .allocate_iso_context   = ohci_allocate_iso_context,
3406         .free_iso_context       = ohci_free_iso_context,
3407         .set_iso_channels       = ohci_set_iso_channels,
3408         .queue_iso              = ohci_queue_iso,
3409         .flush_queue_iso        = ohci_flush_queue_iso,
3410         .start_iso              = ohci_start_iso,
3411         .stop_iso               = ohci_stop_iso,
3412 };
3413
3414 #ifdef CONFIG_PPC_PMAC
3415 static void pmac_ohci_on(struct pci_dev *dev)
3416 {
3417         if (machine_is(powermac)) {
3418                 struct device_node *ofn = pci_device_to_OF_node(dev);
3419
3420                 if (ofn) {
3421                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3422                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3423                 }
3424         }
3425 }
3426
3427 static void pmac_ohci_off(struct pci_dev *dev)
3428 {
3429         if (machine_is(powermac)) {
3430                 struct device_node *ofn = pci_device_to_OF_node(dev);
3431
3432                 if (ofn) {
3433                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3434                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3435                 }
3436         }
3437 }
3438 #else
3439 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3440 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3441 #endif /* CONFIG_PPC_PMAC */
3442
3443 static int __devinit pci_probe(struct pci_dev *dev,
3444                                const struct pci_device_id *ent)
3445 {
3446         struct fw_ohci *ohci;
3447         u32 bus_options, max_receive, link_speed, version;
3448         u64 guid;
3449         int i, err;
3450         size_t size;
3451
3452         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3453                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3454                 return -ENOSYS;
3455         }
3456
3457         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3458         if (ohci == NULL) {
3459                 err = -ENOMEM;
3460                 goto fail;
3461         }
3462
3463         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3464
3465         pmac_ohci_on(dev);
3466
3467         err = pci_enable_device(dev);
3468         if (err) {
3469                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3470                 goto fail_free;
3471         }
3472
3473         pci_set_master(dev);
3474         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3475         pci_set_drvdata(dev, ohci);
3476
3477         spin_lock_init(&ohci->lock);
3478         mutex_init(&ohci->phy_reg_mutex);
3479
3480         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3481
3482         err = pci_request_region(dev, 0, ohci_driver_name);
3483         if (err) {
3484                 dev_err(&dev->dev, "MMIO resource unavailable\n");
3485                 goto fail_disable;
3486         }
3487
3488         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3489         if (ohci->registers == NULL) {
3490                 dev_err(&dev->dev, "failed to remap registers\n");
3491                 err = -ENXIO;
3492                 goto fail_iomem;
3493         }
3494
3495         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3496                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3497                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3498                      ohci_quirks[i].device == dev->device) &&
3499                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3500                      ohci_quirks[i].revision >= dev->revision)) {
3501                         ohci->quirks = ohci_quirks[i].flags;
3502                         break;
3503                 }
3504         if (param_quirks)
3505                 ohci->quirks = param_quirks;
3506
3507         /*
3508          * Because dma_alloc_coherent() allocates at least one page,
3509          * we save space by using a common buffer for the AR request/
3510          * response descriptors and the self IDs buffer.
3511          */
3512         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3513         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3514         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3515                                                PAGE_SIZE,
3516                                                &ohci->misc_buffer_bus,
3517                                                GFP_KERNEL);
3518         if (!ohci->misc_buffer) {
3519                 err = -ENOMEM;
3520                 goto fail_iounmap;
3521         }
3522
3523         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3524                               OHCI1394_AsReqRcvContextControlSet);
3525         if (err < 0)
3526                 goto fail_misc_buf;
3527
3528         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3529                               OHCI1394_AsRspRcvContextControlSet);
3530         if (err < 0)
3531                 goto fail_arreq_ctx;
3532
3533         err = context_init(&ohci->at_request_ctx, ohci,
3534                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3535         if (err < 0)
3536                 goto fail_arrsp_ctx;
3537
3538         err = context_init(&ohci->at_response_ctx, ohci,
3539                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3540         if (err < 0)
3541                 goto fail_atreq_ctx;
3542
3543         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3544         ohci->ir_context_channels = ~0ULL;
3545         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3546         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3547         ohci->ir_context_mask = ohci->ir_context_support;
3548         ohci->n_ir = hweight32(ohci->ir_context_mask);
3549         size = sizeof(struct iso_context) * ohci->n_ir;
3550         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3551
3552         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3553         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3554         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3555         ohci->it_context_mask = ohci->it_context_support;
3556         ohci->n_it = hweight32(ohci->it_context_mask);
3557         size = sizeof(struct iso_context) * ohci->n_it;
3558         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3559
3560         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3561                 err = -ENOMEM;
3562                 goto fail_contexts;
3563         }
3564
3565         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3566         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3567
3568         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3569         max_receive = (bus_options >> 12) & 0xf;
3570         link_speed = bus_options & 0x7;
3571         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3572                 reg_read(ohci, OHCI1394_GUIDLo);
3573
3574         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3575         if (err)
3576                 goto fail_contexts;
3577
3578         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3579         dev_notice(&dev->dev,
3580                   "added OHCI v%x.%x device as card %d, "
3581                   "%d IR + %d IT contexts, quirks 0x%x\n",
3582                   version >> 16, version & 0xff, ohci->card.index,
3583                   ohci->n_ir, ohci->n_it, ohci->quirks);
3584
3585         return 0;
3586
3587  fail_contexts:
3588         kfree(ohci->ir_context_list);
3589         kfree(ohci->it_context_list);
3590         context_release(&ohci->at_response_ctx);
3591  fail_atreq_ctx:
3592         context_release(&ohci->at_request_ctx);
3593  fail_arrsp_ctx:
3594         ar_context_release(&ohci->ar_response_ctx);
3595  fail_arreq_ctx:
3596         ar_context_release(&ohci->ar_request_ctx);
3597  fail_misc_buf:
3598         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3599                           ohci->misc_buffer, ohci->misc_buffer_bus);
3600  fail_iounmap:
3601         pci_iounmap(dev, ohci->registers);
3602  fail_iomem:
3603         pci_release_region(dev, 0);
3604  fail_disable:
3605         pci_disable_device(dev);
3606  fail_free:
3607         kfree(ohci);
3608         pmac_ohci_off(dev);
3609  fail:
3610         if (err == -ENOMEM)
3611                 dev_err(&dev->dev, "out of memory\n");
3612
3613         return err;
3614 }
3615
3616 static void pci_remove(struct pci_dev *dev)
3617 {
3618         struct fw_ohci *ohci;
3619
3620         ohci = pci_get_drvdata(dev);
3621         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3622         flush_writes(ohci);
3623         cancel_work_sync(&ohci->bus_reset_work);
3624         fw_core_remove_card(&ohci->card);
3625
3626         /*
3627          * FIXME: Fail all pending packets here, now that the upper
3628          * layers can't queue any more.
3629          */
3630
3631         software_reset(ohci);
3632         free_irq(dev->irq, ohci);
3633
3634         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3635                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3636                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3637         if (ohci->config_rom)
3638                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3639                                   ohci->config_rom, ohci->config_rom_bus);
3640         ar_context_release(&ohci->ar_request_ctx);
3641         ar_context_release(&ohci->ar_response_ctx);
3642         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3643                           ohci->misc_buffer, ohci->misc_buffer_bus);
3644         context_release(&ohci->at_request_ctx);
3645         context_release(&ohci->at_response_ctx);
3646         kfree(ohci->it_context_list);
3647         kfree(ohci->ir_context_list);
3648         pci_disable_msi(dev);
3649         pci_iounmap(dev, ohci->registers);
3650         pci_release_region(dev, 0);
3651         pci_disable_device(dev);
3652         kfree(ohci);
3653         pmac_ohci_off(dev);
3654
3655         dev_notice(&dev->dev, "removed fw-ohci device\n");
3656 }
3657
3658 #ifdef CONFIG_PM
3659 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3660 {
3661         struct fw_ohci *ohci = pci_get_drvdata(dev);
3662         int err;
3663
3664         software_reset(ohci);
3665         free_irq(dev->irq, ohci);
3666         pci_disable_msi(dev);
3667         err = pci_save_state(dev);
3668         if (err) {
3669                 dev_err(&dev->dev, "pci_save_state failed\n");
3670                 return err;
3671         }
3672         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3673         if (err)
3674                 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
3675         pmac_ohci_off(dev);
3676
3677         return 0;
3678 }
3679
3680 static int pci_resume(struct pci_dev *dev)
3681 {
3682         struct fw_ohci *ohci = pci_get_drvdata(dev);
3683         int err;
3684
3685         pmac_ohci_on(dev);
3686         pci_set_power_state(dev, PCI_D0);
3687         pci_restore_state(dev);
3688         err = pci_enable_device(dev);
3689         if (err) {
3690                 dev_err(&dev->dev, "pci_enable_device failed\n");
3691                 return err;
3692         }
3693
3694         /* Some systems don't setup GUID register on resume from ram  */
3695         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3696                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3697                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3698                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3699         }
3700
3701         err = ohci_enable(&ohci->card, NULL, 0);
3702         if (err)
3703                 return err;
3704
3705         ohci_resume_iso_dma(ohci);
3706
3707         return 0;
3708 }
3709 #endif
3710
3711 static const struct pci_device_id pci_table[] = {
3712         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3713         { }
3714 };
3715
3716 MODULE_DEVICE_TABLE(pci, pci_table);
3717
3718 static struct pci_driver fw_ohci_pci_driver = {
3719         .name           = ohci_driver_name,
3720         .id_table       = pci_table,
3721         .probe          = pci_probe,
3722         .remove         = pci_remove,
3723 #ifdef CONFIG_PM
3724         .resume         = pci_resume,
3725         .suspend        = pci_suspend,
3726 #endif
3727 };
3728
3729 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3730 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3731 MODULE_LICENSE("GPL");
3732
3733 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3734 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3735 MODULE_ALIAS("ohci1394");
3736 #endif
3737
3738 static int __init fw_ohci_init(void)
3739 {
3740         return pci_register_driver(&fw_ohci_pci_driver);
3741 }
3742
3743 static void __exit fw_ohci_cleanup(void)
3744 {
3745         pci_unregister_driver(&fw_ohci_pci_driver);
3746 }
3747
3748 module_init(fw_ohci_init);
3749 module_exit(fw_ohci_cleanup);