Pileus Git - ~andy/linux/blob - drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49
  50 #ifdef CONFIG_PPC_PMAC
  51 #include <asm/pmac_feature.h>
  52 #endif
  53
  54 #include "core.h"
  55 #include "ohci.h"
  56
  57 #define ohci_info(ohci, f, args...)     dev_info(ohci->card.device, f, ##args)
  58 #define ohci_notice(ohci, f, args...)   dev_notice(ohci->card.device, f, ##args)
  59 #define ohci_err(ohci, f, args...)      dev_err(ohci->card.device, f, ##args)
  60
  61 #define DESCRIPTOR_OUTPUT_MORE          0
  62 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  63 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  64 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  65 #define DESCRIPTOR_STATUS               (1 << 11)
  66 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  67 #define DESCRIPTOR_PING                 (1 << 7)
  68 #define DESCRIPTOR_YY                   (1 << 6)
  69 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  70 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  71 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  72 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  73 #define DESCRIPTOR_WAIT                 (3 << 0)
  74
  75 #define DESCRIPTOR_CMD                  (0xf << 12)
  76
  77 struct descriptor {
  78         __le16 req_count;
  79         __le16 control;
  80         __le32 data_address;
  81         __le32 branch_address;
  82         __le16 res_count;
  83         __le16 transfer_status;
  84 } __attribute__((aligned(16)));
  85
  86 #define CONTROL_SET(regs)       (regs)
  87 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  88 #define COMMAND_PTR(regs)       ((regs) + 12)
  89 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  90
  91 #define AR_BUFFER_SIZE  (32*1024)
  92 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  93 /* we need at least two pages for proper list management */
  94 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  95
  96 #define MAX_ASYNC_PAYLOAD       4096
  97 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  98 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  99
 100 struct ar_context {
 101         struct fw_ohci *ohci;
 102         struct page *pages[AR_BUFFERS];
 103         void *buffer;
 104         struct descriptor *descriptors;
 105         dma_addr_t descriptors_bus;
 106         void *pointer;
 107         unsigned int last_buffer_index;
 108         u32 regs;
 109         struct tasklet_struct tasklet;
 110 };
 111
 112 struct context;
 113
 114 typedef int (*descriptor_callback_t)(struct context *ctx,
 115                                      struct descriptor *d,
 116                                      struct descriptor *last);
 117
 118 /*
 119  * A buffer that contains a block of DMA-able coherent memory used for
 120  * storing a portion of a DMA descriptor program.
 121  */
 122 struct descriptor_buffer {
 123         struct list_head list;
 124         dma_addr_t buffer_bus;
 125         size_t buffer_size;
 126         size_t used;
 127         struct descriptor buffer[0];
 128 };
 129
 130 struct context {
 131         struct fw_ohci *ohci;
 132         u32 regs;
 133         int total_allocation;
 134         u32 current_bus;
 135         bool running;
 136         bool flushing;
 137
 138         /*
 139          * List of page-sized buffers for storing DMA descriptors.
 140          * Head of list contains buffers in use and tail of list contains
 141          * free buffers.
 142          */
 143         struct list_head buffer_list;
 144
 145         /*
 146          * Pointer to a buffer inside buffer_list that contains the tail
 147          * end of the current DMA program.
 148          */
 149         struct descriptor_buffer *buffer_tail;
 150
 151         /*
 152          * The descriptor containing the branch address of the first
 153          * descriptor that has not yet been filled by the device.
 154          */
 155         struct descriptor *last;
 156
 157         /*
 158          * The last descriptor block in the DMA program. It contains the branch
 159          * address that must be updated upon appending a new descriptor.
 160          */
 161         struct descriptor *prev;
 162         int prev_z;
 163
 164         descriptor_callback_t callback;
 165
 166         struct tasklet_struct tasklet;
 167 };
 168
 169 #define IT_HEADER_SY(v)          ((v) <<  0)
 170 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 171 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 172 #define IT_HEADER_TAG(v)         ((v) << 14)
 173 #define IT_HEADER_SPEED(v)       ((v) << 16)
 174 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 175
 176 struct iso_context {
 177         struct fw_iso_context base;
 178         struct context context;
 179         void *header;
 180         size_t header_length;
 181         unsigned long flushing_completions;
 182         u32 mc_buffer_bus;
 183         u16 mc_completed;
 184         u16 last_timestamp;
 185         u8 sync;
 186         u8 tags;
 187 };
 188
 189 #define CONFIG_ROM_SIZE 1024
 190
 191 struct fw_ohci {
 192         struct fw_card card;
 193
 194         __iomem char *registers;
 195         int node_id;
 196         int generation;
 197         int request_generation; /* for timestamping incoming requests */
 198         unsigned quirks;
 199         unsigned int pri_req_max;
 200         u32 bus_time;
 201         bool bus_time_running;
 202         bool is_root;
 203         bool csr_state_setclear_abdicate;
 204         int n_ir;
 205         int n_it;
 206         /*
 207          * Spinlock for accessing fw_ohci data.  Never call out of
 208          * this driver with this lock held.
 209          */
 210         spinlock_t lock;
 211
 212         struct mutex phy_reg_mutex;
 213
 214         void *misc_buffer;
 215         dma_addr_t misc_buffer_bus;
 216
 217         struct ar_context ar_request_ctx;
 218         struct ar_context ar_response_ctx;
 219         struct context at_request_ctx;
 220         struct context at_response_ctx;
 221
 222         u32 it_context_support;
 223         u32 it_context_mask;     /* unoccupied IT contexts */
 224         struct iso_context *it_context_list;
 225         u64 ir_context_channels; /* unoccupied channels */
 226         u32 ir_context_support;
 227         u32 ir_context_mask;     /* unoccupied IR contexts */
 228         struct iso_context *ir_context_list;
 229         u64 mc_channels; /* channels in use by the multichannel IR context */
 230         bool mc_allocated;
 231
 232         __be32    *config_rom;
 233         dma_addr_t config_rom_bus;
 234         __be32    *next_config_rom;
 235         dma_addr_t next_config_rom_bus;
 236         __be32     next_header;
 237
 238         __le32    *self_id_cpu;
 239         dma_addr_t self_id_bus;
 240         struct work_struct bus_reset_work;
 241
 242         u32 self_id_buffer[512];
 243 };
 244
 245 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 246 {
 247         return container_of(card, struct fw_ohci, card);
 248 }
 249
 250 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 251 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 252 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 253 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 254 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 255 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 256
 257 #define CONTEXT_RUN     0x8000
 258 #define CONTEXT_WAKE    0x1000
 259 #define CONTEXT_DEAD    0x0800
 260 #define CONTEXT_ACTIVE  0x0400
 261
 262 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 263 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 264 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 265
 266 #define OHCI1394_REGISTER_SIZE          0x800
 267 #define OHCI1394_PCI_HCI_Control        0x40
 268 #define SELF_ID_BUF_SIZE                0x800
 269 #define OHCI_TCODE_PHY_PACKET           0x0e
 270 #define OHCI_VERSION_1_1                0x010010
 271
 272 static char ohci_driver_name[] = KBUILD_MODNAME;
 273
 274 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 275 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 276 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 277 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 278 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 279 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 280 #define PCI_DEVICE_ID_VIA_VT630X        0x3044
 281 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 282 #define PCI_REV_ID_VIA_VT6306           0x46
 283
 284 #define QUIRK_CYCLE_TIMER               1
 285 #define QUIRK_RESET_PACKET              2
 286 #define QUIRK_BE_HEADERS                4
 287 #define QUIRK_NO_1394A                  8
 288 #define QUIRK_NO_MSI                    16
 289 #define QUIRK_TI_SLLZ059                32
 290 #define QUIRK_IR_WAKE                   64
 291 #define QUIRK_PHY_LCTRL_TIMEOUT         128
 292
 293 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 294 static const struct {
 295         unsigned short vendor, device, revision, flags;
 296 } ohci_quirks[] = {
 297         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 298                 QUIRK_CYCLE_TIMER},
 299
 300         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 301                 QUIRK_BE_HEADERS},
 302
 303         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 304                 QUIRK_PHY_LCTRL_TIMEOUT | QUIRK_NO_MSI},
 305
 306         {PCI_VENDOR_ID_ATT, PCI_ANY_ID, PCI_ANY_ID,
 307                 QUIRK_PHY_LCTRL_TIMEOUT},
 308
 309         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 310                 QUIRK_RESET_PACKET},
 311
 312         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 313                 QUIRK_NO_MSI},
 314
 315         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 316                 QUIRK_CYCLE_TIMER},
 317
 318         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 319                 QUIRK_NO_MSI},
 320
 321         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 322                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 323
 324         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 325                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 326
 327         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 328                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 329
 330         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 331                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 332
 333         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 334                 QUIRK_RESET_PACKET},
 335
 336         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
 337                 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
 338
 339         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 340                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 341 };
 342
 343 /* This overrides anything that was found in ohci_quirks[]. */
 344 static int param_quirks;
 345 module_param_named(quirks, param_quirks, int, 0644);
 346 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 347         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 348         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 349         ", AR/selfID endianness = "     __stringify(QUIRK_BE_HEADERS)
 350         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 351         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 352         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 353         ", IR wake unreliable = "       __stringify(QUIRK_IR_WAKE)
 354         ", phy LCtrl timeout = "        __stringify(QUIRK_PHY_LCTRL_TIMEOUT)
 355         ")");
 356
 357 #define OHCI_PARAM_DEBUG_AT_AR          1
 358 #define OHCI_PARAM_DEBUG_SELFIDS        2
 359 #define OHCI_PARAM_DEBUG_IRQS           4
 360 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 361
 362 static int param_debug;
 363 module_param_named(debug, param_debug, int, 0644);
 364 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 365         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 366         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 367         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 368         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 369         ", or a combination, or all = -1)");
 370
 371 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 372 {
 373         if (likely(!(param_debug &
 374                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 375                 return;
 376
 377         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 378             !(evt & OHCI1394_busReset))
 379                 return;
 380
 381         ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 382             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 383             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 384             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 385             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 386             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 387             evt & OHCI1394_isochRx              ? " IR"                 : "",
 388             evt & OHCI1394_isochTx              ? " IT"                 : "",
 389             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 390             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 391             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 392             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 393             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 394             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 395             evt & OHCI1394_busReset             ? " busReset"           : "",
 396             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 397                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 398                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 399                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 400                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 401                     OHCI1394_cycleInconsistent |
 402                     OHCI1394_regAccessFail | OHCI1394_busReset)
 403                                                 ? " ?"                  : "");
 404 }
 405
 406 static const char *speed[] = {
 407         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 408 };
 409 static const char *power[] = {
 410         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 411         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 412 };
 413 static const char port[] = { '.', '-', 'p', 'c', };
 414
 415 static char _p(u32 *s, int shift)
 416 {
 417         return port[*s >> shift & 3];
 418 }
 419
 420 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 421 {
 422         u32 *s;
 423
 424         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 425                 return;
 426
 427         ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
 428                     self_id_count, generation, ohci->node_id);
 429
 430         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 431                 if ((*s & 1 << 23) == 0)
 432                         ohci_notice(ohci,
 433                             "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
 434                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 435                             speed[*s >> 14 & 3], *s >> 16 & 63,
 436                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 437                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 438                 else
 439                         ohci_notice(ohci,
 440                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 441                             *s, *s >> 24 & 63,
 442                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 443                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 444 }
 445
 446 static const char *evts[] = {
 447         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 448         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 449         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 450         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 451         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 452         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 453         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 454         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 455         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 456         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 457         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 458         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 459         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 460         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 461         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 462         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 463         [0x20] = "pending/cancelled",
 464 };
 465 static const char *tcodes[] = {
 466         [0x0] = "QW req",               [0x1] = "BW req",
 467         [0x2] = "W resp",               [0x3] = "-reserved-",
 468         [0x4] = "QR req",               [0x5] = "BR req",
 469         [0x6] = "QR resp",              [0x7] = "BR resp",
 470         [0x8] = "cycle start",          [0x9] = "Lk req",
 471         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 472         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 473         [0xe] = "link internal",        [0xf] = "-reserved-",
 474 };
 475
 476 static void log_ar_at_event(struct fw_ohci *ohci,
 477                             char dir, int speed, u32 *header, int evt)
 478 {
 479         int tcode = header[0] >> 4 & 0xf;
 480         char specific[12];
 481
 482         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 483                 return;
 484
 485         if (unlikely(evt >= ARRAY_SIZE(evts)))
 486                         evt = 0x1f;
 487
 488         if (evt == OHCI1394_evt_bus_reset) {
 489                 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
 490                             dir, (header[2] >> 16) & 0xff);
 491                 return;
 492         }
 493
 494         switch (tcode) {
 495         case 0x0: case 0x6: case 0x8:
 496                 snprintf(specific, sizeof(specific), " = %08x",
 497                          be32_to_cpu((__force __be32)header[3]));
 498                 break;
 499         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 500                 snprintf(specific, sizeof(specific), " %x,%x",
 501                          header[3] >> 16, header[3] & 0xffff);
 502                 break;
 503         default:
 504                 specific[0] = '\0';
 505         }
 506
 507         switch (tcode) {
 508         case 0xa:
 509                 ohci_notice(ohci, "A%c %s, %s\n",
 510                             dir, evts[evt], tcodes[tcode]);
 511                 break;
 512         case 0xe:
 513                 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
 514                             dir, evts[evt], header[1], header[2]);
 515                 break;
 516         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 517                 ohci_notice(ohci,
 518                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
 519                             dir, speed, header[0] >> 10 & 0x3f,
 520                             header[1] >> 16, header[0] >> 16, evts[evt],
 521                             tcodes[tcode], header[1] & 0xffff, header[2], specific);
 522                 break;
 523         default:
 524                 ohci_notice(ohci,
 525                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
 526                             dir, speed, header[0] >> 10 & 0x3f,
 527                             header[1] >> 16, header[0] >> 16, evts[evt],
 528                             tcodes[tcode], specific);
 529         }
 530 }
 531
 532 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 533 {
 534         writel(data, ohci->registers + offset);
 535 }
 536
 537 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 538 {
 539         return readl(ohci->registers + offset);
 540 }
 541
 542 static inline void flush_writes(const struct fw_ohci *ohci)
 543 {
 544         /* Do a dummy read to flush writes. */
 545         reg_read(ohci, OHCI1394_Version);
 546 }
 547
 548 /*
 549  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 550  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 551  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 552  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 553  */
 554 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 555 {
 556         u32 val;
 557         int i;
 558
 559         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 560         for (i = 0; i < 3 + 100; i++) {
 561                 val = reg_read(ohci, OHCI1394_PhyControl);
 562                 if (!~val)
 563                         return -ENODEV; /* Card was ejected. */
 564
 565                 if (val & OHCI1394_PhyControl_ReadDone)
 566                         return OHCI1394_PhyControl_ReadData(val);
 567
 568                 /*
 569                  * Try a few times without waiting.  Sleeping is necessary
 570                  * only when the link/PHY interface is busy.
 571                  */
 572                 if (i >= 3)
 573                         msleep(1);
 574         }
 575         ohci_err(ohci, "failed to read phy reg\n");
 576
 577         return -EBUSY;
 578 }
 579
 580 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 581 {
 582         int i;
 583
 584         reg_write(ohci, OHCI1394_PhyControl,
 585                   OHCI1394_PhyControl_Write(addr, val));
 586         for (i = 0; i < 3 + 100; i++) {
 587                 val = reg_read(ohci, OHCI1394_PhyControl);
 588                 if (!~val)
 589                         return -ENODEV; /* Card was ejected. */
 590
 591                 if (!(val & OHCI1394_PhyControl_WritePending))
 592                         return 0;
 593
 594                 if (i >= 3)
 595                         msleep(1);
 596         }
 597         ohci_err(ohci, "failed to write phy reg\n");
 598
 599         return -EBUSY;
 600 }
 601
 602 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 603                           int clear_bits, int set_bits)
 604 {
 605         int ret = read_phy_reg(ohci, addr);
 606         if (ret < 0)
 607                 return ret;
 608
 609         /*
 610          * The interrupt status bits are cleared by writing a one bit.
 611          * Avoid clearing them unless explicitly requested in set_bits.
 612          */
 613         if (addr == 5)
 614                 clear_bits |= PHY_INT_STATUS_BITS;
 615
 616         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 617 }
 618
 619 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 620 {
 621         int ret;
 622
 623         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 624         if (ret < 0)
 625                 return ret;
 626
 627         return read_phy_reg(ohci, addr);
 628 }
 629
 630 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 631 {
 632         struct fw_ohci *ohci = fw_ohci(card);
 633         int ret;
 634
 635         mutex_lock(&ohci->phy_reg_mutex);
 636         ret = read_phy_reg(ohci, addr);
 637         mutex_unlock(&ohci->phy_reg_mutex);
 638
 639         return ret;
 640 }
 641
 642 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 643                                int clear_bits, int set_bits)
 644 {
 645         struct fw_ohci *ohci = fw_ohci(card);
 646         int ret;
 647
 648         mutex_lock(&ohci->phy_reg_mutex);
 649         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 650         mutex_unlock(&ohci->phy_reg_mutex);
 651
 652         return ret;
 653 }
 654
 655 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 656 {
 657         return page_private(ctx->pages[i]);
 658 }
 659
 660 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 661 {
 662         struct descriptor *d;
 663
 664         d = &ctx->descriptors[index];
 665         d->branch_address  &= cpu_to_le32(~0xf);
 666         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 667         d->transfer_status =  0;
 668
 669         wmb(); /* finish init of new descriptors before branch_address update */
 670         d = &ctx->descriptors[ctx->last_buffer_index];
 671         d->branch_address  |= cpu_to_le32(1);
 672
 673         ctx->last_buffer_index = index;
 674
 675         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 676 }
 677
 678 static void ar_context_release(struct ar_context *ctx)
 679 {
 680         unsigned int i;
 681
 682         if (ctx->buffer)
 683                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 684
 685         for (i = 0; i < AR_BUFFERS; i++)
 686                 if (ctx->pages[i]) {
 687                         dma_unmap_page(ctx->ohci->card.device,
 688                                        ar_buffer_bus(ctx, i),
 689                                        PAGE_SIZE, DMA_FROM_DEVICE);
 690                         __free_page(ctx->pages[i]);
 691                 }
 692 }
 693
 694 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 695 {
 696         struct fw_ohci *ohci = ctx->ohci;
 697
 698         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 699                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 700                 flush_writes(ohci);
 701
 702                 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
 703         }
 704         /* FIXME: restart? */
 705 }
 706
 707 static inline unsigned int ar_next_buffer_index(unsigned int index)
 708 {
 709         return (index + 1) % AR_BUFFERS;
 710 }
 711
 712 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 713 {
 714         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 715 }
 716
 717 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 718 {
 719         return ar_next_buffer_index(ctx->last_buffer_index);
 720 }
 721
 722 /*
 723  * We search for the buffer that contains the last AR packet DMA data written
 724  * by the controller.
 725  */
 726 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 727                                                  unsigned int *buffer_offset)
 728 {
 729         unsigned int i, next_i, last = ctx->last_buffer_index;
 730         __le16 res_count, next_res_count;
 731
 732         i = ar_first_buffer_index(ctx);
 733         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 734
 735         /* A buffer that is not yet completely filled must be the last one. */
 736         while (i != last && res_count == 0) {
 737
 738                 /* Peek at the next descriptor. */
 739                 next_i = ar_next_buffer_index(i);
 740                 rmb(); /* read descriptors in order */
 741                 next_res_count = ACCESS_ONCE(
 742                                 ctx->descriptors[next_i].res_count);
 743                 /*
 744                  * If the next descriptor is still empty, we must stop at this
 745                  * descriptor.
 746                  */
 747                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 748                         /*
 749                          * The exception is when the DMA data for one packet is
 750                          * split over three buffers; in this case, the middle
 751                          * buffer's descriptor might be never updated by the
 752                          * controller and look still empty, and we have to peek
 753                          * at the third one.
 754                          */
 755                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 756                                 next_i = ar_next_buffer_index(next_i);
 757                                 rmb();
 758                                 next_res_count = ACCESS_ONCE(
 759                                         ctx->descriptors[next_i].res_count);
 760                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 761                                         goto next_buffer_is_active;
 762                         }
 763
 764                         break;
 765                 }
 766
 767 next_buffer_is_active:
 768                 i = next_i;
 769                 res_count = next_res_count;
 770         }
 771
 772         rmb(); /* read res_count before the DMA data */
 773
 774         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 775         if (*buffer_offset > PAGE_SIZE) {
 776                 *buffer_offset = 0;
 777                 ar_context_abort(ctx, "corrupted descriptor");
 778         }
 779
 780         return i;
 781 }
 782
 783 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 784                                     unsigned int end_buffer_index,
 785                                     unsigned int end_buffer_offset)
 786 {
 787         unsigned int i;
 788
 789         i = ar_first_buffer_index(ctx);
 790         while (i != end_buffer_index) {
 791                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 792                                         ar_buffer_bus(ctx, i),
 793                                         PAGE_SIZE, DMA_FROM_DEVICE);
 794                 i = ar_next_buffer_index(i);
 795         }
 796         if (end_buffer_offset > 0)
 797                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 798                                         ar_buffer_bus(ctx, i),
 799                                         end_buffer_offset, DMA_FROM_DEVICE);
 800 }
 801
 802 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 803 #define cond_le32_to_cpu(v) \
 804         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 805 #else
 806 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 807 #endif
 808
 809 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 810 {
 811         struct fw_ohci *ohci = ctx->ohci;
 812         struct fw_packet p;
 813         u32 status, length, tcode;
 814         int evt;
 815
 816         p.header[0] = cond_le32_to_cpu(buffer[0]);
 817         p.header[1] = cond_le32_to_cpu(buffer[1]);
 818         p.header[2] = cond_le32_to_cpu(buffer[2]);
 819
 820         tcode = (p.header[0] >> 4) & 0x0f;
 821         switch (tcode) {
 822         case TCODE_WRITE_QUADLET_REQUEST:
 823         case TCODE_READ_QUADLET_RESPONSE:
 824                 p.header[3] = (__force __u32) buffer[3];
 825                 p.header_length = 16;
 826                 p.payload_length = 0;
 827                 break;
 828
 829         case TCODE_READ_BLOCK_REQUEST :
 830                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 831                 p.header_length = 16;
 832                 p.payload_length = 0;
 833                 break;
 834
 835         case TCODE_WRITE_BLOCK_REQUEST:
 836         case TCODE_READ_BLOCK_RESPONSE:
 837         case TCODE_LOCK_REQUEST:
 838         case TCODE_LOCK_RESPONSE:
 839                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 840                 p.header_length = 16;
 841                 p.payload_length = p.header[3] >> 16;
 842                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 843                         ar_context_abort(ctx, "invalid packet length");
 844                         return NULL;
 845                 }
 846                 break;
 847
 848         case TCODE_WRITE_RESPONSE:
 849         case TCODE_READ_QUADLET_REQUEST:
 850         case OHCI_TCODE_PHY_PACKET:
 851                 p.header_length = 12;
 852                 p.payload_length = 0;
 853                 break;
 854
 855         default:
 856                 ar_context_abort(ctx, "invalid tcode");
 857                 return NULL;
 858         }
 859
 860         p.payload = (void *) buffer + p.header_length;
 861
 862         /* FIXME: What to do about evt_* errors? */
 863         length = (p.header_length + p.payload_length + 3) / 4;
 864         status = cond_le32_to_cpu(buffer[length]);
 865         evt    = (status >> 16) & 0x1f;
 866
 867         p.ack        = evt - 16;
 868         p.speed      = (status >> 21) & 0x7;
 869         p.timestamp  = status & 0xffff;
 870         p.generation = ohci->request_generation;
 871
 872         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 873
 874         /*
 875          * Several controllers, notably from NEC and VIA, forget to
 876          * write ack_complete status at PHY packet reception.
 877          */
 878         if (evt == OHCI1394_evt_no_status &&
 879             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 880                 p.ack = ACK_COMPLETE;
 881
 882         /*
 883          * The OHCI bus reset handler synthesizes a PHY packet with
 884          * the new generation number when a bus reset happens (see
 885          * section 8.4.2.3).  This helps us determine when a request
 886          * was received and make sure we send the response in the same
 887          * generation.  We only need this for requests; for responses
 888          * we use the unique tlabel for finding the matching
 889          * request.
 890          *
 891          * Alas some chips sometimes emit bus reset packets with a
 892          * wrong generation.  We set the correct generation for these
 893          * at a slightly incorrect time (in bus_reset_work).
 894          */
 895         if (evt == OHCI1394_evt_bus_reset) {
 896                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 897                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 898         } else if (ctx == &ohci->ar_request_ctx) {
 899                 fw_core_handle_request(&ohci->card, &p);
 900         } else {
 901                 fw_core_handle_response(&ohci->card, &p);
 902         }
 903
 904         return buffer + length + 1;
 905 }
 906
 907 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 908 {
 909         void *next;
 910
 911         while (p < end) {
 912                 next = handle_ar_packet(ctx, p);
 913                 if (!next)
 914                         return p;
 915                 p = next;
 916         }
 917
 918         return p;
 919 }
 920
 921 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 922 {
 923         unsigned int i;
 924
 925         i = ar_first_buffer_index(ctx);
 926         while (i != end_buffer) {
 927                 dma_sync_single_for_device(ctx->ohci->card.device,
 928                                            ar_buffer_bus(ctx, i),
 929                                            PAGE_SIZE, DMA_FROM_DEVICE);
 930                 ar_context_link_page(ctx, i);
 931                 i = ar_next_buffer_index(i);
 932         }
 933 }
 934
 935 static void ar_context_tasklet(unsigned long data)
 936 {
 937         struct ar_context *ctx = (struct ar_context *)data;
 938         unsigned int end_buffer_index, end_buffer_offset;
 939         void *p, *end;
 940
 941         p = ctx->pointer;
 942         if (!p)
 943                 return;
 944
 945         end_buffer_index = ar_search_last_active_buffer(ctx,
 946                                                         &end_buffer_offset);
 947         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 948         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 949
 950         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 951                 /*
 952                  * The filled part of the overall buffer wraps around; handle
 953                  * all packets up to the buffer end here.  If the last packet
 954                  * wraps around, its tail will be visible after the buffer end
 955                  * because the buffer start pages are mapped there again.
 956                  */
 957                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 958                 p = handle_ar_packets(ctx, p, buffer_end);
 959                 if (p < buffer_end)
 960                         goto error;
 961                 /* adjust p to point back into the actual buffer */
 962                 p -= AR_BUFFERS * PAGE_SIZE;
 963         }
 964
 965         p = handle_ar_packets(ctx, p, end);
 966         if (p != end) {
 967                 if (p > end)
 968                         ar_context_abort(ctx, "inconsistent descriptor");
 969                 goto error;
 970         }
 971
 972         ctx->pointer = p;
 973         ar_recycle_buffers(ctx, end_buffer_index);
 974
 975         return;
 976
 977 error:
 978         ctx->pointer = NULL;
 979 }
 980
 981 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 982                            unsigned int descriptors_offset, u32 regs)
 983 {
 984         unsigned int i;
 985         dma_addr_t dma_addr;
 986         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 987         struct descriptor *d;
 988
 989         ctx->regs        = regs;
 990         ctx->ohci        = ohci;
 991         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 992
 993         for (i = 0; i < AR_BUFFERS; i++) {
 994                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 995                 if (!ctx->pages[i])
 996                         goto out_of_memory;
 997                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 998                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 999                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1000                         __free_page(ctx->pages[i]);
1001                         ctx->pages[i] = NULL;
1002                         goto out_of_memory;
1003                 }
1004                 set_page_private(ctx->pages[i], dma_addr);
1005         }
1006
1007         for (i = 0; i < AR_BUFFERS; i++)
1008                 pages[i]              = ctx->pages[i];
1009         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1010                 pages[AR_BUFFERS + i] = ctx->pages[i];
1011         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
1012                                  -1, PAGE_KERNEL);
1013         if (!ctx->buffer)
1014                 goto out_of_memory;
1015
1016         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1017         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1018
1019         for (i = 0; i < AR_BUFFERS; i++) {
1020                 d = &ctx->descriptors[i];
1021                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1022                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1023                                                 DESCRIPTOR_STATUS |
1024                                                 DESCRIPTOR_BRANCH_ALWAYS);
1025                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1026                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1027                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1028         }
1029
1030         return 0;
1031
1032 out_of_memory:
1033         ar_context_release(ctx);
1034
1035         return -ENOMEM;
1036 }
1037
1038 static void ar_context_run(struct ar_context *ctx)
1039 {
1040         unsigned int i;
1041
1042         for (i = 0; i < AR_BUFFERS; i++)
1043                 ar_context_link_page(ctx, i);
1044
1045         ctx->pointer = ctx->buffer;
1046
1047         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1048         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1049 }
1050
1051 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1052 {
1053         __le16 branch;
1054
1055         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1056
1057         /* figure out which descriptor the branch address goes in */
1058         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1059                 return d;
1060         else
1061                 return d + z - 1;
1062 }
1063
1064 static void context_tasklet(unsigned long data)
1065 {
1066         struct context *ctx = (struct context *) data;
1067         struct descriptor *d, *last;
1068         u32 address;
1069         int z;
1070         struct descriptor_buffer *desc;
1071
1072         desc = list_entry(ctx->buffer_list.next,
1073                         struct descriptor_buffer, list);
1074         last = ctx->last;
1075         while (last->branch_address != 0) {
1076                 struct descriptor_buffer *old_desc = desc;
1077                 address = le32_to_cpu(last->branch_address);
1078                 z = address & 0xf;
1079                 address &= ~0xf;
1080                 ctx->current_bus = address;
1081
1082                 /* If the branch address points to a buffer outside of the
1083                  * current buffer, advance to the next buffer. */
1084                 if (address < desc->buffer_bus ||
1085                                 address >= desc->buffer_bus + desc->used)
1086                         desc = list_entry(desc->list.next,
1087                                         struct descriptor_buffer, list);
1088                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1089                 last = find_branch_descriptor(d, z);
1090
1091                 if (!ctx->callback(ctx, d, last))
1092                         break;
1093
1094                 if (old_desc != desc) {
1095                         /* If we've advanced to the next buffer, move the
1096                          * previous buffer to the free list. */
1097                         unsigned long flags;
1098                         old_desc->used = 0;
1099                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1100                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1101                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1102                 }
1103                 ctx->last = last;
1104         }
1105 }
1106
1107 /*
1108  * Allocate a new buffer and add it to the list of free buffers for this
1109  * context.  Must be called with ohci->lock held.
1110  */
1111 static int context_add_buffer(struct context *ctx)
1112 {
1113         struct descriptor_buffer *desc;
1114         dma_addr_t uninitialized_var(bus_addr);
1115         int offset;
1116
1117         /*
1118          * 16MB of descriptors should be far more than enough for any DMA
1119          * program.  This will catch run-away userspace or DoS attacks.
1120          */
1121         if (ctx->total_allocation >= 16*1024*1024)
1122                 return -ENOMEM;
1123
1124         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1125                         &bus_addr, GFP_ATOMIC);
1126         if (!desc)
1127                 return -ENOMEM;
1128
1129         offset = (void *)&desc->buffer - (void *)desc;
1130         desc->buffer_size = PAGE_SIZE - offset;
1131         desc->buffer_bus = bus_addr + offset;
1132         desc->used = 0;
1133
1134         list_add_tail(&desc->list, &ctx->buffer_list);
1135         ctx->total_allocation += PAGE_SIZE;
1136
1137         return 0;
1138 }
1139
1140 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1141                         u32 regs, descriptor_callback_t callback)
1142 {
1143         ctx->ohci = ohci;
1144         ctx->regs = regs;
1145         ctx->total_allocation = 0;
1146
1147         INIT_LIST_HEAD(&ctx->buffer_list);
1148         if (context_add_buffer(ctx) < 0)
1149                 return -ENOMEM;
1150
1151         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1152                         struct descriptor_buffer, list);
1153
1154         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1155         ctx->callback = callback;
1156
1157         /*
1158          * We put a dummy descriptor in the buffer that has a NULL
1159          * branch address and looks like it's been sent.  That way we
1160          * have a descriptor to append DMA programs to.
1161          */
1162         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1163         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1164         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1165         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1166         ctx->last = ctx->buffer_tail->buffer;
1167         ctx->prev = ctx->buffer_tail->buffer;
1168         ctx->prev_z = 1;
1169
1170         return 0;
1171 }
1172
1173 static void context_release(struct context *ctx)
1174 {
1175         struct fw_card *card = &ctx->ohci->card;
1176         struct descriptor_buffer *desc, *tmp;
1177
1178         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1179                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1180                         desc->buffer_bus -
1181                         ((void *)&desc->buffer - (void *)desc));
1182 }
1183
1184 /* Must be called with ohci->lock held */
1185 static struct descriptor *context_get_descriptors(struct context *ctx,
1186                                                   int z, dma_addr_t *d_bus)
1187 {
1188         struct descriptor *d = NULL;
1189         struct descriptor_buffer *desc = ctx->buffer_tail;
1190
1191         if (z * sizeof(*d) > desc->buffer_size)
1192                 return NULL;
1193
1194         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1195                 /* No room for the descriptor in this buffer, so advance to the
1196                  * next one. */
1197
1198                 if (desc->list.next == &ctx->buffer_list) {
1199                         /* If there is no free buffer next in the list,
1200                          * allocate one. */
1201                         if (context_add_buffer(ctx) < 0)
1202                                 return NULL;
1203                 }
1204                 desc = list_entry(desc->list.next,
1205                                 struct descriptor_buffer, list);
1206                 ctx->buffer_tail = desc;
1207         }
1208
1209         d = desc->buffer + desc->used / sizeof(*d);
1210         memset(d, 0, z * sizeof(*d));
1211         *d_bus = desc->buffer_bus + desc->used;
1212
1213         return d;
1214 }
1215
1216 static void context_run(struct context *ctx, u32 extra)
1217 {
1218         struct fw_ohci *ohci = ctx->ohci;
1219
1220         reg_write(ohci, COMMAND_PTR(ctx->regs),
1221                   le32_to_cpu(ctx->last->branch_address));
1222         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1223         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1224         ctx->running = true;
1225         flush_writes(ohci);
1226 }
1227
1228 static void context_append(struct context *ctx,
1229                            struct descriptor *d, int z, int extra)
1230 {
1231         dma_addr_t d_bus;
1232         struct descriptor_buffer *desc = ctx->buffer_tail;
1233         struct descriptor *d_branch;
1234
1235         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1236
1237         desc->used += (z + extra) * sizeof(*d);
1238
1239         wmb(); /* finish init of new descriptors before branch_address update */
1240
1241         d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1242         d_branch->branch_address = cpu_to_le32(d_bus | z);
1243
1244         /*
1245          * VT6306 incorrectly checks only the single descriptor at the
1246          * CommandPtr when the wake bit is written, so if it's a
1247          * multi-descriptor block starting with an INPUT_MORE, put a copy of
1248          * the branch address in the first descriptor.
1249          *
1250          * Not doing this for transmit contexts since not sure how it interacts
1251          * with skip addresses.
1252          */
1253         if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1254             d_branch != ctx->prev &&
1255             (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1256              cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1257                 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1258         }
1259
1260         ctx->prev = d;
1261         ctx->prev_z = z;
1262 }
1263
1264 static void context_stop(struct context *ctx)
1265 {
1266         struct fw_ohci *ohci = ctx->ohci;
1267         u32 reg;
1268         int i;
1269
1270         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1271         ctx->running = false;
1272
1273         for (i = 0; i < 1000; i++) {
1274                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1275                 if ((reg & CONTEXT_ACTIVE) == 0)
1276                         return;
1277
1278                 if (i)
1279                         udelay(10);
1280         }
1281         ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1282 }
1283
1284 struct driver_data {
1285         u8 inline_data[8];
1286         struct fw_packet *packet;
1287 };
1288
1289 /*
1290  * This function apppends a packet to the DMA queue for transmission.
1291  * Must always be called with the ochi->lock held to ensure proper
1292  * generation handling and locking around packet queue manipulation.
1293  */
1294 static int at_context_queue_packet(struct context *ctx,
1295                                    struct fw_packet *packet)
1296 {
1297         struct fw_ohci *ohci = ctx->ohci;
1298         dma_addr_t d_bus, uninitialized_var(payload_bus);
1299         struct driver_data *driver_data;
1300         struct descriptor *d, *last;
1301         __le32 *header;
1302         int z, tcode;
1303
1304         d = context_get_descriptors(ctx, 4, &d_bus);
1305         if (d == NULL) {
1306                 packet->ack = RCODE_SEND_ERROR;
1307                 return -1;
1308         }
1309
1310         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1311         d[0].res_count = cpu_to_le16(packet->timestamp);
1312
1313         /*
1314          * The DMA format for asynchronous link packets is different
1315          * from the IEEE1394 layout, so shift the fields around
1316          * accordingly.
1317          */
1318
1319         tcode = (packet->header[0] >> 4) & 0x0f;
1320         header = (__le32 *) &d[1];
1321         switch (tcode) {
1322         case TCODE_WRITE_QUADLET_REQUEST:
1323         case TCODE_WRITE_BLOCK_REQUEST:
1324         case TCODE_WRITE_RESPONSE:
1325         case TCODE_READ_QUADLET_REQUEST:
1326         case TCODE_READ_BLOCK_REQUEST:
1327         case TCODE_READ_QUADLET_RESPONSE:
1328         case TCODE_READ_BLOCK_RESPONSE:
1329         case TCODE_LOCK_REQUEST:
1330         case TCODE_LOCK_RESPONSE:
1331                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1332                                         (packet->speed << 16));
1333                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1334                                         (packet->header[0] & 0xffff0000));
1335                 header[2] = cpu_to_le32(packet->header[2]);
1336
1337                 if (TCODE_IS_BLOCK_PACKET(tcode))
1338                         header[3] = cpu_to_le32(packet->header[3]);
1339                 else
1340                         header[3] = (__force __le32) packet->header[3];
1341
1342                 d[0].req_count = cpu_to_le16(packet->header_length);
1343                 break;
1344
1345         case TCODE_LINK_INTERNAL:
1346                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1347                                         (packet->speed << 16));
1348                 header[1] = cpu_to_le32(packet->header[1]);
1349                 header[2] = cpu_to_le32(packet->header[2]);
1350                 d[0].req_count = cpu_to_le16(12);
1351
1352                 if (is_ping_packet(&packet->header[1]))
1353                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1354                 break;
1355
1356         case TCODE_STREAM_DATA:
1357                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1358                                         (packet->speed << 16));
1359                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1360                 d[0].req_count = cpu_to_le16(8);
1361                 break;
1362
1363         default:
1364                 /* BUG(); */
1365                 packet->ack = RCODE_SEND_ERROR;
1366                 return -1;
1367         }
1368
1369         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1370         driver_data = (struct driver_data *) &d[3];
1371         driver_data->packet = packet;
1372         packet->driver_data = driver_data;
1373
1374         if (packet->payload_length > 0) {
1375                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1376                         payload_bus = dma_map_single(ohci->card.device,
1377                                                      packet->payload,
1378                                                      packet->payload_length,
1379                                                      DMA_TO_DEVICE);
1380                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1381                                 packet->ack = RCODE_SEND_ERROR;
1382                                 return -1;
1383                         }
1384                         packet->payload_bus     = payload_bus;
1385                         packet->payload_mapped  = true;
1386                 } else {
1387                         memcpy(driver_data->inline_data, packet->payload,
1388                                packet->payload_length);
1389                         payload_bus = d_bus + 3 * sizeof(*d);
1390                 }
1391
1392                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1393                 d[2].data_address = cpu_to_le32(payload_bus);
1394                 last = &d[2];
1395                 z = 3;
1396         } else {
1397                 last = &d[0];
1398                 z = 2;
1399         }
1400
1401         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1402                                      DESCRIPTOR_IRQ_ALWAYS |
1403                                      DESCRIPTOR_BRANCH_ALWAYS);
1404
1405         /* FIXME: Document how the locking works. */
1406         if (ohci->generation != packet->generation) {
1407                 if (packet->payload_mapped)
1408                         dma_unmap_single(ohci->card.device, payload_bus,
1409                                          packet->payload_length, DMA_TO_DEVICE);
1410                 packet->ack = RCODE_GENERATION;
1411                 return -1;
1412         }
1413
1414         context_append(ctx, d, z, 4 - z);
1415
1416         if (ctx->running)
1417                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1418         else
1419                 context_run(ctx, 0);
1420
1421         return 0;
1422 }
1423
1424 static void at_context_flush(struct context *ctx)
1425 {
1426         tasklet_disable(&ctx->tasklet);
1427
1428         ctx->flushing = true;
1429         context_tasklet((unsigned long)ctx);
1430         ctx->flushing = false;
1431
1432         tasklet_enable(&ctx->tasklet);
1433 }
1434
1435 static int handle_at_packet(struct context *context,
1436                             struct descriptor *d,
1437                             struct descriptor *last)
1438 {
1439         struct driver_data *driver_data;
1440         struct fw_packet *packet;
1441         struct fw_ohci *ohci = context->ohci;
1442         int evt;
1443
1444         if (last->transfer_status == 0 && !context->flushing)
1445                 /* This descriptor isn't done yet, stop iteration. */
1446                 return 0;
1447
1448         driver_data = (struct driver_data *) &d[3];
1449         packet = driver_data->packet;
1450         if (packet == NULL)
1451                 /* This packet was cancelled, just continue. */
1452                 return 1;
1453
1454         if (packet->payload_mapped)
1455                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1456                                  packet->payload_length, DMA_TO_DEVICE);
1457
1458         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1459         packet->timestamp = le16_to_cpu(last->res_count);
1460
1461         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1462
1463         switch (evt) {
1464         case OHCI1394_evt_timeout:
1465                 /* Async response transmit timed out. */
1466                 packet->ack = RCODE_CANCELLED;
1467                 break;
1468
1469         case OHCI1394_evt_flushed:
1470                 /*
1471                  * The packet was flushed should give same error as
1472                  * when we try to use a stale generation count.
1473                  */
1474                 packet->ack = RCODE_GENERATION;
1475                 break;
1476
1477         case OHCI1394_evt_missing_ack:
1478                 if (context->flushing)
1479                         packet->ack = RCODE_GENERATION;
1480                 else {
1481                         /*
1482                          * Using a valid (current) generation count, but the
1483                          * node is not on the bus or not sending acks.
1484                          */
1485                         packet->ack = RCODE_NO_ACK;
1486                 }
1487                 break;
1488
1489         case ACK_COMPLETE + 0x10:
1490         case ACK_PENDING + 0x10:
1491         case ACK_BUSY_X + 0x10:
1492         case ACK_BUSY_A + 0x10:
1493         case ACK_BUSY_B + 0x10:
1494         case ACK_DATA_ERROR + 0x10:
1495         case ACK_TYPE_ERROR + 0x10:
1496                 packet->ack = evt - 0x10;
1497                 break;
1498
1499         case OHCI1394_evt_no_status:
1500                 if (context->flushing) {
1501                         packet->ack = RCODE_GENERATION;
1502                         break;
1503                 }
1504                 /* fall through */
1505
1506         default:
1507                 packet->ack = RCODE_SEND_ERROR;
1508                 break;
1509         }
1510
1511         packet->callback(packet, &ohci->card, packet->ack);
1512
1513         return 1;
1514 }
1515
1516 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1517 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1518 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1519 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1520 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1521
1522 static void handle_local_rom(struct fw_ohci *ohci,
1523                              struct fw_packet *packet, u32 csr)
1524 {
1525         struct fw_packet response;
1526         int tcode, length, i;
1527
1528         tcode = HEADER_GET_TCODE(packet->header[0]);
1529         if (TCODE_IS_BLOCK_PACKET(tcode))
1530                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1531         else
1532                 length = 4;
1533
1534         i = csr - CSR_CONFIG_ROM;
1535         if (i + length > CONFIG_ROM_SIZE) {
1536                 fw_fill_response(&response, packet->header,
1537                                  RCODE_ADDRESS_ERROR, NULL, 0);
1538         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1539                 fw_fill_response(&response, packet->header,
1540                                  RCODE_TYPE_ERROR, NULL, 0);
1541         } else {
1542                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1543                                  (void *) ohci->config_rom + i, length);
1544         }
1545
1546         fw_core_handle_response(&ohci->card, &response);
1547 }
1548
1549 static void handle_local_lock(struct fw_ohci *ohci,
1550                               struct fw_packet *packet, u32 csr)
1551 {
1552         struct fw_packet response;
1553         int tcode, length, ext_tcode, sel, try;
1554         __be32 *payload, lock_old;
1555         u32 lock_arg, lock_data;
1556
1557         tcode = HEADER_GET_TCODE(packet->header[0]);
1558         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1559         payload = packet->payload;
1560         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1561
1562         if (tcode == TCODE_LOCK_REQUEST &&
1563             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1564                 lock_arg = be32_to_cpu(payload[0]);
1565                 lock_data = be32_to_cpu(payload[1]);
1566         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1567                 lock_arg = 0;
1568                 lock_data = 0;
1569         } else {
1570                 fw_fill_response(&response, packet->header,
1571                                  RCODE_TYPE_ERROR, NULL, 0);
1572                 goto out;
1573         }
1574
1575         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1576         reg_write(ohci, OHCI1394_CSRData, lock_data);
1577         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1578         reg_write(ohci, OHCI1394_CSRControl, sel);
1579
1580         for (try = 0; try < 20; try++)
1581                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1582                         lock_old = cpu_to_be32(reg_read(ohci,
1583                                                         OHCI1394_CSRData));
1584                         fw_fill_response(&response, packet->header,
1585                                          RCODE_COMPLETE,
1586                                          &lock_old, sizeof(lock_old));
1587                         goto out;
1588                 }
1589
1590         ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1591         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1592
1593  out:
1594         fw_core_handle_response(&ohci->card, &response);
1595 }
1596
1597 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1598 {
1599         u64 offset, csr;
1600
1601         if (ctx == &ctx->ohci->at_request_ctx) {
1602                 packet->ack = ACK_PENDING;
1603                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1604         }
1605
1606         offset =
1607                 ((unsigned long long)
1608                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1609                 packet->header[2];
1610         csr = offset - CSR_REGISTER_BASE;
1611
1612         /* Handle config rom reads. */
1613         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1614                 handle_local_rom(ctx->ohci, packet, csr);
1615         else switch (csr) {
1616         case CSR_BUS_MANAGER_ID:
1617         case CSR_BANDWIDTH_AVAILABLE:
1618         case CSR_CHANNELS_AVAILABLE_HI:
1619         case CSR_CHANNELS_AVAILABLE_LO:
1620                 handle_local_lock(ctx->ohci, packet, csr);
1621                 break;
1622         default:
1623                 if (ctx == &ctx->ohci->at_request_ctx)
1624                         fw_core_handle_request(&ctx->ohci->card, packet);
1625                 else
1626                         fw_core_handle_response(&ctx->ohci->card, packet);
1627                 break;
1628         }
1629
1630         if (ctx == &ctx->ohci->at_response_ctx) {
1631                 packet->ack = ACK_COMPLETE;
1632                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1633         }
1634 }
1635
1636 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1637 {
1638         unsigned long flags;
1639         int ret;
1640
1641         spin_lock_irqsave(&ctx->ohci->lock, flags);
1642
1643         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1644             ctx->ohci->generation == packet->generation) {
1645                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1646                 handle_local_request(ctx, packet);
1647                 return;
1648         }
1649
1650         ret = at_context_queue_packet(ctx, packet);
1651         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1652
1653         if (ret < 0)
1654                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1655
1656 }
1657
1658 static void detect_dead_context(struct fw_ohci *ohci,
1659                                 const char *name, unsigned int regs)
1660 {
1661         u32 ctl;
1662
1663         ctl = reg_read(ohci, CONTROL_SET(regs));
1664         if (ctl & CONTEXT_DEAD)
1665                 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1666                         name, evts[ctl & 0x1f]);
1667 }
1668
1669 static void handle_dead_contexts(struct fw_ohci *ohci)
1670 {
1671         unsigned int i;
1672         char name[8];
1673
1674         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1675         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1676         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1677         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1678         for (i = 0; i < 32; ++i) {
1679                 if (!(ohci->it_context_support & (1 << i)))
1680                         continue;
1681                 sprintf(name, "IT%u", i);
1682                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1683         }
1684         for (i = 0; i < 32; ++i) {
1685                 if (!(ohci->ir_context_support & (1 << i)))
1686                         continue;
1687                 sprintf(name, "IR%u", i);
1688                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1689         }
1690         /* TODO: maybe try to flush and restart the dead contexts */
1691 }
1692
1693 static u32 cycle_timer_ticks(u32 cycle_timer)
1694 {
1695         u32 ticks;
1696
1697         ticks = cycle_timer & 0xfff;
1698         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1699         ticks += (3072 * 8000) * (cycle_timer >> 25);
1700
1701         return ticks;
1702 }
1703
1704 /*
1705  * Some controllers exhibit one or more of the following bugs when updating the
1706  * iso cycle timer register:
1707  *  - When the lowest six bits are wrapping around to zero, a read that happens
1708  *    at the same time will return garbage in the lowest ten bits.
1709  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1710  *    not incremented for about 60 ns.
1711  *  - Occasionally, the entire register reads zero.
1712  *
1713  * To catch these, we read the register three times and ensure that the
1714  * difference between each two consecutive reads is approximately the same, i.e.
1715  * less than twice the other.  Furthermore, any negative difference indicates an
1716  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1717  * execute, so we have enough precision to compute the ratio of the differences.)
1718  */
1719 static u32 get_cycle_time(struct fw_ohci *ohci)
1720 {
1721         u32 c0, c1, c2;
1722         u32 t0, t1, t2;
1723         s32 diff01, diff12;
1724         int i;
1725
1726         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1727
1728         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1729                 i = 0;
1730                 c1 = c2;
1731                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1732                 do {
1733                         c0 = c1;
1734                         c1 = c2;
1735                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1736                         t0 = cycle_timer_ticks(c0);
1737                         t1 = cycle_timer_ticks(c1);
1738                         t2 = cycle_timer_ticks(c2);
1739                         diff01 = t1 - t0;
1740                         diff12 = t2 - t1;
1741                 } while ((diff01 <= 0 || diff12 <= 0 ||
1742                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1743                          && i++ < 20);
1744         }
1745
1746         return c2;
1747 }
1748
1749 /*
1750  * This function has to be called at least every 64 seconds.  The bus_time
1751  * field stores not only the upper 25 bits of the BUS_TIME register but also
1752  * the most significant bit of the cycle timer in bit 6 so that we can detect
1753  * changes in this bit.
1754  */
1755 static u32 update_bus_time(struct fw_ohci *ohci)
1756 {
1757         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1758
1759         if (unlikely(!ohci->bus_time_running)) {
1760                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1761                 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1762                                  (cycle_time_seconds & 0x40);
1763                 ohci->bus_time_running = true;
1764         }
1765
1766         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1767                 ohci->bus_time += 0x40;
1768
1769         return ohci->bus_time | cycle_time_seconds;
1770 }
1771
1772 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1773 {
1774         int reg;
1775
1776         mutex_lock(&ohci->phy_reg_mutex);
1777         reg = write_phy_reg(ohci, 7, port_index);
1778         if (reg >= 0)
1779                 reg = read_phy_reg(ohci, 8);
1780         mutex_unlock(&ohci->phy_reg_mutex);
1781         if (reg < 0)
1782                 return reg;
1783
1784         switch (reg & 0x0f) {
1785         case 0x06:
1786                 return 2;       /* is child node (connected to parent node) */
1787         case 0x0e:
1788                 return 3;       /* is parent node (connected to child node) */
1789         }
1790         return 1;               /* not connected */
1791 }
1792
1793 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1794         int self_id_count)
1795 {
1796         int i;
1797         u32 entry;
1798
1799         for (i = 0; i < self_id_count; i++) {
1800                 entry = ohci->self_id_buffer[i];
1801                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1802                         return -1;
1803                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1804                         return i;
1805         }
1806         return i;
1807 }
1808
1809 static int initiated_reset(struct fw_ohci *ohci)
1810 {
1811         int reg;
1812         int ret = 0;
1813
1814         mutex_lock(&ohci->phy_reg_mutex);
1815         reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1816         if (reg >= 0) {
1817                 reg = read_phy_reg(ohci, 8);
1818                 reg |= 0x40;
1819                 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1820                 if (reg >= 0) {
1821                         reg = read_phy_reg(ohci, 12); /* read register 12 */
1822                         if (reg >= 0) {
1823                                 if ((reg & 0x08) == 0x08) {
1824                                         /* bit 3 indicates "initiated reset" */
1825                                         ret = 0x2;
1826                                 }
1827                         }
1828                 }
1829         }
1830         mutex_unlock(&ohci->phy_reg_mutex);
1831         return ret;
1832 }
1833
1834 /*
1835  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1836  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1837  * Construct the selfID from phy register contents.
1838  */
1839 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1840 {
1841         int reg, i, pos, status;
1842         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1843         u32 self_id = 0x8040c800;
1844
1845         reg = reg_read(ohci, OHCI1394_NodeID);
1846         if (!(reg & OHCI1394_NodeID_idValid)) {
1847                 ohci_notice(ohci,
1848                             "node ID not valid, new bus reset in progress\n");
1849                 return -EBUSY;
1850         }
1851         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1852
1853         reg = ohci_read_phy_reg(&ohci->card, 4);
1854         if (reg < 0)
1855                 return reg;
1856         self_id |= ((reg & 0x07) << 8); /* power class */
1857
1858         reg = ohci_read_phy_reg(&ohci->card, 1);
1859         if (reg < 0)
1860                 return reg;
1861         self_id |= ((reg & 0x3f) << 16); /* gap count */
1862
1863         for (i = 0; i < 3; i++) {
1864                 status = get_status_for_port(ohci, i);
1865                 if (status < 0)
1866                         return status;
1867                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1868         }
1869
1870         self_id |= initiated_reset(ohci);
1871
1872         pos = get_self_id_pos(ohci, self_id, self_id_count);
1873         if (pos >= 0) {
1874                 memmove(&(ohci->self_id_buffer[pos+1]),
1875                         &(ohci->self_id_buffer[pos]),
1876                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1877                 ohci->self_id_buffer[pos] = self_id;
1878                 self_id_count++;
1879         }
1880         return self_id_count;
1881 }
1882
1883 static void bus_reset_work(struct work_struct *work)
1884 {
1885         struct fw_ohci *ohci =
1886                 container_of(work, struct fw_ohci, bus_reset_work);
1887         int self_id_count, generation, new_generation, i, j;
1888         u32 reg;
1889         void *free_rom = NULL;
1890         dma_addr_t free_rom_bus = 0;
1891         bool is_new_root;
1892
1893         reg = reg_read(ohci, OHCI1394_NodeID);
1894         if (!(reg & OHCI1394_NodeID_idValid)) {
1895                 ohci_notice(ohci,
1896                             "node ID not valid, new bus reset in progress\n");
1897                 return;
1898         }
1899         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1900                 ohci_notice(ohci, "malconfigured bus\n");
1901                 return;
1902         }
1903         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1904                                OHCI1394_NodeID_nodeNumber);
1905
1906         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1907         if (!(ohci->is_root && is_new_root))
1908                 reg_write(ohci, OHCI1394_LinkControlSet,
1909                           OHCI1394_LinkControl_cycleMaster);
1910         ohci->is_root = is_new_root;
1911
1912         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1913         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1914                 ohci_notice(ohci, "inconsistent self IDs\n");
1915                 return;
1916         }
1917         /*
1918          * The count in the SelfIDCount register is the number of
1919          * bytes in the self ID receive buffer.  Since we also receive
1920          * the inverted quadlets and a header quadlet, we shift one
1921          * bit extra to get the actual number of self IDs.
1922          */
1923         self_id_count = (reg >> 3) & 0xff;
1924
1925         if (self_id_count > 252) {
1926                 ohci_notice(ohci, "inconsistent self IDs\n");
1927                 return;
1928         }
1929
1930         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1931         rmb();
1932
1933         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1934                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1935                         /*
1936                          * If the invalid data looks like a cycle start packet,
1937                          * it's likely to be the result of the cycle master
1938                          * having a wrong gap count.  In this case, the self IDs
1939                          * so far are valid and should be processed so that the
1940                          * bus manager can then correct the gap count.
1941                          */
1942                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1943                                                         == 0xffff008f) {
1944                                 ohci_notice(ohci,
1945                                             "ignoring spurious self IDs\n");
1946                                 self_id_count = j;
1947                                 break;
1948                         } else {
1949                                 ohci_notice(ohci, "inconsistent self IDs\n");
1950                                 return;
1951                         }
1952                 }
1953                 ohci->self_id_buffer[j] =
1954                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1955         }
1956
1957         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1958                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1959                 if (self_id_count < 0) {
1960                         ohci_notice(ohci,
1961                                     "could not construct local self ID\n");
1962                         return;
1963                 }
1964         }
1965
1966         if (self_id_count == 0) {
1967                 ohci_notice(ohci, "inconsistent self IDs\n");
1968                 return;
1969         }
1970         rmb();
1971
1972         /*
1973          * Check the consistency of the self IDs we just read.  The
1974          * problem we face is that a new bus reset can start while we
1975          * read out the self IDs from the DMA buffer. If this happens,
1976          * the DMA buffer will be overwritten with new self IDs and we
1977          * will read out inconsistent data.  The OHCI specification
1978          * (section 11.2) recommends a technique similar to
1979          * linux/seqlock.h, where we remember the generation of the
1980          * self IDs in the buffer before reading them out and compare
1981          * it to the current generation after reading them out.  If
1982          * the two generations match we know we have a consistent set
1983          * of self IDs.
1984          */
1985
1986         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1987         if (new_generation != generation) {
1988                 ohci_notice(ohci, "new bus reset, discarding self ids\n");
1989                 return;
1990         }
1991
1992         /* FIXME: Document how the locking works. */
1993         spin_lock_irq(&ohci->lock);
1994
1995         ohci->generation = -1; /* prevent AT packet queueing */
1996         context_stop(&ohci->at_request_ctx);
1997         context_stop(&ohci->at_response_ctx);
1998
1999         spin_unlock_irq(&ohci->lock);
2000
2001         /*
2002          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2003          * packets in the AT queues and software needs to drain them.
2004          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2005          */
2006         at_context_flush(&ohci->at_request_ctx);
2007         at_context_flush(&ohci->at_response_ctx);
2008
2009         spin_lock_irq(&ohci->lock);
2010
2011         ohci->generation = generation;
2012         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2013
2014         if (ohci->quirks & QUIRK_RESET_PACKET)
2015                 ohci->request_generation = generation;
2016
2017         /*
2018          * This next bit is unrelated to the AT context stuff but we
2019          * have to do it under the spinlock also.  If a new config rom
2020          * was set up before this reset, the old one is now no longer
2021          * in use and we can free it. Update the config rom pointers
2022          * to point to the current config rom and clear the
2023          * next_config_rom pointer so a new update can take place.
2024          */
2025
2026         if (ohci->next_config_rom != NULL) {
2027                 if (ohci->next_config_rom != ohci->config_rom) {
2028                         free_rom      = ohci->config_rom;
2029                         free_rom_bus  = ohci->config_rom_bus;
2030                 }
2031                 ohci->config_rom      = ohci->next_config_rom;
2032                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
2033                 ohci->next_config_rom = NULL;
2034
2035                 /*
2036                  * Restore config_rom image and manually update
2037                  * config_rom registers.  Writing the header quadlet
2038                  * will indicate that the config rom is ready, so we
2039                  * do that last.
2040                  */
2041                 reg_write(ohci, OHCI1394_BusOptions,
2042                           be32_to_cpu(ohci->config_rom[2]));
2043                 ohci->config_rom[0] = ohci->next_header;
2044                 reg_write(ohci, OHCI1394_ConfigROMhdr,
2045                           be32_to_cpu(ohci->next_header));
2046         }
2047
2048 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2049         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2050         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2051 #endif
2052
2053         spin_unlock_irq(&ohci->lock);
2054
2055         if (free_rom)
2056                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2057                                   free_rom, free_rom_bus);
2058
2059         log_selfids(ohci, generation, self_id_count);
2060
2061         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2062                                  self_id_count, ohci->self_id_buffer,
2063                                  ohci->csr_state_setclear_abdicate);
2064         ohci->csr_state_setclear_abdicate = false;
2065 }
2066
2067 static irqreturn_t irq_handler(int irq, void *data)
2068 {
2069         struct fw_ohci *ohci = data;
2070         u32 event, iso_event;
2071         int i;
2072
2073         event = reg_read(ohci, OHCI1394_IntEventClear);
2074
2075         if (!event || !~event)
2076                 return IRQ_NONE;
2077
2078         /*
2079          * busReset and postedWriteErr must not be cleared yet
2080          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2081          */
2082         reg_write(ohci, OHCI1394_IntEventClear,
2083                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2084         log_irqs(ohci, event);
2085
2086         if (event & OHCI1394_selfIDComplete)
2087                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2088
2089         if (event & OHCI1394_RQPkt)
2090                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2091
2092         if (event & OHCI1394_RSPkt)
2093                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2094
2095         if (event & OHCI1394_reqTxComplete)
2096                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2097
2098         if (event & OHCI1394_respTxComplete)
2099                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2100
2101         if (event & OHCI1394_isochRx) {
2102                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2103                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2104
2105                 while (iso_event) {
2106                         i = ffs(iso_event) - 1;
2107                         tasklet_schedule(
2108                                 &ohci->ir_context_list[i].context.tasklet);
2109                         iso_event &= ~(1 << i);
2110                 }
2111         }
2112
2113         if (event & OHCI1394_isochTx) {
2114                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2115                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2116
2117                 while (iso_event) {
2118                         i = ffs(iso_event) - 1;
2119                         tasklet_schedule(
2120                                 &ohci->it_context_list[i].context.tasklet);
2121                         iso_event &= ~(1 << i);
2122                 }
2123         }
2124
2125         if (unlikely(event & OHCI1394_regAccessFail))
2126                 ohci_err(ohci, "register access failure\n");
2127
2128         if (unlikely(event & OHCI1394_postedWriteErr)) {
2129                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2130                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2131                 reg_write(ohci, OHCI1394_IntEventClear,
2132                           OHCI1394_postedWriteErr);
2133                 if (printk_ratelimit())
2134                         ohci_err(ohci, "PCI posted write error\n");
2135         }
2136
2137         if (unlikely(event & OHCI1394_cycleTooLong)) {
2138                 if (printk_ratelimit())
2139                         ohci_notice(ohci, "isochronous cycle too long\n");
2140                 reg_write(ohci, OHCI1394_LinkControlSet,
2141                           OHCI1394_LinkControl_cycleMaster);
2142         }
2143
2144         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2145                 /*
2146                  * We need to clear this event bit in order to make
2147                  * cycleMatch isochronous I/O work.  In theory we should
2148                  * stop active cycleMatch iso contexts now and restart
2149                  * them at least two cycles later.  (FIXME?)
2150                  */
2151                 if (printk_ratelimit())
2152                         ohci_notice(ohci, "isochronous cycle inconsistent\n");
2153         }
2154
2155         if (unlikely(event & OHCI1394_unrecoverableError))
2156                 handle_dead_contexts(ohci);
2157
2158         if (event & OHCI1394_cycle64Seconds) {
2159                 spin_lock(&ohci->lock);
2160                 update_bus_time(ohci);
2161                 spin_unlock(&ohci->lock);
2162         } else
2163                 flush_writes(ohci);
2164
2165         return IRQ_HANDLED;
2166 }
2167
2168 static int software_reset(struct fw_ohci *ohci)
2169 {
2170         u32 val;
2171         int i;
2172
2173         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2174         for (i = 0; i < 500; i++) {
2175                 val = reg_read(ohci, OHCI1394_HCControlSet);
2176                 if (!~val)
2177                         return -ENODEV; /* Card was ejected. */
2178
2179                 if (!(val & OHCI1394_HCControl_softReset))
2180                         return 0;
2181
2182                 msleep(1);
2183         }
2184
2185         return -EBUSY;
2186 }
2187
2188 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2189 {
2190         size_t size = length * 4;
2191
2192         memcpy(dest, src, size);
2193         if (size < CONFIG_ROM_SIZE)
2194                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2195 }
2196
2197 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2198 {
2199         bool enable_1394a;
2200         int ret, clear, set, offset;
2201
2202         /* Check if the driver should configure link and PHY. */
2203         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2204               OHCI1394_HCControl_programPhyEnable))
2205                 return 0;
2206
2207         /* Paranoia: check whether the PHY supports 1394a, too. */
2208         enable_1394a = false;
2209         ret = read_phy_reg(ohci, 2);
2210         if (ret < 0)
2211                 return ret;
2212         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2213                 ret = read_paged_phy_reg(ohci, 1, 8);
2214                 if (ret < 0)
2215                         return ret;
2216                 if (ret >= 1)
2217                         enable_1394a = true;
2218         }
2219
2220         if (ohci->quirks & QUIRK_NO_1394A)
2221                 enable_1394a = false;
2222
2223         /* Configure PHY and link consistently. */
2224         if (enable_1394a) {
2225                 clear = 0;
2226                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2227         } else {
2228                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2229                 set = 0;
2230         }
2231         ret = update_phy_reg(ohci, 5, clear, set);
2232         if (ret < 0)
2233                 return ret;
2234
2235         if (enable_1394a)
2236                 offset = OHCI1394_HCControlSet;
2237         else
2238                 offset = OHCI1394_HCControlClear;
2239         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2240
2241         /* Clean up: configuration has been taken care of. */
2242         reg_write(ohci, OHCI1394_HCControlClear,
2243                   OHCI1394_HCControl_programPhyEnable);
2244
2245         return 0;
2246 }
2247
2248 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2249 {
2250         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2251         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2252         int reg, i;
2253
2254         reg = read_phy_reg(ohci, 2);
2255         if (reg < 0)
2256                 return reg;
2257         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2258                 return 0;
2259
2260         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2261                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2262                 if (reg < 0)
2263                         return reg;
2264                 if (reg != id[i])
2265                         return 0;
2266         }
2267         return 1;
2268 }
2269
2270 static int ohci_enable(struct fw_card *card,
2271                        const __be32 *config_rom, size_t length)
2272 {
2273         struct fw_ohci *ohci = fw_ohci(card);
2274         u32 lps, version, irqs;
2275         int i, ret;
2276
2277         if (software_reset(ohci)) {
2278                 ohci_err(ohci, "failed to reset ohci card\n");
2279                 return -EBUSY;
2280         }
2281
2282         /*
2283          * Now enable LPS, which we need in order to start accessing
2284          * most of the registers.  In fact, on some cards (ALI M5251),
2285          * accessing registers in the SClk domain without LPS enabled
2286          * will lock up the machine.  Wait 50msec to make sure we have
2287          * full link enabled.  However, with some cards (well, at least
2288          * a JMicron PCIe card), we have to try again sometimes.
2289          *
2290          * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2291          * cannot actually use the phy at that time.  These need tens of
2292          * millisecods pause between LPS write and first phy access too.
2293          *
2294          * But do not wait for 50msec on Agere/LSI cards.  Their phy
2295          * arbitration state machine may time out during such a long wait.
2296          */
2297
2298         reg_write(ohci, OHCI1394_HCControlSet,
2299                   OHCI1394_HCControl_LPS |
2300                   OHCI1394_HCControl_postedWriteEnable);
2301         flush_writes(ohci);
2302
2303         if (!(ohci->quirks & QUIRK_PHY_LCTRL_TIMEOUT))
2304                 msleep(50);
2305
2306         for (lps = 0, i = 0; !lps && i < 150; i++) {
2307                 msleep(1);
2308                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2309                       OHCI1394_HCControl_LPS;
2310         }
2311
2312         if (!lps) {
2313                 ohci_err(ohci, "failed to set Link Power Status\n");
2314                 return -EIO;
2315         }
2316
2317         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2318                 ret = probe_tsb41ba3d(ohci);
2319                 if (ret < 0)
2320                         return ret;
2321                 if (ret)
2322                         ohci_notice(ohci, "local TSB41BA3D phy\n");
2323                 else
2324                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2325         }
2326
2327         reg_write(ohci, OHCI1394_HCControlClear,
2328                   OHCI1394_HCControl_noByteSwapData);
2329
2330         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2331         reg_write(ohci, OHCI1394_LinkControlSet,
2332                   OHCI1394_LinkControl_cycleTimerEnable |
2333                   OHCI1394_LinkControl_cycleMaster);
2334
2335         reg_write(ohci, OHCI1394_ATRetries,
2336                   OHCI1394_MAX_AT_REQ_RETRIES |
2337                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2338                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2339                   (200 << 16));
2340
2341         ohci->bus_time_running = false;
2342
2343         for (i = 0; i < 32; i++)
2344                 if (ohci->ir_context_support & (1 << i))
2345                         reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2346                                   IR_CONTEXT_MULTI_CHANNEL_MODE);
2347
2348         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2349         if (version >= OHCI_VERSION_1_1) {
2350                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2351                           0xfffffffe);
2352                 card->broadcast_channel_auto_allocated = true;
2353         }
2354
2355         /* Get implemented bits of the priority arbitration request counter. */
2356         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2357         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2358         reg_write(ohci, OHCI1394_FairnessControl, 0);
2359         card->priority_budget_implemented = ohci->pri_req_max != 0;
2360
2361         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2362         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2363         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2364
2365         ret = configure_1394a_enhancements(ohci);
2366         if (ret < 0)
2367                 return ret;
2368
2369         /* Activate link_on bit and contender bit in our self ID packets.*/
2370         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2371         if (ret < 0)
2372                 return ret;
2373
2374         /*
2375          * When the link is not yet enabled, the atomic config rom
2376          * update mechanism described below in ohci_set_config_rom()
2377          * is not active.  We have to update ConfigRomHeader and
2378          * BusOptions manually, and the write to ConfigROMmap takes
2379          * effect immediately.  We tie this to the enabling of the
2380          * link, so we have a valid config rom before enabling - the
2381          * OHCI requires that ConfigROMhdr and BusOptions have valid
2382          * values before enabling.
2383          *
2384          * However, when the ConfigROMmap is written, some controllers
2385          * always read back quadlets 0 and 2 from the config rom to
2386          * the ConfigRomHeader and BusOptions registers on bus reset.
2387          * They shouldn't do that in this initial case where the link
2388          * isn't enabled.  This means we have to use the same
2389          * workaround here, setting the bus header to 0 and then write
2390          * the right values in the bus reset tasklet.
2391          */
2392
2393         if (config_rom) {
2394                 ohci->next_config_rom =
2395                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2396                                            &ohci->next_config_rom_bus,
2397                                            GFP_KERNEL);
2398                 if (ohci->next_config_rom == NULL)
2399                         return -ENOMEM;
2400
2401                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2402         } else {
2403                 /*
2404                  * In the suspend case, config_rom is NULL, which
2405                  * means that we just reuse the old config rom.
2406                  */
2407                 ohci->next_config_rom = ohci->config_rom;
2408                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2409         }
2410
2411         ohci->next_header = ohci->next_config_rom[0];
2412         ohci->next_config_rom[0] = 0;
2413         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2414         reg_write(ohci, OHCI1394_BusOptions,
2415                   be32_to_cpu(ohci->next_config_rom[2]));
2416         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2417
2418         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2419
2420         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2421                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2422                 OHCI1394_isochTx | OHCI1394_isochRx |
2423                 OHCI1394_postedWriteErr |
2424                 OHCI1394_selfIDComplete |
2425                 OHCI1394_regAccessFail |
2426                 OHCI1394_cycleInconsistent |
2427                 OHCI1394_unrecoverableError |
2428                 OHCI1394_cycleTooLong |
2429                 OHCI1394_masterIntEnable;
2430         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2431                 irqs |= OHCI1394_busReset;
2432         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2433
2434         reg_write(ohci, OHCI1394_HCControlSet,
2435                   OHCI1394_HCControl_linkEnable |
2436                   OHCI1394_HCControl_BIBimageValid);
2437
2438         reg_write(ohci, OHCI1394_LinkControlSet,
2439                   OHCI1394_LinkControl_rcvSelfID |
2440                   OHCI1394_LinkControl_rcvPhyPkt);
2441
2442         ar_context_run(&ohci->ar_request_ctx);
2443         ar_context_run(&ohci->ar_response_ctx);
2444
2445         flush_writes(ohci);
2446
2447         /* We are ready to go, reset bus to finish initialization. */
2448         fw_schedule_bus_reset(&ohci->card, false, true);
2449
2450         return 0;
2451 }
2452
2453 static int ohci_set_config_rom(struct fw_card *card,
2454                                const __be32 *config_rom, size_t length)
2455 {
2456         struct fw_ohci *ohci;
2457         __be32 *next_config_rom;
2458         dma_addr_t uninitialized_var(next_config_rom_bus);
2459
2460         ohci = fw_ohci(card);
2461
2462         /*
2463          * When the OHCI controller is enabled, the config rom update
2464          * mechanism is a bit tricky, but easy enough to use.  See
2465          * section 5.5.6 in the OHCI specification.
2466          *
2467          * The OHCI controller caches the new config rom address in a
2468          * shadow register (ConfigROMmapNext) and needs a bus reset
2469          * for the changes to take place.  When the bus reset is
2470          * detected, the controller loads the new values for the
2471          * ConfigRomHeader and BusOptions registers from the specified
2472          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2473          * shadow register. All automatically and atomically.
2474          *
2475          * Now, there's a twist to this story.  The automatic load of
2476          * ConfigRomHeader and BusOptions doesn't honor the
2477          * noByteSwapData bit, so with a be32 config rom, the
2478          * controller will load be32 values in to these registers
2479          * during the atomic update, even on litte endian
2480          * architectures.  The workaround we use is to put a 0 in the
2481          * header quadlet; 0 is endian agnostic and means that the
2482          * config rom isn't ready yet.  In the bus reset tasklet we
2483          * then set up the real values for the two registers.
2484          *
2485          * We use ohci->lock to avoid racing with the code that sets
2486          * ohci->next_config_rom to NULL (see bus_reset_work).
2487          */
2488
2489         next_config_rom =
2490                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2491                                    &next_config_rom_bus, GFP_KERNEL);
2492         if (next_config_rom == NULL)
2493                 return -ENOMEM;
2494
2495         spin_lock_irq(&ohci->lock);
2496
2497         /*
2498          * If there is not an already pending config_rom update,
2499          * push our new allocation into the ohci->next_config_rom
2500          * and then mark the local variable as null so that we
2501          * won't deallocate the new buffer.
2502          *
2503          * OTOH, if there is a pending config_rom update, just
2504          * use that buffer with the new config_rom data, and
2505          * let this routine free the unused DMA allocation.
2506          */
2507
2508         if (ohci->next_config_rom == NULL) {
2509                 ohci->next_config_rom = next_config_rom;
2510                 ohci->next_config_rom_bus = next_config_rom_bus;
2511                 next_config_rom = NULL;
2512         }
2513
2514         copy_config_rom(ohci->next_config_rom, config_rom, length);
2515
2516         ohci->next_header = config_rom[0];
2517         ohci->next_config_rom[0] = 0;
2518
2519         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2520
2521         spin_unlock_irq(&ohci->lock);
2522
2523         /* If we didn't use the DMA allocation, delete it. */
2524         if (next_config_rom != NULL)
2525                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2526                                   next_config_rom, next_config_rom_bus);
2527
2528         /*
2529          * Now initiate a bus reset to have the changes take
2530          * effect. We clean up the old config rom memory and DMA
2531          * mappings in the bus reset tasklet, since the OHCI
2532          * controller could need to access it before the bus reset
2533          * takes effect.
2534          */
2535
2536         fw_schedule_bus_reset(&ohci->card, true, true);
2537
2538         return 0;
2539 }
2540
2541 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2542 {
2543         struct fw_ohci *ohci = fw_ohci(card);
2544
2545         at_context_transmit(&ohci->at_request_ctx, packet);
2546 }
2547
2548 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2549 {
2550         struct fw_ohci *ohci = fw_ohci(card);
2551
2552         at_context_transmit(&ohci->at_response_ctx, packet);
2553 }
2554
2555 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2556 {
2557         struct fw_ohci *ohci = fw_ohci(card);
2558         struct context *ctx = &ohci->at_request_ctx;
2559         struct driver_data *driver_data = packet->driver_data;
2560         int ret = -ENOENT;
2561
2562         tasklet_disable(&ctx->tasklet);
2563
2564         if (packet->ack != 0)
2565                 goto out;
2566
2567         if (packet->payload_mapped)
2568                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2569                                  packet->payload_length, DMA_TO_DEVICE);
2570
2571         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2572         driver_data->packet = NULL;
2573         packet->ack = RCODE_CANCELLED;
2574         packet->callback(packet, &ohci->card, packet->ack);
2575         ret = 0;
2576  out:
2577         tasklet_enable(&ctx->tasklet);
2578
2579         return ret;
2580 }
2581
2582 static int ohci_enable_phys_dma(struct fw_card *card,
2583                                 int node_id, int generation)
2584 {
2585 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2586         return 0;
2587 #else
2588         struct fw_ohci *ohci = fw_ohci(card);
2589         unsigned long flags;
2590         int n, ret = 0;
2591
2592         /*
2593          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2594          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2595          */
2596
2597         spin_lock_irqsave(&ohci->lock, flags);
2598
2599         if (ohci->generation != generation) {
2600                 ret = -ESTALE;
2601                 goto out;
2602         }
2603
2604         /*
2605          * Note, if the node ID contains a non-local bus ID, physical DMA is
2606          * enabled for _all_ nodes on remote buses.
2607          */
2608
2609         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2610         if (n < 32)
2611                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2612         else
2613                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2614
2615         flush_writes(ohci);
2616  out:
2617         spin_unlock_irqrestore(&ohci->lock, flags);
2618
2619         return ret;
2620 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2621 }
2622
2623 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2624 {
2625         struct fw_ohci *ohci = fw_ohci(card);
2626         unsigned long flags;
2627         u32 value;
2628
2629         switch (csr_offset) {
2630         case CSR_STATE_CLEAR:
2631         case CSR_STATE_SET:
2632                 if (ohci->is_root &&
2633                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2634                      OHCI1394_LinkControl_cycleMaster))
2635                         value = CSR_STATE_BIT_CMSTR;
2636                 else
2637                         value = 0;
2638                 if (ohci->csr_state_setclear_abdicate)
2639                         value |= CSR_STATE_BIT_ABDICATE;
2640
2641                 return value;
2642
2643         case CSR_NODE_IDS:
2644                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2645
2646         case CSR_CYCLE_TIME:
2647                 return get_cycle_time(ohci);
2648
2649         case CSR_BUS_TIME:
2650                 /*
2651                  * We might be called just after the cycle timer has wrapped
2652                  * around but just before the cycle64Seconds handler, so we
2653                  * better check here, too, if the bus time needs to be updated.
2654                  */
2655                 spin_lock_irqsave(&ohci->lock, flags);
2656                 value = update_bus_time(ohci);
2657                 spin_unlock_irqrestore(&ohci->lock, flags);
2658                 return value;
2659
2660         case CSR_BUSY_TIMEOUT:
2661                 value = reg_read(ohci, OHCI1394_ATRetries);
2662                 return (value >> 4) & 0x0ffff00f;
2663
2664         case CSR_PRIORITY_BUDGET:
2665                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2666                         (ohci->pri_req_max << 8);
2667
2668         default:
2669                 WARN_ON(1);
2670                 return 0;
2671         }
2672 }
2673
2674 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2675 {
2676         struct fw_ohci *ohci = fw_ohci(card);
2677         unsigned long flags;
2678
2679         switch (csr_offset) {
2680         case CSR_STATE_CLEAR:
2681                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2682                         reg_write(ohci, OHCI1394_LinkControlClear,
2683                                   OHCI1394_LinkControl_cycleMaster);
2684                         flush_writes(ohci);
2685                 }
2686                 if (value & CSR_STATE_BIT_ABDICATE)
2687                         ohci->csr_state_setclear_abdicate = false;
2688                 break;
2689
2690         case CSR_STATE_SET:
2691                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2692                         reg_write(ohci, OHCI1394_LinkControlSet,
2693                                   OHCI1394_LinkControl_cycleMaster);
2694                         flush_writes(ohci);
2695                 }
2696                 if (value & CSR_STATE_BIT_ABDICATE)
2697                         ohci->csr_state_setclear_abdicate = true;
2698                 break;
2699
2700         case CSR_NODE_IDS:
2701                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2702                 flush_writes(ohci);
2703                 break;
2704
2705         case CSR_CYCLE_TIME:
2706                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2707                 reg_write(ohci, OHCI1394_IntEventSet,
2708                           OHCI1394_cycleInconsistent);
2709                 flush_writes(ohci);
2710                 break;
2711
2712         case CSR_BUS_TIME:
2713                 spin_lock_irqsave(&ohci->lock, flags);
2714                 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2715                                  (value & ~0x7f);
2716                 spin_unlock_irqrestore(&ohci->lock, flags);
2717                 break;
2718
2719         case CSR_BUSY_TIMEOUT:
2720                 value = (value & 0xf) | ((value & 0xf) << 4) |
2721                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2722                 reg_write(ohci, OHCI1394_ATRetries, value);
2723                 flush_writes(ohci);
2724                 break;
2725
2726         case CSR_PRIORITY_BUDGET:
2727                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2728                 flush_writes(ohci);
2729                 break;
2730
2731         default:
2732                 WARN_ON(1);
2733                 break;
2734         }
2735 }
2736
2737 static void flush_iso_completions(struct iso_context *ctx)
2738 {
2739         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2740                               ctx->header_length, ctx->header,
2741                               ctx->base.callback_data);
2742         ctx->header_length = 0;
2743 }
2744
2745 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2746 {
2747         u32 *ctx_hdr;
2748
2749         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
2750                 flush_iso_completions(ctx);
2751
2752         ctx_hdr = ctx->header + ctx->header_length;
2753         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2754
2755         /*
2756          * The two iso header quadlets are byteswapped to little
2757          * endian by the controller, but we want to present them
2758          * as big endian for consistency with the bus endianness.
2759          */
2760         if (ctx->base.header_size > 0)
2761                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2762         if (ctx->base.header_size > 4)
2763                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2764         if (ctx->base.header_size > 8)
2765                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2766         ctx->header_length += ctx->base.header_size;
2767 }
2768
2769 static int handle_ir_packet_per_buffer(struct context *context,
2770                                        struct descriptor *d,
2771                                        struct descriptor *last)
2772 {
2773         struct iso_context *ctx =
2774                 container_of(context, struct iso_context, context);
2775         struct descriptor *pd;
2776         u32 buffer_dma;
2777
2778         for (pd = d; pd <= last; pd++)
2779                 if (pd->transfer_status)
2780                         break;
2781         if (pd > last)
2782                 /* Descriptor(s) not done yet, stop iteration */
2783                 return 0;
2784
2785         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2786                 d++;
2787                 buffer_dma = le32_to_cpu(d->data_address);
2788                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2789                                               buffer_dma & PAGE_MASK,
2790                                               buffer_dma & ~PAGE_MASK,
2791                                               le16_to_cpu(d->req_count),
2792                                               DMA_FROM_DEVICE);
2793         }
2794
2795         copy_iso_headers(ctx, (u32 *) (last + 1));
2796
2797         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2798                 flush_iso_completions(ctx);
2799
2800         return 1;
2801 }
2802
2803 /* d == last because each descriptor block is only a single descriptor. */
2804 static int handle_ir_buffer_fill(struct context *context,
2805                                  struct descriptor *d,
2806                                  struct descriptor *last)
2807 {
2808         struct iso_context *ctx =
2809                 container_of(context, struct iso_context, context);
2810         unsigned int req_count, res_count, completed;
2811         u32 buffer_dma;
2812
2813         req_count = le16_to_cpu(last->req_count);
2814         res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2815         completed = req_count - res_count;
2816         buffer_dma = le32_to_cpu(last->data_address);
2817
2818         if (completed > 0) {
2819                 ctx->mc_buffer_bus = buffer_dma;
2820                 ctx->mc_completed = completed;
2821         }
2822
2823         if (res_count != 0)
2824                 /* Descriptor(s) not done yet, stop iteration */
2825                 return 0;
2826
2827         dma_sync_single_range_for_cpu(context->ohci->card.device,
2828                                       buffer_dma & PAGE_MASK,
2829                                       buffer_dma & ~PAGE_MASK,
2830                                       completed, DMA_FROM_DEVICE);
2831
2832         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2833                 ctx->base.callback.mc(&ctx->base,
2834                                       buffer_dma + completed,
2835                                       ctx->base.callback_data);
2836                 ctx->mc_completed = 0;
2837         }
2838
2839         return 1;
2840 }
2841
2842 static void flush_ir_buffer_fill(struct iso_context *ctx)
2843 {
2844         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2845                                       ctx->mc_buffer_bus & PAGE_MASK,
2846                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2847                                       ctx->mc_completed, DMA_FROM_DEVICE);
2848
2849         ctx->base.callback.mc(&ctx->base,
2850                               ctx->mc_buffer_bus + ctx->mc_completed,
2851                               ctx->base.callback_data);
2852         ctx->mc_completed = 0;
2853 }
2854
2855 static inline void sync_it_packet_for_cpu(struct context *context,
2856                                           struct descriptor *pd)
2857 {
2858         __le16 control;
2859         u32 buffer_dma;
2860
2861         /* only packets beginning with OUTPUT_MORE* have data buffers */
2862         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2863                 return;
2864
2865         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2866         pd += 2;
2867
2868         /*
2869          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2870          * data buffer is in the context program's coherent page and must not
2871          * be synced.
2872          */
2873         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2874             (context->current_bus          & PAGE_MASK)) {
2875                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2876                         return;
2877                 pd++;
2878         }
2879
2880         do {
2881                 buffer_dma = le32_to_cpu(pd->data_address);
2882                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2883                                               buffer_dma & PAGE_MASK,
2884                                               buffer_dma & ~PAGE_MASK,
2885                                               le16_to_cpu(pd->req_count),
2886                                               DMA_TO_DEVICE);
2887                 control = pd->control;
2888                 pd++;
2889         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2890 }
2891
2892 static int handle_it_packet(struct context *context,
2893                             struct descriptor *d,
2894                             struct descriptor *last)
2895 {
2896         struct iso_context *ctx =
2897                 container_of(context, struct iso_context, context);
2898         struct descriptor *pd;
2899         __be32 *ctx_hdr;
2900
2901         for (pd = d; pd <= last; pd++)
2902                 if (pd->transfer_status)
2903                         break;
2904         if (pd > last)
2905                 /* Descriptor(s) not done yet, stop iteration */
2906                 return 0;
2907
2908         sync_it_packet_for_cpu(context, d);
2909
2910         if (ctx->header_length + 4 > PAGE_SIZE)
2911                 flush_iso_completions(ctx);
2912
2913         ctx_hdr = ctx->header + ctx->header_length;
2914         ctx->last_timestamp = le16_to_cpu(last->res_count);
2915         /* Present this value as big-endian to match the receive code */
2916         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2917                                le16_to_cpu(pd->res_count));
2918         ctx->header_length += 4;
2919
2920         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2921                 flush_iso_completions(ctx);
2922
2923         return 1;
2924 }
2925
2926 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2927 {
2928         u32 hi = channels >> 32, lo = channels;
2929
2930         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2931         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2932         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2933         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2934         mmiowb();
2935         ohci->mc_channels = channels;
2936 }
2937
2938 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2939                                 int type, int channel, size_t header_size)
2940 {
2941         struct fw_ohci *ohci = fw_ohci(card);
2942         struct iso_context *uninitialized_var(ctx);
2943         descriptor_callback_t uninitialized_var(callback);
2944         u64 *uninitialized_var(channels);
2945         u32 *uninitialized_var(mask), uninitialized_var(regs);
2946         int index, ret = -EBUSY;
2947
2948         spin_lock_irq(&ohci->lock);
2949
2950         switch (type) {
2951         case FW_ISO_CONTEXT_TRANSMIT:
2952                 mask     = &ohci->it_context_mask;
2953                 callback = handle_it_packet;
2954                 index    = ffs(*mask) - 1;
2955                 if (index >= 0) {
2956                         *mask &= ~(1 << index);
2957                         regs = OHCI1394_IsoXmitContextBase(index);
2958                         ctx  = &ohci->it_context_list[index];
2959                 }
2960                 break;
2961
2962         case FW_ISO_CONTEXT_RECEIVE:
2963                 channels = &ohci->ir_context_channels;
2964                 mask     = &ohci->ir_context_mask;
2965                 callback = handle_ir_packet_per_buffer;
2966                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2967                 if (index >= 0) {
2968                         *channels &= ~(1ULL << channel);
2969                         *mask     &= ~(1 << index);
2970                         regs = OHCI1394_IsoRcvContextBase(index);
2971                         ctx  = &ohci->ir_context_list[index];
2972                 }
2973                 break;
2974
2975         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2976                 mask     = &ohci->ir_context_mask;
2977                 callback = handle_ir_buffer_fill;
2978                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2979                 if (index >= 0) {
2980                         ohci->mc_allocated = true;
2981                         *mask &= ~(1 << index);
2982                         regs = OHCI1394_IsoRcvContextBase(index);
2983                         ctx  = &ohci->ir_context_list[index];
2984                 }
2985                 break;
2986
2987         default:
2988                 index = -1;
2989                 ret = -ENOSYS;
2990         }
2991
2992         spin_unlock_irq(&ohci->lock);
2993
2994         if (index < 0)
2995                 return ERR_PTR(ret);
2996
2997         memset(ctx, 0, sizeof(*ctx));
2998         ctx->header_length = 0;
2999         ctx->header = (void *) __get_free_page(GFP_KERNEL);
3000         if (ctx->header == NULL) {
3001                 ret = -ENOMEM;
3002                 goto out;
3003         }
3004         ret = context_init(&ctx->context, ohci, regs, callback);
3005         if (ret < 0)
3006                 goto out_with_header;
3007
3008         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3009                 set_multichannel_mask(ohci, 0);
3010                 ctx->mc_completed = 0;
3011         }
3012
3013         return &ctx->base;
3014
3015  out_with_header:
3016         free_page((unsigned long)ctx->header);
3017  out:
3018         spin_lock_irq(&ohci->lock);
3019
3020         switch (type) {
3021         case FW_ISO_CONTEXT_RECEIVE:
3022                 *channels |= 1ULL << channel;
3023                 break;
3024
3025         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3026                 ohci->mc_allocated = false;
3027                 break;
3028         }
3029         *mask |= 1 << index;
3030
3031         spin_unlock_irq(&ohci->lock);
3032
3033         return ERR_PTR(ret);
3034 }
3035
3036 static int ohci_start_iso(struct fw_iso_context *base,
3037                           s32 cycle, u32 sync, u32 tags)
3038 {
3039         struct iso_context *ctx = container_of(base, struct iso_context, base);
3040         struct fw_ohci *ohci = ctx->context.ohci;
3041         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3042         int index;
3043
3044         /* the controller cannot start without any queued packets */
3045         if (ctx->context.last->branch_address == 0)
3046                 return -ENODATA;
3047
3048         switch (ctx->base.type) {
3049         case FW_ISO_CONTEXT_TRANSMIT:
3050                 index = ctx - ohci->it_context_list;
3051                 match = 0;
3052                 if (cycle >= 0)
3053                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3054                                 (cycle & 0x7fff) << 16;
3055
3056                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3057                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3058                 context_run(&ctx->context, match);
3059                 break;
3060
3061         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3062                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3063                 /* fall through */
3064         case FW_ISO_CONTEXT_RECEIVE:
3065                 index = ctx - ohci->ir_context_list;
3066                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3067                 if (cycle >= 0) {
3068                         match |= (cycle & 0x07fff) << 12;
3069                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3070                 }
3071
3072                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3073                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3074                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3075                 context_run(&ctx->context, control);
3076
3077                 ctx->sync = sync;
3078                 ctx->tags = tags;
3079
3080                 break;
3081         }
3082
3083         return 0;
3084 }
3085
3086 static int ohci_stop_iso(struct fw_iso_context *base)
3087 {
3088         struct fw_ohci *ohci = fw_ohci(base->card);
3089         struct iso_context *ctx = container_of(base, struct iso_context, base);
3090         int index;
3091
3092         switch (ctx->base.type) {
3093         case FW_ISO_CONTEXT_TRANSMIT:
3094                 index = ctx - ohci->it_context_list;
3095                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3096                 break;
3097
3098         case FW_ISO_CONTEXT_RECEIVE:
3099         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3100                 index = ctx - ohci->ir_context_list;
3101                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3102                 break;
3103         }
3104         flush_writes(ohci);
3105         context_stop(&ctx->context);
3106         tasklet_kill(&ctx->context.tasklet);
3107
3108         return 0;
3109 }
3110
3111 static void ohci_free_iso_context(struct fw_iso_context *base)
3112 {
3113         struct fw_ohci *ohci = fw_ohci(base->card);
3114         struct iso_context *ctx = container_of(base, struct iso_context, base);
3115         unsigned long flags;
3116         int index;
3117
3118         ohci_stop_iso(base);
3119         context_release(&ctx->context);
3120         free_page((unsigned long)ctx->header);
3121
3122         spin_lock_irqsave(&ohci->lock, flags);
3123
3124         switch (base->type) {
3125         case FW_ISO_CONTEXT_TRANSMIT:
3126                 index = ctx - ohci->it_context_list;
3127                 ohci->it_context_mask |= 1 << index;
3128                 break;
3129
3130         case FW_ISO_CONTEXT_RECEIVE:
3131                 index = ctx - ohci->ir_context_list;
3132                 ohci->ir_context_mask |= 1 << index;
3133                 ohci->ir_context_channels |= 1ULL << base->channel;
3134                 break;
3135
3136         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3137                 index = ctx - ohci->ir_context_list;
3138                 ohci->ir_context_mask |= 1 << index;
3139                 ohci->ir_context_channels |= ohci->mc_channels;
3140                 ohci->mc_channels = 0;
3141                 ohci->mc_allocated = false;
3142                 break;
3143         }
3144
3145         spin_unlock_irqrestore(&ohci->lock, flags);
3146 }
3147
3148 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3149 {
3150         struct fw_ohci *ohci = fw_ohci(base->card);
3151         unsigned long flags;
3152         int ret;
3153
3154         switch (base->type) {
3155         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3156
3157                 spin_lock_irqsave(&ohci->lock, flags);
3158
3159                 /* Don't allow multichannel to grab other contexts' channels. */
3160                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3161                         *channels = ohci->ir_context_channels;
3162                         ret = -EBUSY;
3163                 } else {
3164                         set_multichannel_mask(ohci, *channels);
3165                         ret = 0;
3166                 }
3167
3168                 spin_unlock_irqrestore(&ohci->lock, flags);
3169
3170                 break;
3171         default:
3172                 ret = -EINVAL;
3173         }
3174
3175         return ret;
3176 }
3177
3178 #ifdef CONFIG_PM
3179 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3180 {
3181         int i;
3182         struct iso_context *ctx;
3183
3184         for (i = 0 ; i < ohci->n_ir ; i++) {
3185                 ctx = &ohci->ir_context_list[i];
3186                 if (ctx->context.running)
3187                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3188         }
3189
3190         for (i = 0 ; i < ohci->n_it ; i++) {
3191                 ctx = &ohci->it_context_list[i];
3192                 if (ctx->context.running)
3193                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3194         }
3195 }
3196 #endif
3197
3198 static int queue_iso_transmit(struct iso_context *ctx,
3199                               struct fw_iso_packet *packet,
3200                               struct fw_iso_buffer *buffer,
3201                               unsigned long payload)
3202 {
3203         struct descriptor *d, *last, *pd;
3204         struct fw_iso_packet *p;
3205         __le32 *header;
3206         dma_addr_t d_bus, page_bus;
3207         u32 z, header_z, payload_z, irq;
3208         u32 payload_index, payload_end_index, next_page_index;
3209         int page, end_page, i, length, offset;
3210
3211         p = packet;
3212         payload_index = payload;
3213
3214         if (p->skip)
3215                 z = 1;
3216         else
3217                 z = 2;
3218         if (p->header_length > 0)
3219                 z++;
3220
3221         /* Determine the first page the payload isn't contained in. */
3222         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3223         if (p->payload_length > 0)
3224                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3225         else
3226                 payload_z = 0;
3227
3228         z += payload_z;
3229
3230         /* Get header size in number of descriptors. */
3231         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3232
3233         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3234         if (d == NULL)
3235                 return -ENOMEM;
3236
3237         if (!p->skip) {
3238                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3239                 d[0].req_count = cpu_to_le16(8);
3240                 /*
3241                  * Link the skip address to this descriptor itself.  This causes
3242                  * a context to skip a cycle whenever lost cycles or FIFO
3243                  * overruns occur, without dropping the data.  The application
3244                  * should then decide whether this is an error condition or not.
3245                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3246                  */
3247                 d[0].branch_address = cpu_to_le32(d_bus | z);
3248
3249                 header = (__le32 *) &d[1];
3250                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3251                                         IT_HEADER_TAG(p->tag) |
3252                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3253                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3254                                         IT_HEADER_SPEED(ctx->base.speed));
3255                 header[1] =
3256                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3257                                                           p->payload_length));
3258         }
3259
3260         if (p->header_length > 0) {
3261                 d[2].req_count    = cpu_to_le16(p->header_length);
3262                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3263                 memcpy(&d[z], p->header, p->header_length);
3264         }
3265
3266         pd = d + z - payload_z;
3267         payload_end_index = payload_index + p->payload_length;
3268         for (i = 0; i < payload_z; i++) {
3269                 page               = payload_index >> PAGE_SHIFT;
3270                 offset             = payload_index & ~PAGE_MASK;
3271                 next_page_index    = (page + 1) << PAGE_SHIFT;
3272                 length             =
3273                         min(next_page_index, payload_end_index) - payload_index;
3274                 pd[i].req_count    = cpu_to_le16(length);
3275
3276                 page_bus = page_private(buffer->pages[page]);
3277                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3278
3279                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3280                                                  page_bus, offset, length,
3281                                                  DMA_TO_DEVICE);
3282
3283                 payload_index += length;
3284         }
3285
3286         if (p->interrupt)
3287                 irq = DESCRIPTOR_IRQ_ALWAYS;
3288         else
3289                 irq = DESCRIPTOR_NO_IRQ;
3290
3291         last = z == 2 ? d : d + z - 1;
3292         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3293                                      DESCRIPTOR_STATUS |
3294                                      DESCRIPTOR_BRANCH_ALWAYS |
3295                                      irq);
3296
3297         context_append(&ctx->context, d, z, header_z);
3298
3299         return 0;
3300 }
3301
3302 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3303                                        struct fw_iso_packet *packet,
3304                                        struct fw_iso_buffer *buffer,
3305                                        unsigned long payload)
3306 {
3307         struct device *device = ctx->context.ohci->card.device;
3308         struct descriptor *d, *pd;
3309         dma_addr_t d_bus, page_bus;
3310         u32 z, header_z, rest;
3311         int i, j, length;
3312         int page, offset, packet_count, header_size, payload_per_buffer;
3313
3314         /*
3315          * The OHCI controller puts the isochronous header and trailer in the
3316          * buffer, so we need at least 8 bytes.
3317          */
3318         packet_count = packet->header_length / ctx->base.header_size;
3319         header_size  = max(ctx->base.header_size, (size_t)8);
3320
3321         /* Get header size in number of descriptors. */
3322         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3323         page     = payload >> PAGE_SHIFT;
3324         offset   = payload & ~PAGE_MASK;
3325         payload_per_buffer = packet->payload_length / packet_count;
3326
3327         for (i = 0; i < packet_count; i++) {
3328                 /* d points to the header descriptor */
3329                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3330                 d = context_get_descriptors(&ctx->context,
3331                                 z + header_z, &d_bus);
3332                 if (d == NULL)
3333                         return -ENOMEM;
3334
3335                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3336                                               DESCRIPTOR_INPUT_MORE);
3337                 if (packet->skip && i == 0)
3338                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3339                 d->req_count    = cpu_to_le16(header_size);
3340                 d->res_count    = d->req_count;
3341                 d->transfer_status = 0;
3342                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3343
3344                 rest = payload_per_buffer;
3345                 pd = d;
3346                 for (j = 1; j < z; j++) {
3347                         pd++;
3348                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3349                                                   DESCRIPTOR_INPUT_MORE);
3350
3351                         if (offset + rest < PAGE_SIZE)
3352                                 length = rest;
3353                         else
3354                                 length = PAGE_SIZE - offset;
3355                         pd->req_count = cpu_to_le16(length);
3356                         pd->res_count = pd->req_count;
3357                         pd->transfer_status = 0;
3358
3359                         page_bus = page_private(buffer->pages[page]);
3360                         pd->data_address = cpu_to_le32(page_bus + offset);
3361
3362                         dma_sync_single_range_for_device(device, page_bus,
3363                                                          offset, length,
3364                                                          DMA_FROM_DEVICE);
3365
3366                         offset = (offset + length) & ~PAGE_MASK;
3367                         rest -= length;
3368                         if (offset == 0)
3369                                 page++;
3370                 }
3371                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3372                                           DESCRIPTOR_INPUT_LAST |
3373                                           DESCRIPTOR_BRANCH_ALWAYS);
3374                 if (packet->interrupt && i == packet_count - 1)
3375                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3376
3377                 context_append(&ctx->context, d, z, header_z);
3378         }
3379
3380         return 0;
3381 }
3382
3383 static int queue_iso_buffer_fill(struct iso_context *ctx,
3384                                  struct fw_iso_packet *packet,
3385                                  struct fw_iso_buffer *buffer,
3386                                  unsigned long payload)
3387 {
3388         struct descriptor *d;
3389         dma_addr_t d_bus, page_bus;
3390         int page, offset, rest, z, i, length;
3391
3392         page   = payload >> PAGE_SHIFT;
3393         offset = payload & ~PAGE_MASK;
3394         rest   = packet->payload_length;
3395
3396         /* We need one descriptor for each page in the buffer. */
3397         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3398
3399         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3400                 return -EFAULT;
3401
3402         for (i = 0; i < z; i++) {
3403                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3404                 if (d == NULL)
3405                         return -ENOMEM;
3406
3407                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3408                                          DESCRIPTOR_BRANCH_ALWAYS);
3409                 if (packet->skip && i == 0)
3410                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3411                 if (packet->interrupt && i == z - 1)
3412                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3413
3414                 if (offset + rest < PAGE_SIZE)
3415                         length = rest;
3416                 else
3417                         length = PAGE_SIZE - offset;
3418                 d->req_count = cpu_to_le16(length);
3419                 d->res_count = d->req_count;
3420                 d->transfer_status = 0;
3421
3422                 page_bus = page_private(buffer->pages[page]);
3423                 d->data_address = cpu_to_le32(page_bus + offset);
3424
3425                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3426                                                  page_bus, offset, length,
3427                                                  DMA_FROM_DEVICE);
3428
3429                 rest -= length;
3430                 offset = 0;
3431                 page++;
3432
3433                 context_append(&ctx->context, d, 1, 0);
3434         }
3435
3436         return 0;
3437 }
3438
3439 static int ohci_queue_iso(struct fw_iso_context *base,
3440                           struct fw_iso_packet *packet,
3441                           struct fw_iso_buffer *buffer,
3442                           unsigned long payload)
3443 {
3444         struct iso_context *ctx = container_of(base, struct iso_context, base);
3445         unsigned long flags;
3446         int ret = -ENOSYS;
3447
3448         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3449         switch (base->type) {
3450         case FW_ISO_CONTEXT_TRANSMIT:
3451                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3452                 break;
3453         case FW_ISO_CONTEXT_RECEIVE:
3454                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3455                 break;
3456         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3457                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3458                 break;
3459         }
3460         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3461
3462         return ret;
3463 }
3464
3465 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3466 {
3467         struct context *ctx =
3468                         &container_of(base, struct iso_context, base)->context;
3469
3470         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3471 }
3472
3473 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3474 {
3475         struct iso_context *ctx = container_of(base, struct iso_context, base);
3476         int ret = 0;
3477
3478         tasklet_disable(&ctx->context.tasklet);
3479
3480         if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3481                 context_tasklet((unsigned long)&ctx->context);
3482
3483                 switch (base->type) {
3484                 case FW_ISO_CONTEXT_TRANSMIT:
3485                 case FW_ISO_CONTEXT_RECEIVE:
3486                         if (ctx->header_length != 0)
3487                                 flush_iso_completions(ctx);
3488                         break;
3489                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3490                         if (ctx->mc_completed != 0)
3491                                 flush_ir_buffer_fill(ctx);
3492                         break;
3493                 default:
3494                         ret = -ENOSYS;
3495                 }
3496
3497                 clear_bit_unlock(0, &ctx->flushing_completions);
3498                 smp_mb__after_clear_bit();
3499         }
3500
3501         tasklet_enable(&ctx->context.tasklet);
3502
3503         return ret;
3504 }
3505
3506 static const struct fw_card_driver ohci_driver = {
3507         .enable                 = ohci_enable,
3508         .read_phy_reg           = ohci_read_phy_reg,
3509         .update_phy_reg         = ohci_update_phy_reg,
3510         .set_config_rom         = ohci_set_config_rom,
3511         .send_request           = ohci_send_request,
3512         .send_response          = ohci_send_response,
3513         .cancel_packet          = ohci_cancel_packet,
3514         .enable_phys_dma        = ohci_enable_phys_dma,
3515         .read_csr               = ohci_read_csr,
3516         .write_csr              = ohci_write_csr,
3517
3518         .allocate_iso_context   = ohci_allocate_iso_context,
3519         .free_iso_context       = ohci_free_iso_context,
3520         .set_iso_channels       = ohci_set_iso_channels,
3521         .queue_iso              = ohci_queue_iso,
3522         .flush_queue_iso        = ohci_flush_queue_iso,
3523         .flush_iso_completions  = ohci_flush_iso_completions,
3524         .start_iso              = ohci_start_iso,
3525         .stop_iso               = ohci_stop_iso,
3526 };
3527
3528 #ifdef CONFIG_PPC_PMAC
3529 static void pmac_ohci_on(struct pci_dev *dev)
3530 {
3531         if (machine_is(powermac)) {
3532                 struct device_node *ofn = pci_device_to_OF_node(dev);
3533
3534                 if (ofn) {
3535                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3536                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3537                 }
3538         }
3539 }
3540
3541 static void pmac_ohci_off(struct pci_dev *dev)
3542 {
3543         if (machine_is(powermac)) {
3544                 struct device_node *ofn = pci_device_to_OF_node(dev);
3545
3546                 if (ofn) {
3547                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3548                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3549                 }
3550         }
3551 }
3552 #else
3553 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3554 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3555 #endif /* CONFIG_PPC_PMAC */
3556
3557 static int pci_probe(struct pci_dev *dev,
3558                                const struct pci_device_id *ent)
3559 {
3560         struct fw_ohci *ohci;
3561         u32 bus_options, max_receive, link_speed, version;
3562         u64 guid;
3563         int i, err;
3564         size_t size;
3565
3566         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3567                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3568                 return -ENOSYS;
3569         }
3570
3571         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3572         if (ohci == NULL) {
3573                 err = -ENOMEM;
3574                 goto fail;
3575         }
3576
3577         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3578
3579         pmac_ohci_on(dev);
3580
3581         err = pci_enable_device(dev);
3582         if (err) {
3583                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3584                 goto fail_free;
3585         }
3586
3587         pci_set_master(dev);
3588         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3589         pci_set_drvdata(dev, ohci);
3590
3591         spin_lock_init(&ohci->lock);
3592         mutex_init(&ohci->phy_reg_mutex);
3593
3594         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3595
3596         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3597             pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3598                 ohci_err(ohci, "invalid MMIO resource\n");
3599                 err = -ENXIO;
3600                 goto fail_disable;
3601         }
3602
3603         err = pci_request_region(dev, 0, ohci_driver_name);
3604         if (err) {
3605                 ohci_err(ohci, "MMIO resource unavailable\n");
3606                 goto fail_disable;
3607         }
3608
3609         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3610         if (ohci->registers == NULL) {
3611                 ohci_err(ohci, "failed to remap registers\n");
3612                 err = -ENXIO;
3613                 goto fail_iomem;
3614         }
3615
3616         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3617                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3618                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3619                      ohci_quirks[i].device == dev->device) &&
3620                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3621                      ohci_quirks[i].revision >= dev->revision)) {
3622                         ohci->quirks = ohci_quirks[i].flags;
3623                         break;
3624                 }
3625         if (param_quirks)
3626                 ohci->quirks = param_quirks;
3627
3628         /*
3629          * Because dma_alloc_coherent() allocates at least one page,
3630          * we save space by using a common buffer for the AR request/
3631          * response descriptors and the self IDs buffer.
3632          */
3633         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3634         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3635         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3636                                                PAGE_SIZE,
3637                                                &ohci->misc_buffer_bus,
3638                                                GFP_KERNEL);
3639         if (!ohci->misc_buffer) {
3640                 err = -ENOMEM;
3641                 goto fail_iounmap;
3642         }
3643
3644         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3645                               OHCI1394_AsReqRcvContextControlSet);
3646         if (err < 0)
3647                 goto fail_misc_buf;
3648
3649         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3650                               OHCI1394_AsRspRcvContextControlSet);
3651         if (err < 0)
3652                 goto fail_arreq_ctx;
3653
3654         err = context_init(&ohci->at_request_ctx, ohci,
3655                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3656         if (err < 0)
3657                 goto fail_arrsp_ctx;
3658
3659         err = context_init(&ohci->at_response_ctx, ohci,
3660                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3661         if (err < 0)
3662                 goto fail_atreq_ctx;
3663
3664         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3665         ohci->ir_context_channels = ~0ULL;
3666         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3667         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3668         ohci->ir_context_mask = ohci->ir_context_support;
3669         ohci->n_ir = hweight32(ohci->ir_context_mask);
3670         size = sizeof(struct iso_context) * ohci->n_ir;
3671         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3672
3673         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3674         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3675         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3676         ohci->it_context_mask = ohci->it_context_support;
3677         ohci->n_it = hweight32(ohci->it_context_mask);
3678         size = sizeof(struct iso_context) * ohci->n_it;
3679         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3680
3681         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3682                 err = -ENOMEM;
3683                 goto fail_contexts;
3684         }
3685
3686         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3687         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3688
3689         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3690         max_receive = (bus_options >> 12) & 0xf;
3691         link_speed = bus_options & 0x7;
3692         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3693                 reg_read(ohci, OHCI1394_GUIDLo);
3694
3695         if (!(ohci->quirks & QUIRK_NO_MSI))
3696                 pci_enable_msi(dev);
3697         if (request_irq(dev->irq, irq_handler,
3698                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3699                         ohci_driver_name, ohci)) {
3700                 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
3701                 err = -EIO;
3702                 goto fail_msi;
3703         }
3704
3705         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3706         if (err)
3707                 goto fail_irq;
3708
3709         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3710         ohci_notice(ohci,
3711                     "added OHCI v%x.%x device as card %d, "
3712                     "%d IR + %d IT contexts, quirks 0x%x\n",
3713                     version >> 16, version & 0xff, ohci->card.index,
3714                     ohci->n_ir, ohci->n_it, ohci->quirks);
3715
3716         return 0;
3717
3718  fail_irq:
3719         free_irq(dev->irq, ohci);
3720  fail_msi:
3721         pci_disable_msi(dev);
3722  fail_contexts:
3723         kfree(ohci->ir_context_list);
3724         kfree(ohci->it_context_list);
3725         context_release(&ohci->at_response_ctx);
3726  fail_atreq_ctx:
3727         context_release(&ohci->at_request_ctx);
3728  fail_arrsp_ctx:
3729         ar_context_release(&ohci->ar_response_ctx);
3730  fail_arreq_ctx:
3731         ar_context_release(&ohci->ar_request_ctx);
3732  fail_misc_buf:
3733         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3734                           ohci->misc_buffer, ohci->misc_buffer_bus);
3735  fail_iounmap:
3736         pci_iounmap(dev, ohci->registers);
3737  fail_iomem:
3738         pci_release_region(dev, 0);
3739  fail_disable:
3740         pci_disable_device(dev);
3741  fail_free:
3742         kfree(ohci);
3743         pmac_ohci_off(dev);
3744  fail:
3745         return err;
3746 }
3747
3748 static void pci_remove(struct pci_dev *dev)
3749 {
3750         struct fw_ohci *ohci = pci_get_drvdata(dev);
3751
3752         /*
3753          * If the removal is happening from the suspend state, LPS won't be
3754          * enabled and host registers (eg., IntMaskClear) won't be accessible.
3755          */
3756         if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3757                 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3758                 flush_writes(ohci);
3759         }
3760         cancel_work_sync(&ohci->bus_reset_work);
3761         fw_core_remove_card(&ohci->card);
3762
3763         /*
3764          * FIXME: Fail all pending packets here, now that the upper
3765          * layers can't queue any more.
3766          */
3767
3768         software_reset(ohci);
3769         free_irq(dev->irq, ohci);
3770
3771         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3772                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3773                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3774         if (ohci->config_rom)
3775                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3776                                   ohci->config_rom, ohci->config_rom_bus);
3777         ar_context_release(&ohci->ar_request_ctx);
3778         ar_context_release(&ohci->ar_response_ctx);
3779         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3780                           ohci->misc_buffer, ohci->misc_buffer_bus);
3781         context_release(&ohci->at_request_ctx);
3782         context_release(&ohci->at_response_ctx);
3783         kfree(ohci->it_context_list);
3784         kfree(ohci->ir_context_list);
3785         pci_disable_msi(dev);
3786         pci_iounmap(dev, ohci->registers);
3787         pci_release_region(dev, 0);
3788         pci_disable_device(dev);
3789         kfree(ohci);
3790         pmac_ohci_off(dev);
3791
3792         dev_notice(&dev->dev, "removed fw-ohci device\n");
3793 }
3794
3795 #ifdef CONFIG_PM
3796 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3797 {
3798         struct fw_ohci *ohci = pci_get_drvdata(dev);
3799         int err;
3800
3801         software_reset(ohci);
3802         err = pci_save_state(dev);
3803         if (err) {
3804                 ohci_err(ohci, "pci_save_state failed\n");
3805                 return err;
3806         }
3807         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3808         if (err)
3809                 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
3810         pmac_ohci_off(dev);
3811
3812         return 0;
3813 }
3814
3815 static int pci_resume(struct pci_dev *dev)
3816 {
3817         struct fw_ohci *ohci = pci_get_drvdata(dev);
3818         int err;
3819
3820         pmac_ohci_on(dev);
3821         pci_set_power_state(dev, PCI_D0);
3822         pci_restore_state(dev);
3823         err = pci_enable_device(dev);
3824         if (err) {
3825                 ohci_err(ohci, "pci_enable_device failed\n");
3826                 return err;
3827         }
3828
3829         /* Some systems don't setup GUID register on resume from ram  */
3830         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3831                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3832                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3833                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3834         }
3835
3836         err = ohci_enable(&ohci->card, NULL, 0);
3837         if (err)
3838                 return err;
3839
3840         ohci_resume_iso_dma(ohci);
3841
3842         return 0;
3843 }
3844 #endif
3845
3846 static const struct pci_device_id pci_table[] = {
3847         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3848         { }
3849 };
3850
3851 MODULE_DEVICE_TABLE(pci, pci_table);
3852
3853 static struct pci_driver fw_ohci_pci_driver = {
3854         .name           = ohci_driver_name,
3855         .id_table       = pci_table,
3856         .probe          = pci_probe,
3857         .remove         = pci_remove,
3858 #ifdef CONFIG_PM
3859         .resume         = pci_resume,
3860         .suspend        = pci_suspend,
3861 #endif
3862 };
3863
3864 module_pci_driver(fw_ohci_pci_driver);
3865
3866 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3867 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3868 MODULE_LICENSE("GPL");
3869
3870 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3871 MODULE_ALIAS("ohci1394");