2 * Intel D82875P Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
9 * Wang Zhenyu at intel.com
11 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
13 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/slab.h>
23 #define i82875p_printk(level, fmt, arg...) \
24 edac_printk(level, "i82875p", fmt, ##arg)
26 #define i82875p_mc_printk(mci, level, fmt, arg...) \
27 edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
29 #ifndef PCI_DEVICE_ID_INTEL_82875_0
30 #define PCI_DEVICE_ID_INTEL_82875_0 0x2578
31 #endif /* PCI_DEVICE_ID_INTEL_82875_0 */
33 #ifndef PCI_DEVICE_ID_INTEL_82875_6
34 #define PCI_DEVICE_ID_INTEL_82875_6 0x257e
35 #endif /* PCI_DEVICE_ID_INTEL_82875_6 */
37 /* four csrows in dual channel, eight in single channel */
38 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
40 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
41 #define I82875P_EAP 0x58 /* Error Address Pointer (32b)
47 #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
49 * 7:0 DRAM ECC Syndrome
52 #define I82875P_DES 0x5d /* DRAM Error Status (8b)
58 #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
61 * 9 non-DRAM lock error (ndlock)
62 * 8 Sftwr Generated SMI
65 * 5 MCH detects unimplemented cycle
66 * 4 AGP access outside GA
67 * 3 Invalid AGP access
68 * 2 Invalid GA translation table
69 * 1 Unsupported AGP command
73 #define I82875P_ERRCMD 0xca /* Error Command (16b)
76 * 9 SERR on non-DRAM lock
79 * 6 target abort on high exception
80 * 5 detect unimplemented cyc
81 * 4 AGP access outside of GA
82 * 3 SERR on invalid AGP access
83 * 2 invalid translation table
84 * 1 SERR on unsupported AGP command
88 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
89 #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
92 * 9 fast back-to-back - ro 0
93 * 8 SERR enable - ro 0
94 * 7 addr/data stepping - ro 0
95 * 6 parity err enable - ro 0
96 * 5 VGA palette snoop - ro 0
97 * 4 mem wr & invalidate - ro 0
98 * 3 special cycle - ro 0
100 * 1 mem access dev6 - 0(dis),1(en)
101 * 0 IO access dev3 - 0(dis),1(en)
104 #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
106 * 31:12 mem base addr [31:12]
107 * 11:4 address mask - ro 0
108 * 3 prefetchable - ro 0(non),1(pre)
109 * 2:1 mem type - ro 0
113 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
115 #define I82875P_DRB_SHIFT 26 /* 64MiB grain */
116 #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
119 * 6:0 64MiB row boundary addr
122 #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
135 #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
140 * 22:21 nr chan 00=1,01=2
142 * 19:18 Data Integ Mode 00=none,01=ecc
148 * 1:0 DRAM type 01=DDR
156 struct pci_dev *ovrfl_pdev;
157 void __iomem *ovrfl_window;
160 struct i82875p_dev_info {
161 const char *ctl_name;
164 struct i82875p_error_info {
172 static const struct i82875p_dev_info i82875p_devs[] = {
174 .ctl_name = "i82875p"
178 static struct pci_dev *mci_pdev = NULL; /* init dev: in case that AGP code has
179 * already registered driver
182 static int i82875p_registered = 1;
184 static void i82875p_get_error_info(struct mem_ctl_info *mci,
185 struct i82875p_error_info *info)
188 * This is a mess because there is no atomic way to read all the
189 * registers at once and the registers can transition from CE being
192 pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts);
193 pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
194 pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
195 pci_read_config_byte(mci->pdev, I82875P_DERRSYN, &info->derrsyn);
196 pci_read_config_word(mci->pdev, I82875P_ERRSTS, &info->errsts2);
198 pci_write_bits16(mci->pdev, I82875P_ERRSTS, 0x0081, 0x0081);
201 * If the error is the same then we can for both reads then
202 * the first set of reads is valid. If there is a change then
203 * there is a CE no info and the second set of reads is valid
204 * and should be UE info.
206 if (!(info->errsts2 & 0x0081))
209 if ((info->errsts ^ info->errsts2) & 0x0081) {
210 pci_read_config_dword(mci->pdev, I82875P_EAP, &info->eap);
211 pci_read_config_byte(mci->pdev, I82875P_DES, &info->des);
212 pci_read_config_byte(mci->pdev, I82875P_DERRSYN,
217 static int i82875p_process_error_info(struct mem_ctl_info *mci,
218 struct i82875p_error_info *info, int handle_errors)
222 multi_chan = mci->csrows[0].nr_channels - 1;
224 if (!(info->errsts2 & 0x0081))
230 if ((info->errsts ^ info->errsts2) & 0x0081) {
231 edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
232 info->errsts = info->errsts2;
235 info->eap >>= PAGE_SHIFT;
236 row = edac_mc_find_csrow_by_page(mci, info->eap);
238 if (info->errsts & 0x0080)
239 edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
241 edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
242 multi_chan ? (info->des & 0x1) : 0,
248 static void i82875p_check(struct mem_ctl_info *mci)
250 struct i82875p_error_info info;
252 debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
253 i82875p_get_error_info(mci, &info);
254 i82875p_process_error_info(mci, &info, 1);
257 #ifdef CONFIG_PROC_FS
258 extern int pci_proc_attach_device(struct pci_dev *);
261 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
265 struct mem_ctl_info *mci = NULL;
266 struct i82875p_pvt *pvt = NULL;
267 unsigned long last_cumul_size;
268 struct pci_dev *ovrfl_pdev;
269 void __iomem *ovrfl_window = NULL;
271 u32 drc_chan; /* Number of channels 0=1chan,1=2chan */
273 u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
274 struct i82875p_error_info discard;
276 debugf0("%s()\n", __func__);
277 ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
281 * Intel tells BIOS developers to hide device 6 which
282 * configures the overflow device access containing
283 * the DRBs - this is where we expose device 6.
284 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
286 pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
288 pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
294 #ifdef CONFIG_PROC_FS
295 if (!ovrfl_pdev->procent && pci_proc_attach_device(ovrfl_pdev)) {
296 i82875p_printk(KERN_ERR,
297 "%s(): Failed to attach overflow device\n", __func__);
302 if (pci_enable_device(ovrfl_pdev)) {
303 i82875p_printk(KERN_ERR,
304 "%s(): Failed to enable overflow device\n", __func__);
308 if (pci_request_regions(ovrfl_pdev, pci_name(ovrfl_pdev))) {
314 /* cache is irrelevant for PCI bus reads/writes */
315 ovrfl_window = ioremap_nocache(pci_resource_start(ovrfl_pdev, 0),
316 pci_resource_len(ovrfl_pdev, 0));
319 i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
324 /* need to find out the number of channels */
325 drc = readl(ovrfl_window + I82875P_DRC);
326 drc_chan = ((drc >> 21) & 0x1);
327 nr_chans = drc_chan + 1;
329 drc_ddim = (drc >> 18) & 0x1;
330 mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
338 debugf3("%s(): init mci\n", __func__);
340 mci->mtype_cap = MEM_FLAG_DDR;
341 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
342 mci->edac_cap = EDAC_FLAG_UNKNOWN;
345 mci->mod_name = EDAC_MOD_STR;
346 mci->mod_ver = "$Revision: 1.5.2.11 $";
347 mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
348 mci->edac_check = i82875p_check;
349 mci->ctl_page_to_phys = NULL;
350 debugf3("%s(): init pvt\n", __func__);
351 pvt = (struct i82875p_pvt *) mci->pvt_info;
352 pvt->ovrfl_pdev = ovrfl_pdev;
353 pvt->ovrfl_window = ovrfl_window;
356 * The dram row boundary (DRB) reg values are boundary address
357 * for each DRAM row with a granularity of 32 or 64MB (single/dual
358 * channel operation). DRB regs are cumulative; therefore DRB7 will
359 * contain the total memory contained in all eight rows.
361 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
364 struct csrow_info *csrow = &mci->csrows[index];
366 value = readb(ovrfl_window + I82875P_DRB + index);
367 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
368 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
371 if (cumul_size == last_cumul_size)
372 continue; /* not populated */
374 csrow->first_page = last_cumul_size;
375 csrow->last_page = cumul_size - 1;
376 csrow->nr_pages = cumul_size - last_cumul_size;
377 last_cumul_size = cumul_size;
378 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
379 csrow->mtype = MEM_DDR;
380 csrow->dtype = DEV_UNKNOWN;
381 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
384 i82875p_get_error_info(mci, &discard); /* clear counters */
386 if (edac_mc_add_mc(mci)) {
387 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
391 /* get this far and it's successful */
392 debugf3("%s(): success\n", __func__);
399 iounmap(ovrfl_window);
402 pci_release_regions(ovrfl_pdev);
407 pci_disable_device(ovrfl_pdev);
408 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
412 /* returns count (>= 0), or negative on error */
413 static int __devinit i82875p_init_one(struct pci_dev *pdev,
414 const struct pci_device_id *ent)
418 debugf0("%s()\n", __func__);
419 i82875p_printk(KERN_INFO, "i82875p init one\n");
421 if (pci_enable_device(pdev) < 0)
424 rc = i82875p_probe1(pdev, ent->driver_data);
426 if (mci_pdev == NULL)
427 mci_pdev = pci_dev_get(pdev);
432 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
434 struct mem_ctl_info *mci;
435 struct i82875p_pvt *pvt = NULL;
437 debugf0("%s()\n", __func__);
439 if ((mci = edac_mc_del_mc(pdev)) == NULL)
442 pvt = (struct i82875p_pvt *) mci->pvt_info;
444 if (pvt->ovrfl_window)
445 iounmap(pvt->ovrfl_window);
447 if (pvt->ovrfl_pdev) {
449 pci_release_regions(pvt->ovrfl_pdev);
450 #endif /*CORRECT_BIOS */
451 pci_disable_device(pvt->ovrfl_pdev);
452 pci_dev_put(pvt->ovrfl_pdev);
458 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
460 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
465 } /* 0 terminated list. */
468 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
470 static struct pci_driver i82875p_driver = {
471 .name = EDAC_MOD_STR,
472 .probe = i82875p_init_one,
473 .remove = __devexit_p(i82875p_remove_one),
474 .id_table = i82875p_pci_tbl,
477 static int __init i82875p_init(void)
481 debugf3("%s()\n", __func__);
482 pci_rc = pci_register_driver(&i82875p_driver);
487 if (mci_pdev == NULL) {
488 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
489 PCI_DEVICE_ID_INTEL_82875_0, NULL);
492 debugf0("875p pci_get_device fail\n");
497 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
500 debugf0("875p init fail\n");
509 pci_unregister_driver(&i82875p_driver);
512 if (mci_pdev != NULL)
513 pci_dev_put(mci_pdev);
518 static void __exit i82875p_exit(void)
520 debugf3("%s()\n", __func__);
522 pci_unregister_driver(&i82875p_driver);
524 if (!i82875p_registered) {
525 i82875p_remove_one(mci_pdev);
526 pci_dev_put(mci_pdev);
530 module_init(i82875p_init);
531 module_exit(i82875p_exit);
533 MODULE_LICENSE("GPL");
534 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
535 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");