Pileus Git - ~andy/linux/blob - drivers/dma/ioat/dma.c

   1 /*
   2  * Intel I/OAT DMA Linux driver
   3  * Copyright(c) 2004 - 2009 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  */
  22
  23 /*
  24  * This driver supports an Intel I/OAT DMA engine, which does asynchronous
  25  * copy operations.
  26  */
  27
  28 #include <linux/init.h>
  29 #include <linux/module.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/dmaengine.h>
  34 #include <linux/delay.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/prefetch.h>
  38 #include <linux/i7300_idle.h>
  39 #include "dma.h"
  40 #include "registers.h"
  41 #include "hw.h"
  42
  43 #include "../dmaengine.h"
  44
  45 int ioat_pending_level = 4;
  46 module_param(ioat_pending_level, int, 0644);
  47 MODULE_PARM_DESC(ioat_pending_level,
  48                  "high-water mark for pushing ioat descriptors (default: 4)");
  49
  50 /* internal functions */
  51 static void ioat1_cleanup(struct ioat_dma_chan *ioat);
  52 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat);
  53
  54 /**
  55  * ioat_dma_do_interrupt - handler used for single vector interrupt mode
  56  * @irq: interrupt id
  57  * @data: interrupt data
  58  */
  59 static irqreturn_t ioat_dma_do_interrupt(int irq, void *data)
  60 {
  61         struct ioatdma_device *instance = data;
  62         struct ioat_chan_common *chan;
  63         unsigned long attnstatus;
  64         int bit;
  65         u8 intrctrl;
  66
  67         intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
  68
  69         if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN))
  70                 return IRQ_NONE;
  71
  72         if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) {
  73                 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  74                 return IRQ_NONE;
  75         }
  76
  77         attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
  78         for_each_set_bit(bit, &attnstatus, BITS_PER_LONG) {
  79                 chan = ioat_chan_by_index(instance, bit);
  80                 tasklet_schedule(&chan->cleanup_task);
  81         }
  82
  83         writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
  84         return IRQ_HANDLED;
  85 }
  86
  87 /**
  88  * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode
  89  * @irq: interrupt id
  90  * @data: interrupt data
  91  */
  92 static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data)
  93 {
  94         struct ioat_chan_common *chan = data;
  95
  96         tasklet_schedule(&chan->cleanup_task);
  97
  98         return IRQ_HANDLED;
  99 }
 100
 101 /* common channel initialization */
 102 void ioat_init_channel(struct ioatdma_device *device, struct ioat_chan_common *chan, int idx)
 103 {
 104         struct dma_device *dma = &device->common;
 105         struct dma_chan *c = &chan->common;
 106         unsigned long data = (unsigned long) c;
 107
 108         chan->device = device;
 109         chan->reg_base = device->reg_base + (0x80 * (idx + 1));
 110         spin_lock_init(&chan->cleanup_lock);
 111         chan->common.device = dma;
 112         list_add_tail(&chan->common.device_node, &dma->channels);
 113         device->idx[idx] = chan;
 114         init_timer(&chan->timer);
 115         chan->timer.function = device->timer_fn;
 116         chan->timer.data = data;
 117         tasklet_init(&chan->cleanup_task, device->cleanup_fn, data);
 118         tasklet_disable(&chan->cleanup_task);
 119 }
 120
 121 /**
 122  * ioat1_dma_enumerate_channels - find and initialize the device's channels
 123  * @device: the device to be enumerated
 124  */
 125 static int ioat1_enumerate_channels(struct ioatdma_device *device)
 126 {
 127         u8 xfercap_scale;
 128         u32 xfercap;
 129         int i;
 130         struct ioat_dma_chan *ioat;
 131         struct device *dev = &device->pdev->dev;
 132         struct dma_device *dma = &device->common;
 133
 134         INIT_LIST_HEAD(&dma->channels);
 135         dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
 136         dma->chancnt &= 0x1f; /* bits [4:0] valid */
 137         if (dma->chancnt > ARRAY_SIZE(device->idx)) {
 138                 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
 139                          dma->chancnt, ARRAY_SIZE(device->idx));
 140                 dma->chancnt = ARRAY_SIZE(device->idx);
 141         }
 142         xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
 143         xfercap_scale &= 0x1f; /* bits [4:0] valid */
 144         xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale));
 145         dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap);
 146
 147 #ifdef  CONFIG_I7300_IDLE_IOAT_CHANNEL
 148         if (i7300_idle_platform_probe(NULL, NULL, 1) == 0)
 149                 dma->chancnt--;
 150 #endif
 151         for (i = 0; i < dma->chancnt; i++) {
 152                 ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL);
 153                 if (!ioat)
 154                         break;
 155
 156                 ioat_init_channel(device, &ioat->base, i);
 157                 ioat->xfercap = xfercap;
 158                 spin_lock_init(&ioat->desc_lock);
 159                 INIT_LIST_HEAD(&ioat->free_desc);
 160                 INIT_LIST_HEAD(&ioat->used_desc);
 161         }
 162         dma->chancnt = i;
 163         return i;
 164 }
 165
 166 /**
 167  * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended
 168  *                                 descriptors to hw
 169  * @chan: DMA channel handle
 170  */
 171 static inline void
 172 __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat)
 173 {
 174         void __iomem *reg_base = ioat->base.reg_base;
 175
 176         dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n",
 177                 __func__, ioat->pending);
 178         ioat->pending = 0;
 179         writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET);
 180 }
 181
 182 static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 183 {
 184         struct ioat_dma_chan *ioat = to_ioat_chan(chan);
 185
 186         if (ioat->pending > 0) {
 187                 spin_lock_bh(&ioat->desc_lock);
 188                 __ioat1_dma_memcpy_issue_pending(ioat);
 189                 spin_unlock_bh(&ioat->desc_lock);
 190         }
 191 }
 192
 193 /**
 194  * ioat1_reset_channel - restart a channel
 195  * @ioat: IOAT DMA channel handle
 196  */
 197 static void ioat1_reset_channel(struct ioat_dma_chan *ioat)
 198 {
 199         struct ioat_chan_common *chan = &ioat->base;
 200         void __iomem *reg_base = chan->reg_base;
 201         u32 chansts, chanerr;
 202
 203         dev_warn(to_dev(chan), "reset\n");
 204         chanerr = readl(reg_base + IOAT_CHANERR_OFFSET);
 205         chansts = *chan->completion & IOAT_CHANSTS_STATUS;
 206         if (chanerr) {
 207                 dev_err(to_dev(chan),
 208                         "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
 209                         chan_num(chan), chansts, chanerr);
 210                 writel(chanerr, reg_base + IOAT_CHANERR_OFFSET);
 211         }
 212
 213         /*
 214          * whack it upside the head with a reset
 215          * and wait for things to settle out.
 216          * force the pending count to a really big negative
 217          * to make sure no one forces an issue_pending
 218          * while we're waiting.
 219          */
 220
 221         ioat->pending = INT_MIN;
 222         writeb(IOAT_CHANCMD_RESET,
 223                reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 224         set_bit(IOAT_RESET_PENDING, &chan->state);
 225         mod_timer(&chan->timer, jiffies + RESET_DELAY);
 226 }
 227
 228 static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
 229 {
 230         struct dma_chan *c = tx->chan;
 231         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 232         struct ioat_desc_sw *desc = tx_to_ioat_desc(tx);
 233         struct ioat_chan_common *chan = &ioat->base;
 234         struct ioat_desc_sw *first;
 235         struct ioat_desc_sw *chain_tail;
 236         dma_cookie_t cookie;
 237
 238         spin_lock_bh(&ioat->desc_lock);
 239         /* cookie incr and addition to used_list must be atomic */
 240         cookie = dma_cookie_assign(tx);
 241         dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie);
 242
 243         /* write address into NextDescriptor field of last desc in chain */
 244         first = to_ioat_desc(desc->tx_list.next);
 245         chain_tail = to_ioat_desc(ioat->used_desc.prev);
 246         /* make descriptor updates globally visible before chaining */
 247         wmb();
 248         chain_tail->hw->next = first->txd.phys;
 249         list_splice_tail_init(&desc->tx_list, &ioat->used_desc);
 250         dump_desc_dbg(ioat, chain_tail);
 251         dump_desc_dbg(ioat, first);
 252
 253         if (!test_and_set_bit(IOAT_COMPLETION_PENDING, &chan->state))
 254                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 255
 256         ioat->active += desc->hw->tx_cnt;
 257         ioat->pending += desc->hw->tx_cnt;
 258         if (ioat->pending >= ioat_pending_level)
 259                 __ioat1_dma_memcpy_issue_pending(ioat);
 260         spin_unlock_bh(&ioat->desc_lock);
 261
 262         return cookie;
 263 }
 264
 265 /**
 266  * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair
 267  * @ioat: the channel supplying the memory pool for the descriptors
 268  * @flags: allocation flags
 269  */
 270 static struct ioat_desc_sw *
 271 ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags)
 272 {
 273         struct ioat_dma_descriptor *desc;
 274         struct ioat_desc_sw *desc_sw;
 275         struct ioatdma_device *ioatdma_device;
 276         dma_addr_t phys;
 277
 278         ioatdma_device = ioat->base.device;
 279         desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys);
 280         if (unlikely(!desc))
 281                 return NULL;
 282
 283         desc_sw = kzalloc(sizeof(*desc_sw), flags);
 284         if (unlikely(!desc_sw)) {
 285                 pci_pool_free(ioatdma_device->dma_pool, desc, phys);
 286                 return NULL;
 287         }
 288
 289         memset(desc, 0, sizeof(*desc));
 290
 291         INIT_LIST_HEAD(&desc_sw->tx_list);
 292         dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common);
 293         desc_sw->txd.tx_submit = ioat1_tx_submit;
 294         desc_sw->hw = desc;
 295         desc_sw->txd.phys = phys;
 296         set_desc_id(desc_sw, -1);
 297
 298         return desc_sw;
 299 }
 300
 301 static int ioat_initial_desc_count = 256;
 302 module_param(ioat_initial_desc_count, int, 0644);
 303 MODULE_PARM_DESC(ioat_initial_desc_count,
 304                  "ioat1: initial descriptors per channel (default: 256)");
 305 /**
 306  * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors
 307  * @chan: the channel to be filled out
 308  */
 309 static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
 310 {
 311         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 312         struct ioat_chan_common *chan = &ioat->base;
 313         struct ioat_desc_sw *desc;
 314         u32 chanerr;
 315         int i;
 316         LIST_HEAD(tmp_list);
 317
 318         /* have we already been set up? */
 319         if (!list_empty(&ioat->free_desc))
 320                 return ioat->desccount;
 321
 322         /* Setup register to interrupt and write completion status on error */
 323         writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
 324
 325         chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 326         if (chanerr) {
 327                 dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr);
 328                 writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET);
 329         }
 330
 331         /* Allocate descriptors */
 332         for (i = 0; i < ioat_initial_desc_count; i++) {
 333                 desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL);
 334                 if (!desc) {
 335                         dev_err(to_dev(chan), "Only %d initial descriptors\n", i);
 336                         break;
 337                 }
 338                 set_desc_id(desc, i);
 339                 list_add_tail(&desc->node, &tmp_list);
 340         }
 341         spin_lock_bh(&ioat->desc_lock);
 342         ioat->desccount = i;
 343         list_splice(&tmp_list, &ioat->free_desc);
 344         spin_unlock_bh(&ioat->desc_lock);
 345
 346         /* allocate a completion writeback area */
 347         /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
 348         chan->completion = pci_pool_alloc(chan->device->completion_pool,
 349                                           GFP_KERNEL, &chan->completion_dma);
 350         memset(chan->completion, 0, sizeof(*chan->completion));
 351         writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF,
 352                chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
 353         writel(((u64) chan->completion_dma) >> 32,
 354                chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
 355
 356         tasklet_enable(&chan->cleanup_task);
 357         ioat1_dma_start_null_desc(ioat);  /* give chain to dma device */
 358         dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n",
 359                 __func__, ioat->desccount);
 360         return ioat->desccount;
 361 }
 362
 363 /**
 364  * ioat1_dma_free_chan_resources - release all the descriptors
 365  * @chan: the channel to be cleaned
 366  */
 367 static void ioat1_dma_free_chan_resources(struct dma_chan *c)
 368 {
 369         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 370         struct ioat_chan_common *chan = &ioat->base;
 371         struct ioatdma_device *ioatdma_device = chan->device;
 372         struct ioat_desc_sw *desc, *_desc;
 373         int in_use_descs = 0;
 374
 375         /* Before freeing channel resources first check
 376          * if they have been previously allocated for this channel.
 377          */
 378         if (ioat->desccount == 0)
 379                 return;
 380
 381         tasklet_disable(&chan->cleanup_task);
 382         del_timer_sync(&chan->timer);
 383         ioat1_cleanup(ioat);
 384
 385         /* Delay 100ms after reset to allow internal DMA logic to quiesce
 386          * before removing DMA descriptor resources.
 387          */
 388         writeb(IOAT_CHANCMD_RESET,
 389                chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version));
 390         mdelay(100);
 391
 392         spin_lock_bh(&ioat->desc_lock);
 393         list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) {
 394                 dev_dbg(to_dev(chan), "%s: freeing %d from used list\n",
 395                         __func__, desc_id(desc));
 396                 dump_desc_dbg(ioat, desc);
 397                 in_use_descs++;
 398                 list_del(&desc->node);
 399                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 400                               desc->txd.phys);
 401                 kfree(desc);
 402         }
 403         list_for_each_entry_safe(desc, _desc,
 404                                  &ioat->free_desc, node) {
 405                 list_del(&desc->node);
 406                 pci_pool_free(ioatdma_device->dma_pool, desc->hw,
 407                               desc->txd.phys);
 408                 kfree(desc);
 409         }
 410         spin_unlock_bh(&ioat->desc_lock);
 411
 412         pci_pool_free(ioatdma_device->completion_pool,
 413                       chan->completion,
 414                       chan->completion_dma);
 415
 416         /* one is ok since we left it on there on purpose */
 417         if (in_use_descs > 1)
 418                 dev_err(to_dev(chan), "Freeing %d in use descriptors!\n",
 419                         in_use_descs - 1);
 420
 421         chan->last_completion = 0;
 422         chan->completion_dma = 0;
 423         ioat->pending = 0;
 424         ioat->desccount = 0;
 425 }
 426
 427 /**
 428  * ioat1_dma_get_next_descriptor - return the next available descriptor
 429  * @ioat: IOAT DMA channel handle
 430  *
 431  * Gets the next descriptor from the chain, and must be called with the
 432  * channel's desc_lock held.  Allocates more descriptors if the channel
 433  * has run out.
 434  */
 435 static struct ioat_desc_sw *
 436 ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat)
 437 {
 438         struct ioat_desc_sw *new;
 439
 440         if (!list_empty(&ioat->free_desc)) {
 441                 new = to_ioat_desc(ioat->free_desc.next);
 442                 list_del(&new->node);
 443         } else {
 444                 /* try to get another desc */
 445                 new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC);
 446                 if (!new) {
 447                         dev_err(to_dev(&ioat->base), "alloc failed\n");
 448                         return NULL;
 449                 }
 450         }
 451         dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n",
 452                 __func__, desc_id(new));
 453         prefetch(new->hw);
 454         return new;
 455 }
 456
 457 static struct dma_async_tx_descriptor *
 458 ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
 459                       dma_addr_t dma_src, size_t len, unsigned long flags)
 460 {
 461         struct ioat_dma_chan *ioat = to_ioat_chan(c);
 462         struct ioat_desc_sw *desc;
 463         size_t copy;
 464         LIST_HEAD(chain);
 465         dma_addr_t src = dma_src;
 466         dma_addr_t dest = dma_dest;
 467         size_t total_len = len;
 468         struct ioat_dma_descriptor *hw = NULL;
 469         int tx_cnt = 0;
 470
 471         spin_lock_bh(&ioat->desc_lock);
 472         desc = ioat1_dma_get_next_descriptor(ioat);
 473         do {
 474                 if (!desc)
 475                         break;
 476
 477                 tx_cnt++;
 478                 copy = min_t(size_t, len, ioat->xfercap);
 479
 480                 hw = desc->hw;
 481                 hw->size = copy;
 482                 hw->ctl = 0;
 483                 hw->src_addr = src;
 484                 hw->dst_addr = dest;
 485
 486                 list_add_tail(&desc->node, &chain);
 487
 488                 len -= copy;
 489                 dest += copy;
 490                 src += copy;
 491                 if (len) {
 492                         struct ioat_desc_sw *next;
 493
 494                         async_tx_ack(&desc->txd);
 495                         next = ioat1_dma_get_next_descriptor(ioat);
 496                         hw->next = next ? next->txd.phys : 0;
 497                         dump_desc_dbg(ioat, desc);
 498                         desc = next;
 499                 } else
 500                         hw->next = 0;
 501         } while (len);
 502
 503         if (!desc) {
 504                 struct ioat_chan_common *chan = &ioat->base;
 505
 506                 dev_err(to_dev(chan),
 507                         "chan%d - get_next_desc failed\n", chan_num(chan));
 508                 list_splice(&chain, &ioat->free_desc);
 509                 spin_unlock_bh(&ioat->desc_lock);
 510                 return NULL;
 511         }
 512         spin_unlock_bh(&ioat->desc_lock);
 513
 514         desc->txd.flags = flags;
 515         desc->len = total_len;
 516         list_splice(&chain, &desc->tx_list);
 517         hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
 518         hw->ctl_f.compl_write = 1;
 519         hw->tx_cnt = tx_cnt;
 520         dump_desc_dbg(ioat, desc);
 521
 522         return &desc->txd;
 523 }
 524
 525 static void ioat1_cleanup_event(unsigned long data)
 526 {
 527         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 528
 529         ioat1_cleanup(ioat);
 530         writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
 531 }
 532
 533 void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
 534                     size_t len, struct ioat_dma_descriptor *hw)
 535 {
 536         struct pci_dev *pdev = chan->device->pdev;
 537         size_t offset = len - hw->size;
 538
 539         if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP))
 540                 ioat_unmap(pdev, hw->dst_addr - offset, len,
 541                            PCI_DMA_FROMDEVICE, flags, 1);
 542
 543         if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP))
 544                 ioat_unmap(pdev, hw->src_addr - offset, len,
 545                            PCI_DMA_TODEVICE, flags, 0);
 546 }
 547
 548 unsigned long ioat_get_current_completion(struct ioat_chan_common *chan)
 549 {
 550         unsigned long phys_complete;
 551         u64 completion;
 552
 553         completion = *chan->completion;
 554         phys_complete = ioat_chansts_to_addr(completion);
 555
 556         dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__,
 557                 (unsigned long long) phys_complete);
 558
 559         if (is_ioat_halted(completion)) {
 560                 u32 chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
 561                 dev_err(to_dev(chan), "Channel halted, chanerr = %x\n",
 562                         chanerr);
 563
 564                 /* TODO do something to salvage the situation */
 565         }
 566
 567         return phys_complete;
 568 }
 569
 570 bool ioat_cleanup_preamble(struct ioat_chan_common *chan,
 571                            unsigned long *phys_complete)
 572 {
 573         *phys_complete = ioat_get_current_completion(chan);
 574         if (*phys_complete == chan->last_completion)
 575                 return false;
 576         clear_bit(IOAT_COMPLETION_ACK, &chan->state);
 577         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 578
 579         return true;
 580 }
 581
 582 static void __cleanup(struct ioat_dma_chan *ioat, unsigned long phys_complete)
 583 {
 584         struct ioat_chan_common *chan = &ioat->base;
 585         struct list_head *_desc, *n;
 586         struct dma_async_tx_descriptor *tx;
 587
 588         dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n",
 589                  __func__, phys_complete);
 590         list_for_each_safe(_desc, n, &ioat->used_desc) {
 591                 struct ioat_desc_sw *desc;
 592
 593                 prefetch(n);
 594                 desc = list_entry(_desc, typeof(*desc), node);
 595                 tx = &desc->txd;
 596                 /*
 597                  * Incoming DMA requests may use multiple descriptors,
 598                  * due to exceeding xfercap, perhaps. If so, only the
 599                  * last one will have a cookie, and require unmapping.
 600                  */
 601                 dump_desc_dbg(ioat, desc);
 602                 if (tx->cookie) {
 603                         dma_cookie_complete(tx);
 604                         ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw);
 605                         ioat->active -= desc->hw->tx_cnt;
 606                         if (tx->callback) {
 607                                 tx->callback(tx->callback_param);
 608                                 tx->callback = NULL;
 609                         }
 610                 }
 611
 612                 if (tx->phys != phys_complete) {
 613                         /*
 614                          * a completed entry, but not the last, so clean
 615                          * up if the client is done with the descriptor
 616                          */
 617                         if (async_tx_test_ack(tx))
 618                                 list_move_tail(&desc->node, &ioat->free_desc);
 619                 } else {
 620                         /*
 621                          * last used desc. Do not remove, so we can
 622                          * append from it.
 623                          */
 624
 625                         /* if nothing else is pending, cancel the
 626                          * completion timeout
 627                          */
 628                         if (n == &ioat->used_desc) {
 629                                 dev_dbg(to_dev(chan),
 630                                         "%s cancel completion timeout\n",
 631                                         __func__);
 632                                 clear_bit(IOAT_COMPLETION_PENDING, &chan->state);
 633                         }
 634
 635                         /* TODO check status bits? */
 636                         break;
 637                 }
 638         }
 639
 640         chan->last_completion = phys_complete;
 641 }
 642
 643 /**
 644  * ioat1_cleanup - cleanup up finished descriptors
 645  * @chan: ioat channel to be cleaned up
 646  *
 647  * To prevent lock contention we defer cleanup when the locks are
 648  * contended with a terminal timeout that forces cleanup and catches
 649  * completion notification errors.
 650  */
 651 static void ioat1_cleanup(struct ioat_dma_chan *ioat)
 652 {
 653         struct ioat_chan_common *chan = &ioat->base;
 654         unsigned long phys_complete;
 655
 656         prefetch(chan->completion);
 657
 658         if (!spin_trylock_bh(&chan->cleanup_lock))
 659                 return;
 660
 661         if (!ioat_cleanup_preamble(chan, &phys_complete)) {
 662                 spin_unlock_bh(&chan->cleanup_lock);
 663                 return;
 664         }
 665
 666         if (!spin_trylock_bh(&ioat->desc_lock)) {
 667                 spin_unlock_bh(&chan->cleanup_lock);
 668                 return;
 669         }
 670
 671         __cleanup(ioat, phys_complete);
 672
 673         spin_unlock_bh(&ioat->desc_lock);
 674         spin_unlock_bh(&chan->cleanup_lock);
 675 }
 676
 677 static void ioat1_timer_event(unsigned long data)
 678 {
 679         struct ioat_dma_chan *ioat = to_ioat_chan((void *) data);
 680         struct ioat_chan_common *chan = &ioat->base;
 681
 682         dev_dbg(to_dev(chan), "%s: state: %lx\n", __func__, chan->state);
 683
 684         spin_lock_bh(&chan->cleanup_lock);
 685         if (test_and_clear_bit(IOAT_RESET_PENDING, &chan->state)) {
 686                 struct ioat_desc_sw *desc;
 687
 688                 spin_lock_bh(&ioat->desc_lock);
 689
 690                 /* restart active descriptors */
 691                 desc = to_ioat_desc(ioat->used_desc.prev);
 692                 ioat_set_chainaddr(ioat, desc->txd.phys);
 693                 ioat_start(chan);
 694
 695                 ioat->pending = 0;
 696                 set_bit(IOAT_COMPLETION_PENDING, &chan->state);
 697                 mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 698                 spin_unlock_bh(&ioat->desc_lock);
 699         } else if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) {
 700                 unsigned long phys_complete;
 701
 702                 spin_lock_bh(&ioat->desc_lock);
 703                 /* if we haven't made progress and we have already
 704                  * acknowledged a pending completion once, then be more
 705                  * forceful with a restart
 706                  */
 707                 if (ioat_cleanup_preamble(chan, &phys_complete))
 708                         __cleanup(ioat, phys_complete);
 709                 else if (test_bit(IOAT_COMPLETION_ACK, &chan->state))
 710                         ioat1_reset_channel(ioat);
 711                 else {
 712                         u64 status = ioat_chansts(chan);
 713
 714                         /* manually update the last completion address */
 715                         if (ioat_chansts_to_addr(status) != 0)
 716                                 *chan->completion = status;
 717
 718                         set_bit(IOAT_COMPLETION_ACK, &chan->state);
 719                         mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT);
 720                 }
 721                 spin_unlock_bh(&ioat->desc_lock);
 722         }
 723         spin_unlock_bh(&chan->cleanup_lock);
 724 }
 725
 726 enum dma_status
 727 ioat_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
 728                    struct dma_tx_state *txstate)
 729 {
 730         struct ioat_chan_common *chan = to_chan_common(c);
 731         struct ioatdma_device *device = chan->device;
 732         enum dma_status ret;
 733
 734         ret = dma_cookie_status(c, cookie, txstate);
 735         if (ret == DMA_SUCCESS)
 736                 return ret;
 737
 738         device->cleanup_fn((unsigned long) c);
 739
 740         return dma_cookie_status(c, cookie, txstate);
 741 }
 742
 743 static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat)
 744 {
 745         struct ioat_chan_common *chan = &ioat->base;
 746         struct ioat_desc_sw *desc;
 747         struct ioat_dma_descriptor *hw;
 748
 749         spin_lock_bh(&ioat->desc_lock);
 750
 751         desc = ioat1_dma_get_next_descriptor(ioat);
 752
 753         if (!desc) {
 754                 dev_err(to_dev(chan),
 755                         "Unable to start null desc - get next desc failed\n");
 756                 spin_unlock_bh(&ioat->desc_lock);
 757                 return;
 758         }
 759
 760         hw = desc->hw;
 761         hw->ctl = 0;
 762         hw->ctl_f.null = 1;
 763         hw->ctl_f.int_en = 1;
 764         hw->ctl_f.compl_write = 1;
 765         /* set size to non-zero value (channel returns error when size is 0) */
 766         hw->size = NULL_DESC_BUFFER_SIZE;
 767         hw->src_addr = 0;
 768         hw->dst_addr = 0;
 769         async_tx_ack(&desc->txd);
 770         hw->next = 0;
 771         list_add_tail(&desc->node, &ioat->used_desc);
 772         dump_desc_dbg(ioat, desc);
 773
 774         ioat_set_chainaddr(ioat, desc->txd.phys);
 775         ioat_start(chan);
 776         spin_unlock_bh(&ioat->desc_lock);
 777 }
 778
 779 /*
 780  * Perform a IOAT transaction to verify the HW works.
 781  */
 782 #define IOAT_TEST_SIZE 2000
 783
 784 static void __devinit ioat_dma_test_callback(void *dma_async_param)
 785 {
 786         struct completion *cmp = dma_async_param;
 787
 788         complete(cmp);
 789 }
 790
 791 /**
 792  * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
 793  * @device: device to be tested
 794  */
 795 int __devinit ioat_dma_self_test(struct ioatdma_device *device)
 796 {
 797         int i;
 798         u8 *src;
 799         u8 *dest;
 800         struct dma_device *dma = &device->common;
 801         struct device *dev = &device->pdev->dev;
 802         struct dma_chan *dma_chan;
 803         struct dma_async_tx_descriptor *tx;
 804         dma_addr_t dma_dest, dma_src;
 805         dma_cookie_t cookie;
 806         int err = 0;
 807         struct completion cmp;
 808         unsigned long tmo;
 809         unsigned long flags;
 810
 811         src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 812         if (!src)
 813                 return -ENOMEM;
 814         dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
 815         if (!dest) {
 816                 kfree(src);
 817                 return -ENOMEM;
 818         }
 819
 820         /* Fill in src buffer */
 821         for (i = 0; i < IOAT_TEST_SIZE; i++)
 822                 src[i] = (u8)i;
 823
 824         /* Start copy, using first DMA channel */
 825         dma_chan = container_of(dma->channels.next, struct dma_chan,
 826                                 device_node);
 827         if (dma->device_alloc_chan_resources(dma_chan) < 1) {
 828                 dev_err(dev, "selftest cannot allocate chan resource\n");
 829                 err = -ENODEV;
 830                 goto out;
 831         }
 832
 833         dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
 834         dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
 835         flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE |
 836                 DMA_PREP_INTERRUPT;
 837         tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src,
 838                                                    IOAT_TEST_SIZE, flags);
 839         if (!tx) {
 840                 dev_err(dev, "Self-test prep failed, disabling\n");
 841                 err = -ENODEV;
 842                 goto free_resources;
 843         }
 844
 845         async_tx_ack(tx);
 846         init_completion(&cmp);
 847         tx->callback = ioat_dma_test_callback;
 848         tx->callback_param = &cmp;
 849         cookie = tx->tx_submit(tx);
 850         if (cookie < 0) {
 851                 dev_err(dev, "Self-test setup failed, disabling\n");
 852                 err = -ENODEV;
 853                 goto free_resources;
 854         }
 855         dma->device_issue_pending(dma_chan);
 856
 857         tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
 858
 859         if (tmo == 0 ||
 860             dma->device_tx_status(dma_chan, cookie, NULL)
 861                                         != DMA_SUCCESS) {
 862                 dev_err(dev, "Self-test copy timed out, disabling\n");
 863                 err = -ENODEV;
 864                 goto free_resources;
 865         }
 866         if (memcmp(src, dest, IOAT_TEST_SIZE)) {
 867                 dev_err(dev, "Self-test copy failed compare, disabling\n");
 868                 err = -ENODEV;
 869                 goto free_resources;
 870         }
 871
 872 free_resources:
 873         dma->device_free_chan_resources(dma_chan);
 874 out:
 875         kfree(src);
 876         kfree(dest);
 877         return err;
 878 }
 879
 880 static char ioat_interrupt_style[32] = "msix";
 881 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
 882                     sizeof(ioat_interrupt_style), 0644);
 883 MODULE_PARM_DESC(ioat_interrupt_style,
 884                  "set ioat interrupt style: msix (default), "
 885                  "msix-single-vector, msi, intx)");
 886
 887 /**
 888  * ioat_dma_setup_interrupts - setup interrupt handler
 889  * @device: ioat device
 890  */
 891 static int ioat_dma_setup_interrupts(struct ioatdma_device *device)
 892 {
 893         struct ioat_chan_common *chan;
 894         struct pci_dev *pdev = device->pdev;
 895         struct device *dev = &pdev->dev;
 896         struct msix_entry *msix;
 897         int i, j, msixcnt;
 898         int err = -EINVAL;
 899         u8 intrctrl = 0;
 900
 901         if (!strcmp(ioat_interrupt_style, "msix"))
 902                 goto msix;
 903         if (!strcmp(ioat_interrupt_style, "msix-single-vector"))
 904                 goto msix_single_vector;
 905         if (!strcmp(ioat_interrupt_style, "msi"))
 906                 goto msi;
 907         if (!strcmp(ioat_interrupt_style, "intx"))
 908                 goto intx;
 909         dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
 910         goto err_no_irq;
 911
 912 msix:
 913         /* The number of MSI-X vectors should equal the number of channels */
 914         msixcnt = device->common.chancnt;
 915         for (i = 0; i < msixcnt; i++)
 916                 device->msix_entries[i].entry = i;
 917
 918         err = pci_enable_msix(pdev, device->msix_entries, msixcnt);
 919         if (err < 0)
 920                 goto msi;
 921         if (err > 0)
 922                 goto msix_single_vector;
 923
 924         for (i = 0; i < msixcnt; i++) {
 925                 msix = &device->msix_entries[i];
 926                 chan = ioat_chan_by_index(device, i);
 927                 err = devm_request_irq(dev, msix->vector,
 928                                        ioat_dma_do_interrupt_msix, 0,
 929                                        "ioat-msix", chan);
 930                 if (err) {
 931                         for (j = 0; j < i; j++) {
 932                                 msix = &device->msix_entries[j];
 933                                 chan = ioat_chan_by_index(device, j);
 934                                 devm_free_irq(dev, msix->vector, chan);
 935                         }
 936                         goto msix_single_vector;
 937                 }
 938         }
 939         intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
 940         goto done;
 941
 942 msix_single_vector:
 943         msix = &device->msix_entries[0];
 944         msix->entry = 0;
 945         err = pci_enable_msix(pdev, device->msix_entries, 1);
 946         if (err)
 947                 goto msi;
 948
 949         err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0,
 950                                "ioat-msix", device);
 951         if (err) {
 952                 pci_disable_msix(pdev);
 953                 goto msi;
 954         }
 955         goto done;
 956
 957 msi:
 958         err = pci_enable_msi(pdev);
 959         if (err)
 960                 goto intx;
 961
 962         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
 963                                "ioat-msi", device);
 964         if (err) {
 965                 pci_disable_msi(pdev);
 966                 goto intx;
 967         }
 968         goto done;
 969
 970 intx:
 971         err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
 972                                IRQF_SHARED, "ioat-intx", device);
 973         if (err)
 974                 goto err_no_irq;
 975
 976 done:
 977         if (device->intr_quirk)
 978                 device->intr_quirk(device);
 979         intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
 980         writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET);
 981         return 0;
 982
 983 err_no_irq:
 984         /* Disable all interrupt generation */
 985         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
 986         dev_err(dev, "no usable interrupts\n");
 987         return err;
 988 }
 989
 990 static void ioat_disable_interrupts(struct ioatdma_device *device)
 991 {
 992         /* Disable all interrupt generation */
 993         writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET);
 994 }
 995
 996 int __devinit ioat_probe(struct ioatdma_device *device)
 997 {
 998         int err = -ENODEV;
 999         struct dma_device *dma = &device->common;
1000         struct pci_dev *pdev = device->pdev;
1001         struct device *dev = &pdev->dev;
1002
1003         /* DMA coherent memory pool for DMA descriptor allocations */
1004         device->dma_pool = pci_pool_create("dma_desc_pool", pdev,
1005                                            sizeof(struct ioat_dma_descriptor),
1006                                            64, 0);
1007         if (!device->dma_pool) {
1008                 err = -ENOMEM;
1009                 goto err_dma_pool;
1010         }
1011
1012         device->completion_pool = pci_pool_create("completion_pool", pdev,
1013                                                   sizeof(u64), SMP_CACHE_BYTES,
1014                                                   SMP_CACHE_BYTES);
1015
1016         if (!device->completion_pool) {
1017                 err = -ENOMEM;
1018                 goto err_completion_pool;
1019         }
1020
1021         device->enumerate_channels(device);
1022
1023         dma_cap_set(DMA_MEMCPY, dma->cap_mask);
1024         dma->dev = &pdev->dev;
1025
1026         if (!dma->chancnt) {
1027                 dev_err(dev, "channel enumeration error\n");
1028                 goto err_setup_interrupts;
1029         }
1030
1031         err = ioat_dma_setup_interrupts(device);
1032         if (err)
1033                 goto err_setup_interrupts;
1034
1035         err = device->self_test(device);
1036         if (err)
1037                 goto err_self_test;
1038
1039         return 0;
1040
1041 err_self_test:
1042         ioat_disable_interrupts(device);
1043 err_setup_interrupts:
1044         pci_pool_destroy(device->completion_pool);
1045 err_completion_pool:
1046         pci_pool_destroy(device->dma_pool);
1047 err_dma_pool:
1048         return err;
1049 }
1050
1051 int __devinit ioat_register(struct ioatdma_device *device)
1052 {
1053         int err = dma_async_device_register(&device->common);
1054
1055         if (err) {
1056                 ioat_disable_interrupts(device);
1057                 pci_pool_destroy(device->completion_pool);
1058                 pci_pool_destroy(device->dma_pool);
1059         }
1060
1061         return err;
1062 }
1063
1064 /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */
1065 static void ioat1_intr_quirk(struct ioatdma_device *device)
1066 {
1067         struct pci_dev *pdev = device->pdev;
1068         u32 dmactrl;
1069
1070         pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl);
1071         if (pdev->msi_enabled)
1072                 dmactrl |= IOAT_PCI_DMACTRL_MSI_EN;
1073         else
1074                 dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN;
1075         pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl);
1076 }
1077
1078 static ssize_t ring_size_show(struct dma_chan *c, char *page)
1079 {
1080         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1081
1082         return sprintf(page, "%d\n", ioat->desccount);
1083 }
1084 static struct ioat_sysfs_entry ring_size_attr = __ATTR_RO(ring_size);
1085
1086 static ssize_t ring_active_show(struct dma_chan *c, char *page)
1087 {
1088         struct ioat_dma_chan *ioat = to_ioat_chan(c);
1089
1090         return sprintf(page, "%d\n", ioat->active);
1091 }
1092 static struct ioat_sysfs_entry ring_active_attr = __ATTR_RO(ring_active);
1093
1094 static ssize_t cap_show(struct dma_chan *c, char *page)
1095 {
1096         struct dma_device *dma = c->device;
1097
1098         return sprintf(page, "copy%s%s%s%s%s%s\n",
1099                        dma_has_cap(DMA_PQ, dma->cap_mask) ? " pq" : "",
1100                        dma_has_cap(DMA_PQ_VAL, dma->cap_mask) ? " pq_val" : "",
1101                        dma_has_cap(DMA_XOR, dma->cap_mask) ? " xor" : "",
1102                        dma_has_cap(DMA_XOR_VAL, dma->cap_mask) ? " xor_val" : "",
1103                        dma_has_cap(DMA_MEMSET, dma->cap_mask)  ? " fill" : "",
1104                        dma_has_cap(DMA_INTERRUPT, dma->cap_mask) ? " intr" : "");
1105
1106 }
1107 struct ioat_sysfs_entry ioat_cap_attr = __ATTR_RO(cap);
1108
1109 static ssize_t version_show(struct dma_chan *c, char *page)
1110 {
1111         struct dma_device *dma = c->device;
1112         struct ioatdma_device *device = to_ioatdma_device(dma);
1113
1114         return sprintf(page, "%d.%d\n",
1115                        device->version >> 4, device->version & 0xf);
1116 }
1117 struct ioat_sysfs_entry ioat_version_attr = __ATTR_RO(version);
1118
1119 static struct attribute *ioat1_attrs[] = {
1120         &ring_size_attr.attr,
1121         &ring_active_attr.attr,
1122         &ioat_cap_attr.attr,
1123         &ioat_version_attr.attr,
1124         NULL,
1125 };
1126
1127 static ssize_t
1128 ioat_attr_show(struct kobject *kobj, struct attribute *attr, char *page)
1129 {
1130         struct ioat_sysfs_entry *entry;
1131         struct ioat_chan_common *chan;
1132
1133         entry = container_of(attr, struct ioat_sysfs_entry, attr);
1134         chan = container_of(kobj, struct ioat_chan_common, kobj);
1135
1136         if (!entry->show)
1137                 return -EIO;
1138         return entry->show(&chan->common, page);
1139 }
1140
1141 const struct sysfs_ops ioat_sysfs_ops = {
1142         .show   = ioat_attr_show,
1143 };
1144
1145 static struct kobj_type ioat1_ktype = {
1146         .sysfs_ops = &ioat_sysfs_ops,
1147         .default_attrs = ioat1_attrs,
1148 };
1149
1150 void ioat_kobject_add(struct ioatdma_device *device, struct kobj_type *type)
1151 {
1152         struct dma_device *dma = &device->common;
1153         struct dma_chan *c;
1154
1155         list_for_each_entry(c, &dma->channels, device_node) {
1156                 struct ioat_chan_common *chan = to_chan_common(c);
1157                 struct kobject *parent = &c->dev->device.kobj;
1158                 int err;
1159
1160                 err = kobject_init_and_add(&chan->kobj, type, parent, "quickdata");
1161                 if (err) {
1162                         dev_warn(to_dev(chan),
1163                                  "sysfs init error (%d), continuing...\n", err);
1164                         kobject_put(&chan->kobj);
1165                         set_bit(IOAT_KOBJ_INIT_FAIL, &chan->state);
1166                 }
1167         }
1168 }
1169
1170 void ioat_kobject_del(struct ioatdma_device *device)
1171 {
1172         struct dma_device *dma = &device->common;
1173         struct dma_chan *c;
1174
1175         list_for_each_entry(c, &dma->channels, device_node) {
1176                 struct ioat_chan_common *chan = to_chan_common(c);
1177
1178                 if (!test_bit(IOAT_KOBJ_INIT_FAIL, &chan->state)) {
1179                         kobject_del(&chan->kobj);
1180                         kobject_put(&chan->kobj);
1181                 }
1182         }
1183 }
1184
1185 int __devinit ioat1_dma_probe(struct ioatdma_device *device, int dca)
1186 {
1187         struct pci_dev *pdev = device->pdev;
1188         struct dma_device *dma;
1189         int err;
1190
1191         device->intr_quirk = ioat1_intr_quirk;
1192         device->enumerate_channels = ioat1_enumerate_channels;
1193         device->self_test = ioat_dma_self_test;
1194         device->timer_fn = ioat1_timer_event;
1195         device->cleanup_fn = ioat1_cleanup_event;
1196         dma = &device->common;
1197         dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy;
1198         dma->device_issue_pending = ioat1_dma_memcpy_issue_pending;
1199         dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources;
1200         dma->device_free_chan_resources = ioat1_dma_free_chan_resources;
1201         dma->device_tx_status = ioat_dma_tx_status;
1202
1203         err = ioat_probe(device);
1204         if (err)
1205                 return err;
1206         ioat_set_tcp_copy_break(4096);
1207         err = ioat_register(device);
1208         if (err)
1209                 return err;
1210         ioat_kobject_add(device, &ioat1_ktype);
1211
1212         if (dca)
1213                 device->dca = ioat_dca_init(pdev, device->reg_base);
1214
1215         return err;
1216 }
1217
1218 void __devexit ioat_dma_remove(struct ioatdma_device *device)
1219 {
1220         struct dma_device *dma = &device->common;
1221
1222         ioat_disable_interrupts(device);
1223
1224         ioat_kobject_del(device);
1225
1226         dma_async_device_unregister(dma);
1227
1228         pci_pool_destroy(device->dma_pool);
1229         pci_pool_destroy(device->completion_pool);
1230
1231         INIT_LIST_HEAD(&dma->channels);
1232 }