Pileus Git - ~andy/linux/blob - drivers/dma/imx-sdma.c

   1 /*
   2  * drivers/dma/imx-sdma.c
   3  *
   4  * This file contains a driver for the Freescale Smart DMA engine
   5  *
   6  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   7  *
   8  * Based on code from Freescale:
   9  *
  10  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * The code contained herein is licensed under the GNU General Public
  13  * License. You may obtain a copy of the GNU General Public License
  14  * Version 2 or later at the following locations:
  15  *
  16  * http://www.opensource.org/licenses/gpl-license.html
  17  * http://www.gnu.org/copyleft/gpl.html
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/types.h>
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/clk.h>
  26 #include <linux/wait.h>
  27 #include <linux/sched.h>
  28 #include <linux/semaphore.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/device.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/firmware.h>
  33 #include <linux/slab.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dmaengine.h>
  36 #include <linux/of.h>
  37 #include <linux/of_device.h>
  38 #include <linux/module.h>
  39
  40 #include <asm/irq.h>
  41 #include <mach/sdma.h>
  42 #include <mach/dma.h>
  43 #include <mach/hardware.h>
  44
  45 /* SDMA registers */
  46 #define SDMA_H_C0PTR            0x000
  47 #define SDMA_H_INTR             0x004
  48 #define SDMA_H_STATSTOP         0x008
  49 #define SDMA_H_START            0x00c
  50 #define SDMA_H_EVTOVR           0x010
  51 #define SDMA_H_DSPOVR           0x014
  52 #define SDMA_H_HOSTOVR          0x018
  53 #define SDMA_H_EVTPEND          0x01c
  54 #define SDMA_H_DSPENBL          0x020
  55 #define SDMA_H_RESET            0x024
  56 #define SDMA_H_EVTERR           0x028
  57 #define SDMA_H_INTRMSK          0x02c
  58 #define SDMA_H_PSW              0x030
  59 #define SDMA_H_EVTERRDBG        0x034
  60 #define SDMA_H_CONFIG           0x038
  61 #define SDMA_ONCE_ENB           0x040
  62 #define SDMA_ONCE_DATA          0x044
  63 #define SDMA_ONCE_INSTR         0x048
  64 #define SDMA_ONCE_STAT          0x04c
  65 #define SDMA_ONCE_CMD           0x050
  66 #define SDMA_EVT_MIRROR         0x054
  67 #define SDMA_ILLINSTADDR        0x058
  68 #define SDMA_CHN0ADDR           0x05c
  69 #define SDMA_ONCE_RTB           0x060
  70 #define SDMA_XTRIG_CONF1        0x070
  71 #define SDMA_XTRIG_CONF2        0x074
  72 #define SDMA_CHNENBL0_IMX35     0x200
  73 #define SDMA_CHNENBL0_IMX31     0x080
  74 #define SDMA_CHNPRI_0           0x100
  75
  76 /*
  77  * Buffer descriptor status values.
  78  */
  79 #define BD_DONE  0x01
  80 #define BD_WRAP  0x02
  81 #define BD_CONT  0x04
  82 #define BD_INTR  0x08
  83 #define BD_RROR  0x10
  84 #define BD_LAST  0x20
  85 #define BD_EXTD  0x80
  86
  87 /*
  88  * Data Node descriptor status values.
  89  */
  90 #define DND_END_OF_FRAME  0x80
  91 #define DND_END_OF_XFER   0x40
  92 #define DND_DONE          0x20
  93 #define DND_UNUSED        0x01
  94
  95 /*
  96  * IPCV2 descriptor status values.
  97  */
  98 #define BD_IPCV2_END_OF_FRAME  0x40
  99
 100 #define IPCV2_MAX_NODES        50
 101 /*
 102  * Error bit set in the CCB status field by the SDMA,
 103  * in setbd routine, in case of a transfer error
 104  */
 105 #define DATA_ERROR  0x10000000
 106
 107 /*
 108  * Buffer descriptor commands.
 109  */
 110 #define C0_ADDR             0x01
 111 #define C0_LOAD             0x02
 112 #define C0_DUMP             0x03
 113 #define C0_SETCTX           0x07
 114 #define C0_GETCTX           0x03
 115 #define C0_SETDM            0x01
 116 #define C0_SETPM            0x04
 117 #define C0_GETDM            0x02
 118 #define C0_GETPM            0x08
 119 /*
 120  * Change endianness indicator in the BD command field
 121  */
 122 #define CHANGE_ENDIANNESS   0x80
 123
 124 /*
 125  * Mode/Count of data node descriptors - IPCv2
 126  */
 127 struct sdma_mode_count {
 128         u32 count   : 16; /* size of the buffer pointed by this BD */
 129         u32 status  :  8; /* E,R,I,C,W,D status bits stored here */
 130         u32 command :  8; /* command mostlky used for channel 0 */
 131 };
 132
 133 /*
 134  * Buffer descriptor
 135  */
 136 struct sdma_buffer_descriptor {
 137         struct sdma_mode_count  mode;
 138         u32 buffer_addr;        /* address of the buffer described */
 139         u32 ext_buffer_addr;    /* extended buffer address */
 140 } __attribute__ ((packed));
 141
 142 /**
 143  * struct sdma_channel_control - Channel control Block
 144  *
 145  * @current_bd_ptr      current buffer descriptor processed
 146  * @base_bd_ptr         first element of buffer descriptor array
 147  * @unused              padding. The SDMA engine expects an array of 128 byte
 148  *                      control blocks
 149  */
 150 struct sdma_channel_control {
 151         u32 current_bd_ptr;
 152         u32 base_bd_ptr;
 153         u32 unused[2];
 154 } __attribute__ ((packed));
 155
 156 /**
 157  * struct sdma_state_registers - SDMA context for a channel
 158  *
 159  * @pc:         program counter
 160  * @t:          test bit: status of arithmetic & test instruction
 161  * @rpc:        return program counter
 162  * @sf:         source fault while loading data
 163  * @spc:        loop start program counter
 164  * @df:         destination fault while storing data
 165  * @epc:        loop end program counter
 166  * @lm:         loop mode
 167  */
 168 struct sdma_state_registers {
 169         u32 pc     :14;
 170         u32 unused1: 1;
 171         u32 t      : 1;
 172         u32 rpc    :14;
 173         u32 unused0: 1;
 174         u32 sf     : 1;
 175         u32 spc    :14;
 176         u32 unused2: 1;
 177         u32 df     : 1;
 178         u32 epc    :14;
 179         u32 lm     : 2;
 180 } __attribute__ ((packed));
 181
 182 /**
 183  * struct sdma_context_data - sdma context specific to a channel
 184  *
 185  * @channel_state:      channel state bits
 186  * @gReg:               general registers
 187  * @mda:                burst dma destination address register
 188  * @msa:                burst dma source address register
 189  * @ms:                 burst dma status register
 190  * @md:                 burst dma data register
 191  * @pda:                peripheral dma destination address register
 192  * @psa:                peripheral dma source address register
 193  * @ps:                 peripheral dma status register
 194  * @pd:                 peripheral dma data register
 195  * @ca:                 CRC polynomial register
 196  * @cs:                 CRC accumulator register
 197  * @dda:                dedicated core destination address register
 198  * @dsa:                dedicated core source address register
 199  * @ds:                 dedicated core status register
 200  * @dd:                 dedicated core data register
 201  */
 202 struct sdma_context_data {
 203         struct sdma_state_registers  channel_state;
 204         u32  gReg[8];
 205         u32  mda;
 206         u32  msa;
 207         u32  ms;
 208         u32  md;
 209         u32  pda;
 210         u32  psa;
 211         u32  ps;
 212         u32  pd;
 213         u32  ca;
 214         u32  cs;
 215         u32  dda;
 216         u32  dsa;
 217         u32  ds;
 218         u32  dd;
 219         u32  scratch0;
 220         u32  scratch1;
 221         u32  scratch2;
 222         u32  scratch3;
 223         u32  scratch4;
 224         u32  scratch5;
 225         u32  scratch6;
 226         u32  scratch7;
 227 } __attribute__ ((packed));
 228
 229 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
 230
 231 struct sdma_engine;
 232
 233 /**
 234  * struct sdma_channel - housekeeping for a SDMA channel
 235  *
 236  * @sdma                pointer to the SDMA engine for this channel
 237  * @channel             the channel number, matches dmaengine chan_id + 1
 238  * @direction           transfer type. Needed for setting SDMA script
 239  * @peripheral_type     Peripheral type. Needed for setting SDMA script
 240  * @event_id0           aka dma request line
 241  * @event_id1           for channels that use 2 events
 242  * @word_size           peripheral access size
 243  * @buf_tail            ID of the buffer that was processed
 244  * @done                channel completion
 245  * @num_bd              max NUM_BD. number of descriptors currently handling
 246  */
 247 struct sdma_channel {
 248         struct sdma_engine              *sdma;
 249         unsigned int                    channel;
 250         enum dma_transfer_direction             direction;
 251         enum sdma_peripheral_type       peripheral_type;
 252         unsigned int                    event_id0;
 253         unsigned int                    event_id1;
 254         enum dma_slave_buswidth         word_size;
 255         unsigned int                    buf_tail;
 256         struct completion               done;
 257         unsigned int                    num_bd;
 258         struct sdma_buffer_descriptor   *bd;
 259         dma_addr_t                      bd_phys;
 260         unsigned int                    pc_from_device, pc_to_device;
 261         unsigned long                   flags;
 262         dma_addr_t                      per_address;
 263         u32                             event_mask0, event_mask1;
 264         u32                             watermark_level;
 265         u32                             shp_addr, per_addr;
 266         struct dma_chan                 chan;
 267         spinlock_t                      lock;
 268         struct dma_async_tx_descriptor  desc;
 269         dma_cookie_t                    last_completed;
 270         enum dma_status                 status;
 271         unsigned int                    chn_count;
 272         unsigned int                    chn_real_count;
 273 };
 274
 275 #define IMX_DMA_SG_LOOP         (1 << 0)
 276
 277 #define MAX_DMA_CHANNELS 32
 278 #define MXC_SDMA_DEFAULT_PRIORITY 1
 279 #define MXC_SDMA_MIN_PRIORITY 1
 280 #define MXC_SDMA_MAX_PRIORITY 7
 281
 282 #define SDMA_FIRMWARE_MAGIC 0x414d4453
 283
 284 /**
 285  * struct sdma_firmware_header - Layout of the firmware image
 286  *
 287  * @magic               "SDMA"
 288  * @version_major       increased whenever layout of struct sdma_script_start_addrs
 289  *                      changes.
 290  * @version_minor       firmware minor version (for binary compatible changes)
 291  * @script_addrs_start  offset of struct sdma_script_start_addrs in this image
 292  * @num_script_addrs    Number of script addresses in this image
 293  * @ram_code_start      offset of SDMA ram image in this firmware image
 294  * @ram_code_size       size of SDMA ram image
 295  * @script_addrs        Stores the start address of the SDMA scripts
 296  *                      (in SDMA memory space)
 297  */
 298 struct sdma_firmware_header {
 299         u32     magic;
 300         u32     version_major;
 301         u32     version_minor;
 302         u32     script_addrs_start;
 303         u32     num_script_addrs;
 304         u32     ram_code_start;
 305         u32     ram_code_size;
 306 };
 307
 308 enum sdma_devtype {
 309         IMX31_SDMA,     /* runs on i.mx31 */
 310         IMX35_SDMA,     /* runs on i.mx35 and later */
 311 };
 312
 313 struct sdma_engine {
 314         struct device                   *dev;
 315         struct device_dma_parameters    dma_parms;
 316         struct sdma_channel             channel[MAX_DMA_CHANNELS];
 317         struct sdma_channel_control     *channel_control;
 318         void __iomem                    *regs;
 319         enum sdma_devtype               devtype;
 320         unsigned int                    num_events;
 321         struct sdma_context_data        *context;
 322         dma_addr_t                      context_phys;
 323         struct dma_device               dma_device;
 324         struct clk                      *clk;
 325         struct mutex                    channel_0_lock;
 326         struct sdma_script_start_addrs  *script_addrs;
 327 };
 328
 329 static struct platform_device_id sdma_devtypes[] = {
 330         {
 331                 .name = "imx31-sdma",
 332                 .driver_data = IMX31_SDMA,
 333         }, {
 334                 .name = "imx35-sdma",
 335                 .driver_data = IMX35_SDMA,
 336         }, {
 337                 /* sentinel */
 338         }
 339 };
 340 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
 341
 342 static const struct of_device_id sdma_dt_ids[] = {
 343         { .compatible = "fsl,imx31-sdma", .data = &sdma_devtypes[IMX31_SDMA], },
 344         { .compatible = "fsl,imx35-sdma", .data = &sdma_devtypes[IMX35_SDMA], },
 345         { /* sentinel */ }
 346 };
 347 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
 348
 349 #define SDMA_H_CONFIG_DSPDMA    (1 << 12) /* indicates if the DSPDMA is used */
 350 #define SDMA_H_CONFIG_RTD_PINS  (1 << 11) /* indicates if Real-Time Debug pins are enabled */
 351 #define SDMA_H_CONFIG_ACR       (1 << 4)  /* indicates if AHB freq /core freq = 2 or 1 */
 352 #define SDMA_H_CONFIG_CSM       (3)       /* indicates which context switch mode is selected*/
 353
 354 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
 355 {
 356         u32 chnenbl0 = (sdma->devtype == IMX31_SDMA ? SDMA_CHNENBL0_IMX31 :
 357                                                       SDMA_CHNENBL0_IMX35);
 358         return chnenbl0 + event * 4;
 359 }
 360
 361 static int sdma_config_ownership(struct sdma_channel *sdmac,
 362                 bool event_override, bool mcu_override, bool dsp_override)
 363 {
 364         struct sdma_engine *sdma = sdmac->sdma;
 365         int channel = sdmac->channel;
 366         u32 evt, mcu, dsp;
 367
 368         if (event_override && mcu_override && dsp_override)
 369                 return -EINVAL;
 370
 371         evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
 372         mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
 373         dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
 374
 375         if (dsp_override)
 376                 dsp &= ~(1 << channel);
 377         else
 378                 dsp |= (1 << channel);
 379
 380         if (event_override)
 381                 evt &= ~(1 << channel);
 382         else
 383                 evt |= (1 << channel);
 384
 385         if (mcu_override)
 386                 mcu &= ~(1 << channel);
 387         else
 388                 mcu |= (1 << channel);
 389
 390         writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
 391         writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
 392         writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
 393
 394         return 0;
 395 }
 396
 397 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
 398 {
 399         writel(1 << channel, sdma->regs + SDMA_H_START);
 400 }
 401
 402 /*
 403  * sdma_run_channel - run a channel and wait till it's done
 404  */
 405 static int sdma_run_channel(struct sdma_channel *sdmac)
 406 {
 407         struct sdma_engine *sdma = sdmac->sdma;
 408         int channel = sdmac->channel;
 409         int ret;
 410
 411         init_completion(&sdmac->done);
 412
 413         sdma_enable_channel(sdma, channel);
 414
 415         ret = wait_for_completion_timeout(&sdmac->done, HZ);
 416
 417         return ret ? 0 : -ETIMEDOUT;
 418 }
 419
 420 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
 421                 u32 address)
 422 {
 423         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 424         void *buf_virt;
 425         dma_addr_t buf_phys;
 426         int ret;
 427
 428         mutex_lock(&sdma->channel_0_lock);
 429
 430         buf_virt = dma_alloc_coherent(NULL,
 431                         size,
 432                         &buf_phys, GFP_KERNEL);
 433         if (!buf_virt) {
 434                 ret = -ENOMEM;
 435                 goto err_out;
 436         }
 437
 438         bd0->mode.command = C0_SETPM;
 439         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 440         bd0->mode.count = size / 2;
 441         bd0->buffer_addr = buf_phys;
 442         bd0->ext_buffer_addr = address;
 443
 444         memcpy(buf_virt, buf, size);
 445
 446         ret = sdma_run_channel(&sdma->channel[0]);
 447
 448         dma_free_coherent(NULL, size, buf_virt, buf_phys);
 449
 450 err_out:
 451         mutex_unlock(&sdma->channel_0_lock);
 452
 453         return ret;
 454 }
 455
 456 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
 457 {
 458         struct sdma_engine *sdma = sdmac->sdma;
 459         int channel = sdmac->channel;
 460         u32 val;
 461         u32 chnenbl = chnenbl_ofs(sdma, event);
 462
 463         val = readl_relaxed(sdma->regs + chnenbl);
 464         val |= (1 << channel);
 465         writel_relaxed(val, sdma->regs + chnenbl);
 466 }
 467
 468 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
 469 {
 470         struct sdma_engine *sdma = sdmac->sdma;
 471         int channel = sdmac->channel;
 472         u32 chnenbl = chnenbl_ofs(sdma, event);
 473         u32 val;
 474
 475         val = readl_relaxed(sdma->regs + chnenbl);
 476         val &= ~(1 << channel);
 477         writel_relaxed(val, sdma->regs + chnenbl);
 478 }
 479
 480 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
 481 {
 482         struct sdma_buffer_descriptor *bd;
 483
 484         /*
 485          * loop mode. Iterate over descriptors, re-setup them and
 486          * call callback function.
 487          */
 488         while (1) {
 489                 bd = &sdmac->bd[sdmac->buf_tail];
 490
 491                 if (bd->mode.status & BD_DONE)
 492                         break;
 493
 494                 if (bd->mode.status & BD_RROR)
 495                         sdmac->status = DMA_ERROR;
 496                 else
 497                         sdmac->status = DMA_IN_PROGRESS;
 498
 499                 bd->mode.status |= BD_DONE;
 500                 sdmac->buf_tail++;
 501                 sdmac->buf_tail %= sdmac->num_bd;
 502
 503                 if (sdmac->desc.callback)
 504                         sdmac->desc.callback(sdmac->desc.callback_param);
 505         }
 506 }
 507
 508 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
 509 {
 510         struct sdma_buffer_descriptor *bd;
 511         int i, error = 0;
 512
 513         sdmac->chn_real_count = 0;
 514         /*
 515          * non loop mode. Iterate over all descriptors, collect
 516          * errors and call callback function
 517          */
 518         for (i = 0; i < sdmac->num_bd; i++) {
 519                 bd = &sdmac->bd[i];
 520
 521                  if (bd->mode.status & (BD_DONE | BD_RROR))
 522                         error = -EIO;
 523                  sdmac->chn_real_count += bd->mode.count;
 524         }
 525
 526         if (error)
 527                 sdmac->status = DMA_ERROR;
 528         else
 529                 sdmac->status = DMA_SUCCESS;
 530
 531         sdmac->last_completed = sdmac->desc.cookie;
 532         if (sdmac->desc.callback)
 533                 sdmac->desc.callback(sdmac->desc.callback_param);
 534 }
 535
 536 static void mxc_sdma_handle_channel(struct sdma_channel *sdmac)
 537 {
 538         complete(&sdmac->done);
 539
 540         /* not interested in channel 0 interrupts */
 541         if (sdmac->channel == 0)
 542                 return;
 543
 544         if (sdmac->flags & IMX_DMA_SG_LOOP)
 545                 sdma_handle_channel_loop(sdmac);
 546         else
 547                 mxc_sdma_handle_channel_normal(sdmac);
 548 }
 549
 550 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
 551 {
 552         struct sdma_engine *sdma = dev_id;
 553         u32 stat;
 554
 555         stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
 556         writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
 557
 558         while (stat) {
 559                 int channel = fls(stat) - 1;
 560                 struct sdma_channel *sdmac = &sdma->channel[channel];
 561
 562                 mxc_sdma_handle_channel(sdmac);
 563
 564                 stat &= ~(1 << channel);
 565         }
 566
 567         return IRQ_HANDLED;
 568 }
 569
 570 /*
 571  * sets the pc of SDMA script according to the peripheral type
 572  */
 573 static void sdma_get_pc(struct sdma_channel *sdmac,
 574                 enum sdma_peripheral_type peripheral_type)
 575 {
 576         struct sdma_engine *sdma = sdmac->sdma;
 577         int per_2_emi = 0, emi_2_per = 0;
 578         /*
 579          * These are needed once we start to support transfers between
 580          * two peripherals or memory-to-memory transfers
 581          */
 582         int per_2_per = 0, emi_2_emi = 0;
 583
 584         sdmac->pc_from_device = 0;
 585         sdmac->pc_to_device = 0;
 586
 587         switch (peripheral_type) {
 588         case IMX_DMATYPE_MEMORY:
 589                 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
 590                 break;
 591         case IMX_DMATYPE_DSP:
 592                 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
 593                 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
 594                 break;
 595         case IMX_DMATYPE_FIRI:
 596                 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
 597                 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
 598                 break;
 599         case IMX_DMATYPE_UART:
 600                 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
 601                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 602                 break;
 603         case IMX_DMATYPE_UART_SP:
 604                 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
 605                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 606                 break;
 607         case IMX_DMATYPE_ATA:
 608                 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
 609                 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
 610                 break;
 611         case IMX_DMATYPE_CSPI:
 612         case IMX_DMATYPE_EXT:
 613         case IMX_DMATYPE_SSI:
 614                 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
 615                 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
 616                 break;
 617         case IMX_DMATYPE_SSI_SP:
 618         case IMX_DMATYPE_MMC:
 619         case IMX_DMATYPE_SDHC:
 620         case IMX_DMATYPE_CSPI_SP:
 621         case IMX_DMATYPE_ESAI:
 622         case IMX_DMATYPE_MSHC_SP:
 623                 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
 624                 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
 625                 break;
 626         case IMX_DMATYPE_ASRC:
 627                 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
 628                 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
 629                 per_2_per = sdma->script_addrs->per_2_per_addr;
 630                 break;
 631         case IMX_DMATYPE_MSHC:
 632                 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
 633                 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
 634                 break;
 635         case IMX_DMATYPE_CCM:
 636                 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
 637                 break;
 638         case IMX_DMATYPE_SPDIF:
 639                 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
 640                 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
 641                 break;
 642         case IMX_DMATYPE_IPU_MEMORY:
 643                 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
 644                 break;
 645         default:
 646                 break;
 647         }
 648
 649         sdmac->pc_from_device = per_2_emi;
 650         sdmac->pc_to_device = emi_2_per;
 651 }
 652
 653 static int sdma_load_context(struct sdma_channel *sdmac)
 654 {
 655         struct sdma_engine *sdma = sdmac->sdma;
 656         int channel = sdmac->channel;
 657         int load_address;
 658         struct sdma_context_data *context = sdma->context;
 659         struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
 660         int ret;
 661
 662         if (sdmac->direction == DMA_DEV_TO_MEM) {
 663                 load_address = sdmac->pc_from_device;
 664         } else {
 665                 load_address = sdmac->pc_to_device;
 666         }
 667
 668         if (load_address < 0)
 669                 return load_address;
 670
 671         dev_dbg(sdma->dev, "load_address = %d\n", load_address);
 672         dev_dbg(sdma->dev, "wml = 0x%08x\n", sdmac->watermark_level);
 673         dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
 674         dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
 675         dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", sdmac->event_mask0);
 676         dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", sdmac->event_mask1);
 677
 678         mutex_lock(&sdma->channel_0_lock);
 679
 680         memset(context, 0, sizeof(*context));
 681         context->channel_state.pc = load_address;
 682
 683         /* Send by context the event mask,base address for peripheral
 684          * and watermark level
 685          */
 686         context->gReg[0] = sdmac->event_mask1;
 687         context->gReg[1] = sdmac->event_mask0;
 688         context->gReg[2] = sdmac->per_addr;
 689         context->gReg[6] = sdmac->shp_addr;
 690         context->gReg[7] = sdmac->watermark_level;
 691
 692         bd0->mode.command = C0_SETDM;
 693         bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
 694         bd0->mode.count = sizeof(*context) / 4;
 695         bd0->buffer_addr = sdma->context_phys;
 696         bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
 697
 698         ret = sdma_run_channel(&sdma->channel[0]);
 699
 700         mutex_unlock(&sdma->channel_0_lock);
 701
 702         return ret;
 703 }
 704
 705 static void sdma_disable_channel(struct sdma_channel *sdmac)
 706 {
 707         struct sdma_engine *sdma = sdmac->sdma;
 708         int channel = sdmac->channel;
 709
 710         writel_relaxed(1 << channel, sdma->regs + SDMA_H_STATSTOP);
 711         sdmac->status = DMA_ERROR;
 712 }
 713
 714 static int sdma_config_channel(struct sdma_channel *sdmac)
 715 {
 716         int ret;
 717
 718         sdma_disable_channel(sdmac);
 719
 720         sdmac->event_mask0 = 0;
 721         sdmac->event_mask1 = 0;
 722         sdmac->shp_addr = 0;
 723         sdmac->per_addr = 0;
 724
 725         if (sdmac->event_id0) {
 726                 if (sdmac->event_id0 > 32)
 727                         return -EINVAL;
 728                 sdma_event_enable(sdmac, sdmac->event_id0);
 729         }
 730
 731         switch (sdmac->peripheral_type) {
 732         case IMX_DMATYPE_DSP:
 733                 sdma_config_ownership(sdmac, false, true, true);
 734                 break;
 735         case IMX_DMATYPE_MEMORY:
 736                 sdma_config_ownership(sdmac, false, true, false);
 737                 break;
 738         default:
 739                 sdma_config_ownership(sdmac, true, true, false);
 740                 break;
 741         }
 742
 743         sdma_get_pc(sdmac, sdmac->peripheral_type);
 744
 745         if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
 746                         (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
 747                 /* Handle multiple event channels differently */
 748                 if (sdmac->event_id1) {
 749                         sdmac->event_mask1 = 1 << (sdmac->event_id1 % 32);
 750                         if (sdmac->event_id1 > 31)
 751                                 sdmac->watermark_level |= 1 << 31;
 752                         sdmac->event_mask0 = 1 << (sdmac->event_id0 % 32);
 753                         if (sdmac->event_id0 > 31)
 754                                 sdmac->watermark_level |= 1 << 30;
 755                 } else {
 756                         sdmac->event_mask0 = 1 << sdmac->event_id0;
 757                         sdmac->event_mask1 = 1 << (sdmac->event_id0 - 32);
 758                 }
 759                 /* Watermark Level */
 760                 sdmac->watermark_level |= sdmac->watermark_level;
 761                 /* Address */
 762                 sdmac->shp_addr = sdmac->per_address;
 763         } else {
 764                 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
 765         }
 766
 767         ret = sdma_load_context(sdmac);
 768
 769         return ret;
 770 }
 771
 772 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
 773                 unsigned int priority)
 774 {
 775         struct sdma_engine *sdma = sdmac->sdma;
 776         int channel = sdmac->channel;
 777
 778         if (priority < MXC_SDMA_MIN_PRIORITY
 779             || priority > MXC_SDMA_MAX_PRIORITY) {
 780                 return -EINVAL;
 781         }
 782
 783         writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
 784
 785         return 0;
 786 }
 787
 788 static int sdma_request_channel(struct sdma_channel *sdmac)
 789 {
 790         struct sdma_engine *sdma = sdmac->sdma;
 791         int channel = sdmac->channel;
 792         int ret = -EBUSY;
 793
 794         sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
 795         if (!sdmac->bd) {
 796                 ret = -ENOMEM;
 797                 goto out;
 798         }
 799
 800         memset(sdmac->bd, 0, PAGE_SIZE);
 801
 802         sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
 803         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
 804
 805         clk_enable(sdma->clk);
 806
 807         sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
 808
 809         init_completion(&sdmac->done);
 810
 811         sdmac->buf_tail = 0;
 812
 813         return 0;
 814 out:
 815
 816         return ret;
 817 }
 818
 819 static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac)
 820 {
 821         dma_cookie_t cookie = sdmac->chan.cookie;
 822
 823         if (++cookie < 0)
 824                 cookie = 1;
 825
 826         sdmac->chan.cookie = cookie;
 827         sdmac->desc.cookie = cookie;
 828
 829         return cookie;
 830 }
 831
 832 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
 833 {
 834         return container_of(chan, struct sdma_channel, chan);
 835 }
 836
 837 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
 838 {
 839         unsigned long flags;
 840         struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
 841         dma_cookie_t cookie;
 842
 843         spin_lock_irqsave(&sdmac->lock, flags);
 844
 845         cookie = sdma_assign_cookie(sdmac);
 846
 847         spin_unlock_irqrestore(&sdmac->lock, flags);
 848
 849         return cookie;
 850 }
 851
 852 static int sdma_alloc_chan_resources(struct dma_chan *chan)
 853 {
 854         struct sdma_channel *sdmac = to_sdma_chan(chan);
 855         struct imx_dma_data *data = chan->private;
 856         int prio, ret;
 857
 858         if (!data)
 859                 return -EINVAL;
 860
 861         switch (data->priority) {
 862         case DMA_PRIO_HIGH:
 863                 prio = 3;
 864                 break;
 865         case DMA_PRIO_MEDIUM:
 866                 prio = 2;
 867                 break;
 868         case DMA_PRIO_LOW:
 869         default:
 870                 prio = 1;
 871                 break;
 872         }
 873
 874         sdmac->peripheral_type = data->peripheral_type;
 875         sdmac->event_id0 = data->dma_request;
 876         ret = sdma_request_channel(sdmac);
 877         if (ret)
 878                 return ret;
 879
 880         ret = sdma_set_channel_priority(sdmac, prio);
 881         if (ret)
 882                 return ret;
 883
 884         dma_async_tx_descriptor_init(&sdmac->desc, chan);
 885         sdmac->desc.tx_submit = sdma_tx_submit;
 886         /* txd.flags will be overwritten in prep funcs */
 887         sdmac->desc.flags = DMA_CTRL_ACK;
 888
 889         return 0;
 890 }
 891
 892 static void sdma_free_chan_resources(struct dma_chan *chan)
 893 {
 894         struct sdma_channel *sdmac = to_sdma_chan(chan);
 895         struct sdma_engine *sdma = sdmac->sdma;
 896
 897         sdma_disable_channel(sdmac);
 898
 899         if (sdmac->event_id0)
 900                 sdma_event_disable(sdmac, sdmac->event_id0);
 901         if (sdmac->event_id1)
 902                 sdma_event_disable(sdmac, sdmac->event_id1);
 903
 904         sdmac->event_id0 = 0;
 905         sdmac->event_id1 = 0;
 906
 907         sdma_set_channel_priority(sdmac, 0);
 908
 909         dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
 910
 911         clk_disable(sdma->clk);
 912 }
 913
 914 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
 915                 struct dma_chan *chan, struct scatterlist *sgl,
 916                 unsigned int sg_len, enum dma_transfer_direction direction,
 917                 unsigned long flags)
 918 {
 919         struct sdma_channel *sdmac = to_sdma_chan(chan);
 920         struct sdma_engine *sdma = sdmac->sdma;
 921         int ret, i, count;
 922         int channel = sdmac->channel;
 923         struct scatterlist *sg;
 924
 925         if (sdmac->status == DMA_IN_PROGRESS)
 926                 return NULL;
 927         sdmac->status = DMA_IN_PROGRESS;
 928
 929         sdmac->flags = 0;
 930
 931         dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
 932                         sg_len, channel);
 933
 934         sdmac->direction = direction;
 935         ret = sdma_load_context(sdmac);
 936         if (ret)
 937                 goto err_out;
 938
 939         if (sg_len > NUM_BD) {
 940                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
 941                                 channel, sg_len, NUM_BD);
 942                 ret = -EINVAL;
 943                 goto err_out;
 944         }
 945
 946         sdmac->chn_count = 0;
 947         for_each_sg(sgl, sg, sg_len, i) {
 948                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
 949                 int param;
 950
 951                 bd->buffer_addr = sg->dma_address;
 952
 953                 count = sg->length;
 954
 955                 if (count > 0xffff) {
 956                         dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
 957                                         channel, count, 0xffff);
 958                         ret = -EINVAL;
 959                         goto err_out;
 960                 }
 961
 962                 bd->mode.count = count;
 963                 sdmac->chn_count += count;
 964
 965                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
 966                         ret =  -EINVAL;
 967                         goto err_out;
 968                 }
 969
 970                 switch (sdmac->word_size) {
 971                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 972                         bd->mode.command = 0;
 973                         if (count & 3 || sg->dma_address & 3)
 974                                 return NULL;
 975                         break;
 976                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 977                         bd->mode.command = 2;
 978                         if (count & 1 || sg->dma_address & 1)
 979                                 return NULL;
 980                         break;
 981                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 982                         bd->mode.command = 1;
 983                         break;
 984                 default:
 985                         return NULL;
 986                 }
 987
 988                 param = BD_DONE | BD_EXTD | BD_CONT;
 989
 990                 if (i + 1 == sg_len) {
 991                         param |= BD_INTR;
 992                         param |= BD_LAST;
 993                         param &= ~BD_CONT;
 994                 }
 995
 996                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
 997                                 i, count, sg->dma_address,
 998                                 param & BD_WRAP ? "wrap" : "",
 999                                 param & BD_INTR ? " intr" : "");
1000
1001                 bd->mode.status = param;
1002         }
1003
1004         sdmac->num_bd = sg_len;
1005         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1006
1007         return &sdmac->desc;
1008 err_out:
1009         sdmac->status = DMA_ERROR;
1010         return NULL;
1011 }
1012
1013 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1014                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1015                 size_t period_len, enum dma_transfer_direction direction)
1016 {
1017         struct sdma_channel *sdmac = to_sdma_chan(chan);
1018         struct sdma_engine *sdma = sdmac->sdma;
1019         int num_periods = buf_len / period_len;
1020         int channel = sdmac->channel;
1021         int ret, i = 0, buf = 0;
1022
1023         dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1024
1025         if (sdmac->status == DMA_IN_PROGRESS)
1026                 return NULL;
1027
1028         sdmac->status = DMA_IN_PROGRESS;
1029
1030         sdmac->flags |= IMX_DMA_SG_LOOP;
1031         sdmac->direction = direction;
1032         ret = sdma_load_context(sdmac);
1033         if (ret)
1034                 goto err_out;
1035
1036         if (num_periods > NUM_BD) {
1037                 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1038                                 channel, num_periods, NUM_BD);
1039                 goto err_out;
1040         }
1041
1042         if (period_len > 0xffff) {
1043                 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1044                                 channel, period_len, 0xffff);
1045                 goto err_out;
1046         }
1047
1048         while (buf < buf_len) {
1049                 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1050                 int param;
1051
1052                 bd->buffer_addr = dma_addr;
1053
1054                 bd->mode.count = period_len;
1055
1056                 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1057                         goto err_out;
1058                 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1059                         bd->mode.command = 0;
1060                 else
1061                         bd->mode.command = sdmac->word_size;
1062
1063                 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1064                 if (i + 1 == num_periods)
1065                         param |= BD_WRAP;
1066
1067                 dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%08x %s%s\n",
1068                                 i, period_len, dma_addr,
1069                                 param & BD_WRAP ? "wrap" : "",
1070                                 param & BD_INTR ? " intr" : "");
1071
1072                 bd->mode.status = param;
1073
1074                 dma_addr += period_len;
1075                 buf += period_len;
1076
1077                 i++;
1078         }
1079
1080         sdmac->num_bd = num_periods;
1081         sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1082
1083         return &sdmac->desc;
1084 err_out:
1085         sdmac->status = DMA_ERROR;
1086         return NULL;
1087 }
1088
1089 static int sdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1090                 unsigned long arg)
1091 {
1092         struct sdma_channel *sdmac = to_sdma_chan(chan);
1093         struct dma_slave_config *dmaengine_cfg = (void *)arg;
1094
1095         switch (cmd) {
1096         case DMA_TERMINATE_ALL:
1097                 sdma_disable_channel(sdmac);
1098                 return 0;
1099         case DMA_SLAVE_CONFIG:
1100                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1101                         sdmac->per_address = dmaengine_cfg->src_addr;
1102                         sdmac->watermark_level = dmaengine_cfg->src_maxburst;
1103                         sdmac->word_size = dmaengine_cfg->src_addr_width;
1104                 } else {
1105                         sdmac->per_address = dmaengine_cfg->dst_addr;
1106                         sdmac->watermark_level = dmaengine_cfg->dst_maxburst;
1107                         sdmac->word_size = dmaengine_cfg->dst_addr_width;
1108                 }
1109                 sdmac->direction = dmaengine_cfg->direction;
1110                 return sdma_config_channel(sdmac);
1111         default:
1112                 return -ENOSYS;
1113         }
1114
1115         return -EINVAL;
1116 }
1117
1118 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1119                                             dma_cookie_t cookie,
1120                                             struct dma_tx_state *txstate)
1121 {
1122         struct sdma_channel *sdmac = to_sdma_chan(chan);
1123         dma_cookie_t last_used;
1124
1125         last_used = chan->cookie;
1126
1127         dma_set_tx_state(txstate, sdmac->last_completed, last_used,
1128                         sdmac->chn_count - sdmac->chn_real_count);
1129
1130         return sdmac->status;
1131 }
1132
1133 static void sdma_issue_pending(struct dma_chan *chan)
1134 {
1135         struct sdma_channel *sdmac = to_sdma_chan(chan);
1136         struct sdma_engine *sdma = sdmac->sdma;
1137
1138         if (sdmac->status == DMA_IN_PROGRESS)
1139                 sdma_enable_channel(sdma, sdmac->channel);
1140 }
1141
1142 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1143
1144 static void sdma_add_scripts(struct sdma_engine *sdma,
1145                 const struct sdma_script_start_addrs *addr)
1146 {
1147         s32 *addr_arr = (u32 *)addr;
1148         s32 *saddr_arr = (u32 *)sdma->script_addrs;
1149         int i;
1150
1151         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1152                 if (addr_arr[i] > 0)
1153                         saddr_arr[i] = addr_arr[i];
1154 }
1155
1156 static void sdma_load_firmware(const struct firmware *fw, void *context)
1157 {
1158         struct sdma_engine *sdma = context;
1159         const struct sdma_firmware_header *header;
1160         const struct sdma_script_start_addrs *addr;
1161         unsigned short *ram_code;
1162
1163         if (!fw) {
1164                 dev_err(sdma->dev, "firmware not found\n");
1165                 return;
1166         }
1167
1168         if (fw->size < sizeof(*header))
1169                 goto err_firmware;
1170
1171         header = (struct sdma_firmware_header *)fw->data;
1172
1173         if (header->magic != SDMA_FIRMWARE_MAGIC)
1174                 goto err_firmware;
1175         if (header->ram_code_start + header->ram_code_size > fw->size)
1176                 goto err_firmware;
1177
1178         addr = (void *)header + header->script_addrs_start;
1179         ram_code = (void *)header + header->ram_code_start;
1180
1181         clk_enable(sdma->clk);
1182         /* download the RAM image for SDMA */
1183         sdma_load_script(sdma, ram_code,
1184                         header->ram_code_size,
1185                         addr->ram_code_start_addr);
1186         clk_disable(sdma->clk);
1187
1188         sdma_add_scripts(sdma, addr);
1189
1190         dev_info(sdma->dev, "loaded firmware %d.%d\n",
1191                         header->version_major,
1192                         header->version_minor);
1193
1194 err_firmware:
1195         release_firmware(fw);
1196 }
1197
1198 static int __init sdma_get_firmware(struct sdma_engine *sdma,
1199                 const char *fw_name)
1200 {
1201         int ret;
1202
1203         ret = request_firmware_nowait(THIS_MODULE,
1204                         FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1205                         GFP_KERNEL, sdma, sdma_load_firmware);
1206
1207         return ret;
1208 }
1209
1210 static int __init sdma_init(struct sdma_engine *sdma)
1211 {
1212         int i, ret;
1213         dma_addr_t ccb_phys;
1214
1215         switch (sdma->devtype) {
1216         case IMX31_SDMA:
1217                 sdma->num_events = 32;
1218                 break;
1219         case IMX35_SDMA:
1220                 sdma->num_events = 48;
1221                 break;
1222         default:
1223                 dev_err(sdma->dev, "Unknown sdma type %d. aborting\n",
1224                         sdma->devtype);
1225                 return -ENODEV;
1226         }
1227
1228         clk_enable(sdma->clk);
1229
1230         /* Be sure SDMA has not started yet */
1231         writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1232
1233         sdma->channel_control = dma_alloc_coherent(NULL,
1234                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1235                         sizeof(struct sdma_context_data),
1236                         &ccb_phys, GFP_KERNEL);
1237
1238         if (!sdma->channel_control) {
1239                 ret = -ENOMEM;
1240                 goto err_dma_alloc;
1241         }
1242
1243         sdma->context = (void *)sdma->channel_control +
1244                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1245         sdma->context_phys = ccb_phys +
1246                 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1247
1248         /* Zero-out the CCB structures array just allocated */
1249         memset(sdma->channel_control, 0,
1250                         MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1251
1252         /* disable all channels */
1253         for (i = 0; i < sdma->num_events; i++)
1254                 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1255
1256         /* All channels have priority 0 */
1257         for (i = 0; i < MAX_DMA_CHANNELS; i++)
1258                 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1259
1260         ret = sdma_request_channel(&sdma->channel[0]);
1261         if (ret)
1262                 goto err_dma_alloc;
1263
1264         sdma_config_ownership(&sdma->channel[0], false, true, false);
1265
1266         /* Set Command Channel (Channel Zero) */
1267         writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1268
1269         /* Set bits of CONFIG register but with static context switching */
1270         /* FIXME: Check whether to set ACR bit depending on clock ratios */
1271         writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1272
1273         writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1274
1275         /* Set bits of CONFIG register with given context switching mode */
1276         writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
1277
1278         /* Initializes channel's priorities */
1279         sdma_set_channel_priority(&sdma->channel[0], 7);
1280
1281         clk_disable(sdma->clk);
1282
1283         return 0;
1284
1285 err_dma_alloc:
1286         clk_disable(sdma->clk);
1287         dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1288         return ret;
1289 }
1290
1291 static int __init sdma_probe(struct platform_device *pdev)
1292 {
1293         const struct of_device_id *of_id =
1294                         of_match_device(sdma_dt_ids, &pdev->dev);
1295         struct device_node *np = pdev->dev.of_node;
1296         const char *fw_name;
1297         int ret;
1298         int irq;
1299         struct resource *iores;
1300         struct sdma_platform_data *pdata = pdev->dev.platform_data;
1301         int i;
1302         struct sdma_engine *sdma;
1303         s32 *saddr_arr;
1304
1305         sdma = kzalloc(sizeof(*sdma), GFP_KERNEL);
1306         if (!sdma)
1307                 return -ENOMEM;
1308
1309         mutex_init(&sdma->channel_0_lock);
1310
1311         sdma->dev = &pdev->dev;
1312
1313         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1314         irq = platform_get_irq(pdev, 0);
1315         if (!iores || irq < 0) {
1316                 ret = -EINVAL;
1317                 goto err_irq;
1318         }
1319
1320         if (!request_mem_region(iores->start, resource_size(iores), pdev->name)) {
1321                 ret = -EBUSY;
1322                 goto err_request_region;
1323         }
1324
1325         sdma->clk = clk_get(&pdev->dev, NULL);
1326         if (IS_ERR(sdma->clk)) {
1327                 ret = PTR_ERR(sdma->clk);
1328                 goto err_clk;
1329         }
1330
1331         sdma->regs = ioremap(iores->start, resource_size(iores));
1332         if (!sdma->regs) {
1333                 ret = -ENOMEM;
1334                 goto err_ioremap;
1335         }
1336
1337         ret = request_irq(irq, sdma_int_handler, 0, "sdma", sdma);
1338         if (ret)
1339                 goto err_request_irq;
1340
1341         sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1342         if (!sdma->script_addrs) {
1343                 ret = -ENOMEM;
1344                 goto err_alloc;
1345         }
1346
1347         /* initially no scripts available */
1348         saddr_arr = (s32 *)sdma->script_addrs;
1349         for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1350                 saddr_arr[i] = -EINVAL;
1351
1352         if (of_id)
1353                 pdev->id_entry = of_id->data;
1354         sdma->devtype = pdev->id_entry->driver_data;
1355
1356         dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1357         dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1358
1359         INIT_LIST_HEAD(&sdma->dma_device.channels);
1360         /* Initialize channel parameters */
1361         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1362                 struct sdma_channel *sdmac = &sdma->channel[i];
1363
1364                 sdmac->sdma = sdma;
1365                 spin_lock_init(&sdmac->lock);
1366
1367                 sdmac->chan.device = &sdma->dma_device;
1368                 sdmac->channel = i;
1369
1370                 /*
1371                  * Add the channel to the DMAC list. Do not add channel 0 though
1372                  * because we need it internally in the SDMA driver. This also means
1373                  * that channel 0 in dmaengine counting matches sdma channel 1.
1374                  */
1375                 if (i)
1376                         list_add_tail(&sdmac->chan.device_node,
1377                                         &sdma->dma_device.channels);
1378         }
1379
1380         ret = sdma_init(sdma);
1381         if (ret)
1382                 goto err_init;
1383
1384         if (pdata && pdata->script_addrs)
1385                 sdma_add_scripts(sdma, pdata->script_addrs);
1386
1387         if (pdata) {
1388                 sdma_get_firmware(sdma, pdata->fw_name);
1389         } else {
1390                 /*
1391                  * Because that device tree does not encode ROM script address,
1392                  * the RAM script in firmware is mandatory for device tree
1393                  * probe, otherwise it fails.
1394                  */
1395                 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1396                                               &fw_name);
1397                 if (ret) {
1398                         dev_err(&pdev->dev, "failed to get firmware name\n");
1399                         goto err_init;
1400                 }
1401
1402                 ret = sdma_get_firmware(sdma, fw_name);
1403                 if (ret) {
1404                         dev_err(&pdev->dev, "failed to get firmware\n");
1405                         goto err_init;
1406                 }
1407         }
1408
1409         sdma->dma_device.dev = &pdev->dev;
1410
1411         sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1412         sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1413         sdma->dma_device.device_tx_status = sdma_tx_status;
1414         sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1415         sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1416         sdma->dma_device.device_control = sdma_control;
1417         sdma->dma_device.device_issue_pending = sdma_issue_pending;
1418         sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1419         dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1420
1421         ret = dma_async_device_register(&sdma->dma_device);
1422         if (ret) {
1423                 dev_err(&pdev->dev, "unable to register\n");
1424                 goto err_init;
1425         }
1426
1427         dev_info(sdma->dev, "initialized\n");
1428
1429         return 0;
1430
1431 err_init:
1432         kfree(sdma->script_addrs);
1433 err_alloc:
1434         free_irq(irq, sdma);
1435 err_request_irq:
1436         iounmap(sdma->regs);
1437 err_ioremap:
1438         clk_put(sdma->clk);
1439 err_clk:
1440         release_mem_region(iores->start, resource_size(iores));
1441 err_request_region:
1442 err_irq:
1443         kfree(sdma);
1444         return ret;
1445 }
1446
1447 static int __exit sdma_remove(struct platform_device *pdev)
1448 {
1449         return -EBUSY;
1450 }
1451
1452 static struct platform_driver sdma_driver = {
1453         .driver         = {
1454                 .name   = "imx-sdma",
1455                 .of_match_table = sdma_dt_ids,
1456         },
1457         .id_table       = sdma_devtypes,
1458         .remove         = __exit_p(sdma_remove),
1459 };
1460
1461 static int __init sdma_module_init(void)
1462 {
1463         return platform_driver_probe(&sdma_driver, sdma_probe);
1464 }
1465 module_init(sdma_module_init);
1466
1467 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1468 MODULE_DESCRIPTION("i.MX SDMA driver");
1469 MODULE_LICENSE("GPL");