2 * Driver for the Synopsys DesignWare AHB DMA Controller
4 * Copyright (C) 2005-2007 Atmel Corporation
5 * Copyright (C) 2010-2011 ST Microelectronics
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/dmaengine.h>
13 #include <linux/dw_dmac.h>
15 #define DW_DMA_MAX_NR_CHANNELS 8
30 * Redefine this macro to handle differences between 32- and 64-bit
31 * addressing, big vs. little endian, etc.
33 #define DW_REG(name) u32 name; u32 __pad_##name
35 /* Hardware register definitions. */
36 struct dw_dma_chan_regs {
37 DW_REG(SAR); /* Source Address Register */
38 DW_REG(DAR); /* Destination Address Register */
39 DW_REG(LLP); /* Linked List Pointer */
40 u32 CTL_LO; /* Control Register Low */
41 u32 CTL_HI; /* Control Register High */
46 u32 CFG_LO; /* Configuration Register Low */
47 u32 CFG_HI; /* Configuration Register High */
52 struct dw_dma_irq_regs {
61 /* per-channel registers */
62 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
65 struct dw_dma_irq_regs RAW; /* r */
66 struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
67 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
68 struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
70 DW_REG(STATUS_INT); /* r */
72 /* software handshaking */
90 /* optional encoded params, 0x3c8..0x3f7 */
93 /* per-channel configuration registers */
94 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
98 /* top-level parameters */
102 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
103 #define dma_readl_native ioread32be
104 #define dma_writel_native iowrite32be
106 #define dma_readl_native readl
107 #define dma_writel_native writel
110 /* To access the registers in early stage of probe */
111 #define dma_read_byaddr(addr, name) \
112 dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
114 /* Bitfields in DW_PARAMS */
115 #define DW_PARAMS_NR_CHAN 8 /* number of channels */
116 #define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */
117 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
118 #define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */
119 #define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */
120 #define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */
121 #define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */
122 #define DW_PARAMS_EN 28 /* encoded parameters */
124 /* Bitfields in DWC_PARAMS */
125 #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
127 /* Bitfields in CTL_LO */
128 #define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
129 #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
130 #define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
131 #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
132 #define DWC_CTLL_DST_DEC (1<<7)
133 #define DWC_CTLL_DST_FIX (2<<7)
134 #define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
135 #define DWC_CTLL_SRC_DEC (1<<9)
136 #define DWC_CTLL_SRC_FIX (2<<9)
137 #define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
138 #define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
139 #define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
140 #define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
141 #define DWC_CTLL_FC(n) ((n) << 20)
142 #define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
143 #define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
144 #define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
145 #define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
146 /* plus 4 transfer types for peripheral-as-flow-controller */
147 #define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
148 #define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
149 #define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
150 #define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
152 /* Bitfields in CTL_HI */
153 #define DWC_CTLH_DONE 0x00001000
154 #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
156 /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
157 #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */
158 #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */
159 #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
160 #define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
161 #define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
162 #define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
163 #define DWC_CFGL_MAX_BURST(x) ((x) << 20)
164 #define DWC_CFGL_RELOAD_SAR (1 << 30)
165 #define DWC_CFGL_RELOAD_DAR (1 << 31)
167 /* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
168 #define DWC_CFGH_DS_UPD_EN (1 << 5)
169 #define DWC_CFGH_SS_UPD_EN (1 << 6)
171 /* Bitfields in SGR */
172 #define DWC_SGR_SGI(x) ((x) << 0)
173 #define DWC_SGR_SGC(x) ((x) << 20)
175 /* Bitfields in DSR */
176 #define DWC_DSR_DSI(x) ((x) << 0)
177 #define DWC_DSR_DSC(x) ((x) << 20)
179 /* Bitfields in CFG */
180 #define DW_CFG_DMA_EN (1 << 0)
183 DW_DMA_IS_CYCLIC = 0,
184 DW_DMA_IS_SOFT_LLP = 1,
188 struct dma_chan chan;
189 void __iomem *ch_regs;
192 enum dma_transfer_direction direction;
196 /* software emulation of the LLP transfers */
197 struct list_head *tx_node_active;
201 /* these other elements are all protected by lock */
203 struct list_head active_list;
204 struct list_head queue;
205 struct list_head free_list;
207 struct dw_cyclic_desc *cdesc;
209 unsigned int descs_allocated;
211 /* hardware configuration */
212 unsigned int block_size;
215 /* configuration passed via DMA_SLAVE_CONFIG */
216 struct dma_slave_config dma_sconfig;
219 static inline struct dw_dma_chan_regs __iomem *
220 __dwc_regs(struct dw_dma_chan *dwc)
225 #define channel_readl(dwc, name) \
226 dma_readl_native(&(__dwc_regs(dwc)->name))
227 #define channel_writel(dwc, name, val) \
228 dma_writel_native((val), &(__dwc_regs(dwc)->name))
230 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
232 return container_of(chan, struct dw_dma_chan, chan);
236 struct dma_device dma;
238 struct dma_pool *desc_pool;
239 struct tasklet_struct tasklet;
242 /* slave information */
243 struct dw_dma_slave *sd;
244 unsigned int sd_count;
248 /* hardware configuration */
249 unsigned char nr_masters;
250 unsigned char data_width[4];
252 struct dw_dma_chan chan[0];
255 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
260 #define dma_readl(dw, name) \
261 dma_readl_native(&(__dw_regs(dw)->name))
262 #define dma_writel(dw, name, val) \
263 dma_writel_native((val), &(__dw_regs(dw)->name))
265 #define channel_set_bit(dw, reg, mask) \
266 dma_writel(dw, reg, ((mask) << 8) | (mask))
267 #define channel_clear_bit(dw, reg, mask) \
268 dma_writel(dw, reg, ((mask) << 8) | 0)
270 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
272 return container_of(ddev, struct dw_dma, dma);
275 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
277 /* values that are not changed by hardware */
280 u32 llp; /* chain to next lli */
282 /* values that may get written back: */
284 /* sstat and dstat can snapshot peripheral register state.
285 * silicon config may discard either or both...
292 /* FIRST values the hardware uses */
295 /* THEN values for driver housekeeping */
296 struct list_head desc_node;
297 struct list_head tx_list;
298 struct dma_async_tx_descriptor txd;
303 #define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node)
305 static inline struct dw_desc *
306 txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
308 return container_of(txd, struct dw_desc, txd);