2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
70 * - Break out common code from arch/arm/mach-s3c64xx and share
72 #include <linux/amba/bus.h>
73 #include <linux/amba/pl08x.h>
74 #include <linux/debugfs.h>
75 #include <linux/delay.h>
76 #include <linux/device.h>
77 #include <linux/dmaengine.h>
78 #include <linux/dmapool.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/interrupt.h>
82 #include <linux/module.h>
83 #include <linux/pm_runtime.h>
84 #include <linux/seq_file.h>
85 #include <linux/slab.h>
86 #include <asm/hardware/pl080.h>
88 #define DRIVER_NAME "pl08xdmac"
90 static struct amba_driver pl08x_amba_driver;
93 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
94 * @channels: the number of channels available in this variant
95 * @dualmaster: whether this version supports dual AHB masters or not.
103 * PL08X private data structures
104 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
105 * start & end do not - their bus bit info is in cctl. Also note that these
106 * are fixed 32-bit quantities.
116 * struct pl08x_driver_data - the local state holder for the PL08x
117 * @slave: slave engine for this instance
118 * @memcpy: memcpy engine for this instance
119 * @base: virtual memory base (remapped) for the PL08x
120 * @adev: the corresponding AMBA (PrimeCell) bus entry
121 * @vd: vendor data for this PL08x variant
122 * @pd: platform data passed in from the platform/machine
123 * @phy_chans: array of data for the physical channels
124 * @pool: a pool for the LLI descriptors
125 * @pool_ctr: counter of LLIs in the pool
126 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
128 * @mem_buses: set to indicate memory transfers on AHB2.
129 * @lock: a spinlock for this struct
131 struct pl08x_driver_data {
132 struct dma_device slave;
133 struct dma_device memcpy;
135 struct amba_device *adev;
136 const struct vendor_data *vd;
137 struct pl08x_platform_data *pd;
138 struct pl08x_phy_chan *phy_chans;
139 struct dma_pool *pool;
147 * PL08X specific defines
150 /* Size (bytes) of each LLI buffer allocated for one transfer */
151 # define PL08X_LLI_TSFR_SIZE 0x2000
153 /* Maximum times we call dma_pool_alloc on this pool without freeing */
154 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
155 #define PL08X_ALIGN 8
157 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
159 return container_of(chan, struct pl08x_dma_chan, chan);
162 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
164 return container_of(tx, struct pl08x_txd, tx);
168 * Physical channel handling
171 /* Whether a certain channel is busy or not */
172 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
176 val = readl(ch->base + PL080_CH_CONFIG);
177 return val & PL080_CONFIG_ACTIVE;
181 * Set the initial DMA register values i.e. those for the first LLI
182 * The next LLI pointer and the configuration interrupt bit have
183 * been set when the LLIs were constructed. Poke them into the hardware
184 * and start the transfer.
186 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
187 struct pl08x_txd *txd)
189 struct pl08x_driver_data *pl08x = plchan->host;
190 struct pl08x_phy_chan *phychan = plchan->phychan;
191 struct pl08x_lli *lli = &txd->llis_va[0];
196 /* Wait for channel inactive */
197 while (pl08x_phy_channel_busy(phychan))
200 dev_vdbg(&pl08x->adev->dev,
201 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
202 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
203 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
206 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
207 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
208 writel(lli->lli, phychan->base + PL080_CH_LLI);
209 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
210 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
212 /* Enable the DMA channel */
213 /* Do not access config register until channel shows as disabled */
214 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
217 /* Do not access config register until channel shows as inactive */
218 val = readl(phychan->base + PL080_CH_CONFIG);
219 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
220 val = readl(phychan->base + PL080_CH_CONFIG);
222 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
226 * Pause the channel by setting the HALT bit.
228 * For M->P transfers, pause the DMAC first and then stop the peripheral -
229 * the FIFO can only drain if the peripheral is still requesting data.
230 * (note: this can still timeout if the DMAC FIFO never drains of data.)
232 * For P->M transfers, disable the peripheral first to stop it filling
233 * the DMAC FIFO, and then pause the DMAC.
235 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
240 /* Set the HALT bit and wait for the FIFO to drain */
241 val = readl(ch->base + PL080_CH_CONFIG);
242 val |= PL080_CONFIG_HALT;
243 writel(val, ch->base + PL080_CH_CONFIG);
245 /* Wait for channel inactive */
246 for (timeout = 1000; timeout; timeout--) {
247 if (!pl08x_phy_channel_busy(ch))
251 if (pl08x_phy_channel_busy(ch))
252 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
255 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
259 /* Clear the HALT bit */
260 val = readl(ch->base + PL080_CH_CONFIG);
261 val &= ~PL080_CONFIG_HALT;
262 writel(val, ch->base + PL080_CH_CONFIG);
266 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
267 * clears any pending interrupt status. This should not be used for
268 * an on-going transfer, but as a method of shutting down a channel
269 * (eg, when it's no longer used) or terminating a transfer.
271 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
272 struct pl08x_phy_chan *ch)
274 u32 val = readl(ch->base + PL080_CH_CONFIG);
276 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
277 PL080_CONFIG_TC_IRQ_MASK);
279 writel(val, ch->base + PL080_CH_CONFIG);
281 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
282 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
285 static inline u32 get_bytes_in_cctl(u32 cctl)
287 /* The source width defines the number of bytes */
288 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
290 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
291 case PL080_WIDTH_8BIT:
293 case PL080_WIDTH_16BIT:
296 case PL080_WIDTH_32BIT:
303 /* The channel should be paused when calling this */
304 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
306 struct pl08x_phy_chan *ch;
307 struct pl08x_txd *txd;
311 spin_lock_irqsave(&plchan->lock, flags);
312 ch = plchan->phychan;
316 * Follow the LLIs to get the number of remaining
317 * bytes in the currently active transaction.
320 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
322 /* First get the remaining bytes in the active transfer */
323 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
326 struct pl08x_lli *llis_va = txd->llis_va;
327 dma_addr_t llis_bus = txd->llis_bus;
330 BUG_ON(clli < llis_bus || clli >= llis_bus +
331 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
334 * Locate the next LLI - as this is an array,
335 * it's simple maths to find.
337 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
339 for (; index < MAX_NUM_TSFR_LLIS; index++) {
340 bytes += get_bytes_in_cctl(llis_va[index].cctl);
343 * A LLI pointer of 0 terminates the LLI list
345 if (!llis_va[index].lli)
351 /* Sum up all queued transactions */
352 if (!list_empty(&plchan->pend_list)) {
353 struct pl08x_txd *txdi;
354 list_for_each_entry(txdi, &plchan->pend_list, node) {
359 spin_unlock_irqrestore(&plchan->lock, flags);
365 * Allocate a physical channel for a virtual channel
367 * Try to locate a physical channel to be used for this transfer. If all
368 * are taken return NULL and the requester will have to cope by using
369 * some fallback PIO mode or retrying later.
371 static struct pl08x_phy_chan *
372 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
373 struct pl08x_dma_chan *virt_chan)
375 struct pl08x_phy_chan *ch = NULL;
379 for (i = 0; i < pl08x->vd->channels; i++) {
380 ch = &pl08x->phy_chans[i];
382 spin_lock_irqsave(&ch->lock, flags);
385 ch->serving = virt_chan;
387 spin_unlock_irqrestore(&ch->lock, flags);
391 spin_unlock_irqrestore(&ch->lock, flags);
394 if (i == pl08x->vd->channels) {
395 /* No physical channel available, cope with it */
399 pm_runtime_get_sync(&pl08x->adev->dev);
403 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
404 struct pl08x_phy_chan *ch)
408 spin_lock_irqsave(&ch->lock, flags);
410 /* Stop the channel and clear its interrupts */
411 pl08x_terminate_phy_chan(pl08x, ch);
413 pm_runtime_put(&pl08x->adev->dev);
415 /* Mark it as free */
417 spin_unlock_irqrestore(&ch->lock, flags);
424 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
427 case PL080_WIDTH_8BIT:
429 case PL080_WIDTH_16BIT:
431 case PL080_WIDTH_32BIT:
440 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
445 /* Remove all src, dst and transfer size bits */
446 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
447 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
448 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
450 /* Then set the bits according to the parameters */
453 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
456 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
459 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
468 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
471 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
474 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
481 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
485 struct pl08x_lli_build_data {
486 struct pl08x_txd *txd;
487 struct pl08x_bus_data srcbus;
488 struct pl08x_bus_data dstbus;
494 * Autoselect a master bus to use for the transfer. Slave will be the chosen as
495 * victim in case src & dest are not similarly aligned. i.e. If after aligning
496 * masters address with width requirements of transfer (by sending few byte by
497 * byte data), slave is still not aligned, then its width will be reduced to
499 * - prefers the destination bus if both available
500 * - prefers bus with fixed address (i.e. peripheral)
502 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
503 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
505 if (!(cctl & PL080_CONTROL_DST_INCR)) {
508 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
512 if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
523 * Fills in one LLI for a certain transfer descriptor and advance the counter
525 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
526 int num_llis, int len, u32 cctl)
528 struct pl08x_lli *llis_va = bd->txd->llis_va;
529 dma_addr_t llis_bus = bd->txd->llis_bus;
531 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
533 llis_va[num_llis].cctl = cctl;
534 llis_va[num_llis].src = bd->srcbus.addr;
535 llis_va[num_llis].dst = bd->dstbus.addr;
536 llis_va[num_llis].lli = llis_bus + (num_llis + 1) *
537 sizeof(struct pl08x_lli);
538 llis_va[num_llis].lli |= bd->lli_bus;
540 if (cctl & PL080_CONTROL_SRC_INCR)
541 bd->srcbus.addr += len;
542 if (cctl & PL080_CONTROL_DST_INCR)
543 bd->dstbus.addr += len;
545 BUG_ON(bd->remainder < len);
547 bd->remainder -= len;
550 static inline void prep_byte_width_lli(struct pl08x_lli_build_data *bd,
551 u32 *cctl, u32 len, int num_llis, size_t *total_bytes)
553 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len);
554 pl08x_fill_lli_for_desc(bd, num_llis, len, *cctl);
555 (*total_bytes) += len;
559 * This fills in the table of LLIs for the transfer descriptor
560 * Note that we assume we never have to change the burst sizes
563 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
564 struct pl08x_txd *txd)
566 struct pl08x_bus_data *mbus, *sbus;
567 struct pl08x_lli_build_data bd;
569 u32 cctl, early_bytes = 0;
570 size_t max_bytes_per_lli, total_bytes = 0;
571 struct pl08x_lli *llis_va;
573 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
575 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
581 /* Get the default CCTL */
585 bd.srcbus.addr = txd->src_addr;
586 bd.dstbus.addr = txd->dst_addr;
587 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
589 /* Find maximum width of the source bus */
591 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
592 PL080_CONTROL_SWIDTH_SHIFT);
594 /* Find maximum width of the destination bus */
596 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
597 PL080_CONTROL_DWIDTH_SHIFT);
599 /* Set up the bus widths to the maximum */
600 bd.srcbus.buswidth = bd.srcbus.maxwidth;
601 bd.dstbus.buswidth = bd.dstbus.maxwidth;
603 /* We need to count this down to zero */
604 bd.remainder = txd->len;
606 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
608 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n",
609 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
611 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
614 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
615 mbus == &bd.srcbus ? "src" : "dst",
616 sbus == &bd.srcbus ? "src" : "dst");
619 * Zero length is only allowed if all these requirements are met:
620 * - flow controller is peripheral.
621 * - src.addr is aligned to src.width
622 * - dst.addr is aligned to dst.width
624 * sg_len == 1 should be true, as there can be two cases here:
625 * - Memory addresses are contiguous and are not scattered. Here, Only
626 * one sg will be passed by user driver, with memory address and zero
627 * length. We pass this to controller and after the transfer it will
628 * receive the last burst request from peripheral and so transfer
631 * - Memory addresses are scattered and are not contiguous. Here,
632 * Obviously as DMA controller doesn't know when a lli's transfer gets
633 * over, it can't load next lli. So in this case, there has to be an
634 * assumption that only one lli is supported. Thus, we can't have
635 * scattered addresses.
638 u32 fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
639 PL080_CONFIG_FLOW_CONTROL_SHIFT;
640 if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
641 (fc <= PL080_FLOW_SRC2DST_SRC))) {
642 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
647 if ((bd.srcbus.addr % bd.srcbus.buswidth) ||
648 (bd.srcbus.addr % bd.srcbus.buswidth)) {
649 dev_err(&pl08x->adev->dev,
650 "%s src & dst address must be aligned to src"
651 " & dst width if peripheral is flow controller",
656 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
657 bd.dstbus.buswidth, 0);
658 pl08x_fill_lli_for_desc(&bd, num_llis++, 0, cctl);
662 * Send byte by byte for following cases
663 * - Less than a bus width available
664 * - until master bus is aligned
666 if (bd.remainder < mbus->buswidth)
667 early_bytes = bd.remainder;
668 else if ((mbus->addr) % (mbus->buswidth)) {
669 early_bytes = mbus->buswidth - (mbus->addr) % (mbus->buswidth);
670 if ((bd.remainder - early_bytes) < mbus->buswidth)
671 early_bytes = bd.remainder;
675 dev_vdbg(&pl08x->adev->dev, "%s byte width LLIs "
676 "(remain 0x%08x)\n", __func__, bd.remainder);
677 prep_byte_width_lli(&bd, &cctl, early_bytes, num_llis++,
684 * - if slave is not then we must set its width down
686 if (sbus->addr % sbus->buswidth) {
687 dev_dbg(&pl08x->adev->dev,
688 "%s set down bus width to one byte\n",
694 /* Bytes transferred = tsize * src width, not MIN(buswidths) */
695 max_bytes_per_lli = bd.srcbus.buswidth *
696 PL080_CONTROL_TRANSFER_SIZE_MASK;
699 * Make largest possible LLIs until less than one bus
702 while (bd.remainder > (mbus->buswidth - 1)) {
703 size_t lli_len, tsize, width;
706 * If enough left try to send max possible,
707 * otherwise try to send the remainder
709 lli_len = min(bd.remainder, max_bytes_per_lli);
712 * Check against maximum bus alignment: Calculate actual
713 * transfer size in relation to bus width and get a
714 * maximum remainder of the highest bus width - 1
716 width = max(mbus->buswidth, sbus->buswidth);
717 lli_len = (lli_len / width) * width;
718 tsize = lli_len / bd.srcbus.buswidth;
720 dev_vdbg(&pl08x->adev->dev,
721 "%s fill lli with single lli chunk of "
722 "size 0x%08zx (remainder 0x%08zx)\n",
723 __func__, lli_len, bd.remainder);
725 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth,
726 bd.dstbus.buswidth, tsize);
727 pl08x_fill_lli_for_desc(&bd, num_llis++, lli_len, cctl);
728 total_bytes += lli_len;
735 dev_vdbg(&pl08x->adev->dev,
736 "%s align with boundary, send odd bytes (remain %zu)\n",
737 __func__, bd.remainder);
738 prep_byte_width_lli(&bd, &cctl, bd.remainder,
739 num_llis++, &total_bytes);
743 if (total_bytes != txd->len) {
744 dev_err(&pl08x->adev->dev,
745 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
746 __func__, total_bytes, txd->len);
750 if (num_llis >= MAX_NUM_TSFR_LLIS) {
751 dev_err(&pl08x->adev->dev,
752 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
753 __func__, (u32) MAX_NUM_TSFR_LLIS);
757 llis_va = txd->llis_va;
758 /* The final LLI terminates the LLI. */
759 llis_va[num_llis - 1].lli = 0;
760 /* The final LLI element shall also fire an interrupt. */
761 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
767 dev_vdbg(&pl08x->adev->dev,
768 "%-3s %-9s %-10s %-10s %-10s %s\n",
769 "lli", "", "csrc", "cdst", "clli", "cctl");
770 for (i = 0; i < num_llis; i++) {
771 dev_vdbg(&pl08x->adev->dev,
772 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
773 i, &llis_va[i], llis_va[i].src,
774 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
783 /* You should call this with the struct pl08x lock held */
784 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
785 struct pl08x_txd *txd)
788 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
795 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
796 struct pl08x_dma_chan *plchan)
798 struct pl08x_txd *txdi = NULL;
799 struct pl08x_txd *next;
801 if (!list_empty(&plchan->pend_list)) {
802 list_for_each_entry_safe(txdi,
803 next, &plchan->pend_list, node) {
804 list_del(&txdi->node);
805 pl08x_free_txd(pl08x, txdi);
813 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
818 static void pl08x_free_chan_resources(struct dma_chan *chan)
823 * This should be called with the channel plchan->lock held
825 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
826 struct pl08x_txd *txd)
828 struct pl08x_driver_data *pl08x = plchan->host;
829 struct pl08x_phy_chan *ch;
832 /* Check if we already have a channel */
836 ch = pl08x_get_phy_channel(pl08x, plchan);
838 /* No physical channel available, cope with it */
839 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
844 * OK we have a physical channel: for memcpy() this is all we
845 * need, but for slaves the physical signals may be muxed!
846 * Can the platform allow us to use this channel?
848 if (plchan->slave && pl08x->pd->get_signal) {
849 ret = pl08x->pd->get_signal(plchan);
851 dev_dbg(&pl08x->adev->dev,
852 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
853 ch->id, plchan->name);
854 /* Release physical channel & return */
855 pl08x_put_phy_channel(pl08x, ch);
860 /* Assign the flow control signal to this channel */
861 if (txd->direction == DMA_TO_DEVICE)
862 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
863 else if (txd->direction == DMA_FROM_DEVICE)
864 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
867 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
872 plchan->phychan_hold++;
873 plchan->phychan = ch;
878 static void release_phy_channel(struct pl08x_dma_chan *plchan)
880 struct pl08x_driver_data *pl08x = plchan->host;
882 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
883 pl08x->pd->put_signal(plchan);
884 plchan->phychan->signal = -1;
886 pl08x_put_phy_channel(pl08x, plchan->phychan);
887 plchan->phychan = NULL;
890 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
892 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
893 struct pl08x_txd *txd = to_pl08x_txd(tx);
896 spin_lock_irqsave(&plchan->lock, flags);
898 plchan->chan.cookie += 1;
899 if (plchan->chan.cookie < 0)
900 plchan->chan.cookie = 1;
901 tx->cookie = plchan->chan.cookie;
903 /* Put this onto the pending list */
904 list_add_tail(&txd->node, &plchan->pend_list);
907 * If there was no physical channel available for this memcpy,
908 * stack the request up and indicate that the channel is waiting
909 * for a free physical channel.
911 if (!plchan->slave && !plchan->phychan) {
912 /* Do this memcpy whenever there is a channel ready */
913 plchan->state = PL08X_CHAN_WAITING;
914 plchan->waiting = txd;
916 plchan->phychan_hold--;
919 spin_unlock_irqrestore(&plchan->lock, flags);
924 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
925 struct dma_chan *chan, unsigned long flags)
927 struct dma_async_tx_descriptor *retval = NULL;
933 * Code accessing dma_async_is_complete() in a tight loop may give problems.
934 * If slaves are relying on interrupts to signal completion this function
935 * must not be called with interrupts disabled.
937 static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
938 dma_cookie_t cookie, struct dma_tx_state *txstate)
940 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
941 dma_cookie_t last_used;
942 dma_cookie_t last_complete;
946 last_used = plchan->chan.cookie;
947 last_complete = plchan->lc;
949 ret = dma_async_is_complete(cookie, last_complete, last_used);
950 if (ret == DMA_SUCCESS) {
951 dma_set_tx_state(txstate, last_complete, last_used, 0);
956 * This cookie not complete yet
958 last_used = plchan->chan.cookie;
959 last_complete = plchan->lc;
961 /* Get number of bytes left in the active transactions and queue */
962 bytesleft = pl08x_getbytes_chan(plchan);
964 dma_set_tx_state(txstate, last_complete, last_used,
967 if (plchan->state == PL08X_CHAN_PAUSED)
970 /* Whether waiting or running, we're in progress */
971 return DMA_IN_PROGRESS;
974 /* PrimeCell DMA extension */
980 static const struct burst_table burst_sizes[] = {
983 .reg = PL080_BSIZE_256,
987 .reg = PL080_BSIZE_128,
991 .reg = PL080_BSIZE_64,
995 .reg = PL080_BSIZE_32,
999 .reg = PL080_BSIZE_16,
1003 .reg = PL080_BSIZE_8,
1007 .reg = PL080_BSIZE_4,
1011 .reg = PL080_BSIZE_1,
1016 * Given the source and destination available bus masks, select which
1017 * will be routed to each port. We try to have source and destination
1018 * on separate ports, but always respect the allowable settings.
1020 static u32 pl08x_select_bus(u8 src, u8 dst)
1024 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1025 cctl |= PL080_CONTROL_DST_AHB2;
1026 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1027 cctl |= PL080_CONTROL_SRC_AHB2;
1032 static u32 pl08x_cctl(u32 cctl)
1034 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1035 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1036 PL080_CONTROL_PROT_MASK);
1038 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1039 return cctl | PL080_CONTROL_PROT_SYS;
1042 static u32 pl08x_width(enum dma_slave_buswidth width)
1045 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1046 return PL080_WIDTH_8BIT;
1047 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1048 return PL080_WIDTH_16BIT;
1049 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1050 return PL080_WIDTH_32BIT;
1056 static u32 pl08x_burst(u32 maxburst)
1060 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1061 if (burst_sizes[i].burstwords <= maxburst)
1064 return burst_sizes[i].reg;
1067 static int dma_set_runtime_config(struct dma_chan *chan,
1068 struct dma_slave_config *config)
1070 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1071 struct pl08x_driver_data *pl08x = plchan->host;
1072 enum dma_slave_buswidth addr_width;
1073 u32 width, burst, maxburst;
1079 /* Transfer direction */
1080 plchan->runtime_direction = config->direction;
1081 if (config->direction == DMA_TO_DEVICE) {
1082 addr_width = config->dst_addr_width;
1083 maxburst = config->dst_maxburst;
1084 } else if (config->direction == DMA_FROM_DEVICE) {
1085 addr_width = config->src_addr_width;
1086 maxburst = config->src_maxburst;
1088 dev_err(&pl08x->adev->dev,
1089 "bad runtime_config: alien transfer direction\n");
1093 width = pl08x_width(addr_width);
1095 dev_err(&pl08x->adev->dev,
1096 "bad runtime_config: alien address width\n");
1100 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1101 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1104 * If this channel will only request single transfers, set this
1105 * down to ONE element. Also select one element if no maxburst
1108 if (plchan->cd->single)
1111 burst = pl08x_burst(maxburst);
1112 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1113 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1115 if (plchan->runtime_direction == DMA_FROM_DEVICE) {
1116 plchan->src_addr = config->src_addr;
1117 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1118 pl08x_select_bus(plchan->cd->periph_buses,
1121 plchan->dst_addr = config->dst_addr;
1122 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1123 pl08x_select_bus(pl08x->mem_buses,
1124 plchan->cd->periph_buses);
1127 dev_dbg(&pl08x->adev->dev,
1128 "configured channel %s (%s) for %s, data width %d, "
1129 "maxburst %d words, LE, CCTL=0x%08x\n",
1130 dma_chan_name(chan), plchan->name,
1131 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1140 * Slave transactions callback to the slave device to allow
1141 * synchronization of slave DMA signals with the DMAC enable
1143 static void pl08x_issue_pending(struct dma_chan *chan)
1145 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1146 unsigned long flags;
1148 spin_lock_irqsave(&plchan->lock, flags);
1149 /* Something is already active, or we're waiting for a channel... */
1150 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1151 spin_unlock_irqrestore(&plchan->lock, flags);
1155 /* Take the first element in the queue and execute it */
1156 if (!list_empty(&plchan->pend_list)) {
1157 struct pl08x_txd *next;
1159 next = list_first_entry(&plchan->pend_list,
1162 list_del(&next->node);
1163 plchan->state = PL08X_CHAN_RUNNING;
1165 pl08x_start_txd(plchan, next);
1168 spin_unlock_irqrestore(&plchan->lock, flags);
1171 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1172 struct pl08x_txd *txd)
1174 struct pl08x_driver_data *pl08x = plchan->host;
1175 unsigned long flags;
1178 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1180 spin_lock_irqsave(&plchan->lock, flags);
1181 pl08x_free_txd(pl08x, txd);
1182 spin_unlock_irqrestore(&plchan->lock, flags);
1186 spin_lock_irqsave(&plchan->lock, flags);
1189 * See if we already have a physical channel allocated,
1190 * else this is the time to try to get one.
1192 ret = prep_phy_channel(plchan, txd);
1195 * No physical channel was available.
1197 * memcpy transfers can be sorted out at submission time.
1199 * Slave transfers may have been denied due to platform
1200 * channel muxing restrictions. Since there is no guarantee
1201 * that this will ever be resolved, and the signal must be
1202 * acquired AFTER acquiring the physical channel, we will let
1203 * them be NACK:ed with -EBUSY here. The drivers can retry
1204 * the prep() call if they are eager on doing this using DMA.
1206 if (plchan->slave) {
1207 pl08x_free_txd_list(pl08x, plchan);
1208 pl08x_free_txd(pl08x, txd);
1209 spin_unlock_irqrestore(&plchan->lock, flags);
1214 * Else we're all set, paused and ready to roll, status
1215 * will switch to PL08X_CHAN_RUNNING when we call
1216 * issue_pending(). If there is something running on the
1217 * channel already we don't change its state.
1219 if (plchan->state == PL08X_CHAN_IDLE)
1220 plchan->state = PL08X_CHAN_PAUSED;
1222 spin_unlock_irqrestore(&plchan->lock, flags);
1227 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1228 unsigned long flags)
1230 struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
1233 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1234 txd->tx.flags = flags;
1235 txd->tx.tx_submit = pl08x_tx_submit;
1236 INIT_LIST_HEAD(&txd->node);
1238 /* Always enable error and terminal interrupts */
1239 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1240 PL080_CONFIG_TC_IRQ_MASK;
1246 * Initialize a descriptor to be used by memcpy submit
1248 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1249 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1250 size_t len, unsigned long flags)
1252 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1253 struct pl08x_driver_data *pl08x = plchan->host;
1254 struct pl08x_txd *txd;
1257 txd = pl08x_get_txd(plchan, flags);
1259 dev_err(&pl08x->adev->dev,
1260 "%s no memory for descriptor\n", __func__);
1264 txd->direction = DMA_NONE;
1265 txd->src_addr = src;
1266 txd->dst_addr = dest;
1269 /* Set platform data for m2m */
1270 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1271 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1272 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1274 /* Both to be incremented or the code will break */
1275 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1277 if (pl08x->vd->dualmaster)
1278 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1281 ret = pl08x_prep_channel_resources(plchan, txd);
1288 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1289 struct dma_chan *chan, struct scatterlist *sgl,
1290 unsigned int sg_len, enum dma_data_direction direction,
1291 unsigned long flags)
1293 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1294 struct pl08x_driver_data *pl08x = plchan->host;
1295 struct pl08x_txd *txd;
1299 * Current implementation ASSUMES only one sg
1302 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1307 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1308 __func__, sgl->length, plchan->name);
1310 txd = pl08x_get_txd(plchan, flags);
1312 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1316 if (direction != plchan->runtime_direction)
1317 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1318 "the direction configured for the PrimeCell\n",
1322 * Set up addresses, the PrimeCell configured address
1323 * will take precedence since this may configure the
1324 * channel target address dynamically at runtime.
1326 txd->direction = direction;
1327 txd->len = sgl->length;
1329 if (direction == DMA_TO_DEVICE) {
1330 txd->cctl = plchan->dst_cctl;
1331 txd->src_addr = sgl->dma_address;
1332 txd->dst_addr = plchan->dst_addr;
1333 } else if (direction == DMA_FROM_DEVICE) {
1334 txd->cctl = plchan->src_cctl;
1335 txd->src_addr = plchan->src_addr;
1336 txd->dst_addr = sgl->dma_address;
1338 dev_err(&pl08x->adev->dev,
1339 "%s direction unsupported\n", __func__);
1343 if (plchan->cd->device_fc)
1344 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER_PER :
1345 PL080_FLOW_PER2MEM_PER;
1347 tmp = (direction == DMA_TO_DEVICE) ? PL080_FLOW_MEM2PER :
1350 txd->ccfg |= tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1352 ret = pl08x_prep_channel_resources(plchan, txd);
1359 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1362 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1363 struct pl08x_driver_data *pl08x = plchan->host;
1364 unsigned long flags;
1367 /* Controls applicable to inactive channels */
1368 if (cmd == DMA_SLAVE_CONFIG) {
1369 return dma_set_runtime_config(chan,
1370 (struct dma_slave_config *)arg);
1374 * Anything succeeds on channels with no physical allocation and
1375 * no queued transfers.
1377 spin_lock_irqsave(&plchan->lock, flags);
1378 if (!plchan->phychan && !plchan->at) {
1379 spin_unlock_irqrestore(&plchan->lock, flags);
1384 case DMA_TERMINATE_ALL:
1385 plchan->state = PL08X_CHAN_IDLE;
1387 if (plchan->phychan) {
1388 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1391 * Mark physical channel as free and free any slave
1394 release_phy_channel(plchan);
1396 /* Dequeue jobs and free LLIs */
1398 pl08x_free_txd(pl08x, plchan->at);
1401 /* Dequeue jobs not yet fired as well */
1402 pl08x_free_txd_list(pl08x, plchan);
1405 pl08x_pause_phy_chan(plchan->phychan);
1406 plchan->state = PL08X_CHAN_PAUSED;
1409 pl08x_resume_phy_chan(plchan->phychan);
1410 plchan->state = PL08X_CHAN_RUNNING;
1413 /* Unknown command */
1418 spin_unlock_irqrestore(&plchan->lock, flags);
1423 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1425 struct pl08x_dma_chan *plchan;
1426 char *name = chan_id;
1428 /* Reject channels for devices not bound to this driver */
1429 if (chan->device->dev->driver != &pl08x_amba_driver.drv)
1432 plchan = to_pl08x_chan(chan);
1434 /* Check that the channel is not taken! */
1435 if (!strcmp(plchan->name, name))
1442 * Just check that the device is there and active
1443 * TODO: turn this bit on/off depending on the number of physical channels
1444 * actually used, if it is zero... well shut it off. That will save some
1445 * power. Cut the clock at the same time.
1447 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1449 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
1452 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1454 struct device *dev = txd->tx.chan->device->dev;
1456 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1457 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1458 dma_unmap_single(dev, txd->src_addr, txd->len,
1461 dma_unmap_page(dev, txd->src_addr, txd->len,
1464 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1465 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1466 dma_unmap_single(dev, txd->dst_addr, txd->len,
1469 dma_unmap_page(dev, txd->dst_addr, txd->len,
1474 static void pl08x_tasklet(unsigned long data)
1476 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1477 struct pl08x_driver_data *pl08x = plchan->host;
1478 struct pl08x_txd *txd;
1479 unsigned long flags;
1481 spin_lock_irqsave(&plchan->lock, flags);
1487 /* Update last completed */
1488 plchan->lc = txd->tx.cookie;
1491 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1492 if (!list_empty(&plchan->pend_list)) {
1493 struct pl08x_txd *next;
1495 next = list_first_entry(&plchan->pend_list,
1498 list_del(&next->node);
1500 pl08x_start_txd(plchan, next);
1501 } else if (plchan->phychan_hold) {
1503 * This channel is still in use - we have a new txd being
1504 * prepared and will soon be queued. Don't give up the
1508 struct pl08x_dma_chan *waiting = NULL;
1511 * No more jobs, so free up the physical channel
1512 * Free any allocated signal on slave transfers too
1514 release_phy_channel(plchan);
1515 plchan->state = PL08X_CHAN_IDLE;
1518 * And NOW before anyone else can grab that free:d up
1519 * physical channel, see if there is some memcpy pending
1520 * that seriously needs to start because of being stacked
1521 * up while we were choking the physical channels with data.
1523 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1525 if (waiting->state == PL08X_CHAN_WAITING &&
1526 waiting->waiting != NULL) {
1529 /* This should REALLY not fail now */
1530 ret = prep_phy_channel(waiting,
1533 waiting->phychan_hold--;
1534 waiting->state = PL08X_CHAN_RUNNING;
1535 waiting->waiting = NULL;
1536 pl08x_issue_pending(&waiting->chan);
1542 spin_unlock_irqrestore(&plchan->lock, flags);
1545 dma_async_tx_callback callback = txd->tx.callback;
1546 void *callback_param = txd->tx.callback_param;
1548 /* Don't try to unmap buffers on slave channels */
1550 pl08x_unmap_buffers(txd);
1552 /* Free the descriptor */
1553 spin_lock_irqsave(&plchan->lock, flags);
1554 pl08x_free_txd(pl08x, txd);
1555 spin_unlock_irqrestore(&plchan->lock, flags);
1557 /* Callback to signal completion */
1559 callback(callback_param);
1563 static irqreturn_t pl08x_irq(int irq, void *dev)
1565 struct pl08x_driver_data *pl08x = dev;
1566 u32 mask = 0, err, tc, i;
1568 /* check & clear - ERR & TC interrupts */
1569 err = readl(pl08x->base + PL080_ERR_STATUS);
1571 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
1573 writel(err, pl08x->base + PL080_ERR_CLEAR);
1575 tc = readl(pl08x->base + PL080_INT_STATUS);
1577 writel(tc, pl08x->base + PL080_TC_CLEAR);
1582 for (i = 0; i < pl08x->vd->channels; i++) {
1583 if (((1 << i) & err) || ((1 << i) & tc)) {
1584 /* Locate physical channel */
1585 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1586 struct pl08x_dma_chan *plchan = phychan->serving;
1589 dev_err(&pl08x->adev->dev,
1590 "%s Error TC interrupt on unused channel: 0x%08x\n",
1595 /* Schedule tasklet on this channel */
1596 tasklet_schedule(&plchan->tasklet);
1601 return mask ? IRQ_HANDLED : IRQ_NONE;
1604 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1606 u32 cctl = pl08x_cctl(chan->cd->cctl);
1609 chan->name = chan->cd->bus_id;
1610 chan->src_addr = chan->cd->addr;
1611 chan->dst_addr = chan->cd->addr;
1612 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1613 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1614 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1615 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1619 * Initialise the DMAC memcpy/slave channels.
1620 * Make a local wrapper to hold required data
1622 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1623 struct dma_device *dmadev, unsigned int channels, bool slave)
1625 struct pl08x_dma_chan *chan;
1628 INIT_LIST_HEAD(&dmadev->channels);
1631 * Register as many many memcpy as we have physical channels,
1632 * we won't always be able to use all but the code will have
1633 * to cope with that situation.
1635 for (i = 0; i < channels; i++) {
1636 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1638 dev_err(&pl08x->adev->dev,
1639 "%s no memory for channel\n", __func__);
1644 chan->state = PL08X_CHAN_IDLE;
1647 chan->cd = &pl08x->pd->slave_channels[i];
1648 pl08x_dma_slave_init(chan);
1650 chan->cd = &pl08x->pd->memcpy_channel;
1651 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1657 if (chan->cd->circular_buffer) {
1658 dev_err(&pl08x->adev->dev,
1659 "channel %s: circular buffers not supported\n",
1664 dev_dbg(&pl08x->adev->dev,
1665 "initialize virtual channel \"%s\"\n",
1668 chan->chan.device = dmadev;
1669 chan->chan.cookie = 0;
1672 spin_lock_init(&chan->lock);
1673 INIT_LIST_HEAD(&chan->pend_list);
1674 tasklet_init(&chan->tasklet, pl08x_tasklet,
1675 (unsigned long) chan);
1677 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1679 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1680 i, slave ? "slave" : "memcpy");
1684 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1686 struct pl08x_dma_chan *chan = NULL;
1687 struct pl08x_dma_chan *next;
1689 list_for_each_entry_safe(chan,
1690 next, &dmadev->channels, chan.device_node) {
1691 list_del(&chan->chan.device_node);
1696 #ifdef CONFIG_DEBUG_FS
1697 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1700 case PL08X_CHAN_IDLE:
1702 case PL08X_CHAN_RUNNING:
1704 case PL08X_CHAN_PAUSED:
1706 case PL08X_CHAN_WAITING:
1711 return "UNKNOWN STATE";
1714 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1716 struct pl08x_driver_data *pl08x = s->private;
1717 struct pl08x_dma_chan *chan;
1718 struct pl08x_phy_chan *ch;
1719 unsigned long flags;
1722 seq_printf(s, "PL08x physical channels:\n");
1723 seq_printf(s, "CHANNEL:\tUSER:\n");
1724 seq_printf(s, "--------\t-----\n");
1725 for (i = 0; i < pl08x->vd->channels; i++) {
1726 struct pl08x_dma_chan *virt_chan;
1728 ch = &pl08x->phy_chans[i];
1730 spin_lock_irqsave(&ch->lock, flags);
1731 virt_chan = ch->serving;
1733 seq_printf(s, "%d\t\t%s\n",
1734 ch->id, virt_chan ? virt_chan->name : "(none)");
1736 spin_unlock_irqrestore(&ch->lock, flags);
1739 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1740 seq_printf(s, "CHANNEL:\tSTATE:\n");
1741 seq_printf(s, "--------\t------\n");
1742 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1743 seq_printf(s, "%s\t\t%s\n", chan->name,
1744 pl08x_state_str(chan->state));
1747 seq_printf(s, "\nPL08x virtual slave channels:\n");
1748 seq_printf(s, "CHANNEL:\tSTATE:\n");
1749 seq_printf(s, "--------\t------\n");
1750 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1751 seq_printf(s, "%s\t\t%s\n", chan->name,
1752 pl08x_state_str(chan->state));
1758 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1760 return single_open(file, pl08x_debugfs_show, inode->i_private);
1763 static const struct file_operations pl08x_debugfs_operations = {
1764 .open = pl08x_debugfs_open,
1766 .llseek = seq_lseek,
1767 .release = single_release,
1770 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1772 /* Expose a simple debugfs interface to view all clocks */
1773 (void) debugfs_create_file(dev_name(&pl08x->adev->dev),
1774 S_IFREG | S_IRUGO, NULL, pl08x,
1775 &pl08x_debugfs_operations);
1779 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1784 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1786 struct pl08x_driver_data *pl08x;
1787 const struct vendor_data *vd = id->data;
1791 ret = amba_request_regions(adev, NULL);
1795 /* Create the driver state holder */
1796 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
1802 pm_runtime_set_active(&adev->dev);
1803 pm_runtime_enable(&adev->dev);
1805 /* Initialize memcpy engine */
1806 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1807 pl08x->memcpy.dev = &adev->dev;
1808 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1809 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1810 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1811 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1812 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1813 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1814 pl08x->memcpy.device_control = pl08x_control;
1816 /* Initialize slave engine */
1817 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1818 pl08x->slave.dev = &adev->dev;
1819 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1820 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1821 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1822 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1823 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1824 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1825 pl08x->slave.device_control = pl08x_control;
1827 /* Get the platform data */
1828 pl08x->pd = dev_get_platdata(&adev->dev);
1830 dev_err(&adev->dev, "no platform data supplied\n");
1831 goto out_no_platdata;
1834 /* Assign useful pointers to the driver state */
1838 /* By default, AHB1 only. If dualmaster, from platform */
1839 pl08x->lli_buses = PL08X_AHB1;
1840 pl08x->mem_buses = PL08X_AHB1;
1841 if (pl08x->vd->dualmaster) {
1842 pl08x->lli_buses = pl08x->pd->lli_buses;
1843 pl08x->mem_buses = pl08x->pd->mem_buses;
1846 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1847 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1848 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1851 goto out_no_lli_pool;
1854 spin_lock_init(&pl08x->lock);
1856 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1859 goto out_no_ioremap;
1862 /* Turn on the PL08x */
1863 pl08x_ensure_on(pl08x);
1865 /* Attach the interrupt handler */
1866 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1867 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1869 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1870 DRIVER_NAME, pl08x);
1872 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1873 __func__, adev->irq[0]);
1877 /* Initialize physical channels */
1878 pl08x->phy_chans = kmalloc((vd->channels * sizeof(*pl08x->phy_chans)),
1880 if (!pl08x->phy_chans) {
1881 dev_err(&adev->dev, "%s failed to allocate "
1882 "physical channel holders\n",
1884 goto out_no_phychans;
1887 for (i = 0; i < vd->channels; i++) {
1888 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1891 ch->base = pl08x->base + PL080_Cx_BASE(i);
1892 spin_lock_init(&ch->lock);
1895 dev_dbg(&adev->dev, "physical channel %d is %s\n",
1896 i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1899 /* Register as many memcpy channels as there are physical channels */
1900 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1901 pl08x->vd->channels, false);
1903 dev_warn(&pl08x->adev->dev,
1904 "%s failed to enumerate memcpy channels - %d\n",
1908 pl08x->memcpy.chancnt = ret;
1910 /* Register slave channels */
1911 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1912 pl08x->pd->num_slave_channels, true);
1914 dev_warn(&pl08x->adev->dev,
1915 "%s failed to enumerate slave channels - %d\n",
1919 pl08x->slave.chancnt = ret;
1921 ret = dma_async_device_register(&pl08x->memcpy);
1923 dev_warn(&pl08x->adev->dev,
1924 "%s failed to register memcpy as an async device - %d\n",
1926 goto out_no_memcpy_reg;
1929 ret = dma_async_device_register(&pl08x->slave);
1931 dev_warn(&pl08x->adev->dev,
1932 "%s failed to register slave as an async device - %d\n",
1934 goto out_no_slave_reg;
1937 amba_set_drvdata(adev, pl08x);
1938 init_pl08x_debugfs(pl08x);
1939 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1940 amba_part(adev), amba_rev(adev),
1941 (unsigned long long)adev->res.start, adev->irq[0]);
1943 pm_runtime_put(&adev->dev);
1947 dma_async_device_unregister(&pl08x->memcpy);
1949 pl08x_free_virtual_channels(&pl08x->slave);
1951 pl08x_free_virtual_channels(&pl08x->memcpy);
1953 kfree(pl08x->phy_chans);
1955 free_irq(adev->irq[0], pl08x);
1957 iounmap(pl08x->base);
1959 dma_pool_destroy(pl08x->pool);
1962 pm_runtime_put(&adev->dev);
1963 pm_runtime_disable(&adev->dev);
1967 amba_release_regions(adev);
1971 /* PL080 has 8 channels and the PL080 have just 2 */
1972 static struct vendor_data vendor_pl080 = {
1977 static struct vendor_data vendor_pl081 = {
1979 .dualmaster = false,
1982 static struct amba_id pl08x_ids[] = {
1987 .data = &vendor_pl080,
1993 .data = &vendor_pl081,
1995 /* Nomadik 8815 PL080 variant */
1999 .data = &vendor_pl080,
2004 static struct amba_driver pl08x_amba_driver = {
2005 .drv.name = DRIVER_NAME,
2006 .id_table = pl08x_ids,
2007 .probe = pl08x_probe,
2010 static int __init pl08x_init(void)
2013 retval = amba_driver_register(&pl08x_amba_driver);
2015 printk(KERN_WARNING DRIVER_NAME
2016 "failed to register as an AMBA device (%d)\n",
2020 subsys_initcall(pl08x_init);