Pileus Git - ~andy/linux/blob - drivers/crypto/talitos.c

   1 /*
   2  * talitos - Freescale Integrated Security Engine (SEC) device driver
   3  *
   4  * Copyright (c) 2008 Freescale Semiconductor, Inc.
   5  *
   6  * Scatterlist Crypto API glue code copied from files with the following:
   7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
   8  *
   9  * Crypto algorithm registration code copied from hifn driver:
  10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
  11  * All rights reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/device.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/crypto.h>
  34 #include <linux/hw_random.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/io.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/rtnetlink.h>
  40
  41 #include <crypto/algapi.h>
  42 #include <crypto/aes.h>
  43 #include <crypto/des.h>
  44 #include <crypto/sha.h>
  45 #include <crypto/aead.h>
  46 #include <crypto/authenc.h>
  47 #include <crypto/skcipher.h>
  48 #include <crypto/scatterwalk.h>
  49
  50 #include "talitos.h"
  51
  52 #define TALITOS_TIMEOUT 100000
  53 #define TALITOS_MAX_DATA_LEN 65535
  54
  55 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
  56 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
  57 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
  58
  59 /* descriptor pointer entry */
  60 struct talitos_ptr {
  61         __be16 len;     /* length */
  62         u8 j_extent;    /* jump to sg link table and/or extent */
  63         u8 eptr;        /* extended address */
  64         __be32 ptr;     /* address */
  65 };
  66
  67 /* descriptor */
  68 struct talitos_desc {
  69         __be32 hdr;                     /* header high bits */
  70         __be32 hdr_lo;                  /* header low bits */
  71         struct talitos_ptr ptr[7];      /* ptr/len pair array */
  72 };
  73
  74 /**
  75  * talitos_request - descriptor submission request
  76  * @desc: descriptor pointer (kernel virtual)
  77  * @dma_desc: descriptor's physical bus address
  78  * @callback: whom to call when descriptor processing is done
  79  * @context: caller context (optional)
  80  */
  81 struct talitos_request {
  82         struct talitos_desc *desc;
  83         dma_addr_t dma_desc;
  84         void (*callback) (struct device *dev, struct talitos_desc *desc,
  85                           void *context, int error);
  86         void *context;
  87 };
  88
  89 struct talitos_private {
  90         struct device *dev;
  91         struct of_device *ofdev;
  92         void __iomem *reg;
  93         int irq;
  94
  95         /* SEC version geometry (from device tree node) */
  96         unsigned int num_channels;
  97         unsigned int chfifo_len;
  98         unsigned int exec_units;
  99         unsigned int desc_types;
 100
 101         /* SEC Compatibility info */
 102         unsigned long features;
 103
 104         /* next channel to be assigned next incoming descriptor */
 105         atomic_t last_chan;
 106
 107         /* per-channel number of requests pending in channel h/w fifo */
 108         atomic_t *submit_count;
 109
 110         /* per-channel request fifo */
 111         struct talitos_request **fifo;
 112
 113         /*
 114          * length of the request fifo
 115          * fifo_len is chfifo_len rounded up to next power of 2
 116          * so we can use bitwise ops to wrap
 117          */
 118         unsigned int fifo_len;
 119
 120         /* per-channel index to next free descriptor request */
 121         int *head;
 122
 123         /* per-channel index to next in-progress/done descriptor request */
 124         int *tail;
 125
 126         /* per-channel request submission (head) and release (tail) locks */
 127         spinlock_t *head_lock;
 128         spinlock_t *tail_lock;
 129
 130         /* request callback tasklet */
 131         struct tasklet_struct done_task;
 132
 133         /* list of registered algorithms */
 134         struct list_head alg_list;
 135
 136         /* hwrng device */
 137         struct hwrng rng;
 138 };
 139
 140 /* .features flag */
 141 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
 142 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
 143
 144 /*
 145  * map virtual single (contiguous) pointer to h/w descriptor pointer
 146  */
 147 static void map_single_talitos_ptr(struct device *dev,
 148                                    struct talitos_ptr *talitos_ptr,
 149                                    unsigned short len, void *data,
 150                                    unsigned char extent,
 151                                    enum dma_data_direction dir)
 152 {
 153         talitos_ptr->len = cpu_to_be16(len);
 154         talitos_ptr->ptr = cpu_to_be32(dma_map_single(dev, data, len, dir));
 155         talitos_ptr->j_extent = extent;
 156 }
 157
 158 /*
 159  * unmap bus single (contiguous) h/w descriptor pointer
 160  */
 161 static void unmap_single_talitos_ptr(struct device *dev,
 162                                      struct talitos_ptr *talitos_ptr,
 163                                      enum dma_data_direction dir)
 164 {
 165         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
 166                          be16_to_cpu(talitos_ptr->len), dir);
 167 }
 168
 169 static int reset_channel(struct device *dev, int ch)
 170 {
 171         struct talitos_private *priv = dev_get_drvdata(dev);
 172         unsigned int timeout = TALITOS_TIMEOUT;
 173
 174         setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
 175
 176         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
 177                && --timeout)
 178                 cpu_relax();
 179
 180         if (timeout == 0) {
 181                 dev_err(dev, "failed to reset channel %d\n", ch);
 182                 return -EIO;
 183         }
 184
 185         /* set done writeback and IRQ */
 186         setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_CDWE |
 187                   TALITOS_CCCR_LO_CDIE);
 188
 189         /* and ICCR writeback, if available */
 190         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 191                 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
 192                           TALITOS_CCCR_LO_IWSE);
 193
 194         return 0;
 195 }
 196
 197 static int reset_device(struct device *dev)
 198 {
 199         struct talitos_private *priv = dev_get_drvdata(dev);
 200         unsigned int timeout = TALITOS_TIMEOUT;
 201
 202         setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
 203
 204         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
 205                && --timeout)
 206                 cpu_relax();
 207
 208         if (timeout == 0) {
 209                 dev_err(dev, "failed to reset device\n");
 210                 return -EIO;
 211         }
 212
 213         return 0;
 214 }
 215
 216 /*
 217  * Reset and initialize the device
 218  */
 219 static int init_device(struct device *dev)
 220 {
 221         struct talitos_private *priv = dev_get_drvdata(dev);
 222         int ch, err;
 223
 224         /*
 225          * Master reset
 226          * errata documentation: warning: certain SEC interrupts
 227          * are not fully cleared by writing the MCR:SWR bit,
 228          * set bit twice to completely reset
 229          */
 230         err = reset_device(dev);
 231         if (err)
 232                 return err;
 233
 234         err = reset_device(dev);
 235         if (err)
 236                 return err;
 237
 238         /* reset channels */
 239         for (ch = 0; ch < priv->num_channels; ch++) {
 240                 err = reset_channel(dev, ch);
 241                 if (err)
 242                         return err;
 243         }
 244
 245         /* enable channel done and error interrupts */
 246         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 247         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 248
 249         /* disable integrity check error interrupts (use writeback instead) */
 250         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
 251                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
 252                           TALITOS_MDEUICR_LO_ICE);
 253
 254         return 0;
 255 }
 256
 257 /**
 258  * talitos_submit - submits a descriptor to the device for processing
 259  * @dev:        the SEC device to be used
 260  * @desc:       the descriptor to be processed by the device
 261  * @callback:   whom to call when processing is complete
 262  * @context:    a handle for use by caller (optional)
 263  *
 264  * desc must contain valid dma-mapped (bus physical) address pointers.
 265  * callback must check err and feedback in descriptor header
 266  * for device processing status.
 267  */
 268 static int talitos_submit(struct device *dev, struct talitos_desc *desc,
 269                           void (*callback)(struct device *dev,
 270                                            struct talitos_desc *desc,
 271                                            void *context, int error),
 272                           void *context)
 273 {
 274         struct talitos_private *priv = dev_get_drvdata(dev);
 275         struct talitos_request *request;
 276         unsigned long flags, ch;
 277         int head;
 278
 279         /* select done notification */
 280         desc->hdr |= DESC_HDR_DONE_NOTIFY;
 281
 282         /* emulate SEC's round-robin channel fifo polling scheme */
 283         ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
 284
 285         spin_lock_irqsave(&priv->head_lock[ch], flags);
 286
 287         if (!atomic_inc_not_zero(&priv->submit_count[ch])) {
 288                 /* h/w fifo is full */
 289                 spin_unlock_irqrestore(&priv->head_lock[ch], flags);
 290                 return -EAGAIN;
 291         }
 292
 293         head = priv->head[ch];
 294         request = &priv->fifo[ch][head];
 295
 296         /* map descriptor and save caller data */
 297         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
 298                                            DMA_BIDIRECTIONAL);
 299         request->callback = callback;
 300         request->context = context;
 301
 302         /* increment fifo head */
 303         priv->head[ch] = (priv->head[ch] + 1) & (priv->fifo_len - 1);
 304
 305         smp_wmb();
 306         request->desc = desc;
 307
 308         /* GO! */
 309         wmb();
 310         out_be32(priv->reg + TALITOS_FF_LO(ch), request->dma_desc);
 311
 312         spin_unlock_irqrestore(&priv->head_lock[ch], flags);
 313
 314         return -EINPROGRESS;
 315 }
 316
 317 /*
 318  * process what was done, notify callback of error if not
 319  */
 320 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
 321 {
 322         struct talitos_private *priv = dev_get_drvdata(dev);
 323         struct talitos_request *request, saved_req;
 324         unsigned long flags;
 325         int tail, status;
 326
 327         spin_lock_irqsave(&priv->tail_lock[ch], flags);
 328
 329         tail = priv->tail[ch];
 330         while (priv->fifo[ch][tail].desc) {
 331                 request = &priv->fifo[ch][tail];
 332
 333                 /* descriptors with their done bits set don't get the error */
 334                 rmb();
 335                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
 336                         status = 0;
 337                 else
 338                         if (!error)
 339                                 break;
 340                         else
 341                                 status = error;
 342
 343                 dma_unmap_single(dev, request->dma_desc,
 344                                  sizeof(struct talitos_desc),
 345                                  DMA_BIDIRECTIONAL);
 346
 347                 /* copy entries so we can call callback outside lock */
 348                 saved_req.desc = request->desc;
 349                 saved_req.callback = request->callback;
 350                 saved_req.context = request->context;
 351
 352                 /* release request entry in fifo */
 353                 smp_wmb();
 354                 request->desc = NULL;
 355
 356                 /* increment fifo tail */
 357                 priv->tail[ch] = (tail + 1) & (priv->fifo_len - 1);
 358
 359                 spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
 360
 361                 atomic_dec(&priv->submit_count[ch]);
 362
 363                 saved_req.callback(dev, saved_req.desc, saved_req.context,
 364                                    status);
 365                 /* channel may resume processing in single desc error case */
 366                 if (error && !reset_ch && status == error)
 367                         return;
 368                 spin_lock_irqsave(&priv->tail_lock[ch], flags);
 369                 tail = priv->tail[ch];
 370         }
 371
 372         spin_unlock_irqrestore(&priv->tail_lock[ch], flags);
 373 }
 374
 375 /*
 376  * process completed requests for channels that have done status
 377  */
 378 static void talitos_done(unsigned long data)
 379 {
 380         struct device *dev = (struct device *)data;
 381         struct talitos_private *priv = dev_get_drvdata(dev);
 382         int ch;
 383
 384         for (ch = 0; ch < priv->num_channels; ch++)
 385                 flush_channel(dev, ch, 0, 0);
 386
 387         /* At this point, all completed channels have been processed.
 388          * Unmask done interrupts for channels completed later on.
 389          */
 390         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
 391         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
 392 }
 393
 394 /*
 395  * locate current (offending) descriptor
 396  */
 397 static struct talitos_desc *current_desc(struct device *dev, int ch)
 398 {
 399         struct talitos_private *priv = dev_get_drvdata(dev);
 400         int tail = priv->tail[ch];
 401         dma_addr_t cur_desc;
 402
 403         cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
 404
 405         while (priv->fifo[ch][tail].dma_desc != cur_desc) {
 406                 tail = (tail + 1) & (priv->fifo_len - 1);
 407                 if (tail == priv->tail[ch]) {
 408                         dev_err(dev, "couldn't locate current descriptor\n");
 409                         return NULL;
 410                 }
 411         }
 412
 413         return priv->fifo[ch][tail].desc;
 414 }
 415
 416 /*
 417  * user diagnostics; report root cause of error based on execution unit status
 418  */
 419 static void report_eu_error(struct device *dev, int ch,
 420                             struct talitos_desc *desc)
 421 {
 422         struct talitos_private *priv = dev_get_drvdata(dev);
 423         int i;
 424
 425         switch (desc->hdr & DESC_HDR_SEL0_MASK) {
 426         case DESC_HDR_SEL0_AFEU:
 427                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
 428                         in_be32(priv->reg + TALITOS_AFEUISR),
 429                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
 430                 break;
 431         case DESC_HDR_SEL0_DEU:
 432                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
 433                         in_be32(priv->reg + TALITOS_DEUISR),
 434                         in_be32(priv->reg + TALITOS_DEUISR_LO));
 435                 break;
 436         case DESC_HDR_SEL0_MDEUA:
 437         case DESC_HDR_SEL0_MDEUB:
 438                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 439                         in_be32(priv->reg + TALITOS_MDEUISR),
 440                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 441                 break;
 442         case DESC_HDR_SEL0_RNG:
 443                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
 444                         in_be32(priv->reg + TALITOS_RNGUISR),
 445                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
 446                 break;
 447         case DESC_HDR_SEL0_PKEU:
 448                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
 449                         in_be32(priv->reg + TALITOS_PKEUISR),
 450                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
 451                 break;
 452         case DESC_HDR_SEL0_AESU:
 453                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
 454                         in_be32(priv->reg + TALITOS_AESUISR),
 455                         in_be32(priv->reg + TALITOS_AESUISR_LO));
 456                 break;
 457         case DESC_HDR_SEL0_CRCU:
 458                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 459                         in_be32(priv->reg + TALITOS_CRCUISR),
 460                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 461                 break;
 462         case DESC_HDR_SEL0_KEU:
 463                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
 464                         in_be32(priv->reg + TALITOS_KEUISR),
 465                         in_be32(priv->reg + TALITOS_KEUISR_LO));
 466                 break;
 467         }
 468
 469         switch (desc->hdr & DESC_HDR_SEL1_MASK) {
 470         case DESC_HDR_SEL1_MDEUA:
 471         case DESC_HDR_SEL1_MDEUB:
 472                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
 473                         in_be32(priv->reg + TALITOS_MDEUISR),
 474                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
 475                 break;
 476         case DESC_HDR_SEL1_CRCU:
 477                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
 478                         in_be32(priv->reg + TALITOS_CRCUISR),
 479                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
 480                 break;
 481         }
 482
 483         for (i = 0; i < 8; i++)
 484                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
 485                         in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
 486                         in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
 487 }
 488
 489 /*
 490  * recover from error interrupts
 491  */
 492 static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
 493 {
 494         struct device *dev = (struct device *)data;
 495         struct talitos_private *priv = dev_get_drvdata(dev);
 496         unsigned int timeout = TALITOS_TIMEOUT;
 497         int ch, error, reset_dev = 0, reset_ch = 0;
 498         u32 v, v_lo;
 499
 500         for (ch = 0; ch < priv->num_channels; ch++) {
 501                 /* skip channels without errors */
 502                 if (!(isr & (1 << (ch * 2 + 1))))
 503                         continue;
 504
 505                 error = -EINVAL;
 506
 507                 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
 508                 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
 509
 510                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
 511                         dev_err(dev, "double fetch fifo overflow error\n");
 512                         error = -EAGAIN;
 513                         reset_ch = 1;
 514                 }
 515                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
 516                         /* h/w dropped descriptor */
 517                         dev_err(dev, "single fetch fifo overflow error\n");
 518                         error = -EAGAIN;
 519                 }
 520                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
 521                         dev_err(dev, "master data transfer error\n");
 522                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
 523                         dev_err(dev, "s/g data length zero error\n");
 524                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
 525                         dev_err(dev, "fetch pointer zero error\n");
 526                 if (v_lo & TALITOS_CCPSR_LO_IDH)
 527                         dev_err(dev, "illegal descriptor header error\n");
 528                 if (v_lo & TALITOS_CCPSR_LO_IEU)
 529                         dev_err(dev, "invalid execution unit error\n");
 530                 if (v_lo & TALITOS_CCPSR_LO_EU)
 531                         report_eu_error(dev, ch, current_desc(dev, ch));
 532                 if (v_lo & TALITOS_CCPSR_LO_GB)
 533                         dev_err(dev, "gather boundary error\n");
 534                 if (v_lo & TALITOS_CCPSR_LO_GRL)
 535                         dev_err(dev, "gather return/length error\n");
 536                 if (v_lo & TALITOS_CCPSR_LO_SB)
 537                         dev_err(dev, "scatter boundary error\n");
 538                 if (v_lo & TALITOS_CCPSR_LO_SRL)
 539                         dev_err(dev, "scatter return/length error\n");
 540
 541                 flush_channel(dev, ch, error, reset_ch);
 542
 543                 if (reset_ch) {
 544                         reset_channel(dev, ch);
 545                 } else {
 546                         setbits32(priv->reg + TALITOS_CCCR(ch),
 547                                   TALITOS_CCCR_CONT);
 548                         setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
 549                         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
 550                                TALITOS_CCCR_CONT) && --timeout)
 551                                 cpu_relax();
 552                         if (timeout == 0) {
 553                                 dev_err(dev, "failed to restart channel %d\n",
 554                                         ch);
 555                                 reset_dev = 1;
 556                         }
 557                 }
 558         }
 559         if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
 560                 dev_err(dev, "done overflow, internal time out, or rngu error: "
 561                         "ISR 0x%08x_%08x\n", isr, isr_lo);
 562
 563                 /* purge request queues */
 564                 for (ch = 0; ch < priv->num_channels; ch++)
 565                         flush_channel(dev, ch, -EIO, 1);
 566
 567                 /* reset and reinitialize the device */
 568                 init_device(dev);
 569         }
 570 }
 571
 572 static irqreturn_t talitos_interrupt(int irq, void *data)
 573 {
 574         struct device *dev = data;
 575         struct talitos_private *priv = dev_get_drvdata(dev);
 576         u32 isr, isr_lo;
 577
 578         isr = in_be32(priv->reg + TALITOS_ISR);
 579         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
 580         /* Acknowledge interrupt */
 581         out_be32(priv->reg + TALITOS_ICR, isr);
 582         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
 583
 584         if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
 585                 talitos_error((unsigned long)data, isr, isr_lo);
 586         else
 587                 if (likely(isr & TALITOS_ISR_CHDONE)) {
 588                         /* mask further done interrupts. */
 589                         clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
 590                         /* done_task will unmask done interrupts at exit */
 591                         tasklet_schedule(&priv->done_task);
 592                 }
 593
 594         return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
 595 }
 596
 597 /*
 598  * hwrng
 599  */
 600 static int talitos_rng_data_present(struct hwrng *rng, int wait)
 601 {
 602         struct device *dev = (struct device *)rng->priv;
 603         struct talitos_private *priv = dev_get_drvdata(dev);
 604         u32 ofl;
 605         int i;
 606
 607         for (i = 0; i < 20; i++) {
 608                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
 609                       TALITOS_RNGUSR_LO_OFL;
 610                 if (ofl || !wait)
 611                         break;
 612                 udelay(10);
 613         }
 614
 615         return !!ofl;
 616 }
 617
 618 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
 619 {
 620         struct device *dev = (struct device *)rng->priv;
 621         struct talitos_private *priv = dev_get_drvdata(dev);
 622
 623         /* rng fifo requires 64-bit accesses */
 624         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
 625         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
 626
 627         return sizeof(u32);
 628 }
 629
 630 static int talitos_rng_init(struct hwrng *rng)
 631 {
 632         struct device *dev = (struct device *)rng->priv;
 633         struct talitos_private *priv = dev_get_drvdata(dev);
 634         unsigned int timeout = TALITOS_TIMEOUT;
 635
 636         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
 637         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
 638                && --timeout)
 639                 cpu_relax();
 640         if (timeout == 0) {
 641                 dev_err(dev, "failed to reset rng hw\n");
 642                 return -ENODEV;
 643         }
 644
 645         /* start generating */
 646         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
 647
 648         return 0;
 649 }
 650
 651 static int talitos_register_rng(struct device *dev)
 652 {
 653         struct talitos_private *priv = dev_get_drvdata(dev);
 654
 655         priv->rng.name          = dev_driver_string(dev),
 656         priv->rng.init          = talitos_rng_init,
 657         priv->rng.data_present  = talitos_rng_data_present,
 658         priv->rng.data_read     = talitos_rng_data_read,
 659         priv->rng.priv          = (unsigned long)dev;
 660
 661         return hwrng_register(&priv->rng);
 662 }
 663
 664 static void talitos_unregister_rng(struct device *dev)
 665 {
 666         struct talitos_private *priv = dev_get_drvdata(dev);
 667
 668         hwrng_unregister(&priv->rng);
 669 }
 670
 671 /*
 672  * crypto alg
 673  */
 674 #define TALITOS_CRA_PRIORITY            3000
 675 #define TALITOS_MAX_KEY_SIZE            64
 676 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
 677
 678 #define MD5_DIGEST_SIZE   16
 679
 680 struct talitos_ctx {
 681         struct device *dev;
 682         __be32 desc_hdr_template;
 683         u8 key[TALITOS_MAX_KEY_SIZE];
 684         u8 iv[TALITOS_MAX_IV_LENGTH];
 685         unsigned int keylen;
 686         unsigned int enckeylen;
 687         unsigned int authkeylen;
 688         unsigned int authsize;
 689 };
 690
 691 static int aead_setauthsize(struct crypto_aead *authenc,
 692                             unsigned int authsize)
 693 {
 694         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 695
 696         ctx->authsize = authsize;
 697
 698         return 0;
 699 }
 700
 701 static int aead_setkey(struct crypto_aead *authenc,
 702                        const u8 *key, unsigned int keylen)
 703 {
 704         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 705         struct rtattr *rta = (void *)key;
 706         struct crypto_authenc_key_param *param;
 707         unsigned int authkeylen;
 708         unsigned int enckeylen;
 709
 710         if (!RTA_OK(rta, keylen))
 711                 goto badkey;
 712
 713         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
 714                 goto badkey;
 715
 716         if (RTA_PAYLOAD(rta) < sizeof(*param))
 717                 goto badkey;
 718
 719         param = RTA_DATA(rta);
 720         enckeylen = be32_to_cpu(param->enckeylen);
 721
 722         key += RTA_ALIGN(rta->rta_len);
 723         keylen -= RTA_ALIGN(rta->rta_len);
 724
 725         if (keylen < enckeylen)
 726                 goto badkey;
 727
 728         authkeylen = keylen - enckeylen;
 729
 730         if (keylen > TALITOS_MAX_KEY_SIZE)
 731                 goto badkey;
 732
 733         memcpy(&ctx->key, key, keylen);
 734
 735         ctx->keylen = keylen;
 736         ctx->enckeylen = enckeylen;
 737         ctx->authkeylen = authkeylen;
 738
 739         return 0;
 740
 741 badkey:
 742         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
 743         return -EINVAL;
 744 }
 745
 746 /*
 747  * talitos_edesc - s/w-extended descriptor
 748  * @src_nents: number of segments in input scatterlist
 749  * @dst_nents: number of segments in output scatterlist
 750  * @dma_len: length of dma mapped link_tbl space
 751  * @dma_link_tbl: bus physical address of link_tbl
 752  * @desc: h/w descriptor
 753  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
 754  *
 755  * if decrypting (with authcheck), or either one of src_nents or dst_nents
 756  * is greater than 1, an integrity check value is concatenated to the end
 757  * of link_tbl data
 758  */
 759 struct talitos_edesc {
 760         int src_nents;
 761         int dst_nents;
 762         int src_is_chained;
 763         int dst_is_chained;
 764         int dma_len;
 765         dma_addr_t dma_link_tbl;
 766         struct talitos_desc desc;
 767         struct talitos_ptr link_tbl[0];
 768 };
 769
 770 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
 771                           unsigned int nents, enum dma_data_direction dir,
 772                           int chained)
 773 {
 774         if (unlikely(chained))
 775                 while (sg) {
 776                         dma_map_sg(dev, sg, 1, dir);
 777                         sg = scatterwalk_sg_next(sg);
 778                 }
 779         else
 780                 dma_map_sg(dev, sg, nents, dir);
 781         return nents;
 782 }
 783
 784 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
 785                                    enum dma_data_direction dir)
 786 {
 787         while (sg) {
 788                 dma_unmap_sg(dev, sg, 1, dir);
 789                 sg = scatterwalk_sg_next(sg);
 790         }
 791 }
 792
 793 static void talitos_sg_unmap(struct device *dev,
 794                              struct talitos_edesc *edesc,
 795                              struct scatterlist *src,
 796                              struct scatterlist *dst)
 797 {
 798         unsigned int src_nents = edesc->src_nents ? : 1;
 799         unsigned int dst_nents = edesc->dst_nents ? : 1;
 800
 801         if (src != dst) {
 802                 if (edesc->src_is_chained)
 803                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
 804                 else
 805                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
 806
 807                 if (edesc->dst_is_chained)
 808                         talitos_unmap_sg_chain(dev, dst, DMA_FROM_DEVICE);
 809                 else
 810                         dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
 811         } else
 812                 if (edesc->src_is_chained)
 813                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
 814                 else
 815                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
 816 }
 817
 818 static void ipsec_esp_unmap(struct device *dev,
 819                             struct talitos_edesc *edesc,
 820                             struct aead_request *areq)
 821 {
 822         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
 823         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
 824         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
 825         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
 826
 827         dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
 828
 829         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
 830
 831         if (edesc->dma_len)
 832                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
 833                                  DMA_BIDIRECTIONAL);
 834 }
 835
 836 /*
 837  * ipsec_esp descriptor callbacks
 838  */
 839 static void ipsec_esp_encrypt_done(struct device *dev,
 840                                    struct talitos_desc *desc, void *context,
 841                                    int err)
 842 {
 843         struct aead_request *areq = context;
 844         struct talitos_edesc *edesc =
 845                  container_of(desc, struct talitos_edesc, desc);
 846         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
 847         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 848         struct scatterlist *sg;
 849         void *icvdata;
 850
 851         ipsec_esp_unmap(dev, edesc, areq);
 852
 853         /* copy the generated ICV to dst */
 854         if (edesc->dma_len) {
 855                 icvdata = &edesc->link_tbl[edesc->src_nents +
 856                                            edesc->dst_nents + 2];
 857                 sg = sg_last(areq->dst, edesc->dst_nents);
 858                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
 859                        icvdata, ctx->authsize);
 860         }
 861
 862         kfree(edesc);
 863
 864         aead_request_complete(areq, err);
 865 }
 866
 867 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
 868                                           struct talitos_desc *desc,
 869                                           void *context, int err)
 870 {
 871         struct aead_request *req = context;
 872         struct talitos_edesc *edesc =
 873                  container_of(desc, struct talitos_edesc, desc);
 874         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
 875         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
 876         struct scatterlist *sg;
 877         void *icvdata;
 878
 879         ipsec_esp_unmap(dev, edesc, req);
 880
 881         if (!err) {
 882                 /* auth check */
 883                 if (edesc->dma_len)
 884                         icvdata = &edesc->link_tbl[edesc->src_nents +
 885                                                    edesc->dst_nents + 2];
 886                 else
 887                         icvdata = &edesc->link_tbl[0];
 888
 889                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
 890                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
 891                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
 892         }
 893
 894         kfree(edesc);
 895
 896         aead_request_complete(req, err);
 897 }
 898
 899 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
 900                                           struct talitos_desc *desc,
 901                                           void *context, int err)
 902 {
 903         struct aead_request *req = context;
 904         struct talitos_edesc *edesc =
 905                  container_of(desc, struct talitos_edesc, desc);
 906
 907         ipsec_esp_unmap(dev, edesc, req);
 908
 909         /* check ICV auth status */
 910         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
 911                      DESC_HDR_LO_ICCR1_PASS))
 912                 err = -EBADMSG;
 913
 914         kfree(edesc);
 915
 916         aead_request_complete(req, err);
 917 }
 918
 919 /*
 920  * convert scatterlist to SEC h/w link table format
 921  * stop at cryptlen bytes
 922  */
 923 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
 924                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
 925 {
 926         int n_sg = sg_count;
 927
 928         while (n_sg--) {
 929                 link_tbl_ptr->ptr = cpu_to_be32(sg_dma_address(sg));
 930                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
 931                 link_tbl_ptr->j_extent = 0;
 932                 link_tbl_ptr++;
 933                 cryptlen -= sg_dma_len(sg);
 934                 sg = scatterwalk_sg_next(sg);
 935         }
 936
 937         /* adjust (decrease) last one (or two) entry's len to cryptlen */
 938         link_tbl_ptr--;
 939         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
 940                 /* Empty this entry, and move to previous one */
 941                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
 942                 link_tbl_ptr->len = 0;
 943                 sg_count--;
 944                 link_tbl_ptr--;
 945         }
 946         link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
 947                                         + cryptlen);
 948
 949         /* tag end of link table */
 950         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
 951
 952         return sg_count;
 953 }
 954
 955 /*
 956  * fill in and submit ipsec_esp descriptor
 957  */
 958 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
 959                      u8 *giv, u64 seq,
 960                      void (*callback) (struct device *dev,
 961                                        struct talitos_desc *desc,
 962                                        void *context, int error))
 963 {
 964         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
 965         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
 966         struct device *dev = ctx->dev;
 967         struct talitos_desc *desc = &edesc->desc;
 968         unsigned int cryptlen = areq->cryptlen;
 969         unsigned int authsize = ctx->authsize;
 970         unsigned int ivsize;
 971         int sg_count, ret;
 972         int sg_link_tbl_len;
 973
 974         /* hmac key */
 975         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
 976                                0, DMA_TO_DEVICE);
 977         /* hmac data */
 978         map_single_talitos_ptr(dev, &desc->ptr[1], sg_virt(areq->src) -
 979                                sg_virt(areq->assoc), sg_virt(areq->assoc), 0,
 980                                DMA_TO_DEVICE);
 981         /* cipher iv */
 982         ivsize = crypto_aead_ivsize(aead);
 983         map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
 984                                DMA_TO_DEVICE);
 985
 986         /* cipher key */
 987         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
 988                                (char *)&ctx->key + ctx->authkeylen, 0,
 989                                DMA_TO_DEVICE);
 990
 991         /*
 992          * cipher in
 993          * map and adjust cipher len to aead request cryptlen.
 994          * extent is bytes of HMAC postpended to ciphertext,
 995          * typically 12 for ipsec
 996          */
 997         desc->ptr[4].len = cpu_to_be16(cryptlen);
 998         desc->ptr[4].j_extent = authsize;
 999
1000         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1001                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1002                                                            : DMA_TO_DEVICE,
1003                                   edesc->src_is_chained);
1004
1005         if (sg_count == 1) {
1006                 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
1007         } else {
1008                 sg_link_tbl_len = cryptlen;
1009
1010                 if ((edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV) &&
1011                         (edesc->desc.hdr & DESC_HDR_MODE0_ENCRYPT) == 0)
1012                         sg_link_tbl_len = cryptlen + authsize;
1013
1014                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1015                                           &edesc->link_tbl[0]);
1016                 if (sg_count > 1) {
1017                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1018                         desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
1019                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1020                                                    edesc->dma_len,
1021                                                    DMA_BIDIRECTIONAL);
1022                 } else {
1023                         /* Only one segment now, so no link tbl needed */
1024                         desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->
1025                                                                       src));
1026                 }
1027         }
1028
1029         /* cipher out */
1030         desc->ptr[5].len = cpu_to_be16(cryptlen);
1031         desc->ptr[5].j_extent = authsize;
1032
1033         if (areq->src != areq->dst)
1034                 sg_count = talitos_map_sg(dev, areq->dst,
1035                                           edesc->dst_nents ? : 1,
1036                                           DMA_FROM_DEVICE,
1037                                           edesc->dst_is_chained);
1038
1039         if (sg_count == 1) {
1040                 desc->ptr[5].ptr = cpu_to_be32(sg_dma_address(areq->dst));
1041         } else {
1042                 struct talitos_ptr *link_tbl_ptr =
1043                         &edesc->link_tbl[edesc->src_nents + 1];
1044
1045                 desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
1046                                                edesc->dma_link_tbl +
1047                                                edesc->src_nents + 1);
1048                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1049                                           link_tbl_ptr);
1050
1051                 /* Add an entry to the link table for ICV data */
1052                 link_tbl_ptr += sg_count - 1;
1053                 link_tbl_ptr->j_extent = 0;
1054                 sg_count++;
1055                 link_tbl_ptr++;
1056                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1057                 link_tbl_ptr->len = cpu_to_be16(authsize);
1058
1059                 /* icv data follows link tables */
1060                 link_tbl_ptr->ptr = cpu_to_be32((struct talitos_ptr *)
1061                                                 edesc->dma_link_tbl +
1062                                                 edesc->src_nents +
1063                                                 edesc->dst_nents + 2);
1064
1065                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1066                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1067                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1068         }
1069
1070         /* iv out */
1071         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1072                                DMA_FROM_DEVICE);
1073
1074         ret = talitos_submit(dev, desc, callback, areq);
1075         if (ret != -EINPROGRESS) {
1076                 ipsec_esp_unmap(dev, edesc, areq);
1077                 kfree(edesc);
1078         }
1079         return ret;
1080 }
1081
1082 /*
1083  * derive number of elements in scatterlist
1084  */
1085 static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
1086 {
1087         struct scatterlist *sg = sg_list;
1088         int sg_nents = 0;
1089
1090         *chained = 0;
1091         while (nbytes > 0) {
1092                 sg_nents++;
1093                 nbytes -= sg->length;
1094                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1095                         *chained = 1;
1096                 sg = scatterwalk_sg_next(sg);
1097         }
1098
1099         return sg_nents;
1100 }
1101
1102 /*
1103  * allocate and map the extended descriptor
1104  */
1105 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1106                                                  struct scatterlist *src,
1107                                                  struct scatterlist *dst,
1108                                                  unsigned int cryptlen,
1109                                                  unsigned int authsize,
1110                                                  int icv_stashing,
1111                                                  u32 cryptoflags)
1112 {
1113         struct talitos_edesc *edesc;
1114         int src_nents, dst_nents, alloc_len, dma_len;
1115         int src_chained, dst_chained = 0;
1116         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1117                       GFP_ATOMIC;
1118
1119         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1120                 dev_err(dev, "length exceeds h/w max limit\n");
1121                 return ERR_PTR(-EINVAL);
1122         }
1123
1124         src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1125         src_nents = (src_nents == 1) ? 0 : src_nents;
1126
1127         if (dst == src) {
1128                 dst_nents = src_nents;
1129         } else {
1130                 dst_nents = sg_count(dst, cryptlen + authsize, &dst_chained);
1131                 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1132         }
1133
1134         /*
1135          * allocate space for base edesc plus the link tables,
1136          * allowing for two separate entries for ICV and generated ICV (+ 2),
1137          * and the ICV data itself
1138          */
1139         alloc_len = sizeof(struct talitos_edesc);
1140         if (src_nents || dst_nents) {
1141                 dma_len = (src_nents + dst_nents + 2) *
1142                                  sizeof(struct talitos_ptr) + authsize;
1143                 alloc_len += dma_len;
1144         } else {
1145                 dma_len = 0;
1146                 alloc_len += icv_stashing ? authsize : 0;
1147         }
1148
1149         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1150         if (!edesc) {
1151                 dev_err(dev, "could not allocate edescriptor\n");
1152                 return ERR_PTR(-ENOMEM);
1153         }
1154
1155         edesc->src_nents = src_nents;
1156         edesc->dst_nents = dst_nents;
1157         edesc->src_is_chained = src_chained;
1158         edesc->dst_is_chained = dst_chained;
1159         edesc->dma_len = dma_len;
1160         edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1161                                              edesc->dma_len, DMA_BIDIRECTIONAL);
1162
1163         return edesc;
1164 }
1165
1166 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1167                                               int icv_stashing)
1168 {
1169         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1170         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1171
1172         return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
1173                                    areq->cryptlen, ctx->authsize, icv_stashing,
1174                                    areq->base.flags);
1175 }
1176
1177 static int aead_encrypt(struct aead_request *req)
1178 {
1179         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1180         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1181         struct talitos_edesc *edesc;
1182
1183         /* allocate extended descriptor */
1184         edesc = aead_edesc_alloc(req, 0);
1185         if (IS_ERR(edesc))
1186                 return PTR_ERR(edesc);
1187
1188         /* set encrypt */
1189         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1190
1191         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1192 }
1193
1194 static int aead_decrypt(struct aead_request *req)
1195 {
1196         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1197         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1198         unsigned int authsize = ctx->authsize;
1199         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1200         struct talitos_edesc *edesc;
1201         struct scatterlist *sg;
1202         void *icvdata;
1203
1204         req->cryptlen -= authsize;
1205
1206         /* allocate extended descriptor */
1207         edesc = aead_edesc_alloc(req, 1);
1208         if (IS_ERR(edesc))
1209                 return PTR_ERR(edesc);
1210
1211         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1212             ((!edesc->src_nents && !edesc->dst_nents) ||
1213              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1214
1215                 /* decrypt and check the ICV */
1216                 edesc->desc.hdr = ctx->desc_hdr_template |
1217                                   DESC_HDR_DIR_INBOUND |
1218                                   DESC_HDR_MODE1_MDEU_CICV;
1219
1220                 /* reset integrity check result bits */
1221                 edesc->desc.hdr_lo = 0;
1222
1223                 return ipsec_esp(edesc, req, NULL, 0,
1224                                  ipsec_esp_decrypt_hwauth_done);
1225
1226         }
1227
1228         /* Have to check the ICV with software */
1229         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1230
1231         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1232         if (edesc->dma_len)
1233                 icvdata = &edesc->link_tbl[edesc->src_nents +
1234                                            edesc->dst_nents + 2];
1235         else
1236                 icvdata = &edesc->link_tbl[0];
1237
1238         sg = sg_last(req->src, edesc->src_nents ? : 1);
1239
1240         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1241                ctx->authsize);
1242
1243         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
1244 }
1245
1246 static int aead_givencrypt(struct aead_givcrypt_request *req)
1247 {
1248         struct aead_request *areq = &req->areq;
1249         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1250         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1251         struct talitos_edesc *edesc;
1252
1253         /* allocate extended descriptor */
1254         edesc = aead_edesc_alloc(areq, 0);
1255         if (IS_ERR(edesc))
1256                 return PTR_ERR(edesc);
1257
1258         /* set encrypt */
1259         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1260
1261         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1262         /* avoid consecutive packets going out with same IV */
1263         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1264
1265         return ipsec_esp(edesc, areq, req->giv, req->seq,
1266                          ipsec_esp_encrypt_done);
1267 }
1268
1269 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1270                              const u8 *key, unsigned int keylen)
1271 {
1272         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1273         struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
1274
1275         if (keylen > TALITOS_MAX_KEY_SIZE)
1276                 goto badkey;
1277
1278         if (keylen < alg->min_keysize || keylen > alg->max_keysize)
1279                 goto badkey;
1280
1281         memcpy(&ctx->key, key, keylen);
1282         ctx->keylen = keylen;
1283
1284         return 0;
1285
1286 badkey:
1287         crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1288         return -EINVAL;
1289 }
1290
1291 static void common_nonsnoop_unmap(struct device *dev,
1292                                   struct talitos_edesc *edesc,
1293                                   struct ablkcipher_request *areq)
1294 {
1295         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1296         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1297         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1298
1299         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1300
1301         if (edesc->dma_len)
1302                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1303                                  DMA_BIDIRECTIONAL);
1304 }
1305
1306 static void ablkcipher_done(struct device *dev,
1307                             struct talitos_desc *desc, void *context,
1308                             int err)
1309 {
1310         struct ablkcipher_request *areq = context;
1311         struct talitos_edesc *edesc =
1312                  container_of(desc, struct talitos_edesc, desc);
1313
1314         common_nonsnoop_unmap(dev, edesc, areq);
1315
1316         kfree(edesc);
1317
1318         areq->base.complete(&areq->base, err);
1319 }
1320
1321 static int common_nonsnoop(struct talitos_edesc *edesc,
1322                            struct ablkcipher_request *areq,
1323                            u8 *giv,
1324                            void (*callback) (struct device *dev,
1325                                              struct talitos_desc *desc,
1326                                              void *context, int error))
1327 {
1328         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1329         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1330         struct device *dev = ctx->dev;
1331         struct talitos_desc *desc = &edesc->desc;
1332         unsigned int cryptlen = areq->nbytes;
1333         unsigned int ivsize;
1334         int sg_count, ret;
1335
1336         /* first DWORD empty */
1337         desc->ptr[0].len = 0;
1338         desc->ptr[0].ptr = 0;
1339         desc->ptr[0].j_extent = 0;
1340
1341         /* cipher iv */
1342         ivsize = crypto_ablkcipher_ivsize(cipher);
1343         map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
1344                                DMA_TO_DEVICE);
1345
1346         /* cipher key */
1347         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1348                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1349
1350         /*
1351          * cipher in
1352          */
1353         desc->ptr[3].len = cpu_to_be16(cryptlen);
1354         desc->ptr[3].j_extent = 0;
1355
1356         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1357                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1358                                                            : DMA_TO_DEVICE,
1359                                   edesc->src_is_chained);
1360
1361         if (sg_count == 1) {
1362                 desc->ptr[3].ptr = cpu_to_be32(sg_dma_address(areq->src));
1363         } else {
1364                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1365                                           &edesc->link_tbl[0]);
1366                 if (sg_count > 1) {
1367                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1368                         desc->ptr[3].ptr = cpu_to_be32(edesc->dma_link_tbl);
1369                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1370                                                    edesc->dma_len,
1371                                                    DMA_BIDIRECTIONAL);
1372                 } else {
1373                         /* Only one segment now, so no link tbl needed */
1374                         desc->ptr[3].ptr = cpu_to_be32(sg_dma_address(areq->
1375                                                                       src));
1376                 }
1377         }
1378
1379         /* cipher out */
1380         desc->ptr[4].len = cpu_to_be16(cryptlen);
1381         desc->ptr[4].j_extent = 0;
1382
1383         if (areq->src != areq->dst)
1384                 sg_count = talitos_map_sg(dev, areq->dst,
1385                                           edesc->dst_nents ? : 1,
1386                                           DMA_FROM_DEVICE,
1387                                           edesc->dst_is_chained);
1388
1389         if (sg_count == 1) {
1390                 desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->dst));
1391         } else {
1392                 struct talitos_ptr *link_tbl_ptr =
1393                         &edesc->link_tbl[edesc->src_nents + 1];
1394
1395                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1396                 desc->ptr[4].ptr = cpu_to_be32((struct talitos_ptr *)
1397                                                edesc->dma_link_tbl +
1398                                                edesc->src_nents + 1);
1399                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1400                                           link_tbl_ptr);
1401                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1402                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1403         }
1404
1405         /* iv out */
1406         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1407                                DMA_FROM_DEVICE);
1408
1409         /* last DWORD empty */
1410         desc->ptr[6].len = 0;
1411         desc->ptr[6].ptr = 0;
1412         desc->ptr[6].j_extent = 0;
1413
1414         ret = talitos_submit(dev, desc, callback, areq);
1415         if (ret != -EINPROGRESS) {
1416                 common_nonsnoop_unmap(dev, edesc, areq);
1417                 kfree(edesc);
1418         }
1419         return ret;
1420 }
1421
1422 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1423                                                     areq)
1424 {
1425         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1426         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1427
1428         return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, areq->nbytes,
1429                                    0, 0, areq->base.flags);
1430 }
1431
1432 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1433 {
1434         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1435         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1436         struct talitos_edesc *edesc;
1437
1438         /* allocate extended descriptor */
1439         edesc = ablkcipher_edesc_alloc(areq);
1440         if (IS_ERR(edesc))
1441                 return PTR_ERR(edesc);
1442
1443         /* set encrypt */
1444         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1445
1446         return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1447 }
1448
1449 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1450 {
1451         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1452         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1453         struct talitos_edesc *edesc;
1454
1455         /* allocate extended descriptor */
1456         edesc = ablkcipher_edesc_alloc(areq);
1457         if (IS_ERR(edesc))
1458                 return PTR_ERR(edesc);
1459
1460         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1461
1462         return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1463 }
1464
1465 struct talitos_alg_template {
1466         struct crypto_alg alg;
1467         __be32 desc_hdr_template;
1468 };
1469
1470 static struct talitos_alg_template driver_algs[] = {
1471         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1472         {
1473                 .alg = {
1474                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1475                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1476                         .cra_blocksize = AES_BLOCK_SIZE,
1477                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1478                         .cra_type = &crypto_aead_type,
1479                         .cra_aead = {
1480                                 .setkey = aead_setkey,
1481                                 .setauthsize = aead_setauthsize,
1482                                 .encrypt = aead_encrypt,
1483                                 .decrypt = aead_decrypt,
1484                                 .givencrypt = aead_givencrypt,
1485                                 .geniv = "<built-in>",
1486                                 .ivsize = AES_BLOCK_SIZE,
1487                                 .maxauthsize = SHA1_DIGEST_SIZE,
1488                         }
1489                 },
1490                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1491                                      DESC_HDR_SEL0_AESU |
1492                                      DESC_HDR_MODE0_AESU_CBC |
1493                                      DESC_HDR_SEL1_MDEUA |
1494                                      DESC_HDR_MODE1_MDEU_INIT |
1495                                      DESC_HDR_MODE1_MDEU_PAD |
1496                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1497         },
1498         {
1499                 .alg = {
1500                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1501                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1502                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1503                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1504                         .cra_type = &crypto_aead_type,
1505                         .cra_aead = {
1506                                 .setkey = aead_setkey,
1507                                 .setauthsize = aead_setauthsize,
1508                                 .encrypt = aead_encrypt,
1509                                 .decrypt = aead_decrypt,
1510                                 .givencrypt = aead_givencrypt,
1511                                 .geniv = "<built-in>",
1512                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1513                                 .maxauthsize = SHA1_DIGEST_SIZE,
1514                         }
1515                 },
1516                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1517                                      DESC_HDR_SEL0_DEU |
1518                                      DESC_HDR_MODE0_DEU_CBC |
1519                                      DESC_HDR_MODE0_DEU_3DES |
1520                                      DESC_HDR_SEL1_MDEUA |
1521                                      DESC_HDR_MODE1_MDEU_INIT |
1522                                      DESC_HDR_MODE1_MDEU_PAD |
1523                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1524         },
1525         {
1526                 .alg = {
1527                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
1528                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1529                         .cra_blocksize = AES_BLOCK_SIZE,
1530                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1531                         .cra_type = &crypto_aead_type,
1532                         .cra_aead = {
1533                                 .setkey = aead_setkey,
1534                                 .setauthsize = aead_setauthsize,
1535                                 .encrypt = aead_encrypt,
1536                                 .decrypt = aead_decrypt,
1537                                 .givencrypt = aead_givencrypt,
1538                                 .geniv = "<built-in>",
1539                                 .ivsize = AES_BLOCK_SIZE,
1540                                 .maxauthsize = SHA256_DIGEST_SIZE,
1541                         }
1542                 },
1543                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1544                                      DESC_HDR_SEL0_AESU |
1545                                      DESC_HDR_MODE0_AESU_CBC |
1546                                      DESC_HDR_SEL1_MDEUA |
1547                                      DESC_HDR_MODE1_MDEU_INIT |
1548                                      DESC_HDR_MODE1_MDEU_PAD |
1549                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1550         },
1551         {
1552                 .alg = {
1553                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1554                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1555                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1556                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1557                         .cra_type = &crypto_aead_type,
1558                         .cra_aead = {
1559                                 .setkey = aead_setkey,
1560                                 .setauthsize = aead_setauthsize,
1561                                 .encrypt = aead_encrypt,
1562                                 .decrypt = aead_decrypt,
1563                                 .givencrypt = aead_givencrypt,
1564                                 .geniv = "<built-in>",
1565                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1566                                 .maxauthsize = SHA256_DIGEST_SIZE,
1567                         }
1568                 },
1569                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1570                                      DESC_HDR_SEL0_DEU |
1571                                      DESC_HDR_MODE0_DEU_CBC |
1572                                      DESC_HDR_MODE0_DEU_3DES |
1573                                      DESC_HDR_SEL1_MDEUA |
1574                                      DESC_HDR_MODE1_MDEU_INIT |
1575                                      DESC_HDR_MODE1_MDEU_PAD |
1576                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1577         },
1578         {
1579                 .alg = {
1580                         .cra_name = "authenc(hmac(md5),cbc(aes))",
1581                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
1582                         .cra_blocksize = AES_BLOCK_SIZE,
1583                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1584                         .cra_type = &crypto_aead_type,
1585                         .cra_aead = {
1586                                 .setkey = aead_setkey,
1587                                 .setauthsize = aead_setauthsize,
1588                                 .encrypt = aead_encrypt,
1589                                 .decrypt = aead_decrypt,
1590                                 .givencrypt = aead_givencrypt,
1591                                 .geniv = "<built-in>",
1592                                 .ivsize = AES_BLOCK_SIZE,
1593                                 .maxauthsize = MD5_DIGEST_SIZE,
1594                         }
1595                 },
1596                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1597                                      DESC_HDR_SEL0_AESU |
1598                                      DESC_HDR_MODE0_AESU_CBC |
1599                                      DESC_HDR_SEL1_MDEUA |
1600                                      DESC_HDR_MODE1_MDEU_INIT |
1601                                      DESC_HDR_MODE1_MDEU_PAD |
1602                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1603         },
1604         {
1605                 .alg = {
1606                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1607                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
1608                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1609                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1610                         .cra_type = &crypto_aead_type,
1611                         .cra_aead = {
1612                                 .setkey = aead_setkey,
1613                                 .setauthsize = aead_setauthsize,
1614                                 .encrypt = aead_encrypt,
1615                                 .decrypt = aead_decrypt,
1616                                 .givencrypt = aead_givencrypt,
1617                                 .geniv = "<built-in>",
1618                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1619                                 .maxauthsize = MD5_DIGEST_SIZE,
1620                         }
1621                 },
1622                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1623                                      DESC_HDR_SEL0_DEU |
1624                                      DESC_HDR_MODE0_DEU_CBC |
1625                                      DESC_HDR_MODE0_DEU_3DES |
1626                                      DESC_HDR_SEL1_MDEUA |
1627                                      DESC_HDR_MODE1_MDEU_INIT |
1628                                      DESC_HDR_MODE1_MDEU_PAD |
1629                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
1630         },
1631         /* ABLKCIPHER algorithms. */
1632         {
1633                 .alg = {
1634                         .cra_name = "cbc(aes)",
1635                         .cra_driver_name = "cbc-aes-talitos",
1636                         .cra_blocksize = AES_BLOCK_SIZE,
1637                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1638                                      CRYPTO_ALG_ASYNC,
1639                         .cra_type = &crypto_ablkcipher_type,
1640                         .cra_ablkcipher = {
1641                                 .setkey = ablkcipher_setkey,
1642                                 .encrypt = ablkcipher_encrypt,
1643                                 .decrypt = ablkcipher_decrypt,
1644                                 .geniv = "eseqiv",
1645                                 .min_keysize = AES_MIN_KEY_SIZE,
1646                                 .max_keysize = AES_MAX_KEY_SIZE,
1647                                 .ivsize = AES_BLOCK_SIZE,
1648                         }
1649                 },
1650                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
1651                                      DESC_HDR_SEL0_AESU |
1652                                      DESC_HDR_MODE0_AESU_CBC,
1653         },
1654         {
1655                 .alg = {
1656                         .cra_name = "cbc(des3_ede)",
1657                         .cra_driver_name = "cbc-3des-talitos",
1658                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1659                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1660                                      CRYPTO_ALG_ASYNC,
1661                         .cra_type = &crypto_ablkcipher_type,
1662                         .cra_ablkcipher = {
1663                                 .setkey = ablkcipher_setkey,
1664                                 .encrypt = ablkcipher_encrypt,
1665                                 .decrypt = ablkcipher_decrypt,
1666                                 .geniv = "eseqiv",
1667                                 .min_keysize = DES3_EDE_KEY_SIZE,
1668                                 .max_keysize = DES3_EDE_KEY_SIZE,
1669                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1670                         }
1671                 },
1672                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
1673                                      DESC_HDR_SEL0_DEU |
1674                                      DESC_HDR_MODE0_DEU_CBC |
1675                                      DESC_HDR_MODE0_DEU_3DES,
1676         }
1677 };
1678
1679 struct talitos_crypto_alg {
1680         struct list_head entry;
1681         struct device *dev;
1682         __be32 desc_hdr_template;
1683         struct crypto_alg crypto_alg;
1684 };
1685
1686 static int talitos_cra_init(struct crypto_tfm *tfm)
1687 {
1688         struct crypto_alg *alg = tfm->__crt_alg;
1689         struct talitos_crypto_alg *talitos_alg =
1690                  container_of(alg, struct talitos_crypto_alg, crypto_alg);
1691         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
1692
1693         /* update context with ptr to dev */
1694         ctx->dev = talitos_alg->dev;
1695         /* copy descriptor header template value */
1696         ctx->desc_hdr_template = talitos_alg->desc_hdr_template;
1697
1698         /* random first IV */
1699         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
1700
1701         return 0;
1702 }
1703
1704 /*
1705  * given the alg's descriptor header template, determine whether descriptor
1706  * type and primary/secondary execution units required match the hw
1707  * capabilities description provided in the device tree node.
1708  */
1709 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
1710 {
1711         struct talitos_private *priv = dev_get_drvdata(dev);
1712         int ret;
1713
1714         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
1715               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
1716
1717         if (SECONDARY_EU(desc_hdr_template))
1718                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
1719                               & priv->exec_units);
1720
1721         return ret;
1722 }
1723
1724 static int talitos_remove(struct of_device *ofdev)
1725 {
1726         struct device *dev = &ofdev->dev;
1727         struct talitos_private *priv = dev_get_drvdata(dev);
1728         struct talitos_crypto_alg *t_alg, *n;
1729         int i;
1730
1731         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
1732                 crypto_unregister_alg(&t_alg->crypto_alg);
1733                 list_del(&t_alg->entry);
1734                 kfree(t_alg);
1735         }
1736
1737         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
1738                 talitos_unregister_rng(dev);
1739
1740         kfree(priv->submit_count);
1741         kfree(priv->tail);
1742         kfree(priv->head);
1743
1744         if (priv->fifo)
1745                 for (i = 0; i < priv->num_channels; i++)
1746                         kfree(priv->fifo[i]);
1747
1748         kfree(priv->fifo);
1749         kfree(priv->head_lock);
1750         kfree(priv->tail_lock);
1751
1752         if (priv->irq != NO_IRQ) {
1753                 free_irq(priv->irq, dev);
1754                 irq_dispose_mapping(priv->irq);
1755         }
1756
1757         tasklet_kill(&priv->done_task);
1758
1759         iounmap(priv->reg);
1760
1761         dev_set_drvdata(dev, NULL);
1762
1763         kfree(priv);
1764
1765         return 0;
1766 }
1767
1768 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
1769                                                     struct talitos_alg_template
1770                                                            *template)
1771 {
1772         struct talitos_crypto_alg *t_alg;
1773         struct crypto_alg *alg;
1774
1775         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
1776         if (!t_alg)
1777                 return ERR_PTR(-ENOMEM);
1778
1779         alg = &t_alg->crypto_alg;
1780         *alg = template->alg;
1781
1782         alg->cra_module = THIS_MODULE;
1783         alg->cra_init = talitos_cra_init;
1784         alg->cra_priority = TALITOS_CRA_PRIORITY;
1785         alg->cra_alignmask = 0;
1786         alg->cra_ctxsize = sizeof(struct talitos_ctx);
1787
1788         t_alg->desc_hdr_template = template->desc_hdr_template;
1789         t_alg->dev = dev;
1790
1791         return t_alg;
1792 }
1793
1794 static int talitos_probe(struct of_device *ofdev,
1795                          const struct of_device_id *match)
1796 {
1797         struct device *dev = &ofdev->dev;
1798         struct device_node *np = ofdev->node;
1799         struct talitos_private *priv;
1800         const unsigned int *prop;
1801         int i, err;
1802
1803         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
1804         if (!priv)
1805                 return -ENOMEM;
1806
1807         dev_set_drvdata(dev, priv);
1808
1809         priv->ofdev = ofdev;
1810
1811         tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
1812
1813         INIT_LIST_HEAD(&priv->alg_list);
1814
1815         priv->irq = irq_of_parse_and_map(np, 0);
1816
1817         if (priv->irq == NO_IRQ) {
1818                 dev_err(dev, "failed to map irq\n");
1819                 err = -EINVAL;
1820                 goto err_out;
1821         }
1822
1823         /* get the irq line */
1824         err = request_irq(priv->irq, talitos_interrupt, 0,
1825                           dev_driver_string(dev), dev);
1826         if (err) {
1827                 dev_err(dev, "failed to request irq %d\n", priv->irq);
1828                 irq_dispose_mapping(priv->irq);
1829                 priv->irq = NO_IRQ;
1830                 goto err_out;
1831         }
1832
1833         priv->reg = of_iomap(np, 0);
1834         if (!priv->reg) {
1835                 dev_err(dev, "failed to of_iomap\n");
1836                 err = -ENOMEM;
1837                 goto err_out;
1838         }
1839
1840         /* get SEC version capabilities from device tree */
1841         prop = of_get_property(np, "fsl,num-channels", NULL);
1842         if (prop)
1843                 priv->num_channels = *prop;
1844
1845         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
1846         if (prop)
1847                 priv->chfifo_len = *prop;
1848
1849         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
1850         if (prop)
1851                 priv->exec_units = *prop;
1852
1853         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
1854         if (prop)
1855                 priv->desc_types = *prop;
1856
1857         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
1858             !priv->exec_units || !priv->desc_types) {
1859                 dev_err(dev, "invalid property data in device tree node\n");
1860                 err = -EINVAL;
1861                 goto err_out;
1862         }
1863
1864         if (of_device_is_compatible(np, "fsl,sec3.0"))
1865                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
1866
1867         if (of_device_is_compatible(np, "fsl,sec2.1"))
1868                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK;
1869
1870         priv->head_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1871                                   GFP_KERNEL);
1872         priv->tail_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
1873                                   GFP_KERNEL);
1874         if (!priv->head_lock || !priv->tail_lock) {
1875                 dev_err(dev, "failed to allocate fifo locks\n");
1876                 err = -ENOMEM;
1877                 goto err_out;
1878         }
1879
1880         for (i = 0; i < priv->num_channels; i++) {
1881                 spin_lock_init(&priv->head_lock[i]);
1882                 spin_lock_init(&priv->tail_lock[i]);
1883         }
1884
1885         priv->fifo = kmalloc(sizeof(struct talitos_request *) *
1886                              priv->num_channels, GFP_KERNEL);
1887         if (!priv->fifo) {
1888                 dev_err(dev, "failed to allocate request fifo\n");
1889                 err = -ENOMEM;
1890                 goto err_out;
1891         }
1892
1893         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
1894
1895         for (i = 0; i < priv->num_channels; i++) {
1896                 priv->fifo[i] = kzalloc(sizeof(struct talitos_request) *
1897                                         priv->fifo_len, GFP_KERNEL);
1898                 if (!priv->fifo[i]) {
1899                         dev_err(dev, "failed to allocate request fifo %d\n", i);
1900                         err = -ENOMEM;
1901                         goto err_out;
1902                 }
1903         }
1904
1905         priv->submit_count = kmalloc(sizeof(atomic_t) * priv->num_channels,
1906                                      GFP_KERNEL);
1907         if (!priv->submit_count) {
1908                 dev_err(dev, "failed to allocate fifo submit count space\n");
1909                 err = -ENOMEM;
1910                 goto err_out;
1911         }
1912         for (i = 0; i < priv->num_channels; i++)
1913                 atomic_set(&priv->submit_count[i], -(priv->chfifo_len - 1));
1914
1915         priv->head = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1916         priv->tail = kzalloc(sizeof(int) * priv->num_channels, GFP_KERNEL);
1917         if (!priv->head || !priv->tail) {
1918                 dev_err(dev, "failed to allocate request index space\n");
1919                 err = -ENOMEM;
1920                 goto err_out;
1921         }
1922
1923         /* reset and initialize the h/w */
1924         err = init_device(dev);
1925         if (err) {
1926                 dev_err(dev, "failed to initialize device\n");
1927                 goto err_out;
1928         }
1929
1930         /* register the RNG, if available */
1931         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
1932                 err = talitos_register_rng(dev);
1933                 if (err) {
1934                         dev_err(dev, "failed to register hwrng: %d\n", err);
1935                         goto err_out;
1936                 } else
1937                         dev_info(dev, "hwrng\n");
1938         }
1939
1940         /* register crypto algorithms the device supports */
1941         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
1942                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
1943                         struct talitos_crypto_alg *t_alg;
1944
1945                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
1946                         if (IS_ERR(t_alg)) {
1947                                 err = PTR_ERR(t_alg);
1948                                 goto err_out;
1949                         }
1950
1951                         err = crypto_register_alg(&t_alg->crypto_alg);
1952                         if (err) {
1953                                 dev_err(dev, "%s alg registration failed\n",
1954                                         t_alg->crypto_alg.cra_driver_name);
1955                                 kfree(t_alg);
1956                         } else {
1957                                 list_add_tail(&t_alg->entry, &priv->alg_list);
1958                                 dev_info(dev, "%s\n",
1959                                          t_alg->crypto_alg.cra_driver_name);
1960                         }
1961                 }
1962         }
1963
1964         return 0;
1965
1966 err_out:
1967         talitos_remove(ofdev);
1968
1969         return err;
1970 }
1971
1972 static struct of_device_id talitos_match[] = {
1973         {
1974                 .compatible = "fsl,sec2.0",
1975         },
1976         {},
1977 };
1978 MODULE_DEVICE_TABLE(of, talitos_match);
1979
1980 static struct of_platform_driver talitos_driver = {
1981         .name = "talitos",
1982         .match_table = talitos_match,
1983         .probe = talitos_probe,
1984         .remove = talitos_remove,
1985 };
1986
1987 static int __init talitos_init(void)
1988 {
1989         return of_register_platform_driver(&talitos_driver);
1990 }
1991 module_init(talitos_init);
1992
1993 static void __exit talitos_exit(void)
1994 {
1995         of_unregister_platform_driver(&talitos_driver);
1996 }
1997 module_exit(talitos_exit);
1998
1999 MODULE_LICENSE("GPL");
2000 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2001 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");