2 * Routines supporting the Power 7+ Nest Accelerators driver
4 * Copyright (C) 2011-2012 International Business Machines Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 only.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 * Author: Kent Yoder <yoder1@us.ibm.com>
22 #include <crypto/internal/hash.h>
23 #include <crypto/hash.h>
24 #include <crypto/aes.h>
25 #include <crypto/sha.h>
26 #include <crypto/algapi.h>
27 #include <crypto/scatterwalk.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/types.h>
32 #include <linux/crypto.h>
33 #include <linux/scatterlist.h>
34 #include <linux/device.h>
36 #include <asm/hvcall.h>
39 #include "nx_csbcpb.h"
44 * nx_hcall_sync - make an H_COP_OP hcall for the passed in op structure
46 * @nx_ctx: the crypto context handle
47 * @op: PFO operation struct to pass in
48 * @may_sleep: flag indicating the request can sleep
50 * Make the hcall, retrying while the hardware is busy. If we cannot yield
51 * the thread, limit the number of retries to 10 here.
53 int nx_hcall_sync(struct nx_crypto_ctx *nx_ctx,
54 struct vio_pfo_op *op,
58 struct vio_dev *viodev = nx_driver.viodev;
60 atomic_inc(&(nx_ctx->stats->sync_ops));
63 rc = vio_h_cop_sync(viodev, op);
64 } while (rc == -EBUSY && !may_sleep && retries--);
67 dev_dbg(&viodev->dev, "vio_h_cop_sync failed: rc: %d "
68 "hcall rc: %ld\n", rc, op->hcall_err);
69 atomic_inc(&(nx_ctx->stats->errors));
70 atomic_set(&(nx_ctx->stats->last_error), op->hcall_err);
71 atomic_set(&(nx_ctx->stats->last_error_pid), current->pid);
78 * nx_build_sg_list - build an NX scatter list describing a single buffer
80 * @sg_head: pointer to the first scatter list element to build
81 * @start_addr: pointer to the linear buffer
82 * @len: length of the data at @start_addr
83 * @sgmax: the largest number of scatter list elements we're allowed to create
85 * This function will start writing nx_sg elements at @sg_head and keep
86 * writing them until all of the data from @start_addr is described or
87 * until sgmax elements have been written. Scatter list elements will be
88 * created such that none of the elements describes a buffer that crosses a 4K
91 struct nx_sg *nx_build_sg_list(struct nx_sg *sg_head,
96 unsigned int sg_len = 0;
98 u64 sg_addr = (u64)start_addr;
101 /* determine the start and end for this address range - slightly
102 * different if this is in VMALLOC_REGION */
103 if (is_vmalloc_addr(start_addr))
104 sg_addr = page_to_phys(vmalloc_to_page(start_addr))
105 + offset_in_page(sg_addr);
107 sg_addr = __pa(sg_addr);
109 end_addr = sg_addr + len;
111 /* each iteration will write one struct nx_sg element and add the
112 * length of data described by that element to sg_len. Once @len bytes
113 * have been described (or @sgmax elements have been written), the
114 * loop ends. min_t is used to ensure @end_addr falls on the same page
115 * as sg_addr, if not, we need to create another nx_sg element for the
116 * data on the next page.
118 * Also when using vmalloc'ed data, every time that a system page
119 * boundary is crossed the physical address needs to be re-calculated.
121 for (sg = sg_head; sg_len < len; sg++) {
125 sg_addr = min_t(u64, NX_PAGE_NUM(sg_addr + NX_PAGE_SIZE),
128 next_page = (sg->addr & PAGE_MASK) + PAGE_SIZE;
129 sg->len = min_t(u64, sg_addr, next_page) - sg->addr;
132 if (sg_addr >= next_page &&
133 is_vmalloc_addr(start_addr + sg_len)) {
134 sg_addr = page_to_phys(vmalloc_to_page(
135 start_addr + sg_len));
136 end_addr = sg_addr + len - sg_len;
139 if ((sg - sg_head) == sgmax) {
140 pr_err("nx: scatter/gather list overflow, pid: %d\n",
146 /* return the moved sg_head pointer */
151 * nx_walk_and_build - walk a linux scatterlist and build an nx scatterlist
153 * @nx_dst: pointer to the first nx_sg element to write
154 * @sglen: max number of nx_sg entries we're allowed to write
155 * @sg_src: pointer to the source linux scatterlist to walk
156 * @start: number of bytes to fast-forward past at the beginning of @sg_src
157 * @src_len: number of bytes to walk in @sg_src
159 struct nx_sg *nx_walk_and_build(struct nx_sg *nx_dst,
161 struct scatterlist *sg_src,
163 unsigned int src_len)
165 struct scatter_walk walk;
166 struct nx_sg *nx_sg = nx_dst;
167 unsigned int n, offset = 0, len = src_len;
170 /* we need to fast forward through @start bytes first */
172 scatterwalk_start(&walk, sg_src);
174 if (start < offset + sg_src->length)
177 offset += sg_src->length;
178 sg_src = scatterwalk_sg_next(sg_src);
181 /* start - offset is the number of bytes to advance in the scatterlist
182 * element we're currently looking at */
183 scatterwalk_advance(&walk, start - offset);
185 while (len && nx_sg) {
186 n = scatterwalk_clamp(&walk, len);
188 scatterwalk_start(&walk, sg_next(walk.sg));
189 n = scatterwalk_clamp(&walk, len);
191 dst = scatterwalk_map(&walk);
193 nx_sg = nx_build_sg_list(nx_sg, dst, n, sglen);
196 scatterwalk_unmap(dst);
197 scatterwalk_advance(&walk, n);
198 scatterwalk_done(&walk, SCATTERWALK_FROM_SG, len);
201 /* return the moved destination pointer */
206 * nx_build_sg_lists - walk the input scatterlists and build arrays of NX
207 * scatterlists based on them.
209 * @nx_ctx: NX crypto context for the lists we're building
210 * @desc: the block cipher descriptor for the operation
211 * @dst: destination scatterlist
212 * @src: source scatterlist
213 * @nbytes: length of data described in the scatterlists
214 * @iv: destination for the iv data, if the algorithm requires it
216 * This is common code shared by all the AES algorithms. It uses the block
217 * cipher walk routines to traverse input and output scatterlists, building
218 * corresponding NX scatterlists
220 int nx_build_sg_lists(struct nx_crypto_ctx *nx_ctx,
221 struct blkcipher_desc *desc,
222 struct scatterlist *dst,
223 struct scatterlist *src,
227 struct nx_sg *nx_insg = nx_ctx->in_sg;
228 struct nx_sg *nx_outsg = nx_ctx->out_sg;
231 memcpy(iv, desc->info, AES_BLOCK_SIZE);
233 nx_insg = nx_walk_and_build(nx_insg, nx_ctx->ap->sglen, src, 0, nbytes);
234 nx_outsg = nx_walk_and_build(nx_outsg, nx_ctx->ap->sglen, dst, 0, nbytes);
236 /* these lengths should be negative, which will indicate to phyp that
237 * the input and output parameters are scatterlists, not linear
239 nx_ctx->op.inlen = (nx_ctx->in_sg - nx_insg) * sizeof(struct nx_sg);
240 nx_ctx->op.outlen = (nx_ctx->out_sg - nx_outsg) * sizeof(struct nx_sg);
246 * nx_ctx_init - initialize an nx_ctx's vio_pfo_op struct
248 * @nx_ctx: the nx context to initialize
249 * @function: the function code for the op
251 void nx_ctx_init(struct nx_crypto_ctx *nx_ctx, unsigned int function)
253 spin_lock_init(&nx_ctx->lock);
254 memset(nx_ctx->kmem, 0, nx_ctx->kmem_len);
255 nx_ctx->csbcpb->csb.valid |= NX_CSB_VALID_BIT;
257 nx_ctx->op.flags = function;
258 nx_ctx->op.csbcpb = __pa(nx_ctx->csbcpb);
259 nx_ctx->op.in = __pa(nx_ctx->in_sg);
260 nx_ctx->op.out = __pa(nx_ctx->out_sg);
262 if (nx_ctx->csbcpb_aead) {
263 nx_ctx->csbcpb_aead->csb.valid |= NX_CSB_VALID_BIT;
265 nx_ctx->op_aead.flags = function;
266 nx_ctx->op_aead.csbcpb = __pa(nx_ctx->csbcpb_aead);
267 nx_ctx->op_aead.in = __pa(nx_ctx->in_sg);
268 nx_ctx->op_aead.out = __pa(nx_ctx->out_sg);
272 static void nx_of_update_status(struct device *dev,
276 if (!strncmp(p->value, "okay", p->length)) {
277 props->status = NX_WAITING;
278 props->flags |= NX_OF_FLAG_STATUS_SET;
280 dev_info(dev, "%s: status '%s' is not 'okay'\n", __func__,
285 static void nx_of_update_sglen(struct device *dev,
289 if (p->length != sizeof(props->max_sg_len)) {
290 dev_err(dev, "%s: unexpected format for "
291 "ibm,max-sg-len property\n", __func__);
292 dev_dbg(dev, "%s: ibm,max-sg-len is %d bytes "
293 "long, expected %zd bytes\n", __func__,
294 p->length, sizeof(props->max_sg_len));
298 props->max_sg_len = *(u32 *)p->value;
299 props->flags |= NX_OF_FLAG_MAXSGLEN_SET;
302 static void nx_of_update_msc(struct device *dev,
306 struct msc_triplet *trip;
307 struct max_sync_cop *msc;
308 unsigned int bytes_so_far, i, lenp;
310 msc = (struct max_sync_cop *)p->value;
313 /* You can't tell if the data read in for this property is sane by its
314 * size alone. This is because there are sizes embedded in the data
315 * structure. The best we can do is check lengths as we parse and bail
316 * as soon as a length error is detected. */
319 while ((bytes_so_far + sizeof(struct max_sync_cop)) <= lenp) {
320 bytes_so_far += sizeof(struct max_sync_cop);
325 ((bytes_so_far + sizeof(struct msc_triplet)) <= lenp) &&
328 if (msc->fc > NX_MAX_FC || msc->mode > NX_MAX_MODE) {
329 dev_err(dev, "unknown function code/mode "
330 "combo: %d/%d (ignored)\n", msc->fc,
335 switch (trip->keybitlen) {
338 props->ap[msc->fc][msc->mode][0].databytelen =
340 props->ap[msc->fc][msc->mode][0].sglen =
344 props->ap[msc->fc][msc->mode][1].databytelen =
346 props->ap[msc->fc][msc->mode][1].sglen =
350 if (msc->fc == NX_FC_AES) {
351 props->ap[msc->fc][msc->mode][2].
352 databytelen = trip->databytelen;
353 props->ap[msc->fc][msc->mode][2].sglen =
355 } else if (msc->fc == NX_FC_AES_HMAC ||
356 msc->fc == NX_FC_SHA) {
357 props->ap[msc->fc][msc->mode][1].
358 databytelen = trip->databytelen;
359 props->ap[msc->fc][msc->mode][1].sglen =
362 dev_warn(dev, "unknown function "
363 "code/key bit len combo"
364 ": (%u/256)\n", msc->fc);
368 props->ap[msc->fc][msc->mode][2].databytelen =
370 props->ap[msc->fc][msc->mode][2].sglen =
374 dev_warn(dev, "unknown function code/key bit "
375 "len combo: (%u/%u)\n", msc->fc,
380 bytes_so_far += sizeof(struct msc_triplet);
384 msc = (struct max_sync_cop *)trip;
387 props->flags |= NX_OF_FLAG_MAXSYNCCOP_SET;
391 * nx_of_init - read openFirmware values from the device tree
393 * @dev: device handle
394 * @props: pointer to struct to hold the properties values
396 * Called once at driver probe time, this function will read out the
397 * openFirmware properties we use at runtime. If all the OF properties are
398 * acceptable, when we exit this function props->flags will indicate that
399 * we're ready to register our crypto algorithms.
401 static void nx_of_init(struct device *dev, struct nx_of *props)
403 struct device_node *base_node = dev->of_node;
406 p = of_find_property(base_node, "status", NULL);
408 dev_info(dev, "%s: property 'status' not found\n", __func__);
410 nx_of_update_status(dev, p, props);
412 p = of_find_property(base_node, "ibm,max-sg-len", NULL);
414 dev_info(dev, "%s: property 'ibm,max-sg-len' not found\n",
417 nx_of_update_sglen(dev, p, props);
419 p = of_find_property(base_node, "ibm,max-sync-cop", NULL);
421 dev_info(dev, "%s: property 'ibm,max-sync-cop' not found\n",
424 nx_of_update_msc(dev, p, props);
428 * nx_register_algs - register algorithms with the crypto API
430 * Called from nx_probe()
432 * If all OF properties are in an acceptable state, the driver flags will
433 * indicate that we're ready and we'll create our debugfs files and register
434 * out crypto algorithms.
436 static int nx_register_algs(void)
440 if (nx_driver.of.flags != NX_OF_FLAG_MASK_READY)
443 memset(&nx_driver.stats, 0, sizeof(struct nx_stats));
445 rc = NX_DEBUGFS_INIT(&nx_driver);
449 nx_driver.of.status = NX_OKAY;
451 rc = crypto_register_alg(&nx_ecb_aes_alg);
455 rc = crypto_register_alg(&nx_cbc_aes_alg);
459 rc = crypto_register_alg(&nx_ctr_aes_alg);
463 rc = crypto_register_alg(&nx_ctr3686_aes_alg);
467 rc = crypto_register_alg(&nx_gcm_aes_alg);
469 goto out_unreg_ctr3686;
471 rc = crypto_register_alg(&nx_gcm4106_aes_alg);
475 rc = crypto_register_alg(&nx_ccm_aes_alg);
477 goto out_unreg_gcm4106;
479 rc = crypto_register_alg(&nx_ccm4309_aes_alg);
483 rc = crypto_register_shash(&nx_shash_sha256_alg);
485 goto out_unreg_ccm4309;
487 rc = crypto_register_shash(&nx_shash_sha512_alg);
491 rc = crypto_register_shash(&nx_shash_aes_xcbc_alg);
498 crypto_unregister_shash(&nx_shash_sha512_alg);
500 crypto_unregister_shash(&nx_shash_sha256_alg);
502 crypto_unregister_alg(&nx_ccm4309_aes_alg);
504 crypto_unregister_alg(&nx_ccm_aes_alg);
506 crypto_unregister_alg(&nx_gcm4106_aes_alg);
508 crypto_unregister_alg(&nx_gcm_aes_alg);
510 crypto_unregister_alg(&nx_ctr3686_aes_alg);
512 crypto_unregister_alg(&nx_ctr_aes_alg);
514 crypto_unregister_alg(&nx_cbc_aes_alg);
516 crypto_unregister_alg(&nx_ecb_aes_alg);
522 * nx_crypto_ctx_init - create and initialize a crypto api context
524 * @nx_ctx: the crypto api context
525 * @fc: function code for the context
526 * @mode: the function code specific mode for this context
528 static int nx_crypto_ctx_init(struct nx_crypto_ctx *nx_ctx, u32 fc, u32 mode)
530 if (nx_driver.of.status != NX_OKAY) {
531 pr_err("Attempt to initialize NX crypto context while device "
532 "is not available!\n");
536 /* we need an extra page for csbcpb_aead for these modes */
537 if (mode == NX_MODE_AES_GCM || mode == NX_MODE_AES_CCM)
538 nx_ctx->kmem_len = (4 * NX_PAGE_SIZE) +
539 sizeof(struct nx_csbcpb);
541 nx_ctx->kmem_len = (3 * NX_PAGE_SIZE) +
542 sizeof(struct nx_csbcpb);
544 nx_ctx->kmem = kmalloc(nx_ctx->kmem_len, GFP_KERNEL);
548 /* the csbcpb and scatterlists must be 4K aligned pages */
549 nx_ctx->csbcpb = (struct nx_csbcpb *)(round_up((u64)nx_ctx->kmem,
551 nx_ctx->in_sg = (struct nx_sg *)((u8 *)nx_ctx->csbcpb + NX_PAGE_SIZE);
552 nx_ctx->out_sg = (struct nx_sg *)((u8 *)nx_ctx->in_sg + NX_PAGE_SIZE);
554 if (mode == NX_MODE_AES_GCM || mode == NX_MODE_AES_CCM)
555 nx_ctx->csbcpb_aead =
556 (struct nx_csbcpb *)((u8 *)nx_ctx->out_sg +
559 /* give each context a pointer to global stats and their OF
561 nx_ctx->stats = &nx_driver.stats;
562 memcpy(nx_ctx->props, nx_driver.of.ap[fc][mode],
563 sizeof(struct alg_props) * 3);
568 /* entry points from the crypto tfm initializers */
569 int nx_crypto_ctx_aes_ccm_init(struct crypto_tfm *tfm)
571 return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
575 int nx_crypto_ctx_aes_gcm_init(struct crypto_tfm *tfm)
577 return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
581 int nx_crypto_ctx_aes_ctr_init(struct crypto_tfm *tfm)
583 return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
587 int nx_crypto_ctx_aes_cbc_init(struct crypto_tfm *tfm)
589 return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
593 int nx_crypto_ctx_aes_ecb_init(struct crypto_tfm *tfm)
595 return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
599 int nx_crypto_ctx_sha_init(struct crypto_tfm *tfm)
601 return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_SHA, NX_MODE_SHA);
604 int nx_crypto_ctx_aes_xcbc_init(struct crypto_tfm *tfm)
606 return nx_crypto_ctx_init(crypto_tfm_ctx(tfm), NX_FC_AES,
607 NX_MODE_AES_XCBC_MAC);
611 * nx_crypto_ctx_exit - destroy a crypto api context
613 * @tfm: the crypto transform pointer for the context
615 * As crypto API contexts are destroyed, this exit hook is called to free the
616 * memory associated with it.
618 void nx_crypto_ctx_exit(struct crypto_tfm *tfm)
620 struct nx_crypto_ctx *nx_ctx = crypto_tfm_ctx(tfm);
622 kzfree(nx_ctx->kmem);
623 nx_ctx->csbcpb = NULL;
624 nx_ctx->csbcpb_aead = NULL;
625 nx_ctx->in_sg = NULL;
626 nx_ctx->out_sg = NULL;
629 static int nx_probe(struct vio_dev *viodev, const struct vio_device_id *id)
631 dev_dbg(&viodev->dev, "driver probed: %s resource id: 0x%x\n",
632 viodev->name, viodev->resource_id);
634 if (nx_driver.viodev) {
635 dev_err(&viodev->dev, "%s: Attempt to register more than one "
636 "instance of the hardware\n", __func__);
640 nx_driver.viodev = viodev;
642 nx_of_init(&viodev->dev, &nx_driver.of);
644 return nx_register_algs();
647 static int nx_remove(struct vio_dev *viodev)
649 dev_dbg(&viodev->dev, "entering nx_remove for UA 0x%x\n",
650 viodev->unit_address);
652 if (nx_driver.of.status == NX_OKAY) {
653 NX_DEBUGFS_FINI(&nx_driver);
655 crypto_unregister_alg(&nx_ccm_aes_alg);
656 crypto_unregister_alg(&nx_ccm4309_aes_alg);
657 crypto_unregister_alg(&nx_gcm_aes_alg);
658 crypto_unregister_alg(&nx_gcm4106_aes_alg);
659 crypto_unregister_alg(&nx_ctr_aes_alg);
660 crypto_unregister_alg(&nx_ctr3686_aes_alg);
661 crypto_unregister_alg(&nx_cbc_aes_alg);
662 crypto_unregister_alg(&nx_ecb_aes_alg);
663 crypto_unregister_shash(&nx_shash_sha256_alg);
664 crypto_unregister_shash(&nx_shash_sha512_alg);
665 crypto_unregister_shash(&nx_shash_aes_xcbc_alg);
672 /* module wide initialization/cleanup */
673 static int __init nx_init(void)
675 return vio_register_driver(&nx_driver.viodriver);
678 static void __exit nx_fini(void)
680 vio_unregister_driver(&nx_driver.viodriver);
683 static struct vio_device_id nx_crypto_driver_ids[] = {
684 { "ibm,sym-encryption-v1", "ibm,sym-encryption" },
687 MODULE_DEVICE_TABLE(vio, nx_crypto_driver_ids);
689 /* driver state structure */
690 struct nx_crypto_driver nx_driver = {
692 .id_table = nx_crypto_driver_ids,
699 module_init(nx_init);
700 module_exit(nx_fini);
702 MODULE_AUTHOR("Kent Yoder <yoder1@us.ibm.com>");
703 MODULE_DESCRIPTION(NX_STRING);
704 MODULE_LICENSE("GPL");
705 MODULE_VERSION(NX_VERSION);