2 * CAAM hardware register-level view
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
10 #include <linux/types.h>
14 * Architecture-specific register access methods
16 * CAAM's bus-addressable registers are 64 bits internally.
17 * They have been wired to be safely accessible on 32-bit
18 * architectures, however. Registers were organized such
19 * that (a) they can be contained in 32 bits, (b) if not, then they
20 * can be treated as two 32-bit entities, or finally (c) if they
21 * must be treated as a single 64-bit value, then this can safely
22 * be done with two 32-bit cycles.
24 * For 32-bit operations on 64-bit values, CAAM follows the same
25 * 64-bit register access conventions as it's predecessors, in that
26 * writes are "triggered" by a write to the register at the numerically
27 * higher address, thus, a full 64-bit write cycle requires a write
28 * to the lower address, followed by a write to the higher address,
29 * which will latch/execute the write cycle.
31 * For example, let's assume a SW reset of CAAM through the master
32 * configuration register.
33 * - SWRST is in bit 31 of MCFG.
34 * - MCFG begins at base+0x0000.
35 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
36 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
38 * (and on Power, the convention is 0-31, 32-63, I know...)
40 * Assuming a 64-bit write to this MCFG to perform a software reset
41 * would then require a write of 0 to base+0x0000, followed by a
42 * write of 0x80000000 to base+0x0004, which would "execute" the
45 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
46 * write 0x8000000 to base+0x0004, and the reset would work fine.
47 * However, since CAAM does contain some write-and-read-intended
48 * 64-bit registers, this code defines 64-bit access methods for
49 * the sake of internal consistency and simplicity, and so that a
50 * clean transition to 64-bit is possible when it becomes necessary.
52 * There are limitations to this that the developer must recognize.
53 * 32-bit architectures cannot enforce an atomic-64 operation,
56 * - On writes, since the HW is assumed to latch the cycle on the
57 * write of the higher-numeric-address word, then ordered
60 * - For reads, where a register contains a relevant value of more
61 * that 32 bits, the hardware employs logic to latch the other
62 * "half" of the data until read, ensuring an accurate value.
63 * This is of particular relevance when dealing with CAAM's
64 * performance counters.
69 #define wr_reg32(reg, data) out_be32(reg, data)
70 #define rd_reg32(reg) in_be32(reg)
72 #define wr_reg64(reg, data) out_be64(reg, data)
73 #define rd_reg64(reg) in_be64(reg)
76 #ifdef __LITTLE_ENDIAN
77 #define wr_reg32(reg, data) __raw_writel(reg, data)
78 #define rd_reg32(reg) __raw_readl(reg)
80 #define wr_reg64(reg, data) __raw_writeq(reg, data)
81 #define rd_reg64(reg) __raw_readq(reg)
87 static inline void wr_reg64(u64 __iomem *reg, u64 data)
89 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
90 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull);
93 static inline u64 rd_reg64(u64 __iomem *reg)
95 return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
96 ((u64)rd_reg32((u32 __iomem *)reg + 1));
102 * Represents each entry in a JobR output ring
105 dma_addr_t desc;/* Pointer to completed descriptor */
106 u32 jrstatus; /* Status for completed descriptor */
110 * caam_perfmon - Performance Monitor/Secure Memory Status/
111 * CAAM Global Status/Component Version IDs
113 * Spans f00-fff wherever instantiated
116 /* Number of DECOs */
117 #define CHA_NUM_DECONUM_SHIFT 56
118 #define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
120 struct caam_perfmon {
121 /* Performance Monitor Registers f00-f9f */
122 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
123 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
124 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
125 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
126 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
127 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
128 u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */
131 /* CAAM Hardware Instantiation Parameters fa0-fbf */
132 u64 cha_rev; /* CRNR - CHA Revision Number */
133 #define CTPR_QI_SHIFT 57
134 #define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT)
135 u64 comp_parms; /* CTPR - Compile Parameters Register */
138 /* CAAM Global Status fc0-fdf */
139 u64 faultaddr; /* FAR - Fault Address */
140 u32 faultliodn; /* FALR - Fault Address LIODN */
141 u32 faultdetail; /* FADR - Fault Addr Detail */
143 u32 status; /* CSTA - CAAM Status */
146 /* Component Instantiation Parameters fe0-fff */
147 u32 rtic_id; /* RVID - RTIC Version ID */
148 u32 ccb_id; /* CCBVID - CCB Version ID */
149 u64 cha_id; /* CHAVID - CHA Version ID */
150 u64 cha_num; /* CHANUM - CHA Number */
151 u64 caam_id; /* CAAMVID - CAAM Version ID */
154 /* LIODN programming for DMA configuration */
155 #define MSTRID_LOCK_LIODN 0x80000000
156 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
158 #define MSTRID_LIODN_MASK 0x0fff
160 u32 liodn_ms; /* lock and make-trusted control bits */
161 u32 liodn_ls; /* LIODN for non-sequence and seq access */
164 /* Partition ID for DMA configuration */
167 u32 pidr; /* partition ID, DECO */
170 /* RNGB test mode (replicated twice in some configurations) */
171 /* Padded out to 0x100 */
173 u32 mode; /* RTSTMODEx - Test mode */
175 u32 reset; /* RTSTRESETx - Test reset control */
177 u32 status; /* RTSTSSTATUSx - Test status */
179 u32 errstat; /* RTSTERRSTATx - Test error status */
181 u32 errctl; /* RTSTERRCTLx - Test error control */
183 u32 entropy; /* RTSTENTROPYx - Test entropy */
185 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
187 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
189 u32 verifdata; /* RTSTVERIFDx - Test verification data */
191 u32 xkey; /* RTSTXKEYx - Test XKEY */
193 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
195 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
197 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
199 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
203 /* RNG4 TRNG test registers */
205 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
206 u32 rtmctl; /* misc. control register */
207 u32 rtscmisc; /* statistical check misc. register */
208 u32 rtpkrrng; /* poker range register */
210 u32 rtpkrmax; /* PRGM=1: poker max. limit register */
211 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
213 #define RTSDCTL_ENT_DLY_SHIFT 16
214 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
215 u32 rtsdctl; /* seed control register */
217 u32 rtsblim; /* PRGM=1: sparse bit limit register */
218 u32 rttotsam; /* PRGM=0: total samples register */
220 u32 rtfrqmin; /* frequency count min. limit register */
222 u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
223 u32 rtfrqcnt; /* PRGM=0: freq. count register */
229 * caam_ctrl - basic core configuration
230 * starts base + 0x0000 padded out to 0x1000
233 #define KEK_KEY_SIZE 8
234 #define TKEK_KEY_SIZE 8
235 #define TDSK_KEY_SIZE 8
237 #define DECO_RESET 1 /* Use with DECO reset/availability regs */
238 #define DECO_RESET_0 (DECO_RESET << 0)
239 #define DECO_RESET_1 (DECO_RESET << 1)
240 #define DECO_RESET_2 (DECO_RESET << 2)
241 #define DECO_RESET_3 (DECO_RESET << 3)
242 #define DECO_RESET_4 (DECO_RESET << 4)
245 /* Basic Configuration Section 000-01f */
248 u32 mcr; /* MCFG Master Config Register */
251 /* Bus Access Configuration Section 010-11f */
253 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
255 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
257 u32 deco_rq; /* DECORR - DECO Request */
258 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
261 /* DECO Availability/Reset Section 120-3ff */
262 u32 deco_avail; /* DAR - DECO availability */
263 u32 deco_reset; /* DRR - DECO reset */
266 /* Key Encryption/Decryption Configuration 400-5ff */
267 /* Read/Writable only while in Non-secure mode */
268 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
269 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
270 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
272 u64 sknonce; /* SKNR - Secure Key Nonce */
275 /* RNG Test/Verification/Debug Access 600-7ff */
276 /* (Useful in Test/Debug modes only...) */
278 struct rngtst rtst[2];
279 struct rng4tst r4tst[2];
284 /* Performance Monitor f00-fff */
285 struct caam_perfmon perfmon;
289 * Controller master config register defs
291 #define MCFGR_SWRESET 0x80000000 /* software reset */
292 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
293 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
294 #define MCFGR_DMA_RESET 0x10000000
295 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
297 /* AXI read cache control */
298 #define MCFGR_ARCACHE_SHIFT 12
299 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
301 /* AXI write cache control */
302 #define MCFGR_AWCACHE_SHIFT 8
303 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
305 /* AXI pipeline depth */
306 #define MCFGR_AXIPIPE_SHIFT 4
307 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
309 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
310 #define MCFGR_BURST_64 0x00000001 /* Max burst size */
313 * caam_job_ring - direct job ring setup
314 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
315 * Padded out to 0x1000
317 struct caam_job_ring {
319 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
321 u32 inpring_size; /* IRSx - Input ring size */
323 u32 inpring_avail; /* IRSAx - Input ring room remaining */
325 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
328 u64 outring_base; /* ORBAx - Output status ring base addr */
330 u32 outring_size; /* ORSx - Output ring size */
332 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
334 u32 outring_used; /* ORSFx - Output ring slots full */
336 /* Status/Configuration */
338 u32 jroutstatus; /* JRSTAx - JobR output status */
340 u32 jrintstatus; /* JRINTx - JobR interrupt status */
341 u32 rconfig_hi; /* JRxCFG - Ring configuration */
344 /* Indices. CAAM maintains as "heads" of each queue */
346 u32 inp_rdidx; /* IRRIx - Input ring read index */
348 u32 out_wtidx; /* ORWIx - Output ring write index */
350 /* Command/control */
352 u32 jrcommand; /* JRCRx - JobR command */
356 /* Performance Monitor f00-fff */
357 struct caam_perfmon perfmon;
360 #define JR_RINGSIZE_MASK 0x03ff
362 * jrstatus - Job Ring Output Status
363 * All values in lo word
364 * Also note, same values written out as status through QI
365 * in the command/status field of a frame descriptor
367 #define JRSTA_SSRC_SHIFT 28
368 #define JRSTA_SSRC_MASK 0xf0000000
370 #define JRSTA_SSRC_NONE 0x00000000
371 #define JRSTA_SSRC_CCB_ERROR 0x20000000
372 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
373 #define JRSTA_SSRC_DECO 0x40000000
374 #define JRSTA_SSRC_JRERROR 0x60000000
375 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
377 #define JRSTA_DECOERR_JUMP 0x08000000
378 #define JRSTA_DECOERR_INDEX_SHIFT 8
379 #define JRSTA_DECOERR_INDEX_MASK 0xff00
380 #define JRSTA_DECOERR_ERROR_MASK 0x00ff
382 #define JRSTA_DECOERR_NONE 0x00
383 #define JRSTA_DECOERR_LINKLEN 0x01
384 #define JRSTA_DECOERR_LINKPTR 0x02
385 #define JRSTA_DECOERR_JRCTRL 0x03
386 #define JRSTA_DECOERR_DESCCMD 0x04
387 #define JRSTA_DECOERR_ORDER 0x05
388 #define JRSTA_DECOERR_KEYCMD 0x06
389 #define JRSTA_DECOERR_LOADCMD 0x07
390 #define JRSTA_DECOERR_STORECMD 0x08
391 #define JRSTA_DECOERR_OPCMD 0x09
392 #define JRSTA_DECOERR_FIFOLDCMD 0x0a
393 #define JRSTA_DECOERR_FIFOSTCMD 0x0b
394 #define JRSTA_DECOERR_MOVECMD 0x0c
395 #define JRSTA_DECOERR_JUMPCMD 0x0d
396 #define JRSTA_DECOERR_MATHCMD 0x0e
397 #define JRSTA_DECOERR_SHASHCMD 0x0f
398 #define JRSTA_DECOERR_SEQCMD 0x10
399 #define JRSTA_DECOERR_DECOINTERNAL 0x11
400 #define JRSTA_DECOERR_SHDESCHDR 0x12
401 #define JRSTA_DECOERR_HDRLEN 0x13
402 #define JRSTA_DECOERR_BURSTER 0x14
403 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
404 #define JRSTA_DECOERR_DMA 0x16
405 #define JRSTA_DECOERR_BURSTFIFO 0x17
406 #define JRSTA_DECOERR_JRRESET 0x1a
407 #define JRSTA_DECOERR_JOBFAIL 0x1b
408 #define JRSTA_DECOERR_DNRERR 0x80
409 #define JRSTA_DECOERR_UNDEFPCL 0x81
410 #define JRSTA_DECOERR_PDBERR 0x82
411 #define JRSTA_DECOERR_ANRPLY_LATE 0x83
412 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
413 #define JRSTA_DECOERR_SEQOVF 0x85
414 #define JRSTA_DECOERR_INVSIGN 0x86
415 #define JRSTA_DECOERR_DSASIGN 0x87
417 #define JRSTA_CCBERR_JUMP 0x08000000
418 #define JRSTA_CCBERR_INDEX_MASK 0xff00
419 #define JRSTA_CCBERR_INDEX_SHIFT 8
420 #define JRSTA_CCBERR_CHAID_MASK 0x00f0
421 #define JRSTA_CCBERR_CHAID_SHIFT 4
422 #define JRSTA_CCBERR_ERRID_MASK 0x000f
424 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
425 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
426 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
427 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
428 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
429 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
430 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
431 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
432 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
434 #define JRSTA_CCBERR_ERRID_NONE 0x00
435 #define JRSTA_CCBERR_ERRID_MODE 0x01
436 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02
437 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
438 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
439 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
440 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
441 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
442 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
443 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
444 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
445 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
446 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
447 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f
449 #define JRINT_ERR_INDEX_MASK 0x3fff0000
450 #define JRINT_ERR_INDEX_SHIFT 16
451 #define JRINT_ERR_TYPE_MASK 0xf00
452 #define JRINT_ERR_TYPE_SHIFT 8
453 #define JRINT_ERR_HALT_MASK 0xc
454 #define JRINT_ERR_HALT_SHIFT 2
455 #define JRINT_ERR_HALT_INPROGRESS 0x4
456 #define JRINT_ERR_HALT_COMPLETE 0x8
457 #define JRINT_JR_ERROR 0x02
458 #define JRINT_JR_INT 0x01
460 #define JRINT_ERR_TYPE_WRITE 1
461 #define JRINT_ERR_TYPE_BAD_INPADDR 3
462 #define JRINT_ERR_TYPE_BAD_OUTADDR 4
463 #define JRINT_ERR_TYPE_INV_INPWRT 5
464 #define JRINT_ERR_TYPE_INV_OUTWRT 6
465 #define JRINT_ERR_TYPE_RESET 7
466 #define JRINT_ERR_TYPE_REMOVE_OFL 8
467 #define JRINT_ERR_TYPE_ADD_OFL 9
469 #define JRCFG_SOE 0x04
470 #define JRCFG_ICEN 0x02
471 #define JRCFG_IMSK 0x01
472 #define JRCFG_ICDCT_SHIFT 8
473 #define JRCFG_ICTT_SHIFT 16
475 #define JRCR_RESET 0x01
478 * caam_assurance - Assurance Controller View
479 * base + 0x6000 padded out to 0x1000
482 struct rtic_element {
489 struct rtic_element element[2];
492 struct rtic_memhash {
497 struct caam_assurance {
498 /* Status/Command/Watchdog */
500 u32 status; /* RSTA - Status */
502 u32 cmd; /* RCMD - Command */
504 u32 ctrl; /* RCTL - Control */
506 u32 throttle; /* RTHR - Throttle */
508 u64 watchdog; /* RWDOG - Watchdog Timer */
510 u32 rend; /* REND - Endian corrections */
513 /* Block access/configuration @ 100/110/120/130 */
514 struct rtic_block memblk[4]; /* Memory Blocks A-D */
517 /* Block hashes @ 200/300/400/500 */
518 struct rtic_memhash hash[4]; /* Block hash values A-D */
523 * caam_queue_if - QI configuration and control
524 * starts base + 0x7000, padded out to 0x1000 long
527 struct caam_queue_if {
528 u32 qi_control_hi; /* QICTL - QI Control */
531 u32 qi_status; /* QISTA - QI Status */
532 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
534 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
539 /* QI control bits - low word */
540 #define QICTL_DQEN 0x01 /* Enable frame pop */
541 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
542 #define QICTL_SOE 0x04 /* Stop on error */
544 /* QI control bits - high word */
545 #define QICTL_MBSI 0x01
546 #define QICTL_MHWSI 0x02
547 #define QICTL_MWSI 0x04
548 #define QICTL_MDWSI 0x08
549 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
550 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
551 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
552 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
553 #define QICTL_MBSO 0x0100
554 #define QICTL_MHWSO 0x0200
555 #define QICTL_MWSO 0x0400
556 #define QICTL_MDWSO 0x0800
557 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
558 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
559 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
560 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
561 #define QICTL_DMBS 0x010000
562 #define QICTL_EPO 0x020000
565 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
566 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
567 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
568 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
569 #define QISTA_BTSERR 0x10 /* Buffer Undersize */
570 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
571 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
573 /* deco_sg_table - DECO view of scatter/gather table */
574 struct deco_sg_table {
575 u64 addr; /* Segment Address */
576 u32 elen; /* E, F bits + 30-bit length */
577 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
581 * caam_deco - descriptor controller - CHA cluster block
583 * Only accessible when direct DECO access is turned on
584 * (done in DECORR, via MID programmed in DECOxMID
586 * 5 typical, base + 0x8000/9000/a000/b000
587 * Padded out to 0x1000 long
591 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
593 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
594 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
595 u32 cls1_datasize_lo;
597 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
599 u32 cha_ctrl; /* CCTLR - CHA control */
601 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
603 u32 clr_written; /* CxCWR - Clear-Written */
604 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
607 u32 aad_size; /* CxAADSZR - Current AAD Size */
609 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
611 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
613 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
615 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
617 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
619 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
621 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
623 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
625 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
626 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
627 u32 cls2_datasize_lo;
629 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
631 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
633 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
635 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
638 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
640 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
642 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
644 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
645 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
648 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
649 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
651 u64 math[4]; /* DxMTH - Math register */
653 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
655 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
657 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
662 * Current top-level view of memory map is:
664 * 0x0000 - 0x0fff - CAAM Top-Level Control
665 * 0x1000 - 0x1fff - Job Ring 0
666 * 0x2000 - 0x2fff - Job Ring 1
667 * 0x3000 - 0x3fff - Job Ring 2
668 * 0x4000 - 0x4fff - Job Ring 3
669 * 0x5000 - 0x5fff - (unused)
670 * 0x6000 - 0x6fff - Assurance Controller
671 * 0x7000 - 0x7fff - Queue Interface
672 * 0x8000 - 0x8fff - DECO-CCB 0
673 * 0x9000 - 0x9fff - DECO-CCB 1
674 * 0xa000 - 0xafff - DECO-CCB 2
675 * 0xb000 - 0xbfff - DECO-CCB 3
676 * 0xc000 - 0xcfff - DECO-CCB 4
678 * caam_full describes the full register view of CAAM if useful,
679 * although many configurations may choose to implement parts of
680 * the register map separately, in differing privilege regions
683 struct caam_ctrl __iomem ctrl;
684 struct caam_job_ring jr[4];
686 struct caam_assurance assure;
687 struct caam_queue_if qi;