2 * caam - Freescale FSL CAAM support for crypto API
4 * Copyright 2008-2011 Freescale Semiconductor, Inc.
6 * Based on talitos crypto API driver.
8 * relationship of job descriptors to shared descriptors (SteveC Dec 10 2008):
10 * --------------- ---------------
11 * | JobDesc #1 |-------------------->| ShareDesc |
12 * | *(packet 1) | | (PDB) |
13 * --------------- |------------->| (hashKey) |
15 * . | |-------->| (operation) |
16 * --------------- | | ---------------
17 * | JobDesc #2 |------| |
23 * | JobDesc #3 |------------
27 * The SharedDesc never changes for a connection unless rekeyed, but
28 * each packet will likely be in a different place. So all we need
29 * to know to process the packet is where the input is, where the
30 * output goes, and what context we want to process with. Context is
31 * in the SharedDesc, packet references in the JobDesc.
33 * So, a job desc looks like:
35 * ---------------------
37 * | ShareDesc Pointer |
44 * ---------------------
51 #include "desc_constr.h"
54 #include "sg_sw_sec4.h"
60 #define CAAM_CRA_PRIORITY 3000
61 /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
62 #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
63 SHA512_DIGEST_SIZE * 2)
64 /* max IV is max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
65 #define CAAM_MAX_IV_LENGTH 16
67 /* length of descriptors text */
68 #define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
70 #define DESC_AEAD_BASE (4 * CAAM_CMD_SZ)
71 #define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 16 * CAAM_CMD_SZ)
72 #define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 21 * CAAM_CMD_SZ)
73 #define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
75 #define DESC_ABLKCIPHER_BASE (3 * CAAM_CMD_SZ)
76 #define DESC_ABLKCIPHER_ENC_LEN (DESC_ABLKCIPHER_BASE + \
78 #define DESC_ABLKCIPHER_DEC_LEN (DESC_ABLKCIPHER_BASE + \
81 #define DESC_MAX_USED_BYTES (DESC_AEAD_GIVENC_LEN + \
83 #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
86 /* for print_hex_dumps with line references */
87 #define xstr(s) str(s)
89 #define debug(format, arg...) printk(format, arg)
91 #define debug(format, arg...)
94 /* Set DK bit in class 1 operation if shared */
95 static inline void append_dec_op1(u32 *desc, u32 type)
97 u32 *jump_cmd, *uncond_jump_cmd;
99 jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
100 append_operation(desc, type | OP_ALG_AS_INITFINAL |
102 uncond_jump_cmd = append_jump(desc, JUMP_TEST_ALL);
103 set_jump_tgt_here(desc, jump_cmd);
104 append_operation(desc, type | OP_ALG_AS_INITFINAL |
105 OP_ALG_DECRYPT | OP_ALG_AAI_DK);
106 set_jump_tgt_here(desc, uncond_jump_cmd);
110 * Wait for completion of class 1 key loading before allowing
113 static inline void append_dec_shr_done(u32 *desc)
117 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TEST_ALL);
118 set_jump_tgt_here(desc, jump_cmd);
119 append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
123 * For aead functions, read payload and write payload,
124 * both of which are specified in req->src and req->dst
126 static inline void aead_append_src_dst(u32 *desc, u32 msg_type)
128 append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
129 KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH);
130 append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
134 * For aead encrypt and decrypt, read iv for both classes
136 static inline void aead_append_ld_iv(u32 *desc, int ivsize)
138 append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
139 LDST_CLASS_1_CCB | ivsize);
140 append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize);
144 * For ablkcipher encrypt and decrypt, read from req->src and
147 static inline void ablkcipher_append_src_dst(u32 *desc)
149 append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
150 append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
151 append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 |
152 KEY_VLF | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
153 append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
157 * If all data, including src (with assoc and iv) or dst (with iv only) are
160 #define GIV_SRC_CONTIG 1
161 #define GIV_DST_CONTIG (1 << 1)
164 * per-session context
167 struct device *jrdev;
168 u32 sh_desc_enc[DESC_MAX_USED_LEN];
169 u32 sh_desc_dec[DESC_MAX_USED_LEN];
170 u32 sh_desc_givenc[DESC_MAX_USED_LEN];
171 dma_addr_t sh_desc_enc_dma;
172 dma_addr_t sh_desc_dec_dma;
173 dma_addr_t sh_desc_givenc_dma;
177 u8 key[CAAM_MAX_KEY_SIZE];
179 unsigned int enckeylen;
180 unsigned int split_key_len;
181 unsigned int split_key_pad_len;
182 unsigned int authsize;
185 static void append_key_aead(u32 *desc, struct caam_ctx *ctx,
188 if (keys_fit_inline) {
189 append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
190 ctx->split_key_len, CLASS_2 |
191 KEY_DEST_MDHA_SPLIT | KEY_ENC);
192 append_key_as_imm(desc, (void *)ctx->key +
193 ctx->split_key_pad_len, ctx->enckeylen,
194 ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
196 append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
197 KEY_DEST_MDHA_SPLIT | KEY_ENC);
198 append_key(desc, ctx->key_dma + ctx->split_key_pad_len,
199 ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
203 static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx,
208 init_sh_desc(desc, HDR_SHARE_WAIT);
210 /* Skip if already shared */
211 key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
214 append_key_aead(desc, ctx, keys_fit_inline);
216 set_jump_tgt_here(desc, key_jump_cmd);
218 /* Propagate errors from shared to job descriptor */
219 append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
222 static int aead_set_sh_desc(struct crypto_aead *aead)
224 struct aead_tfm *tfm = &aead->base.crt_aead;
225 struct caam_ctx *ctx = crypto_aead_ctx(aead);
226 struct device *jrdev = ctx->jrdev;
227 bool keys_fit_inline = 0;
228 u32 *key_jump_cmd, *jump_cmd;
232 if (!ctx->enckeylen || !ctx->authsize)
236 * Job Descriptor and Shared Descriptors
237 * must all fit into the 64-word Descriptor h/w Buffer
239 if (DESC_AEAD_ENC_LEN + DESC_JOB_IO_LEN +
240 ctx->split_key_pad_len + ctx->enckeylen <=
244 /* aead_encrypt shared descriptor */
245 desc = ctx->sh_desc_enc;
247 init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
249 /* Class 2 operation */
250 append_operation(desc, ctx->class2_alg_type |
251 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
253 /* cryptlen = seqoutlen - authsize */
254 append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
256 /* assoclen + cryptlen = seqinlen - ivsize */
257 append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize);
259 /* assoclen + cryptlen = (assoclen + cryptlen) - cryptlen */
260 append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ);
262 /* read assoc before reading payload */
263 append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
265 aead_append_ld_iv(desc, tfm->ivsize);
267 /* Class 1 operation */
268 append_operation(desc, ctx->class1_alg_type |
269 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
271 /* Read and write cryptlen bytes */
272 append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
273 append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
274 aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
277 append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
278 LDST_SRCDST_BYTE_CONTEXT);
280 ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
283 if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
284 dev_err(jrdev, "unable to map shared descriptor\n");
288 print_hex_dump(KERN_ERR, "aead enc shdesc@"xstr(__LINE__)": ",
289 DUMP_PREFIX_ADDRESS, 16, 4, desc,
290 desc_bytes(desc), 1);
294 * Job Descriptor and Shared Descriptors
295 * must all fit into the 64-word Descriptor h/w Buffer
297 if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN +
298 ctx->split_key_pad_len + ctx->enckeylen <=
302 desc = ctx->sh_desc_dec;
304 /* aead_decrypt shared descriptor */
305 init_sh_desc(desc, HDR_SHARE_WAIT);
307 /* Skip if already shared */
308 key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
311 append_key_aead(desc, ctx, keys_fit_inline);
313 /* Only propagate error immediately if shared */
314 jump_cmd = append_jump(desc, JUMP_TEST_ALL);
315 set_jump_tgt_here(desc, key_jump_cmd);
316 append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
317 set_jump_tgt_here(desc, jump_cmd);
319 /* Class 2 operation */
320 append_operation(desc, ctx->class2_alg_type |
321 OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
323 /* assoclen + cryptlen = seqinlen - ivsize */
324 append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
325 ctx->authsize + tfm->ivsize)
326 /* assoclen = (assoclen + cryptlen) - cryptlen */
327 append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
328 append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
330 /* read assoc before reading payload */
331 append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
334 aead_append_ld_iv(desc, tfm->ivsize);
336 append_dec_op1(desc, ctx->class1_alg_type);
338 /* Read and write cryptlen bytes */
339 append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
340 append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
341 aead_append_src_dst(desc, FIFOLD_TYPE_MSG);
344 append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
345 FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
346 append_dec_shr_done(desc);
348 ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
351 if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
352 dev_err(jrdev, "unable to map shared descriptor\n");
356 print_hex_dump(KERN_ERR, "aead dec shdesc@"xstr(__LINE__)": ",
357 DUMP_PREFIX_ADDRESS, 16, 4, desc,
358 desc_bytes(desc), 1);
362 * Job Descriptor and Shared Descriptors
363 * must all fit into the 64-word Descriptor h/w Buffer
365 if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN +
366 ctx->split_key_pad_len + ctx->enckeylen <=
370 /* aead_givencrypt shared descriptor */
371 desc = ctx->sh_desc_givenc;
373 init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
376 geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
377 NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
378 NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
379 append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
380 LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
381 append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
382 append_move(desc, MOVE_SRC_INFIFO |
383 MOVE_DEST_CLASS1CTX | (tfm->ivsize << MOVE_LEN_SHIFT));
384 append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
386 /* Copy IV to class 1 context */
387 append_move(desc, MOVE_SRC_CLASS1CTX |
388 MOVE_DEST_OUTFIFO | (tfm->ivsize << MOVE_LEN_SHIFT));
390 /* Return to encryption */
391 append_operation(desc, ctx->class2_alg_type |
392 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
394 /* ivsize + cryptlen = seqoutlen - authsize */
395 append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
397 /* assoclen = seqinlen - (ivsize + cryptlen) */
398 append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
400 /* read assoc before reading payload */
401 append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
404 /* Copy iv from class 1 ctx to class 2 fifo*/
405 moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 |
406 NFIFOENTRY_DTYPE_MSG | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
407 append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB |
408 LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
409 append_load_imm_u32(desc, tfm->ivsize, LDST_CLASS_2_CCB |
410 LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
412 /* Class 1 operation */
413 append_operation(desc, ctx->class1_alg_type |
414 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
416 /* Will write ivsize + cryptlen */
417 append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
419 /* Not need to reload iv */
420 append_seq_fifo_load(desc, tfm->ivsize,
423 /* Will read cryptlen */
424 append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
425 aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
428 append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
429 LDST_SRCDST_BYTE_CONTEXT);
431 ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
434 if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
435 dev_err(jrdev, "unable to map shared descriptor\n");
439 print_hex_dump(KERN_ERR, "aead givenc shdesc@"xstr(__LINE__)": ",
440 DUMP_PREFIX_ADDRESS, 16, 4, desc,
441 desc_bytes(desc), 1);
447 static int aead_setauthsize(struct crypto_aead *authenc,
448 unsigned int authsize)
450 struct caam_ctx *ctx = crypto_aead_ctx(authenc);
452 ctx->authsize = authsize;
453 aead_set_sh_desc(authenc);
458 static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in,
461 return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
462 ctx->split_key_pad_len, key_in, authkeylen,
466 static int aead_setkey(struct crypto_aead *aead,
467 const u8 *key, unsigned int keylen)
469 /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
470 static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
471 struct caam_ctx *ctx = crypto_aead_ctx(aead);
472 struct device *jrdev = ctx->jrdev;
473 struct rtattr *rta = (void *)key;
474 struct crypto_authenc_key_param *param;
475 unsigned int authkeylen;
476 unsigned int enckeylen;
479 param = RTA_DATA(rta);
480 enckeylen = be32_to_cpu(param->enckeylen);
482 key += RTA_ALIGN(rta->rta_len);
483 keylen -= RTA_ALIGN(rta->rta_len);
485 if (keylen < enckeylen)
488 authkeylen = keylen - enckeylen;
490 if (keylen > CAAM_MAX_KEY_SIZE)
493 /* Pick class 2 key length from algorithm submask */
494 ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
495 OP_ALG_ALGSEL_SHIFT] * 2;
496 ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
499 printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
500 keylen, enckeylen, authkeylen);
501 printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
502 ctx->split_key_len, ctx->split_key_pad_len);
503 print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
504 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
507 ret = gen_split_aead_key(ctx, key, authkeylen);
512 /* postpend encryption key to auth split key */
513 memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen);
515 ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
516 enckeylen, DMA_TO_DEVICE);
517 if (dma_mapping_error(jrdev, ctx->key_dma)) {
518 dev_err(jrdev, "unable to map key i/o memory\n");
522 print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
523 DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
524 ctx->split_key_pad_len + enckeylen, 1);
527 ctx->enckeylen = enckeylen;
529 ret = aead_set_sh_desc(aead);
531 dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len +
532 enckeylen, DMA_TO_DEVICE);
537 crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
541 static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
542 const u8 *key, unsigned int keylen)
544 struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
545 struct ablkcipher_tfm *tfm = &ablkcipher->base.crt_ablkcipher;
546 struct device *jrdev = ctx->jrdev;
548 u32 *key_jump_cmd, *jump_cmd;
552 print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ",
553 DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
556 memcpy(ctx->key, key, keylen);
557 ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
559 if (dma_mapping_error(jrdev, ctx->key_dma)) {
560 dev_err(jrdev, "unable to map key i/o memory\n");
563 ctx->enckeylen = keylen;
565 /* ablkcipher_encrypt shared descriptor */
566 desc = ctx->sh_desc_enc;
567 init_sh_desc(desc, HDR_SHARE_WAIT);
568 /* Skip if already shared */
569 key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
572 /* Load class1 key only */
573 append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
574 ctx->enckeylen, CLASS_1 |
577 set_jump_tgt_here(desc, key_jump_cmd);
579 /* Propagate errors from shared to job descriptor */
580 append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
583 append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
584 LDST_CLASS_1_CCB | tfm->ivsize);
587 append_operation(desc, ctx->class1_alg_type |
588 OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
590 /* Perform operation */
591 ablkcipher_append_src_dst(desc);
593 ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
596 if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
597 dev_err(jrdev, "unable to map shared descriptor\n");
601 print_hex_dump(KERN_ERR, "ablkcipher enc shdesc@"xstr(__LINE__)": ",
602 DUMP_PREFIX_ADDRESS, 16, 4, desc,
603 desc_bytes(desc), 1);
605 /* ablkcipher_decrypt shared descriptor */
606 desc = ctx->sh_desc_dec;
608 init_sh_desc(desc, HDR_SHARE_WAIT);
609 /* Skip if already shared */
610 key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
613 /* Load class1 key only */
614 append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
615 ctx->enckeylen, CLASS_1 |
618 /* For aead, only propagate error immediately if shared */
619 jump_cmd = append_jump(desc, JUMP_TEST_ALL);
620 set_jump_tgt_here(desc, key_jump_cmd);
621 append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
622 set_jump_tgt_here(desc, jump_cmd);
625 append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
626 LDST_CLASS_1_CCB | tfm->ivsize);
628 /* Choose operation */
629 append_dec_op1(desc, ctx->class1_alg_type);
631 /* Perform operation */
632 ablkcipher_append_src_dst(desc);
634 /* Wait for key to load before allowing propagating error */
635 append_dec_shr_done(desc);
637 ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
640 if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
641 dev_err(jrdev, "unable to map shared descriptor\n");
646 print_hex_dump(KERN_ERR, "ablkcipher dec shdesc@"xstr(__LINE__)": ",
647 DUMP_PREFIX_ADDRESS, 16, 4, desc,
648 desc_bytes(desc), 1);
655 * aead_edesc - s/w-extended aead descriptor
656 * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist
657 * @src_nents: number of segments in input scatterlist
658 * @dst_nents: number of segments in output scatterlist
659 * @iv_dma: dma address of iv for checking continuity and link table
660 * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
661 * @sec4_sg_bytes: length of dma mapped sec4_sg space
662 * @sec4_sg_dma: bus physical mapped address of h/w link table
663 * @hw_desc: the h/w job descriptor followed by any referenced link tables
671 dma_addr_t sec4_sg_dma;
672 struct sec4_sg_entry *sec4_sg;
677 * ablkcipher_edesc - s/w-extended ablkcipher descriptor
678 * @src_nents: number of segments in input scatterlist
679 * @dst_nents: number of segments in output scatterlist
680 * @iv_dma: dma address of iv for checking continuity and link table
681 * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
682 * @sec4_sg_bytes: length of dma mapped sec4_sg space
683 * @sec4_sg_dma: bus physical mapped address of h/w link table
684 * @hw_desc: the h/w job descriptor followed by any referenced link tables
686 struct ablkcipher_edesc {
691 dma_addr_t sec4_sg_dma;
692 struct sec4_sg_entry *sec4_sg;
696 static void caam_unmap(struct device *dev, struct scatterlist *src,
697 struct scatterlist *dst, int src_nents, int dst_nents,
698 dma_addr_t iv_dma, int ivsize, dma_addr_t sec4_sg_dma,
701 if (unlikely(dst != src)) {
702 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
703 dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
705 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
709 dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
711 dma_unmap_single(dev, sec4_sg_dma, sec4_sg_bytes,
715 static void aead_unmap(struct device *dev,
716 struct aead_edesc *edesc,
717 struct aead_request *req)
719 struct crypto_aead *aead = crypto_aead_reqtfm(req);
720 int ivsize = crypto_aead_ivsize(aead);
722 dma_unmap_sg(dev, req->assoc, edesc->assoc_nents, DMA_TO_DEVICE);
724 caam_unmap(dev, req->src, req->dst,
725 edesc->src_nents, edesc->dst_nents,
726 edesc->iv_dma, ivsize, edesc->sec4_sg_dma,
727 edesc->sec4_sg_bytes);
730 static void ablkcipher_unmap(struct device *dev,
731 struct ablkcipher_edesc *edesc,
732 struct ablkcipher_request *req)
734 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
735 int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
737 caam_unmap(dev, req->src, req->dst,
738 edesc->src_nents, edesc->dst_nents,
739 edesc->iv_dma, ivsize, edesc->sec4_sg_dma,
740 edesc->sec4_sg_bytes);
743 static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
746 struct aead_request *req = context;
747 struct aead_edesc *edesc;
749 struct crypto_aead *aead = crypto_aead_reqtfm(req);
750 struct caam_ctx *ctx = crypto_aead_ctx(aead);
751 int ivsize = crypto_aead_ivsize(aead);
753 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
756 edesc = (struct aead_edesc *)((char *)desc -
757 offsetof(struct aead_edesc, hw_desc));
760 char tmp[CAAM_ERROR_STR_MAX];
762 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
765 aead_unmap(jrdev, edesc, req);
768 print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
769 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
771 print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
772 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src) - ivsize,
773 edesc->src_nents ? 100 : ivsize, 1);
774 print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
775 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
776 edesc->src_nents ? 100 : req->cryptlen +
777 ctx->authsize + 4, 1);
782 aead_request_complete(req, err);
785 static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
788 struct aead_request *req = context;
789 struct aead_edesc *edesc;
791 struct crypto_aead *aead = crypto_aead_reqtfm(req);
792 struct caam_ctx *ctx = crypto_aead_ctx(aead);
793 int ivsize = crypto_aead_ivsize(aead);
795 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
798 edesc = (struct aead_edesc *)((char *)desc -
799 offsetof(struct aead_edesc, hw_desc));
802 print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
803 DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
805 print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
806 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst),
811 char tmp[CAAM_ERROR_STR_MAX];
813 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
816 aead_unmap(jrdev, edesc, req);
819 * verify hw auth check passed else return -EBADMSG
821 if ((err & JRSTA_CCBERR_ERRID_MASK) == JRSTA_CCBERR_ERRID_ICVCHK)
825 print_hex_dump(KERN_ERR, "iphdrout@"xstr(__LINE__)": ",
826 DUMP_PREFIX_ADDRESS, 16, 4,
827 ((char *)sg_virt(req->assoc) - sizeof(struct iphdr)),
828 sizeof(struct iphdr) + req->assoclen +
829 ((req->cryptlen > 1500) ? 1500 : req->cryptlen) +
830 ctx->authsize + 36, 1);
831 if (!err && edesc->sec4_sg_bytes) {
832 struct scatterlist *sg = sg_last(req->src, edesc->src_nents);
833 print_hex_dump(KERN_ERR, "sglastout@"xstr(__LINE__)": ",
834 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg),
835 sg->length + ctx->authsize + 16, 1);
841 aead_request_complete(req, err);
844 static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
847 struct ablkcipher_request *req = context;
848 struct ablkcipher_edesc *edesc;
850 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
851 int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
853 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
856 edesc = (struct ablkcipher_edesc *)((char *)desc -
857 offsetof(struct ablkcipher_edesc, hw_desc));
860 char tmp[CAAM_ERROR_STR_MAX];
862 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
866 print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
867 DUMP_PREFIX_ADDRESS, 16, 4, req->info,
868 edesc->src_nents > 1 ? 100 : ivsize, 1);
869 print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
870 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
871 edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
874 ablkcipher_unmap(jrdev, edesc, req);
877 ablkcipher_request_complete(req, err);
880 static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
883 struct ablkcipher_request *req = context;
884 struct ablkcipher_edesc *edesc;
886 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
887 int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
889 dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
892 edesc = (struct ablkcipher_edesc *)((char *)desc -
893 offsetof(struct ablkcipher_edesc, hw_desc));
895 char tmp[CAAM_ERROR_STR_MAX];
897 dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
901 print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ",
902 DUMP_PREFIX_ADDRESS, 16, 4, req->info,
904 print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ",
905 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
906 edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
909 ablkcipher_unmap(jrdev, edesc, req);
912 ablkcipher_request_complete(req, err);
916 * Fill in aead job descriptor
918 static void init_aead_job(u32 *sh_desc, dma_addr_t ptr,
919 struct aead_edesc *edesc,
920 struct aead_request *req,
921 bool all_contig, bool encrypt)
923 struct crypto_aead *aead = crypto_aead_reqtfm(req);
924 struct caam_ctx *ctx = crypto_aead_ctx(aead);
925 int ivsize = crypto_aead_ivsize(aead);
926 int authsize = ctx->authsize;
927 u32 *desc = edesc->hw_desc;
928 u32 out_options = 0, in_options;
929 dma_addr_t dst_dma, src_dma;
930 int len, sec4_sg_index = 0;
933 debug("assoclen %d cryptlen %d authsize %d\n",
934 req->assoclen, req->cryptlen, authsize);
935 print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
936 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
938 print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
939 DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
940 edesc->src_nents ? 100 : ivsize, 1);
941 print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ",
942 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
943 edesc->src_nents ? 100 : req->cryptlen, 1);
944 print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ",
945 DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
946 desc_bytes(sh_desc), 1);
949 len = desc_len(sh_desc);
950 init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
953 src_dma = sg_dma_address(req->assoc);
956 src_dma = edesc->sec4_sg_dma;
957 sec4_sg_index += (edesc->assoc_nents ? : 1) + 1 +
958 (edesc->src_nents ? : 1);
959 in_options = LDST_SGF;
962 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
963 req->cryptlen - authsize, in_options);
965 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
966 req->cryptlen, in_options);
968 if (likely(req->src == req->dst)) {
970 dst_dma = sg_dma_address(req->src);
972 dst_dma = src_dma + sizeof(struct sec4_sg_entry) *
973 ((edesc->assoc_nents ? : 1) + 1);
974 out_options = LDST_SGF;
977 if (!edesc->dst_nents) {
978 dst_dma = sg_dma_address(req->dst);
980 dst_dma = edesc->sec4_sg_dma +
982 sizeof(struct sec4_sg_entry);
983 out_options = LDST_SGF;
987 append_seq_out_ptr(desc, dst_dma, req->cryptlen, out_options);
989 append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize,
994 * Fill in aead givencrypt job descriptor
996 static void init_aead_giv_job(u32 *sh_desc, dma_addr_t ptr,
997 struct aead_edesc *edesc,
998 struct aead_request *req,
1001 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1002 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1003 int ivsize = crypto_aead_ivsize(aead);
1004 int authsize = ctx->authsize;
1005 u32 *desc = edesc->hw_desc;
1006 u32 out_options = 0, in_options;
1007 dma_addr_t dst_dma, src_dma;
1008 int len, sec4_sg_index = 0;
1011 debug("assoclen %d cryptlen %d authsize %d\n",
1012 req->assoclen, req->cryptlen, authsize);
1013 print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ",
1014 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
1016 print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
1017 DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1);
1018 print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ",
1019 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
1020 edesc->src_nents > 1 ? 100 : req->cryptlen, 1);
1021 print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ",
1022 DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
1023 desc_bytes(sh_desc), 1);
1026 len = desc_len(sh_desc);
1027 init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
1029 if (contig & GIV_SRC_CONTIG) {
1030 src_dma = sg_dma_address(req->assoc);
1033 src_dma = edesc->sec4_sg_dma;
1034 sec4_sg_index += edesc->assoc_nents + 1 + edesc->src_nents;
1035 in_options = LDST_SGF;
1037 append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize +
1038 req->cryptlen - authsize, in_options);
1040 if (contig & GIV_DST_CONTIG) {
1041 dst_dma = edesc->iv_dma;
1043 if (likely(req->src == req->dst)) {
1044 dst_dma = src_dma + sizeof(struct sec4_sg_entry) *
1046 out_options = LDST_SGF;
1048 dst_dma = edesc->sec4_sg_dma +
1050 sizeof(struct sec4_sg_entry);
1051 out_options = LDST_SGF;
1055 append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen, out_options);
1059 * Fill in ablkcipher job descriptor
1061 static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr,
1062 struct ablkcipher_edesc *edesc,
1063 struct ablkcipher_request *req,
1066 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
1067 int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
1068 u32 *desc = edesc->hw_desc;
1069 u32 out_options = 0, in_options;
1070 dma_addr_t dst_dma, src_dma;
1071 int len, sec4_sg_index = 0;
1074 print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ",
1075 DUMP_PREFIX_ADDRESS, 16, 4, req->info,
1077 print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ",
1078 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
1079 edesc->src_nents ? 100 : req->nbytes, 1);
1082 len = desc_len(sh_desc);
1083 init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
1086 src_dma = edesc->iv_dma;
1089 src_dma = edesc->sec4_sg_dma;
1090 sec4_sg_index += (iv_contig ? 0 : 1) + edesc->src_nents;
1091 in_options = LDST_SGF;
1093 append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options);
1095 if (likely(req->src == req->dst)) {
1096 if (!edesc->src_nents && iv_contig) {
1097 dst_dma = sg_dma_address(req->src);
1099 dst_dma = edesc->sec4_sg_dma +
1100 sizeof(struct sec4_sg_entry);
1101 out_options = LDST_SGF;
1104 if (!edesc->dst_nents) {
1105 dst_dma = sg_dma_address(req->dst);
1107 dst_dma = edesc->sec4_sg_dma +
1108 sec4_sg_index * sizeof(struct sec4_sg_entry);
1109 out_options = LDST_SGF;
1112 append_seq_out_ptr(desc, dst_dma, req->nbytes, out_options);
1116 * allocate and map the aead extended descriptor
1118 static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
1119 int desc_bytes, bool *all_contig_ptr)
1121 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1122 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1123 struct device *jrdev = ctx->jrdev;
1124 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1125 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1126 int assoc_nents, src_nents, dst_nents = 0;
1127 struct aead_edesc *edesc;
1128 dma_addr_t iv_dma = 0;
1130 bool all_contig = true;
1131 int ivsize = crypto_aead_ivsize(aead);
1132 int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
1134 assoc_nents = sg_count(req->assoc, req->assoclen);
1135 src_nents = sg_count(req->src, req->cryptlen);
1137 if (unlikely(req->dst != req->src))
1138 dst_nents = sg_count(req->dst, req->cryptlen);
1140 sgc = dma_map_sg(jrdev, req->assoc, assoc_nents ? : 1,
1142 if (likely(req->src == req->dst)) {
1143 sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
1146 sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
1148 sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
1152 /* Check if data are contiguous */
1153 iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE);
1154 if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
1155 iv_dma || src_nents || iv_dma + ivsize !=
1156 sg_dma_address(req->src)) {
1158 assoc_nents = assoc_nents ? : 1;
1159 src_nents = src_nents ? : 1;
1160 sec4_sg_len = assoc_nents + 1 + src_nents;
1162 sec4_sg_len += dst_nents;
1164 sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
1166 /* allocate space for base edesc and hw desc commands, link tables */
1167 edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
1168 sec4_sg_bytes, GFP_DMA | flags);
1170 dev_err(jrdev, "could not allocate extended descriptor\n");
1171 return ERR_PTR(-ENOMEM);
1174 edesc->assoc_nents = assoc_nents;
1175 edesc->src_nents = src_nents;
1176 edesc->dst_nents = dst_nents;
1177 edesc->iv_dma = iv_dma;
1178 edesc->sec4_sg_bytes = sec4_sg_bytes;
1179 edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
1181 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1182 sec4_sg_bytes, DMA_TO_DEVICE);
1183 *all_contig_ptr = all_contig;
1187 sg_to_sec4_sg(req->assoc,
1188 (assoc_nents ? : 1),
1191 sec4_sg_index += assoc_nents ? : 1;
1192 dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
1195 sg_to_sec4_sg_last(req->src,
1199 sec4_sg_index += src_nents ? : 1;
1202 sg_to_sec4_sg_last(req->dst, dst_nents,
1203 edesc->sec4_sg + sec4_sg_index, 0);
1209 static int aead_encrypt(struct aead_request *req)
1211 struct aead_edesc *edesc;
1212 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1213 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1214 struct device *jrdev = ctx->jrdev;
1219 req->cryptlen += ctx->authsize;
1221 /* allocate extended descriptor */
1222 edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
1223 CAAM_CMD_SZ, &all_contig);
1225 return PTR_ERR(edesc);
1227 /* Create and submit job descriptor */
1228 init_aead_job(ctx->sh_desc_enc, ctx->sh_desc_enc_dma, edesc, req,
1231 print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
1232 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1233 desc_bytes(edesc->hw_desc), 1);
1236 desc = edesc->hw_desc;
1237 ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
1241 aead_unmap(jrdev, edesc, req);
1248 static int aead_decrypt(struct aead_request *req)
1250 struct aead_edesc *edesc;
1251 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1252 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1253 struct device *jrdev = ctx->jrdev;
1258 /* allocate extended descriptor */
1259 edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
1260 CAAM_CMD_SZ, &all_contig);
1262 return PTR_ERR(edesc);
1265 print_hex_dump(KERN_ERR, "dec src@"xstr(__LINE__)": ",
1266 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
1270 /* Create and submit job descriptor*/
1271 init_aead_job(ctx->sh_desc_dec,
1272 ctx->sh_desc_dec_dma, edesc, req, all_contig, false);
1274 print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
1275 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1276 desc_bytes(edesc->hw_desc), 1);
1279 desc = edesc->hw_desc;
1280 ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
1284 aead_unmap(jrdev, edesc, req);
1292 * allocate and map the aead extended descriptor for aead givencrypt
1294 static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
1295 *greq, int desc_bytes,
1298 struct aead_request *req = &greq->areq;
1299 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1300 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1301 struct device *jrdev = ctx->jrdev;
1302 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1303 CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1304 int assoc_nents, src_nents, dst_nents = 0;
1305 struct aead_edesc *edesc;
1306 dma_addr_t iv_dma = 0;
1308 u32 contig = GIV_SRC_CONTIG | GIV_DST_CONTIG;
1309 int ivsize = crypto_aead_ivsize(aead);
1310 int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
1312 assoc_nents = sg_count(req->assoc, req->assoclen);
1313 src_nents = sg_count(req->src, req->cryptlen);
1315 if (unlikely(req->dst != req->src))
1316 dst_nents = sg_count(req->dst, req->cryptlen);
1318 sgc = dma_map_sg(jrdev, req->assoc, assoc_nents ? : 1,
1320 if (likely(req->src == req->dst)) {
1321 sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
1324 sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
1326 sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
1330 /* Check if data are contiguous */
1331 iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
1332 if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
1333 iv_dma || src_nents || iv_dma + ivsize != sg_dma_address(req->src))
1334 contig &= ~GIV_SRC_CONTIG;
1335 if (dst_nents || iv_dma + ivsize != sg_dma_address(req->dst))
1336 contig &= ~GIV_DST_CONTIG;
1337 if (unlikely(req->src != req->dst)) {
1338 dst_nents = dst_nents ? : 1;
1341 if (!(contig & GIV_SRC_CONTIG)) {
1342 assoc_nents = assoc_nents ? : 1;
1343 src_nents = src_nents ? : 1;
1344 sec4_sg_len += assoc_nents + 1 + src_nents;
1345 if (likely(req->src == req->dst))
1346 contig &= ~GIV_DST_CONTIG;
1348 sec4_sg_len += dst_nents;
1350 sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
1352 /* allocate space for base edesc and hw desc commands, link tables */
1353 edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
1354 sec4_sg_bytes, GFP_DMA | flags);
1356 dev_err(jrdev, "could not allocate extended descriptor\n");
1357 return ERR_PTR(-ENOMEM);
1360 edesc->assoc_nents = assoc_nents;
1361 edesc->src_nents = src_nents;
1362 edesc->dst_nents = dst_nents;
1363 edesc->iv_dma = iv_dma;
1364 edesc->sec4_sg_bytes = sec4_sg_bytes;
1365 edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
1367 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1368 sec4_sg_bytes, DMA_TO_DEVICE);
1369 *contig_ptr = contig;
1372 if (!(contig & GIV_SRC_CONTIG)) {
1373 sg_to_sec4_sg(req->assoc, assoc_nents,
1376 sec4_sg_index += assoc_nents;
1377 dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
1380 sg_to_sec4_sg_last(req->src, src_nents,
1383 sec4_sg_index += src_nents;
1385 if (unlikely(req->src != req->dst && !(contig & GIV_DST_CONTIG))) {
1386 dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
1389 sg_to_sec4_sg_last(req->dst, dst_nents,
1390 edesc->sec4_sg + sec4_sg_index, 0);
1396 static int aead_givencrypt(struct aead_givcrypt_request *areq)
1398 struct aead_request *req = &areq->areq;
1399 struct aead_edesc *edesc;
1400 struct crypto_aead *aead = crypto_aead_reqtfm(req);
1401 struct caam_ctx *ctx = crypto_aead_ctx(aead);
1402 struct device *jrdev = ctx->jrdev;
1407 req->cryptlen += ctx->authsize;
1409 /* allocate extended descriptor */
1410 edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN *
1411 CAAM_CMD_SZ, &contig);
1414 return PTR_ERR(edesc);
1417 print_hex_dump(KERN_ERR, "giv src@"xstr(__LINE__)": ",
1418 DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
1422 /* Create and submit job descriptor*/
1423 init_aead_giv_job(ctx->sh_desc_givenc,
1424 ctx->sh_desc_givenc_dma, edesc, req, contig);
1426 print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ",
1427 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1428 desc_bytes(edesc->hw_desc), 1);
1431 desc = edesc->hw_desc;
1432 ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
1436 aead_unmap(jrdev, edesc, req);
1444 * allocate and map the ablkcipher extended descriptor for ablkcipher
1446 static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
1447 *req, int desc_bytes,
1448 bool *iv_contig_out)
1450 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
1451 struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
1452 struct device *jrdev = ctx->jrdev;
1453 gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1454 CRYPTO_TFM_REQ_MAY_SLEEP)) ?
1455 GFP_KERNEL : GFP_ATOMIC;
1456 int src_nents, dst_nents = 0, sec4_sg_bytes;
1457 struct ablkcipher_edesc *edesc;
1458 dma_addr_t iv_dma = 0;
1459 bool iv_contig = false;
1461 int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
1464 src_nents = sg_count(req->src, req->nbytes);
1466 if (unlikely(req->dst != req->src))
1467 dst_nents = sg_count(req->dst, req->nbytes);
1469 if (likely(req->src == req->dst)) {
1470 sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
1473 sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1,
1475 sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1,
1480 * Check if iv can be contiguous with source and destination.
1481 * If so, include it. If not, create scatterlist.
1483 iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
1484 if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
1487 src_nents = src_nents ? : 1;
1488 sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
1489 sizeof(struct sec4_sg_entry);
1491 /* allocate space for base edesc and hw desc commands, link tables */
1492 edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
1493 sec4_sg_bytes, GFP_DMA | flags);
1495 dev_err(jrdev, "could not allocate extended descriptor\n");
1496 return ERR_PTR(-ENOMEM);
1499 edesc->src_nents = src_nents;
1500 edesc->dst_nents = dst_nents;
1501 edesc->sec4_sg_bytes = sec4_sg_bytes;
1502 edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
1507 dma_to_sec4_sg_one(edesc->sec4_sg, iv_dma, ivsize, 0);
1508 sg_to_sec4_sg_last(req->src, src_nents,
1509 edesc->sec4_sg + 1, 0);
1510 sec4_sg_index += 1 + src_nents;
1513 if (unlikely(dst_nents)) {
1514 sg_to_sec4_sg_last(req->dst, dst_nents,
1515 edesc->sec4_sg + sec4_sg_index, 0);
1518 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1519 sec4_sg_bytes, DMA_TO_DEVICE);
1520 edesc->iv_dma = iv_dma;
1523 print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"xstr(__LINE__)": ",
1524 DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
1528 *iv_contig_out = iv_contig;
1532 static int ablkcipher_encrypt(struct ablkcipher_request *req)
1534 struct ablkcipher_edesc *edesc;
1535 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
1536 struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
1537 struct device *jrdev = ctx->jrdev;
1542 /* allocate extended descriptor */
1543 edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
1544 CAAM_CMD_SZ, &iv_contig);
1546 return PTR_ERR(edesc);
1548 /* Create and submit job descriptor*/
1549 init_ablkcipher_job(ctx->sh_desc_enc,
1550 ctx->sh_desc_enc_dma, edesc, req, iv_contig);
1552 print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ",
1553 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1554 desc_bytes(edesc->hw_desc), 1);
1556 desc = edesc->hw_desc;
1557 ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req);
1562 ablkcipher_unmap(jrdev, edesc, req);
1569 static int ablkcipher_decrypt(struct ablkcipher_request *req)
1571 struct ablkcipher_edesc *edesc;
1572 struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
1573 struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
1574 struct device *jrdev = ctx->jrdev;
1579 /* allocate extended descriptor */
1580 edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
1581 CAAM_CMD_SZ, &iv_contig);
1583 return PTR_ERR(edesc);
1585 /* Create and submit job descriptor*/
1586 init_ablkcipher_job(ctx->sh_desc_dec,
1587 ctx->sh_desc_dec_dma, edesc, req, iv_contig);
1588 desc = edesc->hw_desc;
1590 print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ",
1591 DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
1592 desc_bytes(edesc->hw_desc), 1);
1595 ret = caam_jr_enqueue(jrdev, desc, ablkcipher_decrypt_done, req);
1599 ablkcipher_unmap(jrdev, edesc, req);
1606 #define template_aead template_u.aead
1607 #define template_ablkcipher template_u.ablkcipher
1608 struct caam_alg_template {
1609 char name[CRYPTO_MAX_ALG_NAME];
1610 char driver_name[CRYPTO_MAX_ALG_NAME];
1611 unsigned int blocksize;
1614 struct ablkcipher_alg ablkcipher;
1615 struct aead_alg aead;
1616 struct blkcipher_alg blkcipher;
1617 struct cipher_alg cipher;
1618 struct compress_alg compress;
1621 u32 class1_alg_type;
1622 u32 class2_alg_type;
1626 static struct caam_alg_template driver_algs[] = {
1627 /* single-pass ipsec_esp descriptor */
1629 .name = "authenc(hmac(md5),cbc(aes))",
1630 .driver_name = "authenc-hmac-md5-cbc-aes-caam",
1631 .blocksize = AES_BLOCK_SIZE,
1632 .type = CRYPTO_ALG_TYPE_AEAD,
1634 .setkey = aead_setkey,
1635 .setauthsize = aead_setauthsize,
1636 .encrypt = aead_encrypt,
1637 .decrypt = aead_decrypt,
1638 .givencrypt = aead_givencrypt,
1639 .geniv = "<built-in>",
1640 .ivsize = AES_BLOCK_SIZE,
1641 .maxauthsize = MD5_DIGEST_SIZE,
1643 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1644 .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
1645 .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
1648 .name = "authenc(hmac(sha1),cbc(aes))",
1649 .driver_name = "authenc-hmac-sha1-cbc-aes-caam",
1650 .blocksize = AES_BLOCK_SIZE,
1651 .type = CRYPTO_ALG_TYPE_AEAD,
1653 .setkey = aead_setkey,
1654 .setauthsize = aead_setauthsize,
1655 .encrypt = aead_encrypt,
1656 .decrypt = aead_decrypt,
1657 .givencrypt = aead_givencrypt,
1658 .geniv = "<built-in>",
1659 .ivsize = AES_BLOCK_SIZE,
1660 .maxauthsize = SHA1_DIGEST_SIZE,
1662 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1663 .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
1664 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
1667 .name = "authenc(hmac(sha224),cbc(aes))",
1668 .driver_name = "authenc-hmac-sha224-cbc-aes-caam",
1669 .blocksize = AES_BLOCK_SIZE,
1671 .setkey = aead_setkey,
1672 .setauthsize = aead_setauthsize,
1673 .encrypt = aead_encrypt,
1674 .decrypt = aead_decrypt,
1675 .givencrypt = aead_givencrypt,
1676 .geniv = "<built-in>",
1677 .ivsize = AES_BLOCK_SIZE,
1678 .maxauthsize = SHA224_DIGEST_SIZE,
1680 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1681 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
1682 OP_ALG_AAI_HMAC_PRECOMP,
1683 .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
1686 .name = "authenc(hmac(sha256),cbc(aes))",
1687 .driver_name = "authenc-hmac-sha256-cbc-aes-caam",
1688 .blocksize = AES_BLOCK_SIZE,
1689 .type = CRYPTO_ALG_TYPE_AEAD,
1691 .setkey = aead_setkey,
1692 .setauthsize = aead_setauthsize,
1693 .encrypt = aead_encrypt,
1694 .decrypt = aead_decrypt,
1695 .givencrypt = aead_givencrypt,
1696 .geniv = "<built-in>",
1697 .ivsize = AES_BLOCK_SIZE,
1698 .maxauthsize = SHA256_DIGEST_SIZE,
1700 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1701 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
1702 OP_ALG_AAI_HMAC_PRECOMP,
1703 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
1706 .name = "authenc(hmac(sha384),cbc(aes))",
1707 .driver_name = "authenc-hmac-sha384-cbc-aes-caam",
1708 .blocksize = AES_BLOCK_SIZE,
1710 .setkey = aead_setkey,
1711 .setauthsize = aead_setauthsize,
1712 .encrypt = aead_encrypt,
1713 .decrypt = aead_decrypt,
1714 .givencrypt = aead_givencrypt,
1715 .geniv = "<built-in>",
1716 .ivsize = AES_BLOCK_SIZE,
1717 .maxauthsize = SHA384_DIGEST_SIZE,
1719 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1720 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
1721 OP_ALG_AAI_HMAC_PRECOMP,
1722 .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
1726 .name = "authenc(hmac(sha512),cbc(aes))",
1727 .driver_name = "authenc-hmac-sha512-cbc-aes-caam",
1728 .blocksize = AES_BLOCK_SIZE,
1729 .type = CRYPTO_ALG_TYPE_AEAD,
1731 .setkey = aead_setkey,
1732 .setauthsize = aead_setauthsize,
1733 .encrypt = aead_encrypt,
1734 .decrypt = aead_decrypt,
1735 .givencrypt = aead_givencrypt,
1736 .geniv = "<built-in>",
1737 .ivsize = AES_BLOCK_SIZE,
1738 .maxauthsize = SHA512_DIGEST_SIZE,
1740 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1741 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
1742 OP_ALG_AAI_HMAC_PRECOMP,
1743 .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
1746 .name = "authenc(hmac(md5),cbc(des3_ede))",
1747 .driver_name = "authenc-hmac-md5-cbc-des3_ede-caam",
1748 .blocksize = DES3_EDE_BLOCK_SIZE,
1749 .type = CRYPTO_ALG_TYPE_AEAD,
1751 .setkey = aead_setkey,
1752 .setauthsize = aead_setauthsize,
1753 .encrypt = aead_encrypt,
1754 .decrypt = aead_decrypt,
1755 .givencrypt = aead_givencrypt,
1756 .geniv = "<built-in>",
1757 .ivsize = DES3_EDE_BLOCK_SIZE,
1758 .maxauthsize = MD5_DIGEST_SIZE,
1760 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1761 .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
1762 .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
1765 .name = "authenc(hmac(sha1),cbc(des3_ede))",
1766 .driver_name = "authenc-hmac-sha1-cbc-des3_ede-caam",
1767 .blocksize = DES3_EDE_BLOCK_SIZE,
1768 .type = CRYPTO_ALG_TYPE_AEAD,
1770 .setkey = aead_setkey,
1771 .setauthsize = aead_setauthsize,
1772 .encrypt = aead_encrypt,
1773 .decrypt = aead_decrypt,
1774 .givencrypt = aead_givencrypt,
1775 .geniv = "<built-in>",
1776 .ivsize = DES3_EDE_BLOCK_SIZE,
1777 .maxauthsize = SHA1_DIGEST_SIZE,
1779 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1780 .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
1781 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
1784 .name = "authenc(hmac(sha224),cbc(des3_ede))",
1785 .driver_name = "authenc-hmac-sha224-cbc-des3_ede-caam",
1786 .blocksize = DES3_EDE_BLOCK_SIZE,
1788 .setkey = aead_setkey,
1789 .setauthsize = aead_setauthsize,
1790 .encrypt = aead_encrypt,
1791 .decrypt = aead_decrypt,
1792 .givencrypt = aead_givencrypt,
1793 .geniv = "<built-in>",
1794 .ivsize = DES3_EDE_BLOCK_SIZE,
1795 .maxauthsize = SHA224_DIGEST_SIZE,
1797 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1798 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
1799 OP_ALG_AAI_HMAC_PRECOMP,
1800 .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
1803 .name = "authenc(hmac(sha256),cbc(des3_ede))",
1804 .driver_name = "authenc-hmac-sha256-cbc-des3_ede-caam",
1805 .blocksize = DES3_EDE_BLOCK_SIZE,
1806 .type = CRYPTO_ALG_TYPE_AEAD,
1808 .setkey = aead_setkey,
1809 .setauthsize = aead_setauthsize,
1810 .encrypt = aead_encrypt,
1811 .decrypt = aead_decrypt,
1812 .givencrypt = aead_givencrypt,
1813 .geniv = "<built-in>",
1814 .ivsize = DES3_EDE_BLOCK_SIZE,
1815 .maxauthsize = SHA256_DIGEST_SIZE,
1817 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1818 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
1819 OP_ALG_AAI_HMAC_PRECOMP,
1820 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
1823 .name = "authenc(hmac(sha384),cbc(des3_ede))",
1824 .driver_name = "authenc-hmac-sha384-cbc-des3_ede-caam",
1825 .blocksize = DES3_EDE_BLOCK_SIZE,
1827 .setkey = aead_setkey,
1828 .setauthsize = aead_setauthsize,
1829 .encrypt = aead_encrypt,
1830 .decrypt = aead_decrypt,
1831 .givencrypt = aead_givencrypt,
1832 .geniv = "<built-in>",
1833 .ivsize = DES3_EDE_BLOCK_SIZE,
1834 .maxauthsize = SHA384_DIGEST_SIZE,
1836 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1837 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
1838 OP_ALG_AAI_HMAC_PRECOMP,
1839 .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
1842 .name = "authenc(hmac(sha512),cbc(des3_ede))",
1843 .driver_name = "authenc-hmac-sha512-cbc-des3_ede-caam",
1844 .blocksize = DES3_EDE_BLOCK_SIZE,
1845 .type = CRYPTO_ALG_TYPE_AEAD,
1847 .setkey = aead_setkey,
1848 .setauthsize = aead_setauthsize,
1849 .encrypt = aead_encrypt,
1850 .decrypt = aead_decrypt,
1851 .givencrypt = aead_givencrypt,
1852 .geniv = "<built-in>",
1853 .ivsize = DES3_EDE_BLOCK_SIZE,
1854 .maxauthsize = SHA512_DIGEST_SIZE,
1856 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
1857 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
1858 OP_ALG_AAI_HMAC_PRECOMP,
1859 .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
1862 .name = "authenc(hmac(md5),cbc(des))",
1863 .driver_name = "authenc-hmac-md5-cbc-des-caam",
1864 .blocksize = DES_BLOCK_SIZE,
1865 .type = CRYPTO_ALG_TYPE_AEAD,
1867 .setkey = aead_setkey,
1868 .setauthsize = aead_setauthsize,
1869 .encrypt = aead_encrypt,
1870 .decrypt = aead_decrypt,
1871 .givencrypt = aead_givencrypt,
1872 .geniv = "<built-in>",
1873 .ivsize = DES_BLOCK_SIZE,
1874 .maxauthsize = MD5_DIGEST_SIZE,
1876 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1877 .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
1878 .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
1881 .name = "authenc(hmac(sha1),cbc(des))",
1882 .driver_name = "authenc-hmac-sha1-cbc-des-caam",
1883 .blocksize = DES_BLOCK_SIZE,
1884 .type = CRYPTO_ALG_TYPE_AEAD,
1886 .setkey = aead_setkey,
1887 .setauthsize = aead_setauthsize,
1888 .encrypt = aead_encrypt,
1889 .decrypt = aead_decrypt,
1890 .givencrypt = aead_givencrypt,
1891 .geniv = "<built-in>",
1892 .ivsize = DES_BLOCK_SIZE,
1893 .maxauthsize = SHA1_DIGEST_SIZE,
1895 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1896 .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
1897 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
1900 .name = "authenc(hmac(sha224),cbc(des))",
1901 .driver_name = "authenc-hmac-sha224-cbc-des-caam",
1902 .blocksize = DES_BLOCK_SIZE,
1904 .setkey = aead_setkey,
1905 .setauthsize = aead_setauthsize,
1906 .encrypt = aead_encrypt,
1907 .decrypt = aead_decrypt,
1908 .givencrypt = aead_givencrypt,
1909 .geniv = "<built-in>",
1910 .ivsize = DES_BLOCK_SIZE,
1911 .maxauthsize = SHA224_DIGEST_SIZE,
1913 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1914 .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
1915 OP_ALG_AAI_HMAC_PRECOMP,
1916 .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
1919 .name = "authenc(hmac(sha256),cbc(des))",
1920 .driver_name = "authenc-hmac-sha256-cbc-des-caam",
1921 .blocksize = DES_BLOCK_SIZE,
1922 .type = CRYPTO_ALG_TYPE_AEAD,
1924 .setkey = aead_setkey,
1925 .setauthsize = aead_setauthsize,
1926 .encrypt = aead_encrypt,
1927 .decrypt = aead_decrypt,
1928 .givencrypt = aead_givencrypt,
1929 .geniv = "<built-in>",
1930 .ivsize = DES_BLOCK_SIZE,
1931 .maxauthsize = SHA256_DIGEST_SIZE,
1933 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1934 .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
1935 OP_ALG_AAI_HMAC_PRECOMP,
1936 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
1939 .name = "authenc(hmac(sha384),cbc(des))",
1940 .driver_name = "authenc-hmac-sha384-cbc-des-caam",
1941 .blocksize = DES_BLOCK_SIZE,
1943 .setkey = aead_setkey,
1944 .setauthsize = aead_setauthsize,
1945 .encrypt = aead_encrypt,
1946 .decrypt = aead_decrypt,
1947 .givencrypt = aead_givencrypt,
1948 .geniv = "<built-in>",
1949 .ivsize = DES_BLOCK_SIZE,
1950 .maxauthsize = SHA384_DIGEST_SIZE,
1952 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1953 .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
1954 OP_ALG_AAI_HMAC_PRECOMP,
1955 .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
1958 .name = "authenc(hmac(sha512),cbc(des))",
1959 .driver_name = "authenc-hmac-sha512-cbc-des-caam",
1960 .blocksize = DES_BLOCK_SIZE,
1961 .type = CRYPTO_ALG_TYPE_AEAD,
1963 .setkey = aead_setkey,
1964 .setauthsize = aead_setauthsize,
1965 .encrypt = aead_encrypt,
1966 .decrypt = aead_decrypt,
1967 .givencrypt = aead_givencrypt,
1968 .geniv = "<built-in>",
1969 .ivsize = DES_BLOCK_SIZE,
1970 .maxauthsize = SHA512_DIGEST_SIZE,
1972 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
1973 .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
1974 OP_ALG_AAI_HMAC_PRECOMP,
1975 .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
1977 /* ablkcipher descriptor */
1980 .driver_name = "cbc-aes-caam",
1981 .blocksize = AES_BLOCK_SIZE,
1982 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
1983 .template_ablkcipher = {
1984 .setkey = ablkcipher_setkey,
1985 .encrypt = ablkcipher_encrypt,
1986 .decrypt = ablkcipher_decrypt,
1988 .min_keysize = AES_MIN_KEY_SIZE,
1989 .max_keysize = AES_MAX_KEY_SIZE,
1990 .ivsize = AES_BLOCK_SIZE,
1992 .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
1995 .name = "cbc(des3_ede)",
1996 .driver_name = "cbc-3des-caam",
1997 .blocksize = DES3_EDE_BLOCK_SIZE,
1998 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
1999 .template_ablkcipher = {
2000 .setkey = ablkcipher_setkey,
2001 .encrypt = ablkcipher_encrypt,
2002 .decrypt = ablkcipher_decrypt,
2004 .min_keysize = DES3_EDE_KEY_SIZE,
2005 .max_keysize = DES3_EDE_KEY_SIZE,
2006 .ivsize = DES3_EDE_BLOCK_SIZE,
2008 .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
2012 .driver_name = "cbc-des-caam",
2013 .blocksize = DES_BLOCK_SIZE,
2014 .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2015 .template_ablkcipher = {
2016 .setkey = ablkcipher_setkey,
2017 .encrypt = ablkcipher_encrypt,
2018 .decrypt = ablkcipher_decrypt,
2020 .min_keysize = DES_KEY_SIZE,
2021 .max_keysize = DES_KEY_SIZE,
2022 .ivsize = DES_BLOCK_SIZE,
2024 .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
2028 struct caam_crypto_alg {
2029 struct list_head entry;
2030 struct device *ctrldev;
2031 int class1_alg_type;
2032 int class2_alg_type;
2034 struct crypto_alg crypto_alg;
2037 static int caam_cra_init(struct crypto_tfm *tfm)
2039 struct crypto_alg *alg = tfm->__crt_alg;
2040 struct caam_crypto_alg *caam_alg =
2041 container_of(alg, struct caam_crypto_alg, crypto_alg);
2042 struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
2043 struct caam_drv_private *priv = dev_get_drvdata(caam_alg->ctrldev);
2044 int tgt_jr = atomic_inc_return(&priv->tfm_count);
2047 * distribute tfms across job rings to ensure in-order
2048 * crypto request processing per tfm
2050 ctx->jrdev = priv->jrdev[(tgt_jr / 2) % priv->total_jobrs];
2052 /* copy descriptor header template value */
2053 ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
2054 ctx->class2_alg_type = OP_TYPE_CLASS2_ALG | caam_alg->class2_alg_type;
2055 ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_alg->alg_op;
2060 static void caam_cra_exit(struct crypto_tfm *tfm)
2062 struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
2064 if (ctx->sh_desc_enc_dma &&
2065 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_enc_dma))
2066 dma_unmap_single(ctx->jrdev, ctx->sh_desc_enc_dma,
2067 desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
2068 if (ctx->sh_desc_dec_dma &&
2069 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_dec_dma))
2070 dma_unmap_single(ctx->jrdev, ctx->sh_desc_dec_dma,
2071 desc_bytes(ctx->sh_desc_dec), DMA_TO_DEVICE);
2072 if (ctx->sh_desc_givenc_dma &&
2073 !dma_mapping_error(ctx->jrdev, ctx->sh_desc_givenc_dma))
2074 dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
2075 desc_bytes(ctx->sh_desc_givenc),
2079 static void __exit caam_algapi_exit(void)
2082 struct device_node *dev_node;
2083 struct platform_device *pdev;
2084 struct device *ctrldev;
2085 struct caam_drv_private *priv;
2086 struct caam_crypto_alg *t_alg, *n;
2088 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
2090 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
2095 pdev = of_find_device_by_node(dev_node);
2099 ctrldev = &pdev->dev;
2100 of_node_put(dev_node);
2101 priv = dev_get_drvdata(ctrldev);
2103 if (!priv->alg_list.next)
2106 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2107 crypto_unregister_alg(&t_alg->crypto_alg);
2108 list_del(&t_alg->entry);
2113 static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
2114 struct caam_alg_template
2117 struct caam_crypto_alg *t_alg;
2118 struct crypto_alg *alg;
2120 t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
2122 dev_err(ctrldev, "failed to allocate t_alg\n");
2123 return ERR_PTR(-ENOMEM);
2126 alg = &t_alg->crypto_alg;
2128 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
2129 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
2130 template->driver_name);
2131 alg->cra_module = THIS_MODULE;
2132 alg->cra_init = caam_cra_init;
2133 alg->cra_exit = caam_cra_exit;
2134 alg->cra_priority = CAAM_CRA_PRIORITY;
2135 alg->cra_blocksize = template->blocksize;
2136 alg->cra_alignmask = 0;
2137 alg->cra_ctxsize = sizeof(struct caam_ctx);
2138 alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
2140 switch (template->type) {
2141 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2142 alg->cra_type = &crypto_ablkcipher_type;
2143 alg->cra_ablkcipher = template->template_ablkcipher;
2145 case CRYPTO_ALG_TYPE_AEAD:
2146 alg->cra_type = &crypto_aead_type;
2147 alg->cra_aead = template->template_aead;
2151 t_alg->class1_alg_type = template->class1_alg_type;
2152 t_alg->class2_alg_type = template->class2_alg_type;
2153 t_alg->alg_op = template->alg_op;
2154 t_alg->ctrldev = ctrldev;
2159 static int __init caam_algapi_init(void)
2161 struct device_node *dev_node;
2162 struct platform_device *pdev;
2163 struct device *ctrldev;
2164 struct caam_drv_private *priv;
2167 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
2169 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
2174 pdev = of_find_device_by_node(dev_node);
2178 ctrldev = &pdev->dev;
2179 priv = dev_get_drvdata(ctrldev);
2180 of_node_put(dev_node);
2182 INIT_LIST_HEAD(&priv->alg_list);
2184 atomic_set(&priv->tfm_count, -1);
2186 /* register crypto algorithms the device supports */
2187 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2188 /* TODO: check if h/w supports alg */
2189 struct caam_crypto_alg *t_alg;
2191 t_alg = caam_alg_alloc(ctrldev, &driver_algs[i]);
2192 if (IS_ERR(t_alg)) {
2193 err = PTR_ERR(t_alg);
2194 dev_warn(ctrldev, "%s alg allocation failed\n",
2195 driver_algs[i].driver_name);
2199 err = crypto_register_alg(&t_alg->crypto_alg);
2201 dev_warn(ctrldev, "%s alg registration failed\n",
2202 t_alg->crypto_alg.cra_driver_name);
2205 list_add_tail(&t_alg->entry, &priv->alg_list);
2207 if (!list_empty(&priv->alg_list))
2208 dev_info(ctrldev, "%s algorithms registered in /proc/crypto\n",
2209 (char *)of_get_property(dev_node, "compatible", NULL));
2214 module_init(caam_algapi_init);
2215 module_exit(caam_algapi_exit);
2217 MODULE_LICENSE("GPL");
2218 MODULE_DESCRIPTION("FSL CAAM support for crypto API");
2219 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");