Pileus Git - ~andy/linux/blob - drivers/cpufreq/spear-cpufreq.c

   1 /*
   2  * drivers/cpufreq/spear-cpufreq.c
   3  *
   4  * CPU Frequency Scaling for SPEAr platform
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Deepak Sikri <deepak.sikri@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16 #include <linux/clk.h>
  17 #include <linux/cpufreq.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/of_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24
  25 /* SPEAr CPUFreq driver data structure */
  26 static struct {
  27         struct clk *clk;
  28         unsigned int transition_latency;
  29         struct cpufreq_frequency_table *freq_tbl;
  30         u32 cnt;
  31 } spear_cpufreq;
  32
  33 static unsigned int spear_cpufreq_get(unsigned int cpu)
  34 {
  35         return clk_get_rate(spear_cpufreq.clk) / 1000;
  36 }
  37
  38 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq)
  39 {
  40         struct clk *sys_pclk;
  41         int pclk;
  42         /*
  43          * In SPEAr1340, cpu clk's parent sys clk can take input from
  44          * following sources
  45          */
  46         const char *sys_clk_src[] = {
  47                 "sys_syn_clk",
  48                 "pll1_clk",
  49                 "pll2_clk",
  50                 "pll3_clk",
  51         };
  52
  53         /*
  54          * As sys clk can have multiple source with their own range
  55          * limitation so we choose possible sources accordingly
  56          */
  57         if (newfreq <= 300000000)
  58                 pclk = 0; /* src is sys_syn_clk */
  59         else if (newfreq > 300000000 && newfreq <= 500000000)
  60                 pclk = 3; /* src is pll3_clk */
  61         else if (newfreq == 600000000)
  62                 pclk = 1; /* src is pll1_clk */
  63         else
  64                 return ERR_PTR(-EINVAL);
  65
  66         /* Get parent to sys clock */
  67         sys_pclk = clk_get(NULL, sys_clk_src[pclk]);
  68         if (IS_ERR(sys_pclk))
  69                 pr_err("Failed to get %s clock\n", sys_clk_src[pclk]);
  70
  71         return sys_pclk;
  72 }
  73
  74 /*
  75  * In SPEAr1340, we cannot use newfreq directly because we need to actually
  76  * access a source clock (clk) which might not be ancestor of cpu at present.
  77  * Hence in SPEAr1340 we would operate on source clock directly before switching
  78  * cpu clock to it.
  79  */
  80 static int spear1340_set_cpu_rate(struct clk *sys_pclk, unsigned long newfreq)
  81 {
  82         struct clk *sys_clk;
  83         int ret = 0;
  84
  85         sys_clk = clk_get_parent(spear_cpufreq.clk);
  86         if (IS_ERR(sys_clk)) {
  87                 pr_err("failed to get cpu's parent (sys) clock\n");
  88                 return PTR_ERR(sys_clk);
  89         }
  90
  91         /* Set the rate of the source clock before changing the parent */
  92         ret = clk_set_rate(sys_pclk, newfreq);
  93         if (ret) {
  94                 pr_err("Failed to set sys clk rate to %lu\n", newfreq);
  95                 return ret;
  96         }
  97
  98         ret = clk_set_parent(sys_clk, sys_pclk);
  99         if (ret) {
 100                 pr_err("Failed to set sys clk parent\n");
 101                 return ret;
 102         }
 103
 104         return 0;
 105 }
 106
 107 static int spear_cpufreq_target(struct cpufreq_policy *policy,
 108                 unsigned int target_freq, unsigned int relation)
 109 {
 110         struct cpufreq_freqs freqs;
 111         unsigned long newfreq;
 112         struct clk *srcclk;
 113         int index, ret, mult = 1;
 114
 115         if (cpufreq_frequency_table_target(policy, spear_cpufreq.freq_tbl,
 116                                 target_freq, relation, &index))
 117                 return -EINVAL;
 118
 119         freqs.old = spear_cpufreq_get(0);
 120
 121         newfreq = spear_cpufreq.freq_tbl[index].frequency * 1000;
 122         if (of_machine_is_compatible("st,spear1340")) {
 123                 /*
 124                  * SPEAr1340 is special in the sense that due to the possibility
 125                  * of multiple clock sources for cpu clk's parent we can have
 126                  * different clock source for different frequency of cpu clk.
 127                  * Hence we need to choose one from amongst these possible clock
 128                  * sources.
 129                  */
 130                 srcclk = spear1340_cpu_get_possible_parent(newfreq);
 131                 if (IS_ERR(srcclk)) {
 132                         pr_err("Failed to get src clk\n");
 133                         return PTR_ERR(srcclk);
 134                 }
 135
 136                 /* SPEAr1340: src clk is always 2 * intended cpu clk */
 137                 mult = 2;
 138         } else {
 139                 /*
 140                  * src clock to be altered is ancestor of cpu clock. Hence we
 141                  * can directly work on cpu clk
 142                  */
 143                 srcclk = spear_cpufreq.clk;
 144         }
 145
 146         newfreq = clk_round_rate(srcclk, newfreq * mult);
 147         if (newfreq < 0) {
 148                 pr_err("clk_round_rate failed for cpu src clock\n");
 149                 return newfreq;
 150         }
 151
 152         freqs.new = newfreq / 1000;
 153         freqs.new /= mult;
 154
 155         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 156
 157         if (mult == 2)
 158                 ret = spear1340_set_cpu_rate(srcclk, newfreq);
 159         else
 160                 ret = clk_set_rate(spear_cpufreq.clk, newfreq);
 161
 162         /* Get current rate after clk_set_rate, in case of failure */
 163         if (ret) {
 164                 pr_err("CPU Freq: cpu clk_set_rate failed: %d\n", ret);
 165                 freqs.new = clk_get_rate(spear_cpufreq.clk) / 1000;
 166         }
 167
 168         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 169         return ret;
 170 }
 171
 172 static int spear_cpufreq_init(struct cpufreq_policy *policy)
 173 {
 174         int ret;
 175
 176         ret = cpufreq_table_validate_and_show(policy, spear_cpufreq.freq_tbl);
 177         if (ret) {
 178                 pr_err("cpufreq_table_validate_and_show() failed");
 179                 return ret;
 180         }
 181
 182         policy->cpuinfo.transition_latency = spear_cpufreq.transition_latency;
 183         cpumask_setall(policy->cpus);
 184
 185         return 0;
 186 }
 187
 188 static struct cpufreq_driver spear_cpufreq_driver = {
 189         .name           = "cpufreq-spear",
 190         .flags          = CPUFREQ_STICKY,
 191         .verify         = cpufreq_generic_frequency_table_verify,
 192         .target         = spear_cpufreq_target,
 193         .get            = spear_cpufreq_get,
 194         .init           = spear_cpufreq_init,
 195         .exit           = cpufreq_generic_exit,
 196         .attr           = cpufreq_generic_attr,
 197 };
 198
 199 static int spear_cpufreq_driver_init(void)
 200 {
 201         struct device_node *np;
 202         const struct property *prop;
 203         struct cpufreq_frequency_table *freq_tbl;
 204         const __be32 *val;
 205         int cnt, i, ret;
 206
 207         np = of_cpu_device_node_get(0);
 208         if (!np) {
 209                 pr_err("No cpu node found");
 210                 return -ENODEV;
 211         }
 212
 213         if (of_property_read_u32(np, "clock-latency",
 214                                 &spear_cpufreq.transition_latency))
 215                 spear_cpufreq.transition_latency = CPUFREQ_ETERNAL;
 216
 217         prop = of_find_property(np, "cpufreq_tbl", NULL);
 218         if (!prop || !prop->value) {
 219                 pr_err("Invalid cpufreq_tbl");
 220                 ret = -ENODEV;
 221                 goto out_put_node;
 222         }
 223
 224         cnt = prop->length / sizeof(u32);
 225         val = prop->value;
 226
 227         freq_tbl = kmalloc(sizeof(*freq_tbl) * (cnt + 1), GFP_KERNEL);
 228         if (!freq_tbl) {
 229                 ret = -ENOMEM;
 230                 goto out_put_node;
 231         }
 232
 233         for (i = 0; i < cnt; i++) {
 234                 freq_tbl[i].driver_data = i;
 235                 freq_tbl[i].frequency = be32_to_cpup(val++);
 236         }
 237
 238         freq_tbl[i].driver_data = i;
 239         freq_tbl[i].frequency = CPUFREQ_TABLE_END;
 240
 241         spear_cpufreq.freq_tbl = freq_tbl;
 242
 243         of_node_put(np);
 244
 245         spear_cpufreq.clk = clk_get(NULL, "cpu_clk");
 246         if (IS_ERR(spear_cpufreq.clk)) {
 247                 pr_err("Unable to get CPU clock\n");
 248                 ret = PTR_ERR(spear_cpufreq.clk);
 249                 goto out_put_mem;
 250         }
 251
 252         ret = cpufreq_register_driver(&spear_cpufreq_driver);
 253         if (!ret)
 254                 return 0;
 255
 256         pr_err("failed register driver: %d\n", ret);
 257         clk_put(spear_cpufreq.clk);
 258
 259 out_put_mem:
 260         kfree(freq_tbl);
 261         return ret;
 262
 263 out_put_node:
 264         of_node_put(np);
 265         return ret;
 266 }
 267 late_initcall(spear_cpufreq_driver_init);
 268
 269 MODULE_AUTHOR("Deepak Sikri <deepak.sikri@st.com>");
 270 MODULE_DESCRIPTION("SPEAr CPUFreq driver");
 271 MODULE_LICENSE("GPL");