Pileus Git - ~andy/linux/blob - drivers/cpufreq/s3c64xx.c

   1 /*
   2  * Copyright 2009 Wolfson Microelectronics plc
   3  *
   4  * S3C64xx CPUfreq Support
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/init.h>
  14 #include <linux/cpufreq.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/regulator/consumer.h>
  18
  19 static struct clk *armclk;
  20 static struct regulator *vddarm;
  21 static unsigned long regulator_latency;
  22
  23 #ifdef CONFIG_CPU_S3C6410
  24 struct s3c64xx_dvfs {
  25         unsigned int vddarm_min;
  26         unsigned int vddarm_max;
  27 };
  28
  29 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
  30         [0] = { 1000000, 1150000 },
  31         [1] = { 1050000, 1150000 },
  32         [2] = { 1100000, 1150000 },
  33         [3] = { 1200000, 1350000 },
  34 };
  35
  36 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
  37         { 0,  66000 },
  38         { 0, 133000 },
  39         { 1, 222000 },
  40         { 1, 266000 },
  41         { 2, 333000 },
  42         { 2, 400000 },
  43         { 2, 532000 },
  44         { 2, 533000 },
  45         { 3, 667000 },
  46         { 0, CPUFREQ_TABLE_END },
  47 };
  48 #endif
  49
  50 static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
  51 {
  52         if (policy->cpu != 0)
  53                 return -EINVAL;
  54
  55         return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
  56 }
  57
  58 static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
  59 {
  60         if (cpu != 0)
  61                 return 0;
  62
  63         return clk_get_rate(armclk) / 1000;
  64 }
  65
  66 static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
  67                                       unsigned int target_freq,
  68                                       unsigned int relation)
  69 {
  70         int ret;
  71         unsigned int i;
  72         struct cpufreq_freqs freqs;
  73         struct s3c64xx_dvfs *dvfs;
  74
  75         ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
  76                                              target_freq, relation, &i);
  77         if (ret != 0)
  78                 return ret;
  79
  80         freqs.cpu = 0;
  81         freqs.old = clk_get_rate(armclk) / 1000;
  82         freqs.new = s3c64xx_freq_table[i].frequency;
  83         freqs.flags = 0;
  84         dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
  85
  86         if (freqs.old == freqs.new)
  87                 return 0;
  88
  89         pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
  90
  91         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  92
  93 #ifdef CONFIG_REGULATOR
  94         if (vddarm && freqs.new > freqs.old) {
  95                 ret = regulator_set_voltage(vddarm,
  96                                             dvfs->vddarm_min,
  97                                             dvfs->vddarm_max);
  98                 if (ret != 0) {
  99                         pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
 100                                freqs.new, ret);
 101                         goto err;
 102                 }
 103         }
 104 #endif
 105
 106         ret = clk_set_rate(armclk, freqs.new * 1000);
 107         if (ret < 0) {
 108                 pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
 109                        freqs.new, ret);
 110                 goto err;
 111         }
 112
 113 #ifdef CONFIG_REGULATOR
 114         if (vddarm && freqs.new < freqs.old) {
 115                 ret = regulator_set_voltage(vddarm,
 116                                             dvfs->vddarm_min,
 117                                             dvfs->vddarm_max);
 118                 if (ret != 0) {
 119                         pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
 120                                freqs.new, ret);
 121                         goto err_clk;
 122                 }
 123         }
 124 #endif
 125
 126         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 127
 128         pr_debug("cpufreq: Set actual frequency %lukHz\n",
 129                  clk_get_rate(armclk) / 1000);
 130
 131         return 0;
 132
 133 err_clk:
 134         if (clk_set_rate(armclk, freqs.old * 1000) < 0)
 135                 pr_err("Failed to restore original clock rate\n");
 136 err:
 137         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 138
 139         return ret;
 140 }
 141
 142 #ifdef CONFIG_REGULATOR
 143 static void __init s3c64xx_cpufreq_config_regulator(void)
 144 {
 145         int count, v, i, found;
 146         struct cpufreq_frequency_table *freq;
 147         struct s3c64xx_dvfs *dvfs;
 148
 149         count = regulator_count_voltages(vddarm);
 150         if (count < 0) {
 151                 pr_err("cpufreq: Unable to check supported voltages\n");
 152         }
 153
 154         freq = s3c64xx_freq_table;
 155         while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
 156                 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
 157                         continue;
 158
 159                 dvfs = &s3c64xx_dvfs_table[freq->index];
 160                 found = 0;
 161
 162                 for (i = 0; i < count; i++) {
 163                         v = regulator_list_voltage(vddarm, i);
 164                         if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
 165                                 found = 1;
 166                 }
 167
 168                 if (!found) {
 169                         pr_debug("cpufreq: %dkHz unsupported by regulator\n",
 170                                  freq->frequency);
 171                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 172                 }
 173
 174                 freq++;
 175         }
 176
 177         /* Guess based on having to do an I2C/SPI write; in future we
 178          * will be able to query the regulator performance here. */
 179         regulator_latency = 1 * 1000 * 1000;
 180 }
 181 #endif
 182
 183 static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 184 {
 185         int ret;
 186         struct cpufreq_frequency_table *freq;
 187
 188         if (policy->cpu != 0)
 189                 return -EINVAL;
 190
 191         if (s3c64xx_freq_table == NULL) {
 192                 pr_err("cpufreq: No frequency information for this CPU\n");
 193                 return -ENODEV;
 194         }
 195
 196         armclk = clk_get(NULL, "armclk");
 197         if (IS_ERR(armclk)) {
 198                 pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
 199                        PTR_ERR(armclk));
 200                 return PTR_ERR(armclk);
 201         }
 202
 203 #ifdef CONFIG_REGULATOR
 204         vddarm = regulator_get(NULL, "vddarm");
 205         if (IS_ERR(vddarm)) {
 206                 ret = PTR_ERR(vddarm);
 207                 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
 208                 pr_err("cpufreq: Only frequency scaling available\n");
 209                 vddarm = NULL;
 210         } else {
 211                 s3c64xx_cpufreq_config_regulator();
 212         }
 213 #endif
 214
 215         freq = s3c64xx_freq_table;
 216         while (freq->frequency != CPUFREQ_TABLE_END) {
 217                 unsigned long r;
 218
 219                 /* Check for frequencies we can generate */
 220                 r = clk_round_rate(armclk, freq->frequency * 1000);
 221                 r /= 1000;
 222                 if (r != freq->frequency) {
 223                         pr_debug("cpufreq: %dkHz unsupported by clock\n",
 224                                  freq->frequency);
 225                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 226                 }
 227
 228                 /* If we have no regulator then assume startup
 229                  * frequency is the maximum we can support. */
 230                 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
 231                         freq->frequency = CPUFREQ_ENTRY_INVALID;
 232
 233                 freq++;
 234         }
 235
 236         policy->cur = clk_get_rate(armclk) / 1000;
 237
 238         /* Datasheet says PLL stabalisation time (if we were to use
 239          * the PLLs, which we don't currently) is ~300us worst case,
 240          * but add some fudge.
 241          */
 242         policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
 243
 244         ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
 245         if (ret != 0) {
 246                 pr_err("cpufreq: Failed to configure frequency table: %d\n",
 247                        ret);
 248                 regulator_put(vddarm);
 249                 clk_put(armclk);
 250         }
 251
 252         return ret;
 253 }
 254
 255 static struct cpufreq_driver s3c64xx_cpufreq_driver = {
 256         .owner          = THIS_MODULE,
 257         .flags          = 0,
 258         .verify         = s3c64xx_cpufreq_verify_speed,
 259         .target         = s3c64xx_cpufreq_set_target,
 260         .get            = s3c64xx_cpufreq_get_speed,
 261         .init           = s3c64xx_cpufreq_driver_init,
 262         .name           = "s3c",
 263 };
 264
 265 static int __init s3c64xx_cpufreq_init(void)
 266 {
 267         return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
 268 }
 269 module_init(s3c64xx_cpufreq_init);