Pileus Git - ~andy/linux/blob - drivers/cpufreq/pmac64-cpufreq.c

   1 /*
   2  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
   3  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
  10  * that is iMac G5 and latest single CPU desktop.
  11  */
  12
  13 #undef DEBUG
  14
  15 #include <linux/module.h>
  16 #include <linux/types.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/sched.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/init.h>
  23 #include <linux/completion.h>
  24 #include <linux/mutex.h>
  25 #include <linux/of_device.h>
  26 #include <asm/prom.h>
  27 #include <asm/machdep.h>
  28 #include <asm/irq.h>
  29 #include <asm/sections.h>
  30 #include <asm/cputable.h>
  31 #include <asm/time.h>
  32 #include <asm/smu.h>
  33 #include <asm/pmac_pfunc.h>
  34
  35 #define DBG(fmt...) pr_debug(fmt)
  36
  37 /* see 970FX user manual */
  38
  39 #define SCOM_PCR 0x0aa001                       /* PCR scom addr */
  40
  41 #define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
  42 #define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
  43 #define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
  44 #define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
  45 #define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
  46 #define PCR_SPEED_SHIFT         17
  47 #define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
  48 #define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
  49 #define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
  50 #define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
  51 #define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
  52 #define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
  53
  54 #define SCOM_PSR 0x408001                       /* PSR scom addr */
  55 /* warning: PSR is a 64 bits register */
  56 #define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
  57 #define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
  58 #define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
  59 #define PSR_CUR_SPEED_SHIFT     (56)
  60
  61 /*
  62  * The G5 only supports two frequencies (Quarter speed is not supported)
  63  */
  64 #define CPUFREQ_HIGH                  0
  65 #define CPUFREQ_LOW                   1
  66
  67 static struct cpufreq_frequency_table g5_cpu_freqs[] = {
  68         {CPUFREQ_HIGH,          0},
  69         {CPUFREQ_LOW,           0},
  70         {0,                     CPUFREQ_TABLE_END},
  71 };
  72
  73 /* Power mode data is an array of the 32 bits PCR values to use for
  74  * the various frequencies, retrieved from the device-tree
  75  */
  76 static int g5_pmode_cur;
  77
  78 static void (*g5_switch_volt)(int speed_mode);
  79 static int (*g5_switch_freq)(int speed_mode);
  80 static int (*g5_query_freq)(void);
  81
  82 static DEFINE_MUTEX(g5_switch_mutex);
  83
  84 static unsigned long transition_latency;
  85
  86 #ifdef CONFIG_PMAC_SMU
  87
  88 static const u32 *g5_pmode_data;
  89 static int g5_pmode_max;
  90
  91 static struct smu_sdbp_fvt *g5_fvt_table;       /* table of op. points */
  92 static int g5_fvt_count;                        /* number of op. points */
  93 static int g5_fvt_cur;                          /* current op. point */
  94
  95 /*
  96  * SMU based voltage switching for Neo2 platforms
  97  */
  98
  99 static void g5_smu_switch_volt(int speed_mode)
 100 {
 101         struct smu_simple_cmd   cmd;
 102
 103         DECLARE_COMPLETION_ONSTACK(comp);
 104         smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
 105                          &comp, 'V', 'S', 'L', 'E', 'W',
 106                          0xff, g5_fvt_cur+1, speed_mode);
 107         wait_for_completion(&comp);
 108 }
 109
 110 /*
 111  * Platform function based voltage/vdnap switching for Neo2
 112  */
 113
 114 static struct pmf_function *pfunc_set_vdnap0;
 115 static struct pmf_function *pfunc_vdnap0_complete;
 116
 117 static void g5_vdnap_switch_volt(int speed_mode)
 118 {
 119         struct pmf_args args;
 120         u32 slew, done = 0;
 121         unsigned long timeout;
 122
 123         slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
 124         args.count = 1;
 125         args.u[0].p = &slew;
 126
 127         pmf_call_one(pfunc_set_vdnap0, &args);
 128
 129         /* It's an irq GPIO so we should be able to just block here,
 130          * I'll do that later after I've properly tested the IRQ code for
 131          * platform functions
 132          */
 133         timeout = jiffies + HZ/10;
 134         while(!time_after(jiffies, timeout)) {
 135                 args.count = 1;
 136                 args.u[0].p = &done;
 137                 pmf_call_one(pfunc_vdnap0_complete, &args);
 138                 if (done)
 139                         break;
 140                 msleep(1);
 141         }
 142         if (done == 0)
 143                 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
 144 }
 145
 146
 147 /*
 148  * SCOM based frequency switching for 970FX rev3
 149  */
 150 static int g5_scom_switch_freq(int speed_mode)
 151 {
 152         unsigned long flags;
 153         int to;
 154
 155         /* If frequency is going up, first ramp up the voltage */
 156         if (speed_mode < g5_pmode_cur)
 157                 g5_switch_volt(speed_mode);
 158
 159         local_irq_save(flags);
 160
 161         /* Clear PCR high */
 162         scom970_write(SCOM_PCR, 0);
 163         /* Clear PCR low */
 164         scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
 165         /* Set PCR low */
 166         scom970_write(SCOM_PCR, PCR_HILO_SELECT |
 167                       g5_pmode_data[speed_mode]);
 168
 169         /* Wait for completion */
 170         for (to = 0; to < 10; to++) {
 171                 unsigned long psr = scom970_read(SCOM_PSR);
 172
 173                 if ((psr & PSR_CMD_RECEIVED) == 0 &&
 174                     (((psr >> PSR_CUR_SPEED_SHIFT) ^
 175                       (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
 176                     == 0)
 177                         break;
 178                 if (psr & PSR_CMD_COMPLETED)
 179                         break;
 180                 udelay(100);
 181         }
 182
 183         local_irq_restore(flags);
 184
 185         /* If frequency is going down, last ramp the voltage */
 186         if (speed_mode > g5_pmode_cur)
 187                 g5_switch_volt(speed_mode);
 188
 189         g5_pmode_cur = speed_mode;
 190         ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 191
 192         return 0;
 193 }
 194
 195 static int g5_scom_query_freq(void)
 196 {
 197         unsigned long psr = scom970_read(SCOM_PSR);
 198         int i;
 199
 200         for (i = 0; i <= g5_pmode_max; i++)
 201                 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
 202                       (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
 203                         break;
 204         return i;
 205 }
 206
 207 /*
 208  * Fake voltage switching for platforms with missing support
 209  */
 210
 211 static void g5_dummy_switch_volt(int speed_mode)
 212 {
 213 }
 214
 215 #endif /* CONFIG_PMAC_SMU */
 216
 217 /*
 218  * Platform function based voltage switching for PowerMac7,2 & 7,3
 219  */
 220
 221 static struct pmf_function *pfunc_cpu0_volt_high;
 222 static struct pmf_function *pfunc_cpu0_volt_low;
 223 static struct pmf_function *pfunc_cpu1_volt_high;
 224 static struct pmf_function *pfunc_cpu1_volt_low;
 225
 226 static void g5_pfunc_switch_volt(int speed_mode)
 227 {
 228         if (speed_mode == CPUFREQ_HIGH) {
 229                 if (pfunc_cpu0_volt_high)
 230                         pmf_call_one(pfunc_cpu0_volt_high, NULL);
 231                 if (pfunc_cpu1_volt_high)
 232                         pmf_call_one(pfunc_cpu1_volt_high, NULL);
 233         } else {
 234                 if (pfunc_cpu0_volt_low)
 235                         pmf_call_one(pfunc_cpu0_volt_low, NULL);
 236                 if (pfunc_cpu1_volt_low)
 237                         pmf_call_one(pfunc_cpu1_volt_low, NULL);
 238         }
 239         msleep(10); /* should be faster , to fix */
 240 }
 241
 242 /*
 243  * Platform function based frequency switching for PowerMac7,2 & 7,3
 244  */
 245
 246 static struct pmf_function *pfunc_cpu_setfreq_high;
 247 static struct pmf_function *pfunc_cpu_setfreq_low;
 248 static struct pmf_function *pfunc_cpu_getfreq;
 249 static struct pmf_function *pfunc_slewing_done;
 250
 251 static int g5_pfunc_switch_freq(int speed_mode)
 252 {
 253         struct pmf_args args;
 254         u32 done = 0;
 255         unsigned long timeout;
 256         int rc;
 257
 258         DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
 259
 260         /* If frequency is going up, first ramp up the voltage */
 261         if (speed_mode < g5_pmode_cur)
 262                 g5_switch_volt(speed_mode);
 263
 264         /* Do it */
 265         if (speed_mode == CPUFREQ_HIGH)
 266                 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
 267         else
 268                 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
 269
 270         if (rc)
 271                 printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc);
 272
 273         /* It's an irq GPIO so we should be able to just block here,
 274          * I'll do that later after I've properly tested the IRQ code for
 275          * platform functions
 276          */
 277         timeout = jiffies + HZ/10;
 278         while(!time_after(jiffies, timeout)) {
 279                 args.count = 1;
 280                 args.u[0].p = &done;
 281                 pmf_call_one(pfunc_slewing_done, &args);
 282                 if (done)
 283                         break;
 284                 msleep(1);
 285         }
 286         if (done == 0)
 287                 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
 288
 289         /* If frequency is going down, last ramp the voltage */
 290         if (speed_mode > g5_pmode_cur)
 291                 g5_switch_volt(speed_mode);
 292
 293         g5_pmode_cur = speed_mode;
 294         ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
 295
 296         return 0;
 297 }
 298
 299 static int g5_pfunc_query_freq(void)
 300 {
 301         struct pmf_args args;
 302         u32 val = 0;
 303
 304         args.count = 1;
 305         args.u[0].p = &val;
 306         pmf_call_one(pfunc_cpu_getfreq, &args);
 307         return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
 308 }
 309
 310
 311 /*
 312  * Common interface to the cpufreq core
 313  */
 314
 315 static int g5_cpufreq_target(struct cpufreq_policy *policy,
 316         unsigned int target_freq, unsigned int relation)
 317 {
 318         unsigned int newstate = 0;
 319         struct cpufreq_freqs freqs;
 320         int rc;
 321
 322         if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
 323                         target_freq, relation, &newstate))
 324                 return -EINVAL;
 325
 326         if (g5_pmode_cur == newstate)
 327                 return 0;
 328
 329         mutex_lock(&g5_switch_mutex);
 330
 331         freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
 332         freqs.new = g5_cpu_freqs[newstate].frequency;
 333
 334         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 335         rc = g5_switch_freq(newstate);
 336         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 337
 338         mutex_unlock(&g5_switch_mutex);
 339
 340         return rc;
 341 }
 342
 343 static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
 344 {
 345         return g5_cpu_freqs[g5_pmode_cur].frequency;
 346 }
 347
 348 static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
 349 {
 350         policy->cpuinfo.transition_latency = transition_latency;
 351         /* secondary CPUs are tied to the primary one by the
 352          * cpufreq core if in the secondary policy we tell it that
 353          * it actually must be one policy together with all others. */
 354         cpumask_copy(policy->cpus, cpu_online_mask);
 355
 356         return cpufreq_table_validate_and_show(policy, g5_cpu_freqs);
 357 }
 358
 359
 360 static struct cpufreq_driver g5_cpufreq_driver = {
 361         .name           = "powermac",
 362         .flags          = CPUFREQ_CONST_LOOPS,
 363         .init           = g5_cpufreq_cpu_init,
 364         .verify         = cpufreq_generic_frequency_table_verify,
 365         .target         = g5_cpufreq_target,
 366         .get            = g5_cpufreq_get_speed,
 367         .attr           = cpufreq_generic_attr,
 368 };
 369
 370
 371 #ifdef CONFIG_PMAC_SMU
 372
 373 static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
 374 {
 375         unsigned int psize, ssize;
 376         unsigned long max_freq;
 377         char *freq_method, *volt_method;
 378         const u32 *valp;
 379         u32 pvr_hi;
 380         int use_volts_vdnap = 0;
 381         int use_volts_smu = 0;
 382         int rc = -ENODEV;
 383
 384         /* Check supported platforms */
 385         if (of_machine_is_compatible("PowerMac8,1") ||
 386             of_machine_is_compatible("PowerMac8,2") ||
 387             of_machine_is_compatible("PowerMac9,1"))
 388                 use_volts_smu = 1;
 389         else if (of_machine_is_compatible("PowerMac11,2"))
 390                 use_volts_vdnap = 1;
 391         else
 392                 return -ENODEV;
 393
 394         /* Check 970FX for now */
 395         valp = of_get_property(cpunode, "cpu-version", NULL);
 396         if (!valp) {
 397                 DBG("No cpu-version property !\n");
 398                 goto bail_noprops;
 399         }
 400         pvr_hi = (*valp) >> 16;
 401         if (pvr_hi != 0x3c && pvr_hi != 0x44) {
 402                 printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
 403                 goto bail_noprops;
 404         }
 405
 406         /* Look for the powertune data in the device-tree */
 407         g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
 408         if (!g5_pmode_data) {
 409                 DBG("No power-mode-data !\n");
 410                 goto bail_noprops;
 411         }
 412         g5_pmode_max = psize / sizeof(u32) - 1;
 413
 414         if (use_volts_smu) {
 415                 const struct smu_sdbp_header *shdr;
 416
 417                 /* Look for the FVT table */
 418                 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
 419                 if (!shdr)
 420                         goto bail_noprops;
 421                 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
 422                 ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
 423                 g5_fvt_count = ssize / sizeof(*g5_fvt_table);
 424                 g5_fvt_cur = 0;
 425
 426                 /* Sanity checking */
 427                 if (g5_fvt_count < 1 || g5_pmode_max < 1)
 428                         goto bail_noprops;
 429
 430                 g5_switch_volt = g5_smu_switch_volt;
 431                 volt_method = "SMU";
 432         } else if (use_volts_vdnap) {
 433                 struct device_node *root;
 434
 435                 root = of_find_node_by_path("/");
 436                 if (root == NULL) {
 437                         printk(KERN_ERR "cpufreq: Can't find root of "
 438                                "device tree\n");
 439                         goto bail_noprops;
 440                 }
 441                 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
 442                 pfunc_vdnap0_complete =
 443                         pmf_find_function(root, "slewing-done");
 444                 if (pfunc_set_vdnap0 == NULL ||
 445                     pfunc_vdnap0_complete == NULL) {
 446                         printk(KERN_ERR "cpufreq: Can't find required "
 447                                "platform function\n");
 448                         goto bail_noprops;
 449                 }
 450
 451                 g5_switch_volt = g5_vdnap_switch_volt;
 452                 volt_method = "GPIO";
 453         } else {
 454                 g5_switch_volt = g5_dummy_switch_volt;
 455                 volt_method = "none";
 456         }
 457
 458         /*
 459          * From what I see, clock-frequency is always the maximal frequency.
 460          * The current driver can not slew sysclk yet, so we really only deal
 461          * with powertune steps for now. We also only implement full freq and
 462          * half freq in this version. So far, I haven't yet seen a machine
 463          * supporting anything else.
 464          */
 465         valp = of_get_property(cpunode, "clock-frequency", NULL);
 466         if (!valp)
 467                 return -ENODEV;
 468         max_freq = (*valp)/1000;
 469         g5_cpu_freqs[0].frequency = max_freq;
 470         g5_cpu_freqs[1].frequency = max_freq/2;
 471
 472         /* Set callbacks */
 473         transition_latency = 12000;
 474         g5_switch_freq = g5_scom_switch_freq;
 475         g5_query_freq = g5_scom_query_freq;
 476         freq_method = "SCOM";
 477
 478         /* Force apply current frequency to make sure everything is in
 479          * sync (voltage is right for example). Firmware may leave us with
 480          * a strange setting ...
 481          */
 482         g5_switch_volt(CPUFREQ_HIGH);
 483         msleep(10);
 484         g5_pmode_cur = -1;
 485         g5_switch_freq(g5_query_freq());
 486
 487         printk(KERN_INFO "Registering G5 CPU frequency driver\n");
 488         printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
 489                freq_method, volt_method);
 490         printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 491                 g5_cpu_freqs[1].frequency/1000,
 492                 g5_cpu_freqs[0].frequency/1000,
 493                 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 494
 495         rc = cpufreq_register_driver(&g5_cpufreq_driver);
 496
 497         /* We keep the CPU node on hold... hopefully, Apple G5 don't have
 498          * hotplug CPU with a dynamic device-tree ...
 499          */
 500         return rc;
 501
 502  bail_noprops:
 503         of_node_put(cpunode);
 504
 505         return rc;
 506 }
 507
 508 #endif /* CONFIG_PMAC_SMU */
 509
 510
 511 static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
 512 {
 513         struct device_node *cpuid = NULL, *hwclock = NULL;
 514         const u8 *eeprom = NULL;
 515         const u32 *valp;
 516         u64 max_freq, min_freq, ih, il;
 517         int has_volt = 1, rc = 0;
 518
 519         DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
 520             " RackMac3,1...\n");
 521
 522         /* Lookup the cpuid eeprom node */
 523         cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
 524         if (cpuid != NULL)
 525                 eeprom = of_get_property(cpuid, "cpuid", NULL);
 526         if (eeprom == NULL) {
 527                 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
 528                 rc = -ENODEV;
 529                 goto bail;
 530         }
 531
 532         /* Lookup the i2c hwclock */
 533         for (hwclock = NULL;
 534              (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
 535                 const char *loc = of_get_property(hwclock,
 536                                 "hwctrl-location", NULL);
 537                 if (loc == NULL)
 538                         continue;
 539                 if (strcmp(loc, "CPU CLOCK"))
 540                         continue;
 541                 if (!of_get_property(hwclock, "platform-get-frequency", NULL))
 542                         continue;
 543                 break;
 544         }
 545         if (hwclock == NULL) {
 546                 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
 547                 rc = -ENODEV;
 548                 goto bail;
 549         }
 550
 551         DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
 552
 553         /* Now get all the platform functions */
 554         pfunc_cpu_getfreq =
 555                 pmf_find_function(hwclock, "get-frequency");
 556         pfunc_cpu_setfreq_high =
 557                 pmf_find_function(hwclock, "set-frequency-high");
 558         pfunc_cpu_setfreq_low =
 559                 pmf_find_function(hwclock, "set-frequency-low");
 560         pfunc_slewing_done =
 561                 pmf_find_function(hwclock, "slewing-done");
 562         pfunc_cpu0_volt_high =
 563                 pmf_find_function(hwclock, "set-voltage-high-0");
 564         pfunc_cpu0_volt_low =
 565                 pmf_find_function(hwclock, "set-voltage-low-0");
 566         pfunc_cpu1_volt_high =
 567                 pmf_find_function(hwclock, "set-voltage-high-1");
 568         pfunc_cpu1_volt_low =
 569                 pmf_find_function(hwclock, "set-voltage-low-1");
 570
 571         /* Check we have minimum requirements */
 572         if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
 573             pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
 574                 printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
 575                 rc = -ENODEV;
 576                 goto bail;
 577         }
 578
 579         /* Check that we have complete sets */
 580         if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
 581                 pmf_put_function(pfunc_cpu0_volt_high);
 582                 pmf_put_function(pfunc_cpu0_volt_low);
 583                 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
 584                 has_volt = 0;
 585         }
 586         if (!has_volt ||
 587             pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
 588                 pmf_put_function(pfunc_cpu1_volt_high);
 589                 pmf_put_function(pfunc_cpu1_volt_low);
 590                 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
 591         }
 592
 593         /* Note: The device tree also contains a "platform-set-values"
 594          * function for which I haven't quite figured out the usage. It
 595          * might have to be called on init and/or wakeup, I'm not too sure
 596          * but things seem to work fine without it so far ...
 597          */
 598
 599         /* Get max frequency from device-tree */
 600         valp = of_get_property(cpunode, "clock-frequency", NULL);
 601         if (!valp) {
 602                 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
 603                 rc = -ENODEV;
 604                 goto bail;
 605         }
 606
 607         max_freq = (*valp)/1000;
 608
 609         /* Now calculate reduced frequency by using the cpuid input freq
 610          * ratio. This requires 64 bits math unless we are willing to lose
 611          * some precision
 612          */
 613         ih = *((u32 *)(eeprom + 0x10));
 614         il = *((u32 *)(eeprom + 0x20));
 615
 616         /* Check for machines with no useful settings */
 617         if (il == ih) {
 618                 printk(KERN_WARNING "cpufreq: No low frequency mode available"
 619                        " on this model !\n");
 620                 rc = -ENODEV;
 621                 goto bail;
 622         }
 623
 624         min_freq = 0;
 625         if (ih != 0 && il != 0)
 626                 min_freq = (max_freq * il) / ih;
 627
 628         /* Sanity check */
 629         if (min_freq >= max_freq || min_freq < 1000) {
 630                 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
 631                 rc = -ENXIO;
 632                 goto bail;
 633         }
 634         g5_cpu_freqs[0].frequency = max_freq;
 635         g5_cpu_freqs[1].frequency = min_freq;
 636
 637         /* Set callbacks */
 638         transition_latency = CPUFREQ_ETERNAL;
 639         g5_switch_volt = g5_pfunc_switch_volt;
 640         g5_switch_freq = g5_pfunc_switch_freq;
 641         g5_query_freq = g5_pfunc_query_freq;
 642
 643         /* Force apply current frequency to make sure everything is in
 644          * sync (voltage is right for example). Firmware may leave us with
 645          * a strange setting ...
 646          */
 647         g5_switch_volt(CPUFREQ_HIGH);
 648         msleep(10);
 649         g5_pmode_cur = -1;
 650         g5_switch_freq(g5_query_freq());
 651
 652         printk(KERN_INFO "Registering G5 CPU frequency driver\n");
 653         printk(KERN_INFO "Frequency method: i2c/pfunc, "
 654                "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
 655         printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 656                 g5_cpu_freqs[1].frequency/1000,
 657                 g5_cpu_freqs[0].frequency/1000,
 658                 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
 659
 660         rc = cpufreq_register_driver(&g5_cpufreq_driver);
 661  bail:
 662         if (rc != 0) {
 663                 pmf_put_function(pfunc_cpu_getfreq);
 664                 pmf_put_function(pfunc_cpu_setfreq_high);
 665                 pmf_put_function(pfunc_cpu_setfreq_low);
 666                 pmf_put_function(pfunc_slewing_done);
 667                 pmf_put_function(pfunc_cpu0_volt_high);
 668                 pmf_put_function(pfunc_cpu0_volt_low);
 669                 pmf_put_function(pfunc_cpu1_volt_high);
 670                 pmf_put_function(pfunc_cpu1_volt_low);
 671         }
 672         of_node_put(hwclock);
 673         of_node_put(cpuid);
 674         of_node_put(cpunode);
 675
 676         return rc;
 677 }
 678
 679 static int __init g5_cpufreq_init(void)
 680 {
 681         struct device_node *cpunode;
 682         int rc = 0;
 683
 684         /* Get first CPU node */
 685         cpunode = of_cpu_device_node_get(0);
 686         if (cpunode == NULL) {
 687                 pr_err("cpufreq: Can't find any CPU node\n");
 688                 return -ENODEV;
 689         }
 690
 691         if (of_machine_is_compatible("PowerMac7,2") ||
 692             of_machine_is_compatible("PowerMac7,3") ||
 693             of_machine_is_compatible("RackMac3,1"))
 694                 rc = g5_pm72_cpufreq_init(cpunode);
 695 #ifdef CONFIG_PMAC_SMU
 696         else
 697                 rc = g5_neo2_cpufreq_init(cpunode);
 698 #endif /* CONFIG_PMAC_SMU */
 699
 700         return rc;
 701 }
 702
 703 module_init(g5_cpufreq_init);
 704
 705
 706 MODULE_LICENSE("GPL");