Pileus Git - ~andy/linux/blob - drivers/cpufreq/maple-cpufreq.c

   1 /*
   2  *  Copyright (C) 2011 Dmitry Eremin-Solenikov
   3  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
   4  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
  11  * that is iMac G5 and latest single CPU desktop.
  12  */
  13
  14 #undef DEBUG
  15
  16 #include <linux/module.h>
  17 #include <linux/types.h>
  18 #include <linux/errno.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/sched.h>
  22 #include <linux/cpufreq.h>
  23 #include <linux/init.h>
  24 #include <linux/completion.h>
  25 #include <linux/mutex.h>
  26 #include <linux/time.h>
  27 #include <linux/of_device.h>
  28
  29 #define DBG(fmt...) pr_debug(fmt)
  30
  31 /* see 970FX user manual */
  32
  33 #define SCOM_PCR 0x0aa001                       /* PCR scom addr */
  34
  35 #define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
  36 #define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
  37 #define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
  38 #define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
  39 #define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
  40 #define PCR_SPEED_SHIFT         17
  41 #define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
  42 #define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
  43 #define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
  44 #define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
  45 #define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
  46 #define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
  47
  48 #define SCOM_PSR 0x408001                       /* PSR scom addr */
  49 /* warning: PSR is a 64 bits register */
  50 #define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
  51 #define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
  52 #define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
  53 #define PSR_CUR_SPEED_SHIFT     (56)
  54
  55 /*
  56  * The G5 only supports two frequencies (Quarter speed is not supported)
  57  */
  58 #define CPUFREQ_HIGH                  0
  59 #define CPUFREQ_LOW                   1
  60
  61 static struct cpufreq_frequency_table maple_cpu_freqs[] = {
  62         {CPUFREQ_HIGH,          0},
  63         {CPUFREQ_LOW,           0},
  64         {0,                     CPUFREQ_TABLE_END},
  65 };
  66
  67 /* Power mode data is an array of the 32 bits PCR values to use for
  68  * the various frequencies, retrieved from the device-tree
  69  */
  70 static int maple_pmode_cur;
  71
  72 static DEFINE_MUTEX(maple_switch_mutex);
  73
  74 static const u32 *maple_pmode_data;
  75 static int maple_pmode_max;
  76
  77 /*
  78  * SCOM based frequency switching for 970FX rev3
  79  */
  80 static int maple_scom_switch_freq(int speed_mode)
  81 {
  82         unsigned long flags;
  83         int to;
  84
  85         local_irq_save(flags);
  86
  87         /* Clear PCR high */
  88         scom970_write(SCOM_PCR, 0);
  89         /* Clear PCR low */
  90         scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
  91         /* Set PCR low */
  92         scom970_write(SCOM_PCR, PCR_HILO_SELECT |
  93                       maple_pmode_data[speed_mode]);
  94
  95         /* Wait for completion */
  96         for (to = 0; to < 10; to++) {
  97                 unsigned long psr = scom970_read(SCOM_PSR);
  98
  99                 if ((psr & PSR_CMD_RECEIVED) == 0 &&
 100                     (((psr >> PSR_CUR_SPEED_SHIFT) ^
 101                       (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
 102                     == 0)
 103                         break;
 104                 if (psr & PSR_CMD_COMPLETED)
 105                         break;
 106                 udelay(100);
 107         }
 108
 109         local_irq_restore(flags);
 110
 111         maple_pmode_cur = speed_mode;
 112         ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
 113
 114         return 0;
 115 }
 116
 117 static int maple_scom_query_freq(void)
 118 {
 119         unsigned long psr = scom970_read(SCOM_PSR);
 120         int i;
 121
 122         for (i = 0; i <= maple_pmode_max; i++)
 123                 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
 124                       (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
 125                         break;
 126         return i;
 127 }
 128
 129 /*
 130  * Common interface to the cpufreq core
 131  */
 132
 133 static int maple_cpufreq_target(struct cpufreq_policy *policy,
 134         unsigned int target_freq, unsigned int relation)
 135 {
 136         unsigned int newstate = 0;
 137         struct cpufreq_freqs freqs;
 138         int rc;
 139
 140         if (cpufreq_frequency_table_target(policy, maple_cpu_freqs,
 141                         target_freq, relation, &newstate))
 142                 return -EINVAL;
 143
 144         if (maple_pmode_cur == newstate)
 145                 return 0;
 146
 147         mutex_lock(&maple_switch_mutex);
 148
 149         freqs.old = maple_cpu_freqs[maple_pmode_cur].frequency;
 150         freqs.new = maple_cpu_freqs[newstate].frequency;
 151
 152         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
 153         rc = maple_scom_switch_freq(newstate);
 154         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 155
 156         mutex_unlock(&maple_switch_mutex);
 157
 158         return rc;
 159 }
 160
 161 static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
 162 {
 163         return maple_cpu_freqs[maple_pmode_cur].frequency;
 164 }
 165
 166 static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
 167 {
 168         policy->cpuinfo.transition_latency = 12000;
 169         /* secondary CPUs are tied to the primary one by the
 170          * cpufreq core if in the secondary policy we tell it that
 171          * it actually must be one policy together with all others. */
 172         cpumask_setall(policy->cpus);
 173
 174         return cpufreq_table_validate_and_show(policy, maple_cpu_freqs);
 175 }
 176
 177
 178 static struct cpufreq_driver maple_cpufreq_driver = {
 179         .name           = "maple",
 180         .flags          = CPUFREQ_CONST_LOOPS,
 181         .init           = maple_cpufreq_cpu_init,
 182         .verify         = cpufreq_generic_frequency_table_verify,
 183         .target         = maple_cpufreq_target,
 184         .get            = maple_cpufreq_get_speed,
 185         .attr           = cpufreq_generic_attr,
 186 };
 187
 188 static int __init maple_cpufreq_init(void)
 189 {
 190         struct device_node *cpunode;
 191         unsigned int psize;
 192         unsigned long max_freq;
 193         const u32 *valp;
 194         u32 pvr_hi;
 195         int rc = -ENODEV;
 196
 197         /*
 198          * Behave here like powermac driver which checks machine compatibility
 199          * to ease merging of two drivers in future.
 200          */
 201         if (!of_machine_is_compatible("Momentum,Maple") &&
 202             !of_machine_is_compatible("Momentum,Apache"))
 203                 return 0;
 204
 205         /* Get first CPU node */
 206         cpunode = of_cpu_device_node_get(0);
 207         if (cpunode == NULL) {
 208                 printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
 209                 goto bail_noprops;
 210         }
 211
 212         /* Check 970FX for now */
 213         /* we actually don't care on which CPU to access PVR */
 214         pvr_hi = PVR_VER(mfspr(SPRN_PVR));
 215         if (pvr_hi != 0x3c && pvr_hi != 0x44) {
 216                 printk(KERN_ERR "cpufreq: Unsupported CPU version (%x)\n",
 217                                 pvr_hi);
 218                 goto bail_noprops;
 219         }
 220
 221         /* Look for the powertune data in the device-tree */
 222         /*
 223          * On Maple this property is provided by PIBS in dual-processor config,
 224          * not provided by PIBS in CPU0 config and also not provided by SLOF,
 225          * so YMMV
 226          */
 227         maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
 228         if (!maple_pmode_data) {
 229                 DBG("No power-mode-data !\n");
 230                 goto bail_noprops;
 231         }
 232         maple_pmode_max = psize / sizeof(u32) - 1;
 233
 234         /*
 235          * From what I see, clock-frequency is always the maximal frequency.
 236          * The current driver can not slew sysclk yet, so we really only deal
 237          * with powertune steps for now. We also only implement full freq and
 238          * half freq in this version. So far, I haven't yet seen a machine
 239          * supporting anything else.
 240          */
 241         valp = of_get_property(cpunode, "clock-frequency", NULL);
 242         if (!valp)
 243                 return -ENODEV;
 244         max_freq = (*valp)/1000;
 245         maple_cpu_freqs[0].frequency = max_freq;
 246         maple_cpu_freqs[1].frequency = max_freq/2;
 247
 248         /* Force apply current frequency to make sure everything is in
 249          * sync (voltage is right for example). Firmware may leave us with
 250          * a strange setting ...
 251          */
 252         msleep(10);
 253         maple_pmode_cur = -1;
 254         maple_scom_switch_freq(maple_scom_query_freq());
 255
 256         printk(KERN_INFO "Registering Maple CPU frequency driver\n");
 257         printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
 258                 maple_cpu_freqs[1].frequency/1000,
 259                 maple_cpu_freqs[0].frequency/1000,
 260                 maple_cpu_freqs[maple_pmode_cur].frequency/1000);
 261
 262         rc = cpufreq_register_driver(&maple_cpufreq_driver);
 263
 264         of_node_put(cpunode);
 265
 266         return rc;
 267
 268 bail_noprops:
 269         of_node_put(cpunode);
 270
 271         return rc;
 272 }
 273
 274 module_init(maple_cpufreq_init);
 275
 276
 277 MODULE_LICENSE("GPL");