Pileus Git - ~andy/linux/blob - drivers/cpufreq/cpufreq-cpu0.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * The OPP code in function cpu0_set_target() is reused from
   5  * drivers/cpufreq/omap-cpufreq.c
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/clk.h>
  15 #include <linux/cpu.h>
  16 #include <linux/cpufreq.h>
  17 #include <linux/err.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/opp.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24
  25 static unsigned int transition_latency;
  26 static unsigned int voltage_tolerance; /* in percentage */
  27
  28 static struct device *cpu_dev;
  29 static struct clk *cpu_clk;
  30 static struct regulator *cpu_reg;
  31 static struct cpufreq_frequency_table *freq_table;
  32
  33 static unsigned int cpu0_get_speed(unsigned int cpu)
  34 {
  35         return clk_get_rate(cpu_clk) / 1000;
  36 }
  37
  38 static int cpu0_set_target(struct cpufreq_policy *policy,
  39                            unsigned int target_freq, unsigned int relation)
  40 {
  41         struct cpufreq_freqs freqs;
  42         struct opp *opp;
  43         unsigned long volt = 0, volt_old = 0, tol = 0;
  44         long freq_Hz, freq_exact;
  45         unsigned int index;
  46         int ret;
  47
  48         ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
  49                                              relation, &index);
  50         if (ret) {
  51                 pr_err("failed to match target freqency %d: %d\n",
  52                        target_freq, ret);
  53                 return ret;
  54         }
  55
  56         freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
  57         if (freq_Hz < 0)
  58                 freq_Hz = freq_table[index].frequency * 1000;
  59         freq_exact = freq_Hz;
  60         freqs.new = freq_Hz / 1000;
  61         freqs.old = clk_get_rate(cpu_clk) / 1000;
  62
  63         if (freqs.old == freqs.new)
  64                 return 0;
  65
  66         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  67
  68         if (!IS_ERR(cpu_reg)) {
  69                 rcu_read_lock();
  70                 opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
  71                 if (IS_ERR(opp)) {
  72                         rcu_read_unlock();
  73                         pr_err("failed to find OPP for %ld\n", freq_Hz);
  74                         freqs.new = freqs.old;
  75                         ret = PTR_ERR(opp);
  76                         goto post_notify;
  77                 }
  78                 volt = opp_get_voltage(opp);
  79                 rcu_read_unlock();
  80                 tol = volt * voltage_tolerance / 100;
  81                 volt_old = regulator_get_voltage(cpu_reg);
  82         }
  83
  84         pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
  85                  freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
  86                  freqs.new / 1000, volt ? volt / 1000 : -1);
  87
  88         /* scaling up?  scale voltage before frequency */
  89         if (!IS_ERR(cpu_reg) && freqs.new > freqs.old) {
  90                 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
  91                 if (ret) {
  92                         pr_err("failed to scale voltage up: %d\n", ret);
  93                         freqs.new = freqs.old;
  94                         goto post_notify;
  95                 }
  96         }
  97
  98         ret = clk_set_rate(cpu_clk, freq_exact);
  99         if (ret) {
 100                 pr_err("failed to set clock rate: %d\n", ret);
 101                 if (!IS_ERR(cpu_reg))
 102                         regulator_set_voltage_tol(cpu_reg, volt_old, tol);
 103                 freqs.new = freqs.old;
 104                 goto post_notify;
 105         }
 106
 107         /* scaling down?  scale voltage after frequency */
 108         if (!IS_ERR(cpu_reg) && freqs.new < freqs.old) {
 109                 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
 110                 if (ret) {
 111                         pr_err("failed to scale voltage down: %d\n", ret);
 112                         clk_set_rate(cpu_clk, freqs.old * 1000);
 113                         freqs.new = freqs.old;
 114                 }
 115         }
 116
 117 post_notify:
 118         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 119
 120         return ret;
 121 }
 122
 123 static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
 124 {
 125         int ret;
 126
 127         ret = cpufreq_table_validate_and_show(policy, freq_table);
 128         if (ret) {
 129                 pr_err("invalid frequency table: %d\n", ret);
 130                 return ret;
 131         }
 132
 133         policy->cpuinfo.transition_latency = transition_latency;
 134
 135         /*
 136          * The driver only supports the SMP configuartion where all processors
 137          * share the clock and voltage and clock.  Use cpufreq affected_cpus
 138          * interface to have all CPUs scaled together.
 139          */
 140         cpumask_setall(policy->cpus);
 141
 142         return 0;
 143 }
 144
 145 static struct cpufreq_driver cpu0_cpufreq_driver = {
 146         .flags = CPUFREQ_STICKY,
 147         .verify = cpufreq_generic_frequency_table_verify,
 148         .target = cpu0_set_target,
 149         .get = cpu0_get_speed,
 150         .init = cpu0_cpufreq_init,
 151         .exit = cpufreq_generic_exit,
 152         .name = "generic_cpu0",
 153         .attr = cpufreq_generic_attr,
 154 };
 155
 156 static int cpu0_cpufreq_probe(struct platform_device *pdev)
 157 {
 158         struct device_node *np;
 159         int ret;
 160
 161         cpu_dev = get_cpu_device(0);
 162         if (!cpu_dev) {
 163                 pr_err("failed to get cpu0 device\n");
 164                 return -ENODEV;
 165         }
 166
 167         np = of_node_get(cpu_dev->of_node);
 168         if (!np) {
 169                 pr_err("failed to find cpu0 node\n");
 170                 return -ENOENT;
 171         }
 172
 173         cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0");
 174         if (IS_ERR(cpu_reg)) {
 175                 /*
 176                  * If cpu0 regulator supply node is present, but regulator is
 177                  * not yet registered, we should try defering probe.
 178                  */
 179                 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
 180                         dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
 181                         ret = -EPROBE_DEFER;
 182                         goto out_put_node;
 183                 }
 184                 pr_warn("failed to get cpu0 regulator: %ld\n",
 185                         PTR_ERR(cpu_reg));
 186         }
 187
 188         cpu_clk = devm_clk_get(cpu_dev, NULL);
 189         if (IS_ERR(cpu_clk)) {
 190                 ret = PTR_ERR(cpu_clk);
 191                 pr_err("failed to get cpu0 clock: %d\n", ret);
 192                 goto out_put_node;
 193         }
 194
 195         ret = of_init_opp_table(cpu_dev);
 196         if (ret) {
 197                 pr_err("failed to init OPP table: %d\n", ret);
 198                 goto out_put_node;
 199         }
 200
 201         ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
 202         if (ret) {
 203                 pr_err("failed to init cpufreq table: %d\n", ret);
 204                 goto out_put_node;
 205         }
 206
 207         of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
 208
 209         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 210                 transition_latency = CPUFREQ_ETERNAL;
 211
 212         if (cpu_reg) {
 213                 struct opp *opp;
 214                 unsigned long min_uV, max_uV;
 215                 int i;
 216
 217                 /*
 218                  * OPP is maintained in order of increasing frequency, and
 219                  * freq_table initialised from OPP is therefore sorted in the
 220                  * same order.
 221                  */
 222                 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
 223                         ;
 224                 rcu_read_lock();
 225                 opp = opp_find_freq_exact(cpu_dev,
 226                                 freq_table[0].frequency * 1000, true);
 227                 min_uV = opp_get_voltage(opp);
 228                 opp = opp_find_freq_exact(cpu_dev,
 229                                 freq_table[i-1].frequency * 1000, true);
 230                 max_uV = opp_get_voltage(opp);
 231                 rcu_read_unlock();
 232                 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
 233                 if (ret > 0)
 234                         transition_latency += ret * 1000;
 235         }
 236
 237         ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
 238         if (ret) {
 239                 pr_err("failed register driver: %d\n", ret);
 240                 goto out_free_table;
 241         }
 242
 243         of_node_put(np);
 244         return 0;
 245
 246 out_free_table:
 247         opp_free_cpufreq_table(cpu_dev, &freq_table);
 248 out_put_node:
 249         of_node_put(np);
 250         return ret;
 251 }
 252
 253 static int cpu0_cpufreq_remove(struct platform_device *pdev)
 254 {
 255         cpufreq_unregister_driver(&cpu0_cpufreq_driver);
 256         opp_free_cpufreq_table(cpu_dev, &freq_table);
 257
 258         return 0;
 259 }
 260
 261 static struct platform_driver cpu0_cpufreq_platdrv = {
 262         .driver = {
 263                 .name   = "cpufreq-cpu0",
 264                 .owner  = THIS_MODULE,
 265         },
 266         .probe          = cpu0_cpufreq_probe,
 267         .remove         = cpu0_cpufreq_remove,
 268 };
 269 module_platform_driver(cpu0_cpufreq_platdrv);
 270
 271 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 272 MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
 273 MODULE_LICENSE("GPL");