Pileus Git - ~andy/linux/blob - drivers/clocksource/sun4i_timer.c

   1 /*
   2  * Allwinner A1X SoCs timer handling.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * Based on code from
   9  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  10  * Benn Huang <benn@allwinnertech.com>
  11  *
  12  * This file is licensed under the terms of the GNU General Public
  13  * License version 2.  This program is licensed "as is" without any
  14  * warranty of any kind, whether express or implied.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqreturn.h>
  22 #include <linux/sched_clock.h>
  23 #include <linux/of.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #define TIMER_IRQ_EN_REG        0x00
  28 #define TIMER_IRQ_EN(val)               BIT(val)
  29 #define TIMER_IRQ_ST_REG        0x04
  30 #define TIMER_CTL_REG(val)      (0x10 * val + 0x10)
  31 #define TIMER_CTL_ENABLE                BIT(0)
  32 #define TIMER_CTL_RELOAD                BIT(1)
  33 #define TIMER_CTL_ONESHOT               BIT(7)
  34 #define TIMER_INTVAL_REG(val)   (0x10 * (val) + 0x14)
  35 #define TIMER_CNTVAL_REG(val)   (0x10 * (val) + 0x18)
  36
  37 static void __iomem *timer_base;
  38
  39 /*
  40  * When we disable a timer, we need to wait at least for 2 cycles of
  41  * the timer source clock. We will use for that the clocksource timer
  42  * that is already setup and runs at the same frequency than the other
  43  * timers, and we never will be disabled.
  44  */
  45 static void sun4i_clkevt_sync(void)
  46 {
  47         u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
  48
  49         while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
  50                 cpu_relax();
  51 }
  52
  53 static void sun4i_clkevt_time_stop(u8 timer)
  54 {
  55         u32 val = readl(timer_base + TIMER_CTL_REG(timer));
  56         writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
  57         sun4i_clkevt_sync();
  58 }
  59
  60 static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
  61 {
  62         writel(delay, timer_base + TIMER_INTVAL_REG(timer));
  63 }
  64
  65 static void sun4i_clkevt_time_start(u8 timer, bool periodic)
  66 {
  67         u32 val = readl(timer_base + TIMER_CTL_REG(timer));
  68
  69         if (periodic)
  70                 val &= ~TIMER_CTL_ONESHOT;
  71         else
  72                 val |= TIMER_CTL_ONESHOT;
  73
  74         writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
  75 }
  76
  77 static void sun4i_clkevt_mode(enum clock_event_mode mode,
  78                               struct clock_event_device *clk)
  79 {
  80         switch (mode) {
  81         case CLOCK_EVT_MODE_PERIODIC:
  82                 sun4i_clkevt_time_stop(0);
  83                 sun4i_clkevt_time_start(0, true);
  84                 break;
  85         case CLOCK_EVT_MODE_ONESHOT:
  86                 sun4i_clkevt_time_stop(0);
  87                 sun4i_clkevt_time_start(0, false);
  88                 break;
  89         case CLOCK_EVT_MODE_UNUSED:
  90         case CLOCK_EVT_MODE_SHUTDOWN:
  91         default:
  92                 sun4i_clkevt_time_stop(0);
  93                 break;
  94         }
  95 }
  96
  97 static int sun4i_clkevt_next_event(unsigned long evt,
  98                                    struct clock_event_device *unused)
  99 {
 100         sun4i_clkevt_time_stop(0);
 101         sun4i_clkevt_time_setup(0, evt);
 102         sun4i_clkevt_time_start(0, false);
 103
 104         return 0;
 105 }
 106
 107 static struct clock_event_device sun4i_clockevent = {
 108         .name = "sun4i_tick",
 109         .rating = 300,
 110         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 111         .set_mode = sun4i_clkevt_mode,
 112         .set_next_event = sun4i_clkevt_next_event,
 113 };
 114
 115
 116 static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
 117 {
 118         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 119
 120         writel(0x1, timer_base + TIMER_IRQ_ST_REG);
 121         evt->event_handler(evt);
 122
 123         return IRQ_HANDLED;
 124 }
 125
 126 static struct irqaction sun4i_timer_irq = {
 127         .name = "sun4i_timer0",
 128         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 129         .handler = sun4i_timer_interrupt,
 130         .dev_id = &sun4i_clockevent,
 131 };
 132
 133 static u32 sun4i_timer_sched_read(void)
 134 {
 135         return ~readl(timer_base + TIMER_CNTVAL_REG(1));
 136 }
 137
 138 static void __init sun4i_timer_init(struct device_node *node)
 139 {
 140         unsigned long rate = 0;
 141         struct clk *clk;
 142         int ret, irq;
 143         u32 val;
 144
 145         timer_base = of_iomap(node, 0);
 146         if (!timer_base)
 147                 panic("Can't map registers");
 148
 149         irq = irq_of_parse_and_map(node, 0);
 150         if (irq <= 0)
 151                 panic("Can't parse IRQ");
 152
 153         clk = of_clk_get(node, 0);
 154         if (IS_ERR(clk))
 155                 panic("Can't get timer clock");
 156         clk_prepare_enable(clk);
 157
 158         rate = clk_get_rate(clk);
 159
 160         writel(~0, timer_base + TIMER_INTVAL_REG(1));
 161         writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
 162                TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
 163                timer_base + TIMER_CTL_REG(1));
 164
 165         setup_sched_clock(sun4i_timer_sched_read, 32, rate);
 166         clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
 167                               rate, 300, 32, clocksource_mmio_readl_down);
 168
 169         writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0));
 170
 171         /* set clock source to HOSC, 16 pre-division */
 172         val = readl(timer_base + TIMER_CTL_REG(0));
 173         val &= ~(0x07 << 4);
 174         val &= ~(0x03 << 2);
 175         val |= (4 << 4) | (1 << 2);
 176         writel(val, timer_base + TIMER_CTL_REG(0));
 177
 178         /* set mode to auto reload */
 179         val = readl(timer_base + TIMER_CTL_REG(0));
 180         writel(val | TIMER_CTL_RELOAD, timer_base + TIMER_CTL_REG(0));
 181
 182         ret = setup_irq(irq, &sun4i_timer_irq);
 183         if (ret)
 184                 pr_warn("failed to setup irq %d\n", irq);
 185
 186         /* Enable timer0 interrupt */
 187         val = readl(timer_base + TIMER_IRQ_EN_REG);
 188         writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 189
 190         sun4i_clockevent.cpumask = cpumask_of(0);
 191
 192         clockevents_config_and_register(&sun4i_clockevent, rate, 0x1,
 193                                         0xffffffff);
 194 }
 195 CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
 196                        sun4i_timer_init);